GD32F3x0_Firmware_Library: Data Structures

GD32F3x0_Firmware_Library V1.0.0
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Data Structures
Here are the data structures with brief descriptions:
[detail level 12]
C backup_state_struct
C dcd_dev_struct
C dma_parameter_struct
C hcd_dev_struct
C rtc_alarm_struct
C rtc_parameter_struct
C rtc_tamper_struct
C rtc_timestamp_struct
C spi_parameter_struct
C state_table_struct
C timer_break_parameter_struct
C timer_ic_parameter_struct
C timer_oc_parameter_struct
C timer_parameter_struct
C usb_core_cfgs_struct
C usb_core_handle_struct
C usb_descriptor_configuration_struct
C usb_descriptor_device_struct
C usb_descriptor_endpoint_struct
C usb_descriptor_header_struct
C usb_descriptor_interface_struct
C usb_descriptor_language_id_struct
C usb_device_req_struct
C usb_ep_struct
C usb_hostchannel_struct
▼C usb_setup_union
C _setup_packet_struct
C usbd_int_cb_struct
C usbh_ctrl_struct
C usbh_device_struct
C usbh_hcd_int_cb_struct
C usbh_host_struct
C usbh_state_handle_struct
C usbh_state_regist_table_struct
C usbh_state_stack_struct
C usbh_user_callback_struct
Generated on Tue Jun 27 2017 14:36:15 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: backup_state_struct Struct Reference

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Data Fields
backup_state_struct Struct Reference

#include <usbh_core.h>

Data Fields

host_state_enum host_backup_state
enum_state_enum enum_backup_state
ctrl_state_enum ctrl_backup_state
uint8_t | class_req_backup_state
uint8_t | class_backup_state

Detailed Description

Definition at line 178 of file usbh_core.h.

Field Documentation

uint8_t class_backup_state

Definition at line 184 of file usbh_core.h.

uint8_t class_req_backup_state

Definition at line 183 of file usbh_core.h.

ctrl_state_enum ctrl_backup_state

Definition at line 182 of file usbh_core.h.

enum_state_enum enum_backup_state

Definition at line 181 of file usbh_core.h.

host_state_enum host_backup_state

Definition at line 180 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_core.h


GD32F3x0_Firmware_Library: dcd_dev_struct Struct Reference

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Data Fields
dcd_dev_struct Struct Reference

#include <usb_core.h>

Data Fields

uint8_t | config_num
uint8_t | status
uint8_t | ctl_status
uint8_t | prev_status
uint8_t | connection_status
uint32_t | remote_wakeup
uint32_t | remain_len
uint32_t | sum_len
uint32_t | ctl_len
uint8_t | setup_packet [8 *3]
usb_ep_struct in_ep [USB_MAX_DEV_EPCOUNT]
usb_ep_struct out_ep [USB_MAX_DEV_EPCOUNT]
uint8_t * | dev_desc
uint8_t * | config_desc
uint8_t ** | strings
uint8_t(* | class_init )(void *pudev, uint8_t config_index)
uint8_t(* | class_deinit )(void *pudev, uint8_t config_index)
uint8_t(* | class_req_handler )(void *pudev, usb_device_req_struct *req)
uint8_t(* | class_data_handler )(void *pudev, usb_dir_enum rx_tx, uint8_t ep_num)

Detailed Description

Definition at line 124 of file usb_core.h.

Field Documentation

uint8_t(* class_data_handler) (void *pudev, usb_dir_enum rx_tx, uint8_t ep_num)

Definition at line 150 of file usb_core.h.

uint8_t(* class_deinit) (void *pudev, uint8_t config_index)

Definition at line 148 of file usb_core.h.

uint8_t(* class_init) (void *pudev, uint8_t config_index)

Definition at line 147 of file usb_core.h.

uint8_t(* class_req_handler) (void *pudev, usb_device_req_struct *req)

Definition at line 149 of file usb_core.h.

uint8_t* config_desc

Definition at line 143 of file usb_core.h.

uint8_t config_num

Definition at line 126 of file usb_core.h.

uint8_t connection_status

Definition at line 130 of file usb_core.h.

uint32_t ctl_len

Definition at line 136 of file usb_core.h.

uint8_t ctl_status

Definition at line 128 of file usb_core.h.

uint8_t* dev_desc

Definition at line 142 of file usb_core.h.

usb_ep_struct in_ep[USB_MAX_DEV_EPCOUNT]

Definition at line 139 of file usb_core.h.

usb_ep_struct out_ep[USB_MAX_DEV_EPCOUNT]

Definition at line 140 of file usb_core.h.

uint8_t prev_status

Definition at line 129 of file usb_core.h.

uint32_t remain_len

Definition at line 134 of file usb_core.h.

uint32_t remote_wakeup

Definition at line 131 of file usb_core.h.

uint8_t setup_packet[8 *3]

Definition at line 137 of file usb_core.h.

uint8_t status

Definition at line 127 of file usb_core.h.

uint8_t* * strings

Definition at line 144 of file usb_core.h.

uint32_t sum_len

Definition at line 135 of file usb_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_core.h


GD32F3x0_Firmware_Library: dma_parameter_struct Struct Reference

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Data Fields
dma_parameter_struct Struct Reference

#include <gd32f3x0_dma.h>

Data Fields

uint32_t | periph_addr
uint32_t | periph_width
uint8_t | periph_inc
uint32_t | memory_addr
uint32_t | memory_width
uint8_t | memory_inc
uint8_t | direction
uint32_t | number
uint32_t | priority

Detailed Description

Definition at line 102 of file gd32f3x0_dma.h.

Field Documentation

uint8_t direction

channel data transfer direction

Definition at line 110 of file gd32f3x0_dma.h.

uint32_t memory_addr

memory base address

Definition at line 107 of file gd32f3x0_dma.h.

uint8_t memory_inc

memory increasing mode

Definition at line 109 of file gd32f3x0_dma.h.

uint32_t memory_width

transfer data size of memory

Definition at line 108 of file gd32f3x0_dma.h.

uint32_t number

channel transfer number

Definition at line 111 of file gd32f3x0_dma.h.

uint32_t periph_addr

peripheral base address

Definition at line 104 of file gd32f3x0_dma.h.

uint8_t periph_inc

peripheral increasing mode

Definition at line 106 of file gd32f3x0_dma.h.

uint32_t periph_width

transfer data size of peripheral

Definition at line 105 of file gd32f3x0_dma.h.

uint32_t priority

channel priority level

Definition at line 112 of file gd32f3x0_dma.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_dma.h


GD32F3x0_Firmware_Library: hcd_dev_struct Struct Reference

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Data Fields
hcd_dev_struct Struct Reference

#include <usb_core.h>

Data Fields

uint8_t | rx_buffer [RX_MAX_DATA_LENGTH]
uint8_t | connect_status
usb_hostchannel_struct host_channel [USB_MAX_FIFOS]
void(* | vbus_drive )(void *pudev, uint8_t state)

Detailed Description

Definition at line 179 of file usb_core.h.

Field Documentation

uint8_t connect_status

Definition at line 182 of file usb_core.h.

usb_hostchannel_struct host_channel[USB_MAX_FIFOS]

Definition at line 183 of file usb_core.h.

uint8_t rx_buffer[RX_MAX_DATA_LENGTH]

Definition at line 181 of file usb_core.h.

void(* vbus_drive) (void *pudev, uint8_t state)

Definition at line 184 of file usb_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_core.h


GD32F3x0_Firmware_Library: rtc_alarm_struct Struct Reference

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Data Fields
rtc_alarm_struct Struct Reference

#include <gd32f3x0_rtc.h>

Data Fields

uint32_t | rtc_alarm_mask
uint32_t | rtc_weekday_or_date
uint8_t | rtc_alarm_day
uint8_t | rtc_alarm_hour
uint8_t | rtc_alarm_minute
uint8_t | rtc_alarm_second
uint32_t | rtc_am_pm

Detailed Description

Definition at line 202 of file gd32f3x0_rtc.h.

Field Documentation

uint8_t rtc_alarm_day

RTC alarm date or weekday value

Definition at line 206 of file gd32f3x0_rtc.h.

uint8_t rtc_alarm_hour

RTC alarm hour value

Definition at line 207 of file gd32f3x0_rtc.h.

uint32_t rtc_alarm_mask

RTC alarm mask

Definition at line 204 of file gd32f3x0_rtc.h.

uint8_t rtc_alarm_minute

RTC alarm minute value: 0x0 - 0x59(BCD format)

Definition at line 208 of file gd32f3x0_rtc.h.

uint8_t rtc_alarm_second

RTC alarm second value: 0x0 - 0x59(BCD format)

Definition at line 209 of file gd32f3x0_rtc.h.

uint32_t rtc_am_pm

RTC alarm AM/PM value

Definition at line 210 of file gd32f3x0_rtc.h.

uint32_t rtc_weekday_or_date

specify RTC alarm is on date or weekday

Definition at line 205 of file gd32f3x0_rtc.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h


GD32F3x0_Firmware_Library: rtc_parameter_struct Struct Reference

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Data Fields
rtc_parameter_struct Struct Reference

#include <gd32f3x0_rtc.h>

Data Fields

uint8_t | rtc_year
uint8_t | rtc_month
uint8_t | rtc_date
uint8_t | rtc_day_of_week
uint8_t | rtc_hour
uint8_t | rtc_minute
uint8_t | rtc_second
uint16_t | rtc_factor_asyn
uint16_t | rtc_factor_syn
uint32_t | rtc_am_pm
uint32_t | rtc_display_format

Detailed Description

Definition at line 186 of file gd32f3x0_rtc.h.

Field Documentation

uint32_t rtc_am_pm

RTC AM/PM value

Definition at line 197 of file gd32f3x0_rtc.h.

uint8_t rtc_date

RTC date value: 0x1 - 0x31(BCD format)

Definition at line 190 of file gd32f3x0_rtc.h.

uint8_t rtc_day_of_week

RTC weekday value

Definition at line 191 of file gd32f3x0_rtc.h.

uint32_t rtc_display_format

RTC time notation

Definition at line 198 of file gd32f3x0_rtc.h.

uint16_t rtc_factor_asyn

RTC asynchronous prescaler value: 0x0 - 0x7F

Definition at line 195 of file gd32f3x0_rtc.h.

uint16_t rtc_factor_syn

RTC synchronous prescaler value: 0x0 - 0x7FFF

Definition at line 196 of file gd32f3x0_rtc.h.

uint8_t rtc_hour

RTC hour value

Definition at line 192 of file gd32f3x0_rtc.h.

uint8_t rtc_minute

RTC minute value: 0x0 - 0x59(BCD format)

Definition at line 193 of file gd32f3x0_rtc.h.

uint8_t rtc_month

RTC month value

Definition at line 189 of file gd32f3x0_rtc.h.

uint8_t rtc_second

RTC second value: 0x0 - 0x59(BCD format)

Definition at line 194 of file gd32f3x0_rtc.h.

uint8_t rtc_year

RTC year value: 0x0 - 0x99(BCD format)

Definition at line 188 of file gd32f3x0_rtc.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h


GD32F3x0_Firmware_Library: rtc_tamper_struct Struct Reference

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Data Fields
rtc_tamper_struct Struct Reference

#include <gd32f3x0_rtc.h>

Data Fields

uint32_t | rtc_tamper_source
uint32_t | rtc_tamper_trigger
uint32_t | rtc_tamper_filter
uint32_t | rtc_tamper_sample_frequency
ControlStatus | rtc_tamper_precharge_enable
uint32_t | rtc_tamper_precharge_time
ControlStatus | rtc_tamper_with_timestamp

Detailed Description

Definition at line 226 of file gd32f3x0_rtc.h.

Field Documentation

uint32_t rtc_tamper_filter

RTC tamper consecutive samples needed during a voltage level detection

Definition at line 230 of file gd32f3x0_rtc.h.

ControlStatus rtc_tamper_precharge_enable

RTC tamper precharge feature during a voltage level detection

Definition at line 232 of file gd32f3x0_rtc.h.

uint32_t rtc_tamper_precharge_time

RTC tamper precharge duration if precharge feature is enabled

Definition at line 233 of file gd32f3x0_rtc.h.

uint32_t rtc_tamper_sample_frequency

RTC tamper sampling frequency during a voltage level detection

Definition at line 231 of file gd32f3x0_rtc.h.

uint32_t rtc_tamper_source

RTC tamper source

Definition at line 228 of file gd32f3x0_rtc.h.

uint32_t rtc_tamper_trigger

RTC tamper trigger

Definition at line 229 of file gd32f3x0_rtc.h.

ControlStatus rtc_tamper_with_timestamp

RTC tamper time-stamp feature

Definition at line 234 of file gd32f3x0_rtc.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h


GD32F3x0_Firmware_Library: rtc_timestamp_struct Struct Reference

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Data Fields
rtc_timestamp_struct Struct Reference

#include <gd32f3x0_rtc.h>

Data Fields

uint8_t | rtc_timestamp_month
uint8_t | rtc_timestamp_date
uint8_t | rtc_timestamp_day
uint8_t | rtc_timestamp_hour
uint8_t | rtc_timestamp_minute
uint8_t | rtc_timestamp_second
uint32_t | rtc_am_pm

Detailed Description

Definition at line 214 of file gd32f3x0_rtc.h.

Field Documentation

uint32_t rtc_am_pm

RTC time-stamp AM/PM value

Definition at line 222 of file gd32f3x0_rtc.h.

uint8_t rtc_timestamp_date

RTC time-stamp date value: 0x1 - 0x31(BCD format)

Definition at line 217 of file gd32f3x0_rtc.h.

uint8_t rtc_timestamp_day

RTC time-stamp weekday value

Definition at line 218 of file gd32f3x0_rtc.h.

uint8_t rtc_timestamp_hour

RTC time-stamp hour value

Definition at line 219 of file gd32f3x0_rtc.h.

uint8_t rtc_timestamp_minute

RTC time-stamp minute value: 0x0 - 0x59(BCD format)

Definition at line 220 of file gd32f3x0_rtc.h.

uint8_t rtc_timestamp_month

RTC time-stamp month value

Definition at line 216 of file gd32f3x0_rtc.h.

uint8_t rtc_timestamp_second

RTC time-stamp second value: 0x0 - 0x59(BCD format)

Definition at line 221 of file gd32f3x0_rtc.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h


GD32F3x0_Firmware_Library: spi_parameter_struct Struct Reference

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Data Fields
spi_parameter_struct Struct Reference

#include <gd32f3x0_spi.h>

Data Fields

uint32_t | device_mode
uint32_t | trans_mode
uint32_t | frame_size
uint32_t | nss
uint32_t | endian
uint32_t | clock_polarity_phase
uint32_t | prescale

Detailed Description

Definition at line 106 of file gd32f3x0_spi.h.

Field Documentation

uint32_t clock_polarity_phase

SPI clock phase and polarity

Definition at line 113 of file gd32f3x0_spi.h.

uint32_t device_mode

SPI master or slave

Definition at line 108 of file gd32f3x0_spi.h.

uint32_t endian

SPI big endian or little endian

Definition at line 112 of file gd32f3x0_spi.h.

uint32_t frame_size

SPI frame size

Definition at line 110 of file gd32f3x0_spi.h.

uint32_t nss

SPI NSS control by handware or software

Definition at line 111 of file gd32f3x0_spi.h.

uint32_t prescale

SPI prescale factor

Definition at line 114 of file gd32f3x0_spi.h.

uint32_t trans_mode

SPI transtype

Definition at line 109 of file gd32f3x0_spi.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_spi.h


GD32F3x0_Firmware_Library: state_table_struct Struct Reference

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Data Fields
state_table_struct Struct Reference

#include <usbh_core.h>

Data Fields

uint8_t | cur_state
uint8_t | cur_event
uint8_t | next_state
ACT_FUN event_action_fun

Detailed Description

Definition at line 202 of file usbh_core.h.

Field Documentation

uint8_t cur_event

Definition at line 205 of file usbh_core.h.

uint8_t cur_state

Definition at line 204 of file usbh_core.h.

ACT_FUN event_action_fun

Definition at line 207 of file usbh_core.h.

uint8_t next_state

Definition at line 206 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_core.h


GD32F3x0_Firmware_Library: timer_break_parameter_struct Struct Reference

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Data Fields
timer_break_parameter_struct Struct Reference

#include <gd32f3x0_timer.h>

Data Fields

uint16_t | runoffstate
uint32_t | ideloffstate
uint16_t | deadtime
uint16_t | breakpolarity
uint16_t | outputautostate
uint16_t | protectmode
uint16_t | breakstate

Detailed Description

Definition at line 249 of file gd32f3x0_timer.h.

Field Documentation

uint16_t breakpolarity

break polarity

Definition at line 254 of file gd32f3x0_timer.h.

uint16_t breakstate

break enable

Definition at line 257 of file gd32f3x0_timer.h.

uint16_t deadtime

dead time

Definition at line 253 of file gd32f3x0_timer.h.

uint32_t ideloffstate

idle mode off-state

Definition at line 252 of file gd32f3x0_timer.h.

uint16_t outputautostate

output automatic enable

Definition at line 255 of file gd32f3x0_timer.h.

uint16_t protectmode

complementary register protect control

Definition at line 256 of file gd32f3x0_timer.h.

uint16_t runoffstate

run mode off-state

Definition at line 251 of file gd32f3x0_timer.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h


GD32F3x0_Firmware_Library: timer_ic_parameter_struct Struct Reference

  • Data Structures
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Data Fields
timer_ic_parameter_struct Struct Reference

#include <gd32f3x0_timer.h>

Data Fields

uint16_t | icpolarity
uint16_t | icselection
uint16_t | icprescaler
uint16_t | icfilter

Detailed Description

Definition at line 272 of file gd32f3x0_timer.h.

Field Documentation

uint16_t icfilter

channel input capture filter control

Definition at line 277 of file gd32f3x0_timer.h.

uint16_t icpolarity

channel input polarity

Definition at line 274 of file gd32f3x0_timer.h.

uint16_t icprescaler

channel input capture prescaler

Definition at line 276 of file gd32f3x0_timer.h.

uint16_t icselection

channel input mode selection

Definition at line 275 of file gd32f3x0_timer.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h


GD32F3x0_Firmware_Library: timer_oc_parameter_struct Struct Reference

  • Data Structures
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Data Fields
timer_oc_parameter_struct Struct Reference

#include <gd32f3x0_timer.h>

Data Fields

uint32_t | outputstate
uint16_t | outputnstate
uint16_t | ocpolarity
uint16_t | ocnpolarity
uint16_t | ocidlestate
uint16_t | ocnidlestate

Detailed Description

Definition at line 261 of file gd32f3x0_timer.h.

Field Documentation

uint16_t ocidlestate

idle state of channel output

Definition at line 267 of file gd32f3x0_timer.h.

uint16_t ocnidlestate

idle state of channel complementary output

Definition at line 268 of file gd32f3x0_timer.h.

uint16_t ocnpolarity

channel complementary output polarity

Definition at line 266 of file gd32f3x0_timer.h.

uint16_t ocpolarity

channel output polarity

Definition at line 265 of file gd32f3x0_timer.h.

uint16_t outputnstate

channel complementary output state

Definition at line 264 of file gd32f3x0_timer.h.

uint32_t outputstate

channel output state

Definition at line 263 of file gd32f3x0_timer.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h


GD32F3x0_Firmware_Library: timer_parameter_struct Struct Reference

  • Data Structures
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Data Fields
timer_parameter_struct Struct Reference

#include <gd32f3x0_timer.h>

Data Fields

uint16_t | prescaler
uint16_t | alignedmode
uint16_t | counterdirection
uint32_t | period
uint16_t | clockdivision
uint8_t | repetitioncounter

Detailed Description

Definition at line 238 of file gd32f3x0_timer.h.

Field Documentation

uint16_t alignedmode

aligned mode

Definition at line 241 of file gd32f3x0_timer.h.

uint16_t clockdivision

clock division value

Definition at line 244 of file gd32f3x0_timer.h.

uint16_t counterdirection

counter direction

Definition at line 242 of file gd32f3x0_timer.h.

uint32_t period

period value

Definition at line 243 of file gd32f3x0_timer.h.

uint16_t prescaler

prescaler value

Definition at line 240 of file gd32f3x0_timer.h.

uint8_t repetitioncounter

the counter repetition value

Definition at line 245 of file gd32f3x0_timer.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h


GD32F3x0_Firmware_Library: usb_core_cfgs_struct Struct Reference

  • Data Structures
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Data Fields
usb_core_cfgs_struct Struct Reference

#include <usb_core.h>

Data Fields

uint8_t | core_id
uint8_t | core_speed
uint8_t | phy_interface
uint8_t | host_channel_num
uint8_t | dev_endp_num
uint8_t | sof_output
uint8_t | low_power
uint16_t | max_packet_size
uint16_t | max_fifo_size

Detailed Description

Definition at line 59 of file usb_core.h.

Field Documentation

uint8_t core_id

Definition at line 61 of file usb_core.h.

uint8_t core_speed

Definition at line 62 of file usb_core.h.

uint8_t dev_endp_num

Definition at line 65 of file usb_core.h.

uint8_t host_channel_num

Definition at line 64 of file usb_core.h.

uint8_t low_power

Definition at line 67 of file usb_core.h.

uint16_t max_fifo_size

Definition at line 69 of file usb_core.h.

uint16_t max_packet_size

Definition at line 68 of file usb_core.h.

uint8_t phy_interface

Definition at line 63 of file usb_core.h.

uint8_t sof_output

Definition at line 66 of file usb_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_core.h


GD32F3x0_Firmware_Library: usb_core_handle_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_core_handle_struct Struct Reference

#include <usb_core.h>

Data Fields

usb_core_cfgs_struct cfg
void(* | udelay )(const uint32_t usec)
void(* | mdelay )(const uint32_t msec)

Detailed Description

Definition at line 200 of file usb_core.h.

Field Documentation

usb_core_cfgs_struct cfg

Definition at line 202 of file usb_core.h.

void(* mdelay) (const uint32_t msec)

Definition at line 217 of file usb_core.h.

void(* udelay) (const uint32_t usec)

Definition at line 216 of file usb_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_core.h


GD32F3x0_Firmware_Library: usb_descriptor_configuration_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_descriptor_configuration_struct Struct Reference

#include <usb_std.h>

Data Fields

usb_descriptor_header_struct Header
uint16_t | wTotalLength
uint8_t | bNumInterfaces
uint8_t | bConfigurationValue
uint8_t | iConfiguration
uint8_t | bmAttributes
uint8_t | bMaxPower

Detailed Description

Definition at line 145 of file usb_std.h.

Field Documentation

uint8_t bConfigurationValue

configuration index of the current configuration

Definition at line 151 of file usb_std.h.

uint8_t bmAttributes

configuration attributes

Definition at line 153 of file usb_std.h.

uint8_t bMaxPower

maximum power consumption of the device while in the current configuration

Definition at line 154 of file usb_std.h.

uint8_t bNumInterfaces

total number of interfaces in the configuration

Definition at line 150 of file usb_std.h.

usb_descriptor_header_struct Header

descriptor header, including type and size

Definition at line 147 of file usb_std.h.

uint8_t iConfiguration

index of a string descriptor describing the configuration

Definition at line 152 of file usb_std.h.

uint16_t wTotalLength

size of the configuration descriptor header,and all sub descriptors inside the configuration

Definition at line 149 of file usb_std.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_std.h


GD32F3x0_Firmware_Library: usb_descriptor_device_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_descriptor_device_struct Struct Reference

#include <usb_std.h>

Data Fields

usb_descriptor_header_struct Header
uint16_t | bcdUSB
uint8_t | bDeviceClass
uint8_t | bDeviceSubClass
uint8_t | bDeviceProtocol
uint8_t | bMaxPacketSize0
uint16_t | idVendor
uint16_t | idProduct
uint16_t | bcdDevice
uint8_t | iManufacturer
uint8_t | iProduct
uint8_t | iSerialNumber
uint8_t | bNumberConfigurations

Detailed Description

Definition at line 127 of file usb_std.h.

Field Documentation

uint16_t bcdDevice

product release (version) number

Definition at line 138 of file usb_std.h.

uint16_t bcdUSB

BCD of the supported USB specification

Definition at line 131 of file usb_std.h.

uint8_t bDeviceClass

USB device class

Definition at line 132 of file usb_std.h.

uint8_t bDeviceProtocol

USB device protocol

Definition at line 134 of file usb_std.h.

uint8_t bDeviceSubClass

USB device subclass

Definition at line 133 of file usb_std.h.

uint8_t bMaxPacketSize0

size of the control (address 0) endpoint's bank in bytes

Definition at line 135 of file usb_std.h.

uint8_t bNumberConfigurations

total number of configurations supported by the device

Definition at line 142 of file usb_std.h.

usb_descriptor_header_struct Header

descriptor header, including type and size

Definition at line 129 of file usb_std.h.

uint16_t idProduct

unique product ID for the USB product

Definition at line 137 of file usb_std.h.

uint16_t idVendor

vendor ID for the USB product

Definition at line 136 of file usb_std.h.

uint8_t iManufacturer

string index for the manufacturer's name

Definition at line 139 of file usb_std.h.

uint8_t iProduct

string index for the product name/details

Definition at line 140 of file usb_std.h.

uint8_t iSerialNumber

string index for the product's globally unique hexadecimal serial number

Definition at line 141 of file usb_std.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_std.h


GD32F3x0_Firmware_Library: usb_descriptor_endpoint_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_descriptor_endpoint_struct Struct Reference

#include <usb_std.h>

Data Fields

usb_descriptor_header_struct Header
uint8_t | bEndpointAddress
uint8_t | bmAttributes
uint16_t | wMaxPacketSize
uint8_t | bInterval

Detailed Description

Definition at line 170 of file usb_std.h.

Field Documentation

uint8_t bEndpointAddress

logical address of the endpoint

Definition at line 174 of file usb_std.h.

uint8_t bInterval

polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type

Definition at line 177 of file usb_std.h.

uint8_t bmAttributes

endpoint attributes

Definition at line 175 of file usb_std.h.

usb_descriptor_header_struct Header

descriptor header, including type and size.

Definition at line 172 of file usb_std.h.

uint16_t wMaxPacketSize

size of the endpoint bank, in bytes

Definition at line 176 of file usb_std.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_std.h


GD32F3x0_Firmware_Library: usb_descriptor_header_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_descriptor_header_struct Struct Reference

#include <usb_std.h>

Data Fields

uint8_t | bLength
uint8_t | bDescriptorType

Detailed Description

Definition at line 121 of file usb_std.h.

Field Documentation

uint8_t bDescriptorType

type of the descriptor

Definition at line 124 of file usb_std.h.

uint8_t bLength

size of the descriptor

Definition at line 123 of file usb_std.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_std.h


GD32F3x0_Firmware_Library: usb_descriptor_interface_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_descriptor_interface_struct Struct Reference

#include <usb_std.h>

Data Fields

usb_descriptor_header_struct Header
uint8_t | bInterfaceNumber
uint8_t | bAlternateSetting
uint8_t | bNumEndpoints
uint8_t | bInterfaceClass
uint8_t | bInterfaceSubClass
uint8_t | bInterfaceProtocol
uint8_t | iInterface

Detailed Description

Definition at line 157 of file usb_std.h.

Field Documentation

uint8_t bAlternateSetting

alternate setting for the interface number

Definition at line 162 of file usb_std.h.

uint8_t bInterfaceClass

interface class ID

Definition at line 164 of file usb_std.h.

uint8_t bInterfaceNumber

index of the interface in the current configuration

Definition at line 161 of file usb_std.h.

uint8_t bInterfaceProtocol

interface protocol ID

Definition at line 166 of file usb_std.h.

uint8_t bInterfaceSubClass

interface subclass ID

Definition at line 165 of file usb_std.h.

uint8_t bNumEndpoints

total number of endpoints in the interface

Definition at line 163 of file usb_std.h.

usb_descriptor_header_struct Header

descriptor header, including type and size

Definition at line 159 of file usb_std.h.

uint8_t iInterface

index of the string descriptor describing the interface

Definition at line 167 of file usb_std.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_std.h


GD32F3x0_Firmware_Library: usb_descriptor_language_id_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_descriptor_language_id_struct Struct Reference

#include <usb_std.h>

Data Fields

usb_descriptor_header_struct Header
uint16_t wLANGID

Detailed Description

Definition at line 180 of file usb_std.h.

Field Documentation

usb_descriptor_header_struct Header

descriptor header, including type and size.

Definition at line 182 of file usb_std.h.

uint16_t wLANGID

LANGID code

Definition at line 183 of file usb_std.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_std.h


GD32F3x0_Firmware_Library: usb_device_req_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_device_req_struct Struct Reference

#include <usb_core.h>

Data Fields

uint8_t | bmRequestType
uint8_t | bRequest
uint16_t | wValue
uint16_t | wIndex
uint16_t | wLength

Detailed Description

Definition at line 114 of file usb_core.h.

Field Documentation

uint8_t bmRequestType

Definition at line 116 of file usb_core.h.

uint8_t bRequest

Definition at line 117 of file usb_core.h.

uint16_t wIndex

Definition at line 119 of file usb_core.h.

uint16_t wLength

Definition at line 120 of file usb_core.h.

uint16_t wValue

Definition at line 118 of file usb_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_core.h


GD32F3x0_Firmware_Library: usb_ep_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_ep_struct Struct Reference

#include <usb_core.h>

Data Fields

uint8_t | endp_type
uint8_t | endp_frame
uint32_t | endp_mps
uint8_t * | xfer_buff
uint32_t | xfer_len
uint32_t | xfer_count
uint32_t | dma_addr

Detailed Description

Definition at line 99 of file usb_core.h.

Field Documentation

uint32_t dma_addr

Definition at line 110 of file usb_core.h.

uint8_t endp_frame

Definition at line 102 of file usb_core.h.

uint32_t endp_mps

Definition at line 103 of file usb_core.h.

uint8_t endp_type

Definition at line 101 of file usb_core.h.

uint8_t* xfer_buff

Definition at line 106 of file usb_core.h.

uint32_t xfer_count

Definition at line 108 of file usb_core.h.

uint32_t xfer_len

Definition at line 107 of file usb_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_core.h


GD32F3x0_Firmware_Library: usb_hostchannel_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usb_hostchannel_struct Struct Reference

#include <usb_core.h>

Data Fields

uint8_t | dev_addr
uint8_t | dev_speed
uint8_t | DPID
uint8_t | endp_id
uint8_t | endp_in
uint8_t | endp_type
uint16_t | endp_mps
uint16_t | info
uint8_t * | xfer_buff
uint32_t | xfer_len
uint32_t | xfer_count
uint32_t | err_count
hc_status_enum status
urb_state_enum urb_state
uint8_t | data_tg_in
uint8_t | data_tg_out

Detailed Description

Definition at line 154 of file usb_core.h.

Field Documentation

uint8_t data_tg_in

Definition at line 174 of file usb_core.h.

uint8_t data_tg_out

Definition at line 175 of file usb_core.h.

uint8_t dev_addr

Definition at line 156 of file usb_core.h.

uint8_t dev_speed

Definition at line 157 of file usb_core.h.

uint8_t DPID

Definition at line 158 of file usb_core.h.

uint8_t endp_id

Definition at line 159 of file usb_core.h.

uint8_t endp_in

Definition at line 160 of file usb_core.h.

uint16_t endp_mps

Definition at line 162 of file usb_core.h.

uint8_t endp_type

Definition at line 161 of file usb_core.h.

uint32_t err_count

Definition at line 169 of file usb_core.h.

uint16_t info

Definition at line 163 of file usb_core.h.

hc_status_enum status

Definition at line 171 of file usb_core.h.

urb_state_enum urb_state

Definition at line 172 of file usb_core.h.

uint8_t* xfer_buff

Definition at line 165 of file usb_core.h.

uint32_t xfer_count

Definition at line 167 of file usb_core.h.

uint32_t xfer_len

Definition at line 166 of file usb_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_core.h


GD32F3x0_Firmware_Library: usb_setup_union Union Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Structures | Data Fields
usb_setup_union Union Reference

#include <usb_std.h>

Data Structures

struct _setup_packet_struct

Data Fields

uint8_t | data [8]
struct usb_setup_union::_setup_packet_struct | b

Detailed Description

Definition at line 107 of file usb_std.h.

Field Documentation

struct usb_setup_union::_setup_packet_struct b
uint8_t data[8]

Definition at line 109 of file usb_std.h.

The documentation for this union was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_std.h


GD32F3x0_Firmware_Library: usb_setup_union::_setup_packet_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
  • usb_setup_union
  • _setup_packet_struct
Data Fields
usb_setup_union::_setup_packet_struct Struct Reference

#include <usb_std.h>

Data Fields

uint8_t | bmRequestType
uint8_t | bRequest
uint16_t | wValue
uint16_t | wIndex
uint16_t | wLength

Detailed Description

Definition at line 111 of file usb_std.h.

Field Documentation

uint8_t bmRequestType

type of request

Definition at line 113 of file usb_std.h.

uint8_t bRequest

request of setup packet

Definition at line 114 of file usb_std.h.

uint16_t wIndex

index of setup packet

Definition at line 116 of file usb_std.h.

uint16_t wLength

length of setup packet

Definition at line 117 of file usb_std.h.

uint16_t wValue

value of setup packet

Definition at line 115 of file usb_std.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_std.h


GD32F3x0_Firmware_Library: usbd_int_cb_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbd_int_cb_struct Struct Reference

#include <usbd_int.h>

Data Fields

uint8_t(* SOF )(usb_core_handle_struct *pudev)

Detailed Description

Definition at line 17 of file usbd_int.h.

Field Documentation

uint8_t(* SOF) (usb_core_handle_struct *pudev)

Definition at line 19 of file usbd_int.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbd_int.h


GD32F3x0_Firmware_Library: usbh_ctrl_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_ctrl_struct Struct Reference

#include <usbh_core.h>

Data Fields

uint8_t | hc_in_num
uint8_t | hc_out_num
uint8_t | ep0_size
uint8_t | error_count
uint16_t | length
uint16_t | timer
uint8_t * | buff
usb_setup_union setup

Detailed Description

Definition at line 125 of file usbh_core.h.

Field Documentation

uint8_t* buff

Definition at line 133 of file usbh_core.h.

uint8_t ep0_size

Definition at line 129 of file usbh_core.h.

uint8_t error_count

Definition at line 130 of file usbh_core.h.

uint8_t hc_in_num

Definition at line 127 of file usbh_core.h.

uint8_t hc_out_num

Definition at line 128 of file usbh_core.h.

uint16_t length

Definition at line 131 of file usbh_core.h.

usb_setup_union setup

Definition at line 134 of file usbh_core.h.

uint16_t timer

Definition at line 132 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_core.h


GD32F3x0_Firmware_Library: usbh_device_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_device_struct Struct Reference

#include <usbh_core.h>

Data Fields

uint8_t | address
uint8_t | speed
usb_descriptor_device_struct dev_desc
usb_descriptor_configuration_struct cfg_desc
usb_descriptor_interface_struct | itf_desc [USBH_MAX_INTERFACES_NUM]
usb_descriptor_endpoint_struct | ep_desc [USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]

Detailed Description

Definition at line 138 of file usbh_core.h.

Field Documentation

uint8_t address

Definition at line 140 of file usbh_core.h.

usb_descriptor_configuration_struct cfg_desc

Definition at line 143 of file usbh_core.h.

usb_descriptor_device_struct dev_desc

Definition at line 142 of file usbh_core.h.

usb_descriptor_endpoint_struct ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]

Definition at line 145 of file usbh_core.h.

usb_descriptor_interface_struct itf_desc[USBH_MAX_INTERFACES_NUM]

Definition at line 144 of file usbh_core.h.

uint8_t speed

Definition at line 141 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_core.h


GD32F3x0_Firmware_Library: usbh_hcd_int_cb_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_hcd_int_cb_struct Struct Reference

#include <usbh_int.h>

Data Fields

uint8_t(* | sof )(usb_core_handle_struct *pudev)
uint8_t(* | device_connected )(usb_core_handle_struct *pudev)
uint8_t(* | device_disconnected )(usb_core_handle_struct *pudev)

Detailed Description

Definition at line 17 of file usbh_int.h.

Field Documentation

uint8_t(* device_connected) (usb_core_handle_struct *pudev)

Definition at line 20 of file usbh_int.h.

uint8_t(* device_disconnected) (usb_core_handle_struct *pudev)

Definition at line 21 of file usbh_int.h.

uint8_t(* sof) (usb_core_handle_struct *pudev)

Definition at line 19 of file usbh_int.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_int.h


GD32F3x0_Firmware_Library: usbh_host_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_host_struct Struct Reference

#include <usbh_core.h>

Data Fields

backup_state_struct usbh_backup_state
usbh_ctrl_struct control
usbh_device_struct device
usbh_user_callback_struct * usr_cb
usbh_status_enum(* | class_init )(usb_core_handle_struct *pudev, void *phost)
void(* | class_deinit )(usb_core_handle_struct *pudev, void *phost)

Detailed Description

Definition at line 188 of file usbh_core.h.

Field Documentation

void(* class_deinit) (usb_core_handle_struct *pudev, void *phost)

Definition at line 195 of file usbh_core.h.

usbh_status_enum(* class_init) (usb_core_handle_struct *pudev, void *phost)

Definition at line 194 of file usbh_core.h.

usbh_ctrl_struct control

Definition at line 191 of file usbh_core.h.

usbh_device_struct device

Definition at line 192 of file usbh_core.h.

backup_state_struct usbh_backup_state

Definition at line 190 of file usbh_core.h.

usbh_user_callback_struct* usr_cb

Definition at line 193 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_core.h


GD32F3x0_Firmware_Library: usbh_state_handle_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_state_handle_struct Struct Reference

#include <usbh_core.h>

Data Fields

uint8_t | usbh_current_state
uint8_t | usbh_current_state_table_size
state_table_struct * usbh_current_state_table
usbh_state_stack_struct stack [MAX_USBH_STATE_STACK_DEEP]
int8_t | usbh_current_state_stack_top
usbh_state_regist_table_struct usbh_regist_state_table [MAX_USBH_STATE_TABLE_NUM]
uint8_t | usbh_regist_state_table_num

Detailed Description

Definition at line 227 of file usbh_core.h.

Field Documentation

usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]

Definition at line 233 of file usbh_core.h.

uint8_t usbh_current_state

Definition at line 229 of file usbh_core.h.

int8_t usbh_current_state_stack_top

Definition at line 234 of file usbh_core.h.

state_table_struct* usbh_current_state_table

Definition at line 231 of file usbh_core.h.

uint8_t usbh_current_state_table_size

Definition at line 230 of file usbh_core.h.

usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]

Definition at line 236 of file usbh_core.h.

uint8_t usbh_regist_state_table_num

Definition at line 237 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_core.h


GD32F3x0_Firmware_Library: usbh_state_regist_table_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_state_regist_table_struct Struct Reference

#include <usbh_core.h>

Data Fields

uint8_t | id
state_table_struct * table
uint8_t | table_size

Detailed Description

Definition at line 219 of file usbh_core.h.

Field Documentation

uint8_t id

Definition at line 221 of file usbh_core.h.

state_table_struct* table

Definition at line 222 of file usbh_core.h.

uint8_t table_size

Definition at line 223 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_core.h


GD32F3x0_Firmware_Library: usbh_state_stack_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_state_stack_struct Struct Reference

#include <usbh_core.h>

Data Fields

uint8_t | state
state_table_struct * table
uint8_t | table_size

Detailed Description

Definition at line 211 of file usbh_core.h.

Field Documentation

uint8_t state

Definition at line 213 of file usbh_core.h.

state_table_struct* table

Definition at line 214 of file usbh_core.h.

uint8_t table_size

Definition at line 215 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_core.h


GD32F3x0_Firmware_Library: usbh_user_callback_struct Struct Reference

  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
usbh_user_callback_struct Struct Reference

#include <usbh_core.h>

Data Fields

void(* | init )(void)
void(* | deinit )(void)
void(* | device_connected )(void)
void(* | device_reset )(void)
void(* | device_disconnected )(void)
void(* | over_current_detected )(void)
void(* | device_speed_detected )(uint8_t device_speed)
void(* | device_desc_available )(void *devDesc)
void(* | device_address_set )(void)
void(* | configuration_desc_available )(usb_descriptor_configuration_struct *cfg_desc, usb_descriptor_interface_struct *itf_desc, usb_descriptor_endpoint_struct *ep_desc)
void(* | manufacturer_string )(void *mfc_string)
void(* | product_string )(void *prod_string)
void(* | serial_num_string )(void *serial_string)
void(* | enumeration_finish )(void)
usbh_user_status_enum(* | user_input )(void)
int(* | user_application )(usb_core_handle_struct *pudev, uint8_t id)
void(* | device_not_supported )(void)
void(* | unrecovered_error )(void)

Detailed Description

Definition at line 149 of file usbh_core.h.

Field Documentation

void(* configuration_desc_available) (usb_descriptor_configuration_struct *cfg_desc, usb_descriptor_interface_struct *itf_desc, usb_descriptor_endpoint_struct *ep_desc)

Definition at line 161 of file usbh_core.h.

void(* deinit) (void)

Definition at line 152 of file usbh_core.h.

void(* device_address_set) (void)

Definition at line 159 of file usbh_core.h.

void(* device_connected) (void)

Definition at line 153 of file usbh_core.h.

void(* device_desc_available) (void *devDesc)

Definition at line 158 of file usbh_core.h.

void(* device_disconnected) (void)

Definition at line 155 of file usbh_core.h.

void(* device_not_supported) (void)

Definition at line 173 of file usbh_core.h.

void(* device_reset) (void)

Definition at line 154 of file usbh_core.h.

void(* device_speed_detected) (uint8_t device_speed)

Definition at line 157 of file usbh_core.h.

void(* enumeration_finish) (void)

Definition at line 169 of file usbh_core.h.

void(* init) (void)

Definition at line 151 of file usbh_core.h.

void(* manufacturer_string) (void *mfc_string)

Definition at line 166 of file usbh_core.h.

void(* over_current_detected) (void)

Definition at line 156 of file usbh_core.h.

void(* product_string) (void *prod_string)

Definition at line 167 of file usbh_core.h.

void(* serial_num_string) (void *serial_string)

Definition at line 168 of file usbh_core.h.

void(* unrecovered_error) (void)

Definition at line 174 of file usbh_core.h.

int(* user_application) (usb_core_handle_struct *pudev, uint8_t id)

Definition at line 171 of file usbh_core.h.

usbh_user_status_enum(* user_input) (void)

Definition at line 170 of file usbh_core.h.

The documentation for this struct was generated from the following file:
  • E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_core.h


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Data Structure Index
B | D | H | R | S | T | U | _
_
r
timer_ic_parameter_struct usb_descriptor_interface_struct usbh_state_handle_struct
timer_oc_parameter_struct usb_descriptor_language_id_struct usbh_state_regist_table_struct
usb_setup_union::_setup_packet_struct rtc_alarm_struct timer_parameter_struct usb_device_req_struct usbh_state_stack_struct
b
rtc_parameter_struct
u
usb_ep_struct usbh_user_callback_struct
rtc_tamper_struct usb_hostchannel_struct
backup_state_struct rtc_timestamp_struct usb_core_cfgs_struct usb_setup_union
d
s
usb_core_handle_struct usbd_int_cb_struct
usb_descriptor_configuration_struct usbh_ctrl_struct
dcd_dev_struct spi_parameter_struct usb_descriptor_device_struct usbh_device_struct
dma_parameter_struct state_table_struct usb_descriptor_endpoint_struct usbh_hcd_int_cb_struct
h
t
usb_descriptor_header_struct usbh_host_struct
hcd_dev_struct timer_break_parameter_struct
B | D | H | R | S | T | U | _


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  • address : usbh_device_struct
  • alignedmode : timer_parameter_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • b : usb_setup_union
  • bAlternateSetting : usb_descriptor_interface_struct
  • bcdDevice : usb_descriptor_device_struct
  • bcdUSB : usb_descriptor_device_struct
  • bConfigurationValue : usb_descriptor_configuration_struct
  • bDescriptorType : usb_descriptor_header_struct
  • bDeviceClass : usb_descriptor_device_struct
  • bDeviceProtocol : usb_descriptor_device_struct
  • bDeviceSubClass : usb_descriptor_device_struct
  • bEndpointAddress : usb_descriptor_endpoint_struct
  • bInterfaceClass : usb_descriptor_interface_struct
  • bInterfaceNumber : usb_descriptor_interface_struct
  • bInterfaceProtocol : usb_descriptor_interface_struct
  • bInterfaceSubClass : usb_descriptor_interface_struct
  • bInterval : usb_descriptor_endpoint_struct
  • bLength : usb_descriptor_header_struct
  • bmAttributes : usb_descriptor_configuration_struct , usb_descriptor_endpoint_struct
  • bMaxPacketSize0 : usb_descriptor_device_struct
  • bMaxPower : usb_descriptor_configuration_struct
  • bmRequestType : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • bNumberConfigurations : usb_descriptor_device_struct
  • bNumEndpoints : usb_descriptor_interface_struct
  • bNumInterfaces : usb_descriptor_configuration_struct
  • breakpolarity : timer_break_parameter_struct
  • breakstate : timer_break_parameter_struct
  • bRequest : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • buff : usbh_ctrl_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • cfg : usb_core_handle_struct
  • cfg_desc : usbh_device_struct
  • class_backup_state : backup_state_struct
  • class_data_handler : dcd_dev_struct
  • class_deinit : dcd_dev_struct , usbh_host_struct
  • class_init : dcd_dev_struct , usbh_host_struct
  • class_req_backup_state : backup_state_struct
  • class_req_handler : dcd_dev_struct
  • clock_polarity_phase : spi_parameter_struct
  • clockdivision : timer_parameter_struct
  • config_desc : dcd_dev_struct
  • config_num : dcd_dev_struct
  • configuration_desc_available : usbh_user_callback_struct
  • connect_status : hcd_dev_struct
  • connection_status : dcd_dev_struct
  • control : usbh_host_struct
  • core_id : usb_core_cfgs_struct
  • core_speed : usb_core_cfgs_struct
  • counterdirection : timer_parameter_struct
  • ctl_len : dcd_dev_struct
  • ctl_status : dcd_dev_struct
  • ctrl_backup_state : backup_state_struct
  • cur_event : state_table_struct
  • cur_state : state_table_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • data : usb_setup_union
  • data_tg_in : usb_hostchannel_struct
  • data_tg_out : usb_hostchannel_struct
  • deadtime : timer_break_parameter_struct
  • deinit : usbh_user_callback_struct
  • dev_addr : usb_hostchannel_struct
  • dev_desc : dcd_dev_struct , usbh_device_struct
  • dev_endp_num : usb_core_cfgs_struct
  • dev_speed : usb_hostchannel_struct
  • device : usbh_host_struct
  • device_address_set : usbh_user_callback_struct
  • device_connected : usbh_hcd_int_cb_struct , usbh_user_callback_struct
  • device_desc_available : usbh_user_callback_struct
  • device_disconnected : usbh_hcd_int_cb_struct , usbh_user_callback_struct
  • device_mode : spi_parameter_struct
  • device_not_supported : usbh_user_callback_struct
  • device_reset : usbh_user_callback_struct
  • device_speed_detected : usbh_user_callback_struct
  • direction : dma_parameter_struct
  • dma_addr : usb_ep_struct
  • DPID : usb_hostchannel_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • endian : spi_parameter_struct
  • endp_frame : usb_ep_struct
  • endp_id : usb_hostchannel_struct
  • endp_in : usb_hostchannel_struct
  • endp_mps : usb_ep_struct , usb_hostchannel_struct
  • endp_type : usb_ep_struct , usb_hostchannel_struct
  • enum_backup_state : backup_state_struct
  • enumeration_finish : usbh_user_callback_struct
  • ep0_size : usbh_ctrl_struct
  • ep_desc : usbh_device_struct
  • err_count : usb_hostchannel_struct
  • error_count : usbh_ctrl_struct
  • event_action_fun : state_table_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • frame_size : spi_parameter_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • hc_in_num : usbh_ctrl_struct
  • hc_out_num : usbh_ctrl_struct
  • Header : usb_descriptor_configuration_struct , usb_descriptor_device_struct , usb_descriptor_endpoint_struct , usb_descriptor_interface_struct , usb_descriptor_language_id_struct
  • host_backup_state : backup_state_struct
  • host_channel : hcd_dev_struct
  • host_channel_num : usb_core_cfgs_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • icfilter : timer_ic_parameter_struct
  • iConfiguration : usb_descriptor_configuration_struct
  • icpolarity : timer_ic_parameter_struct
  • icprescaler : timer_ic_parameter_struct
  • icselection : timer_ic_parameter_struct
  • id : usbh_state_regist_table_struct
  • ideloffstate : timer_break_parameter_struct
  • idProduct : usb_descriptor_device_struct
  • idVendor : usb_descriptor_device_struct
  • iInterface : usb_descriptor_interface_struct
  • iManufacturer : usb_descriptor_device_struct
  • in_ep : dcd_dev_struct
  • info : usb_hostchannel_struct
  • init : usbh_user_callback_struct
  • iProduct : usb_descriptor_device_struct
  • iSerialNumber : usb_descriptor_device_struct
  • itf_desc : usbh_device_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • length : usbh_ctrl_struct
  • low_power : usb_core_cfgs_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • manufacturer_string : usbh_user_callback_struct
  • max_fifo_size : usb_core_cfgs_struct
  • max_packet_size : usb_core_cfgs_struct
  • mdelay : usb_core_handle_struct
  • memory_addr : dma_parameter_struct
  • memory_inc : dma_parameter_struct
  • memory_width : dma_parameter_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • next_state : state_table_struct
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • ocidlestate : timer_oc_parameter_struct
  • ocnidlestate : timer_oc_parameter_struct
  • ocnpolarity : timer_oc_parameter_struct
  • ocpolarity : timer_oc_parameter_struct
  • out_ep : dcd_dev_struct
  • outputautostate : timer_break_parameter_struct
  • outputnstate : timer_oc_parameter_struct
  • outputstate : timer_oc_parameter_struct
  • over_current_detected : usbh_user_callback_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • period : timer_parameter_struct
  • periph_addr : dma_parameter_struct
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  • periph_width : dma_parameter_struct
  • phy_interface : usb_core_cfgs_struct
  • prescale : spi_parameter_struct
  • prescaler : timer_parameter_struct
  • prev_status : dcd_dev_struct
  • priority : dma_parameter_struct
  • product_string : usbh_user_callback_struct
  • protectmode : timer_break_parameter_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • remain_len : dcd_dev_struct
  • remote_wakeup : dcd_dev_struct
  • repetitioncounter : timer_parameter_struct
  • rtc_alarm_day : rtc_alarm_struct
  • rtc_alarm_hour : rtc_alarm_struct
  • rtc_alarm_mask : rtc_alarm_struct
  • rtc_alarm_minute : rtc_alarm_struct
  • rtc_alarm_second : rtc_alarm_struct
  • rtc_am_pm : rtc_alarm_struct , rtc_parameter_struct , rtc_timestamp_struct
  • rtc_date : rtc_parameter_struct
  • rtc_day_of_week : rtc_parameter_struct
  • rtc_display_format : rtc_parameter_struct
  • rtc_factor_asyn : rtc_parameter_struct
  • rtc_factor_syn : rtc_parameter_struct
  • rtc_hour : rtc_parameter_struct
  • rtc_minute : rtc_parameter_struct
  • rtc_month : rtc_parameter_struct
  • rtc_second : rtc_parameter_struct
  • rtc_tamper_filter : rtc_tamper_struct
  • rtc_tamper_precharge_enable : rtc_tamper_struct
  • rtc_tamper_precharge_time : rtc_tamper_struct
  • rtc_tamper_sample_frequency : rtc_tamper_struct
  • rtc_tamper_source : rtc_tamper_struct
  • rtc_tamper_trigger : rtc_tamper_struct
  • rtc_tamper_with_timestamp : rtc_tamper_struct
  • rtc_timestamp_date : rtc_timestamp_struct
  • rtc_timestamp_day : rtc_timestamp_struct
  • rtc_timestamp_hour : rtc_timestamp_struct
  • rtc_timestamp_minute : rtc_timestamp_struct
  • rtc_timestamp_month : rtc_timestamp_struct
  • rtc_timestamp_second : rtc_timestamp_struct
  • rtc_weekday_or_date : rtc_alarm_struct
  • rtc_year : rtc_parameter_struct
  • runoffstate : timer_break_parameter_struct
  • rx_buffer : hcd_dev_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • serial_num_string : usbh_user_callback_struct
  • setup : usbh_ctrl_struct
  • setup_packet : dcd_dev_struct
  • SOF : usbd_int_cb_struct
  • sof : usbh_hcd_int_cb_struct
  • sof_output : usb_core_cfgs_struct
  • speed : usbh_device_struct
  • stack : usbh_state_handle_struct
  • state : usbh_state_stack_struct
  • status : dcd_dev_struct , usb_hostchannel_struct
  • strings : dcd_dev_struct
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • table : usbh_state_regist_table_struct , usbh_state_stack_struct
  • table_size : usbh_state_regist_table_struct , usbh_state_stack_struct
  • timer : usbh_ctrl_struct
  • trans_mode : spi_parameter_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • udelay : usb_core_handle_struct
  • unrecovered_error : usbh_user_callback_struct
  • urb_state : usb_hostchannel_struct
  • usbh_backup_state : usbh_host_struct
  • usbh_current_state : usbh_state_handle_struct
  • usbh_current_state_stack_top : usbh_state_handle_struct
  • usbh_current_state_table : usbh_state_handle_struct
  • usbh_current_state_table_size : usbh_state_handle_struct
  • usbh_regist_state_table : usbh_state_handle_struct
  • usbh_regist_state_table_num : usbh_state_handle_struct
  • user_application : usbh_user_callback_struct
  • user_input : usbh_user_callback_struct
  • usr_cb : usbh_host_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • vbus_drive : hcd_dev_struct


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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • wIndex : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • wLANGID : usb_descriptor_language_id_struct
  • wLength : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • wMaxPacketSize : usb_descriptor_endpoint_struct
  • wTotalLength : usb_descriptor_configuration_struct
  • wValue : usb_device_req_struct , usb_setup_union::_setup_packet_struct


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  • x
Here is a list of all struct and union fields with links to the structures/unions they belong to:

- x -

  • xfer_buff : usb_ep_struct , usb_hostchannel_struct
  • xfer_count : usb_ep_struct , usb_hostchannel_struct
  • xfer_len : usb_ep_struct , usb_hostchannel_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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  • a
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- a -

  • address : usbh_device_struct
  • alignedmode : timer_parameter_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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  • a
  • b
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- b -

  • b : usb_setup_union
  • bAlternateSetting : usb_descriptor_interface_struct
  • bcdDevice : usb_descriptor_device_struct
  • bcdUSB : usb_descriptor_device_struct
  • bConfigurationValue : usb_descriptor_configuration_struct
  • bDescriptorType : usb_descriptor_header_struct
  • bDeviceClass : usb_descriptor_device_struct
  • bDeviceProtocol : usb_descriptor_device_struct
  • bDeviceSubClass : usb_descriptor_device_struct
  • bEndpointAddress : usb_descriptor_endpoint_struct
  • bInterfaceClass : usb_descriptor_interface_struct
  • bInterfaceNumber : usb_descriptor_interface_struct
  • bInterfaceProtocol : usb_descriptor_interface_struct
  • bInterfaceSubClass : usb_descriptor_interface_struct
  • bInterval : usb_descriptor_endpoint_struct
  • bLength : usb_descriptor_header_struct
  • bmAttributes : usb_descriptor_configuration_struct , usb_descriptor_endpoint_struct
  • bMaxPacketSize0 : usb_descriptor_device_struct
  • bMaxPower : usb_descriptor_configuration_struct
  • bmRequestType : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • bNumberConfigurations : usb_descriptor_device_struct
  • bNumEndpoints : usb_descriptor_interface_struct
  • bNumInterfaces : usb_descriptor_configuration_struct
  • breakpolarity : timer_break_parameter_struct
  • breakstate : timer_break_parameter_struct
  • bRequest : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • buff : usbh_ctrl_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- c -

  • cfg : usb_core_handle_struct
  • cfg_desc : usbh_device_struct
  • class_backup_state : backup_state_struct
  • class_data_handler : dcd_dev_struct
  • class_deinit : dcd_dev_struct , usbh_host_struct
  • class_init : dcd_dev_struct , usbh_host_struct
  • class_req_backup_state : backup_state_struct
  • class_req_handler : dcd_dev_struct
  • clock_polarity_phase : spi_parameter_struct
  • clockdivision : timer_parameter_struct
  • config_desc : dcd_dev_struct
  • config_num : dcd_dev_struct
  • configuration_desc_available : usbh_user_callback_struct
  • connect_status : hcd_dev_struct
  • connection_status : dcd_dev_struct
  • control : usbh_host_struct
  • core_id : usb_core_cfgs_struct
  • core_speed : usb_core_cfgs_struct
  • counterdirection : timer_parameter_struct
  • ctl_len : dcd_dev_struct
  • ctl_status : dcd_dev_struct
  • ctrl_backup_state : backup_state_struct
  • cur_event : state_table_struct
  • cur_state : state_table_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
  • a
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- d -

  • data : usb_setup_union
  • data_tg_in : usb_hostchannel_struct
  • data_tg_out : usb_hostchannel_struct
  • deadtime : timer_break_parameter_struct
  • deinit : usbh_user_callback_struct
  • dev_addr : usb_hostchannel_struct
  • dev_desc : dcd_dev_struct , usbh_device_struct
  • dev_endp_num : usb_core_cfgs_struct
  • dev_speed : usb_hostchannel_struct
  • device : usbh_host_struct
  • device_address_set : usbh_user_callback_struct
  • device_connected : usbh_hcd_int_cb_struct , usbh_user_callback_struct
  • device_desc_available : usbh_user_callback_struct
  • device_disconnected : usbh_hcd_int_cb_struct , usbh_user_callback_struct
  • device_mode : spi_parameter_struct
  • device_not_supported : usbh_user_callback_struct
  • device_reset : usbh_user_callback_struct
  • device_speed_detected : usbh_user_callback_struct
  • direction : dma_parameter_struct
  • dma_addr : usb_ep_struct
  • DPID : usb_hostchannel_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
  • a
  • b
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- e -

  • endian : spi_parameter_struct
  • endp_frame : usb_ep_struct
  • endp_id : usb_hostchannel_struct
  • endp_in : usb_hostchannel_struct
  • endp_mps : usb_ep_struct , usb_hostchannel_struct
  • endp_type : usb_ep_struct , usb_hostchannel_struct
  • enum_backup_state : backup_state_struct
  • enumeration_finish : usbh_user_callback_struct
  • ep0_size : usbh_ctrl_struct
  • ep_desc : usbh_device_struct
  • err_count : usb_hostchannel_struct
  • error_count : usbh_ctrl_struct
  • event_action_fun : state_table_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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- f -

  • frame_size : spi_parameter_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
  • a
  • b
  • c
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- h -

  • hc_in_num : usbh_ctrl_struct
  • hc_out_num : usbh_ctrl_struct
  • Header : usb_descriptor_configuration_struct , usb_descriptor_device_struct , usb_descriptor_endpoint_struct , usb_descriptor_interface_struct , usb_descriptor_language_id_struct
  • host_backup_state : backup_state_struct
  • host_channel : hcd_dev_struct
  • host_channel_num : usb_core_cfgs_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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  • a
  • b
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- i -

  • icfilter : timer_ic_parameter_struct
  • iConfiguration : usb_descriptor_configuration_struct
  • icpolarity : timer_ic_parameter_struct
  • icprescaler : timer_ic_parameter_struct
  • icselection : timer_ic_parameter_struct
  • id : usbh_state_regist_table_struct
  • ideloffstate : timer_break_parameter_struct
  • idProduct : usb_descriptor_device_struct
  • idVendor : usb_descriptor_device_struct
  • iInterface : usb_descriptor_interface_struct
  • iManufacturer : usb_descriptor_device_struct
  • in_ep : dcd_dev_struct
  • info : usb_hostchannel_struct
  • init : usbh_user_callback_struct
  • iProduct : usb_descriptor_device_struct
  • iSerialNumber : usb_descriptor_device_struct
  • itf_desc : usbh_device_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- l -

  • length : usbh_ctrl_struct
  • low_power : usb_core_cfgs_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • Variables
  • a
  • b
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- m -

  • manufacturer_string : usbh_user_callback_struct
  • max_fifo_size : usb_core_cfgs_struct
  • max_packet_size : usb_core_cfgs_struct
  • mdelay : usb_core_handle_struct
  • memory_addr : dma_parameter_struct
  • memory_inc : dma_parameter_struct
  • memory_width : dma_parameter_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • a
  • b
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- n -

  • next_state : state_table_struct
  • nss : spi_parameter_struct
  • number : dma_parameter_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • a
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- o -

  • ocidlestate : timer_oc_parameter_struct
  • ocnidlestate : timer_oc_parameter_struct
  • ocnpolarity : timer_oc_parameter_struct
  • ocpolarity : timer_oc_parameter_struct
  • out_ep : dcd_dev_struct
  • outputautostate : timer_break_parameter_struct
  • outputnstate : timer_oc_parameter_struct
  • outputstate : timer_oc_parameter_struct
  • over_current_detected : usbh_user_callback_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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- p -

  • period : timer_parameter_struct
  • periph_addr : dma_parameter_struct
  • periph_inc : dma_parameter_struct
  • periph_width : dma_parameter_struct
  • phy_interface : usb_core_cfgs_struct
  • prescale : spi_parameter_struct
  • prescaler : timer_parameter_struct
  • prev_status : dcd_dev_struct
  • priority : dma_parameter_struct
  • product_string : usbh_user_callback_struct
  • protectmode : timer_break_parameter_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • a
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- r -

  • remain_len : dcd_dev_struct
  • remote_wakeup : dcd_dev_struct
  • repetitioncounter : timer_parameter_struct
  • rtc_alarm_day : rtc_alarm_struct
  • rtc_alarm_hour : rtc_alarm_struct
  • rtc_alarm_mask : rtc_alarm_struct
  • rtc_alarm_minute : rtc_alarm_struct
  • rtc_alarm_second : rtc_alarm_struct
  • rtc_am_pm : rtc_alarm_struct , rtc_parameter_struct , rtc_timestamp_struct
  • rtc_date : rtc_parameter_struct
  • rtc_day_of_week : rtc_parameter_struct
  • rtc_display_format : rtc_parameter_struct
  • rtc_factor_asyn : rtc_parameter_struct
  • rtc_factor_syn : rtc_parameter_struct
  • rtc_hour : rtc_parameter_struct
  • rtc_minute : rtc_parameter_struct
  • rtc_month : rtc_parameter_struct
  • rtc_second : rtc_parameter_struct
  • rtc_tamper_filter : rtc_tamper_struct
  • rtc_tamper_precharge_enable : rtc_tamper_struct
  • rtc_tamper_precharge_time : rtc_tamper_struct
  • rtc_tamper_sample_frequency : rtc_tamper_struct
  • rtc_tamper_source : rtc_tamper_struct
  • rtc_tamper_trigger : rtc_tamper_struct
  • rtc_tamper_with_timestamp : rtc_tamper_struct
  • rtc_timestamp_date : rtc_timestamp_struct
  • rtc_timestamp_day : rtc_timestamp_struct
  • rtc_timestamp_hour : rtc_timestamp_struct
  • rtc_timestamp_minute : rtc_timestamp_struct
  • rtc_timestamp_month : rtc_timestamp_struct
  • rtc_timestamp_second : rtc_timestamp_struct
  • rtc_weekday_or_date : rtc_alarm_struct
  • rtc_year : rtc_parameter_struct
  • runoffstate : timer_break_parameter_struct
  • rx_buffer : hcd_dev_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
  • Data Fields
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  • a
  • b
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- s -

  • serial_num_string : usbh_user_callback_struct
  • setup : usbh_ctrl_struct
  • setup_packet : dcd_dev_struct
  • SOF : usbd_int_cb_struct
  • sof : usbh_hcd_int_cb_struct
  • sof_output : usb_core_cfgs_struct
  • speed : usbh_device_struct
  • stack : usbh_state_handle_struct
  • state : usbh_state_stack_struct
  • status : dcd_dev_struct , usb_hostchannel_struct
  • strings : dcd_dev_struct
  • sum_len : dcd_dev_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
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  • a
  • b
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- t -

  • table : usbh_state_regist_table_struct , usbh_state_stack_struct
  • table_size : usbh_state_regist_table_struct , usbh_state_stack_struct
  • timer : usbh_ctrl_struct
  • trans_mode : spi_parameter_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

  • Data Structures
  • Data Structure Index
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  • a
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- u -

  • udelay : usb_core_handle_struct
  • unrecovered_error : usbh_user_callback_struct
  • urb_state : usb_hostchannel_struct
  • usbh_backup_state : usbh_host_struct
  • usbh_current_state : usbh_state_handle_struct
  • usbh_current_state_stack_top : usbh_state_handle_struct
  • usbh_current_state_table : usbh_state_handle_struct
  • usbh_current_state_table_size : usbh_state_handle_struct
  • usbh_regist_state_table : usbh_state_handle_struct
  • usbh_regist_state_table_num : usbh_state_handle_struct
  • user_application : usbh_user_callback_struct
  • user_input : usbh_user_callback_struct
  • usr_cb : usbh_host_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

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- v -

  • vbus_drive : hcd_dev_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

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- w -

  • wIndex : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • wLANGID : usb_descriptor_language_id_struct
  • wLength : usb_device_req_struct , usb_setup_union::_setup_packet_struct
  • wMaxPacketSize : usb_descriptor_endpoint_struct
  • wTotalLength : usb_descriptor_configuration_struct
  • wValue : usb_device_req_struct , usb_setup_union::_setup_packet_struct


GD32F3x0_Firmware_Library: Data Fields - Variables

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- x -

  • xfer_buff : usb_ep_struct , usb_hostchannel_struct
  • xfer_count : usb_ep_struct , usb_hostchannel_struct
  • xfer_len : usb_ep_struct , usb_hostchannel_struct


GD32F3x0_Firmware_Library: File List

  • File List
  • Globals
File List
Here is a list of all files with brief descriptions:
[detail level 123456]
▼ E: |
▼ GD32F3x0_Firmware_Library |
▼ Firmware |
▼ GD32F3x0_standard_peripheral |
▼ Include |
gd32f3x0_adc.h | Definitions for the ADC
gd32f3x0_cec.h | Definitions for the CEC
gd32f3x0_cmp.h | Definitions for the CMP
gd32f3x0_crc.h | Definitions for the CRC
gd32f3x0_ctc.h | Definitions for the CTC
gd32f3x0_dac.h | Definitions for the DAC
gd32f3x0_dbg.h | Definitions for the DBG
gd32f3x0_dma.h | Definitions for the DMA
gd32f3x0_exti.h | Definitions for the EXTI
gd32f3x0_fmc.h | Definitions for the FMC
gd32f3x0_fwdgt.h | Definitions for the FWDGT
gd32f3x0_gpio.h | Definitions for the GPIO
gd32f3x0_i2c.h | Definitions for the I2C
gd32f3x0_misc.h | Definitions for the MISC
gd32f3x0_pmu.h | Definitions for the PMU
gd32f3x0_rcu.h | Definitions for the RCU
gd32f3x0_rtc.h | Definitions for the RTC
gd32f3x0_spi.h | Definitions for the SPI
gd32f3x0_syscfg.h | Definitions for the SYSCFG
gd32f3x0_timer.h | Definitions for the TIMER
gd32f3x0_tsi.h | Definitions for the TSI
gd32f3x0_usart.h | Definitions for the USART
gd32f3x0_wwdgt.h | Definitions for the WWDGT
▼ Source |
gd32f3x0_adc.c | ADC driver
gd32f3x0_cec.c | CEC driver
gd32f3x0_cmp.c | CMP driver
gd32f3x0_crc.c | CRC driver
gd32f3x0_ctc.c | CTC driver
gd32f3x0_dac.c | DAC driver
gd32f3x0_dbg.c | DBG driver
gd32f3x0_dma.c | DMA driver
gd32f3x0_exti.c | EXTI driver
gd32f3x0_fmc.c | FMC driver
gd32f3x0_fwdgt.c | FWDGT driver
gd32f3x0_gpio.c | GPIO driver
gd32f3x0_i2c.c | I2C driver
gd32f3x0_misc.c | MISC driver
gd32f3x0_pmu.c | PMU driver
gd32f3x0_rcu.c | RCU driver
gd32f3x0_rtc.c | RTC driver
gd32f3x0_spi.c | SPI driver
gd32f3x0_syscfg.c | SYSCFG driver
gd32f3x0_timer.c | TIMER driver
gd32f3x0_tsi.c | Tsi driver
gd32f3x0_usart.c | USART driver
gd32f3x0_wwdgt.c | WWDGT driver
▼ GD32F3x0_usbfs_driver |
▼ Include |
usb_core.h | USB core driver header file
usb_defines.h | USB core defines
usb_regs.h | USB FS cell registers definition and handle macros
usb_std.h | USB 2.0 standard defines
usbd_core.h | USB device mode core driver header file
usbd_int.h | USB device mode interrupt handler header file
usbd_std.h | USB 2.0 standard defines
usbh_core.h | Header file for usbh_core.c
usbh_ctrl.h | Header file for usbh_ctrl.c
usbh_hcs.h | Header file for usbh_hcs.c
usbh_int.h | USB host mode interrupt handler header file
usbh_std.h | Header file for usbh_std.c
▼ Source |
system_gd32f3x0.c | CMSIS Cortex-M4 Device Peripheral Access Layer Source File for GD32F3x0 Device Series
usb_core.c | USB core driver which can operate in host-mode and device-mode
usbd_core.c | USB device mode core driver
usbd_int.c | USB device mode interrupt routines
usbd_std.c | USB 2.0 standard handler driver
usbh_core.c | This file implements the functions for the core state machine process
usbh_ctrl.c | This file implements the functions for the control transmit process
usbh_hcs.c | This file implements functions for opening and closing host channels
usbh_int.c | USB host mode interrupt handler file
usbh_std.c | USB 2.0 standard function definition


GD32F3x0_Firmware_Library: E: Directory Reference

  • E:
E: Directory Reference

Directories

directory GD32F3x0_Firmware_Library


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library Directory Reference

  • E:
  • GD32F3x0_Firmware_Library
GD32F3x0_Firmware_Library Directory Reference

Directories

directory Firmware


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware Directory Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
Firmware Directory Reference

Directories

directory | GD32F3x0_standard_peripheral
directory | GD32F3x0_usbfs_driver


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral Directory Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
GD32F3x0_standard_peripheral Directory Reference

Directories

directory | Include
directory | Source


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include Directory Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Include Directory Reference

Files

file | gd32f3x0_adc.h [code]
definitions for the ADC
file | gd32f3x0_cec.h [code]
definitions for the CEC
file | gd32f3x0_cmp.h [code]
definitions for the CMP
file | gd32f3x0_crc.h [code]
definitions for the CRC
file | gd32f3x0_ctc.h [code]
definitions for the CTC
file | gd32f3x0_dac.h [code]
definitions for the DAC
file | gd32f3x0_dbg.h [code]
definitions for the DBG
file | gd32f3x0_dma.h [code]
definitions for the DMA
file | gd32f3x0_exti.h [code]
definitions for the EXTI
file | gd32f3x0_fmc.h [code]
definitions for the FMC
file | gd32f3x0_fwdgt.h [code]
definitions for the FWDGT
file | gd32f3x0_gpio.h [code]
definitions for the GPIO
file | gd32f3x0_i2c.h [code]
definitions for the I2C
file | gd32f3x0_misc.h [code]
definitions for the MISC
file | gd32f3x0_pmu.h [code]
definitions for the PMU
file | gd32f3x0_rcu.h [code]
definitions for the RCU
file | gd32f3x0_rtc.h [code]
definitions for the RTC
file | gd32f3x0_spi.h [code]
definitions for the SPI
file | gd32f3x0_syscfg.h [code]
definitions for the SYSCFG
file | gd32f3x0_timer.h [code]
definitions for the TIMER
file | gd32f3x0_tsi.h [code]
definitions for the TSI
file | gd32f3x0_usart.h [code]
definitions for the USART
file | gd32f3x0_wwdgt.h [code]
definitions for the WWDGT


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_adc.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Functions
gd32f3x0_adc.h File Reference

definitions for the ADC More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | ADC ADC_BASE
#define | ADC_STAT REG32(ADC + 0x00U)
#define | ADC_CTL0 REG32(ADC + 0x04U)
#define | ADC_CTL1 REG32(ADC + 0x08U)
#define | ADC_SAMPT0 REG32(ADC + 0x0CU)
#define | ADC_SAMPT1 REG32(ADC + 0x10U)
#define | ADC_IOFF0 REG32(ADC + 0x14U)
#define | ADC_IOFF1 REG32(ADC + 0x18U)
#define | ADC_IOFF2 REG32(ADC + 0x1CU)
#define | ADC_IOFF3 REG32(ADC + 0x20U)
#define | ADC_WDHT REG32(ADC + 0x24U)
#define | ADC_WDLT REG32(ADC + 0x28U)
#define | ADC_RSQ0 REG32(ADC + 0x2CU)
#define | ADC_RSQ1 REG32(ADC + 0x30U)
#define | ADC_RSQ2 REG32(ADC + 0x34U)
#define | ADC_ISQ REG32(ADC + 0x38U)
#define | ADC_IDATA0 REG32(ADC + 0x3CU)
#define | ADC_IDATA1 REG32(ADC + 0x40U)
#define | ADC_IDATA2 REG32(ADC + 0x44U)
#define | ADC_IDATA3 REG32(ADC + 0x48U)
#define | ADC_RDATA REG32(ADC + 0x4CU)
#define | ADC_OVSAMPCTL REG32(ADC + 0x80U)
#define | ADC_STAT_WDE BIT(0)
#define | ADC_STAT_EOC BIT(1)
#define | ADC_STAT_EOIC BIT(2)
#define | ADC_STAT_STIC BIT(3)
#define | ADC_STAT_STRC BIT(4)
#define | ADC_CTL0_WDCHSEL BITS(0,4)
#define | ADC_CTL0_EOCIE BIT(5)
#define | ADC_CTL0_WDEIE BIT(6)
#define | ADC_CTL0_EOICIE BIT(7)
#define | ADC_CTL0_SM BIT(8)
#define | ADC_CTL0_WDSC BIT(9)
#define | ADC_CTL0_ICA BIT(10)
#define | ADC_CTL0_DISRC BIT(11)
#define | ADC_CTL0_DISIC BIT(12)
#define | ADC_CTL0_DISNUM BITS(13,15)
#define | ADC_CTL0_IWDEN BIT(22)
#define | ADC_CTL0_RWDEN BIT(23)
#define | ADC_CTL0_DRES BITS(24,25)
#define | ADC_CTL1_ADCON BIT(0)
#define | ADC_CTL1_CTN BIT(1)
#define | ADC_CTL1_CLB BIT(2)
#define | ADC_CTL1_RSTCLB BIT(3)
#define | ADC_CTL1_DMA BIT(8)
#define | ADC_CTL1_DAL BIT(11)
#define | ADC_CTL1_ETSIC BITS(12,14)
#define | ADC_CTL1_ETEIC BIT(15)
#define | ADC_CTL1_ETSRC BITS(17,19)
#define | ADC_CTL1_ETERC BIT(20)
#define | ADC_CTL1_SWICST BIT(21)
#define | ADC_CTL1_SWRCST BIT(22)
#define | ADC_CTL1_TSVREN BIT(23)
#define | ADC_CTL1_VBETEN BIT(24)
#define | ADC_SAMPTX_SPTN BITS(0,2)
#define | ADC_IOFFX_IOFF BITS(0,11)
#define | ADC_WDHT_WDHT BITS(0,11)
#define | ADC_WDLT_WDLT BITS(0,11)
#define | ADC_RSQX_RSQN BITS(0,4)
#define | ADC_RSQ0_RL BITS(20,23)
#define | ADC_ISQ_ISQN BITS(0,4)
#define | ADC_ISQ_IL BITS(20,21)
#define | ADC_IDATAX_IDATAN BITS(0,15)
#define | ADC_RDATA_RDATA BITS(0,15)
#define | ADC_OVSAMPCTL_OVSEN BIT(0)
#define | ADC_OVSAMPCTL_OVSR BITS(2,4)
#define | ADC_OVSAMPCTL_OVSS BITS(5,8)
#define | ADC_OVSAMPCTL_TOVS BIT(9)
#define | ADC_FLAG_WDE ADC_STAT_WDE
#define | ADC_FLAG_EOC ADC_STAT_EOC
#define | ADC_FLAG_EOIC ADC_STAT_EOIC
#define | ADC_FLAG_STIC ADC_STAT_STIC
#define | ADC_FLAG_STRC ADC_STAT_STRC
#define | CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13))
#define | ADC_SCAN_MODE ADC_CTL0_SM
#define | ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA
#define | ADC_CONTINUOUS_MODE ADC_CTL1_CTN
#define | ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define | ADC_DATAALIGN_LEFT ADC_CTL1_DAL
#define | CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
#define | ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0)
#define | ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1)
#define | ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2)
#define | ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3)
#define | ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4)
#define | ADC_EXTTRIG_REGULAR_T14_CH1 CTL1_ETSRC(5)
#define | ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6)
#define | ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7)
#define | CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12))
#define | ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0)
#define | ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1)
#define | ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2)
#define | ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3)
#define | ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4)
#define | ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5)
#define | ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6)
#define | ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7)
#define | SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
#define | ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0)
#define | ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1)
#define | ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2)
#define | ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3)
#define | ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4)
#define | ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5)
#define | ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6)
#define | ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7)
#define | IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
#define | WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
#define | WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
#define | RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
#define | ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
#define | CTL0_DRES(regval) (BITS(24,25) & ((regval) << 24))
#define | ADC_RESOLUTION_12B CTL0_DRES(0)
#define | ADC_RESOLUTION_10B CTL0_DRES(1)
#define | ADC_RESOLUTION_8B CTL0_DRES(2)
#define | ADC_RESOLUTION_6B CTL0_DRES(3)
#define | OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
#define | ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0)
#define | ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1)
#define | ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2)
#define | ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3)
#define | ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4)
#define | ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5)
#define | ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6)
#define | ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7)
#define | ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8)
#define | OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2))
#define | ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0)
#define | ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1)
#define | ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2)
#define | ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3)
#define | ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4)
#define | ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5)
#define | ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6)
#define | ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7)
#define | ADC_OVERSAMPLING_ALL_CONVERT 0U
#define | ADC_OVERSAMPLING_ONE_CONVERT 1U
#define | ADC_REGULAR_CHANNEL ((uint8_t)0x01U)
#define | ADC_INSERTED_CHANNEL ((uint8_t)0x02U)
#define | ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U)
#define | ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U)
#define | ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U)
#define | ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U)
#define | ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U)
#define | ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U)
#define | ADC_CHANNEL_0 ((uint8_t)0x00U)
#define | ADC_CHANNEL_1 ((uint8_t)0x01U)
#define | ADC_CHANNEL_2 ((uint8_t)0x02U)
#define | ADC_CHANNEL_3 ((uint8_t)0x03U)
#define | ADC_CHANNEL_4 ((uint8_t)0x04U)
#define | ADC_CHANNEL_5 ((uint8_t)0x05U)
#define | ADC_CHANNEL_6 ((uint8_t)0x06U)
#define | ADC_CHANNEL_7 ((uint8_t)0x07U)
#define | ADC_CHANNEL_8 ((uint8_t)0x08U)
#define | ADC_CHANNEL_9 ((uint8_t)0x09U)
#define | ADC_CHANNEL_10 ((uint8_t)0x0AU)
#define | ADC_CHANNEL_11 ((uint8_t)0x0BU)
#define | ADC_CHANNEL_12 ((uint8_t)0x0CU)
#define | ADC_CHANNEL_13 ((uint8_t)0x0DU)
#define | ADC_CHANNEL_14 ((uint8_t)0x0EU)
#define | ADC_CHANNEL_15 ((uint8_t)0x0FU)
#define | ADC_CHANNEL_16 ((uint8_t)0x10U)
#define | ADC_CHANNEL_17 ((uint8_t)0x11U)
#define | ADC_CHANNEL_18 ((uint8_t)0x12U)
#define | ADC_INT_WDE ADC_STAT_WDE
#define | ADC_INT_EOC ADC_STAT_EOC
#define | ADC_INT_EOIC ADC_STAT_EOIC
#define | ADC_INT_FLAG_WDE ADC_STAT_WDE
#define | ADC_INT_FLAG_EOC ADC_STAT_EOC
#define | ADC_INT_FLAG_EOIC ADC_STAT_EOIC

Functions

void | adc_deinit (void)
reset ADC More...
void | adc_enable (void)
enable ADC interface More...
void | adc_disable (void)
disable ADC interface More...
void | adc_calibration_enable (void)
ADC calibration and reset calibration. More...
void | adc_dma_mode_enable (void)
enable DMA request More...
void | adc_dma_mode_disable (void)
disable DMA request More...
void | adc_tempsensor_vrefint_enable (void)
enable the temperature sensor and Vrefint channel More...
void | adc_tempsensor_vrefint_disable (void)
disable the temperature sensor and Vrefint channel More...
void | adc_vbat_enable (void)
enable the vbat channel More...
void | adc_vbat_disable (void)
disable the vbat channel More...
void | adc_discontinuous_mode_config (uint8_t channel_group, uint8_t length)
configure ADC discontinuous mode More...
void | adc_special_function_config (uint32_t function, ControlStatus newvalue)
configure ADC special function More...
void | adc_data_alignment_config (uint32_t data_alignment)
configure ADC data alignment More...
void | adc_channel_length_config (uint8_t channel_group, uint32_t length)
configure the length of regular channel group or inserted channel group More...
void | adc_regular_channel_config (uint8_t rank, uint8_t channel, uint32_t sample_time)
configure ADC regular channel More...
void | adc_inserted_channel_config (uint8_t rank, uint8_t channel, uint32_t sample_time)
configure ADC inserted channel More...
void | adc_inserted_channel_offset_config (uint8_t inserted_channel, uint16_t offset)
configure ADC inserted channel offset More...
void | adc_external_trigger_config (uint8_t channel_group, ControlStatus newvalue)
enable or disable ADC external trigger More...
void | adc_external_trigger_source_config (uint8_t channel_group, uint32_t external_trigger_source)
configure ADC external trigger source More...
void | adc_software_trigger_enable (uint8_t channel_group)
enable ADC software trigger More...
uint16_t | adc_regular_data_read (void)
read ADC regular group data register More...
uint16_t | adc_inserted_data_read (uint8_t inserted_channel)
read ADC inserted group data register More...
FlagStatus | adc_flag_get (uint32_t flag)
get the ADC flag bits More...
void | adc_flag_clear (uint32_t flag)
clear the ADC flag More...
FlagStatus | adc_interrupt_flag_get (uint32_t flag)
get the ADC interrupt flag More...
void | adc_interrupt_flag_clear (uint32_t flag)
clear ADC interrupt flag More...
void | adc_interrupt_enable (uint32_t interrupt)
enable ADC interrupt More...
void | adc_interrupt_disable (uint32_t interrupt)
disable ADC interrupt More...
void | adc_watchdog_single_channel_enable (uint8_t channel)
configure ADC analog watchdog single channel More...
void | adc_watchdog_group_channel_enable (uint8_t channel_group)
configure ADC analog watchdog group channel More...
void | adc_watchdog_disable (void)
disable ADC analog watchdog More...
void | adc_watchdog_threshold_config (uint16_t low_threshold, uint16_t high_threshold)
configure ADC analog watchdog threshold More...
void | adc_resolution_config (uint32_t resolution)
configure ADC resolution More...
void | adc_oversample_mode_config (uint8_t mode, uint16_t shift, uint8_t ratio)
configure ADC oversample mode More...
void | adc_oversample_mode_enable (void)
enable ADC oversample mode More...
void | adc_oversample_mode_disable (void)
disable ADC oversample mode More...

Detailed Description

definitions for the ADC

Definition in file gd32f3x0_adc.h.

Macro Definition Documentation

#define ADC ADC_BASE

Definition at line 18 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_0 ((uint8_t)0x00U)

ADC channel 0

Definition at line 229 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_1 ((uint8_t)0x01U)

ADC channel 1

Definition at line 230 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_10 ((uint8_t)0x0AU)

ADC channel 10

Definition at line 239 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_11 ((uint8_t)0x0BU)

ADC channel 11

Definition at line 240 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_12 ((uint8_t)0x0CU)

ADC channel 12

Definition at line 241 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_13 ((uint8_t)0x0DU)

ADC channel 13

Definition at line 242 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_14 ((uint8_t)0x0EU)

ADC channel 14

Definition at line 243 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_15 ((uint8_t)0x0FU)

ADC channel 15

Definition at line 244 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_16 ((uint8_t)0x10U)

ADC channel 16

Definition at line 245 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_17 ((uint8_t)0x11U)

ADC channel 17

Definition at line 246 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_18 ((uint8_t)0x12U)

ADC channel 18

Definition at line 247 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_2 ((uint8_t)0x02U)

ADC channel 2

Definition at line 231 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_3 ((uint8_t)0x03U)

ADC channel 3

Definition at line 232 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_4 ((uint8_t)0x04U)

ADC channel 4

Definition at line 233 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_5 ((uint8_t)0x05U)

ADC channel 5

Definition at line 234 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_6 ((uint8_t)0x06U)

ADC channel 6

Definition at line 235 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_7 ((uint8_t)0x07U)

ADC channel 7

Definition at line 236 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_8 ((uint8_t)0x08U)

ADC channel 8

Definition at line 237 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_9 ((uint8_t)0x09U)

ADC channel 9

Definition at line 238 of file gd32f3x0_adc.h.

#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U)

disable discontinuous mode of regular & inserted channel

Definition at line 220 of file gd32f3x0_adc.h.

#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN

continuous mode

Definition at line 128 of file gd32f3x0_adc.h.

#define ADC_CTL0 REG32(ADC + 0x04U)

ADC control register 0

Definition at line 22 of file gd32f3x0_adc.h.

#define ADC_CTL0_DISIC BIT(12)

discontinuous mode on inserted channels

Definition at line 60 of file gd32f3x0_adc.h.

#define ADC_CTL0_DISNUM BITS(13,15)

discontinuous mode channel count

Definition at line 61 of file gd32f3x0_adc.h.

#define ADC_CTL0_DISRC BIT(11)

discontinuous mode on regular channels

Definition at line 59 of file gd32f3x0_adc.h.

#define ADC_CTL0_DRES BITS(24,25)

ADC data resolution

Definition at line 64 of file gd32f3x0_adc.h.

#define ADC_CTL0_EOCIE BIT(5)

interrupt enable for EOC

Definition at line 53 of file gd32f3x0_adc.h.

#define ADC_CTL0_EOICIE BIT(7)

interrupt enable for inserted channels

Definition at line 55 of file gd32f3x0_adc.h.

#define ADC_CTL0_ICA BIT(10)

automatic inserted group conversion

Definition at line 58 of file gd32f3x0_adc.h.

#define ADC_CTL0_IWDEN BIT(22)

analog watchdog enable on inserted channels

Definition at line 62 of file gd32f3x0_adc.h.

#define ADC_CTL0_RWDEN BIT(23)

analog watchdog enable on regular channels

Definition at line 63 of file gd32f3x0_adc.h.

#define ADC_CTL0_SM BIT(8)

scan mode

Definition at line 56 of file gd32f3x0_adc.h.

#define ADC_CTL0_WDCHSEL BITS(0,4)

analog watchdog channel select bits

Definition at line 52 of file gd32f3x0_adc.h.

#define ADC_CTL0_WDEIE BIT(6)

analog watchdog interrupt enable

Definition at line 54 of file gd32f3x0_adc.h.

#define ADC_CTL0_WDSC BIT(9)

when in scan mode, analog watchdog is effective on a single channel

Definition at line 57 of file gd32f3x0_adc.h.

#define ADC_CTL1 REG32(ADC + 0x08U)

ADC control register 1

Definition at line 23 of file gd32f3x0_adc.h.

#define ADC_CTL1_ADCON BIT(0)

ADC converter on

Definition at line 67 of file gd32f3x0_adc.h.

#define ADC_CTL1_CLB BIT(2)

ADC calibration

Definition at line 69 of file gd32f3x0_adc.h.

#define ADC_CTL1_CTN BIT(1)

continuous conversion

Definition at line 68 of file gd32f3x0_adc.h.

#define ADC_CTL1_DAL BIT(11)

data alignment

Definition at line 72 of file gd32f3x0_adc.h.

#define ADC_CTL1_DMA BIT(8)

direct memory access mode

Definition at line 71 of file gd32f3x0_adc.h.

#define ADC_CTL1_ETEIC BIT(15)

external trigger enable for inserted channel

Definition at line 74 of file gd32f3x0_adc.h.

#define ADC_CTL1_ETERC BIT(20)

external trigger enable for regular channel

Definition at line 76 of file gd32f3x0_adc.h.

#define ADC_CTL1_ETSIC BITS(12,14)

external trigger select for inserted channel

Definition at line 73 of file gd32f3x0_adc.h.

#define ADC_CTL1_ETSRC BITS(17,19)

external trigger select for regular channel

Definition at line 75 of file gd32f3x0_adc.h.

#define ADC_CTL1_RSTCLB BIT(3)

reset calibration

Definition at line 70 of file gd32f3x0_adc.h.

#define ADC_CTL1_SWICST BIT(21)

start on inserted channel

Definition at line 77 of file gd32f3x0_adc.h.

#define ADC_CTL1_SWRCST BIT(22)

start on regular channel

Definition at line 78 of file gd32f3x0_adc.h.

#define ADC_CTL1_TSVREN BIT(23)

enable channel 16 and 17

Definition at line 79 of file gd32f3x0_adc.h.

#define ADC_CTL1_VBETEN BIT(24)

VBAT enable

Definition at line 80 of file gd32f3x0_adc.h.

#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL

MSB alignment

Definition at line 132 of file gd32f3x0_adc.h.

#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)

LSB alignment

Definition at line 131 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6)

external interrupt line 15

Definition at line 153 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7)

software trigger

Definition at line 154 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1)

TIMER0 CH3 event select

Definition at line 148 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0)

TIMER0 TRGO event select

Definition at line 147 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5)

TIMER14 TRGO event select

Definition at line 152 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3)

TIMER1 CH0 event select

Definition at line 150 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2)

TIMER1 TRGO event select

Definition at line 149 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4)

TIMER2 CH3 event select

Definition at line 151 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6)

external interrupt line 11

Definition at line 142 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7)

software trigger

Definition at line 143 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0)

TIMER0 CH0 event select

Definition at line 136 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1)

TIMER0 CH1 event select

Definition at line 137 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2)

TIMER0 CH2 event select

Definition at line 138 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_REGULAR_T14_CH1 CTL1_ETSRC(5)

TIMER14 CH1 event select

Definition at line 141 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3)

TIMER1 CH1 event select

Definition at line 139 of file gd32f3x0_adc.h.

#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4)

TIMER2 TRGO event select

Definition at line 140 of file gd32f3x0_adc.h.

#define ADC_FLAG_EOC ADC_STAT_EOC

end of group conversion flag

Definition at line 117 of file gd32f3x0_adc.h.

#define ADC_FLAG_EOIC ADC_STAT_EOIC

end of inserted channel group conversion flag

Definition at line 118 of file gd32f3x0_adc.h.

#define ADC_FLAG_STIC ADC_STAT_STIC

start flag of inserted channel group

Definition at line 119 of file gd32f3x0_adc.h.

#define ADC_FLAG_STRC ADC_STAT_STRC

start flag of regular channel group

Definition at line 120 of file gd32f3x0_adc.h.

#define ADC_FLAG_WDE ADC_STAT_WDE

analog watchdog event flag

Definition at line 116 of file gd32f3x0_adc.h.

#define ADC_IDATA0 REG32(ADC + 0x3CU)

ADC inserted data register 0

Definition at line 36 of file gd32f3x0_adc.h.

#define ADC_IDATA1 REG32(ADC + 0x40U)

ADC inserted data register 1

Definition at line 37 of file gd32f3x0_adc.h.

#define ADC_IDATA2 REG32(ADC + 0x44U)

ADC inserted data register 2

Definition at line 38 of file gd32f3x0_adc.h.

#define ADC_IDATA3 REG32(ADC + 0x48U)

ADC inserted data register 3

Definition at line 39 of file gd32f3x0_adc.h.

#define ADC_IDATAX_IDATAN BITS(0,15)

inserted channel x conversion data

Definition at line 103 of file gd32f3x0_adc.h.

#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U)

ADC inserted channel group

Definition at line 218 of file gd32f3x0_adc.h.

#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U)

ADC inserted channel 0

Definition at line 223 of file gd32f3x0_adc.h.

#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U)

ADC inserted channel 1

Definition at line 224 of file gd32f3x0_adc.h.

#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U)

ADC inserted channel 2

Definition at line 225 of file gd32f3x0_adc.h.

#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U)

ADC inserted channel 3

Definition at line 226 of file gd32f3x0_adc.h.

#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA

inserted channel group convert automatically

Definition at line 127 of file gd32f3x0_adc.h.

#define ADC_INT_EOC ADC_STAT_EOC

end of group conversion interrupt

Definition at line 251 of file gd32f3x0_adc.h.

#define ADC_INT_EOIC ADC_STAT_EOIC

end of inserted group conversion interrupt

Definition at line 252 of file gd32f3x0_adc.h.

#define ADC_INT_FLAG_EOC ADC_STAT_EOC

end of group conversion interrupt flag

Definition at line 256 of file gd32f3x0_adc.h.

#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC

end of inserted group conversion interrupt flag

Definition at line 257 of file gd32f3x0_adc.h.

#define ADC_INT_FLAG_WDE ADC_STAT_WDE

analog watchdog event interrupt flag

Definition at line 255 of file gd32f3x0_adc.h.

#define ADC_INT_WDE ADC_STAT_WDE

analog watchdog event interrupt

Definition at line 250 of file gd32f3x0_adc.h.

#define ADC_IOFF0 REG32(ADC + 0x14U)

ADC inserted channel data offset register 0

Definition at line 26 of file gd32f3x0_adc.h.

#define ADC_IOFF1 REG32(ADC + 0x18U)

ADC inserted channel data offset register 1

Definition at line 27 of file gd32f3x0_adc.h.

#define ADC_IOFF2 REG32(ADC + 0x1CU)

ADC inserted channel data offset register 2

Definition at line 28 of file gd32f3x0_adc.h.

#define ADC_IOFF3 REG32(ADC + 0x20U)

ADC inserted channel data offset register 3

Definition at line 29 of file gd32f3x0_adc.h.

#define ADC_IOFFX_IOFF BITS(0,11)

data offset for inserted channel x

Definition at line 86 of file gd32f3x0_adc.h.

#define ADC_ISQ REG32(ADC + 0x38U)

ADC inserted sequence register

Definition at line 35 of file gd32f3x0_adc.h.

#define ADC_ISQ_IL BITS(20,21)

inserted sequence length

Definition at line 100 of file gd32f3x0_adc.h.

#define ADC_ISQ_ISQN BITS(0,4)

n conversion in regular sequence

Definition at line 99 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_ALL_CONVERT 0U

all oversampled conversions for a channel are done consecutively after a trigger

Definition at line 213 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_ONE_CONVERT 1U

each oversampled conversion for a channel needs a trigger

Definition at line 214 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6)

oversampling ratio multiple 128

Definition at line 209 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3)

oversampling ratio multiple 16

Definition at line 206 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0)

oversampling ratio multiple 2

Definition at line 203 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7)

oversampling ratio multiple 256

Definition at line 210 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4)

oversampling ratio multiple 32

Definition at line 207 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1)

oversampling ratio multiple 4

Definition at line 204 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5)

oversampling ratio multiple 64

Definition at line 208 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2)

oversampling ratio multiple 8

Definition at line 205 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1)

1-bit oversampling shift

Definition at line 192 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2)

2-bit oversampling shift

Definition at line 193 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3)

3-bit oversampling shift

Definition at line 194 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4)

4-bit oversampling shift

Definition at line 195 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5)

5-bit oversampling shift

Definition at line 196 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6)

6-bit oversampling shift

Definition at line 197 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7)

7-bit oversampling shift

Definition at line 198 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8)

8-bit oversampling shift

Definition at line 199 of file gd32f3x0_adc.h.

#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0)

no oversampling shift

Definition at line 191 of file gd32f3x0_adc.h.

#define ADC_OVSAMPCTL REG32(ADC + 0x80U)

ADC oversampling control register

Definition at line 41 of file gd32f3x0_adc.h.

#define ADC_OVSAMPCTL_OVSEN BIT(0)

oversampling enable

Definition at line 109 of file gd32f3x0_adc.h.

#define ADC_OVSAMPCTL_OVSR BITS(2,4)

oversampling ratio

Definition at line 110 of file gd32f3x0_adc.h.

#define ADC_OVSAMPCTL_OVSS BITS(5,8)

oversampling shift

Definition at line 111 of file gd32f3x0_adc.h.

#define ADC_OVSAMPCTL_TOVS BIT(9)

triggered oversampling

Definition at line 112 of file gd32f3x0_adc.h.

#define ADC_RDATA REG32(ADC + 0x4CU)

ADC regular data register

Definition at line 40 of file gd32f3x0_adc.h.

#define ADC_RDATA_RDATA BITS(0,15)

regular channel data

Definition at line 106 of file gd32f3x0_adc.h.

#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U)

ADC regular channel group

Definition at line 217 of file gd32f3x0_adc.h.

#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U)

both regular and inserted channel group

Definition at line 219 of file gd32f3x0_adc.h.

#define ADC_RESOLUTION_10B CTL0_DRES(1)

10-bit ADC resolution

Definition at line 185 of file gd32f3x0_adc.h.

#define ADC_RESOLUTION_12B CTL0_DRES(0)

12-bit ADC resolution

Definition at line 184 of file gd32f3x0_adc.h.

#define ADC_RESOLUTION_6B CTL0_DRES(3)

6-bit ADC resolution

Definition at line 187 of file gd32f3x0_adc.h.

#define ADC_RESOLUTION_8B CTL0_DRES(2)

8-bit ADC resolution

Definition at line 186 of file gd32f3x0_adc.h.

#define ADC_RSQ0 REG32(ADC + 0x2CU)

ADC regular sequence register 0

Definition at line 32 of file gd32f3x0_adc.h.

#define ADC_RSQ0_RL BITS(20,23)

regular channel sequence length

Definition at line 96 of file gd32f3x0_adc.h.

#define ADC_RSQ1 REG32(ADC + 0x30U)

ADC regular sequence register 1

Definition at line 33 of file gd32f3x0_adc.h.

#define ADC_RSQ2 REG32(ADC + 0x34U)

ADC regular sequence register 2

Definition at line 34 of file gd32f3x0_adc.h.

#define ADC_RSQX_RSQN BITS(0,4)

x conversion in regular sequence

Definition at line 95 of file gd32f3x0_adc.h.

#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2)

13.5 sampling cycles

Definition at line 160 of file gd32f3x0_adc.h.

#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0)

1.5 sampling cycles

Definition at line 158 of file gd32f3x0_adc.h.

#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7)

239.5 sampling cycles

Definition at line 165 of file gd32f3x0_adc.h.

#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3)

28.5 sampling cycles

Definition at line 161 of file gd32f3x0_adc.h.

#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4)

41.5 sampling cycles

Definition at line 162 of file gd32f3x0_adc.h.

#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5)

55.5 sampling cycles

Definition at line 163 of file gd32f3x0_adc.h.

#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6)

71.5 sampling cycles

Definition at line 164 of file gd32f3x0_adc.h.

#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1)

7.5 sampling cycles

Definition at line 159 of file gd32f3x0_adc.h.

#define ADC_SAMPT0 REG32(ADC + 0x0CU)

ADC sampling time register 0

Definition at line 24 of file gd32f3x0_adc.h.

#define ADC_SAMPT1 REG32(ADC + 0x10U)

ADC sampling time register 1

Definition at line 25 of file gd32f3x0_adc.h.

#define ADC_SAMPTX_SPTN BITS(0,2)

channel n sample time selection

Definition at line 83 of file gd32f3x0_adc.h.

#define ADC_SCAN_MODE ADC_CTL0_SM

scan mode

Definition at line 126 of file gd32f3x0_adc.h.

#define ADC_STAT REG32(ADC + 0x00U)

ADC status register

Definition at line 21 of file gd32f3x0_adc.h.

#define ADC_STAT_EOC BIT(1)

end of conversion

Definition at line 46 of file gd32f3x0_adc.h.

#define ADC_STAT_EOIC BIT(2)

inserted channel end of conversion

Definition at line 47 of file gd32f3x0_adc.h.

#define ADC_STAT_STIC BIT(3)

inserted channel start flag

Definition at line 48 of file gd32f3x0_adc.h.

#define ADC_STAT_STRC BIT(4)

regular channel start flag

Definition at line 49 of file gd32f3x0_adc.h.

#define ADC_STAT_WDE BIT(0)

analog watchdog event flag

Definition at line 45 of file gd32f3x0_adc.h.

#define ADC_WDHT REG32(ADC + 0x24U)

ADC watchdog high threshold register

Definition at line 30 of file gd32f3x0_adc.h.

#define ADC_WDHT_WDHT BITS(0,11)

analog watchdog high threshold

Definition at line 89 of file gd32f3x0_adc.h.

#define ADC_WDLT REG32(ADC + 0x28U)

ADC watchdog low threshold register

Definition at line 31 of file gd32f3x0_adc.h.

#define ADC_WDLT_WDLT BITS(0,11)

analog watchdog low threshold

Definition at line 92 of file gd32f3x0_adc.h.

#define CTL0_DISNUM ( regval ) (BITS(13,15) & ((uint32_t)(regval) << 13))

number of conversions in discontinuous mode

Definition at line 123 of file gd32f3x0_adc.h.

#define CTL0_DRES ( regval ) (BITS(24,25) & ((regval) << 24))

ADC resolution

Definition at line 183 of file gd32f3x0_adc.h.

#define CTL1_ETSIC ( regval ) (BITS(12,14) & ((uint32_t)(regval) << 12))

Definition at line 146 of file gd32f3x0_adc.h.

#define CTL1_ETSRC ( regval ) (BITS(17,19) & ((uint32_t)(regval) << 17))

Definition at line 135 of file gd32f3x0_adc.h.

#define IOFFX_IOFF ( regval ) (BITS(0,11) & ((uint32_t)(regval) << 0))

Definition at line 168 of file gd32f3x0_adc.h.

#define ISQ_IL ( regval ) (BITS(20,21) & ((uint32_t)(regval) << 20))

Definition at line 180 of file gd32f3x0_adc.h.

#define OVSAMPCTL_OVSR ( regval ) (BITS(2,4) & ((uint32_t)(regval) << 2))

Definition at line 202 of file gd32f3x0_adc.h.

#define OVSAMPCTL_OVSS ( regval ) (BITS(5,8) & ((uint32_t)(regval) << 5))

Definition at line 190 of file gd32f3x0_adc.h.

#define RSQ0_RL ( regval ) (BITS(20,23) & ((uint32_t)(regval) << 20))

Definition at line 177 of file gd32f3x0_adc.h.

#define SAMPTX_SPT ( regval ) (BITS(0,2) & ((uint32_t)(regval) << 0))

Definition at line 157 of file gd32f3x0_adc.h.

#define WDHT_WDHT ( regval ) (BITS(0,11) & ((uint32_t)(regval) << 0))

Definition at line 171 of file gd32f3x0_adc.h.

#define WDLT_WDLT ( regval ) (BITS(0,11) & ((uint32_t)(regval) << 0))

Definition at line 174 of file gd32f3x0_adc.h.

Function Documentation

void adc_calibration_enable ( void )

ADC calibration and reset calibration.

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 56 of file gd32f3x0_adc.c.

57 {
58 /* reset the selected ADC calibration register */
59 ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB;
60 /* check the RSTCLB bit state */
61 while((ADC_CTL1 & ADC_CTL1_RSTCLB)){
62 }
63
64 /* enable ADC calibration process */
65 ADC_CTL1 |= ADC_CTL1_CLB;
66 /* check the CLB bit state */
67 while((ADC_CTL1 & ADC_CTL1_CLB)){
68 }
69 }
ADC_CTL1_RSTCLB
#define ADC_CTL1_RSTCLB
Definition: gd32f3x0_adc.h:70
ADC_CTL1_CLB
#define ADC_CTL1_CLB
Definition: gd32f3x0_adc.h:69
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_channel_length_config | ( | uint8_t | channel_group,
 |  | uint32_t | length
 | ) |  |

configure the length of regular channel group or inserted channel group

Parameters
[in] channel_group select the channel group only one parameter can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[in] | length | the length of the channel regular channel 1-16 inserted channel 1-4
[out] | none
Return values
none

Definition at line 262 of file gd32f3x0_adc.c.

263 {
264 switch(channel_group){
265 case ADC_REGULAR_CHANNEL:
266 /* configure the length of regular channel group */
267 ADC_RSQ0 &= ~((uint32_t)ADC_RSQ0_RL);
268 ADC_RSQ0 |= RSQ0_RL((uint32_t)(length-1U));
269 break;
270 case ADC_INSERTED_CHANNEL:
271 /* configure the length of inserted channel group */
272 ADC_ISQ &= ~((uint32_t)ADC_ISQ_IL);
273 ADC_ISQ |= ISQ_IL((uint32_t)(length-1U));
274 break;
275 default:
276 break;
277 }
278 }
ADC_ISQ_IL
#define ADC_ISQ_IL
Definition: gd32f3x0_adc.h:100
ADC_ISQ
#define ADC_ISQ
Definition: gd32f3x0_adc.h:35
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f3x0_adc.h:217
ISQ_IL
#define ISQ_IL(regval)
Definition: gd32f3x0_adc.h:180
ADC_RSQ0
#define ADC_RSQ0
Definition: gd32f3x0_adc.h:32
ADC_RSQ0_RL
#define ADC_RSQ0_RL
Definition: gd32f3x0_adc.h:96
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:218
RSQ0_RL
#define RSQ0_RL(regval)
Definition: gd32f3x0_adc.h:177
void adc_data_alignment_config ( uint32_t data_alignment )

configure ADC data alignment

Parameters
[in] data_alignment data alignment select only one parameter can be selected
  • ADC_DATAALIGN_RIGHT: LSB alignment
  • ADC_DATAALIGN_LEFT: MSB alignment
[out] none
Return values
none

Definition at line 241 of file gd32f3x0_adc.c.

242 {
243 if(ADC_DATAALIGN_RIGHT != data_alignment){
244 ADC_CTL1 |= ADC_CTL1_DAL;
245 }else{
246 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DAL);
247 }
248 }
ADC_CTL1_DAL
#define ADC_CTL1_DAL
Definition: gd32f3x0_adc.h:72
ADC_DATAALIGN_RIGHT
#define ADC_DATAALIGN_RIGHT
Definition: gd32f3x0_adc.h:131
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_deinit ( void )

reset ADC

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_adc.c.

21 {
22 rcu_periph_reset_enable(RCU_ADCRST);
23 rcu_periph_reset_disable(RCU_ADCRST);
24 }
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
RCU_ADCRST
Definition: gd32f3x0_rcu.h:335
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
void adc_disable ( void )

disable ADC interface

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 45 of file gd32f3x0_adc.c.

46 {
47 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ADCON);
48 }
ADC_CTL1_ADCON
#define ADC_CTL1_ADCON
Definition: gd32f3x0_adc.h:67
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_discontinuous_mode_config | ( | uint8_t | channel_group,
 |  | uint8_t | length
 | ) |  |

configure ADC discontinuous mode

Parameters
[in] channel_group select the channel group only one among these parameters can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
  • ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular and inserted channel
[in] | length | number of conversions in discontinuous mode,the number can be 1..8 for regular channel, the number has no effect for inserted channel
[out] | none
Return values
none

Definition at line 170 of file gd32f3x0_adc.c.

171 {
172 ADC_CTL0 &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
173
174 switch(channel_group){
175 case ADC_REGULAR_CHANNEL:
176 /* configure the number of conversions in discontinuous mode */
177 ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DISNUM);
178 ADC_CTL0 |= CTL0_DISNUM(((uint32_t)length - 1U));
179 ADC_CTL0 |= (uint32_t)ADC_CTL0_DISRC;
180 break;
181 case ADC_INSERTED_CHANNEL:
182 ADC_CTL0 |= (uint32_t)ADC_CTL0_DISIC;
183 break;
184 case ADC_CHANNEL_DISCON_DISABLE:
185 default:
186 break;
187 }
188 }
CTL0_DISNUM
#define CTL0_DISNUM(regval)
Definition: gd32f3x0_adc.h:123
ADC_CTL0_DISRC
#define ADC_CTL0_DISRC
Definition: gd32f3x0_adc.h:59
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f3x0_adc.h:217
ADC_CTL0_DISNUM
#define ADC_CTL0_DISNUM
Definition: gd32f3x0_adc.h:61
ADC_CHANNEL_DISCON_DISABLE
#define ADC_CHANNEL_DISCON_DISABLE
Definition: gd32f3x0_adc.h:220
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:218
ADC_CTL0_DISIC
#define ADC_CTL0_DISIC
Definition: gd32f3x0_adc.h:60
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_dma_mode_disable ( void )

disable DMA request

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 88 of file gd32f3x0_adc.c.

89 {
90 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DMA);
91 }
ADC_CTL1_DMA
#define ADC_CTL1_DMA
Definition: gd32f3x0_adc.h:71
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_dma_mode_enable ( void )

enable DMA request

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 77 of file gd32f3x0_adc.c.

78 {
79 ADC_CTL1 |= (uint32_t)(ADC_CTL1_DMA);
80 }
ADC_CTL1_DMA
#define ADC_CTL1_DMA
Definition: gd32f3x0_adc.h:71
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_enable ( void )

enable ADC interface

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 32 of file gd32f3x0_adc.c.

33 {
34 if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)){
35 ADC_CTL1 |= (uint32_t)ADC_CTL1_ADCON;
36 }
37 }
ADC_CTL1_ADCON
#define ADC_CTL1_ADCON
Definition: gd32f3x0_adc.h:67
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_external_trigger_config | ( | uint8_t | channel_group,
 |  | ControlStatus | newvalue
 | ) |  |

enable or disable ADC external trigger

Parameters
[in] channel_group select the channel group one or more parameters can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 423 of file gd32f3x0_adc.c.

424 {
425 if(newvalue){
426 /* external trigger enable for regular channel */
427 if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
428 ADC_CTL1 |= ADC_CTL1_ETERC;
429 }
430 /* external trigger enable for inserted channel */
431 if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
432 ADC_CTL1 |= ADC_CTL1_ETEIC;
433 }
434 }else{
435 /* external trigger disable for regular channel */
436 if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
437 ADC_CTL1 &= ~ADC_CTL1_ETERC;
438 }
439 /* external trigger disable for inserted channel */
440 if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
441 ADC_CTL1 &= ~ADC_CTL1_ETEIC;
442 }
443 }
444 }
ADC_CTL1_ETEIC
#define ADC_CTL1_ETEIC
Definition: gd32f3x0_adc.h:74
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f3x0_adc.h:217
ADC_CTL1_ETERC
#define ADC_CTL1_ETERC
Definition: gd32f3x0_adc.h:76
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:218
void adc_external_trigger_source_config | ( | uint8_t | channel_group,
 |  | uint32_t | external_trigger_source
 | ) |  |

configure ADC external trigger source

Parameters
[in] channel_group select the channel group only one parameter can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[in] external_trigger_source regular or inserted group trigger source only one parameter can be selected for regular channel:
  • ADC_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select
  • ADC_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select
  • ADC_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select
  • ADC_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select
  • ADC_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select
  • ADC_EXTTRIG_REGULAR_T14_CH1: TIMER14 CH1 event select
  • ADC_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11
  • ADC_EXTTRIG_REGULAR_NONE: software trigger for inserted channel:
  • ADC_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select
  • ADC_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select
  • ADC_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select
  • ADC_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select
  • ADC_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select
  • ADC_EXTTRIG_INSERTED_T14_TRGO: TIMER14 TRGO event select
  • ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15
  • ADC_EXTTRIG_INSERTED_NONE: software trigger
[out] none
Return values
none

Definition at line 475 of file gd32f3x0_adc.c.

476 {
477 switch(channel_group){
478 case ADC_REGULAR_CHANNEL:
479 /* external trigger select for regular channel */
480 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSRC);
481 ADC_CTL1 |= (uint32_t)external_trigger_source;
482 break;
483 case ADC_INSERTED_CHANNEL:
484 /* external trigger select for inserted channel */
485 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSIC);
486 ADC_CTL1 |= (uint32_t)external_trigger_source;
487 break;
488 default:
489 break;
490 }
491 }
ADC_CTL1_ETSIC
#define ADC_CTL1_ETSIC
Definition: gd32f3x0_adc.h:73
ADC_CTL1_ETSRC
#define ADC_CTL1_ETSRC
Definition: gd32f3x0_adc.h:75
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f3x0_adc.h:217
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:218
void adc_flag_clear ( uint32_t flag )

clear the ADC flag

Parameters
[in] flag the adc flag one or more parameters can be selected
  • ADC_FLAG_WDE: analog watchdog event flag
  • ADC_FLAG_EOC: end of group conversion flag
  • ADC_FLAG_EOIC: end of inserted group conversion flag
  • ADC_FLAG_STIC: start flag of inserted channel group
  • ADC_FLAG_STRC: start flag of regular channel group
[out] none
Return values
none

Definition at line 594 of file gd32f3x0_adc.c.

595 {
596 ADC_STAT &= ~((uint32_t)flag);
597 }
ADC_STAT
#define ADC_STAT
Definition: gd32f3x0_adc.h:21
FlagStatus adc_flag_get ( uint32_t flag )

get the ADC flag bits

Parameters
[in] flag the adc flag bits only one parameter can be selected
  • ADC_FLAG_WDE: analog watchdog event flag
  • ADC_FLAG_EOC: end of group conversion flag
  • ADC_FLAG_EOIC: end of inserted group conversion flag
  • ADC_FLAG_STIC: start flag of inserted channel group
  • ADC_FLAG_STRC: start flag of regular channel group
[out] none
Return values
FlagStatus SET or RESET

Definition at line 572 of file gd32f3x0_adc.c.

573 {
574 FlagStatus reval = RESET;
575
576 if(ADC_STAT & flag){
577 reval = SET;
578 }
579 return reval;
580 }
ADC_STAT
#define ADC_STAT
Definition: gd32f3x0_adc.h:21
void adc_inserted_channel_config | ( | uint8_t | rank,
 |  | uint8_t | channel,
 |  | uint32_t | sample_time
 | ) |  |

configure ADC inserted channel

Parameters
[in] | rank | the inserted group sequencer rank,this parameter must be between 0 to 3
[in] channel the selected ADC channel only one among these parameters can be selected
  • ADC_CHANNEL_x(x=0..18): ADC Channelx
[in] sample_time The sample time value only one parameter can be selected
  • ADC_SAMPLETIME_1POINT5: 1.5 cycles
  • ADC_SAMPLETIME_7POINT5: 7.5 cycles
  • ADC_SAMPLETIME_13POINT5: 13.5 cycles
  • ADC_SAMPLETIME_28POINT5: 28.5 cycles
  • ADC_SAMPLETIME_41POINT5: 41.5 cycles
  • ADC_SAMPLETIME_55POINT5: 55.5 cycles
  • ADC_SAMPLETIME_71POINT5: 71.5 cycles
  • ADC_SAMPLETIME_239POINT5: 239.5 cycles
[out] | none
Return values
none

Definition at line 357 of file gd32f3x0_adc.c.

358 {
359 uint8_t inserted_length;
360 uint32_t isq,sampt;
361
362 inserted_length = (uint8_t)GET_BITS(ADC_ISQ , 20U , 21U);
363
364 isq = ADC_ISQ;
365 isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U - (inserted_length - rank)*5U)));
366 isq |= ((uint32_t)channel << (15U - (inserted_length - rank)*5U));
367 ADC_ISQ = isq;
368
369 /* configure ADC sampling time */
370 if(channel < 10U){
371 sampt = ADC_SAMPT1;
372 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel)));
373 sampt |= (uint32_t) sample_time << (3U*channel);
374 ADC_SAMPT1 = sampt;
375 }else if(channel < 19U){
376 sampt = ADC_SAMPT0;
377 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel - 10U))));
378 sampt |= ((uint32_t)sample_time << (3U*(channel - 10U)));
379 ADC_SAMPT0 = sampt;
380 }else{
381 /* illegal parameters */
382 }
383 }
ADC_SAMPT0
#define ADC_SAMPT0
Definition: gd32f3x0_adc.h:24
ADC_ISQ_ISQN
#define ADC_ISQ_ISQN
Definition: gd32f3x0_adc.h:99
ADC_ISQ
#define ADC_ISQ
Definition: gd32f3x0_adc.h:35
ADC_SAMPT1
#define ADC_SAMPT1
Definition: gd32f3x0_adc.h:25
ADC_SAMPTX_SPTN
#define ADC_SAMPTX_SPTN
Definition: gd32f3x0_adc.h:83
void adc_inserted_channel_offset_config | ( | uint8_t | inserted_channel,
 |  | uint16_t | offset
 | ) |  |

configure ADC inserted channel offset

Parameters
[in] inserted_channel insert channel select only one parameter can be selected
  • ADC_INSERTED_CHANNEL_0: ADC inserted channel 0
  • ADC_INSERTED_CHANNEL_1: ADC inserted channel 1
  • ADC_INSERTED_CHANNEL_2: ADC inserted channel 2
  • ADC_INSERTED_CHANNEL_3: ADC inserted channel 3
[in] | offset | the offset data
[out] | none
Return values
none

Definition at line 397 of file gd32f3x0_adc.c.

398 {
399 uint8_t inserted_length;
400 uint32_t num = 0U;
401
402 inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U);
403 num = 3U - (inserted_length - inserted_channel);
404
405 if(num <= 3U){
406 /* calculate the offset of the register */
407 num = num * 4U;
408 /* configure the offset of the selected channels */
409 REG32((ADC) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
410 }
411 }
ADC_ISQ
#define ADC_ISQ
Definition: gd32f3x0_adc.h:35
ADC
#define ADC
Definition: gd32f3x0_adc.h:18
IOFFX_IOFF
#define IOFFX_IOFF(regval)
Definition: gd32f3x0_adc.h:168
uint16_t adc_inserted_data_read ( uint8_t inserted_channel )

read ADC inserted group data register

Parameters
[in] inserted_channel inserted channel select only one parameter can be selected
  • ADC_INSERTED_CHANNEL_0: ADC inserted channel 0
  • ADC_INSERTED_CHANNEL_1: ADC inserted channel 1
  • ADC_INSERTED_CHANNEL_2: ADC inserted channel 2
  • ADC_INSERTED_CHANNEL_3: ADC inserted channel 3
[out] none
Return values
the conversion value

Definition at line 536 of file gd32f3x0_adc.c.

537 {
538 uint32_t idata;
539 /* read the data of the selected channel */
540 switch(inserted_channel){
541 case ADC_INSERTED_CHANNEL_0:
542 idata = ADC_IDATA0;
543 break;
544 case ADC_INSERTED_CHANNEL_1:
545 idata = ADC_IDATA1;
546 break;
547 case ADC_INSERTED_CHANNEL_2:
548 idata = ADC_IDATA2;
549 break;
550 case ADC_INSERTED_CHANNEL_3:
551 idata = ADC_IDATA3;
552 break;
553 default:
554 idata = 0U;
555 break;
556 }
557 return (uint16_t)idata;
558 }
ADC_IDATA2
#define ADC_IDATA2
Definition: gd32f3x0_adc.h:38
ADC_IDATA0
#define ADC_IDATA0
Definition: gd32f3x0_adc.h:36
ADC_INSERTED_CHANNEL_1
#define ADC_INSERTED_CHANNEL_1
Definition: gd32f3x0_adc.h:224
ADC_INSERTED_CHANNEL_3
#define ADC_INSERTED_CHANNEL_3
Definition: gd32f3x0_adc.h:226
ADC_IDATA3
#define ADC_IDATA3
Definition: gd32f3x0_adc.h:39
ADC_INSERTED_CHANNEL_0
#define ADC_INSERTED_CHANNEL_0
Definition: gd32f3x0_adc.h:223
ADC_IDATA1
#define ADC_IDATA1
Definition: gd32f3x0_adc.h:37
ADC_INSERTED_CHANNEL_2
#define ADC_INSERTED_CHANNEL_2
Definition: gd32f3x0_adc.h:225
void adc_interrupt_disable ( uint32_t interrupt )

disable ADC interrupt

Parameters
[in] interrupt the adc interrupt flag one or more parameters can be selected
  • ADC_INT_WDE: analog watchdog interrupt
  • ADC_INT_EOC: end of group conversion interrupt
  • ADC_INT_EOIC: end of inserted group conversion interrupt
[out] none
Return values
none

Definition at line 693 of file gd32f3x0_adc.c.

694 {
695 /* disable analog watchdog interrupt */
696 if(RESET != (interrupt & ADC_INT_WDE)){
697 ADC_CTL0 &= ~(uint32_t)ADC_CTL0_WDEIE;
698 }
699
700 /* disable end of group conversion interrupt */
701 if(RESET != (interrupt & ADC_INT_EOC)){
702 ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOCIE;
703 }
704
705 /* disable end of inserted group conversion interrupt */
706 if(RESET != (interrupt & ADC_INT_EOIC)){
707 ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOICIE;
708 }
709 }
ADC_INT_EOC
#define ADC_INT_EOC
Definition: gd32f3x0_adc.h:251
ADC_CTL0_WDEIE
#define ADC_CTL0_WDEIE
Definition: gd32f3x0_adc.h:54
ADC_INT_WDE
#define ADC_INT_WDE
Definition: gd32f3x0_adc.h:250
ADC_CTL0_EOICIE
#define ADC_CTL0_EOICIE
Definition: gd32f3x0_adc.h:55
ADC_INT_EOIC
#define ADC_INT_EOIC
Definition: gd32f3x0_adc.h:252
ADC_CTL0_EOCIE
#define ADC_CTL0_EOCIE
Definition: gd32f3x0_adc.h:53
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_interrupt_enable ( uint32_t interrupt )

enable ADC interrupt

Parameters
[in] interrupt the adc interrupt one or more parameters can be selected
  • ADC_INT_WDE: analog watchdog interrupt
  • ADC_INT_EOC: end of group conversion interrupt
  • ADC_INT_EOIC: end of inserted group conversion interrupt
[out] none
Return values
none

Definition at line 665 of file gd32f3x0_adc.c.

666 {
667 /* enable analog watchdog interrupt */
668 if(RESET != (interrupt & ADC_INT_WDE)){
669 ADC_CTL0 |= (uint32_t)ADC_CTL0_WDEIE;
670 }
671
672 /* enable end of group conversion interrupt */
673 if(RESET != (interrupt & ADC_INT_EOC)){
674 ADC_CTL0 |= (uint32_t)ADC_CTL0_EOCIE;
675 }
676
677 /* enable end of inserted group conversion interrupt */
678 if(RESET != (interrupt & ADC_INT_EOIC)){
679 ADC_CTL0 |= (uint32_t)ADC_CTL0_EOICIE;
680 }
681 }
ADC_INT_EOC
#define ADC_INT_EOC
Definition: gd32f3x0_adc.h:251
ADC_CTL0_WDEIE
#define ADC_CTL0_WDEIE
Definition: gd32f3x0_adc.h:54
ADC_INT_WDE
#define ADC_INT_WDE
Definition: gd32f3x0_adc.h:250
ADC_CTL0_EOICIE
#define ADC_CTL0_EOICIE
Definition: gd32f3x0_adc.h:55
ADC_INT_EOIC
#define ADC_INT_EOIC
Definition: gd32f3x0_adc.h:252
ADC_CTL0_EOCIE
#define ADC_CTL0_EOCIE
Definition: gd32f3x0_adc.h:53
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_interrupt_flag_clear ( uint32_t flag )

clear ADC interrupt flag

Parameters
[in] flag the adc interrupt flag only oneparameter can be selected
  • ADC_INT_FLAG_WDE: analog watchdog interrupt flag
  • ADC_INT_FLAG_EOC: end of group conversion interrupt flag
  • ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag
[out] none
Return values
none

Definition at line 650 of file gd32f3x0_adc.c.

651 {
652 ADC_STAT &= ~((uint32_t)flag);
653 }
ADC_STAT
#define ADC_STAT
Definition: gd32f3x0_adc.h:21
FlagStatus adc_interrupt_flag_get ( uint32_t flag )

get the ADC interrupt flag

Parameters
[in] flag the adc interrupt flag only oneparameter can be selected
  • ADC_INT_FLAG_WDE: analog watchdog interrupt flag
  • ADC_INT_FLAG_EOC: end of group conversion interrupt flag
  • ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 609 of file gd32f3x0_adc.c.

610 {
611 FlagStatus interrupt_flag = RESET;
612 uint32_t state;
613
614 /* check the interrupt bits */
615 switch(flag){
616 case ADC_INT_FLAG_WDE:
617 state = ADC_STAT & ADC_STAT_WDE;
618 if((ADC_CTL0 & ADC_CTL0_WDEIE) && state){
619 interrupt_flag = SET;
620 }
621 break;
622 case ADC_INT_FLAG_EOC:
623 state = ADC_STAT & ADC_STAT_EOC;
624 if((ADC_CTL0 & ADC_CTL0_EOCIE) && state){
625 interrupt_flag = SET;
626 }
627 break;
628 case ADC_INT_FLAG_EOIC:
629 state = ADC_STAT & ADC_STAT_EOIC;
630 if((ADC_CTL0 & ADC_CTL0_EOICIE) && state){
631 interrupt_flag = SET;
632 }
633 break;
634 default:
635 break;
636 }
637 return interrupt_flag;
638 }
ADC_STAT_WDE
#define ADC_STAT_WDE
Definition: gd32f3x0_adc.h:45
ADC_INT_FLAG_EOIC
#define ADC_INT_FLAG_EOIC
Definition: gd32f3x0_adc.h:257
ADC_INT_FLAG_EOC
#define ADC_INT_FLAG_EOC
Definition: gd32f3x0_adc.h:256
ADC_INT_FLAG_WDE
#define ADC_INT_FLAG_WDE
Definition: gd32f3x0_adc.h:255
ADC_CTL0_WDEIE
#define ADC_CTL0_WDEIE
Definition: gd32f3x0_adc.h:54
ADC_STAT_EOIC
#define ADC_STAT_EOIC
Definition: gd32f3x0_adc.h:47
ADC_STAT
#define ADC_STAT
Definition: gd32f3x0_adc.h:21
ADC_CTL0_EOICIE
#define ADC_CTL0_EOICIE
Definition: gd32f3x0_adc.h:55
ADC_STAT_EOC
#define ADC_STAT_EOC
Definition: gd32f3x0_adc.h:46
ADC_CTL0_EOCIE
#define ADC_CTL0_EOCIE
Definition: gd32f3x0_adc.h:53
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_oversample_mode_config | ( | uint8_t | mode,
 |  | uint16_t | shift,
 |  | uint8_t | ratio
 | ) |  |

configure ADC oversample mode

Parameters
[in] mode ADC oversampling mode only oneparameter can be selected
  • ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger
  • ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger
[in] shift ADC oversampling shift only oneparameter can be selected
  • ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift
  • ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift
  • ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift
  • ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift
  • ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift
  • ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift
  • ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift
  • ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift
  • ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift
[in] ratio ADC oversampling ratio only oneparameter can be selected
  • ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2
  • ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4
  • ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8
  • ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16
  • ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32
  • ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64
  • ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128
  • ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256
[out] none
Return values
none

Definition at line 811 of file gd32f3x0_adc.c.

812 {
813 /* configure ADC oversampling mode */
814 if(ADC_OVERSAMPLING_ONE_CONVERT == mode){
815 ADC_OVSAMPCTL |= (uint32_t)ADC_OVSAMPCTL_TOVS;
816 }else{
817 ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_TOVS);
818 }
819
820 /* configure the shift and ratio */
821 ADC_OVSAMPCTL &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS));
822 ADC_OVSAMPCTL |= ((uint32_t)shift | (uint32_t)ratio);
823 }
ADC_OVSAMPCTL_TOVS
#define ADC_OVSAMPCTL_TOVS
Definition: gd32f3x0_adc.h:112
ADC_OVSAMPCTL_OVSR
#define ADC_OVSAMPCTL_OVSR
Definition: gd32f3x0_adc.h:110
ADC_OVSAMPCTL_OVSS
#define ADC_OVSAMPCTL_OVSS
Definition: gd32f3x0_adc.h:111
ADC_OVERSAMPLING_ONE_CONVERT
#define ADC_OVERSAMPLING_ONE_CONVERT
Definition: gd32f3x0_adc.h:214
ADC_OVSAMPCTL
#define ADC_OVSAMPCTL
Definition: gd32f3x0_adc.h:41
void adc_oversample_mode_disable ( void )

disable ADC oversample mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 842 of file gd32f3x0_adc.c.

843 {
844 ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN);
845 }
ADC_OVSAMPCTL_OVSEN
#define ADC_OVSAMPCTL_OVSEN
Definition: gd32f3x0_adc.h:109
ADC_OVSAMPCTL
#define ADC_OVSAMPCTL
Definition: gd32f3x0_adc.h:41
void adc_oversample_mode_enable ( void )

enable ADC oversample mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 831 of file gd32f3x0_adc.c.

832 {
833 ADC_OVSAMPCTL |= ADC_OVSAMPCTL_OVSEN;
834 }
ADC_OVSAMPCTL_OVSEN
#define ADC_OVSAMPCTL_OVSEN
Definition: gd32f3x0_adc.h:109
ADC_OVSAMPCTL
#define ADC_OVSAMPCTL
Definition: gd32f3x0_adc.h:41
void adc_regular_channel_config | ( | uint8_t | rank,
 |  | uint8_t | channel,
 |  | uint32_t | sample_time
 | ) |  |

configure ADC regular channel

Parameters
[in] | rank | the regular group sequence rank, this parameter must be between 0 to 15
[in] channel the selected ADC channel only one among these parameters can be selected
  • ADC_CHANNEL_x(x=0..18): ADC Channelx
[in] sample_time the sample time value only one parameter can be selected
  • ADC_SAMPLETIME_1POINT5: 1.5 cycles
  • ADC_SAMPLETIME_7POINT5: 7.5 cycles
  • ADC_SAMPLETIME_13POINT5: 13.5 cycles
  • ADC_SAMPLETIME_28POINT5: 28.5 cycles
  • ADC_SAMPLETIME_41POINT5: 41.5 cycles
  • ADC_SAMPLETIME_55POINT5: 55.5 cycles
  • ADC_SAMPLETIME_71POINT5: 71.5 cycles
  • ADC_SAMPLETIME_239POINT5: 239.5 cycles
[out] | none
Return values
none

Definition at line 299 of file gd32f3x0_adc.c.

300 {
301 uint32_t rsq,sampt;
302
303 /* configure ADC regular sequence */
304 if(rank < 6U){
305 rsq = ADC_RSQ2;
306 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank)));
307 rsq |= ((uint32_t)channel << (5U*rank));
308 ADC_RSQ2 = rsq;
309 }else if(rank < 12U){
310 rsq = ADC_RSQ1;
311 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U))));
312 rsq |= ((uint32_t)channel << (5U*(rank-6U)));
313 ADC_RSQ1 = rsq;
314 }else if(rank < 16U){
315 rsq = ADC_RSQ0;
316 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U))));
317 rsq |= ((uint32_t)channel << (5U*(rank-12U)));
318 ADC_RSQ0 = rsq;
319 }else{
320 }
321
322 /* configure ADC sampling time */
323 if(channel < 10U){
324 sampt = ADC_SAMPT1;
325 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel)));
326 sampt |= (uint32_t)(sample_time << (3U*channel));
327 ADC_SAMPT1 = sampt;
328 }else if(channel < 19U){
329 sampt = ADC_SAMPT0;
330 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel-10U))));
331 sampt |= (uint32_t)(sample_time << (3U*(channel-10U)));
332 ADC_SAMPT0 = sampt;
333 }else{
334 /* illegal parameters */
335 }
336 }
ADC_SAMPT0
#define ADC_SAMPT0
Definition: gd32f3x0_adc.h:24
ADC_RSQ2
#define ADC_RSQ2
Definition: gd32f3x0_adc.h:34
ADC_RSQ1
#define ADC_RSQ1
Definition: gd32f3x0_adc.h:33
ADC_RSQX_RSQN
#define ADC_RSQX_RSQN
Definition: gd32f3x0_adc.h:95
ADC_RSQ0
#define ADC_RSQ0
Definition: gd32f3x0_adc.h:32
ADC_SAMPT1
#define ADC_SAMPT1
Definition: gd32f3x0_adc.h:25
ADC_SAMPTX_SPTN
#define ADC_SAMPTX_SPTN
Definition: gd32f3x0_adc.h:83
uint16_t adc_regular_data_read ( void )

read ADC regular group data register

Parameters
[in] | none
[out] | none
Return values
the conversion value

Definition at line 520 of file gd32f3x0_adc.c.

521 {
522 return ((uint16_t)ADC_RDATA);
523 }
ADC_RDATA
#define ADC_RDATA
Definition: gd32f3x0_adc.h:40
void adc_resolution_config ( uint32_t resolution )

configure ADC resolution

Parameters
[in] resolution ADC resolution only one among these parameters can be selected
  • ADC_RESOLUTION_12B: 12-bit ADC resolution
  • ADC_RESOLUTION_10B: 10-bit ADC resolution
  • ADC_RESOLUTION_8B: 8-bit ADC resolution
  • ADC_RESOLUTION_6B: 6-bit ADC resolution
[out] none
Return values
none

Definition at line 152 of file gd32f3x0_adc.c.

153 {
154 ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DRES);
155 ADC_CTL0 |= (uint32_t)resolution;
156 }
ADC_CTL0_DRES
#define ADC_CTL0_DRES
Definition: gd32f3x0_adc.h:64
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_software_trigger_enable ( uint8_t channel_group )

enable ADC software trigger

Parameters
[in] channel_group select the channel group one or more parameters can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[out] none
Return values
none

Definition at line 502 of file gd32f3x0_adc.c.

503 {
504 /* enable regular group channel software trigger */
505 if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
506 ADC_CTL1 |= ADC_CTL1_SWRCST;
507 }
508 /* enable inserted channel group software trigger */
509 if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
510 ADC_CTL1 |= ADC_CTL1_SWICST;
511 }
512 }
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f3x0_adc.h:217
ADC_CTL1_SWICST
#define ADC_CTL1_SWICST
Definition: gd32f3x0_adc.h:77
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:218
ADC_CTL1_SWRCST
#define ADC_CTL1_SWRCST
Definition: gd32f3x0_adc.h:78
void adc_special_function_config | ( | uint32_t | function,
 |  | ControlStatus | newvalue
 | ) |  |

configure ADC special function

Parameters
[in] function the function to configure one or more parameters can be selected below:
  • ADC_SCAN_MODE: scan mode select
  • ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
  • ADC_CONTINUOUS_MODE: continuous mode select
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 201 of file gd32f3x0_adc.c.

202 {
203 if(newvalue){
204 /* enable ADC scan mode */
205 if(RESET != (function & ADC_SCAN_MODE)){
206 ADC_CTL0 |= ADC_SCAN_MODE;
207 }
208 /* enable ADC inserted channel group convert automatically */
209 if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){
210 ADC_CTL0 |= ADC_INSERTED_CHANNEL_AUTO;
211 }
212 /* enable ADC continuous mode */
213 if(RESET != (function & ADC_CONTINUOUS_MODE)){
214 ADC_CTL1 |= ADC_CONTINUOUS_MODE;
215 }
216 }else{
217 /* disable ADC scan mode */
218 if(RESET != (function & ADC_SCAN_MODE)){
219 ADC_CTL0 &= ~ADC_SCAN_MODE;
220 }
221 /* disable ADC inserted channel group convert automatically */
222 if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){
223 ADC_CTL0 &= ~ADC_INSERTED_CHANNEL_AUTO;
224 }
225 /* disable ADC continuous mode */
226 if(RESET != (function & ADC_CONTINUOUS_MODE)){
227 ADC_CTL1 &= ~ADC_CONTINUOUS_MODE;
228 }
229 }
230 }
ADC_INSERTED_CHANNEL_AUTO
#define ADC_INSERTED_CHANNEL_AUTO
Definition: gd32f3x0_adc.h:127
ADC_CONTINUOUS_MODE
#define ADC_CONTINUOUS_MODE
Definition: gd32f3x0_adc.h:128
ADC_SCAN_MODE
#define ADC_SCAN_MODE
Definition: gd32f3x0_adc.h:126
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_tempsensor_vrefint_disable ( void )

disable the temperature sensor and Vrefint channel

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 111 of file gd32f3x0_adc.c.

112 {
113 /* disable the temperature sensor and Vrefint channel */
114 ADC_CTL1 &= ~ADC_CTL1_TSVREN;
115 }
ADC_CTL1_TSVREN
#define ADC_CTL1_TSVREN
Definition: gd32f3x0_adc.h:79
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_tempsensor_vrefint_enable ( void )

enable the temperature sensor and Vrefint channel

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 99 of file gd32f3x0_adc.c.

100 {
101 /* enable the temperature sensor and Vrefint channel */
102 ADC_CTL1 |= ADC_CTL1_TSVREN;
103 }
ADC_CTL1_TSVREN
#define ADC_CTL1_TSVREN
Definition: gd32f3x0_adc.h:79
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_vbat_disable ( void )

disable the vbat channel

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 135 of file gd32f3x0_adc.c.

136 {
137 /* disable the vbat channel */
138 ADC_CTL1 &= ~ADC_CTL1_VBETEN;
139 }
ADC_CTL1_VBETEN
#define ADC_CTL1_VBETEN
Definition: gd32f3x0_adc.h:80
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_vbat_enable ( void )

enable the vbat channel

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 123 of file gd32f3x0_adc.c.

124 {
125 /* enable the vbat channel */
126 ADC_CTL1 |= ADC_CTL1_VBETEN;
127 }
ADC_CTL1_VBETEN
#define ADC_CTL1_VBETEN
Definition: gd32f3x0_adc.h:80
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_watchdog_disable ( void )

disable ADC analog watchdog

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 763 of file gd32f3x0_adc.c.

764 {
765 ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
766 }
ADC_CTL0_IWDEN
#define ADC_CTL0_IWDEN
Definition: gd32f3x0_adc.h:62
ADC_CTL0_RWDEN
#define ADC_CTL0_RWDEN
Definition: gd32f3x0_adc.h:63
ADC_CTL0_WDSC
#define ADC_CTL0_WDSC
Definition: gd32f3x0_adc.h:57
ADC_CTL0_WDCHSEL
#define ADC_CTL0_WDCHSEL
Definition: gd32f3x0_adc.h:52
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_watchdog_group_channel_enable ( uint8_t channel_group )

configure ADC analog watchdog group channel

Parameters
[in] channel_group the channel group use analog watchdog only one parameter can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
  • ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
[out] none
Return values
none

Definition at line 737 of file gd32f3x0_adc.c.

738 {
739 ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
740
741 /* select the group */
742 switch(channel_group){
743 case ADC_REGULAR_CHANNEL:
744 ADC_CTL0 |= (uint32_t)ADC_CTL0_RWDEN;
745 break;
746 case ADC_INSERTED_CHANNEL:
747 ADC_CTL0 |= (uint32_t)ADC_CTL0_IWDEN;
748 break;
749 case ADC_REGULAR_INSERTED_CHANNEL:
750 ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
751 break;
752 default:
753 break;
754 }
755 }
ADC_CTL0_IWDEN
#define ADC_CTL0_IWDEN
Definition: gd32f3x0_adc.h:62
ADC_CTL0_RWDEN
#define ADC_CTL0_RWDEN
Definition: gd32f3x0_adc.h:63
ADC_CTL0_WDSC
#define ADC_CTL0_WDSC
Definition: gd32f3x0_adc.h:57
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f3x0_adc.h:217
ADC_REGULAR_INSERTED_CHANNEL
#define ADC_REGULAR_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:219
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:218
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_watchdog_single_channel_enable ( uint8_t channel )

configure ADC analog watchdog single channel

Parameters
[in] channel the selected ADC channel only one among these parameters can be selected
  • ADC_CHANNEL_x(x=0..18): ADC Channelx
[out] none
Return values
none

Definition at line 719 of file gd32f3x0_adc.c.

720 {
721 ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
722
723 ADC_CTL0 |= (uint32_t)channel;
724 ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
725 }
ADC_CTL0_IWDEN
#define ADC_CTL0_IWDEN
Definition: gd32f3x0_adc.h:62
ADC_CTL0_RWDEN
#define ADC_CTL0_RWDEN
Definition: gd32f3x0_adc.h:63
ADC_CTL0_WDSC
#define ADC_CTL0_WDSC
Definition: gd32f3x0_adc.h:57
ADC_CTL0_WDCHSEL
#define ADC_CTL0_WDCHSEL
Definition: gd32f3x0_adc.h:52
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_watchdog_threshold_config | ( | uint16_t | low_threshold,
 |  | uint16_t | high_threshold
 | ) |  |

configure ADC analog watchdog threshold

Parameters
[in] | low_threshold | analog watchdog low threshold,0..4095
[in] | high_threshold | analog watchdog high threshold,0..4095
[out] | none
Return values
none

Definition at line 775 of file gd32f3x0_adc.c.

776 {
777 ADC_WDLT = (uint32_t)WDLT_WDLT(low_threshold);
778 ADC_WDHT = (uint32_t)WDHT_WDHT(high_threshold);
779 }
ADC_WDLT
#define ADC_WDLT
Definition: gd32f3x0_adc.h:31
WDHT_WDHT
#define WDHT_WDHT(regval)
Definition: gd32f3x0_adc.h:171
WDLT_WDLT
#define WDLT_WDLT(regval)
Definition: gd32f3x0_adc.h:174
ADC_WDHT
#define ADC_WDHT
Definition: gd32f3x0_adc.h:30
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_cec.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_cec.h File Reference

definitions for the CEC More...

Go to the source code of this file.

Detailed Description

definitions for the CEC

Definition in file gd32f3x0_cec.h.

Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_cmp.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Enumerations | Functions
gd32f3x0_cmp.h File Reference

definitions for the CMP More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | CMP CMP_BASE
#define | CMP_CS REG32((CMP) + 0x00U)
#define | CMP_CS_CMP0EN BIT(0)
#define | CMP_CS_CMP0SW BIT(1)
#define | CMP_CS_CMP0M BITS(2,3)
#define | CMP_CS_CMP0MSEL BITS(4,6)
#define | CMP_CS_CMP0OSEL BITS(8,10)
#define | CMP_CS_CMP0PL BIT(11)
#define | CMP_CS_CMP0HST BITS(12,13)
#define | CMP_CS_CMP0O BIT(14)
#define | CMP_CS_CMP0LK BIT(15)
#define | CMP_CS_CMP1EN BIT(16)
#define | CMP_CS_CMP1M BITS(18,19)
#define | CMP_CS_CMP1MSEL BITS(20,22)
#define | CMP_CS_WNDEN BIT(23)
#define | CMP_CS_CMP1OSEL BITS(24,26)
#define | CMP_CS_CMP1PL BIT(27)
#define | CMP_CS_CMP1HST BITS(28,29)
#define | CMP_CS_CMP1O BIT(30)
#define | CMP_CS_CMP1LK BIT(31)
#define | CS_CMP0M(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
#define | CS_CMP0M_HIGHSPEED CS_CMP0M(0)
#define | CS_CMP0M_MIDDLESPEED CS_CMP0M(1)
#define | CS_CMP0M_LOWSPEED CS_CMP0M(2)
#define | CS_CMP0M_VERYLOWSPEED CS_CMP0M(3)
#define | CS_CMP0MSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
#define | CS_CMP0MSEL_1_4VREFINT CS_CMP0MSEL(0)
#define | CS_CMP0MSEL_1_2VREFINT CS_CMP0MSEL(1)
#define | CS_CMP0MSEL_3_4VREFINT CS_CMP0MSEL(2)
#define | CS_CMP0MSEL_VREFINT CS_CMP0MSEL(3)
#define | CS_CMP0MSEL_DAC CS_CMP0MSEL(4)
#define | CS_CMP0MSEL_PA5 CS_CMP0MSEL(5)
#define | CS_CMP0MSEL_PA0 CS_CMP0MSEL(6)
#define | CS_CMP0OSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
#define | CS_CMP0OSEL_OUTPUT_NONE CS_CMP0OSEL(0)
#define | CS_CMP0OSEL_OUTPUT_TIMER0BKIN CS_CMP0OSEL(1)
#define | CS_CMP0OSEL_OUTPUT_TIMER0IC0 CS_CMP0OSEL(2)
#define | CS_CMP0OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP0OSEL(3)
#define | CS_CMP0OSEL_OUTPUT_TIMER1IC3 CS_CMP0OSEL(4)
#define | CS_CMP0OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP0OSEL(5)
#define | CS_CMP0OSEL_OUTPUT_TIMER2IC0 CS_CMP0OSEL(6)
#define | CS_CMP0OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP0OSEL(7)
#define | CS_CMP0HST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
#define | CS_CMP0HST_HYSTERESIS_NO CS_CMP0HST(0)
#define | CS_CMP0HST_HYSTERESIS_LOW CS_CMP0HST(1)
#define | CS_CMP0HST_HYSTERESIS_MIDDLE CS_CMP0HST(2)
#define | CS_CMP0HST_HYSTERESIS_HIGH CS_CMP0HST(3)
#define | CS_CMP1M(regval) (BITS(18,19) & ((uint32_t)(regval) << 18))
#define | CS_CMP1M_HIGHSPEED CS_CMP1M(0)
#define | CS_CMP1M_MIDDLESPEED CS_CMP1M(1)
#define | CS_CMP1M_LOWSPEED CS_CMP1M(2)
#define | CS_CMP1M_VERYLOWSPEED CS_CMP1M(3)
#define | CS_CMP1MSEL(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
#define | CS_CMP1MSEL_1_4VREFINT CS_CMP1MSEL(0)
#define | CS_CMP1MSEL_1_2VREFINT CS_CMP1MSEL(1)
#define | CS_CMP1MSEL_3_4VREFINT CS_CMP1MSEL(2)
#define | CS_CMP1MSEL_VREFINT CS_CMP1MSEL(3)
#define | CS_CMP1MSEL_DAC CS_CMP1MSEL(4)
#define | CS_CMP1MSEL_PA5 CS_CMP1MSEL(5)
#define | CS_CMP1MSEL_PA2 CS_CMP1MSEL(6)
#define | CS_CMP1OSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
#define | CS_CMP1OSEL_OUTPUT_NONE CS_CMP1OSEL(0)
#define | CS_CMP1OSEL_OUTPUT_TIMER0BKIN CS_CMP1OSEL(1)
#define | CS_CMP1OSEL_OUTPUT_TIMER0IC0 CS_CMP1OSEL(2)
#define | CS_CMP1OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP1OSEL(3)
#define | CS_CMP1OSEL_OUTPUT_TIMER1IC3 CS_CMP1OSEL(4)
#define | CS_CMP1OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP1OSEL(5)
#define | CS_CMP1OSEL_OUTPUT_TIMER2IC0 CS_CMP1OSEL(6)
#define | CS_CMP1OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP1OSEL(7)
#define | CS_CMP1HST(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
#define | CS_CMP1HST_HSTHYSTERESIS_NO CS_CMP1HST(0)
#define | CS_CMP1HST_HYSTERESIS_LOW CS_CMP1HST(1)
#define | CS_CMP1HST_HYSTERESIS_MIDDLE CS_CMP1HST(2)
#define | CS_CMP1HST_HYSTERESIS_HIGH CS_CMP1HST(3)
#define | CMP0 ((uint32_t)0x00000000)
#define | CMP1 ((uint32_t)0x00000010)
#define | CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001)
#define | CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000)
#define | CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001)
#define | CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000)

Enumerations

enum | operating_mode_enum { CMP_HIGHSPEED = 0, CMP_MIDDLESPEED, CMP_LOWSPEED, CMP_VERYLOWSPEED }
enum inverting_input_enum {
CMP_1_4VREFINT = 0, CMP_1_2VREFINT, CMP_3_4VREFINT, CMP_VREFINT,
CMP_DAC, CMP_PA5, CMP_PA_0_2
}
enum | cmp_hysteresis_enum { CMP_HYSTERESIS_NO = 0, CMP_HYSTERESIS_LOW, CMP_HYSTERESIS_MIDDLE, CMP_HYSTERESIS_HIGH }
enum cmp_output_enum {
CMP_OUTPUT_NONE = 0, CMP_OUTPUT_TIMER0BKIN, CMP_OUTPUT_TIMER0IC0, CMP_OUTPUT_TIMER0OCPRECLR,
CMP_OUTPUT_TIMER1IC3, CMP_OUTPUT_TIMER1OCPRECLR, CMP_OUTPUT_TIMER2IC0, CMP_OUTPUT_TIMER2OCPRECLR
}

Functions

void | cmp_deinit (void)
deinitialize comparator More...
void | cmp_mode_init (uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis)
initialize comparator mode More...
void | cmp_output_init (uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity)
initialize comparator output More...
void | cmp_enable (uint32_t cmp_periph)
enable comparator More...
void | cmp_disable (uint32_t cmp_periph)
disable comparator More...
void | cmp_switch_enable (void)
enable comparator switch More...
void | cmp_switch_disable (void)
disable comparator switch More...
void | cmp_window_enable (void)
enable the window mode More...
void | cmp_window_disable (void)
disable the window mode More...
void | cmp_lock_enable (uint32_t cmp_periph)
lock the comparator More...
void | cmp_lock_disable (uint32_t cmp_periph)
unlock the comparator More...
uint32_t | cmp_output_level_get (uint32_t cmp_periph)
get output level More...

Detailed Description

definitions for the CMP

Definition in file gd32f3x0_cmp.h.

Macro Definition Documentation

#define CMP CMP_BASE

CMP base address

Definition at line 18 of file gd32f3x0_cmp.h.

#define CMP0 ((uint32_t)0x00000000)

comparator 0

Definition at line 154 of file gd32f3x0_cmp.h.

#define CMP1 ((uint32_t)0x00000010)

comparator 1

Definition at line 155 of file gd32f3x0_cmp.h.

#define CMP_CS REG32((CMP) + 0x00U)

CMP control and status register

Definition at line 21 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP0EN BIT(0)

CMP0 enable

Definition at line 24 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP0HST BITS(12,13)

CMP0 hysteresis

Definition at line 30 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP0LK BIT(15)

CMP0 lock

Definition at line 32 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP0M BITS(2,3)

CMP0 mode

Definition at line 26 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP0MSEL BITS(4,6)

COMP0_M input selection

Definition at line 27 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP0O BIT(14)

CMP0 output

Definition at line 31 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP0OSEL BITS(8,10)

CMP0 output selection

Definition at line 28 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP0PL BIT(11)

polarity of CMP0 output

Definition at line 29 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP0SW BIT(1)

CMP0 switch

Definition at line 25 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP1EN BIT(16)

CMP1 enable

Definition at line 33 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP1HST BITS(28,29)

CMP1 hysteresis

Definition at line 39 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP1LK BIT(31)

CMP1 lock

Definition at line 41 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP1M BITS(18,19)

CMP1 mode

Definition at line 34 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP1MSEL BITS(20,22)

CMP1_M input selection

Definition at line 35 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP1O BIT(30)

CMP1 output

Definition at line 40 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP1OSEL BITS(24,26)

CMP1 output selection

Definition at line 37 of file gd32f3x0_cmp.h.

#define CMP_CS_CMP1PL BIT(27)

polarity of CMP1 output

Definition at line 38 of file gd32f3x0_cmp.h.

#define CMP_CS_WNDEN BIT(23)

window mode enable

Definition at line 36 of file gd32f3x0_cmp.h.

#define CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001)

output is inverted

Definition at line 162 of file gd32f3x0_cmp.h.

#define CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000)

output is not inverted

Definition at line 163 of file gd32f3x0_cmp.h.

#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001)

comparator output high

Definition at line 158 of file gd32f3x0_cmp.h.

#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000)

comparator output low

Definition at line 159 of file gd32f3x0_cmp.h.

#define CS_CMP0HST ( regval ) (BITS(12,13) & ((uint32_t)(regval) << 12))

Definition at line 112 of file gd32f3x0_cmp.h.

#define CS_CMP0HST_HYSTERESIS_HIGH CS_CMP0HST(3)

CMP0 output high hysteresis

Definition at line 116 of file gd32f3x0_cmp.h.

#define CS_CMP0HST_HYSTERESIS_LOW CS_CMP0HST(1)

CMP0 output low hysteresis

Definition at line 114 of file gd32f3x0_cmp.h.

#define CS_CMP0HST_HYSTERESIS_MIDDLE CS_CMP0HST(2)

CMP0 output middle hysteresis

Definition at line 115 of file gd32f3x0_cmp.h.

#define CS_CMP0HST_HYSTERESIS_NO CS_CMP0HST(0)

CMP0 output no hysteresis

Definition at line 113 of file gd32f3x0_cmp.h.

#define CS_CMP0M ( regval ) (BITS(2,3) & ((uint32_t)(regval) << 2))

Definition at line 84 of file gd32f3x0_cmp.h.

#define CS_CMP0M_HIGHSPEED CS_CMP0M(0)

CMP0 mode high speed

Definition at line 85 of file gd32f3x0_cmp.h.

#define CS_CMP0M_LOWSPEED CS_CMP0M(2)

CMP0 mode low speed

Definition at line 87 of file gd32f3x0_cmp.h.

#define CS_CMP0M_MIDDLESPEED CS_CMP0M(1)

CMP0 mode middle speed

Definition at line 86 of file gd32f3x0_cmp.h.

#define CS_CMP0M_VERYLOWSPEED CS_CMP0M(3)

CMP0 mode very low speed

Definition at line 88 of file gd32f3x0_cmp.h.

#define CS_CMP0MSEL ( regval ) (BITS(4,6) & ((uint32_t)(regval) << 4))

Definition at line 91 of file gd32f3x0_cmp.h.

#define CS_CMP0MSEL_1_2VREFINT CS_CMP0MSEL(1)

CMP0 inverting input 1/2 Vrefint

Definition at line 93 of file gd32f3x0_cmp.h.

#define CS_CMP0MSEL_1_4VREFINT CS_CMP0MSEL(0)

CMP0 inverting input 1/4 Vrefint

Definition at line 92 of file gd32f3x0_cmp.h.

#define CS_CMP0MSEL_3_4VREFINT CS_CMP0MSEL(2)

CMP0 inverting input 3/4 Vrefint

Definition at line 94 of file gd32f3x0_cmp.h.

#define CS_CMP0MSEL_DAC CS_CMP0MSEL(4)

CMP0 inverting input DAC

Definition at line 96 of file gd32f3x0_cmp.h.

#define CS_CMP0MSEL_PA0 CS_CMP0MSEL(6)

CMP0 inverting input PA0

Definition at line 98 of file gd32f3x0_cmp.h.

#define CS_CMP0MSEL_PA5 CS_CMP0MSEL(5)

CMP0 inverting input PA5

Definition at line 97 of file gd32f3x0_cmp.h.

#define CS_CMP0MSEL_VREFINT CS_CMP0MSEL(3)

CMP0 inverting input Vrefint

Definition at line 95 of file gd32f3x0_cmp.h.

#define CS_CMP0OSEL ( regval ) (BITS(8,10) & ((uint32_t)(regval) << 8))

Definition at line 101 of file gd32f3x0_cmp.h.

#define CS_CMP0OSEL_OUTPUT_NONE CS_CMP0OSEL(0)

CMP0 output none

Definition at line 102 of file gd32f3x0_cmp.h.

#define CS_CMP0OSEL_OUTPUT_TIMER0BKIN CS_CMP0OSEL(1)

CMP0 output TIMER 0 break input

Definition at line 103 of file gd32f3x0_cmp.h.

#define CS_CMP0OSEL_OUTPUT_TIMER0IC0 CS_CMP0OSEL(2)

CMP0 output TIMER 0 channel 0 input capture

Definition at line 104 of file gd32f3x0_cmp.h.

#define CS_CMP0OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP0OSEL(3)

CMP0 output TIMER 0 ocpreclear input

Definition at line 105 of file gd32f3x0_cmp.h.

#define CS_CMP0OSEL_OUTPUT_TIMER1IC3 CS_CMP0OSEL(4)

CMP0 output TIMER 1 channel 3 input capture

Definition at line 106 of file gd32f3x0_cmp.h.

#define CS_CMP0OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP0OSEL(5)

CMP0 output TIMER 1 ocpreclear input

Definition at line 107 of file gd32f3x0_cmp.h.

#define CS_CMP0OSEL_OUTPUT_TIMER2IC0 CS_CMP0OSEL(6)

CMP0 output TIMER 2 channle 0 input capture

Definition at line 108 of file gd32f3x0_cmp.h.

#define CS_CMP0OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP0OSEL(7)

CMP0 output TIMER 2 ocpreclear input

Definition at line 109 of file gd32f3x0_cmp.h.

#define CS_CMP1HST ( regval ) (BITS(28,29) & ((uint32_t)(regval) << 28))

Definition at line 147 of file gd32f3x0_cmp.h.

#define CS_CMP1HST_HSTHYSTERESIS_NO CS_CMP1HST(0)

CMP1 output no hysteresis

Definition at line 148 of file gd32f3x0_cmp.h.

#define CS_CMP1HST_HYSTERESIS_HIGH CS_CMP1HST(3)

CMP1 output high hysteresis

Definition at line 151 of file gd32f3x0_cmp.h.

#define CS_CMP1HST_HYSTERESIS_LOW CS_CMP1HST(1)

CMP1 output low hysteresis

Definition at line 149 of file gd32f3x0_cmp.h.

#define CS_CMP1HST_HYSTERESIS_MIDDLE CS_CMP1HST(2)

CMP1 output middle hysteresis

Definition at line 150 of file gd32f3x0_cmp.h.

#define CS_CMP1M ( regval ) (BITS(18,19) & ((uint32_t)(regval) << 18))

Definition at line 119 of file gd32f3x0_cmp.h.

#define CS_CMP1M_HIGHSPEED CS_CMP1M(0)

CMP1 mode high speed

Definition at line 120 of file gd32f3x0_cmp.h.

#define CS_CMP1M_LOWSPEED CS_CMP1M(2)

CMP1 mode low speed

Definition at line 122 of file gd32f3x0_cmp.h.

#define CS_CMP1M_MIDDLESPEED CS_CMP1M(1)

CMP1 mode middle speed

Definition at line 121 of file gd32f3x0_cmp.h.

#define CS_CMP1M_VERYLOWSPEED CS_CMP1M(3)

CMP1 mode very low speed

Definition at line 123 of file gd32f3x0_cmp.h.

#define CS_CMP1MSEL ( regval ) (BITS(20,22) & ((uint32_t)(regval) << 20))

Definition at line 126 of file gd32f3x0_cmp.h.

#define CS_CMP1MSEL_1_2VREFINT CS_CMP1MSEL(1)

CMP1 inverting input 1/2 Vrefint

Definition at line 128 of file gd32f3x0_cmp.h.

#define CS_CMP1MSEL_1_4VREFINT CS_CMP1MSEL(0)

CMP1 inverting input 1/4 Vrefint

Definition at line 127 of file gd32f3x0_cmp.h.

#define CS_CMP1MSEL_3_4VREFINT CS_CMP1MSEL(2)

CMP1 inverting input 3/4 Vrefint

Definition at line 129 of file gd32f3x0_cmp.h.

#define CS_CMP1MSEL_DAC CS_CMP1MSEL(4)

CMP1 inverting input DAC

Definition at line 131 of file gd32f3x0_cmp.h.

#define CS_CMP1MSEL_PA2 CS_CMP1MSEL(6)

CMP1 inverting input PA2

Definition at line 133 of file gd32f3x0_cmp.h.

#define CS_CMP1MSEL_PA5 CS_CMP1MSEL(5)

CMP1 inverting input PA5

Definition at line 132 of file gd32f3x0_cmp.h.

#define CS_CMP1MSEL_VREFINT CS_CMP1MSEL(3)

CMP1 inverting input Vrefint

Definition at line 130 of file gd32f3x0_cmp.h.

#define CS_CMP1OSEL ( regval ) (BITS(24,26) & ((uint32_t)(regval) << 24))

Definition at line 136 of file gd32f3x0_cmp.h.

#define CS_CMP1OSEL_OUTPUT_NONE CS_CMP1OSEL(0)

CMP1 output none

Definition at line 137 of file gd32f3x0_cmp.h.

#define CS_CMP1OSEL_OUTPUT_TIMER0BKIN CS_CMP1OSEL(1)

CMP1 output TIMER 0 break input

Definition at line 138 of file gd32f3x0_cmp.h.

#define CS_CMP1OSEL_OUTPUT_TIMER0IC0 CS_CMP1OSEL(2)

CMP1 output TIMER 0 channel 0 input capture

Definition at line 139 of file gd32f3x0_cmp.h.

#define CS_CMP1OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP1OSEL(3)

CMP1 output TIMER 0 ocpreclear input

Definition at line 140 of file gd32f3x0_cmp.h.

#define CS_CMP1OSEL_OUTPUT_TIMER1IC3 CS_CMP1OSEL(4)

CMP1 output TIMER 1 channel 3 input capture

Definition at line 141 of file gd32f3x0_cmp.h.

#define CS_CMP1OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP1OSEL(5)

CMP1 output TIMER 1 ocpreclear input

Definition at line 142 of file gd32f3x0_cmp.h.

#define CS_CMP1OSEL_OUTPUT_TIMER2IC0 CS_CMP1OSEL(6)

CMP1 output TIMER 2 channle 0 input capture

Definition at line 143 of file gd32f3x0_cmp.h.

#define CS_CMP1OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP1OSEL(7)

CMP1 output TIMER 2 ocpreclear input

Definition at line 144 of file gd32f3x0_cmp.h.

Enumeration Type Documentation

enum cmp_hysteresis_enum
Enumerator
CMP_HYSTERESIS_NO | output no hysteresis
CMP_HYSTERESIS_LOW | output low hysteresis
CMP_HYSTERESIS_MIDDLE | output middle hysteresis
CMP_HYSTERESIS_HIGH | output high hysteresis

Definition at line 64 of file gd32f3x0_cmp.h.

64 {
65 CMP_HYSTERESIS_NO = 0,
66 CMP_HYSTERESIS_LOW,
67 CMP_HYSTERESIS_MIDDLE,
68 CMP_HYSTERESIS_HIGH
69 }cmp_hysteresis_enum;
CMP_HYSTERESIS_MIDDLE
Definition: gd32f3x0_cmp.h:67
CMP_HYSTERESIS_LOW
Definition: gd32f3x0_cmp.h:66
CMP_HYSTERESIS_NO
Definition: gd32f3x0_cmp.h:65
CMP_HYSTERESIS_HIGH
Definition: gd32f3x0_cmp.h:68
cmp_hysteresis_enum
cmp_hysteresis_enum
Definition: gd32f3x0_cmp.h:64
enum cmp_output_enum
Enumerator
CMP_OUTPUT_NONE | output no selection
CMP_OUTPUT_TIMER0BKIN | TIMER 0 break input
CMP_OUTPUT_TIMER0IC0 | TIMER 0 channel0 input capture
CMP_OUTPUT_TIMER0OCPRECLR | TIMER 0 OCPRE_CLR input
CMP_OUTPUT_TIMER1IC3 | TIMER 1 channel3 input capture
CMP_OUTPUT_TIMER1OCPRECLR | TIMER 1 OCPRE_CLR input
CMP_OUTPUT_TIMER2IC0 | TIMER 2 channel0 input capture
CMP_OUTPUT_TIMER2OCPRECLR | TIMER 2 OCPRE_CLR input

Definition at line 72 of file gd32f3x0_cmp.h.

72 {
73 CMP_OUTPUT_NONE = 0,
74 CMP_OUTPUT_TIMER0BKIN,
75 CMP_OUTPUT_TIMER0IC0,
76 CMP_OUTPUT_TIMER0OCPRECLR,
77 CMP_OUTPUT_TIMER1IC3,
78 CMP_OUTPUT_TIMER1OCPRECLR,
79 CMP_OUTPUT_TIMER2IC0,
80 CMP_OUTPUT_TIMER2OCPRECLR
81 }cmp_output_enum;
CMP_OUTPUT_NONE
Definition: gd32f3x0_cmp.h:73
CMP_OUTPUT_TIMER2IC0
Definition: gd32f3x0_cmp.h:79
CMP_OUTPUT_TIMER1IC3
Definition: gd32f3x0_cmp.h:77
CMP_OUTPUT_TIMER0IC0
Definition: gd32f3x0_cmp.h:75
CMP_OUTPUT_TIMER1OCPRECLR
Definition: gd32f3x0_cmp.h:78
CMP_OUTPUT_TIMER0OCPRECLR
Definition: gd32f3x0_cmp.h:76
CMP_OUTPUT_TIMER0BKIN
Definition: gd32f3x0_cmp.h:74
CMP_OUTPUT_TIMER2OCPRECLR
Definition: gd32f3x0_cmp.h:80
cmp_output_enum
cmp_output_enum
Definition: gd32f3x0_cmp.h:72
enum inverting_input_enum
Enumerator
CMP_1_4VREFINT | VREFINT /4 input
CMP_1_2VREFINT | VREFINT /2 input
CMP_3_4VREFINT | VREFINT *3/4 input
CMP_VREFINT | VREFINT input
CMP_DAC | PA4 (DAC) input
CMP_PA5 | PA5 input
CMP_PA_0_2 | PA0 or PA2 input

Definition at line 53 of file gd32f3x0_cmp.h.

53 {
54 CMP_1_4VREFINT = 0,
55 CMP_1_2VREFINT,
56 CMP_3_4VREFINT,
57 CMP_VREFINT,
58 CMP_DAC,
59 CMP_PA5,
60 CMP_PA_0_2
61 }inverting_input_enum;
CMP_VREFINT
Definition: gd32f3x0_cmp.h:57
CMP_PA5
Definition: gd32f3x0_cmp.h:59
CMP_DAC
Definition: gd32f3x0_cmp.h:58
CMP_1_2VREFINT
Definition: gd32f3x0_cmp.h:55
CMP_1_4VREFINT
Definition: gd32f3x0_cmp.h:54
CMP_3_4VREFINT
Definition: gd32f3x0_cmp.h:56
inverting_input_enum
inverting_input_enum
Definition: gd32f3x0_cmp.h:53
CMP_PA_0_2
Definition: gd32f3x0_cmp.h:60
enum operating_mode_enum
Enumerator
CMP_HIGHSPEED | high speed mode
CMP_MIDDLESPEED | medium speed mode
CMP_LOWSPEED | low speed mode
CMP_VERYLOWSPEED | very-low speed mode

Definition at line 45 of file gd32f3x0_cmp.h.

45 {
46 CMP_HIGHSPEED = 0,
47 CMP_MIDDLESPEED,
48 CMP_LOWSPEED,
49 CMP_VERYLOWSPEED
50 }operating_mode_enum;
CMP_HIGHSPEED
Definition: gd32f3x0_cmp.h:46
CMP_VERYLOWSPEED
Definition: gd32f3x0_cmp.h:49
operating_mode_enum
operating_mode_enum
Definition: gd32f3x0_cmp.h:45
CMP_LOWSPEED
Definition: gd32f3x0_cmp.h:48
CMP_MIDDLESPEED
Definition: gd32f3x0_cmp.h:47

Function Documentation

void cmp_deinit ( void )

deinitialize comparator

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_cmp.c.

21 {
22 CMP_CS = ((uint32_t)0x00000000U);
23 }
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
void cmp_disable ( uint32_t cmp_periph )

disable comparator

Parameters
[in] cmp_periph
  • CMP0: comparator 0
  • CMP1: comparator 1
[out] none
Return values
none

Definition at line 129 of file gd32f3x0_cmp.c.

130 {
131 if(CMP0 == cmp_periph){
132 CMP_CS &= ~CMP_CS_CMP0EN;
133 }else{
134 CMP_CS &= ~CMP_CS_CMP1EN;
135 }
136 }
CMP_CS_CMP0EN
#define CMP_CS_CMP0EN
Definition: gd32f3x0_cmp.h:24
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CMP_CS_CMP1EN
#define CMP_CS_CMP1EN
Definition: gd32f3x0_cmp.h:33
void cmp_enable ( uint32_t cmp_periph )

enable comparator

Parameters
[in] cmp_periph
  • CMP0: comparator 0
  • CMP1: comparator 1
[out] none
Return values
none

Definition at line 112 of file gd32f3x0_cmp.c.

113 {
114 if(CMP0 == cmp_periph){
115 CMP_CS |= CMP_CS_CMP0EN;
116 }else{
117 CMP_CS |= CMP_CS_CMP1EN;
118 }
119 }
CMP_CS_CMP0EN
#define CMP_CS_CMP0EN
Definition: gd32f3x0_cmp.h:24
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CMP_CS_CMP1EN
#define CMP_CS_CMP1EN
Definition: gd32f3x0_cmp.h:33
void cmp_lock_disable ( uint32_t cmp_periph )

unlock the comparator

Parameters
[in] cmp_periph
  • CMP0: comparator 0
  • CMP1: comparator 1
[out] none
Return values
none

Definition at line 232 of file gd32f3x0_cmp.c.

233 {
234 if(CMP0 == cmp_periph){
235 CMP_CS &= ~CMP_CS_CMP0LK;
236 }else{
237 CMP_CS &= ~CMP_CS_CMP1LK;
238 }
239 }
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
CMP_CS_CMP1LK
#define CMP_CS_CMP1LK
Definition: gd32f3x0_cmp.h:41
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CMP_CS_CMP0LK
#define CMP_CS_CMP0LK
Definition: gd32f3x0_cmp.h:32
void cmp_lock_enable ( uint32_t cmp_periph )

lock the comparator

Parameters
[in] cmp_periph
  • CMP0: comparator 0
  • CMP1: comparator 1
[out] none
Return values
none

Definition at line 215 of file gd32f3x0_cmp.c.

216 {
217 if(CMP0 == cmp_periph){
218 CMP_CS |= CMP_CS_CMP0LK;
219 }else{
220 CMP_CS |= CMP_CS_CMP1LK;
221 }
222 }
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
CMP_CS_CMP1LK
#define CMP_CS_CMP1LK
Definition: gd32f3x0_cmp.h:41
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CMP_CS_CMP0LK
#define CMP_CS_CMP0LK
Definition: gd32f3x0_cmp.h:32
void cmp_mode_init | ( | uint32_t | cmp_periph,
 |  | operating_mode_enum | operating_mode,
 |  | inverting_input_enum | inverting_input,
 |  | cmp_hysteresis_enum | output_hysteresis
 | ) |  |

initialize comparator mode

Parameters
[in] cmp_periph
  • CMP0: comparator 0
  • CMP1: comparator 1
[in] operating_mode
  • CMP_HIGHSPEED: high speed mode
  • CMP_MIDDLESPEED: medium speed mode
  • CMP_LOWSPEED: low speed mode
  • CMP_VERYLOWSPEED: very-low speed mode
[in] inverting_input
  • CMP_1_4VREFINT: VREFINT *1/4 input
  • CMP_1_2VREFINT: VREFINT *1/2 input
  • CMP_3_4VREFINT: VREFINT *3/4 input
  • CMP_VREFINT: VREFINT input
  • CMP_DAC: PA4 (DAC) input
  • CMP_PA5: PA5 input
  • CMP_PA_0_2: PA0 or PA2 input
[in] hysteresis
  • CMP_HYSTERESIS_NO: output no hysteresis
  • CMP_HYSTERESIS_LOW: output low hysteresis
  • CMP_HYSTERESIS_MIDDLE: output middle hysteresis
  • CMP_HYSTERESIS_HIGH: output high hysteresis
[out] none
Return values
none

Definition at line 51 of file gd32f3x0_cmp.c.

52 {
53 if(CMP0 == cmp_periph){
54 /* initialize comparator 0 mode */
55 CMP_CS |= CS_CMP0M(operating_mode) | CS_CMP0MSEL(inverting_input) | CS_CMP0HST(output_hysteresis);
56 }else{
57 /* initialize comparator 1 mode */
58 CMP_CS |= CS_CMP1M(operating_mode) | CS_CMP1MSEL(inverting_input) | CS_CMP1HST(output_hysteresis);
59 }
60 }
CS_CMP0MSEL
#define CS_CMP0MSEL(regval)
Definition: gd32f3x0_cmp.h:91
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CS_CMP1HST
#define CS_CMP1HST(regval)
Definition: gd32f3x0_cmp.h:147
CS_CMP0M
#define CS_CMP0M(regval)
Definition: gd32f3x0_cmp.h:84
CS_CMP1M
#define CS_CMP1M(regval)
Definition: gd32f3x0_cmp.h:119
CS_CMP0HST
#define CS_CMP0HST(regval)
Definition: gd32f3x0_cmp.h:112
CS_CMP1MSEL
#define CS_CMP1MSEL(regval)
Definition: gd32f3x0_cmp.h:126
void cmp_output_init | ( | uint32_t | cmp_periph,
 |  | cmp_output_enum | output_slection,
 |  | uint32_t | output_polarity
 | ) |  |

initialize comparator output

Parameters
[in] cmp_periph
  • CMP0: comparator 0
  • CMP1: comparator 1
[in] output_slection
  • CMP_OUTPUT_NONE: output no selection
  • CMP_OUTPUT_TIMER0BKIN: TIMER 0 break input
  • CMP_OUTPUT_TIMER0IC0: TIMER 0 channel0 input capture
  • CMP_OUTPUT_TIMER0OCPRECLR: TIMER 0 OCPRE_CLR input
  • CMP_OUTPUT_TIMER1IC3: TIMER 1 channel3 input capture
  • CMP_OUTPUT_TIMER1OCPRECLR: TIMER 1 OCPRE_CLR input
  • CMP_OUTPUT_TIMER2IC0: TIMER 2 channel0 input capture
  • CMP_OUTPUT_TIMER2OCPRECLR: TIMER 2 OCPRE_CLR input
[in] output_polarity
  • CMP_OUTPUT_POLARITY_INVERTED: output is inverted
  • CMP_OUTPUT_POLARITY_NOINVERTED: output is not inverted
[out] none
Return values
none

Definition at line 82 of file gd32f3x0_cmp.c.

83 {
84 /* initialize comparator 0 output */
85 if(CMP0 == cmp_periph){
86 CMP_CS |= CS_CMP0OSEL(output_slection);
87 /* output polarity */
88 if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
89 CMP_CS |= CMP_CS_CMP0PL;
90 }else{
91 CMP_CS &= ~CMP_CS_CMP0PL;
92 }
93 }else{
94 CMP_CS |= CS_CMP1OSEL(output_slection);
95
96 if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
97 CMP_CS |= CMP_CS_CMP1PL;
98 }else{
99 CMP_CS &= ~CMP_CS_CMP1PL;
100 }
101 }
102 }
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
CMP_CS_CMP0PL
#define CMP_CS_CMP0PL
Definition: gd32f3x0_cmp.h:29
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CS_CMP0OSEL
#define CS_CMP0OSEL(regval)
Definition: gd32f3x0_cmp.h:101
CMP_OUTPUT_POLARITY_INVERTED
#define CMP_OUTPUT_POLARITY_INVERTED
Definition: gd32f3x0_cmp.h:162
CMP_CS_CMP1PL
#define CMP_CS_CMP1PL
Definition: gd32f3x0_cmp.h:38
CS_CMP1OSEL
#define CS_CMP1OSEL(regval)
Definition: gd32f3x0_cmp.h:136
uint32_t cmp_output_level_get ( uint32_t cmp_periph )

get output level

Parameters
[in] cmp_periph
  • CMP0: comparator 0
  • CMP1: comparator 1
[out] none
Return values
the output level

Definition at line 168 of file gd32f3x0_cmp.c.

169 {
170 if(CMP0 == cmp_periph){
171 if(CMP_CS & CMP_CS_CMP0O){
172 return CMP_OUTPUTLEVEL_HIGH;
173 }else{
174 return CMP_OUTPUTLEVEL_LOW;
175 }
176 }else{
177 if(CMP_CS & CMP_CS_CMP1O){
178 return CMP_OUTPUTLEVEL_HIGH;
179 }else{
180 return CMP_OUTPUTLEVEL_LOW;
181 }
182 }
183 }
CMP_CS_CMP0O
#define CMP_CS_CMP0O
Definition: gd32f3x0_cmp.h:31
CMP_OUTPUTLEVEL_LOW
#define CMP_OUTPUTLEVEL_LOW
Definition: gd32f3x0_cmp.h:159
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
CMP_OUTPUTLEVEL_HIGH
#define CMP_OUTPUTLEVEL_HIGH
Definition: gd32f3x0_cmp.h:158
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CMP_CS_CMP1O
#define CMP_CS_CMP1O
Definition: gd32f3x0_cmp.h:40
void cmp_switch_disable ( void )

disable comparator switch

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 155 of file gd32f3x0_cmp.c.

156 {
157 CMP_CS &= ~CMP_CS_CMP0SW;
158 }
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CMP_CS_CMP0SW
#define CMP_CS_CMP0SW
Definition: gd32f3x0_cmp.h:25
void cmp_switch_enable ( void )

enable comparator switch

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 144 of file gd32f3x0_cmp.c.

145 {
146 CMP_CS |= CMP_CS_CMP0SW;
147 }
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CMP_CS_CMP0SW
#define CMP_CS_CMP0SW
Definition: gd32f3x0_cmp.h:25
void cmp_window_disable ( void )

disable the window mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 202 of file gd32f3x0_cmp.c.

203 {
204 CMP_CS &= ~CMP_CS_WNDEN;
205 }
CMP_CS_WNDEN
#define CMP_CS_WNDEN
Definition: gd32f3x0_cmp.h:36
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
void cmp_window_enable ( void )

enable the window mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 191 of file gd32f3x0_cmp.c.

192 {
193 CMP_CS |= CMP_CS_WNDEN;
194 }
CMP_CS_WNDEN
#define CMP_CS_WNDEN
Definition: gd32f3x0_cmp.h:36
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_crc.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Functions
gd32f3x0_crc.h File Reference

definitions for the CRC More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | CRC CRC_BASE
#define | CRC_DATA REG32((CRC) + 0x00U)
#define | CRC_FDATA REG32((CRC) + 0x04U)
#define | CRC_CTL REG32((CRC) + 0x08U)
#define | CRC_IDATA REG32((CRC) + 0x10U)
#define | CRC_POLY REG32((CRC) + 0x14U)
#define | CRC_DATA_DATA BITS(0,31)
#define | CRC_FDATA_FDATA BITS(0,7)
#define | CRC_CTL_RST BIT(0)
#define | CRC_CTL_PS BITS(3,4)
#define | CRC_CTL_REV_I BITS(5,6)
#define | CRC_CTL_REV_O BIT(7)
#define | CRC_IDATA_IDATA BITS(0,31)
#define | CRC_POLY_POLY BITS(0,31)
#define | CTL_PS(regval) (BITS(3, 4) & ((regval) << 3))
#define | CRC_CTL_PS_32 CTL_PS(0)
#define | CRC_CTL_PS_16 CTL_PS(1)
#define | CRC_CTL_PS_8 CTL_PS(2)
#define | CRC_CTL_PS_7 CTL_PS(3)
#define | CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5))
#define | CRC_INPUT_DATA_NOT CTL_REV_I(0)
#define | CRC_INPUT_DATA_BYTE CTL_REV_I(1)
#define | CRC_INPUT_DATA_HALFWORD CTL_REV_I(2)
#define | CRC_INPUT_DATA_WORD CTL_REV_I(3)

Functions

void | crc_deinit (void)
deinit CRC calculation unit More...
void | crc_reverse_output_data_enable (void)
enable the reverse operation of output data More...
void | crc_reverse_output_data_disable (void)
disable the reverse operation of output data More...
void | crc_data_register_reset (void)
reset data register to the value of initializaiton data register More...
uint32_t | crc_data_register_read (void)
read the data register More...
uint8_t | crc_free_data_register_read (void)
read the free data register More...
void | crc_free_data_register_write (uint8_t free_data)
write the free data register More...
void | crc_init_data_register_write (uint32_t init_data)
write the initializaiton data register More...
void | crc_input_data_reverse_config (uint32_t data_reverse)
configure the CRC input data function More...
void | crc_polynomial_size_set (uint32_t poly_size)
configure the CRC size of polynomial function More...
void | crc_polynomial_set (uint32_t poly)
configure the CRC polynomial value function More...
uint32_t | crc_single_data_calculate (uint32_t sdata)
CRC calculate a 32-bit data. More...
uint32_t | crc_block_data_calculate (uint32_t array[], uint32_t size)
CRC calculate a 32-bit data array. More...

Detailed Description

definitions for the CRC

Definition in file gd32f3x0_crc.h.

Macro Definition Documentation

#define CRC CRC_BASE

Definition at line 18 of file gd32f3x0_crc.h.

#define CRC_CTL REG32((CRC) + 0x08U)

CRC control register

Definition at line 23 of file gd32f3x0_crc.h.

#define CRC_CTL_PS BITS(3,4)

size of polynomial function bits

Definition at line 36 of file gd32f3x0_crc.h.

#define CRC_CTL_PS_16 CTL_PS(1)

16-bit polynomial for CRC calculation

Definition at line 50 of file gd32f3x0_crc.h.

#define CRC_CTL_PS_32 CTL_PS(0)

32-bit polynomial for CRC calculation

Definition at line 49 of file gd32f3x0_crc.h.

#define CRC_CTL_PS_7 CTL_PS(3)

7-bit polynomial for CRC calculation

Definition at line 52 of file gd32f3x0_crc.h.

#define CRC_CTL_PS_8 CTL_PS(2)

8-bit polynomial for CRC calculation

Definition at line 51 of file gd32f3x0_crc.h.

#define CRC_CTL_REV_I BITS(5,6)

input data reverse function bits

Definition at line 37 of file gd32f3x0_crc.h.

#define CRC_CTL_REV_O BIT(7)

output data reverse function bit

Definition at line 38 of file gd32f3x0_crc.h.

#define CRC_CTL_RST BIT(0)

CRC reset bit

Definition at line 35 of file gd32f3x0_crc.h.

#define CRC_DATA REG32((CRC) + 0x00U)

CRC data register

Definition at line 21 of file gd32f3x0_crc.h.

#define CRC_DATA_DATA BITS(0,31)

CRC data bits

Definition at line 29 of file gd32f3x0_crc.h.

#define CRC_FDATA REG32((CRC) + 0x04U)

CRC free data register

Definition at line 22 of file gd32f3x0_crc.h.

#define CRC_FDATA_FDATA BITS(0,7)

CRC free data bits

Definition at line 32 of file gd32f3x0_crc.h.

#define CRC_IDATA REG32((CRC) + 0x10U)

CRC initialization data register

Definition at line 24 of file gd32f3x0_crc.h.

#define CRC_IDATA_IDATA BITS(0,31)

CRC initialization data bits

Definition at line 41 of file gd32f3x0_crc.h.

#define CRC_INPUT_DATA_BYTE CTL_REV_I(1)

input data reversed by byte type

Definition at line 57 of file gd32f3x0_crc.h.

#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2)

input data reversed by half-word type

Definition at line 58 of file gd32f3x0_crc.h.

#define CRC_INPUT_DATA_NOT CTL_REV_I(0)

input data not reverse

Definition at line 56 of file gd32f3x0_crc.h.

#define CRC_INPUT_DATA_WORD CTL_REV_I(3)

input data reversed by word type

Definition at line 59 of file gd32f3x0_crc.h.

#define CRC_POLY REG32((CRC) + 0x14U)

CRC polynomial register

Definition at line 25 of file gd32f3x0_crc.h.

#define CRC_POLY_POLY BITS(0,31)

CRC polynomial value bits

Definition at line 44 of file gd32f3x0_crc.h.

#define CTL_PS ( regval ) (BITS(3, 4) & ((regval) << 3))

Definition at line 48 of file gd32f3x0_crc.h.

#define CTL_REV_I ( regval ) (BITS(5, 6) & ((regval) << 5))

Definition at line 55 of file gd32f3x0_crc.h.

Function Documentation

uint32_t crc_block_data_calculate | ( | uint32_t | array[],
 |  | uint32_t | size
 | ) |  |

CRC calculate a 32-bit data array.

Parameters
[in] | array | pointer to an array of 32 bit data words
[in] | size | size of the array
[out] | none
Return values
32-bit CRC calculate value

Definition at line 174 of file gd32f3x0_crc.c.

175 {
176 uint32_t index;
177 for(index = 0U; index < size; index++){
178 CRC_DATA = array[index];
179 }
180 return (CRC_DATA);
181 }
CRC_DATA
#define CRC_DATA
Definition: gd32f3x0_crc.h:21
uint32_t crc_data_register_read ( void )

read the data register

Parameters
[in] | none
[out] | none
Return values
32-bit value of the data register

Definition at line 69 of file gd32f3x0_crc.c.

70 {
71 uint32_t data;
72 data = CRC_DATA;
73 return (data);
74 }
CRC_DATA
#define CRC_DATA
Definition: gd32f3x0_crc.h:21
void crc_data_register_reset ( void )

reset data register to the value of initializaiton data register

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 58 of file gd32f3x0_crc.c.

59 {
60 CRC_CTL |= (uint32_t)CRC_CTL_RST;
61 }
CRC_CTL_RST
#define CRC_CTL_RST
Definition: gd32f3x0_crc.h:35
CRC_CTL
#define CRC_CTL
Definition: gd32f3x0_crc.h:23
void crc_deinit ( void )

deinit CRC calculation unit

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_crc.c.

21 {
22 CRC_IDATA = (uint32_t)0xFFFFFFFFU;
23 CRC_DATA = (uint32_t)0xFFFFFFFFU;
24 CRC_FDATA = (uint32_t)0x00000000U;
25 CRC_POLY = (uint32_t)0x04C11DB7U;
26 CRC_CTL = CRC_CTL_RST;
27 }
CRC_IDATA
#define CRC_IDATA
Definition: gd32f3x0_crc.h:24
CRC_DATA
#define CRC_DATA
Definition: gd32f3x0_crc.h:21
CRC_FDATA
#define CRC_FDATA
Definition: gd32f3x0_crc.h:22
CRC_POLY
#define CRC_POLY
Definition: gd32f3x0_crc.h:25
CRC_CTL_RST
#define CRC_CTL_RST
Definition: gd32f3x0_crc.h:35
CRC_CTL
#define CRC_CTL
Definition: gd32f3x0_crc.h:23
uint8_t crc_free_data_register_read ( void )

read the free data register

Parameters
[in] | none
[out] | none
Return values
8-bit value of the free data register

Definition at line 82 of file gd32f3x0_crc.c.

83 {
84 uint8_t fdata;
85 fdata = (uint8_t)CRC_FDATA;
86 return (fdata);
87 }
CRC_FDATA
#define CRC_FDATA
Definition: gd32f3x0_crc.h:22
void crc_free_data_register_write ( uint8_t free_data )

write the free data register

Parameters
[in] | free_data | specify 8-bit data
[out] | none
Return values
none

Definition at line 95 of file gd32f3x0_crc.c.

96 {
97 CRC_FDATA = (uint32_t)free_data;
98 }
CRC_FDATA
#define CRC_FDATA
Definition: gd32f3x0_crc.h:22
void crc_init_data_register_write ( uint32_t init_data )

write the initializaiton data register

Parameters
[in] | init_data:specify | 32-bit data
[out] | none
Return values
none

Definition at line 106 of file gd32f3x0_crc.c.

107 {
108 CRC_IDATA = (uint32_t)init_data;
109 }
CRC_IDATA
#define CRC_IDATA
Definition: gd32f3x0_crc.h:24
void crc_input_data_reverse_config ( uint32_t data_reverse )

configure the CRC input data function

Parameters
[in] data_reverse specify input data reverse function
  • CRC_INPUT_DATA_NOT: input data is not reversed
  • CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits
  • CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits
  • CRC_INPUT_DATA_WORD: input data is reversed on 32 bits
[out] none
Return values
none

Definition at line 121 of file gd32f3x0_crc.c.

122 {
123 CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I);
124 CRC_CTL |= (uint32_t)data_reverse;
125 }
CRC_CTL_REV_I
#define CRC_CTL_REV_I
Definition: gd32f3x0_crc.h:37
CRC_CTL
#define CRC_CTL
Definition: gd32f3x0_crc.h:23
void crc_polynomial_set ( uint32_t poly )

configure the CRC polynomial value function

Parameters
[in] | poly | configurable polynomial value
[out] | none
Return values
none

Definition at line 149 of file gd32f3x0_crc.c.

150 {
151 CRC_POLY &= (uint32_t)(~CRC_POLY_POLY);
152 CRC_POLY = poly;
153 }
CRC_POLY
#define CRC_POLY
Definition: gd32f3x0_crc.h:25
CRC_POLY_POLY
#define CRC_POLY_POLY
Definition: gd32f3x0_crc.h:44
void crc_polynomial_size_set ( uint32_t poly_size )

configure the CRC size of polynomial function

Parameters
[in] poly_size size of polynomial
  • CRC_CTL_PS_32: 32-bit polynomial for CRC calculation
  • CRC_CTL_PS_16: 16-bit polynomial for CRC calculation
  • CRC_CTL_PS_8: 8-bit polynomial for CRC calculation
  • CRC_CTL_PS_7: 7-bit polynomial for CRC calculation
[out] none
Return values
none

Definition at line 137 of file gd32f3x0_crc.c.

138 {
139 CRC_CTL &= (uint32_t)(~(CRC_CTL_PS));
140 CRC_CTL |= (uint32_t)poly_size;
141 }
CRC_CTL
#define CRC_CTL
Definition: gd32f3x0_crc.h:23
CRC_CTL_PS
#define CRC_CTL_PS
Definition: gd32f3x0_crc.h:36
void crc_reverse_output_data_disable ( void )

disable the reverse operation of output data

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 47 of file gd32f3x0_crc.c.

48 {
49 CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
50 }
CRC_CTL_REV_O
#define CRC_CTL_REV_O
Definition: gd32f3x0_crc.h:38
CRC_CTL
#define CRC_CTL
Definition: gd32f3x0_crc.h:23
void crc_reverse_output_data_enable ( void )

enable the reverse operation of output data

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 35 of file gd32f3x0_crc.c.

36 {
37 CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
38 CRC_CTL |= (uint32_t)CRC_CTL_REV_O;
39 }
CRC_CTL_REV_O
#define CRC_CTL_REV_O
Definition: gd32f3x0_crc.h:38
CRC_CTL
#define CRC_CTL
Definition: gd32f3x0_crc.h:23
uint32_t crc_single_data_calculate ( uint32_t sdata )

CRC calculate a 32-bit data.

Parameters
[in] | sdata | specify 32-bit data
[out] | none
Return values
32-bit CRC calculate value

Definition at line 161 of file gd32f3x0_crc.c.

162 {
163 CRC_DATA = sdata;
164 return(CRC_DATA);
165 }
CRC_DATA
#define CRC_DATA
Definition: gd32f3x0_crc.h:21
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_ctc.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Functions
gd32f3x0_ctc.h File Reference

definitions for the CTC More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | CTC CTC_BASE
#define | CTC_CTL0 REG32((CTC) + 0x00U)
#define | CTC_CTL1 REG32((CTC) + 0x04U)
#define | CTC_STAT REG32((CTC) + 0x08U)
#define | CTC_INTC REG32((CTC) + 0x0CU)
#define | CTC_CTL0_CKOKIE BIT(0)
#define | CTC_CTL0_CKWARNIE BIT(1)
#define | CTC_CTL0_ERRIE BIT(2)
#define | CTC_CTL0_EREFIE BIT(3)
#define | CTC_CTL0_CNTEN BIT(5)
#define | CTC_CTL0_AUTOTRIM BIT(6)
#define | CTC_CTL0_SWREFPUL BIT(7)
#define | CTC_CTL0_TRIMVALUE BITS(8,13)
#define | CTC_CTL1_RLVALUE BITS(0,15)
#define | CTC_CTL1_CKLIM BITS(16,23)
#define | CTC_CTL1_REFPSC BITS(24,26)
#define | CTC_CTL1_REFSEL BITS(28,29)
#define | CTC_CTL1_REFPOL BIT(31)
#define | CTC_STAT_CKOKIF BIT(0)
#define | CTC_STAT_CKWARNIF BIT(1)
#define | CTC_STAT_ERRIF BIT(2)
#define | CTC_STAT_EREFIF BIT(3)
#define | CTC_STAT_CKERR BIT(8)
#define | CTC_STAT_REFMISS BIT(9)
#define | CTC_STAT_TRIMERR BIT(10)
#define | CTC_STAT_REFDIR BIT(15)
#define | CTC_STAT_REFCAP BITS(16,31)
#define | CTC_INTC_CKOKIC BIT(0)
#define | CTC_INTC_CKWARNIC BIT(1)
#define | CTC_INTC_ERRIC BIT(2)
#define | CTC_INTC_EREFIC BIT(3)
#define | CTL0_TRIMVALUE(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
#define | CTL1_CKLIM(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
#define | GET_STAT_REFCAP(regval) GET_BITS((regval),16,31)
#define | GET_CTL0_TRIMVALUE(regval) GET_BITS((regval),8,13)
#define | CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM
#define | CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U)
#define | CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL
#define | CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U)
#define | CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
#define | CTC_REFSOURCE_GPIO CTL1_REFSEL(0)
#define | CTC_REFSOURCE_LXTAL CTL1_REFSEL(1)
#define | CTC_REFSOURCE_USBSOF CTL1_REFSEL(2)
#define | CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
#define | CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0)
#define | CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1)
#define | CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2)
#define | CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3)
#define | CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4)
#define | CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5)
#define | CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6)
#define | CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7)
#define | CTC_INT_CKOK CTC_CTL0_CKOKIE
#define | CTC_INT_CKWARN CTC_CTL0_CKWARNIE
#define | CTC_INT_ERR CTC_CTL0_ERRIE
#define | CTC_INT_EREF CTC_CTL0_EREFIE
#define | CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF
#define | CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF
#define | CTC_INT_FLAG_ERR CTC_STAT_ERRIF
#define | CTC_INT_FLAG_EREF CTC_STAT_EREFIF
#define | CTC_INT_FLAG_CKERR CTC_STAT_CKERR
#define | CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS
#define | CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR
#define | CTC_FLAG_CKOK CTC_STAT_CKOKIF
#define | CTC_FLAG_CKWARN CTC_STAT_CKWARNIF
#define | CTC_FLAG_ERR CTC_STAT_ERRIF
#define | CTC_FLAG_EREF CTC_STAT_EREFIF
#define | CTC_FLAG_CKERR CTC_STAT_CKERR
#define | CTC_FLAG_REFMISS CTC_STAT_REFMISS
#define | CTC_FLAG_TRIMERR CTC_STAT_TRIMERR

Functions

void | ctc_deinit (void)
reset CTC clock trim controller More...
void | ctc_interrupt_enable (uint32_t interrupt)
enable the CTC interrupt More...
void | ctc_interrupt_disable (uint32_t interrupt)
disable the CTC interrupt More...
FlagStatus | ctc_interrupt_flag_get (uint32_t interrupt)
get CTC interrupt flag More...
void | ctc_interrupt_flag_clear (uint32_t interrupt)
clear CTC interrupt flag More...
FlagStatus | ctc_flag_get (uint32_t flag)
get CTC flag More...
void | ctc_flag_clear (uint32_t flag)
clear CTC flag More...
void | ctc_irc48m_trim_value_config (uint8_t trim_value)
configure the IRC48M trim value More...
void | ctc_software_refsource_pulse_generate (void)
generate software reference source sync pulse More...
void | ctc_hardware_trim_mode_config (uint32_t hardmode)
configure hardware automatically trim mode More...
void | ctc_counter_enable (void)
enable CTC trim counter More...
void | ctc_counter_disable (void)
disable CTC trim counter More...
void | ctc_refsource_polarity_config (uint32_t polarity)
configure reference signal source polarity More...
void | ctc_refsource_signal_select (uint32_t refs)
select reference signal source More...
void | ctc_refsource_prescaler_config (uint32_t prescaler)
configure reference signal source prescaler More...
void | ctc_clock_limit_value_config (uint8_t limit_value)
configure clock trim base limit value More...
void | ctc_counter_reload_value_config (uint16_t reload_value)
configure CTC counter reload value More...
uint16_t | ctc_counter_capture_value_read (void)
read CTC counter capture value when reference sync pulse occurred More...
FlagStatus | ctc_counter_direction_read (void)
read CTC trim counter direction when reference sync pulse occurred More...
uint16_t | ctc_counter_reload_value_read (void)
read CTC counter reload value More...
uint8_t | ctc_irc48m_trim_value_read (void)
read the IRC48M trim value More...

Detailed Description

definitions for the CTC

Definition in file gd32f3x0_ctc.h.

Macro Definition Documentation

#define CTC CTC_BASE

Definition at line 18 of file gd32f3x0_ctc.h.

#define CTC_CTL0 REG32((CTC) + 0x00U)

CTC control register 0

Definition at line 21 of file gd32f3x0_ctc.h.

#define CTC_CTL0_AUTOTRIM BIT(6)

hardware automatically trim mode

Definition at line 33 of file gd32f3x0_ctc.h.

#define CTC_CTL0_CKOKIE BIT(0)

clock trim OK(CKOKIF) interrupt enable

Definition at line 28 of file gd32f3x0_ctc.h.

#define CTC_CTL0_CKWARNIE BIT(1)

clock trim warning(CKWARNIF) interrupt enable

Definition at line 29 of file gd32f3x0_ctc.h.

#define CTC_CTL0_CNTEN BIT(5)

CTC counter enable

Definition at line 32 of file gd32f3x0_ctc.h.

#define CTC_CTL0_EREFIE BIT(3)

EREFIF interrupt enable

Definition at line 31 of file gd32f3x0_ctc.h.

#define CTC_CTL0_ERRIE BIT(2)

error(ERRIF) interrupt enable

Definition at line 30 of file gd32f3x0_ctc.h.

#define CTC_CTL0_SWREFPUL BIT(7)

software reference source sync pulse

Definition at line 34 of file gd32f3x0_ctc.h.

#define CTC_CTL0_TRIMVALUE BITS(8,13)

IRC48M trim value

Definition at line 35 of file gd32f3x0_ctc.h.

#define CTC_CTL1 REG32((CTC) + 0x04U)

CTC control register 1

Definition at line 22 of file gd32f3x0_ctc.h.

#define CTC_CTL1_CKLIM BITS(16,23)

clock trim base limit value

Definition at line 39 of file gd32f3x0_ctc.h.

#define CTC_CTL1_REFPOL BIT(31)

reference signal source polarity

Definition at line 42 of file gd32f3x0_ctc.h.

#define CTC_CTL1_REFPSC BITS(24,26)

reference signal source prescaler

Definition at line 40 of file gd32f3x0_ctc.h.

#define CTC_CTL1_REFSEL BITS(28,29)

reference signal source selection

Definition at line 41 of file gd32f3x0_ctc.h.

#define CTC_CTL1_RLVALUE BITS(0,15)

CTC counter reload value

Definition at line 38 of file gd32f3x0_ctc.h.

#define CTC_FLAG_CKERR CTC_STAT_CKERR

clock trim error bit

Definition at line 112 of file gd32f3x0_ctc.h.

#define CTC_FLAG_CKOK CTC_STAT_CKOKIF

clock trim OK flag

Definition at line 108 of file gd32f3x0_ctc.h.

#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF

clock trim warning flag

Definition at line 109 of file gd32f3x0_ctc.h.

#define CTC_FLAG_EREF CTC_STAT_EREFIF

expect reference flag

Definition at line 111 of file gd32f3x0_ctc.h.

#define CTC_FLAG_ERR CTC_STAT_ERRIF

error flag

Definition at line 110 of file gd32f3x0_ctc.h.

#define CTC_FLAG_REFMISS CTC_STAT_REFMISS

reference sync pulse miss

Definition at line 113 of file gd32f3x0_ctc.h.

#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR

trim value error bit

Definition at line 114 of file gd32f3x0_ctc.h.

#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U)

hardware automatically trim mode disable

Definition at line 69 of file gd32f3x0_ctc.h.

#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM

hardware automatically trim mode enable

Definition at line 68 of file gd32f3x0_ctc.h.

#define CTC_INT_CKOK CTC_CTL0_CKOKIE

clock trim OK interrupt enable

Definition at line 93 of file gd32f3x0_ctc.h.

#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE

clock trim warning interrupt enable

Definition at line 94 of file gd32f3x0_ctc.h.

#define CTC_INT_EREF CTC_CTL0_EREFIE

expect reference interrupt enable

Definition at line 96 of file gd32f3x0_ctc.h.

#define CTC_INT_ERR CTC_CTL0_ERRIE

error interrupt enable

Definition at line 95 of file gd32f3x0_ctc.h.

#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR

clock trim error bit

Definition at line 103 of file gd32f3x0_ctc.h.

#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF

clock trim OK interrupt flag

Definition at line 99 of file gd32f3x0_ctc.h.

#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF

clock trim warning interrupt flag

Definition at line 100 of file gd32f3x0_ctc.h.

#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF

expect reference interrupt flag

Definition at line 102 of file gd32f3x0_ctc.h.

#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF

error interrupt flag

Definition at line 101 of file gd32f3x0_ctc.h.

#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS

reference sync pulse miss

Definition at line 104 of file gd32f3x0_ctc.h.

#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR

trim value error

Definition at line 105 of file gd32f3x0_ctc.h.

#define CTC_INTC REG32((CTC) + 0x0CU)

CTC interrupt clear register

Definition at line 24 of file gd32f3x0_ctc.h.

#define CTC_INTC_CKOKIC BIT(0)

CKOKIF interrupt clear bit

Definition at line 56 of file gd32f3x0_ctc.h.

#define CTC_INTC_CKWARNIC BIT(1)

CKWARNIF interrupt clear bit

Definition at line 57 of file gd32f3x0_ctc.h.

#define CTC_INTC_EREFIC BIT(3)

EREFIF interrupt clear bit

Definition at line 59 of file gd32f3x0_ctc.h.

#define CTC_INTC_ERRIC BIT(2)

ERRIF interrupt clear bit

Definition at line 58 of file gd32f3x0_ctc.h.

#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0)

GPIO is selected

Definition at line 77 of file gd32f3x0_ctc.h.

#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1)

LXTAL is clock selected

Definition at line 78 of file gd32f3x0_ctc.h.

#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL

reference signal source polarity is falling edge

Definition at line 72 of file gd32f3x0_ctc.h.

#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U)

reference signal source polarity is rising edge

Definition at line 73 of file gd32f3x0_ctc.h.

#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7)

reference signal divided by 128

Definition at line 90 of file gd32f3x0_ctc.h.

#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4)

reference signal divided by 16

Definition at line 87 of file gd32f3x0_ctc.h.

#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1)

reference signal divided by 2

Definition at line 84 of file gd32f3x0_ctc.h.

#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5)

reference signal divided by 32

Definition at line 88 of file gd32f3x0_ctc.h.

#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2)

reference signal divided by 4

Definition at line 85 of file gd32f3x0_ctc.h.

#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6)

reference signal divided by 64

Definition at line 89 of file gd32f3x0_ctc.h.

#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3)

reference signal divided by 8

Definition at line 86 of file gd32f3x0_ctc.h.

#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0)

reference signal not divided

Definition at line 83 of file gd32f3x0_ctc.h.

#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2)

USBFSSOF selected

Definition at line 79 of file gd32f3x0_ctc.h.

#define CTC_STAT REG32((CTC) + 0x08U)

CTC status register

Definition at line 23 of file gd32f3x0_ctc.h.

#define CTC_STAT_CKERR BIT(8)

clock trim error bit

Definition at line 49 of file gd32f3x0_ctc.h.

#define CTC_STAT_CKOKIF BIT(0)

clock trim OK interrupt flag

Definition at line 45 of file gd32f3x0_ctc.h.

#define CTC_STAT_CKWARNIF BIT(1)

clock trim warning interrupt flag

Definition at line 46 of file gd32f3x0_ctc.h.

#define CTC_STAT_EREFIF BIT(3)

expect reference interrupt flag

Definition at line 48 of file gd32f3x0_ctc.h.

#define CTC_STAT_ERRIF BIT(2)

error interrupt flag

Definition at line 47 of file gd32f3x0_ctc.h.

#define CTC_STAT_REFCAP BITS(16,31)

CTC counter capture when reference sync pulse occurred

Definition at line 53 of file gd32f3x0_ctc.h.

#define CTC_STAT_REFDIR BIT(15)

CTC trim counter direction when reference sync pulse occurred

Definition at line 52 of file gd32f3x0_ctc.h.

#define CTC_STAT_REFMISS BIT(9)

reference sync pulse miss

Definition at line 50 of file gd32f3x0_ctc.h.

#define CTC_STAT_TRIMERR BIT(10)

trim value error bit

Definition at line 51 of file gd32f3x0_ctc.h.

#define CTL0_TRIMVALUE ( regval ) (BITS(8,13) & ((uint32_t)(regval) << 8))

Definition at line 62 of file gd32f3x0_ctc.h.

#define CTL1_CKLIM ( regval ) (BITS(16,23) & ((uint32_t)(regval) << 16))

Definition at line 63 of file gd32f3x0_ctc.h.

#define CTL1_REFPSC ( regval ) (BITS(24,26) & ((uint32_t)(regval) << 24))

Definition at line 82 of file gd32f3x0_ctc.h.

#define CTL1_REFSEL ( regval ) (BITS(28,29) & ((uint32_t)(regval) << 28))

Definition at line 76 of file gd32f3x0_ctc.h.

#define GET_CTL0_TRIMVALUE ( regval ) GET_BITS((regval),8,13)

Definition at line 65 of file gd32f3x0_ctc.h.

#define GET_STAT_REFCAP ( regval ) GET_BITS((regval),16,31)

Definition at line 64 of file gd32f3x0_ctc.h.

Function Documentation

void ctc_clock_limit_value_config ( uint8_t limit_value )

configure clock trim base limit value

Parameters
[in] | limit_value | 8-bit clock trim base limit value
[out] | none
Return values
none

Definition at line 145 of file gd32f3x0_ctc.c.

146 {
147 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM);
148 CTC_CTL1 |= CTL1_CKLIM(limit_value);
149 }
CTC_CTL1_CKLIM
#define CTC_CTL1_CKLIM
Definition: gd32f3x0_ctc.h:39
CTC_CTL1
#define CTC_CTL1
Definition: gd32f3x0_ctc.h:22
CTL1_CKLIM
#define CTL1_CKLIM(regval)
Definition: gd32f3x0_ctc.h:63
uint16_t ctc_counter_capture_value_read ( void )

read CTC counter capture value when reference sync pulse occurred

Parameters
[in] | none
[out] | none
Return values
the 16-bit CTC counter capture value

Definition at line 169 of file gd32f3x0_ctc.c.

170 {
171 uint16_t capture_value = 0U;
172 capture_value = (uint16_t)GET_STAT_REFCAP(CTC_STAT);
173 return (capture_value);
174 }
GET_STAT_REFCAP
#define GET_STAT_REFCAP(regval)
Definition: gd32f3x0_ctc.h:64
CTC_STAT
#define CTC_STAT
Definition: gd32f3x0_ctc.h:23
FlagStatus ctc_counter_direction_read ( void )

read CTC trim counter direction when reference sync pulse occurred

Parameters
[in] | none
[out] | none
Return values
FlagStatus SET or RESET
  • SET: CTC trim counter direction is down-counting
  • RESET: CTC trim counter direction is up-counting

Definition at line 184 of file gd32f3x0_ctc.c.

185 {
186 FlagStatus ret_status = RESET;
187 if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){
188 ret_status = SET;
189 }
190 return ret_status;
191 }
CTC_STAT
#define CTC_STAT
Definition: gd32f3x0_ctc.h:23
CTC_STAT_REFDIR
#define CTC_STAT_REFDIR
Definition: gd32f3x0_ctc.h:52
void ctc_counter_disable ( void )

disable CTC trim counter

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 85 of file gd32f3x0_ctc.c.

86 {
87 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN);
88 }
CTC_CTL0_CNTEN
#define CTC_CTL0_CNTEN
Definition: gd32f3x0_ctc.h:32
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
void ctc_counter_enable ( void )

enable CTC trim counter

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 74 of file gd32f3x0_ctc.c.

75 {
76 CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN;
77 }
CTC_CTL0_CNTEN
#define CTC_CTL0_CNTEN
Definition: gd32f3x0_ctc.h:32
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
void ctc_counter_reload_value_config ( uint16_t reload_value )

configure CTC counter reload value

Parameters
[in] | reload_value | 16-bit CTC counter reload value
[out] | none
Return values
none

Definition at line 157 of file gd32f3x0_ctc.c.

158 {
159 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE);
160 CTC_CTL1 |= (uint32_t)reload_value;
161 }
CTC_CTL1_RLVALUE
#define CTC_CTL1_RLVALUE
Definition: gd32f3x0_ctc.h:38
CTC_CTL1
#define CTC_CTL1
Definition: gd32f3x0_ctc.h:22
uint16_t ctc_counter_reload_value_read ( void )

read CTC counter reload value

Parameters
[in] | none
[out] | none
Return values
the 16-bit CTC counter reload value

Definition at line 199 of file gd32f3x0_ctc.c.

200 {
201 uint16_t reload_value = 0U;
202 reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE);
203 return (reload_value);
204 }
CTC_CTL1_RLVALUE
#define CTC_CTL1_RLVALUE
Definition: gd32f3x0_ctc.h:38
CTC_CTL1
#define CTC_CTL1
Definition: gd32f3x0_ctc.h:22
void ctc_deinit ( void )

reset CTC clock trim controller

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 22 of file gd32f3x0_ctc.c.

23 {
24 /* reset CTC */
25 rcu_periph_reset_enable(RCU_CTCRST);
26 rcu_periph_reset_disable(RCU_CTCRST);
27 }
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
RCU_CTCRST
Definition: gd32f3x0_rcu.h:362
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
void ctc_flag_clear ( uint32_t flag )

clear CTC flag

Parameters
[in] flag the CTC flag
  • CTC_FLAG_CKOK: clock trim OK flag
  • CTC_FLAG_CKWARN: clock trim warning flag
  • CTC_FLAG_ERR: error flag
  • CTC_FLAG_EREF: expect reference flag
  • CTC_FLAG_CKERR: clock trim error bit
  • CTC_FLAG_REFMISS: reference sync pulse miss
  • CTC_FLAG_TRIMERR: trim value error bit
[out] none
Return values
none

Definition at line 338 of file gd32f3x0_ctc.c.

339 {
340 if(flag & CTC_FLAG_MASK){
341 CTC_INTC |= CTC_INTC_ERRIC;
342 }else{
343 CTC_INTC |= flag;
344 }
345 }
CTC_INTC
#define CTC_INTC
Definition: gd32f3x0_ctc.h:24
CTC_INTC_ERRIC
#define CTC_INTC_ERRIC
Definition: gd32f3x0_ctc.h:58
CTC_FLAG_MASK
#define CTC_FLAG_MASK
Definition: gd32f3x0_ctc.c:14
FlagStatus ctc_flag_get ( uint32_t flag )

get CTC flag

Parameters
[in] flag the CTC flag
  • CTC_FLAG_CKOK: clock trim OK flag
  • CTC_FLAG_CKWARN: clock trim warning flag
  • CTC_FLAG_ERR: error flag
  • CTC_FLAG_EREF: expect reference flag
  • CTC_FLAG_CKERR: clock trim error bit
  • CTC_FLAG_REFMISS: reference sync pulse miss
  • CTC_FLAG_TRIMERR: trim value error bit
[out] none
Return values
FlagStatus SET or RESET

Definition at line 315 of file gd32f3x0_ctc.c.

316 {
317 FlagStatus ret_status = RESET;
318
319 if(RESET != (CTC_STAT & flag)){
320 ret_status = SET;
321 }
322 return ret_status;
323 }
CTC_STAT
#define CTC_STAT
Definition: gd32f3x0_ctc.h:23
void ctc_hardware_trim_mode_config ( uint32_t hardmode )

configure hardware automatically trim mode

Parameters
[in] hardmode
  • CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable
  • CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable
[out] none
Return values
none

Definition at line 62 of file gd32f3x0_ctc.c.

63 {
64 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM);
65 CTC_CTL0 |= (uint32_t)hardmode;
66 }
CTC_CTL0_AUTOTRIM
#define CTC_CTL0_AUTOTRIM
Definition: gd32f3x0_ctc.h:33
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
void ctc_interrupt_disable ( uint32_t interrupt )

disable the CTC interrupt

Parameters
[in] interrupt CTC interrupt enable source
  • CTC_INT_CKOK: clock trim OK interrupt enable
  • CTC_INT_CKWARN: clock trim warning interrupt enable
  • CTC_INT_ERR: error interrupt enable
  • CTC_INT_EREF: expect reference interrupt enable
[out] none
Return values
none

Definition at line 244 of file gd32f3x0_ctc.c.

245 {
246 CTC_CTL0 &= (uint32_t)(~interrupt);
247 }
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
void ctc_interrupt_enable ( uint32_t interrupt )

enable the CTC interrupt

Parameters
[in] interrupt CTC interrupt enable
  • CTC_INT_CKOK: clock trim OK interrupt enable
  • CTC_INT_CKWARN: clock trim warning interrupt enable
  • CTC_INT_ERR: error interrupt enable
  • CTC_INT_EREF: expect reference interrupt enable
[out] none
Return values
none

Definition at line 229 of file gd32f3x0_ctc.c.

230 {
231 CTC_CTL0 |= (uint32_t)interrupt;
232 }
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
void ctc_interrupt_flag_clear ( uint32_t interrupt )

clear CTC interrupt flag

Parameters
[in] interrupt the CTC interrupt flag
  • CTC_INT_FLAG_CKOK: clock trim OK interrupt
  • CTC_INT_FLAG_CKWARN: clock trim warning interrupt
  • CTC_INT_FLAG_ERR: error interrupt
  • CTC_INT_FLAG_EREF: expect reference interrupt
  • CTC_INT_FLAG_CKERR: clock trim error bit interrupt
  • CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt
  • CTC_INT_FLAG_TRIMERR: trim value error interrupt
[out] none
Return values
none

Definition at line 293 of file gd32f3x0_ctc.c.

294 {
295 if(interrupt & CTC_FLAG_MASK){
296 CTC_INTC |= CTC_INTC_ERRIC;
297 }else{
298 CTC_INTC |= interrupt;
299 }
300 }
CTC_INTC
#define CTC_INTC
Definition: gd32f3x0_ctc.h:24
CTC_INTC_ERRIC
#define CTC_INTC_ERRIC
Definition: gd32f3x0_ctc.h:58
CTC_FLAG_MASK
#define CTC_FLAG_MASK
Definition: gd32f3x0_ctc.c:14
FlagStatus ctc_interrupt_flag_get ( uint32_t interrupt )

get CTC interrupt flag

Parameters
[in] interrupt the CTC interrupt flag
  • CTC_INT_FLAG_CKOK: clock trim OK interrupt
  • CTC_INT_FLAG_CKWARN: clock trim warning interrupt
  • CTC_INT_FLAG_ERR: error interrupt
  • CTC_INT_FLAG_EREF: expect reference interrupt
  • CTC_INT_FLAG_CKERR: clock trim error bit interrupt
  • CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt
  • CTC_INT_FLAG_TRIMERR: trim value error interrupt
[out] none
Return values
FlagStatus SET or RESET

Definition at line 262 of file gd32f3x0_ctc.c.

263 {
264 uint32_t ctc_int = 0U, intenable = 0U;
265 FlagStatus ret_status = RESET;
266
267 if(interrupt & CTC_FLAG_MASK){
268 intenable = CTC_CTL0 & CTC_INT_ERR;
269 }else{
270 intenable = CTC_CTL0 & interrupt;
271 }
272 ctc_int = CTC_STAT & interrupt;
273
274 if(ctc_int && intenable){
275 ret_status = SET;
276 }
277 return ret_status;
278 }
CTC_STAT
#define CTC_STAT
Definition: gd32f3x0_ctc.h:23
CTC_FLAG_MASK
#define CTC_FLAG_MASK
Definition: gd32f3x0_ctc.c:14
CTC_INT_ERR
#define CTC_INT_ERR
Definition: gd32f3x0_ctc.h:95
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
void ctc_irc48m_trim_value_config ( uint8_t trim_value )

configure the IRC48M trim value

Parameters
[in] | trim_value | 8-bit IRC48M trim value
[out] | none
Return values
none

Definition at line 35 of file gd32f3x0_ctc.c.

36 {
37 /* clear TRIMVALUE bits */
38 CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE);
39 /* set TRIMVALUE bits */
40 CTC_CTL0 |= CTL0_TRIMVALUE(trim_value);
41 }
CTC_CTL0_TRIMVALUE
#define CTC_CTL0_TRIMVALUE
Definition: gd32f3x0_ctc.h:35
CTL0_TRIMVALUE
#define CTL0_TRIMVALUE(regval)
Definition: gd32f3x0_ctc.h:62
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
uint8_t ctc_irc48m_trim_value_read ( void )

read the IRC48M trim value

Parameters
[in] | none
[out] | none
Return values
the 8-bit IRC48M trim value

Definition at line 212 of file gd32f3x0_ctc.c.

213 {
214 uint8_t trim_value = 0U;
215 trim_value = (uint8_t)GET_CTL0_TRIMVALUE(CTC_CTL0);
216 return (trim_value);
217 }
GET_CTL0_TRIMVALUE
#define GET_CTL0_TRIMVALUE(regval)
Definition: gd32f3x0_ctc.h:65
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
void ctc_refsource_polarity_config ( uint32_t polarity )

configure reference signal source polarity

Parameters
[in] polarity
  • CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge
  • CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge
[out] none
Return values
none

Definition at line 98 of file gd32f3x0_ctc.c.

99 {
100 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL);
101 CTC_CTL1 |= (uint32_t)polarity;
102 }
CTC_CTL1
#define CTC_CTL1
Definition: gd32f3x0_ctc.h:22
CTC_CTL1_REFPOL
#define CTC_CTL1_REFPOL
Definition: gd32f3x0_ctc.h:42
void ctc_refsource_prescaler_config ( uint32_t prescaler )

configure reference signal source prescaler

Parameters
[in] prescaler
  • CTC_REFSOURCE_PSC_OFF: reference signal not divided
  • CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2
  • CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4
  • CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8
  • CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16
  • CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32
  • CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64
  • CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128
[out] none
Return values
none

Definition at line 133 of file gd32f3x0_ctc.c.

134 {
135 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC);
136 CTC_CTL1 |= (uint32_t)prescaler;
137 }
CTC_CTL1
#define CTC_CTL1
Definition: gd32f3x0_ctc.h:22
CTC_CTL1_REFPSC
#define CTC_CTL1_REFPSC
Definition: gd32f3x0_ctc.h:40
void ctc_refsource_signal_select ( uint32_t refs )

select reference signal source

Parameters
[in] refs
  • CTC_REFSOURCE_GPIO: GPIO is selected
  • CTC_REFSOURCE_LXTAL: LXTAL is clock selected
  • CTC_REFSOURCE_USBSOF: USBSOF is selected
[out] none
Return values
none

Definition at line 113 of file gd32f3x0_ctc.c.

114 {
115 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL);
116 CTC_CTL1 |= (uint32_t)refs;
117 }
CTC_CTL1_REFSEL
#define CTC_CTL1_REFSEL
Definition: gd32f3x0_ctc.h:41
CTC_CTL1
#define CTC_CTL1
Definition: gd32f3x0_ctc.h:22
void ctc_software_refsource_pulse_generate ( void )

generate software reference source sync pulse

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 49 of file gd32f3x0_ctc.c.

50 {
51 CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL;
52 }
CTC_CTL0_SWREFPUL
#define CTC_CTL0_SWREFPUL
Definition: gd32f3x0_ctc.h:34
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_dac.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_dac.h File Reference

definitions for the DAC More...

Go to the source code of this file.

Detailed Description

definitions for the DAC

Definition in file gd32f3x0_dac.h.

Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_dbg.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Enumerations | Functions
gd32f3x0_dbg.h File Reference

definitions for the DBG More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | DBG DBG_BASE
#define | DBG_ID REG32(DBG + 0x00U)
#define | DBG_CTL0 REG32(DBG + 0x04U)
#define | DBG_CTL1 REG32(DBG + 0x08U)
#define | DBG_ID_ID_CODE BITS(0,31)
#define | DBG_CTL0_SLP_HOLD BIT(0)
#define | DBG_CTL0_DSLP_HOLD BIT(1)
#define | DBG_CTL0_STB_HOLD BIT(2)
#define | DBG_CTL0_FWDGT_HOLD BIT(8)
#define | DBG_CTL0_WWDGT_HOLD BIT(9)
#define | DBG_CTL0_TIMER0_HOLD BIT(10)
#define | DBG_CTL0_TIMER1_HOLD BIT(11)
#define | DBG_CTL0_TIMER2_HOLD BIT(12)
#define | DBG_CTL0_I2C0_HOLD BIT(15)
#define | DBG_CTL0_I2C1_HOLD BIT(16)
#define | DBG_CTL0_I2C2_HOLD BIT(17)
#define | DBG_CTL0_TIMER13_HOLD BIT(27)
#define | DBG_CTL1_RTC_HOLD BIT(10)
#define | DBG_CTL1_TIMER14_HOLD BIT(16)
#define | DBG_CTL1_TIMER15_HOLD BIT(17)
#define | DBG_CTL1_TIMER16_HOLD BIT(18)
#define | DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD
#define | DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD
#define | DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD
#define | DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
#define | DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
#define | DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU)

Enumerations

enum dbg_reg_idx { DBG_IDX_CTL0 = 0x04U, DBG_IDX_CTL1 = 0x08U }
enum dbg_periph_enum {
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 11U),
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U),
DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 17U),
DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U)
}

Functions

void | dbg_deinit (void)
deinitialize the DBG More...
uint32_t | dbg_id_get (void)
read DBG_ID code register More...
void | dbg_low_power_enable (uint32_t dbg_low_power)
enable low power behavior when the mcu is in debug mode More...
void | dbg_low_power_disable (uint32_t dbg_low_power)
disable low power behavior when the mcu is in debug mode More...
void | dbg_periph_enable (dbg_periph_enum dbg_periph)
enable peripheral behavior when the mcu is in debug mode More...
void | dbg_periph_disable (dbg_periph_enum dbg_periph)
disable peripheral behavior when the mcu is in debug mode More...

Detailed Description

definitions for the DBG

Definition in file gd32f3x0_dbg.h.

Macro Definition Documentation

#define DBG DBG_BASE

Definition at line 18 of file gd32f3x0_dbg.h.

#define DBG_BIT_POS ( val ) ((uint32_t)(val) & 0x1FU)

Definition at line 60 of file gd32f3x0_dbg.h.

#define DBG_CTL0 REG32(DBG + 0x04U)

DBG control register 0

Definition at line 22 of file gd32f3x0_dbg.h.

#define DBG_CTL0_DSLP_HOLD BIT(1)

keep debugger connection during deepsleep mode

Definition at line 31 of file gd32f3x0_dbg.h.

#define DBG_CTL0_FWDGT_HOLD BIT(8)

debug FWDGT kept when core is halted

Definition at line 33 of file gd32f3x0_dbg.h.

#define DBG_CTL0_I2C0_HOLD BIT(15)

hold I2C0 smbus when core is halted

Definition at line 38 of file gd32f3x0_dbg.h.

#define DBG_CTL0_I2C1_HOLD BIT(16)

hold I2C1 smbus when core is halted

Definition at line 39 of file gd32f3x0_dbg.h.

#define DBG_CTL0_I2C2_HOLD BIT(17)

hold I2C2 smbus when core is halted

Definition at line 40 of file gd32f3x0_dbg.h.

#define DBG_CTL0_SLP_HOLD BIT(0)

keep debugger connection during sleep mode

Definition at line 30 of file gd32f3x0_dbg.h.

#define DBG_CTL0_STB_HOLD BIT(2)

keep debugger connection during standby mode

Definition at line 32 of file gd32f3x0_dbg.h.

#define DBG_CTL0_TIMER0_HOLD BIT(10)

TIMER0 counter kept when core is halted

Definition at line 35 of file gd32f3x0_dbg.h.

#define DBG_CTL0_TIMER13_HOLD BIT(27)

hold TIMER13 counter when core is halted

Definition at line 44 of file gd32f3x0_dbg.h.

#define DBG_CTL0_TIMER1_HOLD BIT(11)

TIMER1 counter kept when core is halted

Definition at line 36 of file gd32f3x0_dbg.h.

#define DBG_CTL0_TIMER2_HOLD BIT(12)

TIMER2 counter kept when core is halted

Definition at line 37 of file gd32f3x0_dbg.h.

#define DBG_CTL0_WWDGT_HOLD BIT(9)

debug WWDGT kept when core is halted

Definition at line 34 of file gd32f3x0_dbg.h.

#define DBG_CTL1 REG32(DBG + 0x08U)

DBG control register 1

Definition at line 23 of file gd32f3x0_dbg.h.

#define DBG_CTL1_RTC_HOLD BIT(10)

hold RTC calendar and wakeup counter when core is halted

Definition at line 47 of file gd32f3x0_dbg.h.

#define DBG_CTL1_TIMER14_HOLD BIT(16)

hold TIMER14 counter when core is halted

Definition at line 48 of file gd32f3x0_dbg.h.

#define DBG_CTL1_TIMER15_HOLD BIT(17)

hold TIMER15 counter when core is halted

Definition at line 49 of file gd32f3x0_dbg.h.

#define DBG_CTL1_TIMER16_HOLD BIT(18)

hold TIMER16 counter when core is halted

Definition at line 50 of file gd32f3x0_dbg.h.

#define DBG_ID REG32(DBG + 0x00U)

DBG_ID code register

Definition at line 21 of file gd32f3x0_dbg.h.

#define DBG_ID_ID_CODE BITS(0,31)

DBG ID code values

Definition at line 27 of file gd32f3x0_dbg.h.

#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD

keep debugger connection during deepsleep mode

Definition at line 54 of file gd32f3x0_dbg.h.

#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD

keep debugger connection during sleep mode

Definition at line 53 of file gd32f3x0_dbg.h.

#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD

keep debugger connection during standby mode

Definition at line 55 of file gd32f3x0_dbg.h.

#define DBG_REG_VAL ( periph ) (REG32(DBG + ((uint32_t)(periph) >> 6)))

Definition at line 59 of file gd32f3x0_dbg.h.

#define DBG_REGIDX_BIT | ( | regidx,
 |  | bitpos
 | ) | (((regidx) << 6) | (bitpos))

Definition at line 58 of file gd32f3x0_dbg.h.

Enumeration Type Documentation

enum dbg_periph_enum
Enumerator
DBG_FWDGT_HOLD | FWDGT hold bit
DBG_WWDGT_HOLD | WWDGT hold bit
DBG_TIMER0_HOLD | TIMER0 hold bit
DBG_TIMER1_HOLD | TIMER1 hold bit
DBG_TIMER2_HOLD | TIMER2 hold bit
DBG_TIMER13_HOLD | TIMER13 hold bit
DBG_TIMER14_HOLD | TIMER14 hold bit
DBG_TIMER15_HOLD | TIMER15 hold bit
DBG_TIMER16_HOLD | TIMER16 hold bit
DBG_I2C0_HOLD | I2C0 hold bit
DBG_I2C1_HOLD | I2C1 hold bit
DBG_I2C2_HOLD | I2C2 hold bit
DBG_RTC_HOLD | RTC hold bit

Definition at line 70 of file gd32f3x0_dbg.h.

71 {
72 DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U),
73 DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U),
74 DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U),
75 DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 11U),
76 DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U),
77 #ifdef GD32F350
78 DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U),
79 #endif /* GD32F350 */
80 DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U),
81 DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U),
82 DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U),
83 DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U),
84 DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U),
85 DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U),
86 DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 17U),
87 DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U),
88 }dbg_periph_enum;
DBG_I2C1_HOLD
Definition: gd32f3x0_dbg.h:85
dbg_periph_enum
dbg_periph_enum
Definition: gd32f3x0_dbg.h:70
DBG_I2C0_HOLD
Definition: gd32f3x0_dbg.h:84
DBG_TIMER16_HOLD
Definition: gd32f3x0_dbg.h:83
DBG_TIMER2_HOLD
Definition: gd32f3x0_dbg.h:76
DBG_RTC_HOLD
Definition: gd32f3x0_dbg.h:87
DBG_WWDGT_HOLD
Definition: gd32f3x0_dbg.h:73
DBG_IDX_CTL0
Definition: gd32f3x0_dbg.h:65
DBG_TIMER14_HOLD
Definition: gd32f3x0_dbg.h:81
DBG_IDX_CTL1
Definition: gd32f3x0_dbg.h:66
DBG_FWDGT_HOLD
Definition: gd32f3x0_dbg.h:72
DBG_TIMER15_HOLD
Definition: gd32f3x0_dbg.h:82
DBG_TIMER1_HOLD
Definition: gd32f3x0_dbg.h:75
DBG_I2C2_HOLD
Definition: gd32f3x0_dbg.h:86
DBG_TIMER13_HOLD
Definition: gd32f3x0_dbg.h:80
DBG_TIMER0_HOLD
Definition: gd32f3x0_dbg.h:74
DBG_REGIDX_BIT
#define DBG_REGIDX_BIT(regidx, bitpos)
Definition: gd32f3x0_dbg.h:58
enum dbg_reg_idx
Enumerator
DBG_IDX_CTL0
DBG_IDX_CTL1

Definition at line 63 of file gd32f3x0_dbg.h.

64 {
65 DBG_IDX_CTL0 = 0x04U,
66 DBG_IDX_CTL1 = 0x08U,
67 };
DBG_IDX_CTL0
Definition: gd32f3x0_dbg.h:65
DBG_IDX_CTL1
Definition: gd32f3x0_dbg.h:66

Function Documentation

void dbg_deinit ( void )

deinitialize the DBG

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 22 of file gd32f3x0_dbg.c.

23 {
24 DBG_CTL0 = DBG_RESET_VAL;
25 DBG_CTL1 = DBG_RESET_VAL;
26 }
DBG_RESET_VAL
#define DBG_RESET_VAL
Definition: gd32f3x0_dbg.c:14
DBG_CTL1
#define DBG_CTL1
Definition: gd32f3x0_dbg.h:23
DBG_CTL0
#define DBG_CTL0
Definition: gd32f3x0_dbg.h:22
uint32_t dbg_id_get ( void )

read DBG_ID code register

Parameters
[in] | none
[out] | none
Return values
DBG_ID code

Definition at line 34 of file gd32f3x0_dbg.c.

35 {
36 return DBG_ID;
37 }
DBG_ID
#define DBG_ID
Definition: gd32f3x0_dbg.h:21
void dbg_low_power_disable ( uint32_t dbg_low_power )

disable low power behavior when the mcu is in debug mode

Parameters
[in] dbg_low_power this parameter can be any combination of the following values:
  • DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
  • DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
  • DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
[out] none
Return values
none

Definition at line 64 of file gd32f3x0_dbg.c.

65 {
66 DBG_CTL0 &= ~dbg_low_power;
67 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f3x0_dbg.h:22
void dbg_low_power_enable ( uint32_t dbg_low_power )

enable low power behavior when the mcu is in debug mode

Parameters
[in] dbg_low_power this parameter can be any combination of the following values:
  • DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
  • DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
  • DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
[out] none
Return values
none

Definition at line 49 of file gd32f3x0_dbg.c.

50 {
51 DBG_CTL0 |= dbg_low_power;
52 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f3x0_dbg.h:22
void dbg_periph_disable ( dbg_periph_enum dbg_periph )

disable peripheral behavior when the mcu is in debug mode

Parameters
[in] dbg_periph DBG peripheral only one parameter can be selected which is shown as below:
  • DBG_SLEEP_HOLD: keep debugger connection during sleep mode
  • DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode
  • DBG_STANDBY_HOLD: keep debugger connection during standby mode
  • DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
  • DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
  • DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted
  • DBG_TIMER1_HOLD: TIMER1 counter kept when core is halted
  • DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted
  • DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
  • DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
  • DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted
  • DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted
  • DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted
  • DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted
  • DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted
  • DBG_I2C2_HOLD: hold I2C2 SMBUS when core is halted
  • DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
[out] none
Return values
none

Definition at line 122 of file gd32f3x0_dbg.c.

123 {
124 DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
125 }
DBG_REG_VAL
#define DBG_REG_VAL(periph)
Definition: gd32f3x0_dbg.h:59
DBG_BIT_POS
#define DBG_BIT_POS(val)
Definition: gd32f3x0_dbg.h:60
void dbg_periph_enable ( dbg_periph_enum dbg_periph )

enable peripheral behavior when the mcu is in debug mode

Parameters
[in] dbg_periph DBG peripheral only one parameter can be selected which is shown as below:
  • DBG_SLEEP_HOLD: keep debugger connection during sleep mode
  • DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode
  • DBG_STANDBY_HOLD: keep debugger connection during standby mode
  • DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
  • DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
  • DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted
  • DBG_TIMER1_HOLD: TIMER1 counter kept when core is halted
  • DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted
  • DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
  • DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
  • DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted
  • DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted
  • DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted
  • DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted
  • DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted
  • DBG_I2C2_HOLD: hold I2C2 SMBUS when core is halted
  • DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
[out] none
Return values
none

Definition at line 93 of file gd32f3x0_dbg.c.

94 {
95 DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
96 }
DBG_REG_VAL
#define DBG_REG_VAL(periph)
Definition: gd32f3x0_dbg.h:59
DBG_BIT_POS
#define DBG_BIT_POS(val)
Definition: gd32f3x0_dbg.h:60
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_dma.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Data Structures | Macros | Enumerations | Functions
gd32f3x0_dma.h File Reference

definitions for the DMA More...

#include "gd32f3x0.h"

Go to the source code of this file.

Data Structures

struct dma_parameter_struct

Macros

#define | DMA DMA_BASE
#define | DMA_INTF REG32(DMA + 0x00U)
#define | DMA_INTC REG32(DMA + 0x04U)
#define | DMA_CH0CTL REG32(DMA + 0x08U)
#define | DMA_CH0CNT REG32(DMA + 0x0CU)
#define | DMA_CH0PADDR REG32(DMA + 0x10U)
#define | DMA_CH0MADDR REG32(DMA + 0x14U)
#define | DMA_CH1CTL REG32(DMA + 0x1CU)
#define | DMA_CH1CNT REG32(DMA + 0x20U)
#define | DMA_CH1PADDR REG32(DMA + 0x24U)
#define | DMA_CH1MADDR REG32(DMA + 0x28U)
#define | DMA_CH2CTL REG32(DMA + 0x30U)
#define | DMA_CH2CNT REG32(DMA + 0x34U)
#define | DMA_CH2PADDR REG32(DMA + 0x38U)
#define | DMA_CH2MADDR REG32(DMA + 0x3CU)
#define | DMA_CH3CTL REG32(DMA + 0x44U)
#define | DMA_CH3CNT REG32(DMA + 0x48U)
#define | DMA_CH3PADDR REG32(DMA + 0x4CU)
#define | DMA_CH3MADDR REG32(DMA + 0x50U)
#define | DMA_CH4CTL REG32(DMA + 0x58U)
#define | DMA_CH4CNT REG32(DMA + 0x5CU)
#define | DMA_CH4PADDR REG32(DMA + 0x60U)
#define | DMA_CH4MADDR REG32(DMA + 0x64U)
#define | DMA_CH5CTL REG32(DMA + 0x6CU)
#define | DMA_CH5CNT REG32(DMA + 0x70U)
#define | DMA_CH5PADDR REG32(DMA + 0x74U)
#define | DMA_CH5MADDR REG32(DMA + 0x78U)
#define | DMA_CH6CTL REG32(DMA + 0x80U)
#define | DMA_CH6CNT REG32(DMA + 0x84U)
#define | DMA_CH6PADDR REG32(DMA + 0x88U)
#define | DMA_CH6MADDR REG32(DMA + 0x8CU)
#define | DMA_INTF_GIF BIT(0)
#define | DMA_INTF_FTFIF BIT(1)
#define | DMA_INTF_HTFIF BIT(2)
#define | DMA_INTF_ERRIF BIT(3)
#define | DMA_INTC_GIFC BIT(0)
#define | DMA_INTC_FTFIFC BIT(1)
#define | DMA_INTC_HTFIFC BIT(2)
#define | DMA_INTC_ERRIFC BIT(3)
#define | DMA_CHXCTL_CHEN BIT(0)
#define | DMA_CHXCTL_FTFIE BIT(1)
#define | DMA_CHXCTL_HTFIE BIT(2)
#define | DMA_CHXCTL_ERRIE BIT(3)
#define | DMA_CHXCTL_DIR BIT(4)
#define | DMA_CHXCTL_CMEN BIT(5)
#define | DMA_CHXCTL_PNAGA BIT(6)
#define | DMA_CHXCTL_MNAGA BIT(7)
#define | DMA_CHXCTL_PWIDTH BITS(8,9)
#define | DMA_CHXCTL_MWIDTH BITS(10,11)
#define | DMA_CHXCTL_PRIO BITS(12,13)
#define | DMA_CHXCTL_M2M BIT(14)
#define | DMA_CHXCNT_CNT BITS(0,15)
#define | DMA_CHXPADDR_PADDR BITS(0,31)
#define | DMA_CHXMADDR_MADDR BITS(0,31)
#define | DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U)
#define | DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U)
#define | DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U)
#define | DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U)
#define | DMA_CHINTF_RESET_VALUE
#define | DMA_FLAG_ADD(flag, shift) ((flag) << ((uint32_t)(shift) * 4U))
#define | DMA_CHXCTL_BASE (DMA + 0x08U)
#define | DMA_CHXCNT_BASE (DMA + 0x0CU)
#define | DMA_CHXPADDR_BASE (DMA + 0x10U)
#define | DMA_CHXMADDR_BASE (DMA + 0x14U)
#define | DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + 0x14U * (uint32_t)(channel))
#define | DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + 0x14U * (uint32_t)(channel))
#define | DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + 0x14U * (uint32_t)(channel))
#define | DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + 0x14U * (uint32_t)(channel))
#define | DMA_INT_FLAG_G DMA_INTF_GIF
#define | DMA_INT_FLAG_FTF DMA_INTF_FTFIF
#define | DMA_INT_FLAG_HTF DMA_INTF_HTFIF
#define | DMA_INT_FLAG_ERR DMA_INTF_ERRIF
#define | DMA_FLAG_G DMA_INTF_GIF
#define | DMA_FLAG_FTF DMA_INTF_FTFIF
#define | DMA_FLAG_HTF DMA_INTF_HTFIF
#define | DMA_FLAG_ERR DMA_INTF_ERRIF
#define | DMA_INT_FTF DMA_CHXCTL_FTFIE
#define | DMA_INT_HTF DMA_CHXCTL_HTFIE
#define | DMA_INT_ERR DMA_CHXCTL_ERRIE
#define | DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U)
#define | DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U)
#define | DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U)
#define | DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U)
#define | DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U)
#define | DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U)
#define | CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8))
#define | DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0)
#define | DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1)
#define | DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2)
#define | CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10))
#define | DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0)
#define | DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1)
#define | DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2)
#define | CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12))
#define | DMA_PRIORITY_LOW CHCTL_PRIO(0)
#define | DMA_PRIORITY_MEDIUM CHCTL_PRIO(1)
#define | DMA_PRIORITY_HIGH CHCTL_PRIO(2)
#define | DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3)
#define | DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT

Enumerations

enum dma_channel_enum {
DMA_CH0 = 0, DMA_CH1, DMA_CH2, DMA_CH3,
DMA_CH4, DMA_CH5, DMA_CH6
}

Functions

void | dma_deinit (dma_channel_enum channelx)
deinitialize DMA a channel registers More...
void | dma_init (dma_channel_enum channelx, dma_parameter_struct init_struct)
initialize DMA channel More...
void | dma_circulation_enable (dma_channel_enum channelx)
enable DMA circulation mode More...
void | dma_circulation_disable (dma_channel_enum channelx)
disable DMA circulation mode More...
void | dma_memory_to_memory_enable (dma_channel_enum channelx)
enable memory to memory mode More...
void | dma_memory_to_memory_disable (dma_channel_enum channelx)
disable memory to memory mode More...
void | dma_channel_enable (dma_channel_enum channelx)
enable DMA channel More...
void | dma_channel_disable (dma_channel_enum channelx)
disable DMA channel More...
void | dma_periph_address_config (dma_channel_enum channelx, uint32_t address)
set DMA peripheral base address More...
void | dma_memory_address_config (dma_channel_enum channelx, uint32_t address)
set DMA memory base address More...
void | dma_transfer_number_config (dma_channel_enum channelx, uint32_t number)
set the number of remaining data to be transferred by the DMA More...
uint32_t | dma_transfer_number_get (dma_channel_enum channelx)
get the number of remaining data to be transferred by the DMA More...
void | dma_priority_config (dma_channel_enum channelx, uint32_t priority)
configure priority level of DMA channel More...
void | dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth)
configure transfer data size of memory More...
void | dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth)
configure transfer data size of peripheral More...
void | dma_memory_increase_enable (dma_channel_enum channelx)
enable next address increasement algorithm of memory More...
void | dma_memory_increase_disable (dma_channel_enum channelx)
disable next address increasement algorithm of memory More...
void | dma_periph_increase_enable (dma_channel_enum channelx)
enable next address increasement algorithm of peripheral More...
void | dma_periph_increase_disable (dma_channel_enum channelx)
disable next address increasement algorithm of peripheral More...
void | dma_transfer_direction_config (dma_channel_enum channelx, uint32_t direction)
configure the direction of data transfer on the channel More...
FlagStatus | dma_flag_get (dma_channel_enum channelx, uint32_t flag)
check DMA flag is set or not More...
void | dma_flag_clear (uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag More...
FlagStatus | dma_interrupt_flag_get (dma_channel_enum channelx, uint32_t flag)
check DMA flag and interrupt enable bit is set or not More...
void | dma_interrupt_flag_clear (dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag More...
void | dma_interrupt_enable (dma_channel_enum channelx, uint32_t source)
enable DMA interrupt More...
void | dma_interrupt_disable (dma_channel_enum channelx, uint32_t source)
disable DMA interrupt More...

Detailed Description

definitions for the DMA

Definition in file gd32f3x0_dma.h.

Macro Definition Documentation

#define CHCTL_MWIDTH ( regval ) (BITS(10,11) & ((regval) << 10))

transfer data size of memory

Definition at line 175 of file gd32f3x0_dma.h.

#define CHCTL_PRIO ( regval ) (BITS(12,13) & ((regval) << 12))

DMA channel priority level

Definition at line 181 of file gd32f3x0_dma.h.

#define CHCTL_PWIDTH ( regval ) (BITS(8,9) & ((regval) << 8))

transfer data size of peripheral

Definition at line 169 of file gd32f3x0_dma.h.

#define DMA DMA_BASE

DMA base address

Definition at line 18 of file gd32f3x0_dma.h.

#define DMA_CH0CNT REG32(DMA + 0x0CU)

DMA channel 0 counter register

Definition at line 24 of file gd32f3x0_dma.h.

#define DMA_CH0CTL REG32(DMA + 0x08U)

DMA channel 0 control register

Definition at line 23 of file gd32f3x0_dma.h.

#define DMA_CH0MADDR REG32(DMA + 0x14U)

DMA channel 0 memory base address register

Definition at line 26 of file gd32f3x0_dma.h.

#define DMA_CH0PADDR REG32(DMA + 0x10U)

DMA channel 0 peripheral base address register

Definition at line 25 of file gd32f3x0_dma.h.

#define DMA_CH1CNT REG32(DMA + 0x20U)

DMA channel 1 counter register

Definition at line 28 of file gd32f3x0_dma.h.

#define DMA_CH1CTL REG32(DMA + 0x1CU)

DMA channel 1 control register

Definition at line 27 of file gd32f3x0_dma.h.

#define DMA_CH1MADDR REG32(DMA + 0x28U)

DMA channel 1 memory base address register

Definition at line 30 of file gd32f3x0_dma.h.

#define DMA_CH1PADDR REG32(DMA + 0x24U)

DMA channel 1 peripheral base address register

Definition at line 29 of file gd32f3x0_dma.h.

#define DMA_CH2CNT REG32(DMA + 0x34U)

DMA channel 2 counter register

Definition at line 32 of file gd32f3x0_dma.h.

#define DMA_CH2CTL REG32(DMA + 0x30U)

DMA channel 2 control register

Definition at line 31 of file gd32f3x0_dma.h.

#define DMA_CH2MADDR REG32(DMA + 0x3CU)

DMA channel 2 memory base address register

Definition at line 34 of file gd32f3x0_dma.h.

#define DMA_CH2PADDR REG32(DMA + 0x38U)

DMA channel 2 peripheral base address register

Definition at line 33 of file gd32f3x0_dma.h.

#define DMA_CH3CNT REG32(DMA + 0x48U)

DMA channel 3 counter register

Definition at line 36 of file gd32f3x0_dma.h.

#define DMA_CH3CTL REG32(DMA + 0x44U)

DMA channel 3 control register

Definition at line 35 of file gd32f3x0_dma.h.

#define DMA_CH3MADDR REG32(DMA + 0x50U)

DMA channel 3 memory base address register

Definition at line 38 of file gd32f3x0_dma.h.

#define DMA_CH3PADDR REG32(DMA + 0x4CU)

DMA channel 3 peripheral base address register

Definition at line 37 of file gd32f3x0_dma.h.

#define DMA_CH4CNT REG32(DMA + 0x5CU)

DMA channel 4 counter register

Definition at line 40 of file gd32f3x0_dma.h.

#define DMA_CH4CTL REG32(DMA + 0x58U)

DMA channel 4 control register

Definition at line 39 of file gd32f3x0_dma.h.

#define DMA_CH4MADDR REG32(DMA + 0x64U)

DMA channel 4 memory base address register

Definition at line 42 of file gd32f3x0_dma.h.

#define DMA_CH4PADDR REG32(DMA + 0x60U)

DMA channel 4 peripheral base address register

Definition at line 41 of file gd32f3x0_dma.h.

#define DMA_CH5CNT REG32(DMA + 0x70U)

DMA channel 5 counter register

Definition at line 44 of file gd32f3x0_dma.h.

#define DMA_CH5CTL REG32(DMA + 0x6CU)

DMA channel 5 control register

Definition at line 43 of file gd32f3x0_dma.h.

#define DMA_CH5MADDR REG32(DMA + 0x78U)

DMA channel 5 memory base address register

Definition at line 46 of file gd32f3x0_dma.h.

#define DMA_CH5PADDR REG32(DMA + 0x74U)

DMA channel 5 peripheral base address register

Definition at line 45 of file gd32f3x0_dma.h.

#define DMA_CH6CNT REG32(DMA + 0x84U)

DMA channel 6 counter register

Definition at line 48 of file gd32f3x0_dma.h.

#define DMA_CH6CTL REG32(DMA + 0x80U)

DMA channel 6 control register

Definition at line 47 of file gd32f3x0_dma.h.

#define DMA_CH6MADDR REG32(DMA + 0x8CU)

DMA channel 6 memory base address register

Definition at line 50 of file gd32f3x0_dma.h.

#define DMA_CH6PADDR REG32(DMA + 0x88U)

DMA channel 6 peripheral base address register

Definition at line 49 of file gd32f3x0_dma.h.

#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT

Definition at line 189 of file gd32f3x0_dma.h.

#define DMA_CHCNT ( channel ) REG32(DMA_CHXCNT_BASE + 0x14U * (uint32_t)(channel))

the address of DMA channel CHXCNT register

Definition at line 133 of file gd32f3x0_dma.h.

#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U)

the reset value of DMA channel CHXCNT register

Definition at line 117 of file gd32f3x0_dma.h.

#define DMA_CHCTL ( channel ) REG32(DMA_CHXCTL_BASE + 0x14U * (uint32_t)(channel))

the address of DMA channel CHXCTL register

Definition at line 132 of file gd32f3x0_dma.h.

#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U)

the reset value of DMA channel CHXCTL register

Definition at line 116 of file gd32f3x0_dma.h.

#define DMA_CHINTF_RESET_VALUE
Value:
(DMA_INTF_GIF | DMA_INTF_FTFIF | \
DMA_INTF_HTFIF | DMA_INTF_ERRIF)
DMA_INTF_GIF
#define DMA_INTF_GIF
Definition: gd32f3x0_dma.h:54
DMA_INTF_HTFIF
#define DMA_INTF_HTFIF
Definition: gd32f3x0_dma.h:56
DMA_INTF_FTFIF
#define DMA_INTF_FTFIF
Definition: gd32f3x0_dma.h:55
DMA_INTF_ERRIF
#define DMA_INTF_ERRIF
Definition: gd32f3x0_dma.h:57

Definition at line 120 of file gd32f3x0_dma.h.

#define DMA_CHMADDR ( channel ) REG32(DMA_CHXMADDR_BASE + 0x14U * (uint32_t)(channel))

the address of DMA channel CHXMADDR register

Definition at line 135 of file gd32f3x0_dma.h.

#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U)

the reset value of DMA channel CHXMADDR register

Definition at line 119 of file gd32f3x0_dma.h.

#define DMA_CHPADDR ( channel ) REG32(DMA_CHXPADDR_BASE + 0x14U * (uint32_t)(channel))

the address of DMA channel CHXPADDR register

Definition at line 134 of file gd32f3x0_dma.h.

#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U)

the reset value of DMA channel CHXPADDR register

Definition at line 118 of file gd32f3x0_dma.h.

#define DMA_CHXCNT_BASE (DMA + 0x0CU)

the base address of DMA channel CHXCNT register

Definition at line 127 of file gd32f3x0_dma.h.

#define DMA_CHXCNT_CNT BITS(0,15)

transfer counter

Definition at line 80 of file gd32f3x0_dma.h.

#define DMA_CHXCTL_BASE (DMA + 0x08U)

the base address of DMA channel CHXCTL register

Definition at line 126 of file gd32f3x0_dma.h.

#define DMA_CHXCTL_CHEN BIT(0)

channel x enable

Definition at line 66 of file gd32f3x0_dma.h.

#define DMA_CHXCTL_CMEN BIT(5)

circulation mode

Definition at line 71 of file gd32f3x0_dma.h.

#define DMA_CHXCTL_DIR BIT(4)

direction of the data transfer on the channel

Definition at line 70 of file gd32f3x0_dma.h.

#define DMA_CHXCTL_ERRIE BIT(3)

enable bit for channel x error interrupt

Definition at line 69 of file gd32f3x0_dma.h.

#define DMA_CHXCTL_FTFIE BIT(1)

enable bit for channel x transfer complete interrupt

Definition at line 67 of file gd32f3x0_dma.h.

#define DMA_CHXCTL_HTFIE BIT(2)

enable bit for channel x transfer half complete interrupt

Definition at line 68 of file gd32f3x0_dma.h.

#define DMA_CHXCTL_M2M BIT(14)

memory to memory mode

Definition at line 77 of file gd32f3x0_dma.h.

#define DMA_CHXCTL_MNAGA BIT(7)

next address generation algorithm of memory

Definition at line 73 of file gd32f3x0_dma.h.

#define DMA_CHXCTL_MWIDTH BITS(10,11)

transfer data size of memory

Definition at line 75 of file gd32f3x0_dma.h.

#define DMA_CHXCTL_PNAGA BIT(6)

next address generation algorithm of peripheral

Definition at line 72 of file gd32f3x0_dma.h.

#define DMA_CHXCTL_PRIO BITS(12,13)

priority level of channelx

Definition at line 76 of file gd32f3x0_dma.h.

#define DMA_CHXCTL_PWIDTH BITS(8,9)

transfer data size of peripheral

Definition at line 74 of file gd32f3x0_dma.h.

#define DMA_CHXMADDR_BASE (DMA + 0x14U)

the base address of DMA channel CHXMADDR register

Definition at line 129 of file gd32f3x0_dma.h.

#define DMA_CHXMADDR_MADDR BITS(0,31)

memory base address

Definition at line 86 of file gd32f3x0_dma.h.

#define DMA_CHXPADDR_BASE (DMA + 0x10U)

the base address of DMA channel CHXPADDR register

Definition at line 128 of file gd32f3x0_dma.h.

#define DMA_CHXPADDR_PADDR BITS(0,31)

peripheral base address

Definition at line 83 of file gd32f3x0_dma.h.

#define DMA_FLAG_ADD | ( | flag,
 |  | shift
 | ) | ((flag) << ((uint32_t)(shift) * 4U))

DMA channel flag shift

Definition at line 123 of file gd32f3x0_dma.h.

#define DMA_FLAG_ERR DMA_INTF_ERRIF

error flag of channel

Definition at line 148 of file gd32f3x0_dma.h.

#define DMA_FLAG_FTF DMA_INTF_FTFIF

full transfer finish flag of channel

Definition at line 146 of file gd32f3x0_dma.h.

#define DMA_FLAG_G DMA_INTF_GIF

global interrupt flag of channel

Definition at line 145 of file gd32f3x0_dma.h.

#define DMA_FLAG_HTF DMA_INTF_HTFIF

half transfer finish flag of channel

Definition at line 147 of file gd32f3x0_dma.h.

#define DMA_INT_ERR DMA_CHXCTL_ERRIE

enable bit for channel error interrupt

Definition at line 154 of file gd32f3x0_dma.h.

#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF

error interrupt flag of channel

Definition at line 142 of file gd32f3x0_dma.h.

#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF

full transfer finish interrupt flag of channel

Definition at line 140 of file gd32f3x0_dma.h.

#define DMA_INT_FLAG_G DMA_INTF_GIF

global interrupt flag of channel

Definition at line 139 of file gd32f3x0_dma.h.

#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF

half transfer finish interrupt flag of channel

Definition at line 141 of file gd32f3x0_dma.h.

#define DMA_INT_FTF DMA_CHXCTL_FTFIE

enable bit for channel full transfer finish interrupt

Definition at line 152 of file gd32f3x0_dma.h.

#define DMA_INT_HTF DMA_CHXCTL_HTFIE

enable bit for channel half transfer finish interrupt

Definition at line 153 of file gd32f3x0_dma.h.

#define DMA_INTC REG32(DMA + 0x04U)

DMA interrupt flag clear register

Definition at line 22 of file gd32f3x0_dma.h.

#define DMA_INTC_ERRIFC BIT(3)

clear error flag of channel

Definition at line 63 of file gd32f3x0_dma.h.

#define DMA_INTC_FTFIFC BIT(1)

clear transfer finish flag of channel

Definition at line 61 of file gd32f3x0_dma.h.

#define DMA_INTC_GIFC BIT(0)

clear global interrupt flag of channel

Definition at line 60 of file gd32f3x0_dma.h.

#define DMA_INTC_HTFIFC BIT(2)

clear half transfer finish flag of channel

Definition at line 62 of file gd32f3x0_dma.h.

#define DMA_INTF REG32(DMA + 0x00U)

DMA interrupt flag register

Definition at line 21 of file gd32f3x0_dma.h.

#define DMA_INTF_ERRIF BIT(3)

error flag of channel

Definition at line 57 of file gd32f3x0_dma.h.

#define DMA_INTF_FTFIF BIT(1)

full transfer finish flag of channel

Definition at line 55 of file gd32f3x0_dma.h.

#define DMA_INTF_GIF BIT(0)

global interrupt flag of channel

Definition at line 54 of file gd32f3x0_dma.h.

#define DMA_INTF_HTFIF BIT(2)

half transfer finish flag of channel

Definition at line 56 of file gd32f3x0_dma.h.

#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U)

next address of memory is fixed address mode

Definition at line 165 of file gd32f3x0_dma.h.

#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U)

next address of memory is increasing address mode

Definition at line 166 of file gd32f3x0_dma.h.

#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U)

read from memory and write to peripheral

Definition at line 158 of file gd32f3x0_dma.h.

#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1)

transfer data size of memory is 16-bit

Definition at line 177 of file gd32f3x0_dma.h.

#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2)

transfer data size of memory is 32-bit

Definition at line 178 of file gd32f3x0_dma.h.

#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0)

transfer data size of memory is 8-bit

Definition at line 176 of file gd32f3x0_dma.h.

#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U)

next address of peripheral is fixed address mode

Definition at line 161 of file gd32f3x0_dma.h.

#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U)

next address of peripheral is increasing address mode

Definition at line 162 of file gd32f3x0_dma.h.

#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U)

read from peripheral and write to memory

Definition at line 157 of file gd32f3x0_dma.h.

#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1)

transfer data size of peripheral is 16-bit

Definition at line 171 of file gd32f3x0_dma.h.

#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2)

transfer data size of peripheral is 32-bit

Definition at line 172 of file gd32f3x0_dma.h.

#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0)

transfer data size of peripheral is 8-bit

Definition at line 170 of file gd32f3x0_dma.h.

#define DMA_PRIORITY_HIGH CHCTL_PRIO(2)

high priority

Definition at line 184 of file gd32f3x0_dma.h.

#define DMA_PRIORITY_LOW CHCTL_PRIO(0)

low priority

Definition at line 182 of file gd32f3x0_dma.h.

#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1)

medium priority

Definition at line 183 of file gd32f3x0_dma.h.

#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3)

ultra high priority

Definition at line 185 of file gd32f3x0_dma.h.

Enumeration Type Documentation

enum dma_channel_enum
Enumerator
DMA_CH0 | DMA Channel0
DMA_CH1 | DMA Channel1
DMA_CH2 | DMA Channel2
DMA_CH3 | DMA Channel3
DMA_CH4 | DMA Channel4
DMA_CH5 | DMA Channel5
DMA_CH6 | DMA Channel6

Definition at line 90 of file gd32f3x0_dma.h.

91 {
92 DMA_CH0 = 0,
93 DMA_CH1,
94 DMA_CH2,
95 DMA_CH3,
96 DMA_CH4,
97 DMA_CH5,
98 DMA_CH6
99 } dma_channel_enum;
dma_channel_enum
dma_channel_enum
Definition: gd32f3x0_dma.h:90
DMA_CH0
Definition: gd32f3x0_dma.h:92
DMA_CH5
Definition: gd32f3x0_dma.h:97
DMA_CH6
Definition: gd32f3x0_dma.h:98
DMA_CH3
Definition: gd32f3x0_dma.h:95
DMA_CH4
Definition: gd32f3x0_dma.h:96
DMA_CH1
Definition: gd32f3x0_dma.h:93
DMA_CH2
Definition: gd32f3x0_dma.h:94

Function Documentation

void dma_channel_disable ( dma_channel_enum channelx )

disable DMA channel

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 160 of file gd32f3x0_dma.c.

161 {
162 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
163 }
DMA_CHXCTL_CHEN
#define DMA_CHXCTL_CHEN
Definition: gd32f3x0_dma.h:66
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_channel_enable ( dma_channel_enum channelx )

enable DMA channel

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 148 of file gd32f3x0_dma.c.

149 {
150 DMA_CHCTL(channelx) |= DMA_CHXCTL_CHEN;
151 }
DMA_CHXCTL_CHEN
#define DMA_CHXCTL_CHEN
Definition: gd32f3x0_dma.h:66
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_circulation_disable ( dma_channel_enum channelx )

disable DMA circulation mode

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 112 of file gd32f3x0_dma.c.

113 {
114 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CMEN;
115 }
DMA_CHXCTL_CMEN
#define DMA_CHXCTL_CMEN
Definition: gd32f3x0_dma.h:71
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_circulation_enable ( dma_channel_enum channelx )

enable DMA circulation mode

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 100 of file gd32f3x0_dma.c.

101 {
102 DMA_CHCTL(channelx) |= DMA_CHXCTL_CMEN;
103 }
DMA_CHXCTL_CMEN
#define DMA_CHXCTL_CMEN
Definition: gd32f3x0_dma.h:71
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_deinit ( dma_channel_enum channelx )

deinitialize DMA a channel registers

Parameters
[in] channelx specify which DMA channel is deinitialized
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 21 of file gd32f3x0_dma.c.

22 {
23 /* disable DMA a channel */
24 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
25 /* reset DMA channel registers */
26 DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE;
27 DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE;
28 DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE;
29 DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE;
30 DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
31 }
DMA_CHCNT_RESET_VALUE
#define DMA_CHCNT_RESET_VALUE
Definition: gd32f3x0_dma.h:117
DMA_CHINTF_RESET_VALUE
#define DMA_CHINTF_RESET_VALUE
Definition: gd32f3x0_dma.h:120
DMA_CHCTL_RESET_VALUE
#define DMA_CHCTL_RESET_VALUE
Definition: gd32f3x0_dma.h:116
DMA_CHPADDR_RESET_VALUE
#define DMA_CHPADDR_RESET_VALUE
Definition: gd32f3x0_dma.h:118
DMA_INTC
#define DMA_INTC
Definition: gd32f3x0_dma.h:22
DMA_CHMADDR_RESET_VALUE
#define DMA_CHMADDR_RESET_VALUE
Definition: gd32f3x0_dma.h:119
DMA_CHCNT
#define DMA_CHCNT(channel)
Definition: gd32f3x0_dma.h:133
DMA_CHMADDR
#define DMA_CHMADDR(channel)
Definition: gd32f3x0_dma.h:135
DMA_CHXCTL_CHEN
#define DMA_CHXCTL_CHEN
Definition: gd32f3x0_dma.h:66
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f3x0_dma.h:123
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
DMA_CHPADDR
#define DMA_CHPADDR(channel)
Definition: gd32f3x0_dma.h:134
void dma_flag_clear | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

clear DMA a channel flag

Parameters
[in] channelx specify which DMA channel to clear flag
  • DMA_CHx(x=0..6)
[in] flag specify get which flag
  • DMA_FLAG_G: global interrupt flag of channel
  • DMA_FLAG_FTF: full transfer finish flag of channel
  • DMA_FLAG_HTF: half transfer finish flag of channel
  • DMA_FLAG_ERR: error flag of channel
[out] none
Return values
none

Definition at line 391 of file gd32f3x0_dma.c.

392 {
393 DMA_INTC |= DMA_FLAG_ADD(flag, channelx);
394 }
DMA_INTC
#define DMA_INTC
Definition: gd32f3x0_dma.h:22
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f3x0_dma.h:123
FlagStatus dma_flag_get | ( | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

check DMA flag is set or not

Parameters
[in] channelx specify which DMA channel to get flag
  • DMA_CHx(x=0..6)
[in] flag specify get which flag only one parameter can be selected which is shown as below:
  • DMA_FLAG_G: global interrupt flag of channel
  • DMA_FLAG_FTF: full transfer finish flag of channel
  • DMA_FLAG_HTF: half transfer finish flag of channel
  • DMA_FLAG_ERR: error flag of channel
[out] none
Return values
FlagStatus SET or RESET

Definition at line 366 of file gd32f3x0_dma.c.

367 {
368 FlagStatus reval;
369
370 if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))){
371 reval = SET;
372 }else{
373 reval = RESET;
374 }
375
376 return reval;
377 }
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f3x0_dma.h:123
DMA_INTF
#define DMA_INTF
Definition: gd32f3x0_dma.h:21
void dma_init | ( | dma_channel_enum | channelx,
 |  | dma_parameter_struct | init_struct
 | ) |  |

initialize DMA channel

Parameters
[in] channelx specify which DMA channel is initialized
  • DMA_CHx(x=0..6)
[in] | init_struct | the data needed to initialize DMA channel periph_addr: peripheral base address periph_width: DMA_PERIPHERAL_WIDTH_8BIT,DMA_PERIPHERAL_WIDTH_16BIT,DMA_PERIPHERAL_WIDTH_32BIT periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE memory_addr: memory base address memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE direction: DMA_PERIPHERAL_TO_MEMORY,DMA_MEMORY_TO_PERIPHERAL number: the number of remaining data to be transferred by the DMA priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH
[out] | none
Return values
none

Definition at line 50 of file gd32f3x0_dma.c.

51 {
52 uint32_t ctl;
53
54 dma_channel_disable(channelx);
55
56 /* configure peripheral base address */
57 DMA_CHPADDR(channelx) = init_struct.periph_addr;
58
59 /* configure memory base address */
60 DMA_CHMADDR(channelx) = init_struct.memory_addr;
61
62 /* configure the number of remaining data to be transferred */
63 DMA_CHCNT(channelx) = init_struct.number;
64
65 /* configure peripheral transfer width,memory transfer width,channel priotity */
66 ctl = DMA_CHCTL(channelx);
67 ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
68 ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority);
69 DMA_CHCTL(channelx) = ctl;
70
71 /* configure peripheral increasing mode */
72 if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){
73 DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
74 }else{
75 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
76 }
77
78 /* configure memory increasing mode */
79 if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){
80 DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
81 }else{
82 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
83 }
84
85 /* configure the direction of data transfer */
86 if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){
87 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
88 }else{
89 DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
90 }
91 }
DMA_CHXCTL_DIR
#define DMA_CHXCTL_DIR
Definition: gd32f3x0_dma.h:70
dma_channel_disable
void dma_channel_disable(dma_channel_enum channelx)
disable DMA channel
Definition: gd32f3x0_dma.c:160
dma_parameter_struct::priority
uint32_t priority
Definition: gd32f3x0_dma.h:112
dma_parameter_struct::memory_width
uint32_t memory_width
Definition: gd32f3x0_dma.h:108
dma_parameter_struct::periph_inc
uint8_t periph_inc
Definition: gd32f3x0_dma.h:106
DMA_CHXCTL_PWIDTH
#define DMA_CHXCTL_PWIDTH
Definition: gd32f3x0_dma.h:74
DMA_CHXCTL_MNAGA
#define DMA_CHXCTL_MNAGA
Definition: gd32f3x0_dma.h:73
DMA_PERIPH_INCREASE_ENABLE
#define DMA_PERIPH_INCREASE_ENABLE
Definition: gd32f3x0_dma.h:162
dma_parameter_struct::number
uint32_t number
Definition: gd32f3x0_dma.h:111
DMA_CHXCTL_PRIO
#define DMA_CHXCTL_PRIO
Definition: gd32f3x0_dma.h:76
DMA_MEMORY_INCREASE_ENABLE
#define DMA_MEMORY_INCREASE_ENABLE
Definition: gd32f3x0_dma.h:166
dma_parameter_struct::periph_width
uint32_t periph_width
Definition: gd32f3x0_dma.h:105
dma_parameter_struct::memory_inc
uint8_t memory_inc
Definition: gd32f3x0_dma.h:109
dma_parameter_struct::direction
uint8_t direction
Definition: gd32f3x0_dma.h:110
DMA_CHXCTL_PNAGA
#define DMA_CHXCTL_PNAGA
Definition: gd32f3x0_dma.h:72
DMA_CHCNT
#define DMA_CHCNT(channel)
Definition: gd32f3x0_dma.h:133
DMA_CHMADDR
#define DMA_CHMADDR(channel)
Definition: gd32f3x0_dma.h:135
DMA_PERIPHERAL_TO_MEMORY
#define DMA_PERIPHERAL_TO_MEMORY
Definition: gd32f3x0_dma.h:157
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
dma_parameter_struct::periph_addr
uint32_t periph_addr
Definition: gd32f3x0_dma.h:104
DMA_CHPADDR
#define DMA_CHPADDR(channel)
Definition: gd32f3x0_dma.h:134
DMA_CHXCTL_MWIDTH
#define DMA_CHXCTL_MWIDTH
Definition: gd32f3x0_dma.h:75
dma_parameter_struct::memory_addr
uint32_t memory_addr
Definition: gd32f3x0_dma.h:107
void dma_interrupt_disable | ( | dma_channel_enum | channelx,
 |  | uint32_t | source
 | ) |  |

disable DMA interrupt

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[in] source specify which interrupt to disbale
  • DMA_INT_ERR: channel error interrupt
  • DMA_INT_HTF: channel transfer half finish interrupt
  • DMA_INT_FTF: channel transfer finish interrupt
[out] none
Return values
none

Definition at line 480 of file gd32f3x0_dma.c.

481 {
482 DMA_CHCTL(channelx) &= ~source;
483 }
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_interrupt_enable | ( | dma_channel_enum | channelx,
 |  | uint32_t | source
 | ) |  |

enable DMA interrupt

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[in] source specify which interrupt to enbale
  • DMA_INT_ERR: channel error interrupt
  • DMA_INT_HTF: channel transfer half finish interrupt
  • DMA_INT_FTF: channel transfer finish interrupt
[out] none
Return values
none

Definition at line 464 of file gd32f3x0_dma.c.

465 {
466 DMA_CHCTL(channelx) |= source;
467 }
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_interrupt_flag_clear | ( | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

clear DMA a channel flag

Parameters
[in] channelx specify which DMA channel to clear flag
  • DMA_CHx(x=0..6)
[in] flag specify get which flag
  • DMA_INT_FLAG_G: global interrupt flag of channel
  • DMA_INT_FLAG_FTF: transfer finish flag of channel
  • DMA_INT_FLAG_HTF: half transfer finish flag of channel
  • DMA_INT_FLAG_ERR: error flag of channel
[out] none
Return values
none

Definition at line 448 of file gd32f3x0_dma.c.

449 {
450 DMA_INTC |= DMA_FLAG_ADD(flag,channelx);
451 }
DMA_INTC
#define DMA_INTC
Definition: gd32f3x0_dma.h:22
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f3x0_dma.h:123
FlagStatus dma_interrupt_flag_get | ( | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

check DMA flag and interrupt enable bit is set or not

Parameters
[in] channelx specify which DMA channel to get flag
  • DMA_CHx(x=0..6)
[in] flag specify get which flag only one parameter can be selected which is shown as below:
  • DMA_INT_FLAG_FTF: transfer finish flag of channel
  • DMA_INT_FLAG_HTF: half transfer finish flag of channel
  • DMA_INT_FLAG_ERR: error flag of channel
[out] none
Return values
FlagStatus SET or RESET

Definition at line 408 of file gd32f3x0_dma.c.

409 {
410 uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
411
412 switch(flag){
413 case DMA_INT_FLAG_FTF:
414 interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
415 interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE;
416 break;
417 case DMA_INT_FLAG_HTF:
418 interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
419 interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE;
420 break;
421 case DMA_INT_FLAG_ERR:
422 interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
423 interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_ERRIE;
424 break;
425 default:
426 break;
427 }
428
429 if(interrupt_flag && interrupt_enable){
430 return SET;
431 }else{
432 return RESET;
433 }
434 }
DMA_INT_FLAG_FTF
#define DMA_INT_FLAG_FTF
Definition: gd32f3x0_dma.h:140
DMA_CHXCTL_ERRIE
#define DMA_CHXCTL_ERRIE
Definition: gd32f3x0_dma.h:69
DMA_INT_FLAG_HTF
#define DMA_INT_FLAG_HTF
Definition: gd32f3x0_dma.h:141
DMA_CHXCTL_HTFIE
#define DMA_CHXCTL_HTFIE
Definition: gd32f3x0_dma.h:68
DMA_CHXCTL_FTFIE
#define DMA_CHXCTL_FTFIE
Definition: gd32f3x0_dma.h:67
DMA_INT_FLAG_ERR
#define DMA_INT_FLAG_ERR
Definition: gd32f3x0_dma.h:142
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f3x0_dma.h:123
DMA_INTF
#define DMA_INTF
Definition: gd32f3x0_dma.h:21
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_memory_address_config | ( | dma_channel_enum | channelx,
 |  | uint32_t | address
 | ) |  |

set DMA memory base address

Parameters
[in] channelx specify which DMA channel to set memory base address
  • DMA_CHx(x=0..6)
[in] | address | memory base address
[out] | none
Return values
none

Definition at line 186 of file gd32f3x0_dma.c.

187 {
188 DMA_CHMADDR(channelx) = address;
189 }
DMA_CHMADDR
#define DMA_CHMADDR(channel)
Definition: gd32f3x0_dma.h:135
void dma_memory_increase_disable ( dma_channel_enum channelx )

disable next address increasement algorithm of memory

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 305 of file gd32f3x0_dma.c.

306 {
307 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
308 }
DMA_CHXCTL_MNAGA
#define DMA_CHXCTL_MNAGA
Definition: gd32f3x0_dma.h:73
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_memory_increase_enable ( dma_channel_enum channelx )

enable next address increasement algorithm of memory

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 293 of file gd32f3x0_dma.c.

294 {
295 DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
296 }
DMA_CHXCTL_MNAGA
#define DMA_CHXCTL_MNAGA
Definition: gd32f3x0_dma.h:73
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_memory_to_memory_disable ( dma_channel_enum channelx )

disable memory to memory mode

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 136 of file gd32f3x0_dma.c.

137 {
138 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M;
139 }
DMA_CHXCTL_M2M
#define DMA_CHXCTL_M2M
Definition: gd32f3x0_dma.h:77
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_memory_to_memory_enable ( dma_channel_enum channelx )

enable memory to memory mode

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 124 of file gd32f3x0_dma.c.

125 {
126 DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M;
127 }
DMA_CHXCTL_M2M
#define DMA_CHXCTL_M2M
Definition: gd32f3x0_dma.h:77
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_memory_width_config | ( | dma_channel_enum | channelx,
 |  | uint32_t | mwidth
 | ) |  |

configure transfer data size of memory

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[in] mwidth transfer data size of memory
  • DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit
  • DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit
  • DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit
[out] none
Return values
none

Definition at line 251 of file gd32f3x0_dma.c.

252 {
253 uint32_t ctl;
254
255 /* acquire DMA_CHxCTL register */
256 ctl = DMA_CHCTL(channelx);
257 /* assign regiser */
258 ctl &= ~DMA_CHXCTL_MWIDTH;
259 ctl |= mwidth;
260 DMA_CHCTL(channelx) = ctl;
261 }
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
DMA_CHXCTL_MWIDTH
#define DMA_CHXCTL_MWIDTH
Definition: gd32f3x0_dma.h:75
void dma_periph_address_config | ( | dma_channel_enum | channelx,
 |  | uint32_t | address
 | ) |  |

set DMA peripheral base address

Parameters
[in] channelx specify which DMA channel to set peripheral base address
  • DMA_CHx(x=0..6)
[in] | address | peripheral base address
[out] | none
Return values
none

Definition at line 173 of file gd32f3x0_dma.c.

174 {
175 DMA_CHPADDR(channelx) = address;
176 }
DMA_CHPADDR
#define DMA_CHPADDR(channel)
Definition: gd32f3x0_dma.h:134
void dma_periph_increase_disable ( dma_channel_enum channelx )

disable next address increasement algorithm of peripheral

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 329 of file gd32f3x0_dma.c.

330 {
331 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
332 }
DMA_CHXCTL_PNAGA
#define DMA_CHXCTL_PNAGA
Definition: gd32f3x0_dma.h:72
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_periph_increase_enable ( dma_channel_enum channelx )

enable next address increasement algorithm of peripheral

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 317 of file gd32f3x0_dma.c.

318 {
319 DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
320 }
DMA_CHXCTL_PNAGA
#define DMA_CHXCTL_PNAGA
Definition: gd32f3x0_dma.h:72
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_periph_width_config | ( | dma_channel_enum | channelx,
 |  | uint32_t | pwidth
 | ) |  |

configure transfer data size of peripheral

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[in] pwidth transfer data size of peripheral
  • DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit
  • DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit
  • DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit
[out] none
Return values
none

Definition at line 274 of file gd32f3x0_dma.c.

275 {
276 uint32_t ctl;
277
278 /* acquire DMA_CHxCTL register */
279 ctl = DMA_CHCTL(channelx);
280 /* assign regiser */
281 ctl &= ~DMA_CHXCTL_PWIDTH;
282 ctl |= pwidth;
283 DMA_CHCTL(channelx) = ctl;
284 }
DMA_CHXCTL_PWIDTH
#define DMA_CHXCTL_PWIDTH
Definition: gd32f3x0_dma.h:74
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_priority_config | ( | dma_channel_enum | channelx,
 |  | uint32_t | priority
 | ) |  |

configure priority level of DMA channel

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[in] priority priority level of this channel
  • DMA_PRIORITY_LOW: low priority
  • DMA_PRIORITY_MEDIUM: medium priority
  • DMA_PRIORITY_HIGH: high priority
  • DMA_PRIORITY_ULTRA_HIGH: ultra high priority
[out] none
Return values
none

Definition at line 228 of file gd32f3x0_dma.c.

229 {
230 uint32_t ctl;
231
232 /* acquire DMA_CHxCTL register */
233 ctl = DMA_CHCTL(channelx);
234 /* assign regiser */
235 ctl &= ~DMA_CHXCTL_PRIO;
236 ctl |= priority;
237 DMA_CHCTL(channelx) = ctl;
238 }
DMA_CHXCTL_PRIO
#define DMA_CHXCTL_PRIO
Definition: gd32f3x0_dma.h:76
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_transfer_direction_config | ( | dma_channel_enum | channelx,
 |  | uint32_t | direction
 | ) |  |

configure the direction of data transfer on the channel

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[in] direction specify the direction of data transfer
  • DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
  • DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
[out] none
Return values
none

Definition at line 344 of file gd32f3x0_dma.c.

345 {
346 if(DMA_PERIPHERAL_TO_MEMORY == direction){
347 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
348 } else {
349 DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
350 }
351 }
DMA_CHXCTL_DIR
#define DMA_CHXCTL_DIR
Definition: gd32f3x0_dma.h:70
DMA_PERIPHERAL_TO_MEMORY
#define DMA_PERIPHERAL_TO_MEMORY
Definition: gd32f3x0_dma.h:157
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_transfer_number_config | ( | dma_channel_enum | channelx,
 |  | uint32_t | number
 | ) |  |

set the number of remaining data to be transferred by the DMA

Parameters
[in] channelx specify which DMA channel to set number
  • DMA_CHx(x=0..6)
[in] | number | the number of remaining data to be transferred by the DMA
[out] | none
Return values
none

Definition at line 199 of file gd32f3x0_dma.c.

200 {
201 DMA_CHCNT(channelx) = (number & DMA_CHANNEL_CNT_MASK);
202 }
DMA_CHCNT
#define DMA_CHCNT(channel)
Definition: gd32f3x0_dma.h:133
DMA_CHANNEL_CNT_MASK
#define DMA_CHANNEL_CNT_MASK
Definition: gd32f3x0_dma.h:189
uint32_t dma_transfer_number_get ( dma_channel_enum channelx )

get the number of remaining data to be transferred by the DMA

Parameters
[in] channelx specify which DMA channel to set number
  • DMA_CHx(x=0..6)
[out] none
Return values
the number of remaining data to be transferred by the DMA

Definition at line 211 of file gd32f3x0_dma.c.

212 {
213 return (uint32_t)DMA_CHCNT(channelx);
214 }
DMA_CHCNT
#define DMA_CHCNT(channel)
Definition: gd32f3x0_dma.h:133
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_exti.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Enumerations | Functions
gd32f3x0_exti.h File Reference

definitions for the EXTI More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | EXTI EXTI_BASE
#define | EXTI_INTEN REG32(EXTI + 0x00U)
#define | EXTI_EVEN REG32(EXTI + 0x04U)
#define | EXTI_RTEN REG32(EXTI + 0x08U)
#define | EXTI_FTEN REG32(EXTI + 0x0CU)
#define | EXTI_SWIEV REG32(EXTI + 0x10U)
#define | EXTI_PD REG32(EXTI + 0x14U)
#define | EXTI_INTEN_INTEN0 BIT(0)
#define | EXTI_INTEN_INTEN1 BIT(1)
#define | EXTI_INTEN_INTEN2 BIT(2)
#define | EXTI_INTEN_INTEN3 BIT(3)
#define | EXTI_INTEN_INTEN4 BIT(4)
#define | EXTI_INTEN_INTEN5 BIT(5)
#define | EXTI_INTEN_INTEN6 BIT(6)
#define | EXTI_INTEN_INTEN7 BIT(7)
#define | EXTI_INTEN_INTEN8 BIT(8)
#define | EXTI_INTEN_INTEN9 BIT(9)
#define | EXTI_INTEN_INTEN10 BIT(10)
#define | EXTI_INTEN_INTEN11 BIT(11)
#define | EXTI_INTEN_INTEN12 BIT(12)
#define | EXTI_INTEN_INTEN13 BIT(13)
#define | EXTI_INTEN_INTEN14 BIT(14)
#define | EXTI_INTEN_INTEN15 BIT(15)
#define | EXTI_INTEN_INTEN16 BIT(16)
#define | EXTI_INTEN_INTEN17 BIT(17)
#define | EXTI_INTEN_INTEN18 BIT(18)
#define | EXTI_INTEN_INTEN19 BIT(19)
#define | EXTI_INTEN_INTEN20 BIT(20)
#define | EXTI_INTEN_INTEN21 BIT(21)
#define | EXTI_INTEN_INTEN22 BIT(22)
#define | EXTI_INTEN_INTEN23 BIT(23)
#define | EXTI_INTEN_INTEN24 BIT(24)
#define | EXTI_INTEN_INTEN25 BIT(25)
#define | EXTI_INTEN_INTEN26 BIT(26)
#define | EXTI_INTEN_INTEN27 BIT(27)
#define | EXTI_EVEN_EVEN0 BIT(0)
#define | EXTI_EVEN_EVEN1 BIT(1)
#define | EXTI_EVEN_EVEN2 BIT(2)
#define | EXTI_EVEN_EVEN3 BIT(3)
#define | EXTI_EVEN_EVEN4 BIT(4)
#define | EXTI_EVEN_EVEN5 BIT(5)
#define | EXTI_EVEN_EVEN6 BIT(6)
#define | EXTI_EVEN_EVEN7 BIT(7)
#define | EXTI_EVEN_EVEN8 BIT(8)
#define | EXTI_EVEN_EVEN9 BIT(9)
#define | EXTI_EVEN_EVEN10 BIT(10)
#define | EXTI_EVEN_EVEN11 BIT(11)
#define | EXTI_EVEN_EVEN12 BIT(12)
#define | EXTI_EVEN_EVEN13 BIT(13)
#define | EXTI_EVEN_EVEN14 BIT(14)
#define | EXTI_EVEN_EVEN15 BIT(15)
#define | EXTI_EVEN_EVEN16 BIT(16)
#define | EXTI_EVEN_EVEN17 BIT(17)
#define | EXTI_EVEN_EVEN18 BIT(18)
#define | EXTI_EVEN_EVEN19 BIT(19)
#define | EXTI_EVEN_EVEN20 BIT(20)
#define | EXTI_EVEN_EVEN21 BIT(21)
#define | EXTI_EVEN_EVEN22 BIT(22)
#define | EXTI_EVEN_EVEN23 BIT(23)
#define | EXTI_EVEN_EVEN24 BIT(24)
#define | EXTI_EVEN_EVEN25 BIT(25)
#define | EXTI_EVEN_EVEN26 BIT(26)
#define | EXTI_EVEN_EVEN27 BIT(27)
#define | EXTI_RTEN_RTEN0 BIT(0)
#define | EXTI_RTEN_RTEN1 BIT(1)
#define | EXTI_RTEN_RTEN2 BIT(2)
#define | EXTI_RTEN_RTEN3 BIT(3)
#define | EXTI_RTEN_RTEN4 BIT(4)
#define | EXTI_RTEN_RTEN5 BIT(5)
#define | EXTI_RTEN_RTEN6 BIT(6)
#define | EXTI_RTEN_RTEN7 BIT(7)
#define | EXTI_RTEN_RTEN8 BIT(8)
#define | EXTI_RTEN_RTEN9 BIT(9)
#define | EXTI_RTEN_RTEN10 BIT(10)
#define | EXTI_RTEN_RTEN11 BIT(11)
#define | EXTI_RTEN_RTEN12 BIT(12)
#define | EXTI_RTEN_RTEN13 BIT(13)
#define | EXTI_RTEN_RTEN14 BIT(14)
#define | EXTI_RTEN_RTEN15 BIT(15)
#define | EXTI_RTEN_RTEN16 BIT(16)
#define | EXTI_RTEN_RTEN17 BIT(17)
#define | EXTI_RTEN_RTEN18 BIT(18)
#define | EXTI_RTEN_RTEN19 BIT(19)
#define | EXTI_RTEN_RTEN21 BIT(21)
#define | EXTI_RTEN_RTEN22 BIT(22)
#define | EXTI_FTEN_FTEN0 BIT(0)
#define | EXTI_FTEN_FTEN1 BIT(1)
#define | EXTI_FTEN_FTEN2 BIT(2)
#define | EXTI_FTEN_FTEN3 BIT(3)
#define | EXTI_FTEN_FTEN4 BIT(4)
#define | EXTI_FTEN_FTEN5 BIT(5)
#define | EXTI_FTEN_FTEN6 BIT(6)
#define | EXTI_FTEN_FTEN7 BIT(7)
#define | EXTI_FTEN_FTEN8 BIT(8)
#define | EXTI_FTEN_FTEN9 BIT(9)
#define | EXTI_FTEN_FTEN10 BIT(10)
#define | EXTI_FTEN_FTEN11 BIT(11)
#define | EXTI_FTEN_FTEN12 BIT(12)
#define | EXTI_FTEN_FTEN13 BIT(13)
#define | EXTI_FTEN_FTEN14 BIT(14)
#define | EXTI_FTEN_FTEN15 BIT(15)
#define | EXTI_FTEN_FTEN16 BIT(16)
#define | EXTI_FTEN_FTEN17 BIT(17)
#define | EXTI_FTEN_FTEN18 BIT(18)
#define | EXTI_FTEN_FTEN19 BIT(19)
#define | EXTI_FTEN_FTEN21 BIT(21)
#define | EXTI_FTEN_FTEN22 BIT(22)
#define | EXTI_SWIEV_SWIEV0 BIT(0)
#define | EXTI_SWIEV_SWIEV1 BIT(1)
#define | EXTI_SWIEV_SWIEV2 BIT(2)
#define | EXTI_SWIEV_SWIEV3 BIT(3)
#define | EXTI_SWIEV_SWIEV4 BIT(4)
#define | EXTI_SWIEV_SWIEV5 BIT(5)
#define | EXTI_SWIEV_SWIEV6 BIT(6)
#define | EXTI_SWIEV_SWIEV7 BIT(7)
#define | EXTI_SWIEV_SWIEV8 BIT(8)
#define | EXTI_SWIEV_SWIEV9 BIT(9)
#define | EXTI_SWIEV_SWIEV10 BIT(10)
#define | EXTI_SWIEV_SWIEV11 BIT(11)
#define | EXTI_SWIEV_SWIEV12 BIT(12)
#define | EXTI_SWIEV_SWIEV13 BIT(13)
#define | EXTI_SWIEV_SWIEV14 BIT(14)
#define | EXTI_SWIEV_SWIEV15 BIT(15)
#define | EXTI_SWIEV_SWIEV16 BIT(16)
#define | EXTI_SWIEV_SWIEV17 BIT(17)
#define | EXTI_SWIEV_SWIEV18 BIT(18)
#define | EXTI_SWIEV_SWIEV19 BIT(19)
#define | EXTI_SWIEV_SWIEV21 BIT(21)
#define | EXTI_SWIEV_SWIEV22 BIT(22)
#define | EXTI_PD_PD0 BIT(0)
#define | EXTI_PD_PD1 BIT(1)
#define | EXTI_PD_PD2 BIT(2)
#define | EXTI_PD_PD3 BIT(3)
#define | EXTI_PD_PD4 BIT(4)
#define | EXTI_PD_PD5 BIT(5)
#define | EXTI_PD_PD6 BIT(6)
#define | EXTI_PD_PD7 BIT(7)
#define | EXTI_PD_PD8 BIT(8)
#define | EXTI_PD_PD9 BIT(9)
#define | EXTI_PD_PD10 BIT(10)
#define | EXTI_PD_PD11 BIT(11)
#define | EXTI_PD_PD12 BIT(12)
#define | EXTI_PD_PD13 BIT(13)
#define | EXTI_PD_PD14 BIT(14)
#define | EXTI_PD_PD15 BIT(15)
#define | EXTI_PD_PD16 BIT(16)
#define | EXTI_PD_PD17 BIT(17)
#define | EXTI_PD_PD18 BIT(18)
#define | EXTI_PD_PD19 BIT(19)
#define | EXTI_PD_PD21 BIT(21)
#define | EXTI_PD_PD22 BIT(22)

Enumerations

enum exti_line_enum {
EXTI_0 = BIT(0), EXTI_1 = BIT(1), EXTI_2 = BIT(2), EXTI_3 = BIT(3),
EXTI_4 = BIT(4), EXTI_5 = BIT(5), EXTI_6 = BIT(6), EXTI_7 = BIT(7),
EXTI_8 = BIT(8), EXTI_9 = BIT(9), EXTI_10 = BIT(10), EXTI_11 = BIT(11),
EXTI_12 = BIT(12), EXTI_13 = BIT(13), EXTI_14 = BIT(14), EXTI_15 = BIT(15),
EXTI_16 = BIT(16), EXTI_17 = BIT(17), EXTI_18 = BIT(18), EXTI_19 = BIT(19),
EXTI_20 = BIT(20), EXTI_21 = BIT(21), EXTI_22 = BIT(22), EXTI_23 = BIT(23),
EXTI_24 = BIT(24), EXTI_25 = BIT(25), EXTI_26 = BIT(26), EXTI_27 = BIT(27)
}
enum | exti_mode_enum { EXTI_INTERRUPT = 0, EXTI_EVENT }
enum | exti_trig_type_enum { EXTI_TRIG_RISING = 0, EXTI_TRIG_FALLING, EXTI_TRIG_BOTH }

Functions

void | exti_deinit (void)
deinitialize the EXTI More...
void | exti_init (exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
initialize the EXTI More...
void | exti_interrupt_enable (exti_line_enum linex)
enable the interrupts from EXTI line x More...
void | exti_event_enable (exti_line_enum linex)
enable the events from EXTI line x More...
void | exti_interrupt_disable (exti_line_enum linex)
disable the interrupt from EXTI line x More...
void | exti_event_disable (exti_line_enum linex)
disable the events from EXTI line x More...
FlagStatus | exti_flag_get (exti_line_enum linex)
get EXTI lines flag More...
void | exti_flag_clear (exti_line_enum linex)
clear EXTI lines pending flag More...
FlagStatus | exti_interrupt_flag_get (exti_line_enum linex)
get EXTI lines flag when the interrupt flag is set More...
void | exti_interrupt_flag_clear (exti_line_enum linex)
clear EXTI lines pending flag More...
void | exti_software_interrupt_enable (exti_line_enum linex)
enable EXTI software interrupt event More...
void | exti_software_interrupt_disable (exti_line_enum linex)
disable EXTI software interrupt event More...

Detailed Description

definitions for the EXTI

Definition in file gd32f3x0_exti.h.

Macro Definition Documentation

#define EXTI EXTI_BASE

Definition at line 18 of file gd32f3x0_exti.h.

#define EXTI_EVEN REG32(EXTI + 0x04U)

event enable register

Definition at line 22 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN0 BIT(0)

event from line 0

Definition at line 60 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN1 BIT(1)

event from line 1

Definition at line 61 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN10 BIT(10)

event from line 10

Definition at line 70 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN11 BIT(11)

event from line 11

Definition at line 71 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN12 BIT(12)

event from line 12

Definition at line 72 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN13 BIT(13)

event from line 13

Definition at line 73 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN14 BIT(14)

event from line 14

Definition at line 74 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN15 BIT(15)

event from line 15

Definition at line 75 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN16 BIT(16)

event from line 16

Definition at line 76 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN17 BIT(17)

event from line 17

Definition at line 77 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN18 BIT(18)

event from line 18

Definition at line 78 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN19 BIT(19)

event from line 19

Definition at line 79 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN2 BIT(2)

event from line 2

Definition at line 62 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN20 BIT(20)

event from line 20

Definition at line 80 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN21 BIT(21)

event from line 21

Definition at line 81 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN22 BIT(22)

event from line 22

Definition at line 82 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN23 BIT(23)

event from line 23

Definition at line 83 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN24 BIT(24)

event from line 24

Definition at line 84 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN25 BIT(25)

event from line 25

Definition at line 85 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN26 BIT(26)

event from line 26

Definition at line 86 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN27 BIT(27)

event from line 27

Definition at line 87 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN3 BIT(3)

event from line 3

Definition at line 63 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN4 BIT(4)

event from line 4

Definition at line 64 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN5 BIT(5)

event from line 5

Definition at line 65 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN6 BIT(6)

event from line 6

Definition at line 66 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN7 BIT(7)

event from line 7

Definition at line 67 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN8 BIT(8)

event from line 8

Definition at line 68 of file gd32f3x0_exti.h.

#define EXTI_EVEN_EVEN9 BIT(9)

event from line 9

Definition at line 69 of file gd32f3x0_exti.h.

#define EXTI_FTEN REG32(EXTI + 0x0CU)

falling trigger enable register

Definition at line 24 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN0 BIT(0)

falling edge from line 0

Definition at line 114 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN1 BIT(1)

falling edge from line 1

Definition at line 115 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN10 BIT(10)

falling edge from line 10

Definition at line 124 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN11 BIT(11)

falling edge from line 11

Definition at line 125 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN12 BIT(12)

falling edge from line 12

Definition at line 126 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN13 BIT(13)

falling edge from line 13

Definition at line 127 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN14 BIT(14)

falling edge from line 14

Definition at line 128 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN15 BIT(15)

falling edge from line 15

Definition at line 129 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN16 BIT(16)

falling edge from line 16

Definition at line 130 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN17 BIT(17)

falling edge from line 17

Definition at line 131 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN18 BIT(18)

falling edge from line 18

Definition at line 132 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN19 BIT(19)

falling edge from line 19

Definition at line 133 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN2 BIT(2)

falling edge from line 2

Definition at line 116 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN21 BIT(21)

falling edge from line 21

Definition at line 134 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN22 BIT(22)

falling edge from line 22

Definition at line 135 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN3 BIT(3)

falling edge from line 3

Definition at line 117 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN4 BIT(4)

falling edge from line 4

Definition at line 118 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN5 BIT(5)

falling edge from line 5

Definition at line 119 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN6 BIT(6)

falling edge from line 6

Definition at line 120 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN7 BIT(7)

falling edge from line 7

Definition at line 121 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN8 BIT(8)

falling edge from line 8

Definition at line 122 of file gd32f3x0_exti.h.

#define EXTI_FTEN_FTEN9 BIT(9)

falling edge from line 9

Definition at line 123 of file gd32f3x0_exti.h.

#define EXTI_INTEN REG32(EXTI + 0x00U)

interrupt enable register

Definition at line 21 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN0 BIT(0)

interrupt from line 0

Definition at line 30 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN1 BIT(1)

interrupt from line 1

Definition at line 31 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN10 BIT(10)

interrupt from line 10

Definition at line 40 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN11 BIT(11)

interrupt from line 11

Definition at line 41 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN12 BIT(12)

interrupt from line 12

Definition at line 42 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN13 BIT(13)

interrupt from line 13

Definition at line 43 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN14 BIT(14)

interrupt from line 14

Definition at line 44 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN15 BIT(15)

interrupt from line 15

Definition at line 45 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN16 BIT(16)

interrupt from line 16

Definition at line 46 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN17 BIT(17)

interrupt from line 17

Definition at line 47 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN18 BIT(18)

interrupt from line 18

Definition at line 48 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN19 BIT(19)

interrupt from line 19

Definition at line 49 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN2 BIT(2)

interrupt from line 2

Definition at line 32 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN20 BIT(20)

interrupt from line 20

Definition at line 50 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN21 BIT(21)

interrupt from line 21

Definition at line 51 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN22 BIT(22)

interrupt from line 22

Definition at line 52 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN23 BIT(23)

interrupt from line 23

Definition at line 53 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN24 BIT(24)

interrupt from line 24

Definition at line 54 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN25 BIT(25)

interrupt from line 25

Definition at line 55 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN26 BIT(26)

interrupt from line 26

Definition at line 56 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN27 BIT(27)

interrupt from line 27

Definition at line 57 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN3 BIT(3)

interrupt from line 3

Definition at line 33 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN4 BIT(4)

interrupt from line 4

Definition at line 34 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN5 BIT(5)

interrupt from line 5

Definition at line 35 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN6 BIT(6)

interrupt from line 6

Definition at line 36 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN7 BIT(7)

interrupt from line 7

Definition at line 37 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN8 BIT(8)

interrupt from line 8

Definition at line 38 of file gd32f3x0_exti.h.

#define EXTI_INTEN_INTEN9 BIT(9)

interrupt from line 9

Definition at line 39 of file gd32f3x0_exti.h.

#define EXTI_PD REG32(EXTI + 0x14U)

pending register

Definition at line 26 of file gd32f3x0_exti.h.

#define EXTI_PD_PD0 BIT(0)

interrupt/event pending status from line 0

Definition at line 162 of file gd32f3x0_exti.h.

#define EXTI_PD_PD1 BIT(1)

interrupt/event pending status from line 1

Definition at line 163 of file gd32f3x0_exti.h.

#define EXTI_PD_PD10 BIT(10)

interrupt/event pending status from line 10

Definition at line 172 of file gd32f3x0_exti.h.

#define EXTI_PD_PD11 BIT(11)

interrupt/event pending status from line 11

Definition at line 173 of file gd32f3x0_exti.h.

#define EXTI_PD_PD12 BIT(12)

interrupt/event pending status from line 12

Definition at line 174 of file gd32f3x0_exti.h.

#define EXTI_PD_PD13 BIT(13)

interrupt/event pending status from line 13

Definition at line 175 of file gd32f3x0_exti.h.

#define EXTI_PD_PD14 BIT(14)

interrupt/event pending status from line 14

Definition at line 176 of file gd32f3x0_exti.h.

#define EXTI_PD_PD15 BIT(15)

interrupt/event pending status from line 15

Definition at line 177 of file gd32f3x0_exti.h.

#define EXTI_PD_PD16 BIT(16)

interrupt/event pending status from line 16

Definition at line 178 of file gd32f3x0_exti.h.

#define EXTI_PD_PD17 BIT(17)

interrupt/event pending status from line 17

Definition at line 179 of file gd32f3x0_exti.h.

#define EXTI_PD_PD18 BIT(18)

interrupt/event pending status from line 18

Definition at line 180 of file gd32f3x0_exti.h.

#define EXTI_PD_PD19 BIT(19)

interrupt/event pending status from line 19

Definition at line 181 of file gd32f3x0_exti.h.

#define EXTI_PD_PD2 BIT(2)

interrupt/event pending status from line 2

Definition at line 164 of file gd32f3x0_exti.h.

#define EXTI_PD_PD21 BIT(21)

interrupt/event pending status from line 21

Definition at line 182 of file gd32f3x0_exti.h.

#define EXTI_PD_PD22 BIT(22)

interrupt/event pending status from line 22

Definition at line 183 of file gd32f3x0_exti.h.

#define EXTI_PD_PD3 BIT(3)

interrupt/event pending status from line 3

Definition at line 165 of file gd32f3x0_exti.h.

#define EXTI_PD_PD4 BIT(4)

interrupt/event pending status from line 4

Definition at line 166 of file gd32f3x0_exti.h.

#define EXTI_PD_PD5 BIT(5)

interrupt/event pending status from line 5

Definition at line 167 of file gd32f3x0_exti.h.

#define EXTI_PD_PD6 BIT(6)

interrupt/event pending status from line 6

Definition at line 168 of file gd32f3x0_exti.h.

#define EXTI_PD_PD7 BIT(7)

interrupt/event pending status from line 7

Definition at line 169 of file gd32f3x0_exti.h.

#define EXTI_PD_PD8 BIT(8)

interrupt/event pending status from line 8

Definition at line 170 of file gd32f3x0_exti.h.

#define EXTI_PD_PD9 BIT(9)

interrupt/event pending status from line 9

Definition at line 171 of file gd32f3x0_exti.h.

#define EXTI_RTEN REG32(EXTI + 0x08U)

rising edge trigger enable register

Definition at line 23 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN0 BIT(0)

rising edge from line 0

Definition at line 90 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN1 BIT(1)

rising edge from line 1

Definition at line 91 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN10 BIT(10)

rising edge from line 10

Definition at line 100 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN11 BIT(11)

rising edge from line 11

Definition at line 101 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN12 BIT(12)

rising edge from line 12

Definition at line 102 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN13 BIT(13)

rising edge from line 13

Definition at line 103 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN14 BIT(14)

rising edge from line 14

Definition at line 104 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN15 BIT(15)

rising edge from line 15

Definition at line 105 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN16 BIT(16)

rising edge from line 16

Definition at line 106 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN17 BIT(17)

rising edge from line 17

Definition at line 107 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN18 BIT(18)

rising edge from line 18

Definition at line 108 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN19 BIT(19)

rising edge from line 19

Definition at line 109 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN2 BIT(2)

rising edge from line 2

Definition at line 92 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN21 BIT(21)

rising edge from line 21

Definition at line 110 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN22 BIT(22)

rising edge from line 22

Definition at line 111 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN3 BIT(3)

rising edge from line 3

Definition at line 93 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN4 BIT(4)

rising edge from line 4

Definition at line 94 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN5 BIT(5)

rising edge from line 5

Definition at line 95 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN6 BIT(6)

rising edge from line 6

Definition at line 96 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN7 BIT(7)

rising edge from line 7

Definition at line 97 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN8 BIT(8)

rising edge from line 8

Definition at line 98 of file gd32f3x0_exti.h.

#define EXTI_RTEN_RTEN9 BIT(9)

rising edge from line 9

Definition at line 99 of file gd32f3x0_exti.h.

#define EXTI_SWIEV REG32(EXTI + 0x10U)

software interrupt event register

Definition at line 25 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV0 BIT(0)

software interrupt/event request from line 0

Definition at line 138 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV1 BIT(1)

software interrupt/event request from line 1

Definition at line 139 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV10 BIT(10)

software interrupt/event request from line 10

Definition at line 148 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV11 BIT(11)

software interrupt/event request from line 11

Definition at line 149 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV12 BIT(12)

software interrupt/event request from line 12

Definition at line 150 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV13 BIT(13)

software interrupt/event request from line 13

Definition at line 151 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV14 BIT(14)

software interrupt/event request from line 14

Definition at line 152 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV15 BIT(15)

software interrupt/event request from line 15

Definition at line 153 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV16 BIT(16)

software interrupt/event request from line 16

Definition at line 154 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV17 BIT(17)

software interrupt/event request from line 17

Definition at line 155 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV18 BIT(18)

software interrupt/event request from line 18

Definition at line 156 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV19 BIT(19)

software interrupt/event request from line 19

Definition at line 157 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV2 BIT(2)

software interrupt/event request from line 2

Definition at line 140 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV21 BIT(21)

software interrupt/event request from line 21

Definition at line 158 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV22 BIT(22)

software interrupt/event request from line 22

Definition at line 159 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV3 BIT(3)

software interrupt/event request from line 3

Definition at line 141 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV4 BIT(4)

software interrupt/event request from line 4

Definition at line 142 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV5 BIT(5)

software interrupt/event request from line 5

Definition at line 143 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV6 BIT(6)

software interrupt/event request from line 6

Definition at line 144 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV7 BIT(7)

software interrupt/event request from line 7

Definition at line 145 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV8 BIT(8)

software interrupt/event request from line 8

Definition at line 146 of file gd32f3x0_exti.h.

#define EXTI_SWIEV_SWIEV9 BIT(9)

software interrupt/event request from line 9

Definition at line 147 of file gd32f3x0_exti.h.

Enumeration Type Documentation

enum exti_line_enum
Enumerator
EXTI_0 | EXTI line 0
EXTI_1 | EXTI line 1
EXTI_2 | EXTI line 2
EXTI_3 | EXTI line 3
EXTI_4 | EXTI line 4
EXTI_5 | EXTI line 5
EXTI_6 | EXTI line 6
EXTI_7 | EXTI line 7
EXTI_8 | EXTI line 8
EXTI_9 | EXTI line 9
EXTI_10 | EXTI line 10
EXTI_11 | EXTI line 11
EXTI_12 | EXTI line 12
EXTI_13 | EXTI line 13
EXTI_14 | EXTI line 14
EXTI_15 | EXTI line 15
EXTI_16 | EXTI line 16
EXTI_17 | EXTI line 17
EXTI_18 | EXTI line 18
EXTI_19 | EXTI line 19
EXTI_20 | EXTI line 20
EXTI_21 | EXTI line 21
EXTI_22 | EXTI line 22
EXTI_23 | EXTI line 23
EXTI_24 | EXTI line 24
EXTI_25 | EXTI line 25
EXTI_26 | EXTI line 26
EXTI_27 | EXTI line 27

Definition at line 187 of file gd32f3x0_exti.h.

188 {
189 EXTI_0 = BIT(0),
190 EXTI_1 = BIT(1),
191 EXTI_2 = BIT(2),
192 EXTI_3 = BIT(3),
193 EXTI_4 = BIT(4),
194 EXTI_5 = BIT(5),
195 EXTI_6 = BIT(6),
196 EXTI_7 = BIT(7),
197 EXTI_8 = BIT(8),
198 EXTI_9 = BIT(9),
199 EXTI_10 = BIT(10),
200 EXTI_11 = BIT(11),
201 EXTI_12 = BIT(12),
202 EXTI_13 = BIT(13),
203 EXTI_14 = BIT(14),
204 EXTI_15 = BIT(15),
205 EXTI_16 = BIT(16),
206 EXTI_17 = BIT(17),
207 EXTI_18 = BIT(18),
208 EXTI_19 = BIT(19),
209 EXTI_20 = BIT(20),
210 EXTI_21 = BIT(21),
211 EXTI_22 = BIT(22),
212 EXTI_23 = BIT(23),
213 EXTI_24 = BIT(24),
214 EXTI_25 = BIT(25),
215 EXTI_26 = BIT(26),
216 EXTI_27 = BIT(27),
217 }exti_line_enum;
EXTI_20
Definition: gd32f3x0_exti.h:209
EXTI_27
Definition: gd32f3x0_exti.h:216
EXTI_12
Definition: gd32f3x0_exti.h:201
EXTI_4
Definition: gd32f3x0_exti.h:193
EXTI_23
Definition: gd32f3x0_exti.h:212
EXTI_15
Definition: gd32f3x0_exti.h:204
exti_line_enum
exti_line_enum
Definition: gd32f3x0_exti.h:187
EXTI_2
Definition: gd32f3x0_exti.h:191
EXTI_8
Definition: gd32f3x0_exti.h:197
EXTI_13
Definition: gd32f3x0_exti.h:202
EXTI_1
Definition: gd32f3x0_exti.h:190
EXTI_17
Definition: gd32f3x0_exti.h:206
EXTI_22
Definition: gd32f3x0_exti.h:211
EXTI_14
Definition: gd32f3x0_exti.h:203
EXTI_6
Definition: gd32f3x0_exti.h:195
EXTI_24
Definition: gd32f3x0_exti.h:213
EXTI_10
Definition: gd32f3x0_exti.h:199
EXTI_26
Definition: gd32f3x0_exti.h:215
EXTI_5
Definition: gd32f3x0_exti.h:194
EXTI_7
Definition: gd32f3x0_exti.h:196
EXTI_19
Definition: gd32f3x0_exti.h:208
EXTI_9
Definition: gd32f3x0_exti.h:198
EXTI_11
Definition: gd32f3x0_exti.h:200
EXTI_18
Definition: gd32f3x0_exti.h:207
EXTI_25
Definition: gd32f3x0_exti.h:214
EXTI_16
Definition: gd32f3x0_exti.h:205
EXTI_0
Definition: gd32f3x0_exti.h:189
EXTI_21
Definition: gd32f3x0_exti.h:210
EXTI_3
Definition: gd32f3x0_exti.h:192
enum exti_mode_enum
Enumerator
EXTI_INTERRUPT | EXTI interrupt mode
EXTI_EVENT | EXTI event mode

Definition at line 220 of file gd32f3x0_exti.h.

221 {
222 EXTI_INTERRUPT = 0,
223 EXTI_EVENT
224 }exti_mode_enum;
EXTI_EVENT
Definition: gd32f3x0_exti.h:223
exti_mode_enum
exti_mode_enum
Definition: gd32f3x0_exti.h:220
EXTI_INTERRUPT
Definition: gd32f3x0_exti.h:222
enum exti_trig_type_enum
Enumerator
EXTI_TRIG_RISING | EXTI rising edge trigger
EXTI_TRIG_FALLING | EXTI falling edge trigger
EXTI_TRIG_BOTH | EXTI rising and falling edge trigger

Definition at line 227 of file gd32f3x0_exti.h.

228 {
229 EXTI_TRIG_RISING = 0,
230 EXTI_TRIG_FALLING,
231 EXTI_TRIG_BOTH
232 }exti_trig_type_enum;
EXTI_TRIG_FALLING
Definition: gd32f3x0_exti.h:230
exti_trig_type_enum
exti_trig_type_enum
Definition: gd32f3x0_exti.h:227
EXTI_TRIG_BOTH
Definition: gd32f3x0_exti.h:231
EXTI_TRIG_RISING
Definition: gd32f3x0_exti.h:229

Function Documentation

void exti_deinit ( void )

deinitialize the EXTI

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_exti.c.

21 {
22 /* reset the value of all the EXTI registers */
23 EXTI_INTEN = (uint32_t)0x0F940000U;
24 EXTI_EVEN = (uint32_t)0x00000000U;
25 EXTI_RTEN = (uint32_t)0x00000000U;
26 EXTI_FTEN = (uint32_t)0x00000000U;
27 EXTI_SWIEV = (uint32_t)0x00000000U;
28 }
EXTI_SWIEV
#define EXTI_SWIEV
Definition: gd32f3x0_exti.h:25
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f3x0_exti.h:22
EXTI_FTEN
#define EXTI_FTEN
Definition: gd32f3x0_exti.h:24
EXTI_RTEN
#define EXTI_RTEN
Definition: gd32f3x0_exti.h:23
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f3x0_exti.h:21
void exti_event_disable ( exti_line_enum linex )

disable the events from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..27): EXTI line x
[out] none
Return values
none

Definition at line 135 of file gd32f3x0_exti.c.

136 {
137 EXTI_EVEN &= ~(uint32_t)linex;
138 }
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f3x0_exti.h:22
void exti_event_enable ( exti_line_enum linex )

enable the events from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..27): EXTI line x
[out] none
Return values
none

Definition at line 109 of file gd32f3x0_exti.c.

110 {
111 EXTI_EVEN |= (uint32_t)linex;
112 }
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f3x0_exti.h:22
void exti_flag_clear ( exti_line_enum linex )

clear EXTI lines pending flag

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19,21,22): EXTI line x
[out] none
Return values
none

Definition at line 165 of file gd32f3x0_exti.c.

166 {
167 EXTI_PD = (uint32_t)linex;
168 }
EXTI_PD
#define EXTI_PD
Definition: gd32f3x0_exti.h:26
FlagStatus exti_flag_get ( exti_line_enum linex )

get EXTI lines flag

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19,21,22): EXTI line x
[out] none
Return values
FlagStatus status of flag (RESET or SET)

Definition at line 148 of file gd32f3x0_exti.c.

149 {
150 if(RESET != (EXTI_PD & (uint32_t)linex)){
151 return SET;
152 }else{
153 return RESET;
154 }
155 }
EXTI_PD
#define EXTI_PD
Definition: gd32f3x0_exti.h:26
void exti_init | ( | exti_line_enum | linex,
 |  | exti_mode_enum | mode,
 |  | exti_trig_type_enum | trig_type
 | ) |  |

initialize the EXTI

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19,21,22): EXTI line x
[in] mode interrupt or event mode, refer to exti_mode_enum only one parameter can be selected which is shown as below:
  • EXTI_INTERRUPT: interrupt mode
  • EXTI_EVENT: event mode
[in] trig_type interrupt trigger type, refer to exti_trig_type_enum only one parameter can be selected which is shown as below:
  • EXTI_TRIG_RISING: rising edge trigger
  • EXTI_TRIG_FALLING: falling trigger
  • EXTI_TRIG_BOTH: rising and falling trigger
[out] none
Return values
none

Definition at line 47 of file gd32f3x0_exti.c.

50 {
51 /* reset the EXTI line x */
52 EXTI_INTEN &= ~(uint32_t)linex;
53 EXTI_EVEN &= ~(uint32_t)linex;
54 EXTI_RTEN &= ~(uint32_t)linex;
55 EXTI_FTEN &= ~(uint32_t)linex;
56
57 /* set the EXTI mode and enable the interrupts or events from EXTI line x */
58 switch(mode){
59 case EXTI_INTERRUPT:
60 EXTI_INTEN |= (uint32_t)linex;
61 break;
62 case EXTI_EVENT:
63 EXTI_EVEN |= (uint32_t)linex;
64 break;
65 default:
66 break;
67 }
68
69 /* set the EXTI trigger type */
70 switch(trig_type){
71 case EXTI_TRIG_RISING:
72 EXTI_RTEN |= (uint32_t)linex;
73 EXTI_FTEN &= ~(uint32_t)linex;
74 break;
75 case EXTI_TRIG_FALLING:
76 EXTI_RTEN &= ~(uint32_t)linex;
77 EXTI_FTEN |= (uint32_t)linex;
78 break;
79 case EXTI_TRIG_BOTH:
80 EXTI_RTEN |= (uint32_t)linex;
81 EXTI_FTEN |= (uint32_t)linex;
82 break;
83 default:
84 break;
85 }
86 }
EXTI_TRIG_FALLING
Definition: gd32f3x0_exti.h:230
EXTI_EVENT
Definition: gd32f3x0_exti.h:223
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f3x0_exti.h:22
EXTI_FTEN
#define EXTI_FTEN
Definition: gd32f3x0_exti.h:24
EXTI_RTEN
#define EXTI_RTEN
Definition: gd32f3x0_exti.h:23
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f3x0_exti.h:21
EXTI_INTERRUPT
Definition: gd32f3x0_exti.h:222
EXTI_TRIG_BOTH
Definition: gd32f3x0_exti.h:231
EXTI_TRIG_RISING
Definition: gd32f3x0_exti.h:229
void exti_interrupt_disable ( exti_line_enum linex )

disable the interrupt from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..27): EXTI line x
[out] none
Return values
none

Definition at line 122 of file gd32f3x0_exti.c.

123 {
124 EXTI_INTEN &= ~(uint32_t)linex;
125 }
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f3x0_exti.h:21
void exti_interrupt_enable ( exti_line_enum linex )

enable the interrupts from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..27): EXTI line x
[out] none
Return values
none

Definition at line 96 of file gd32f3x0_exti.c.

97 {
98 EXTI_INTEN |= (uint32_t)linex;
99 }
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f3x0_exti.h:21
void exti_interrupt_flag_clear ( exti_line_enum linex )

clear EXTI lines pending flag

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19,21,22): EXTI line x
[out] none
Return values
none

Definition at line 200 of file gd32f3x0_exti.c.

201 {
202 EXTI_PD = (uint32_t)linex;
203 }
EXTI_PD
#define EXTI_PD
Definition: gd32f3x0_exti.h:26
FlagStatus exti_interrupt_flag_get ( exti_line_enum linex )

get EXTI lines flag when the interrupt flag is set

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19,21,22): EXTI line x
[out] none
Return values
FlagStatus status of flag (RESET or SET)

Definition at line 178 of file gd32f3x0_exti.c.

179 {
180 uint32_t flag_left, flag_right;
181
182 flag_left = EXTI_PD & (uint32_t)linex;
183 flag_right = EXTI_INTEN & (uint32_t)linex;
184
185 if((RESET != flag_left) && (RESET != flag_right)){
186 return SET;
187 }else{
188 return RESET;
189 }
190 }
EXTI_PD
#define EXTI_PD
Definition: gd32f3x0_exti.h:26
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f3x0_exti.h:21
void exti_software_interrupt_disable ( exti_line_enum linex )

disable EXTI software interrupt event

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19,21,22): EXTI line x
[out] none
Return values
none

Definition at line 226 of file gd32f3x0_exti.c.

227 {
228 EXTI_SWIEV &= ~(uint32_t)linex;
229 }
EXTI_SWIEV
#define EXTI_SWIEV
Definition: gd32f3x0_exti.h:25
void exti_software_interrupt_enable ( exti_line_enum linex )

enable EXTI software interrupt event

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19,21,22): EXTI line x
[out] none
Return values
none

Definition at line 213 of file gd32f3x0_exti.c.

214 {
215 EXTI_SWIEV |= (uint32_t)linex;
216 }
EXTI_SWIEV
#define EXTI_SWIEV
Definition: gd32f3x0_exti.h:25
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_fmc.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Enumerations | Functions
gd32f3x0_fmc.h File Reference

definitions for the FMC More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | FMC FMC_BASE
#define | OB OB_BASE
#define | FMC_WS REG32((FMC) + 0x00U)
#define | FMC_KEY REG32((FMC) + 0x04U)
#define | FMC_OBKEY REG32((FMC) + 0x08U)
#define | FMC_STAT REG32((FMC) + 0x0CU)
#define | FMC_CTL REG32((FMC) + 0x10U)
#define | FMC_ADDR REG32((FMC) + 0x14U)
#define | FMC_OBSTAT REG32((FMC) + 0x1CU)
#define | FMC_WP REG32((FMC) + 0x20U)
#define | FMC_WSEN REG32((FMC) + 0xFCU)
#define | FMC_PID REG32((FMC) + 0x100U)
#define | OB_SPC REG16((OB) + 0x00U)
#define | OB_USER REG16((OB) + 0x02U)
#define | OB_WP0 REG16((OB) + 0x08U)
#define | OB_WP1 REG16((OB) + 0x0AU)
#define | FMC_WS_WSCNT BITS(0,2)
#define | FMC_KEY_KEY BITS(0,31)
#define | FMC_OBKEY_OBKEY BITS(0,31)
#define | FMC_STAT_BUSY BIT(0)
#define | FMC_STAT_PGERR BIT(2)
#define | FMC_STAT_WPERR BIT(4)
#define | FMC_STAT_ENDF BIT(5)
#define | FMC_CTL_PG BIT(0)
#define | FMC_CTL_PER BIT(1)
#define | FMC_CTL_MER BIT(2)
#define | FMC_CTL_OBPG BIT(4)
#define | FMC_CTL_OBER BIT(5)
#define | FMC_CTL_START BIT(6)
#define | FMC_CTL_LK BIT(7)
#define | FMC_CTL_OBWEN BIT(9)
#define | FMC_CTL_ERRIE BIT(10)
#define | FMC_CTL_ENDIE BIT(12)
#define | FMC_CTL_OBRLD BIT(13)
#define | FMC_ADDR_ADDR BITS(0,31)
#define | FMC_OBSTAT_OBERR BIT(0)
#define | FMC_OBSTAT_PLVL_BIT0 BIT(1)
#define | FMC_OBSTAT_PLVL_BIT1 BIT(2)
#define | FMC_OBSTAT_USER BITS(8,15)
#define | FMC_OBSTAT_DATA BITS(16,31)
#define | FMC_WSEN_WSEN BIT(0)
#define | FMC_WSEN_BPEN BIT(1)
#define | FMC_PID_PID BITS(0,31)
#define | UNLOCK_KEY0 ((uint32_t)0x45670123U)
#define | UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU)
#define | WS_WSCNT_0 ((uint8_t)0x00U)
#define | WS_WSCNT_1 ((uint8_t)0x01U)
#define | WS_WSCNT_2 ((uint8_t)0x02U)
#define | FMC_NSPC ((uint8_t)0xA5U)
#define | FMC_LSPC ((uint8_t)0xBBU)
#define | FMC_HSPC ((uint8_t)0xCCU)
#define | OB_LWP ((uint32_t)0x000000FFU)
#define | OB_HWP ((uint32_t)0x0000FF00U)
#define | OBUSER_NWDG_HW(regval) (BIT(0) & ((uint32_t)(regval) << 0))
#define | OB_FWDGT_HW OBUSER_NWDG_HW(0)
#define | OB_FWDGT_SW OBUSER_NWDG_HW(1)
#define | OBUSER_NRST_DPSLP(regval) (BIT(1) & ((uint32_t)(regval) << 1))
#define | OB_DEEPSLEEP_RST OBUSER_NRST_DPSLP(0)
#define | OB_DEEPSLEEP_NRST OBUSER_NRST_DPSLP(1)
#define | OBUSER_NRST_STDBY(regval) (BIT(2) & ((uint32_t)(regval) << 2))
#define | OB_STDBY_RST OBUSER_NRST_STDBY(0)
#define | OB_STDBY_NRST OBUSER_NRST_STDBY(1)
#define | OBUSER_BOOT1_N(regval) (BIT(4) & ((uint32_t)(regval) << 4))
#define | OB_BOOT1_SET_1 OBUSER_BOOT1_N(0)
#define | OB_BOOT1_SET_0 OBUSER_BOOT1_N(1)
#define | OBUSER_VDDA_VISOR(regval) (BIT(5) & ((uint32_t)(regval) << 5))
#define | OB_VDDA_DISABLE OBUSER_VDDA_VISOR(0)
#define | OB_VDDA_ENABLE OBUSER_VDDA_VISOR(1)
#define | OBUSER_SRAM_PARITY(regval) (BIT(6) & ((uint32_t)(regval) << 6))
#define | OB_SRAM_PARITY_ENABLE OBUSER_SRAM_PARITY(0)
#define | OB_SRAM_PARITY_DISABLE OBUSER_SRAM_PARITY(1)
#define | OB_OBSTAT_PLEVEL_NO ((uint32_t)0x00000000U)
#define | OB_OBSTAT_PLEVEL_LOW ((uint32_t)0x00000002U)
#define | OB_OBSTAT_PLEVEL_HIGH ((uint32_t)0x00000006U)
#define | OB_USER_MASK ((uint8_t)0x88U)
#define | OB_DATA_ADDR0 ((uint32_t)0x1FFFF804U)
#define | OB_DATA_ADDR1 ((uint32_t)0x1FFFF806U)
#define | FMC_FLAG_BUSY FMC_STAT_BUSY
#define | FMC_FLAG_PGERR FMC_STAT_PGERR
#define | FMC_FLAG_WPERR FMC_STAT_WPERR
#define | FMC_FLAG_END FMC_STAT_ENDF
#define | FMC_INTEN_END FMC_CTL_ENDIE
#define | FMC_INTEN_ERR FMC_CTL_ERRIE
#define | FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U)

Enumerations

enum fmc_state_enum {
FMC_READY, FMC_BUSY, FMC_PGERR, FMC_WPERR,
FMC_TOERR, FMC_OB_HSPC
}

Functions

void | fmc_unlock (void)
unlock the main FMC operation it is better to used in pairs with fmc_lock More...
void | fmc_lock (void)
lock the main FMC operation it is better to used in pairs with fmc_unlock after an operation More...
void | fmc_wscnt_set (uint8_t wscnt)
set the wait state counter value More...
void | fmc_wait_state_enable (void)
fmc wait state enable More...
void | fmc_wait_state_disable (void)
fmc wait state disable More...
fmc_state_enum | fmc_page_erase (uint32_t page_address)
erase page More...
fmc_state_enum | fmc_mass_erase (void)
erase whole chip More...
fmc_state_enum | fmc_word_program (uint32_t address, uint32_t data)
program a word at the corresponding address More...
fmc_state_enum | fmc_halfword_program (uint32_t address, uint16_t data)
program a half word at the corresponding address More...
fmc_state_enum | fmc_word_reprogram (uint32_t address, uint32_t data)
program a word at the corresponding address without erasing More...
void | ob_unlock (void)
unlock the option byte operation it is better to used in pairs with ob_lock More...
void | ob_lock (void)
lock the option byte operation it is better to used in pairs with ob_unlock after an operation More...
void | ob_reset (void)
reload the option byte and generate a system reset More...
fmc_state_enum | ob_erase (void)
erase the option byte programmer must ensure FMC & option byte are both unlocked before calling this function More...
fmc_state_enum | ob_write_protection_enable (uint32_t ob_wp)
enable option byte write protection (OB_WP) More...
fmc_state_enum | ob_security_protection_config (uint8_t ob_spc)
configure security protection More...
fmc_state_enum | ob_user_write (uint8_t ob_user)
program the FMC user option byte More...
fmc_state_enum | ob_data_program (uint32_t address, uint8_t data)
program the FMC data option byte More...
uint8_t | ob_user_get (void)
get OB_USER in register FMC_OBSTAT More...
uint16_t | ob_data_get (void)
get OB_DATA in register FMC_OBSTAT More...
uint16_t | ob_write_protection_get (void)
get the FMC option byte write protection (OB_WP) in register FMC_WP More...
uint32_t | ob_obstat_plevel_get (void)
get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register More...
void | fmc_interrupt_enable (uint32_t interrupt)
enable FMC interrupt More...
void | fmc_interrupt_disable (uint32_t interrupt)
disable FMC interrupt More...
FlagStatus | fmc_flag_get (uint32_t flag)
get flag set or reset More...
void | fmc_flag_clear (uint32_t flag)
clear the FMC pending flag by writing 1 More...
fmc_state_enum | fmc_state_get (void)
get the FMC state More...
fmc_state_enum | fmc_ready_wait (uint32_t timeout)
check whether FMC is ready or not More...

Detailed Description

definitions for the FMC

Definition in file gd32f3x0_fmc.h.

Macro Definition Documentation

#define FMC FMC_BASE

FMC register base address

Definition at line 18 of file gd32f3x0_fmc.h.

#define FMC_ADDR REG32((FMC) + 0x14U)

FMC address register

Definition at line 27 of file gd32f3x0_fmc.h.

#define FMC_ADDR_ADDR BITS(0,31)

flash command address bits

Definition at line 68 of file gd32f3x0_fmc.h.

#define FMC_CTL REG32((FMC) + 0x10U)

FMC control register

Definition at line 26 of file gd32f3x0_fmc.h.

#define FMC_CTL_ENDIE BIT(12)

end of operation interrupt enable bit

Definition at line 64 of file gd32f3x0_fmc.h.

#define FMC_CTL_ERRIE BIT(10)

error interrupt enable bit

Definition at line 63 of file gd32f3x0_fmc.h.

#define FMC_CTL_LK BIT(7)

flash lock bit

Definition at line 61 of file gd32f3x0_fmc.h.

#define FMC_CTL_MER BIT(2)

main flash mass erase bit

Definition at line 57 of file gd32f3x0_fmc.h.

#define FMC_CTL_OBER BIT(5)

option bytes erase command bit

Definition at line 59 of file gd32f3x0_fmc.h.

#define FMC_CTL_OBPG BIT(4)

option bytes program command bit

Definition at line 58 of file gd32f3x0_fmc.h.

#define FMC_CTL_OBRLD BIT(13)

option bytes reload bit

Definition at line 65 of file gd32f3x0_fmc.h.

#define FMC_CTL_OBWEN BIT(9)

option bytes erase/program enable bit

Definition at line 62 of file gd32f3x0_fmc.h.

#define FMC_CTL_PER BIT(1)

main flash page erase bit

Definition at line 56 of file gd32f3x0_fmc.h.

#define FMC_CTL_PG BIT(0)

main flash program command bit

Definition at line 55 of file gd32f3x0_fmc.h.

#define FMC_CTL_START BIT(6)

send erase command to FMC bit

Definition at line 60 of file gd32f3x0_fmc.h.

#define FMC_FLAG_BUSY FMC_STAT_BUSY

FMC busy flag

Definition at line 157 of file gd32f3x0_fmc.h.

#define FMC_FLAG_END FMC_STAT_ENDF

FMC end of programming flag

Definition at line 160 of file gd32f3x0_fmc.h.

#define FMC_FLAG_PGERR FMC_STAT_PGERR

FMC programming error flag

Definition at line 158 of file gd32f3x0_fmc.h.

#define FMC_FLAG_WPERR FMC_STAT_WPERR

FMC write protection error flag

Definition at line 159 of file gd32f3x0_fmc.h.

#define FMC_HSPC ((uint8_t)0xCCU)

high security protection

Definition at line 108 of file gd32f3x0_fmc.h.

#define FMC_INTEN_END FMC_CTL_ENDIE

enable FMC end of operation interrupt

Definition at line 163 of file gd32f3x0_fmc.h.

#define FMC_INTEN_ERR FMC_CTL_ERRIE

enable FMC error interrupt

Definition at line 164 of file gd32f3x0_fmc.h.

#define FMC_KEY REG32((FMC) + 0x04U)

FMC unlock key register

Definition at line 23 of file gd32f3x0_fmc.h.

#define FMC_KEY_KEY BITS(0,31)

FMC main flash unlock key bits

Definition at line 43 of file gd32f3x0_fmc.h.

#define FMC_LSPC ((uint8_t)0xBBU)

low security protection, any value except 0xA5 or 0xCC

Definition at line 107 of file gd32f3x0_fmc.h.

#define FMC_NSPC ((uint8_t)0xA5U)

no security protection

Definition at line 106 of file gd32f3x0_fmc.h.

#define FMC_OBKEY REG32((FMC) + 0x08U)

FMC option bytes unlock key register

Definition at line 24 of file gd32f3x0_fmc.h.

#define FMC_OBKEY_OBKEY BITS(0,31)

option bytes unlock key bits

Definition at line 46 of file gd32f3x0_fmc.h.

#define FMC_OBSTAT REG32((FMC) + 0x1CU)

FMC option bytes status register

Definition at line 28 of file gd32f3x0_fmc.h.

#define FMC_OBSTAT_DATA BITS(16,31)

option byte data bits

Definition at line 75 of file gd32f3x0_fmc.h.

#define FMC_OBSTAT_OBERR BIT(0)

option bytes read error bit

Definition at line 71 of file gd32f3x0_fmc.h.

#define FMC_OBSTAT_PLVL_BIT0 BIT(1)

protection level bit 0

Definition at line 72 of file gd32f3x0_fmc.h.

#define FMC_OBSTAT_PLVL_BIT1 BIT(2)

protection level bit 1

Definition at line 73 of file gd32f3x0_fmc.h.

#define FMC_OBSTAT_USER BITS(8,15)

option bytes user bits

Definition at line 74 of file gd32f3x0_fmc.h.

#define FMC_PID REG32((FMC) + 0x100U)

FMC product ID register

Definition at line 31 of file gd32f3x0_fmc.h.

#define FMC_PID_PID BITS(0,31)

product ID bits

Definition at line 82 of file gd32f3x0_fmc.h.

#define FMC_STAT REG32((FMC) + 0x0CU)

FMC status register

Definition at line 25 of file gd32f3x0_fmc.h.

#define FMC_STAT_BUSY BIT(0)

flash busy flag bit

Definition at line 49 of file gd32f3x0_fmc.h.

#define FMC_STAT_ENDF BIT(5)

end of operation flag bit

Definition at line 52 of file gd32f3x0_fmc.h.

#define FMC_STAT_PGERR BIT(2)

flash program error flag bit

Definition at line 50 of file gd32f3x0_fmc.h.

#define FMC_STAT_WPERR BIT(4)

flash write protection error flag bit

Definition at line 51 of file gd32f3x0_fmc.h.

#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U)

count to judge of FMC timeout

Definition at line 167 of file gd32f3x0_fmc.h.

#define FMC_WP REG32((FMC) + 0x20U)

FMC write protection register

Definition at line 29 of file gd32f3x0_fmc.h.

#define FMC_WS REG32((FMC) + 0x00U)

FMC wait state register

Definition at line 22 of file gd32f3x0_fmc.h.

#define FMC_WS_WSCNT BITS(0,2)

wait state counter

Definition at line 40 of file gd32f3x0_fmc.h.

#define FMC_WSEN REG32((FMC) + 0xFCU)

FMC wait state enable register

Definition at line 30 of file gd32f3x0_fmc.h.

#define FMC_WSEN_BPEN BIT(1)

FMC bit program enable bit

Definition at line 79 of file gd32f3x0_fmc.h.

#define FMC_WSEN_WSEN BIT(0)

FMC wait state enable bit

Definition at line 78 of file gd32f3x0_fmc.h.

#define OB OB_BASE

option byte base address

Definition at line 19 of file gd32f3x0_fmc.h.

#define OB_BOOT1_SET_0 OBUSER_BOOT1_N(1)

BOOT1 bit is 0

Definition at line 132 of file gd32f3x0_fmc.h.

#define OB_BOOT1_SET_1 OBUSER_BOOT1_N(0)

BOOT1 bit is 1

Definition at line 131 of file gd32f3x0_fmc.h.

#define OB_DATA_ADDR0 ((uint32_t)0x1FFFF804U)

option byte data address 0

Definition at line 153 of file gd32f3x0_fmc.h.

#define OB_DATA_ADDR1 ((uint32_t)0x1FFFF806U)

option byte data address 1

Definition at line 154 of file gd32f3x0_fmc.h.

#define OB_DEEPSLEEP_NRST OBUSER_NRST_DPSLP(1)

no reset when entering deepsleep mode

Definition at line 122 of file gd32f3x0_fmc.h.

#define OB_DEEPSLEEP_RST OBUSER_NRST_DPSLP(0)

generate a reset instead of entering deepsleep mode

Definition at line 121 of file gd32f3x0_fmc.h.

#define OB_FWDGT_HW OBUSER_NWDG_HW(0)

hardware free watchdog timer

Definition at line 116 of file gd32f3x0_fmc.h.

#define OB_FWDGT_SW OBUSER_NWDG_HW(1)

software free watchdog timer

Definition at line 117 of file gd32f3x0_fmc.h.

#define OB_HWP ((uint32_t)0x0000FF00U)

write protection high bits

Definition at line 112 of file gd32f3x0_fmc.h.

#define OB_LWP ((uint32_t)0x000000FFU)

write protection low bits

Definition at line 111 of file gd32f3x0_fmc.h.

#define OB_OBSTAT_PLEVEL_HIGH ((uint32_t)0x00000006U)

high security protection

Definition at line 147 of file gd32f3x0_fmc.h.

#define OB_OBSTAT_PLEVEL_LOW ((uint32_t)0x00000002U)

low security protection

Definition at line 146 of file gd32f3x0_fmc.h.

#define OB_OBSTAT_PLEVEL_NO ((uint32_t)0x00000000U)

no security protection

Definition at line 145 of file gd32f3x0_fmc.h.

#define OB_SPC REG16((OB) + 0x00U)

option byte security protection value

Definition at line 33 of file gd32f3x0_fmc.h.

#define OB_SRAM_PARITY_DISABLE OBUSER_SRAM_PARITY(1)

disable SRAM parity check

Definition at line 142 of file gd32f3x0_fmc.h.

#define OB_SRAM_PARITY_ENABLE OBUSER_SRAM_PARITY(0)

enable SRAM parity check

Definition at line 141 of file gd32f3x0_fmc.h.

#define OB_STDBY_NRST OBUSER_NRST_STDBY(1)

no reset when entering deepsleep mode

Definition at line 127 of file gd32f3x0_fmc.h.

#define OB_STDBY_RST OBUSER_NRST_STDBY(0)

generate a reset instead of entering standby mode

Definition at line 126 of file gd32f3x0_fmc.h.

#define OB_USER REG16((OB) + 0x02U)

option byte user value

Definition at line 34 of file gd32f3x0_fmc.h.

#define OB_USER_MASK ((uint8_t)0x88U)

OB_USER reserved bit mask

Definition at line 150 of file gd32f3x0_fmc.h.

#define OB_VDDA_DISABLE OBUSER_VDDA_VISOR(0)

disable VDDA monitor

Definition at line 136 of file gd32f3x0_fmc.h.

#define OB_VDDA_ENABLE OBUSER_VDDA_VISOR(1)

enable VDDA monitor

Definition at line 137 of file gd32f3x0_fmc.h.

#define OB_WP0 REG16((OB) + 0x08U)

option byte write protection 0

Definition at line 35 of file gd32f3x0_fmc.h.

#define OB_WP1 REG16((OB) + 0x0AU)

option byte write protection 1

Definition at line 36 of file gd32f3x0_fmc.h.

#define OBUSER_BOOT1_N ( regval ) (BIT(4) & ((uint32_t)(regval) << 4))

Definition at line 130 of file gd32f3x0_fmc.h.

#define OBUSER_NRST_DPSLP ( regval ) (BIT(1) & ((uint32_t)(regval) << 1))

Definition at line 120 of file gd32f3x0_fmc.h.

#define OBUSER_NRST_STDBY ( regval ) (BIT(2) & ((uint32_t)(regval) << 2))

Definition at line 125 of file gd32f3x0_fmc.h.

#define OBUSER_NWDG_HW ( regval ) (BIT(0) & ((uint32_t)(regval) << 0))

Definition at line 115 of file gd32f3x0_fmc.h.

#define OBUSER_SRAM_PARITY ( regval ) (BIT(6) & ((uint32_t)(regval) << 6))

Definition at line 140 of file gd32f3x0_fmc.h.

#define OBUSER_VDDA_VISOR ( regval ) (BIT(5) & ((uint32_t)(regval) << 5))

Definition at line 135 of file gd32f3x0_fmc.h.

#define UNLOCK_KEY0 ((uint32_t)0x45670123U)

unlock key 0

Definition at line 97 of file gd32f3x0_fmc.h.

#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU)

unlock key 1

Definition at line 98 of file gd32f3x0_fmc.h.

#define WS_WSCNT_0 ((uint8_t)0x00U)

0 wait state added

Definition at line 101 of file gd32f3x0_fmc.h.

#define WS_WSCNT_1 ((uint8_t)0x01U)

1 wait state added

Definition at line 102 of file gd32f3x0_fmc.h.

#define WS_WSCNT_2 ((uint8_t)0x02U)

2 wait state added

Definition at line 103 of file gd32f3x0_fmc.h.

Enumeration Type Documentation

enum fmc_state_enum
Enumerator
FMC_READY | the operation has been completed
FMC_BUSY | the operation is in progress
FMC_PGERR | program error
FMC_WPERR | erase/program protection error
FMC_TOERR | timeout error
FMC_OB_HSPC | option byte security protection code high

Definition at line 86 of file gd32f3x0_fmc.h.

87 {
88 FMC_READY,
89 FMC_BUSY,
90 FMC_PGERR,
91 FMC_WPERR,
92 FMC_TOERR,
93 FMC_OB_HSPC
94 }fmc_state_enum;
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_OB_HSPC
Definition: gd32f3x0_fmc.h:93
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
FMC_PGERR
Definition: gd32f3x0_fmc.h:90
FMC_WPERR
Definition: gd32f3x0_fmc.h:91
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
FMC_BUSY
Definition: gd32f3x0_fmc.h:89

Function Documentation

void fmc_flag_clear ( uint32_t flag )

clear the FMC pending flag by writing 1

Parameters
[in] flag clear FMC flag
  • FMC_FLAG_PGERR: FMC programming error flag
  • FMC_FLAG_WPERR: FMC write protection error flag
  • FMC_FLAG_END: fmc end of programming flag
[out] none
Return values
none

Definition at line 606 of file gd32f3x0_fmc.c.

607 {
608 /* clear the flags */
609 FMC_STAT = flag;
610 }
FMC_STAT
#define FMC_STAT
Definition: gd32f3x0_fmc.h:25
FlagStatus fmc_flag_get ( uint32_t flag )

get flag set or reset

Parameters
[in] flag check FMC flag
  • FMC_FLAG_BUSY: FMC busy flag
  • FMC_FLAG_PGERR: FMC programming error flag
  • FMC_FLAG_WPERR: FMC write protection error flag
  • FMC_FLAG_END: FMC end of programming flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 586 of file gd32f3x0_fmc.c.

587 {
588 FlagStatus status = RESET;
589
590 if(FMC_STAT & flag){
591 status = SET;
592 }
593 /* return the state of corresponding FMC flag */
594 return status;
595 }
FMC_STAT
#define FMC_STAT
Definition: gd32f3x0_fmc.h:25
fmc_state_enum fmc_halfword_program | ( | uint32_t | address,
 |  | uint16_t | data
 | ) |  |

program a half word at the corresponding address

Parameters
[in] | address | address to program
[in] | data | word to program
[out] | none
Return values
fmc_state

Definition at line 188 of file gd32f3x0_fmc.c.

189 {
190 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
191
192 if(FMC_READY == fmc_state){
193 /* set the PG bit to start program */
194 FMC_CTL |= FMC_CTL_PG;
195
196 REG16(address) = data;
197
198 /* wait for the FMC ready */
199 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
200
201 /* reset the PG bit */
202 FMC_CTL &= ~FMC_CTL_PG;
203 }
204
205 /* return the FMC state */
206 return fmc_state;
207 }
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL_PG
#define FMC_CTL_PG
Definition: gd32f3x0_fmc.h:55
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
void fmc_interrupt_disable ( uint32_t interrupt )

disable FMC interrupt

Parameters
[in] interrupt the FMC interrupt source
  • FMC_INTEN_END: FMC end of operation interrupt
  • FMC_INTEN_ERR: FMC error interrupt
[out] none
Return values
none

Definition at line 571 of file gd32f3x0_fmc.c.

572 {
573 FMC_CTL &= ~(uint32_t)interrupt;
574 }
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
void fmc_interrupt_enable ( uint32_t interrupt )

enable FMC interrupt

Parameters
[in] interrupt the FMC interrupt source
  • FMC_INTEN_END: FMC end of operation interrupt
  • FMC_INTEN_ERR: FMC error interrupt
[out] none
Return values
none

Definition at line 558 of file gd32f3x0_fmc.c.

559 {
560 FMC_CTL |= interrupt;
561 }
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
void fmc_lock ( void )

lock the main FMC operation it is better to used in pairs with fmc_unlock after an operation

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 39 of file gd32f3x0_fmc.c.

40 {
41 /* set the LK bit*/
42 FMC_CTL |= FMC_CTL_LK;
43 }
FMC_CTL_LK
#define FMC_CTL_LK
Definition: gd32f3x0_fmc.h:61
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum fmc_mass_erase ( void )

erase whole chip

Parameters
[in] | none
[out] | none
Return values
fmc_state

Definition at line 133 of file gd32f3x0_fmc.c.

134 {
135 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
136
137 if(FMC_READY == fmc_state){
138 /* start chip erase */
139 FMC_CTL |= FMC_CTL_MER;
140 FMC_CTL |= FMC_CTL_START;
141
142 /* wait for the FMC ready */
143 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
144
145 /* reset the MER bit */
146 FMC_CTL &= ~FMC_CTL_MER;
147 }
148
149 /* return the fmc state */
150 return fmc_state;
151 }
FMC_CTL_START
#define FMC_CTL_START
Definition: gd32f3x0_fmc.h:60
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL_MER
#define FMC_CTL_MER
Definition: gd32f3x0_fmc.h:57
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
fmc_state_enum fmc_page_erase ( uint32_t page_address )

erase page

Parameters
[in] | page_address | target page start address
[out] | none
Return values
fmc_state

Definition at line 106 of file gd32f3x0_fmc.c.

107 {
108 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
109
110 if(FMC_READY == fmc_state){
111 /* start page erase */
112 FMC_CTL |= FMC_CTL_PER;
113 FMC_ADDR = page_address;
114 FMC_CTL |= FMC_CTL_START;
115
116 /* wait for the FMC ready */
117 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
118
119 /* reset the PER bit */
120 FMC_CTL &= ~FMC_CTL_PER;
121 }
122
123 /* return the FMC state */
124 return fmc_state;
125 }
FMC_CTL_START
#define FMC_CTL_START
Definition: gd32f3x0_fmc.h:60
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_ADDR
#define FMC_ADDR
Definition: gd32f3x0_fmc.h:27
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
FMC_CTL_PER
#define FMC_CTL_PER
Definition: gd32f3x0_fmc.h:56
fmc_state_enum fmc_ready_wait ( uint32_t timeout )

check whether FMC is ready or not

Parameters
[in] | timeout | timeout count
[out] | none
Return values
fmc_state

Definition at line 643 of file gd32f3x0_fmc.c.

644 {
645 fmc_state_enum fmc_state = FMC_BUSY;
646
647 /* wait for FMC ready */
648 do{
649 /* get FMC state */
650 fmc_state = fmc_state_get();
651 timeout--;
652 }while((FMC_BUSY == fmc_state) && (0U != timeout));
653
654 if(FMC_BUSY == fmc_state){
655 fmc_state = FMC_TOERR;
656 }
657 /* return the FMC state */
658 return fmc_state;
659 }
fmc_state_get
fmc_state_enum fmc_state_get(void)
get the FMC state
Definition: gd32f3x0_fmc.c:618
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
FMC_BUSY
Definition: gd32f3x0_fmc.h:89
fmc_state_enum fmc_state_get ( void )

get the FMC state

Parameters
[in] | none
[out] | none
Return values
fmc_state

Definition at line 618 of file gd32f3x0_fmc.c.

619 {
620 fmc_state_enum fmc_state = FMC_READY;
621
622 if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)){
623 fmc_state = FMC_BUSY;
624 }else{
625 if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)){
626 fmc_state = FMC_WPERR;
627 }else{
628 if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGERR)){
629 fmc_state = FMC_PGERR;
630 }
631 }
632 }
633 /* return the FMC state */
634 return fmc_state;
635 }
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_STAT
#define FMC_STAT
Definition: gd32f3x0_fmc.h:25
FMC_STAT_PGERR
#define FMC_STAT_PGERR
Definition: gd32f3x0_fmc.h:50
FMC_PGERR
Definition: gd32f3x0_fmc.h:90
FMC_STAT_WPERR
#define FMC_STAT_WPERR
Definition: gd32f3x0_fmc.h:51
FMC_STAT_BUSY
#define FMC_STAT_BUSY
Definition: gd32f3x0_fmc.h:49
FMC_WPERR
Definition: gd32f3x0_fmc.h:91
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
FMC_BUSY
Definition: gd32f3x0_fmc.h:89
void fmc_unlock ( void )

unlock the main FMC operation it is better to used in pairs with fmc_lock

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 23 of file gd32f3x0_fmc.c.

24 {
25 if((RESET != (FMC_CTL & FMC_CTL_LK))){
26 /* write the FMC key */
27 FMC_KEY = UNLOCK_KEY0;
28 FMC_KEY = UNLOCK_KEY1;
29 }
30 }
UNLOCK_KEY1
#define UNLOCK_KEY1
Definition: gd32f3x0_fmc.h:98
UNLOCK_KEY0
#define UNLOCK_KEY0
Definition: gd32f3x0_fmc.h:97
FMC_KEY
#define FMC_KEY
Definition: gd32f3x0_fmc.h:23
FMC_CTL_LK
#define FMC_CTL_LK
Definition: gd32f3x0_fmc.h:61
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
void fmc_wait_state_disable ( void )

fmc wait state disable

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 88 of file gd32f3x0_fmc.c.

89 {
90 /* unlock the main flash */
91 fmc_unlock();
92
93 /* reset the WSEN bit in register FMC_WSEN */
94 FMC_WSEN &= ~FMC_WSEN_WSEN;
95
96 /* lock the main flash after operation */
97 fmc_lock();
98 }
fmc_lock
void fmc_lock(void)
lock the main FMC operation it is better to used in pairs with fmc_unlock after an operation ...
Definition: gd32f3x0_fmc.c:39
FMC_WSEN
#define FMC_WSEN
Definition: gd32f3x0_fmc.h:30
fmc_unlock
void fmc_unlock(void)
unlock the main FMC operation it is better to used in pairs with fmc_lock
Definition: gd32f3x0_fmc.c:23
FMC_WSEN_WSEN
#define FMC_WSEN_WSEN
Definition: gd32f3x0_fmc.h:78
void fmc_wait_state_enable ( void )

fmc wait state enable

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 70 of file gd32f3x0_fmc.c.

71 {
72 /* unlock the main flash */
73 fmc_unlock();
74
75 /* set the WSEN bit in register FMC_WSEN */
76 FMC_WSEN |= FMC_WSEN_WSEN;
77
78 /* lock the main flash after operation */
79 fmc_lock();
80 }
fmc_lock
void fmc_lock(void)
lock the main FMC operation it is better to used in pairs with fmc_unlock after an operation ...
Definition: gd32f3x0_fmc.c:39
FMC_WSEN
#define FMC_WSEN
Definition: gd32f3x0_fmc.h:30
fmc_unlock
void fmc_unlock(void)
unlock the main FMC operation it is better to used in pairs with fmc_lock
Definition: gd32f3x0_fmc.c:23
FMC_WSEN_WSEN
#define FMC_WSEN_WSEN
Definition: gd32f3x0_fmc.h:78
fmc_state_enum fmc_word_program | ( | uint32_t | address,
 |  | uint32_t | data
 | ) |  |

program a word at the corresponding address

Parameters
[in] | address | address to program
[in] | data | word to program
[out] | none
Return values
fmc_state

Definition at line 160 of file gd32f3x0_fmc.c.

161 {
162 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
163
164 if(FMC_READY == fmc_state){
165 /* set the PG bit to start program */
166 FMC_CTL |= FMC_CTL_PG;
167
168 REG32(address) = data;
169
170 /* wait for the FMC ready */
171 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
172
173 /* reset the PG bit */
174 FMC_CTL &= ~FMC_CTL_PG;
175 }
176
177 /* return the FMC state */
178 return fmc_state;
179 }
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL_PG
#define FMC_CTL_PG
Definition: gd32f3x0_fmc.h:55
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
fmc_state_enum fmc_word_reprogram | ( | uint32_t | address,
 |  | uint32_t | data
 | ) |  |

program a word at the corresponding address without erasing

Parameters
[in] | address | address to program
[in] | data | word to program
[out] | none
Return values
fmc_state

Definition at line 216 of file gd32f3x0_fmc.c.

217 {
218 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
219 FMC_WSEN |= FMC_WSEN_BPEN;
220
221 if(FMC_READY == fmc_state){
222 /* set the PG bit to start program */
223 FMC_CTL |= FMC_CTL_PG;
224
225 REG32(address) = data;
226
227 /* wait for the FMC ready */
228 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
229
230 /* reset the PG bit */
231 FMC_CTL &= ~FMC_CTL_PG;
232 }
233
234 /* return the FMC state */
235 return fmc_state;
236 }
FMC_WSEN
#define FMC_WSEN
Definition: gd32f3x0_fmc.h:30
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_WSEN_BPEN
#define FMC_WSEN_BPEN
Definition: gd32f3x0_fmc.h:79
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL_PG
#define FMC_CTL_PG
Definition: gd32f3x0_fmc.h:55
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
void fmc_wscnt_set ( uint8_t wscnt )

set the wait state counter value

Parameters
[in] wscnt wait state counter value
  • WS_WSCNT_0: 0 wait state added
  • WS_WSCNT_1: 1 wait state added
  • WS_WSCNT_2: 2 wait state added
[out] none
Return values
none

Definition at line 54 of file gd32f3x0_fmc.c.

55 {
56 uint32_t reg;
57
58 reg = FMC_WS;
59 /* set the wait state counter value */
60 reg &= ~FMC_WS_WSCNT;
61 FMC_WS = (reg | wscnt);
62 }
FMC_WS_WSCNT
#define FMC_WS_WSCNT
Definition: gd32f3x0_fmc.h:40
FMC_WS
#define FMC_WS
Definition: gd32f3x0_fmc.h:22
uint16_t ob_data_get ( void )

get OB_DATA in register FMC_OBSTAT

Parameters
[in] | none
[out] | none
Return values
ob_data

Definition at line 522 of file gd32f3x0_fmc.c.

523 {
524 return (uint16_t)(FMC_OBSTAT >> 16);
525 }
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f3x0_fmc.h:28
fmc_state_enum ob_data_program | ( | uint32_t | address,
 |  | uint8_t | data
 | ) |  |

program the FMC data option byte

Parameters
[in] address OB_DATA_ADDR0 or OB_DATA_ADDR1
  • OB_DATA_ADDR0: option byte data address 0
  • OB_DATA_ADDR1: option byte data address 1
[in] | data | the byte to be programmed
[out] | none
Return values
fmc_state

Definition at line 484 of file gd32f3x0_fmc.c.

485 {
486 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
487
488 if(FMC_READY == fmc_state){
489 /* set the OBPG bit */
490 FMC_CTL |= FMC_CTL_OBPG;
491 REG16(address) = data;
492
493 /* wait for the FMC ready */
494 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
495
496 if(FMC_TOERR != fmc_state){
497 /* reset the OBPG bit */
498 FMC_CTL &= ~FMC_CTL_OBPG;
499 }
500 }
501 /* return the FMC state */
502 return fmc_state;
503 }
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
FMC_CTL_OBPG
#define FMC_CTL_OBPG
Definition: gd32f3x0_fmc.h:58
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
fmc_state_enum ob_erase ( void )

erase the option byte programmer must ensure FMC & option byte are both unlocked before calling this function

Parameters
[in] | none
[out] | none
Return values
fmc_state

Definition at line 288 of file gd32f3x0_fmc.c.

289 {
290 uint16_t fmc_spc;
291 uint32_t fmc_plevel = ob_obstat_plevel_get();
292 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
293
294 /* get the original option byte security protection code */
295 if(OB_OBSTAT_PLEVEL_NO == fmc_plevel){
296 fmc_spc = FMC_NSPC;
297 }else if(OB_OBSTAT_PLEVEL_LOW == fmc_plevel){
298 fmc_spc = FMC_LSPC;
299 }else{
300 fmc_spc = FMC_HSPC;
301 fmc_state = FMC_OB_HSPC;
302 }
303
304 if(FMC_READY == fmc_state){
305 /* start erase the option byte */
306 FMC_CTL |= FMC_CTL_OBER;
307 FMC_CTL |= FMC_CTL_START;
308
309 /* wait for the FMC ready */
310 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
311
312 if(FMC_READY == fmc_state){
313 /* reset the OBER bit */
314 FMC_CTL &= ~FMC_CTL_OBER;
315
316 /* set the OBPG bit */
317 FMC_CTL |= FMC_CTL_OBPG;
318
319 /* restore the last get option byte security protection code */
320 OB_SPC = fmc_spc;
321
322 /* wait for the FMC ready */
323 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
324
325 if(FMC_TOERR != fmc_state){
326 /* reset the OBPG bit */
327 FMC_CTL &= ~FMC_CTL_OBPG;
328 }
329 }else{
330 if(FMC_TOERR != fmc_state){
331 /* reset the OBPG bit */
332 FMC_CTL &= ~FMC_CTL_OBPG;
333 }
334 }
335 }
336 /* return the FMC state */
337 return fmc_state;
338 }
FMC_CTL_START
#define FMC_CTL_START
Definition: gd32f3x0_fmc.h:60
OB_OBSTAT_PLEVEL_NO
#define OB_OBSTAT_PLEVEL_NO
Definition: gd32f3x0_fmc.h:145
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_LSPC
#define FMC_LSPC
Definition: gd32f3x0_fmc.h:107
OB_SPC
#define OB_SPC
Definition: gd32f3x0_fmc.h:33
FMC_OB_HSPC
Definition: gd32f3x0_fmc.h:93
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
OB_OBSTAT_PLEVEL_LOW
#define OB_OBSTAT_PLEVEL_LOW
Definition: gd32f3x0_fmc.h:146
FMC_CTL_OBPG
#define FMC_CTL_OBPG
Definition: gd32f3x0_fmc.h:58
ob_obstat_plevel_get
uint32_t ob_obstat_plevel_get(void)
get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register ...
Definition: gd32f3x0_fmc.c:544
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
FMC_HSPC
#define FMC_HSPC
Definition: gd32f3x0_fmc.h:108
FMC_NSPC
#define FMC_NSPC
Definition: gd32f3x0_fmc.h:106
FMC_CTL_OBER
#define FMC_CTL_OBER
Definition: gd32f3x0_fmc.h:59
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
void ob_lock ( void )

lock the option byte operation it is better to used in pairs with ob_unlock after an operation

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 263 of file gd32f3x0_fmc.c.

264 {
265 /* reset the OBWE bit */
266 FMC_CTL &= ~FMC_CTL_OBWEN;
267 }
FMC_CTL_OBWEN
#define FMC_CTL_OBWEN
Definition: gd32f3x0_fmc.h:62
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
uint32_t ob_obstat_plevel_get ( void )

get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register

Parameters
[in] | none
[out] | none
Return values
the value of PLEVEL

Definition at line 544 of file gd32f3x0_fmc.c.

545 {
546 return (FMC_OBSTAT & (FMC_OBSTAT_PLVL_BIT0 | FMC_OBSTAT_PLVL_BIT1));
547 }
FMC_OBSTAT_PLVL_BIT1
#define FMC_OBSTAT_PLVL_BIT1
Definition: gd32f3x0_fmc.h:73
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f3x0_fmc.h:28
FMC_OBSTAT_PLVL_BIT0
#define FMC_OBSTAT_PLVL_BIT0
Definition: gd32f3x0_fmc.h:72
void ob_reset ( void )

reload the option byte and generate a system reset

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 275 of file gd32f3x0_fmc.c.

276 {
277 /* set the OBRLD bit */
278 FMC_CTL |= FMC_CTL_OBRLD;
279 }
FMC_CTL_OBRLD
#define FMC_CTL_OBRLD
Definition: gd32f3x0_fmc.h:65
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum ob_security_protection_config ( uint8_t ob_spc )

configure security protection

Parameters
[in] ob_spc specify security protection code
  • FMC_NSPC: no security protection
  • FMC_LSPC: low security protection
  • FMC_HSPC: high security protection
[out] none
Return values
fmc_state

Definition at line 390 of file gd32f3x0_fmc.c.

391 {
392 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
393
394 /* the OB_SPC byte cannot be reprogrammed if protection level is high */
395 if(OB_OBSTAT_PLEVEL_HIGH == ob_obstat_plevel_get()){
396 fmc_state = FMC_OB_HSPC;
397 }
398
399 if(FMC_READY == fmc_state){
400 /* start erase the option byte */
401 FMC_CTL |= FMC_CTL_OBER;
402 FMC_CTL |= FMC_CTL_START;
403
404 /* wait for the FMC ready */
405 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
406
407 if(FMC_READY == fmc_state){
408
409 /* reset the OBER bit */
410 FMC_CTL &= ~FMC_CTL_OBER;
411
412 /* enable the option bytes programming */
413 FMC_CTL |= FMC_CTL_OBPG;
414
415 OB_SPC = ob_spc;
416
417 /* wait for the FMC ready */
418 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
419
420 if(FMC_TOERR != fmc_state){
421 /* reset the OBPG bit */
422 FMC_CTL &= ~FMC_CTL_OBPG;
423 }
424 }else{
425 if(FMC_TOERR != fmc_state){
426 /* reset the OBER bit */
427 FMC_CTL &= ~FMC_CTL_OBER;
428 }
429 }
430 }
431 /* return the FMC state */
432 return fmc_state;
433 }
FMC_CTL_START
#define FMC_CTL_START
Definition: gd32f3x0_fmc.h:60
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
OB_SPC
#define OB_SPC
Definition: gd32f3x0_fmc.h:33
FMC_OB_HSPC
Definition: gd32f3x0_fmc.h:93
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
OB_OBSTAT_PLEVEL_HIGH
#define OB_OBSTAT_PLEVEL_HIGH
Definition: gd32f3x0_fmc.h:147
FMC_CTL_OBPG
#define FMC_CTL_OBPG
Definition: gd32f3x0_fmc.h:58
ob_obstat_plevel_get
uint32_t ob_obstat_plevel_get(void)
get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register ...
Definition: gd32f3x0_fmc.c:544
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
FMC_CTL_OBER
#define FMC_CTL_OBER
Definition: gd32f3x0_fmc.h:59
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
void ob_unlock ( void )

unlock the option byte operation it is better to used in pairs with ob_lock

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 247 of file gd32f3x0_fmc.c.

248 {
249 if(RESET == (FMC_CTL & FMC_CTL_OBWEN)){
250 /* write the FMC key */
251 FMC_OBKEY = UNLOCK_KEY0;
252 FMC_OBKEY = UNLOCK_KEY1;
253 }
254 }
FMC_CTL_OBWEN
#define FMC_CTL_OBWEN
Definition: gd32f3x0_fmc.h:62
FMC_OBKEY
#define FMC_OBKEY
Definition: gd32f3x0_fmc.h:24
UNLOCK_KEY1
#define UNLOCK_KEY1
Definition: gd32f3x0_fmc.h:98
UNLOCK_KEY0
#define UNLOCK_KEY0
Definition: gd32f3x0_fmc.h:97
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
uint8_t ob_user_get ( void )

get OB_USER in register FMC_OBSTAT

Parameters
[in] | none
[out] | none
Return values
ob_user

Definition at line 511 of file gd32f3x0_fmc.c.

512 {
513 return (uint8_t)(FMC_OBSTAT >> 8);
514 }
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f3x0_fmc.h:28
fmc_state_enum ob_user_write ( uint8_t ob_user )

program the FMC user option byte

Parameters
[in] ob_user user option byte
  • OB_FWDGT_SW: software free watchdog timer
  • OB_FWDGT_HW: hardware free watchdog timer
  • OB_DEEPSLEEP_NRST: generate a reset instead of entering deepsleep mode
  • OB_DEEPSLEEP_RST: no reset when entering deepsleep mode
  • OB_STDBY_NRST: generate a reset instead of entering standby mode
  • OB_STDBY_RST: no reset when entering deepsleep mode
  • OB_BOOT1_SET_1: BOOT1 bit is 1
  • OB_BOOT1_SET_0: BOOT1 bit is 0
  • OB_VDDA_DISABLE: disable VDDA monitor
  • OB_VDDA_ENABLE: enable VDDA monitor
  • OB_SRAM_PARITY_DISABLE: disable sram parity check
  • OB_SRAM_PARITY_ENABLE: enable sram parity check
[out] none
Return values
fmc_state

Definition at line 453 of file gd32f3x0_fmc.c.

454 {
455 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
456
457 if(FMC_READY == fmc_state){
458 /* set the OBPG bit */
459 FMC_CTL |= FMC_CTL_OBPG;
460
461 OB_USER = (uint8_t)(ob_user | OB_USER_MASK);
462
463 /* wait for the FMC ready */
464 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
465
466 if(FMC_TOERR != fmc_state){
467 /* reset the OBPG bit */
468 FMC_CTL &= ~FMC_CTL_OBPG;
469 }
470 }
471 /* return the FMC state */
472 return fmc_state;
473 }
OB_USER_MASK
#define OB_USER_MASK
Definition: gd32f3x0_fmc.h:150
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
FMC_CTL_OBPG
#define FMC_CTL_OBPG
Definition: gd32f3x0_fmc.h:58
OB_USER
#define OB_USER
Definition: gd32f3x0_fmc.h:34
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
fmc_state_enum ob_write_protection_enable ( uint32_t ob_wp )

enable option byte write protection (OB_WP)

Parameters
[in] | ob_wp | write protection configuration data
[out] | none
Return values
fmc_state

Definition at line 346 of file gd32f3x0_fmc.c.

347 {
348 uint16_t ob_wrp0, ob_wrp1;
349
350 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
351
352 ob_wp = (uint32_t)(~ob_wp);
353 ob_wrp0 = (uint16_t)(ob_wp & OB_LWP);
354 ob_wrp1 = (uint16_t)((ob_wp & OB_HWP) >> 8);
355
356 if(FMC_READY == fmc_state){
357 /* set the OBPG bit*/
358 FMC_CTL |= FMC_CTL_OBPG;
359
360 if(0xFFU != ob_wrp0){
361 OB_WP0 = ob_wrp0;
362
363 /* wait for the FMC ready */
364 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
365 }
366 if((FMC_READY == fmc_state) && (0xFFU != ob_wrp1)){
367 OB_WP1 = ob_wrp1;
368
369 /* wait for the FMC ready */
370 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
371 }
372 if(FMC_TOERR != fmc_state){
373 /* reset the OBPG bit */
374 FMC_CTL &= ~FMC_CTL_OBPG;
375 }
376 }
377 /* return the FMC state */
378 return fmc_state;
379 }
OB_LWP
#define OB_LWP
Definition: gd32f3x0_fmc.h:111
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
OB_HWP
#define OB_HWP
Definition: gd32f3x0_fmc.h:112
OB_WP0
#define OB_WP0
Definition: gd32f3x0_fmc.h:35
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
FMC_CTL_OBPG
#define FMC_CTL_OBPG
Definition: gd32f3x0_fmc.h:58
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
OB_WP1
#define OB_WP1
Definition: gd32f3x0_fmc.h:36
uint16_t ob_write_protection_get ( void )

get the FMC option byte write protection (OB_WP) in register FMC_WP

Parameters
[in] | none
[out] | none
Return values
OB_WP

Definition at line 533 of file gd32f3x0_fmc.c.

534 {
535 return (uint16_t)(FMC_WP);
536 }
FMC_WP
#define FMC_WP
Definition: gd32f3x0_fmc.h:29
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_fwdgt.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Functions
gd32f3x0_fwdgt.h File Reference

definitions for the FWDGT More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | FWDGT FWDGT_BASE
#define | FWDGT_CTL REG32((FWDGT) + 0x00U)
#define | FWDGT_PSC REG32((FWDGT) + 0x04U)
#define | FWDGT_RLD REG32((FWDGT) + 0x08U)
#define | FWDGT_STAT REG32((FWDGT) + 0x0CU)
#define | FWDGT_WND REG32((FWDGT) + 0x10U)
#define | FWDGT_CTL_CMD BITS(0,15)
#define | FWDGT_PSC_PSC BITS(0,2)
#define | FWDGT_RLD_RLD BITS(0,11)
#define | FWDGT_STAT_PUD BIT(0)
#define | FWDGT_STAT_RUD BIT(1)
#define | FWDGT_STAT_WUD BIT(2)
#define | FWDGT_WND_WND BITS(0,11)
#define | CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U))
#define | PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U))
#define | FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0))
#define | FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1))
#define | FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2))
#define | FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3))
#define | FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4))
#define | FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5))
#define | FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6))
#define | RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U))
#define | WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U))
#define | FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U)
#define | FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U)
#define | FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU)
#define | FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU)
#define | FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU)
#define | FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU)
#define | FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU)
#define | FWDGT_FLAG_PUD FWDGT_STAT_PUD
#define | FWDGT_FLAG_RUD FWDGT_STAT_RUD
#define | FWDGT_FLAG_WUD FWDGT_STAT_WUD

Functions

void | fwdgt_write_disable (void)
disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND More...
void | fwdgt_enable (void)
start the free watchdog timer counter More...
ErrStatus | fwdgt_window_value_config (uint16_t window_value)
configure the free watchdog timer counter window value More...
void | fwdgt_counter_reload (void)
reload the counter of FWDGT More...
ErrStatus | fwdgt_config (uint16_t reload_value, uint8_t prescaler_div)
configure counter reload value, and prescaler divider value More...
FlagStatus | fwdgt_flag_get (uint16_t flag)
get flag state of FWDGT More...

Detailed Description

definitions for the FWDGT

Definition in file gd32f3x0_fwdgt.h.

Macro Definition Documentation

#define CTL_CMD ( regval ) (BITS(0,15) & ((uint32_t)(regval) << 0U))

write value to FWDGT_CTL_CMD bit field

Definition at line 47 of file gd32f3x0_fwdgt.h.

#define FWDGT FWDGT_BASE

Definition at line 18 of file gd32f3x0_fwdgt.h.

#define FWDGT_CTL REG32((FWDGT) + 0x00U)

FWDGT control register

Definition at line 21 of file gd32f3x0_fwdgt.h.

#define FWDGT_CTL_CMD BITS(0,15)

FWDGT command value

Definition at line 29 of file gd32f3x0_fwdgt.h.

#define FWDGT_FLAG_PUD FWDGT_STAT_PUD

a write operation to FWDGT_PSC register is on going

Definition at line 77 of file gd32f3x0_fwdgt.h.

#define FWDGT_FLAG_RUD FWDGT_STAT_RUD

a write operation to FWDGT_RLD register is on going

Definition at line 78 of file gd32f3x0_fwdgt.h.

#define FWDGT_FLAG_WUD FWDGT_STAT_WUD

a write operation to FWDGT_WND register is on going

Definition at line 79 of file gd32f3x0_fwdgt.h.

#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU)

FWDGT_CTL bits fwdgt counter enable value

Definition at line 69 of file gd32f3x0_fwdgt.h.

#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU)

FWDGT_CTL bits fwdgt counter reload value

Definition at line 68 of file gd32f3x0_fwdgt.h.

#define FWDGT_PSC REG32((FWDGT) + 0x04U)

FWDGT prescaler register

Definition at line 22 of file gd32f3x0_fwdgt.h.

#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5))

FWDGT prescaler set to 128

Definition at line 56 of file gd32f3x0_fwdgt.h.

#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2))

FWDGT prescaler set to 16

Definition at line 53 of file gd32f3x0_fwdgt.h.

#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6))

FWDGT prescaler set to 256

Definition at line 57 of file gd32f3x0_fwdgt.h.

#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3))

FWDGT prescaler set to 32

Definition at line 54 of file gd32f3x0_fwdgt.h.

#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0))

FWDGT prescaler set to 4

Definition at line 51 of file gd32f3x0_fwdgt.h.

#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4))

FWDGT prescaler set to 64

Definition at line 55 of file gd32f3x0_fwdgt.h.

#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1))

FWDGT prescaler set to 8

Definition at line 52 of file gd32f3x0_fwdgt.h.

#define FWDGT_PSC_PSC BITS(0,2)

FWDGT prescaler divider value

Definition at line 32 of file gd32f3x0_fwdgt.h.

#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU)

FWDGT_PSC register write operation state flag timeout

Definition at line 73 of file gd32f3x0_fwdgt.h.

#define FWDGT_RLD REG32((FWDGT) + 0x08U)

FWDGT reload register

Definition at line 23 of file gd32f3x0_fwdgt.h.

#define FWDGT_RLD_RLD BITS(0,11)

FWDGT counter reload value

Definition at line 35 of file gd32f3x0_fwdgt.h.

#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU)

FWDGT_RLD register write operation state flag timeout

Definition at line 74 of file gd32f3x0_fwdgt.h.

#define FWDGT_STAT REG32((FWDGT) + 0x0CU)

FWDGT status register

Definition at line 24 of file gd32f3x0_fwdgt.h.

#define FWDGT_STAT_PUD BIT(0)

FWDGT prescaler divider value update

Definition at line 38 of file gd32f3x0_fwdgt.h.

#define FWDGT_STAT_RUD BIT(1)

FWDGT counter reload value update

Definition at line 39 of file gd32f3x0_fwdgt.h.

#define FWDGT_STAT_WUD BIT(2)

FWDGT counter window value update

Definition at line 40 of file gd32f3x0_fwdgt.h.

#define FWDGT_WND REG32((FWDGT) + 0x10U)

FWDGT window register

Definition at line 25 of file gd32f3x0_fwdgt.h.

#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU)

FWDGT_WND register write operation state flag timeout

Definition at line 72 of file gd32f3x0_fwdgt.h.

#define FWDGT_WND_WND BITS(0,11)

FWDGT counter window value

Definition at line 43 of file gd32f3x0_fwdgt.h.

#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U)

FWDGT_CTL bits write access disable value

Definition at line 67 of file gd32f3x0_fwdgt.h.

#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U)

FWDGT_CTL bits write access enable value

Definition at line 66 of file gd32f3x0_fwdgt.h.

#define PSC_PSC ( regval ) (BITS(0,2) & ((uint32_t)(regval) << 0U))

Definition at line 50 of file gd32f3x0_fwdgt.h.

#define RLD_RLD ( regval ) (BITS(0,11) & ((uint32_t)(regval) << 0U))

write value to FWDGT_RLD_RLD bit field

Definition at line 60 of file gd32f3x0_fwdgt.h.

#define WND_WND ( regval ) (BITS(0,11) & ((uint32_t)(regval) << 0U))

write value to FWDGT_WND_WND bit field

Definition at line 63 of file gd32f3x0_fwdgt.h.

Function Documentation

ErrStatus fwdgt_config | ( | uint16_t | reload_value,
 |  | uint8_t | prescaler_div
 | ) |  |

configure counter reload value, and prescaler divider value

Parameters
[in] | reload_value | specify reload value(0x0000 - 0x0FFF)
[in] prescaler_div FWDGT prescaler value
  • FWDGT_PSC_DIV4: FWDGT prescaler set to 4
  • FWDGT_PSC_DIV8: FWDGT prescaler set to 8
  • FWDGT_PSC_DIV16: FWDGT prescaler set to 16
  • FWDGT_PSC_DIV32: FWDGT prescaler set to 32
  • FWDGT_PSC_DIV64: FWDGT prescaler set to 64
  • FWDGT_PSC_DIV128: FWDGT prescaler set to 128
  • FWDGT_PSC_DIV256: FWDGT prescaler set to 256
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 89 of file gd32f3x0_fwdgt.c.

90 {
91 uint32_t timeout = FWDGT_PSC_TIMEOUT;
92 uint32_t flag_status = RESET;
93
94 /* enable write access to FWDGT_PSC,and FWDGT_RLD */
95 FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
96
97 /* wait until the PUD flag to be reset */
98 do{
99 flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
100 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
101
102 if ((uint32_t)RESET != flag_status){
103 return ERROR;
104 }
105
106 /* configure FWDGT */
107 FWDGT_PSC = (uint32_t)prescaler_div;
108
109 timeout = FWDGT_RLD_TIMEOUT;
110 /* wait until the RUD flag to be reset */
111 do{
112 flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
113 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
114
115 if ((uint32_t)RESET != flag_status){
116 return ERROR;
117 }
118
119 FWDGT_RLD = RLD_RLD(reload_value);
120
121 /* reload the counter */
122 FWDGT_CTL = FWDGT_KEY_RELOAD;
123
124 return SUCCESS;
125 }
FWDGT_RLD_TIMEOUT
#define FWDGT_RLD_TIMEOUT
Definition: gd32f3x0_fwdgt.h:74
FWDGT_WRITEACCESS_ENABLE
#define FWDGT_WRITEACCESS_ENABLE
Definition: gd32f3x0_fwdgt.h:66
FWDGT_RLD
#define FWDGT_RLD
Definition: gd32f3x0_fwdgt.h:23
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f3x0_fwdgt.h:21
FWDGT_KEY_RELOAD
#define FWDGT_KEY_RELOAD
Definition: gd32f3x0_fwdgt.h:68
RLD_RLD
#define RLD_RLD(regval)
Definition: gd32f3x0_fwdgt.h:60
FWDGT_STAT_PUD
#define FWDGT_STAT_PUD
Definition: gd32f3x0_fwdgt.h:38
FWDGT_PSC_TIMEOUT
#define FWDGT_PSC_TIMEOUT
Definition: gd32f3x0_fwdgt.h:73
FWDGT_STAT
#define FWDGT_STAT
Definition: gd32f3x0_fwdgt.h:24
FWDGT_STAT_RUD
#define FWDGT_STAT_RUD
Definition: gd32f3x0_fwdgt.h:39
FWDGT_PSC
#define FWDGT_PSC
Definition: gd32f3x0_fwdgt.h:22
void fwdgt_counter_reload ( void )

reload the counter of FWDGT

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 31 of file gd32f3x0_fwdgt.c.

32 {
33 FWDGT_CTL = FWDGT_KEY_RELOAD;
34 }
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f3x0_fwdgt.h:21
FWDGT_KEY_RELOAD
#define FWDGT_KEY_RELOAD
Definition: gd32f3x0_fwdgt.h:68
void fwdgt_enable ( void )

start the free watchdog timer counter

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 42 of file gd32f3x0_fwdgt.c.

43 {
44 FWDGT_CTL = FWDGT_KEY_ENABLE;
45 }
FWDGT_KEY_ENABLE
#define FWDGT_KEY_ENABLE
Definition: gd32f3x0_fwdgt.h:69
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f3x0_fwdgt.h:21
FlagStatus fwdgt_flag_get ( uint16_t flag )

get flag state of FWDGT

Parameters
[in] flag flag to get
  • FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
  • FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
  • FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going
[out] none
Return values
FlagStatus SET or RESET

Definition at line 136 of file gd32f3x0_fwdgt.c.

137 {
138 if(FWDGT_STAT & flag){
139 return SET;
140 }
141 return RESET;
142 }
FWDGT_STAT
#define FWDGT_STAT
Definition: gd32f3x0_fwdgt.h:24
ErrStatus fwdgt_window_value_config ( uint16_t window_value )

configure the free watchdog timer counter window value

Parameters
[in] | window_value | specify window value(0x0000 - 0x0FFF)
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 53 of file gd32f3x0_fwdgt.c.

54 {
55 uint32_t time_index = FWDGT_WND_TIMEOUT;
56 uint32_t flag_status = RESET;
57
58 /* enable write access to FWDGT_WND */
59 FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
60
61 /* wait until the WUD flag to be reset */
62 do{
63 flag_status = FWDGT_STAT & FWDGT_STAT_WUD;
64 }while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
65
66 if ((uint32_t)RESET != flag_status){
67 return ERROR;
68 }
69
70 FWDGT_WND = WND_WND(window_value);
71
72 return SUCCESS;
73 }
FWDGT_WND
#define FWDGT_WND
Definition: gd32f3x0_fwdgt.h:25
FWDGT_WRITEACCESS_ENABLE
#define FWDGT_WRITEACCESS_ENABLE
Definition: gd32f3x0_fwdgt.h:66
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f3x0_fwdgt.h:21
WND_WND
#define WND_WND(regval)
Definition: gd32f3x0_fwdgt.h:63
FWDGT_STAT_WUD
#define FWDGT_STAT_WUD
Definition: gd32f3x0_fwdgt.h:40
FWDGT_STAT
#define FWDGT_STAT
Definition: gd32f3x0_fwdgt.h:24
FWDGT_WND_TIMEOUT
#define FWDGT_WND_TIMEOUT
Definition: gd32f3x0_fwdgt.h:72
void fwdgt_write_disable ( void )

disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_fwdgt.c.

21 {
22 FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
23 }
FWDGT_WRITEACCESS_DISABLE
#define FWDGT_WRITEACCESS_DISABLE
Definition: gd32f3x0_fwdgt.h:67
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f3x0_fwdgt.h:21
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_gpio.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Typedefs | Functions
gd32f3x0_gpio.h File Reference

definitions for the GPIO More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | GPIOA (GPIO_BASE + 0x00000000U)
#define | GPIOB (GPIO_BASE + 0x00000400U)
#define | GPIOC (GPIO_BASE + 0x00000800U)
#define | GPIOD (GPIO_BASE + 0x00000C00U)
#define | GPIOF (GPIO_BASE + 0x00001400U)
#define | GPIO_CTL(gpiox) REG32((gpiox) + 0x00U)
#define | GPIO_OMODE(gpiox) REG32((gpiox) + 0x04U)
#define | GPIO_OSPD0(gpiox) REG32((gpiox) + 0x08U)
#define | GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU)
#define | GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U)
#define | GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U)
#define | GPIO_BOP(gpiox) REG32((gpiox) + 0x18U)
#define | GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU)
#define | GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U)
#define | GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U)
#define | GPIO_BC(gpiox) REG32((gpiox) + 0x28U)
#define | GPIO_TG(gpiox) REG32((gpiox) + 0x2CU)
#define | GPIO_OSPD1(gpiox) REG32((gpiox) + 0x3CU)
#define | GPIO_CTL_CTL0 BITS(0,1)
#define | GPIO_CTL_CTL1 BITS(2,3)
#define | GPIO_CTL_CTL2 BITS(4,5)
#define | GPIO_CTL_CTL3 BITS(6,7)
#define | GPIO_CTL_CTL4 BITS(8,9)
#define | GPIO_CTL_CTL5 BITS(10,11)
#define | GPIO_CTL_CTL6 BITS(12,13)
#define | GPIO_CTL_CTL7 BITS(14,15)
#define | GPIO_CTL_CTL8 BITS(16,17)
#define | GPIO_CTL_CTL9 BITS(18,19)
#define | GPIO_CTL_CTL10 BITS(20,21)
#define | GPIO_CTL_CTL11 BITS(22,23)
#define | GPIO_CTL_CTL12 BITS(24,25)
#define | GPIO_CTL_CTL13 BITS(26,27)
#define | GPIO_CTL_CTL14 BITS(28,29)
#define | GPIO_CTL_CTL15 BITS(30,31)
#define | GPIO_OMODE_OM0 BIT(0)
#define | GPIO_OMODE_OM1 BIT(1)
#define | GPIO_OMODE_OM2 BIT(2)
#define | GPIO_OMODE_OM3 BIT(3)
#define | GPIO_OMODE_OM4 BIT(4)
#define | GPIO_OMODE_OM5 BIT(5)
#define | GPIO_OMODE_OM6 BIT(6)
#define | GPIO_OMODE_OM7 BIT(7)
#define | GPIO_OMODE_OM8 BIT(8)
#define | GPIO_OMODE_OM9 BIT(9)
#define | GPIO_OMODE_OM10 BIT(10)
#define | GPIO_OMODE_OM11 BIT(11)
#define | GPIO_OMODE_OM12 BIT(12)
#define | GPIO_OMODE_OM13 BIT(13)
#define | GPIO_OMODE_OM14 BIT(14)
#define | GPIO_OMODE_OM15 BIT(15)
#define | GPIO_OSPD0_OSPD0 BITS(0,1)
#define | GPIO_OSPD0_OSPD1 BITS(2,3)
#define | GPIO_OSPD0_OSPD2 BITS(4,5)
#define | GPIO_OSPD0_OSPD3 BITS(6,7)
#define | GPIO_OSPD0_OSPD4 BITS(8,9)
#define | GPIO_OSPD0_OSPD5 BITS(10,11)
#define | GPIO_OSPD0_OSPD6 BITS(12,13)
#define | GPIO_OSPD0_OSPD7 BITS(14,15)
#define | GPIO_OSPD0_OSPD8 BITS(16,17)
#define | GPIO_OSPD0_OSPD9 BITS(18,19)
#define | GPIO_OSPD0_OSPD10 BITS(20,21)
#define | GPIO_OSPD0_OSPD11 BITS(22,23)
#define | GPIO_OSPD0_OSPD12 BITS(24,25)
#define | GPIO_OSPD0_OSPD13 BITS(26,27)
#define | GPIO_OSPD0_OSPD14 BITS(28,29)
#define | GPIO_OSPD0_OSPD15 BITS(30,31)
#define | GPIO_PUD_PUD0 BITS(0,1)
#define | GPIO_PUD_PUD1 BITS(2,3)
#define | GPIO_PUD_PUD2 BITS(4,5)
#define | GPIO_PUD_PUD3 BITS(6,7)
#define | GPIO_PUD_PUD4 BITS(8,9)
#define | GPIO_PUD_PUD5 BITS(10,11)
#define | GPIO_PUD_PUD6 BITS(12,13)
#define | GPIO_PUD_PUD7 BITS(14,15)
#define | GPIO_PUD_PUD8 BITS(16,17)
#define | GPIO_PUD_PUD9 BITS(18,19)
#define | GPIO_PUD_PUD10 BITS(20,21)
#define | GPIO_PUD_PUD11 BITS(22,23)
#define | GPIO_PUD_PUD12 BITS(24,25)
#define | GPIO_PUD_PUD13 BITS(26,27)
#define | GPIO_PUD_PUD14 BITS(28,29)
#define | GPIO_PUD_PUD15 BITS(30,31)
#define | GPIO_ISTAT_ISTAT0 BIT(0)
#define | GPIO_ISTAT_ISTAT1 BIT(1)
#define | GPIO_ISTAT_ISTAT2 BIT(2)
#define | GPIO_ISTAT_ISTAT3 BIT(3)
#define | GPIO_ISTAT_ISTAT4 BIT(4)
#define | GPIO_ISTAT_ISTAT5 BIT(5)
#define | GPIO_ISTAT_ISTAT6 BIT(6)
#define | GPIO_ISTAT_ISTAT7 BIT(7)
#define | GPIO_ISTAT_ISTAT8 BIT(8)
#define | GPIO_ISTAT_ISTAT9 BIT(9)
#define | GPIO_ISTAT_ISTAT10 BIT(10)
#define | GPIO_ISTAT_ISTAT11 BIT(11)
#define | GPIO_ISTAT_ISTAT12 BIT(12)
#define | GPIO_ISTAT_ISTAT13 BIT(13)
#define | GPIO_ISTAT_ISTAT14 BIT(14)
#define | GPIO_ISTAT_ISTAT15 BIT(15)
#define | GPIO_OCTL_OCTL0 BIT(0)
#define | GPIO_OCTL_OCTL1 BIT(1)
#define | GPIO_OCTL_OCTL2 BIT(2)
#define | GPIO_OCTL_OCTL3 BIT(3)
#define | GPIO_OCTL_OCTL4 BIT(4)
#define | GPIO_OCTL_OCTL5 BIT(5)
#define | GPIO_OCTL_OCTL6 BIT(6)
#define | GPIO_OCTL_OCTL7 BIT(7)
#define | GPIO_OCTL_OCTL8 BIT(8)
#define | GPIO_OCTL_OCTL9 BIT(9)
#define | GPIO_OCTL_OCTL10 BIT(10)
#define | GPIO_OCTL_OCTL11 BIT(11)
#define | GPIO_OCTL_OCTL12 BIT(12)
#define | GPIO_OCTL_OCTL13 BIT(13)
#define | GPIO_OCTL_OCTL14 BIT(14)
#define | GPIO_OCTL_OCTL15 BIT(15)
#define | GPIO_BOP_BOP0 BIT(0)
#define | GPIO_BOP_BOP1 BIT(1)
#define | GPIO_BOP_BOP2 BIT(2)
#define | GPIO_BOP_BOP3 BIT(3)
#define | GPIO_BOP_BOP4 BIT(4)
#define | GPIO_BOP_BOP5 BIT(5)
#define | GPIO_BOP_BOP6 BIT(6)
#define | GPIO_BOP_BOP7 BIT(7)
#define | GPIO_BOP_BOP8 BIT(8)
#define | GPIO_BOP_BOP9 BIT(9)
#define | GPIO_BOP_BOP10 BIT(10)
#define | GPIO_BOP_BOP11 BIT(11)
#define | GPIO_BOP_BOP12 BIT(12)
#define | GPIO_BOP_BOP13 BIT(13)
#define | GPIO_BOP_BOP14 BIT(14)
#define | GPIO_BOP_BOP15 BIT(15)
#define | GPIO_BOP_CR0 BIT(16)
#define | GPIO_BOP_CR1 BIT(17)
#define | GPIO_BOP_CR2 BIT(18)
#define | GPIO_BOP_CR3 BIT(19)
#define | GPIO_BOP_CR4 BIT(20)
#define | GPIO_BOP_CR5 BIT(21)
#define | GPIO_BOP_CR6 BIT(22)
#define | GPIO_BOP_CR7 BIT(23)
#define | GPIO_BOP_CR8 BIT(24)
#define | GPIO_BOP_CR9 BIT(25)
#define | GPIO_BOP_CR10 BIT(26)
#define | GPIO_BOP_CR11 BIT(27)
#define | GPIO_BOP_CR12 BIT(28)
#define | GPIO_BOP_CR13 BIT(29)
#define | GPIO_BOP_CR14 BIT(30)
#define | GPIO_BOP_CR15 BIT(31)
#define | GPIO_LOCK_LK0 BIT(0)
#define | GPIO_LOCK_LK1 BIT(1)
#define | GPIO_LOCK_LK2 BIT(2)
#define | GPIO_LOCK_LK3 BIT(3)
#define | GPIO_LOCK_LK4 BIT(4)
#define | GPIO_LOCK_LK5 BIT(5)
#define | GPIO_LOCK_LK6 BIT(6)
#define | GPIO_LOCK_LK7 BIT(7)
#define | GPIO_LOCK_LK8 BIT(8)
#define | GPIO_LOCK_LK9 BIT(9)
#define | GPIO_LOCK_LK10 BIT(10)
#define | GPIO_LOCK_LK11 BIT(11)
#define | GPIO_LOCK_LK12 BIT(12)
#define | GPIO_LOCK_LK13 BIT(13)
#define | GPIO_LOCK_LK14 BIT(14)
#define | GPIO_LOCK_LK15 BIT(15)
#define | GPIO_LOCK_LKK BIT(16)
#define | GPIO_AFSEL0_SEL0 BITS(0,3)
#define | GPIO_AFSEL0_SEL1 BITS(4,7)
#define | GPIO_AFSEL0_SEL2 BITS(8,11)
#define | GPIO_AFSEL0_SEL3 BITS(12,15)
#define | GPIO_AFSEL0_SEL4 BITS(16,19)
#define | GPIO_AFSEL0_SEL5 BITS(20,23)
#define | GPIO_AFSEL0_SEL6 BITS(24,27)
#define | GPIO_AFSEL0_SEL7 BITS(28,31)
#define | GPIO_AFSEL1_SEL8 BITS(0,3)
#define | GPIO_AFSEL1_SEL9 BITS(4,7)
#define | GPIO_AFSEL1_SEL10 BITS(8,11)
#define | GPIO_AFSEL1_SEL11 BITS(12,15)
#define | GPIO_AFSEL1_SEL12 BITS(16,19)
#define | GPIO_AFSEL1_SEL13 BITS(20,23)
#define | GPIO_AFSEL1_SEL14 BITS(24,27)
#define | GPIO_AFSEL1_SEL15 BITS(28,31)
#define | GPIO_BC_CR0 BIT(0)
#define | GPIO_BC_CR1 BIT(1)
#define | GPIO_BC_CR2 BIT(2)
#define | GPIO_BC_CR3 BIT(3)
#define | GPIO_BC_CR4 BIT(4)
#define | GPIO_BC_CR5 BIT(5)
#define | GPIO_BC_CR6 BIT(6)
#define | GPIO_BC_CR7 BIT(7)
#define | GPIO_BC_CR8 BIT(8)
#define | GPIO_BC_CR9 BIT(9)
#define | GPIO_BC_CR10 BIT(10)
#define | GPIO_BC_CR11 BIT(11)
#define | GPIO_BC_CR12 BIT(12)
#define | GPIO_BC_CR13 BIT(13)
#define | GPIO_BC_CR14 BIT(14)
#define | GPIO_BC_CR15 BIT(15)
#define | GPIO_TG_TG0 BIT(0)
#define | GPIO_TG_TG1 BIT(1)
#define | GPIO_TG_TG2 BIT(2)
#define | GPIO_TG_TG3 BIT(3)
#define | GPIO_TG_TG4 BIT(4)
#define | GPIO_TG_TG5 BIT(5)
#define | GPIO_TG_TG6 BIT(6)
#define | GPIO_TG_TG7 BIT(7)
#define | GPIO_TG_TG8 BIT(8)
#define | GPIO_TG_TG9 BIT(9)
#define | GPIO_TG_TG10 BIT(10)
#define | GPIO_TG_TG11 BIT(11)
#define | GPIO_TG_TG12 BIT(12)
#define | GPIO_TG_TG13 BIT(13)
#define | GPIO_TG_TG14 BIT(14)
#define | GPIO_TG_TG15 BIT(15)
#define | GPIO_OSPD1_SPD0 BIT(0)
#define | GPIO_OSPD1_SPD1 BIT(1)
#define | GPIO_OSPD1_SPD2 BIT(2)
#define | GPIO_OSPD1_SPD3 BIT(3)
#define | GPIO_OSPD1_SPD4 BIT(4)
#define | GPIO_OSPD1_SPD5 BIT(5)
#define | GPIO_OSPD1_SPD6 BIT(6)
#define | GPIO_OSPD1_SPD7 BIT(7)
#define | GPIO_OSPD1_SPD8 BIT(8)
#define | GPIO_OSPD1_SPD9 BIT(9)
#define | GPIO_OSPD1_SPD10 BIT(10)
#define | GPIO_OSPD1_SPD11 BIT(11)
#define | GPIO_OSPD1_SPD12 BIT(12)
#define | GPIO_OSPD1_SPD13 BIT(13)
#define | GPIO_OSPD1_SPD14 BIT(14)
#define | GPIO_OSPD1_SPD15 BIT(15)
#define | CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define | GPIO_MODE_INPUT CTL_CLTR(0)
#define | GPIO_MODE_OUTPUT CTL_CLTR(1)
#define | GPIO_MODE_AF CTL_CLTR(2)
#define | GPIO_MODE_ANALOG CTL_CLTR(3)
#define | PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define | GPIO_PUPD_NONE PUD_PUPD(0)
#define | GPIO_PUPD_PULLUP PUD_PUPD(1)
#define | GPIO_PUPD_PULLDOWN PUD_PUPD(2)
#define | GPIO_PIN_0 BIT(0)
#define | GPIO_PIN_1 BIT(1)
#define | GPIO_PIN_2 BIT(2)
#define | GPIO_PIN_3 BIT(3)
#define | GPIO_PIN_4 BIT(4)
#define | GPIO_PIN_5 BIT(5)
#define | GPIO_PIN_6 BIT(6)
#define | GPIO_PIN_7 BIT(7)
#define | GPIO_PIN_8 BIT(8)
#define | GPIO_PIN_9 BIT(9)
#define | GPIO_PIN_10 BIT(10)
#define | GPIO_PIN_11 BIT(11)
#define | GPIO_PIN_12 BIT(12)
#define | GPIO_PIN_13 BIT(13)
#define | GPIO_PIN_14 BIT(14)
#define | GPIO_PIN_15 BIT(15)
#define | GPIO_PIN_ALL BITS(0,15)
#define | GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n))))
#define | GPIO_MODE_MASK(n) (0x3U << (2U * (n)))
#define | GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n))))
#define | GPIO_PUPD_MASK(n) (0x3U << (2U * (n)))
#define | GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n))))
#define | GPIO_OSPEED_MASK(n) (0x3U << (2U * (n)))
#define | GPIO_OTYPE_PP ((uint8_t)(0x00U))
#define | GPIO_OTYPE_OD ((uint8_t)(0x01U))
#define | OSPD_OSPD0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define | GPIO_OSPEED_2MHZ OSPD_OSPD0(0)
#define | GPIO_OSPEED_10MHZ OSPD_OSPD0(1)
#define | GPIO_OSPEED_50MHZ OSPD_OSPD0(3)
#define | GPIO_OSPEED_MAX 0x0000FFFFU
#define | GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
#define | GPIO_AFR_MASK(n) (0xFU << (4U * (n)))
#define | AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
#define | GPIO_AF_0 AF(0)
#define | GPIO_AF_1 AF(1)
#define | GPIO_AF_2 AF(2)
#define | GPIO_AF_3 AF(3)
#define | GPIO_AF_4 AF(4)
#define | GPIO_AF_5 AF(5)
#define | GPIO_AF_6 AF(6)
#define | GPIO_AF_7 AF(7)

Typedefs

typedef FlagStatus bit_status

Functions

void | gpio_deinit (uint32_t gpio_periph)
reset GPIO port More...
void | gpio_mode_set (uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin)
set GPIO output mode More...
void | gpio_output_options_set (uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin)
set GPIO output type and speed More...
void | gpio_bit_set (uint32_t gpio_periph, uint32_t pin)
set GPIO pin bit More...
void | gpio_bit_reset (uint32_t gpio_periph, uint32_t pin)
reset GPIO pin bit More...
void | gpio_bit_write (uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
write data to the specified GPIO pin More...
void | gpio_port_write (uint32_t gpio_periph, uint16_t data)
write data to the specified GPIO port More...
FlagStatus | gpio_input_bit_get (uint32_t gpio_periph, uint32_t pin)
get GPIO pin input status More...
uint16_t | gpio_input_port_get (uint32_t gpio_periph)
get GPIO all pins input status More...
FlagStatus | gpio_output_bit_get (uint32_t gpio_periph, uint32_t pin)
get GPIO pin output status More...
uint16_t | gpio_output_port_get (uint32_t gpio_periph)
get GPIO all pins output status More...
void | gpio_af_set (uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin)
set GPIO alternate function More...
void | gpio_pin_lock (uint32_t gpio_periph, uint32_t pin)
lock GPIO pin bit More...
void | gpio_bit_toggle (uint32_t gpio_periph, uint32_t pin)
toggle GPIO pin status More...
void | gpio_port_toggle (uint32_t gpio_periph)
toggle GPIO port status More...

Detailed Description

definitions for the GPIO

Definition in file gd32f3x0_gpio.h.

Macro Definition Documentation

#define AF ( regval ) (BITS(0,3) & ((uint32_t)(regval) << 0))

Definition at line 338 of file gd32f3x0_gpio.h.

#define CTL_CLTR ( regval ) (BITS(0,1) & ((uint32_t)(regval) << 0))

Definition at line 279 of file gd32f3x0_gpio.h.

#define GPIO_AF_0 AF(0)

alternate function 0 selected

Definition at line 339 of file gd32f3x0_gpio.h.

#define GPIO_AF_1 AF(1)

alternate function 1 selected

Definition at line 340 of file gd32f3x0_gpio.h.

#define GPIO_AF_2 AF(2)

alternate function 2 selected

Definition at line 341 of file gd32f3x0_gpio.h.

#define GPIO_AF_3 AF(3)

alternate function 3 selected

Definition at line 342 of file gd32f3x0_gpio.h.

#define GPIO_AF_4 AF(4)

alternate function 4 selected (port A,B only)

Definition at line 343 of file gd32f3x0_gpio.h.

#define GPIO_AF_5 AF(5)

alternate function 5 selected (port A,B only)

Definition at line 344 of file gd32f3x0_gpio.h.

#define GPIO_AF_6 AF(6)

alternate function 6 selected (port A,B only)

Definition at line 345 of file gd32f3x0_gpio.h.

#define GPIO_AF_7 AF(7)

alternate function 7 selected (port A,B only)

Definition at line 346 of file gd32f3x0_gpio.h.

#define GPIO_AFR_MASK ( n ) (0xFU << (4U * (n)))

Definition at line 335 of file gd32f3x0_gpio.h.

#define GPIO_AFR_SET | ( | n,
 |  | af
 | ) | ((uint32_t)((uint32_t)(af) << (4U * (n))))

Definition at line 334 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL0 ( gpiox ) REG32((gpiox) + 0x20U)

GPIO alternate function selected register 0

Definition at line 33 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL0_SEL0 BITS(0,3)

pin 0 alternate function selected

Definition at line 202 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL0_SEL1 BITS(4,7)

pin 1 alternate function selected

Definition at line 203 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL0_SEL2 BITS(8,11)

pin 2 alternate function selected

Definition at line 204 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL0_SEL3 BITS(12,15)

pin 3 alternate function selected

Definition at line 205 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL0_SEL4 BITS(16,19)

pin 4 alternate function selected

Definition at line 206 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL0_SEL5 BITS(20,23)

pin 5 alternate function selected

Definition at line 207 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL0_SEL6 BITS(24,27)

pin 6 alternate function selected

Definition at line 208 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL0_SEL7 BITS(28,31)

pin 7 alternate function selected

Definition at line 209 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL1 ( gpiox ) REG32((gpiox) + 0x24U)

GPIO alternate function selected register 1

Definition at line 34 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL1_SEL10 BITS(8,11)

pin 10 alternate function selected

Definition at line 214 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL1_SEL11 BITS(12,15)

pin 11 alternate function selected

Definition at line 215 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL1_SEL12 BITS(16,19)

pin 12 alternate function selected

Definition at line 216 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL1_SEL13 BITS(20,23)

pin 13 alternate function selected

Definition at line 217 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL1_SEL14 BITS(24,27)

pin 14 alternate function selected

Definition at line 218 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL1_SEL15 BITS(28,31)

pin 15 alternate function selected

Definition at line 219 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL1_SEL8 BITS(0,3)

pin 8 alternate function selected

Definition at line 212 of file gd32f3x0_gpio.h.

#define GPIO_AFSEL1_SEL9 BITS(4,7)

pin 9 alternate function selected

Definition at line 213 of file gd32f3x0_gpio.h.

#define GPIO_BC ( gpiox ) REG32((gpiox) + 0x28U)

GPIO bit clear register

Definition at line 35 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR0 BIT(0)

pin 0 clear bit

Definition at line 222 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR1 BIT(1)

pin 1 clear bit

Definition at line 223 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR10 BIT(10)

pin 10 clear bit

Definition at line 232 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR11 BIT(11)

pin 11 clear bit

Definition at line 233 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR12 BIT(12)

pin 12 clear bit

Definition at line 234 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR13 BIT(13)

pin 13 clear bit

Definition at line 235 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR14 BIT(14)

pin 14 clear bit

Definition at line 236 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR15 BIT(15)

pin 15 clear bit

Definition at line 237 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR2 BIT(2)

pin 2 clear bit

Definition at line 224 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR3 BIT(3)

pin 3 clear bit

Definition at line 225 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR4 BIT(4)

pin 4 clear bit

Definition at line 226 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR5 BIT(5)

pin 5 clear bit

Definition at line 227 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR6 BIT(6)

pin 6 clear bit

Definition at line 228 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR7 BIT(7)

pin 7 clear bit

Definition at line 229 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR8 BIT(8)

pin 8 clear bit

Definition at line 230 of file gd32f3x0_gpio.h.

#define GPIO_BC_CR9 BIT(9)

pin 9 clear bit

Definition at line 231 of file gd32f3x0_gpio.h.

#define GPIO_BOP ( gpiox ) REG32((gpiox) + 0x18U)

GPIO port bit operation register

Definition at line 31 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP0 BIT(0)

pin 0 set bit

Definition at line 149 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP1 BIT(1)

pin 1 set bit

Definition at line 150 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP10 BIT(10)

pin 10 set bit

Definition at line 159 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP11 BIT(11)

pin 11 set bit

Definition at line 160 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP12 BIT(12)

pin 12 set bit

Definition at line 161 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP13 BIT(13)

pin 13 set bit

Definition at line 162 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP14 BIT(14)

pin 14 set bit

Definition at line 163 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP15 BIT(15)

pin 15 set bit

Definition at line 164 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP2 BIT(2)

pin 2 set bit

Definition at line 151 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP3 BIT(3)

pin 3 set bit

Definition at line 152 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP4 BIT(4)

pin 4 set bit

Definition at line 153 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP5 BIT(5)

pin 5 set bit

Definition at line 154 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP6 BIT(6)

pin 6 set bit

Definition at line 155 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP7 BIT(7)

pin 7 set bit

Definition at line 156 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP8 BIT(8)

pin 8 set bit

Definition at line 157 of file gd32f3x0_gpio.h.

#define GPIO_BOP_BOP9 BIT(9)

pin 9 set bit

Definition at line 158 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR0 BIT(16)

pin 0 clear bit

Definition at line 165 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR1 BIT(17)

pin 1 clear bit

Definition at line 166 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR10 BIT(26)

pin 10 clear bit

Definition at line 175 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR11 BIT(27)

pin 11 clear bit

Definition at line 176 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR12 BIT(28)

pin 12 clear bit

Definition at line 177 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR13 BIT(29)

pin 13 clear bit

Definition at line 178 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR14 BIT(30)

pin 14 clear bit

Definition at line 179 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR15 BIT(31)

pin 15 clear bit

Definition at line 180 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR2 BIT(18)

pin 2 clear bit

Definition at line 167 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR3 BIT(19)

pin 3 clear bit

Definition at line 168 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR4 BIT(20)

pin 4 clear bit

Definition at line 169 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR5 BIT(21)

pin 5 clear bit

Definition at line 170 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR6 BIT(22)

pin 6 clear bit

Definition at line 171 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR7 BIT(23)

pin 7 clear bit

Definition at line 172 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR8 BIT(24)

pin 8 clear bit

Definition at line 173 of file gd32f3x0_gpio.h.

#define GPIO_BOP_CR9 BIT(25)

pin 9 clear bit

Definition at line 174 of file gd32f3x0_gpio.h.

#define GPIO_CTL ( gpiox ) REG32((gpiox) + 0x00U)

GPIO port control register

Definition at line 25 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL0 BITS(0,1)

pin 0 configuration bits

Definition at line 41 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL1 BITS(2,3)

pin 1 configuration bits

Definition at line 42 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL10 BITS(20,21)

pin 10 configuration bits

Definition at line 51 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL11 BITS(22,23)

pin 11 configuration bits

Definition at line 52 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL12 BITS(24,25)

pin 12 configuration bits

Definition at line 53 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL13 BITS(26,27)

pin 13 configuration bits

Definition at line 54 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL14 BITS(28,29)

pin 14 configuration bits

Definition at line 55 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL15 BITS(30,31)

pin 15 configuration bits

Definition at line 56 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL2 BITS(4,5)

pin 2 configuration bits

Definition at line 43 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL3 BITS(6,7)

pin 3 configuration bits

Definition at line 44 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL4 BITS(8,9)

pin 4 configuration bits

Definition at line 45 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL5 BITS(10,11)

pin 5 configuration bits

Definition at line 46 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL6 BITS(12,13)

pin 6 configuration bits

Definition at line 47 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL7 BITS(14,15)

pin 7 configuration bits

Definition at line 48 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL8 BITS(16,17)

pin 8 configuration bits

Definition at line 49 of file gd32f3x0_gpio.h.

#define GPIO_CTL_CTL9 BITS(18,19)

pin 9 configuration bits

Definition at line 50 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT ( gpiox ) REG32((gpiox) + 0x10U)

GPIO port input status register

Definition at line 29 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT0 BIT(0)

pin 0 input status

Definition at line 113 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT1 BIT(1)

pin 1 input status

Definition at line 114 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT10 BIT(10)

pin 10 input status

Definition at line 123 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT11 BIT(11)

pin 11 input status

Definition at line 124 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT12 BIT(12)

pin 12 input status

Definition at line 125 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT13 BIT(13)

pin 13 input status

Definition at line 126 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT14 BIT(14)

pin 14 input status

Definition at line 127 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT15 BIT(15)

pin 15 input status

Definition at line 128 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT2 BIT(2)

pin 2 input status

Definition at line 115 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT3 BIT(3)

pin 3 input status

Definition at line 116 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT4 BIT(4)

pin 4 input status

Definition at line 117 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT5 BIT(5)

pin 5 input status

Definition at line 118 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT6 BIT(6)

pin 6 input status

Definition at line 119 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT7 BIT(7)

pin 7 input status

Definition at line 120 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT8 BIT(8)

pin 8 input status

Definition at line 121 of file gd32f3x0_gpio.h.

#define GPIO_ISTAT_ISTAT9 BIT(9)

pin 9 input status

Definition at line 122 of file gd32f3x0_gpio.h.

#define GPIO_LOCK ( gpiox ) REG32((gpiox) + 0x1CU)

GPIO port configuration lock register

Definition at line 32 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK0 BIT(0)

pin 0 lock bit

Definition at line 183 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK1 BIT(1)

pin 1 lock bit

Definition at line 184 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK10 BIT(10)

pin 10 lock bit

Definition at line 193 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK11 BIT(11)

pin 11 lock bit

Definition at line 194 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK12 BIT(12)

pin 12 lock bit

Definition at line 195 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK13 BIT(13)

pin 13 lock bit

Definition at line 196 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK14 BIT(14)

pin 14 lock bit

Definition at line 197 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK15 BIT(15)

pin 15 lock bit

Definition at line 198 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK2 BIT(2)

pin 2 lock bit

Definition at line 185 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK3 BIT(3)

pin 3 lock bit

Definition at line 186 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK4 BIT(4)

pin 4 lock bit

Definition at line 187 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK5 BIT(5)

pin 5 lock bit

Definition at line 188 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK6 BIT(6)

pin 6 lock bit

Definition at line 189 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK7 BIT(7)

pin 7 lock bit

Definition at line 190 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK8 BIT(8)

pin 8 lock bit

Definition at line 191 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LK9 BIT(9)

pin 9 lock bit

Definition at line 192 of file gd32f3x0_gpio.h.

#define GPIO_LOCK_LKK BIT(16)

pin sequence lock key

Definition at line 199 of file gd32f3x0_gpio.h.

#define GPIO_MODE_AF CTL_CLTR(2)

alternate function mode

Definition at line 282 of file gd32f3x0_gpio.h.

#define GPIO_MODE_ANALOG CTL_CLTR(3)

analog mode

Definition at line 283 of file gd32f3x0_gpio.h.

#define GPIO_MODE_INPUT CTL_CLTR(0)

input mode

Definition at line 280 of file gd32f3x0_gpio.h.

#define GPIO_MODE_MASK ( n ) (0x3U << (2U * (n)))

Definition at line 312 of file gd32f3x0_gpio.h.

#define GPIO_MODE_OUTPUT CTL_CLTR(1)

output mode

Definition at line 281 of file gd32f3x0_gpio.h.

#define GPIO_MODE_SET | ( | n,
 |  | mode
 | ) | ((uint32_t)((uint32_t)(mode) << (2U * (n))))

Definition at line 311 of file gd32f3x0_gpio.h.

#define GPIO_OCTL ( gpiox ) REG32((gpiox) + 0x14U)

GPIO port output control register

Definition at line 30 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL0 BIT(0)

pin 0 output bit

Definition at line 131 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL1 BIT(1)

pin 1 output bit

Definition at line 132 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL10 BIT(10)

pin 10 output bit

Definition at line 141 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL11 BIT(11)

pin 11 output bit

Definition at line 142 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL12 BIT(12)

pin 12 output bit

Definition at line 143 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL13 BIT(13)

pin 13 output bit

Definition at line 144 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL14 BIT(14)

pin 14 output bit

Definition at line 145 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL15 BIT(15)

pin 15 output bit

Definition at line 146 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL2 BIT(2)

pin 2 output bit

Definition at line 133 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL3 BIT(3)

pin 3 output bit

Definition at line 134 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL4 BIT(4)

pin 4 output bit

Definition at line 135 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL5 BIT(5)

pin 5 output bit

Definition at line 136 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL6 BIT(6)

pin 6 output bit

Definition at line 137 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL7 BIT(7)

pin 7 output bit

Definition at line 138 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL8 BIT(8)

pin 8 output bit

Definition at line 139 of file gd32f3x0_gpio.h.

#define GPIO_OCTL_OCTL9 BIT(9)

pin 9 output bit

Definition at line 140 of file gd32f3x0_gpio.h.

#define GPIO_OMODE ( gpiox ) REG32((gpiox) + 0x04U)

GPIO port output mode register

Definition at line 26 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM0 BIT(0)

pin 0 output mode bit

Definition at line 59 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM1 BIT(1)

pin 1 output mode bit

Definition at line 60 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM10 BIT(10)

pin 10 output mode bit

Definition at line 69 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM11 BIT(11)

pin 11 output mode bit

Definition at line 70 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM12 BIT(12)

pin 12 output mode bit

Definition at line 71 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM13 BIT(13)

pin 13 output mode bit

Definition at line 72 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM14 BIT(14)

pin 14 output mode bit

Definition at line 73 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM15 BIT(15)

pin 15 output mode bit

Definition at line 74 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM2 BIT(2)

pin 2 output mode bit

Definition at line 61 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM3 BIT(3)

pin 3 output mode bit

Definition at line 62 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM4 BIT(4)

pin 4 output mode bit

Definition at line 63 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM5 BIT(5)

pin 5 output mode bit

Definition at line 64 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM6 BIT(6)

pin 6 output mode bit

Definition at line 65 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM7 BIT(7)

pin 7 output mode bit

Definition at line 66 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM8 BIT(8)

pin 8 output mode bit

Definition at line 67 of file gd32f3x0_gpio.h.

#define GPIO_OMODE_OM9 BIT(9)

pin 9 output mode bit

Definition at line 68 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0 ( gpiox ) REG32((gpiox) + 0x08U)

GPIO port output speed register 0

Definition at line 27 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD0 BITS(0,1)

pin 0 output max speed bits

Definition at line 77 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD1 BITS(2,3)

pin 1 output max speed bits

Definition at line 78 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD10 BITS(20,21)

pin 10 output max speed bits

Definition at line 87 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD11 BITS(22,23)

pin 11 output max speed bits

Definition at line 88 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD12 BITS(24,25)

pin 12 output max speed bits

Definition at line 89 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD13 BITS(26,27)

pin 13 output max speed bits

Definition at line 90 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD14 BITS(28,29)

pin 14 output max speed bits

Definition at line 91 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD15 BITS(30,31)

pin 15 output max speed bits

Definition at line 92 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD2 BITS(4,5)

pin 2 output max speed bits

Definition at line 79 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD3 BITS(6,7)

pin 3 output max speed bits

Definition at line 80 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD4 BITS(8,9)

pin 4 output max speed bits

Definition at line 81 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD5 BITS(10,11)

pin 5 output max speed bits

Definition at line 82 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD6 BITS(12,13)

pin 6 output max speed bits

Definition at line 83 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD7 BITS(14,15)

pin 7 output max speed bits

Definition at line 84 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD8 BITS(16,17)

pin 8 output max speed bits

Definition at line 85 of file gd32f3x0_gpio.h.

#define GPIO_OSPD0_OSPD9 BITS(18,19)

pin 9 output max speed bits

Definition at line 86 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1 ( gpiox ) REG32((gpiox) + 0x3CU)

GPIO port output speed register 1

Definition at line 37 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD0 BIT(0)

set pin 0 very high output speed when OSPD0 is "11"

Definition at line 258 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD1 BIT(1)

set pin 1 very high output speed when OSPD1 is "11"

Definition at line 259 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD10 BIT(10)

set pin 10 very high output speed when OSPD10 is "11"

Definition at line 268 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD11 BIT(11)

set pin 11 very high output speed when OSPD11 is "11"

Definition at line 269 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD12 BIT(12)

set pin 12 very high output speed when OSPD12 is "11"

Definition at line 270 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD13 BIT(13)

set pin 13 very high output speed when OSPD13 is "11"

Definition at line 271 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD14 BIT(14)

set pin 14 very high output speed when OSPD14 is "11"

Definition at line 272 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD15 BIT(15)

set pin 15 very high output speed when OSPD15 is "11"

Definition at line 273 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD2 BIT(2)

set pin 2 very high output speed when OSPD2 is "11"

Definition at line 260 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD3 BIT(3)

set pin 3 very high output speed when OSPD3 is "11"

Definition at line 261 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD4 BIT(4)

set pin 4 very high output speed when OSPD4 is "11"

Definition at line 262 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD5 BIT(5)

set pin 5 very high output speed when OSPD5 is "11"

Definition at line 263 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD6 BIT(6)

set pin 6 very high output speed when OSPD6 is "11"

Definition at line 264 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD7 BIT(7)

set pin 7 very high output speed when OSPD7 is "11"

Definition at line 265 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD8 BIT(8)

set pin 8 very high output speed when OSPD8 is "11"

Definition at line 266 of file gd32f3x0_gpio.h.

#define GPIO_OSPD1_SPD9 BIT(9)

set pin 9 very high output speed when OSPD9 is "11"

Definition at line 267 of file gd32f3x0_gpio.h.

#define GPIO_OSPEED_10MHZ OSPD_OSPD0(1)

output max speed 10MHz

Definition at line 329 of file gd32f3x0_gpio.h.

#define GPIO_OSPEED_2MHZ OSPD_OSPD0(0)

output max speed 2MHz

Definition at line 328 of file gd32f3x0_gpio.h.

#define GPIO_OSPEED_50MHZ OSPD_OSPD0(3)

output max speed 50MHz

Definition at line 330 of file gd32f3x0_gpio.h.

#define GPIO_OSPEED_MASK ( n ) (0x3U << (2U * (n)))

Definition at line 320 of file gd32f3x0_gpio.h.

#define GPIO_OSPEED_MAX 0x0000FFFFU

GPIO very high output speed, max speed more than 50MHz

Definition at line 331 of file gd32f3x0_gpio.h.

#define GPIO_OSPEED_SET | ( | n,
 |  | speed
 | ) | ((uint32_t)((uint32_t)(speed) << (2U * (n))))

Definition at line 319 of file gd32f3x0_gpio.h.

#define GPIO_OTYPE_OD ((uint8_t)(0x01U))

open drain mode

Definition at line 324 of file gd32f3x0_gpio.h.

#define GPIO_OTYPE_PP ((uint8_t)(0x00U))

push pull mode

Definition at line 323 of file gd32f3x0_gpio.h.

#define GPIO_PIN_0 BIT(0)

GPIO pin 0

Definition at line 292 of file gd32f3x0_gpio.h.

#define GPIO_PIN_1 BIT(1)

GPIO pin 1

Definition at line 293 of file gd32f3x0_gpio.h.

#define GPIO_PIN_10 BIT(10)

GPIO pin 10

Definition at line 302 of file gd32f3x0_gpio.h.

#define GPIO_PIN_11 BIT(11)

GPIO pin 11

Definition at line 303 of file gd32f3x0_gpio.h.

#define GPIO_PIN_12 BIT(12)

GPIO pin 12

Definition at line 304 of file gd32f3x0_gpio.h.

#define GPIO_PIN_13 BIT(13)

GPIO pin 13

Definition at line 305 of file gd32f3x0_gpio.h.

#define GPIO_PIN_14 BIT(14)

GPIO pin 14

Definition at line 306 of file gd32f3x0_gpio.h.

#define GPIO_PIN_15 BIT(15)

GPIO pin 15

Definition at line 307 of file gd32f3x0_gpio.h.

#define GPIO_PIN_2 BIT(2)

GPIO pin 2

Definition at line 294 of file gd32f3x0_gpio.h.

#define GPIO_PIN_3 BIT(3)

GPIO pin 3

Definition at line 295 of file gd32f3x0_gpio.h.

#define GPIO_PIN_4 BIT(4)

GPIO pin 4

Definition at line 296 of file gd32f3x0_gpio.h.

#define GPIO_PIN_5 BIT(5)

GPIO pin 5

Definition at line 297 of file gd32f3x0_gpio.h.

#define GPIO_PIN_6 BIT(6)

GPIO pin 6

Definition at line 298 of file gd32f3x0_gpio.h.

#define GPIO_PIN_7 BIT(7)

GPIO pin 7

Definition at line 299 of file gd32f3x0_gpio.h.

#define GPIO_PIN_8 BIT(8)

GPIO pin 8

Definition at line 300 of file gd32f3x0_gpio.h.

#define GPIO_PIN_9 BIT(9)

GPIO pin 9

Definition at line 301 of file gd32f3x0_gpio.h.

#define GPIO_PIN_ALL BITS(0,15)

GPIO pin all

Definition at line 308 of file gd32f3x0_gpio.h.

#define GPIO_PUD ( gpiox ) REG32((gpiox) + 0x0CU)

GPIO port pull-up/pull-down register

Definition at line 28 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD0 BITS(0,1)

pin 0 pull-up or pull-down bits

Definition at line 95 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD1 BITS(2,3)

pin 1 pull-up or pull-down bits

Definition at line 96 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD10 BITS(20,21)

pin 10 pull-up or pull-down bits

Definition at line 105 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD11 BITS(22,23)

pin 11 pull-up or pull-down bits

Definition at line 106 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD12 BITS(24,25)

pin 12 pull-up or pull-down bits

Definition at line 107 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD13 BITS(26,27)

pin 13 pull-up or pull-down bits

Definition at line 108 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD14 BITS(28,29)

pin 14 pull-up or pull-down bits

Definition at line 109 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD15 BITS(30,31)

pin 15 pull-up or pull-down bits

Definition at line 110 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD2 BITS(4,5)

pin 2 pull-up or pull-down bits

Definition at line 97 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD3 BITS(6,7)

pin 3 pull-up or pull-down bits

Definition at line 98 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD4 BITS(8,9)

pin 4 pull-up or pull-down bits

Definition at line 99 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD5 BITS(10,11)

pin 5 pull-up or pull-down bits

Definition at line 100 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD6 BITS(12,13)

pin 6 pull-up or pull-down bits

Definition at line 101 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD7 BITS(14,15)

pin 7 pull-up or pull-down bits

Definition at line 102 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD8 BITS(16,17)

pin 8 pull-up or pull-down bits

Definition at line 103 of file gd32f3x0_gpio.h.

#define GPIO_PUD_PUD9 BITS(18,19)

pin 9 pull-up or pull-down bits

Definition at line 104 of file gd32f3x0_gpio.h.

#define GPIO_PUPD_MASK ( n ) (0x3U << (2U * (n)))

Definition at line 316 of file gd32f3x0_gpio.h.

#define GPIO_PUPD_NONE PUD_PUPD(0)

floating mode, no pull-up and pull-down resistors

Definition at line 287 of file gd32f3x0_gpio.h.

#define GPIO_PUPD_PULLDOWN PUD_PUPD(2)

with pull-down resistor

Definition at line 289 of file gd32f3x0_gpio.h.

#define GPIO_PUPD_PULLUP PUD_PUPD(1)

with pull-up resistor

Definition at line 288 of file gd32f3x0_gpio.h.

#define GPIO_PUPD_SET | ( | n,
 |  | pupd
 | ) | ((uint32_t)((uint32_t)(pupd) << (2U * (n))))

Definition at line 315 of file gd32f3x0_gpio.h.

#define GPIO_TG ( gpiox ) REG32((gpiox) + 0x2CU)

GPIO port bit toggle register

Definition at line 36 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG0 BIT(0)

pin 0 toggle bit

Definition at line 240 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG1 BIT(1)

pin 1 toggle bit

Definition at line 241 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG10 BIT(10)

pin 10 toggle bit

Definition at line 250 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG11 BIT(11)

pin 11 toggle bit

Definition at line 251 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG12 BIT(12)

pin 12 toggle bit

Definition at line 252 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG13 BIT(13)

pin 13 toggle bit

Definition at line 253 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG14 BIT(14)

pin 14 toggle bit

Definition at line 254 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG15 BIT(15)

pin 15 toggle bit

Definition at line 255 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG2 BIT(2)

pin 2 toggle bit

Definition at line 242 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG3 BIT(3)

pin 3 toggle bit

Definition at line 243 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG4 BIT(4)

pin 4 toggle bit

Definition at line 244 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG5 BIT(5)

pin 5 toggle bit

Definition at line 245 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG6 BIT(6)

pin 6 toggle bit

Definition at line 246 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG7 BIT(7)

pin 7 toggle bit

Definition at line 247 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG8 BIT(8)

pin 8 toggle bit

Definition at line 248 of file gd32f3x0_gpio.h.

#define GPIO_TG_TG9 BIT(9)

pin 9 toggle bit

Definition at line 249 of file gd32f3x0_gpio.h.

#define GPIOA (GPIO_BASE + 0x00000000U)

Definition at line 18 of file gd32f3x0_gpio.h.

#define GPIOB (GPIO_BASE + 0x00000400U)

Definition at line 19 of file gd32f3x0_gpio.h.

#define GPIOC (GPIO_BASE + 0x00000800U)

Definition at line 20 of file gd32f3x0_gpio.h.

#define GPIOD (GPIO_BASE + 0x00000C00U)

Definition at line 21 of file gd32f3x0_gpio.h.

#define GPIOF (GPIO_BASE + 0x00001400U)

Definition at line 22 of file gd32f3x0_gpio.h.

#define OSPD_OSPD0 ( regval ) (BITS(0,1) & ((uint32_t)(regval) << 0))

Definition at line 327 of file gd32f3x0_gpio.h.

#define PUD_PUPD ( regval ) (BITS(0,1) & ((uint32_t)(regval) << 0))

Definition at line 286 of file gd32f3x0_gpio.h.

Typedef Documentation

typedef FlagStatus bit_status

Definition at line 276 of file gd32f3x0_gpio.h.

Function Documentation

void gpio_af_set | ( | uint32_t | gpio_periph,
 |  | uint32_t | alt_func_num,
 |  | uint32_t | pin
 | ) |  |

set GPIO alternate function

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C)
[in] alt_func_num GPIO pin af function, please refer to specific device datasheet
  • GPIO_AF_0: TIMER2, TIMER13, TIMER14, TIMER16, SPI0, SPI1, I2S0, CK_OUT, USART0, CEC, IFRP, TSI, CTC, I2C0, I2C1, SWDIO, SWCLK
  • GPIO_AF_1: USART0, USART1, TIMER2, TIMER14, I2C0, I2C1, IFRP, CEC
  • GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, I2S0
  • GPIO_AF_3: TSI, I2C0, TIMER14
  • GPIO_AF_4(port A,B only): USART1, I2C0, I2C1, TIMER13
  • GPIO_AF_5(port A,B only): TIMER15, TIMER16, USBFS, I2S0
  • GPIO_AF_6(port A,B only): CTC, SPI1
  • GPIO_AF_7(port A,B only): CMP0, CMP1
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 276 of file gd32f3x0_gpio.c.

277 {
278 uint16_t i;
279 uint32_t afrl, afrh;
280
281 afrl = GPIO_AFSEL0(gpio_periph);
282 afrh = GPIO_AFSEL1(gpio_periph);
283
284 for(i = 0U;i < 8U;i++){
285 if((1U << i) & pin){
286 /* clear the specified pin alternate function bits */
287 afrl &= ~GPIO_AFR_MASK(i);
288 afrl |= GPIO_AFR_SET(i,alt_func_num);
289 }
290 }
291
292 for(i = 8U;i < 16U;i++){
293 if((1U << i) & pin){
294 /* clear the specified pin alternate function bits */
295 afrh &= ~GPIO_AFR_MASK(i - 8U);
296 afrh |= GPIO_AFR_SET(i - 8U,alt_func_num);
297 }
298 }
299
300 GPIO_AFSEL0(gpio_periph) = afrl;
301 GPIO_AFSEL1(gpio_periph) = afrh;
302 }
GPIO_AFR_MASK
#define GPIO_AFR_MASK(n)
Definition: gd32f3x0_gpio.h:335
GPIO_AFR_SET
#define GPIO_AFR_SET(n, af)
Definition: gd32f3x0_gpio.h:334
GPIO_AFSEL0
#define GPIO_AFSEL0(gpiox)
Definition: gd32f3x0_gpio.h:33
GPIO_AFSEL1
#define GPIO_AFSEL1(gpiox)
Definition: gd32f3x0_gpio.h:34
void gpio_bit_reset | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

reset GPIO pin bit

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 169 of file gd32f3x0_gpio.c.

170 {
171 GPIO_BC(gpio_periph) = (uint32_t)pin;
172 }
GPIO_BC
#define GPIO_BC(gpiox)
Definition: gd32f3x0_gpio.h:35
void gpio_bit_set | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

set GPIO pin bit

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 157 of file gd32f3x0_gpio.c.

158 {
159 GPIO_BOP(gpio_periph) = (uint32_t)pin;
160 }
GPIO_BOP
#define GPIO_BOP(gpiox)
Definition: gd32f3x0_gpio.h:31
void gpio_bit_toggle | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

toggle GPIO pin status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 331 of file gd32f3x0_gpio.c.

332 {
333 GPIO_TG(gpio_periph) = (uint32_t)pin;
334 }
GPIO_TG
#define GPIO_TG(gpiox)
Definition: gd32f3x0_gpio.h:36
void gpio_bit_write | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin,
 |  | bit_status | bit_value
 | ) |  |

write data to the specified GPIO pin

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[in] bit_value SET or RESET
  • RESET: clear the port pin
  • SET: set the port pin
[out] | none
Return values
none

Definition at line 184 of file gd32f3x0_gpio.c.

185 {
186 if(RESET != bit_value){
187 GPIO_BOP(gpio_periph) = (uint32_t)pin;
188 }else{
189 GPIO_BC(gpio_periph) = (uint32_t)pin;
190 }
191 }
GPIO_BC
#define GPIO_BC(gpiox)
Definition: gd32f3x0_gpio.h:35
GPIO_BOP
#define GPIO_BOP(gpiox)
Definition: gd32f3x0_gpio.h:31
void gpio_deinit ( uint32_t gpio_periph )

reset GPIO port

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_gpio.c.

21 {
22 switch(gpio_periph){
23 case GPIOA:
24 /* reset GPIOA */
25 rcu_periph_reset_enable(RCU_GPIOARST);
26 rcu_periph_reset_disable(RCU_GPIOARST);
27 break;
28 case GPIOB:
29 /* reset GPIOB */
30 rcu_periph_reset_enable(RCU_GPIOBRST);
31 rcu_periph_reset_disable(RCU_GPIOBRST);
32 break;
33 case GPIOC:
34 /* reset GPIOC */
35 rcu_periph_reset_enable(RCU_GPIOCRST);
36 rcu_periph_reset_disable(RCU_GPIOCRST);
37 break;
38 case GPIOD:
39 /* reset GPIOD */
40 rcu_periph_reset_enable(RCU_GPIODRST);
41 rcu_periph_reset_disable(RCU_GPIODRST);
42 break;
43 case GPIOF:
44 /* reset GPIOF */
45 rcu_periph_reset_enable(RCU_GPIOFRST);
46 rcu_periph_reset_disable(RCU_GPIOFRST);
47 break;
48 default:
49 break;
50 }
51 }
RCU_GPIOCRST
Definition: gd32f3x0_rcu.h:328
GPIOB
#define GPIOB
Definition: gd32f3x0_gpio.h:19
RCU_GPIOBRST
Definition: gd32f3x0_rcu.h:327
GPIOF
#define GPIOF
Definition: gd32f3x0_gpio.h:22
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
GPIOA
#define GPIOA
Definition: gd32f3x0_gpio.h:18
GPIOC
#define GPIOC
Definition: gd32f3x0_gpio.h:20
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
GPIOD
#define GPIOD
Definition: gd32f3x0_gpio.h:21
RCU_GPIOARST
Definition: gd32f3x0_rcu.h:326
RCU_GPIODRST
Definition: gd32f3x0_rcu.h:329
RCU_GPIOFRST
Definition: gd32f3x0_rcu.h:330
FlagStatus gpio_input_bit_get | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

get GPIO pin input status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
SET or RESET

Definition at line 212 of file gd32f3x0_gpio.c.

213 {
214 if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){
215 return SET;
216 }else{
217 return RESET;
218 }
219 }
GPIO_ISTAT
#define GPIO_ISTAT(gpiox)
Definition: gd32f3x0_gpio.h:29
uint16_t gpio_input_port_get ( uint32_t gpio_periph )

get GPIO all pins input status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[out] | none
Return values
state of GPIO all pins

Definition at line 227 of file gd32f3x0_gpio.c.

228 {
229 return (uint16_t)GPIO_ISTAT(gpio_periph);
230 }
GPIO_ISTAT
#define GPIO_ISTAT(gpiox)
Definition: gd32f3x0_gpio.h:29
void gpio_mode_set | ( | uint32_t | gpio_periph,
 |  | uint32_t | mode,
 |  | uint32_t | pull_up_down,
 |  | uint32_t | pin
 | ) |  |

set GPIO output mode

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] mode gpio pin mode
  • GPIO_MODE_INPUT: input mode
  • GPIO_MODE_OUTPUT: output mode
  • GPIO_MODE_AF: alternate function mode
  • GPIO_MODE_ANALOG: analog mode
[in] pull_up_down gpio pin with pull-up or pull-down resistor
  • GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors
  • GPIO_PUPD_PULLUP: with pull-up resistor
  • GPIO_PUPD_PULLDOWN:with pull-down resistor
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 69 of file gd32f3x0_gpio.c.

70 {
71 uint16_t i;
72 uint32_t ctl, pupd;
73
74 ctl = GPIO_CTL(gpio_periph);
75 pupd = GPIO_PUD(gpio_periph);
76
77 for(i = 0U;i < 16U;i++){
78 if((1U << i) & pin){
79 /* clear the specified pin mode bits */
80 ctl &= ~GPIO_MODE_MASK(i);
81 /* set the specified pin mode bits */
82 ctl |= GPIO_MODE_SET(i, mode);
83
84 /* clear the specified pin pupd bits */
85 pupd &= ~GPIO_PUPD_MASK(i);
86 /* set the specified pin pupd bits */
87 pupd |= GPIO_PUPD_SET(i, pull_up_down);
88 }
89 }
90
91 GPIO_CTL(gpio_periph) = ctl;
92 GPIO_PUD(gpio_periph) = pupd;
93 }
GPIO_PUD
#define GPIO_PUD(gpiox)
Definition: gd32f3x0_gpio.h:28
GPIO_PUPD_SET
#define GPIO_PUPD_SET(n, pupd)
Definition: gd32f3x0_gpio.h:315
GPIO_PUPD_MASK
#define GPIO_PUPD_MASK(n)
Definition: gd32f3x0_gpio.h:316
GPIO_CTL
#define GPIO_CTL(gpiox)
Definition: gd32f3x0_gpio.h:25
GPIO_MODE_MASK
#define GPIO_MODE_MASK(n)
Definition: gd32f3x0_gpio.h:312
GPIO_MODE_SET
#define GPIO_MODE_SET(n, mode)
Definition: gd32f3x0_gpio.h:311
FlagStatus gpio_output_bit_get | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

get GPIO pin output status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
SET or RESET

Definition at line 239 of file gd32f3x0_gpio.c.

240 {
241 if((uint32_t)RESET != (GPIO_OCTL(gpio_periph)&(pin))){
242 return SET;
243 }else{
244 return RESET;
245 }
246 }
GPIO_OCTL
#define GPIO_OCTL(gpiox)
Definition: gd32f3x0_gpio.h:30
void gpio_output_options_set | ( | uint32_t | gpio_periph,
 |  | uint8_t | otype,
 |  | uint32_t | speed,
 |  | uint32_t | pin
 | ) |  |

set GPIO output type and speed

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] otype gpio pin output mode
  • GPIO_OTYPE_PP: push pull mode
  • GPIO_OTYPE_OD: open drain mode
[in] speed gpio pin output max speed
  • GPIO_OSPEED_2MHZ: output max speed 2MHz
  • GPIO_OSPEED_10MHZ: output max speed 10MHz
  • GPIO_OSPEED_50MHZ: output max speed 50MHz
  • GPIO_OSPEED_MAX: GPIO very high output speed, max speed more than 50MHz
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 110 of file gd32f3x0_gpio.c.

111 {
112 uint16_t i;
113 uint32_t ospeed0,ospeed1;
114
115 if(GPIO_OTYPE_OD == otype){
116 GPIO_OMODE(gpio_periph) |= (uint32_t)pin;
117 }else{
118 GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin);
119 }
120
121 /* get the specified pin output speed bits value */
122 ospeed0 = GPIO_OSPD0(gpio_periph);
123
124 if(GPIO_OSPEED_MAX == speed){
125 ospeed1 = GPIO_OSPD1(gpio_periph);
126
127 for(i = 0U;i < 16U;i++){
128 if((1U << i) & pin){
129 /* enable very high output speed function of the pin when the corresponding OSPDy(y=0..15)
130 is "11" (output max speed 50MHz) */
131 ospeed0 |= GPIO_OSPEED_SET(i,0x03);
132 ospeed1 |= (1U << i);
133 }
134 }
135 GPIO_OSPD0(gpio_periph) = ospeed0;
136 GPIO_OSPD1(gpio_periph) = ospeed1;
137 }else{
138 for(i = 0U;i < 16U;i++){
139 if((1U << i) & pin){
140 /* clear the specified pin output speed bits */
141 ospeed0 &= ~GPIO_OSPEED_MASK(i);
142 /* set the specified pin output speed bits */
143 ospeed0 |= GPIO_OSPEED_SET(i,speed);
144 }
145 }
146 GPIO_OSPD0(gpio_periph) = ospeed0;
147 }
148 }
GPIO_OSPEED_MAX
#define GPIO_OSPEED_MAX
Definition: gd32f3x0_gpio.h:331
GPIO_OSPEED_SET
#define GPIO_OSPEED_SET(n, speed)
Definition: gd32f3x0_gpio.h:319
GPIO_OSPEED_MASK
#define GPIO_OSPEED_MASK(n)
Definition: gd32f3x0_gpio.h:320
GPIO_OMODE
#define GPIO_OMODE(gpiox)
Definition: gd32f3x0_gpio.h:26
GPIO_OTYPE_OD
#define GPIO_OTYPE_OD
Definition: gd32f3x0_gpio.h:324
GPIO_OSPD0
#define GPIO_OSPD0(gpiox)
Definition: gd32f3x0_gpio.h:27
GPIO_OSPD1
#define GPIO_OSPD1(gpiox)
Definition: gd32f3x0_gpio.h:37
uint16_t gpio_output_port_get ( uint32_t gpio_periph )

get GPIO all pins output status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[out] | none
Return values
state of GPIO all pins

Definition at line 254 of file gd32f3x0_gpio.c.

255 {
256 return (uint16_t)GPIO_OCTL(gpio_periph);
257 }
GPIO_OCTL
#define GPIO_OCTL(gpiox)
Definition: gd32f3x0_gpio.h:30
void gpio_pin_lock | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

lock GPIO pin bit

Parameters
[in] | gpio_periph | GPIOx(x = A,B)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 311 of file gd32f3x0_gpio.c.

312 {
313 uint32_t lock = 0x00010000U;
314 lock |= pin;
315
316 /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */
317 GPIO_LOCK(gpio_periph) = (uint32_t)lock;
318 GPIO_LOCK(gpio_periph) = (uint32_t)pin;
319 GPIO_LOCK(gpio_periph) = (uint32_t)lock;
320 lock = GPIO_LOCK(gpio_periph);
321 lock = GPIO_LOCK(gpio_periph);
322 }
GPIO_LOCK
#define GPIO_LOCK(gpiox)
Definition: gd32f3x0_gpio.h:32
void gpio_port_toggle ( uint32_t gpio_periph )

toggle GPIO port status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[out] | none
Return values
none

Definition at line 342 of file gd32f3x0_gpio.c.

343 {
344 GPIO_TG(gpio_periph) = 0x0000FFFFU;
345 }
GPIO_TG
#define GPIO_TG(gpiox)
Definition: gd32f3x0_gpio.h:36
void gpio_port_write | ( | uint32_t | gpio_periph,
 |  | uint16_t | data
 | ) |  |

write data to the specified GPIO port

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] | data | specify the value to be written to the port output control register
[out] | none
Return values
none

Definition at line 200 of file gd32f3x0_gpio.c.

201 {
202 GPIO_OCTL(gpio_periph) = (uint32_t)data;
203 }
GPIO_OCTL
#define GPIO_OCTL(gpiox)
Definition: gd32f3x0_gpio.h:30
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_i2c.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Functions
gd32f3x0_i2c.h File Reference

definitions for the I2C More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | I2C0 I2C_BASE
#define | I2C1 (I2C_BASE+0x400U)
#define | I2C2 (I2C_BASE+0x6C00U)
#define | I2C_CTL0(i2cx) REG32((i2cx) + 0x00U)
#define | I2C_CTL1(i2cx) REG32((i2cx) + 0x04U)
#define | I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U)
#define | I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU)
#define | I2C_DATA(i2cx) REG32((i2cx) + 0x10U)
#define | I2C_STAT0(i2cx) REG32((i2cx) + 0x14U)
#define | I2C_STAT1(i2cx) REG32((i2cx) + 0x18U)
#define | I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU)
#define | I2C_RT(i2cx) REG32((i2cx) + 0x20U)
#define | I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U)
#define | I2C_CTL0_I2CEN BIT(0)
#define | I2C_CTL0_SMBEN BIT(1)
#define | I2C_CTL0_SMBSEL BIT(3)
#define | I2C_CTL0_ARPEN BIT(4)
#define | I2C_CTL0_PECEN BIT(5)
#define | I2C_CTL0_GCEN BIT(6)
#define | I2C_CTL0_DISSTRC BIT(7)
#define | I2C_CTL0_START BIT(8)
#define | I2C_CTL0_STOP BIT(9)
#define | I2C_CTL0_ACKEN BIT(10)
#define | I2C_CTL0_POAP BIT(11)
#define | I2C_CTL0_PECTRANS BIT(12)
#define | I2C_CTL0_SALT BIT(13)
#define | I2C_CTL0_SRESET BIT(15)
#define | I2C_CTL1_I2CCLK BITS(0,6)
#define | I2C_CTL1_ERRIE BIT(8)
#define | I2C_CTL1_EVIE BIT(9)
#define | I2C_CTL1_BUFIE BIT(10)
#define | I2C_CTL1_DMAON BIT(11)
#define | I2C_CTL1_DMALST BIT(12)
#define | I2C_SADDR0_ADDRESS0 BIT(0)
#define | I2C_SADDR0_ADDRESS BITS(1,7)
#define | I2C_SADDR0_ADDRESS_H BITS(8,9)
#define | I2C_SADDR0_ADDFORMAT BIT(15)
#define | I2C_SADDR1_DUADEN BIT(0)
#define | I2C_SADDR1_ADDRESS2 BITS(1,7)
#define | I2C_DATA_TRB BITS(0,7)
#define | I2C_STAT0_SBSEND BIT(0)
#define | I2C_STAT0_ADDSEND BIT(1)
#define | I2C_STAT0_BTC BIT(2)
#define | I2C_STAT0_ADD10SEND BIT(3)
#define | I2C_STAT0_STPDET BIT(4)
#define | I2C_STAT0_RBNE BIT(6)
#define | I2C_STAT0_TBE BIT(7)
#define | I2C_STAT0_BERR BIT(8)
#define | I2C_STAT0_LOSTARB BIT(9)
#define | I2C_STAT0_AERR BIT(10)
#define | I2C_STAT0_OUERR BIT(11)
#define | I2C_STAT0_PECERR BIT(12)
#define | I2C_STAT0_SMBTO BIT(14)
#define | I2C_STAT0_SMBALT BIT(15)
#define | I2C_STAT1_MASTER BIT(0)
#define | I2C_STAT1_I2CBSY BIT(1)
#define | I2C_STAT1_TRS BIT(2)
#define | I2C_STAT1_RXGC BIT(4)
#define | I2C_STAT1_DEFSMB BIT(5)
#define | I2C_STAT1_HSTSMB BIT(6)
#define | I2C_STAT1_DUMODF BIT(7)
#define | I2C_STAT1_ECV BITS(8,15)
#define | I2C_CKCFG_CLKC BITS(0,11)
#define | I2C_CKCFG_DTCY BIT(14)
#define | I2C_CKCFG_FAST BIT(15)
#define | I2C_RT_RISETIME BITS(0,6)
#define | I2C_FMPCFG_FMPEN BIT(0)
#define | I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U)
#define | I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN
#define | I2C_SMBUS_DEVICE ((uint32_t)0x00000000U)
#define | I2C_SMBUS_HOST I2C_CTL0_SMBSEL
#define | I2C_RECEIVER ((uint32_t)0x00000001U)
#define | I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU)
#define | I2C_ACK_DISABLE ((uint32_t)0x00000000U)
#define | I2C_ACK_ENABLE ((uint32_t)0x00000001U)
#define | I2C_ACKPOS_NEXT ((uint32_t)0x00000000U)
#define | I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U)
#define | I2C_DUADEN_DISABLE ((uint32_t)0x00000000U)
#define | I2C_DUADEN_ENABLE ((uint32_t)0x00000001U)
#define | I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U)
#define | I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC
#define | I2C_GCEN_ENABLE I2C_CTL0_GCEN
#define | I2C_GCEN_DISABLE ((uint32_t)0x00000000U)
#define | I2C_SRESET_SET I2C_CTL0_SRESET
#define | I2C_SRESET_RESET ((uint32_t)0x00000000U)
#define | I2C_DMA_ON I2C_CTL1_DMAON
#define | I2C_DMA_OFF ((uint32_t)0x00000000U)
#define | I2C_DMALST_ON I2C_CTL1_DMALST
#define | I2C_DMALST_OFF ((uint32_t)0x00000000U)
#define | I2C_PEC_ENABLE I2C_CTL0_PECEN
#define | I2C_PEC_DISABLE ((uint32_t)0x00000000U)
#define | I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS
#define | I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U)
#define | I2C_SALTSEND_ENABLE I2C_CTL0_SALT
#define | I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U)
#define | I2C_ARP_ENABLE I2C_CTL0_ARPEN
#define | I2C_ARP_DISABLE ((uint32_t)0x00000000U)
#define | I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN
#define | I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U)
#define | DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
#define | DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
#define | I2C_FLAG_SBSEND BIT(0)
#define | I2C_FLAG_ADDSEND BIT(1)
#define | I2C_FLAG_BTC BIT(2)
#define | I2C_FLAG_ADD10SEND BIT(3)
#define | I2C_FLAG_STPDET BIT(4)
#define | I2C_FLAG_RBNE BIT(6)
#define | I2C_FLAG_TBE BIT(7)
#define | I2C_FLAG_BERR BIT(8)
#define | I2C_FLAG_LOSTARB BIT(9)
#define | I2C_FLAG_AERR BIT(10)
#define | I2C_FLAG_OUERR BIT(11)
#define | I2C_FLAG_PECERR BIT(12)
#define | I2C_FLAG_SMBTO BIT(14)
#define | I2C_FLAG_SMBALT BIT(15)
#define | I2C_FLAG_MASTER (BIT(0)|BIT(31))
#define | I2C_FLAG_I2CBSY (BIT(1)|BIT(31))
#define | I2C_FLAG_TRS (BIT(2)|BIT(31))
#define | I2C_FLAG_RXGC (BIT(4)|BIT(31))
#define | I2C_FLAG_DEFSMB (BIT(5)|BIT(31))
#define | I2C_FLAG_HSTSMB (BIT(6)|BIT(31))
#define | I2C_FLAG_DUMOD (BIT(7)|BIT(31))
#define | I2C_INT_FLAG_SBSEND I2C_FLAG_SBSEND
#define | I2C_INT_FLAG_ADDSEND I2C_FLAG_ADDSEND
#define | I2C_INT_FLAG_BTC I2C_FLAG_BTC
#define | I2C_INT_FLAG_ADD10SEND I2C_FLAG_ADD10SEND
#define | I2C_INT_FLAG_STPDET I2C_FLAG_STPDET
#define | I2C_INT_FLAG_RBNE I2C_FLAG_RBNE
#define | I2C_INT_FLAG_TBE I2C_FLAG_TBE
#define | I2C_INT_FLAG_BERR I2C_FLAG_BERR
#define | I2C_INT_FLAG_LOSTARB I2C_FLAG_LOSTARB
#define | I2C_INT_FLAG_AERR I2C_FLAG_AERR
#define | I2C_INT_FLAG_OUERR I2C_FLAG_OUERR
#define | I2C_INT_FLAG_PECERR I2C_FLAG_PECERR
#define | I2C_INT_FLAG_SMBTO I2C_FLAG_SMBTO
#define | I2C_INT_FLAG_SMBALT I2C_FLAG_SMBALT
#define | I2C_INT_ERR I2C_CTL1_ERRIE
#define | I2C_INT_EV I2C_CTL1_EVIE
#define | I2C_INT_BUF I2C_CTL1_BUFIE
#define | CKCFG_DTCY(regval) (BIT(14) & ((uint32_t)(regval) << 14))
#define | I2C_DTCY_2 CKCFG_DTCY(0)
#define | I2C_DTCY_16_9 CKCFG_DTCY(1)
#define | SADDR0_ADDFORMAT(regval) (BIT(15) & ((uint32_t)(regval) << 15))
#define | I2C_ADDFORMAT_7BITS SADDR0_ADDFORMAT(0)
#define | I2C_ADDFORMAT_10BITS SADDR0_ADDFORMAT(1)

Functions

void | i2c_deinit (uint32_t i2c_periph)
reset I2C More...
void | i2c_clock_config (uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
configure I2C clock More...
void | i2c_mode_addr_config (uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
configure I2C address More...
void | i2c_smbus_type_config (uint32_t i2c_periph, uint32_t type)
SMBus type selection. More...
void | i2c_ack_config (uint32_t i2c_periph, uint32_t ack)
whether or not to send an ACK More...
void | i2c_ackpos_config (uint32_t i2c_periph, uint32_t pos)
I2C POAP position configure. More...
void | i2c_master_addressing (uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
master send slave address More...
void | i2c_dualaddr_enable (uint32_t i2c_periph, uint32_t dualaddr)
dual-address mode switch More...
void | i2c_enable (uint32_t i2c_periph)
enable I2C More...
void | i2c_disable (uint32_t i2c_periph)
disable I2C More...
void | i2c_start_on_bus (uint32_t i2c_periph)
generate a START condition on I2C bus More...
void | i2c_stop_on_bus (uint32_t i2c_periph)
generate a STOP condition on I2C bus More...
void | i2c_data_transmit (uint32_t i2c_periph, uint8_t data)
I2C transmit data function. More...
uint8_t | i2c_data_receive (uint32_t i2c_periph)
I2C receive data function. More...
void | i2c_dma_enable (uint32_t i2c_periph, uint32_t dmastate)
enable I2C DMA mode More...
void | i2c_dma_last_transfer_enable (uint32_t i2c_periph, uint32_t dmalast)
flag indicating DMA last transfer More...
void | i2c_stretch_scl_low_config (uint32_t i2c_periph, uint32_t stretchpara)
whether to stretch SCL low when data is not ready in slave mode More...
void | i2c_slave_response_to_gcall_config (uint32_t i2c_periph, uint32_t gcallpara)
whether or not to response to a general call More...
void | i2c_software_reset_config (uint32_t i2c_periph, uint32_t sreset)
software reset I2C More...
FlagStatus | i2c_flag_get (uint32_t i2c_periph, uint32_t flag)
check I2C flag is set or not More...
void | i2c_flag_clear (uint32_t i2c_periph, uint32_t flag)
clear I2C flag More...
void | i2c_interrupt_enable (uint32_t i2c_periph, uint32_t inttype)
enable I2C interrupt More...
void | i2c_interrupt_disable (uint32_t i2c_periph, uint32_t inttype)
disable I2C interrupt More...
FlagStatus | i2c_interrupt_flag_get (uint32_t i2c_periph, uint32_t intflag)
check I2C interrupt flag More...
void | i2c_interrupt_flag_clear (uint32_t i2c_periph, uint32_t intflag)
clear I2C interrupt flag More...
void | i2c_pec_enable (uint32_t i2c_periph, uint32_t pecstate)
I2C PEC calculation on or off. More...
void | i2c_pec_transfer_enable (uint32_t i2c_periph, uint32_t pecpara)
I2C whether to transfer PEC value. More...
uint8_t | i2c_pec_value_get (uint32_t i2c_periph)
get packet error checking value More...
void | i2c_smbus_issue_alert (uint32_t i2c_periph, uint32_t smbuspara)
I2C issue alert through SMBA pin. More...
void | i2c_smbus_arp_enable (uint32_t i2c_periph, uint32_t arpstate)
enable or disable I2C ARP protocol in SMBus switch More...

Detailed Description

definitions for the I2C

Definition in file gd32f3x0_i2c.h.

Macro Definition Documentation

#define CKCFG_DTCY ( regval ) (BIT(14) & ((uint32_t)(regval) << 14))

Definition at line 229 of file gd32f3x0_i2c.h.

#define DATA_RECV ( regval ) GET_BITS((uint32_t)(regval), 0, 7)

Definition at line 182 of file gd32f3x0_i2c.h.

#define DATA_TRANS ( regval ) (BITS(0,7) & ((uint32_t)(regval) << 0))

Definition at line 179 of file gd32f3x0_i2c.h.

#define I2C0 I2C_BASE

I2C0 base address

Definition at line 19 of file gd32f3x0_i2c.h.

#define I2C1 (I2C_BASE+0x400U)

I2C1 base address

Definition at line 20 of file gd32f3x0_i2c.h.

#define I2C2 (I2C_BASE+0x6C00U)

I2C2 base address

Definition at line 21 of file gd32f3x0_i2c.h.

#define I2C_ACK_DISABLE ((uint32_t)0x00000000U)

ACK will be not sent

Definition at line 124 of file gd32f3x0_i2c.h.

#define I2C_ACK_ENABLE ((uint32_t)0x00000001U)

ACK will be sent

Definition at line 125 of file gd32f3x0_i2c.h.

#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U)

ACKEN bit decides whether or not to send ACK or not for the current byte

Definition at line 129 of file gd32f3x0_i2c.h.

#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U)

ACKEN bit decides whether or not to send ACK for the next byte

Definition at line 128 of file gd32f3x0_i2c.h.

#define I2C_ADDFORMAT_10BITS SADDR0_ADDFORMAT(1)

address:10 bits

Definition at line 236 of file gd32f3x0_i2c.h.

#define I2C_ADDFORMAT_7BITS SADDR0_ADDFORMAT(0)

address:7 bits

Definition at line 235 of file gd32f3x0_i2c.h.

#define I2C_ARP_DISABLE ((uint32_t)0x00000000U)

ARP disable

Definition at line 172 of file gd32f3x0_i2c.h.

#define I2C_ARP_ENABLE I2C_CTL0_ARPEN

ARP enable

Definition at line 171 of file gd32f3x0_i2c.h.

#define I2C_CKCFG ( i2cx ) REG32((i2cx) + 0x1CU)

I2C clock configure register

Definition at line 31 of file gd32f3x0_i2c.h.

#define I2C_CKCFG_CLKC BITS(0,11)

clock control register in fast/standard mode or fast mode plus(master mode)

Definition at line 100 of file gd32f3x0_i2c.h.

#define I2C_CKCFG_DTCY BIT(14)

duty cycle of fast mode or fast mode plus

Definition at line 101 of file gd32f3x0_i2c.h.

#define I2C_CKCFG_FAST BIT(15)

I2C speed selection in master mode

Definition at line 102 of file gd32f3x0_i2c.h.

#define I2C_CTL0 ( i2cx ) REG32((i2cx) + 0x00U)

I2C control register 0

Definition at line 24 of file gd32f3x0_i2c.h.

#define I2C_CTL0_ACKEN BIT(10)

acknowledge enable

Definition at line 46 of file gd32f3x0_i2c.h.

#define I2C_CTL0_ARPEN BIT(4)

ARP enable

Definition at line 40 of file gd32f3x0_i2c.h.

#define I2C_CTL0_DISSTRC BIT(7)

clock stretching disable (slave mode)

Definition at line 43 of file gd32f3x0_i2c.h.

#define I2C_CTL0_GCEN BIT(6)

general call enable

Definition at line 42 of file gd32f3x0_i2c.h.

#define I2C_CTL0_I2CEN BIT(0)

peripheral enable

Definition at line 37 of file gd32f3x0_i2c.h.

#define I2C_CTL0_PECEN BIT(5)

PEC enable

Definition at line 41 of file gd32f3x0_i2c.h.

#define I2C_CTL0_PECTRANS BIT(12)

packet error checking

Definition at line 48 of file gd32f3x0_i2c.h.

#define I2C_CTL0_POAP BIT(11)

acknowledge/PEC position (for data reception)

Definition at line 47 of file gd32f3x0_i2c.h.

#define I2C_CTL0_SALT BIT(13)

SMBus alert

Definition at line 49 of file gd32f3x0_i2c.h.

#define I2C_CTL0_SMBEN BIT(1)

SMBus mode

Definition at line 38 of file gd32f3x0_i2c.h.

#define I2C_CTL0_SMBSEL BIT(3)

SMBus type

Definition at line 39 of file gd32f3x0_i2c.h.

#define I2C_CTL0_SRESET BIT(15)

software reset

Definition at line 50 of file gd32f3x0_i2c.h.

#define I2C_CTL0_START BIT(8)

start generation

Definition at line 44 of file gd32f3x0_i2c.h.

#define I2C_CTL0_STOP BIT(9)

stop generation

Definition at line 45 of file gd32f3x0_i2c.h.

#define I2C_CTL1 ( i2cx ) REG32((i2cx) + 0x04U)

I2C control register 1

Definition at line 25 of file gd32f3x0_i2c.h.

#define I2C_CTL1_BUFIE BIT(10)

buffer interrupt enable

Definition at line 56 of file gd32f3x0_i2c.h.

#define I2C_CTL1_DMALST BIT(12)

DMA last transfer

Definition at line 58 of file gd32f3x0_i2c.h.

#define I2C_CTL1_DMAON BIT(11)

DMA requests enable

Definition at line 57 of file gd32f3x0_i2c.h.

#define I2C_CTL1_ERRIE BIT(8)

error interrupt inable

Definition at line 54 of file gd32f3x0_i2c.h.

#define I2C_CTL1_EVIE BIT(9)

event interrupt enable

Definition at line 55 of file gd32f3x0_i2c.h.

#define I2C_CTL1_I2CCLK BITS(0,6)

I2CCLK[6:0] bits (peripheral clock frequency)

Definition at line 53 of file gd32f3x0_i2c.h.

#define I2C_DATA ( i2cx ) REG32((i2cx) + 0x10U)

I2C transfer buffer register

Definition at line 28 of file gd32f3x0_i2c.h.

#define I2C_DATA_TRB BITS(0,7)

8-bit data register

Definition at line 71 of file gd32f3x0_i2c.h.

#define I2C_DMA_OFF ((uint32_t)0x00000000U)

DMA mode disabled

Definition at line 150 of file gd32f3x0_i2c.h.

#define I2C_DMA_ON I2C_CTL1_DMAON

DMA mode enabled

Definition at line 149 of file gd32f3x0_i2c.h.

#define I2C_DMALST_OFF ((uint32_t)0x00000000U)

next DMA EOT is not the last transfer

Definition at line 154 of file gd32f3x0_i2c.h.

#define I2C_DMALST_ON I2C_CTL1_DMALST

next DMA EOT is the last transfer

Definition at line 153 of file gd32f3x0_i2c.h.

#define I2C_DTCY_16_9 CKCFG_DTCY(1)

in I2C fast mode or fast mode plus Tlow/Thigh = 16/9

Definition at line 231 of file gd32f3x0_i2c.h.

#define I2C_DTCY_2 CKCFG_DTCY(0)

in I2C fast mode or fast mode plus Tlow/Thigh = 2

Definition at line 230 of file gd32f3x0_i2c.h.

#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U)

dual-address mode disabled

Definition at line 132 of file gd32f3x0_i2c.h.

#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U)

dual-address mode enabled

Definition at line 133 of file gd32f3x0_i2c.h.

#define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U)

fast mode plus disable

Definition at line 176 of file gd32f3x0_i2c.h.

#define I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN

fast mode plus enable

Definition at line 175 of file gd32f3x0_i2c.h.

#define I2C_FLAG_ADD10SEND BIT(3)

header of 10-bit address is sent in master mode

Definition at line 188 of file gd32f3x0_i2c.h.

#define I2C_FLAG_ADDSEND BIT(1)

address is sent in master mode or received and matches in slave mode

Definition at line 186 of file gd32f3x0_i2c.h.

#define I2C_FLAG_AERR BIT(10)

acknowledge error

Definition at line 194 of file gd32f3x0_i2c.h.

#define I2C_FLAG_BERR BIT(8)

a bus error occurs indication a unexpected start or stop condition on I2C bus

Definition at line 192 of file gd32f3x0_i2c.h.

#define I2C_FLAG_BTC BIT(2)

byte transmission finishes

Definition at line 187 of file gd32f3x0_i2c.h.

#define I2C_FLAG_DEFSMB (BIT(5)|BIT(31))

default address of SMBus device

Definition at line 203 of file gd32f3x0_i2c.h.

#define I2C_FLAG_DUMOD (BIT(7)|BIT(31))

dual flag in slave mode indicating which address is matched in dual-address mode

Definition at line 205 of file gd32f3x0_i2c.h.

#define I2C_FLAG_HSTSMB (BIT(6)|BIT(31))

SMBus host header detected in slave mode

Definition at line 204 of file gd32f3x0_i2c.h.

#define I2C_FLAG_I2CBSY (BIT(1)|BIT(31))

busy flag

Definition at line 200 of file gd32f3x0_i2c.h.

#define I2C_FLAG_LOSTARB BIT(9)

arbitration lost in master mode

Definition at line 193 of file gd32f3x0_i2c.h.

#define I2C_FLAG_MASTER (BIT(0)|BIT(31))

a flag indicating whether I2C block is in master or slave mode

Definition at line 199 of file gd32f3x0_i2c.h.

#define I2C_FLAG_OUERR BIT(11)

over-run or under-run situation occurs in slave mode

Definition at line 195 of file gd32f3x0_i2c.h.

#define I2C_FLAG_PECERR BIT(12)

PEC error when receiving data

Definition at line 196 of file gd32f3x0_i2c.h.

#define I2C_FLAG_RBNE BIT(6)

I2C_DATA is not Empty during receiving

Definition at line 190 of file gd32f3x0_i2c.h.

#define I2C_FLAG_RXGC (BIT(4)|BIT(31))

general call address (00h) received

Definition at line 202 of file gd32f3x0_i2c.h.

#define I2C_FLAG_SBSEND BIT(0)

start condition sent out in master mode

Definition at line 185 of file gd32f3x0_i2c.h.

#define I2C_FLAG_SMBALT BIT(15)

SMBus alert status

Definition at line 198 of file gd32f3x0_i2c.h.

#define I2C_FLAG_SMBTO BIT(14)

timeout signal in SMBus mode

Definition at line 197 of file gd32f3x0_i2c.h.

#define I2C_FLAG_STPDET BIT(4)

etop condition detected in slave mode

Definition at line 189 of file gd32f3x0_i2c.h.

#define I2C_FLAG_TBE BIT(7)

I2C_DATA is empty during transmitting

Definition at line 191 of file gd32f3x0_i2c.h.

#define I2C_FLAG_TRS (BIT(2)|BIT(31))

whether the I2C is a transmitter or a receiver

Definition at line 201 of file gd32f3x0_i2c.h.

#define I2C_FMPCFG ( i2cx ) REG32((i2cx) + 0x90U)

I2C fast-mode-plus configure register

Definition at line 33 of file gd32f3x0_i2c.h.

#define I2C_FMPCFG_FMPEN BIT(0)

fast mode plus enable bit

Definition at line 108 of file gd32f3x0_i2c.h.

#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U)

slave will not response to a general call

Definition at line 141 of file gd32f3x0_i2c.h.

#define I2C_GCEN_ENABLE I2C_CTL0_GCEN

slave will response to a general call

Definition at line 140 of file gd32f3x0_i2c.h.

#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U)

I2C mode

Definition at line 112 of file gd32f3x0_i2c.h.

#define I2C_INT_BUF I2C_CTL1_BUFIE

buffer interrupt enable

Definition at line 226 of file gd32f3x0_i2c.h.

#define I2C_INT_ERR I2C_CTL1_ERRIE

error interrupt enable

Definition at line 224 of file gd32f3x0_i2c.h.

#define I2C_INT_EV I2C_CTL1_EVIE

event interrupt enable

Definition at line 225 of file gd32f3x0_i2c.h.

#define I2C_INT_FLAG_ADD10SEND I2C_FLAG_ADD10SEND

header of 10-bit address is sent in master mode interrupt flag

Definition at line 211 of file gd32f3x0_i2c.h.

#define I2C_INT_FLAG_ADDSEND I2C_FLAG_ADDSEND

address is sent in master mode or received and matches in slave mode interrupt flag

Definition at line 209 of file gd32f3x0_i2c.h.

#define I2C_INT_FLAG_AERR I2C_FLAG_AERR

acknowledge error interrupt flag

Definition at line 217 of file gd32f3x0_i2c.h.

#define I2C_INT_FLAG_BERR I2C_FLAG_BERR

a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag

Definition at line 215 of file gd32f3x0_i2c.h.

#define I2C_INT_FLAG_BTC I2C_FLAG_BTC

byte transmission finishes

Definition at line 210 of file gd32f3x0_i2c.h.

#define I2C_INT_FLAG_LOSTARB I2C_FLAG_LOSTARB

arbitration lost in master mode interrupt flag

Definition at line 216 of file gd32f3x0_i2c.h.

#define I2C_INT_FLAG_OUERR I2C_FLAG_OUERR

over-run or under-run situation occurs in slave mode interrupt flag

Definition at line 218 of file gd32f3x0_i2c.h.

#define I2C_INT_FLAG_PECERR I2C_FLAG_PECERR

PEC error when receiving data interrupt flag

Definition at line 219 of file gd32f3x0_i2c.h.

#define I2C_INT_FLAG_RBNE I2C_FLAG_RBNE

I2C_DATA is not Empty during receiving interrupt flag

Definition at line 213 of file gd32f3x0_i2c.h.

#define I2C_INT_FLAG_SBSEND I2C_FLAG_SBSEND

start condition sent out in master mode interrupt flag

Definition at line 208 of file gd32f3x0_i2c.h.

#define I2C_INT_FLAG_SMBALT I2C_FLAG_SMBALT

SMBus Alert status interrupt flag

Definition at line 221 of file gd32f3x0_i2c.h.

#define I2C_INT_FLAG_SMBTO I2C_FLAG_SMBTO

timeout signal in SMBus mode interrupt flag

Definition at line 220 of file gd32f3x0_i2c.h.

#define I2C_INT_FLAG_STPDET I2C_FLAG_STPDET

stop condition detected in slave mode interrupt flag

Definition at line 212 of file gd32f3x0_i2c.h.

#define I2C_INT_FLAG_TBE I2C_FLAG_TBE

I2C_DATA is empty during transmitting interrupt flag

Definition at line 214 of file gd32f3x0_i2c.h.

#define I2C_PEC_DISABLE ((uint32_t)0x00000000U)

PEC calculation off

Definition at line 159 of file gd32f3x0_i2c.h.

#define I2C_PEC_ENABLE I2C_CTL0_PECEN

PEC calculation on

Definition at line 158 of file gd32f3x0_i2c.h.

#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U)

not transfer PEC value

Definition at line 163 of file gd32f3x0_i2c.h.

#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS

transfer PEC

Definition at line 162 of file gd32f3x0_i2c.h.

#define I2C_RECEIVER ((uint32_t)0x00000001U)

receiver

Definition at line 120 of file gd32f3x0_i2c.h.

#define I2C_RT ( i2cx ) REG32((i2cx) + 0x20U)

I2C rise time register

Definition at line 32 of file gd32f3x0_i2c.h.

#define I2C_RT_RISETIME BITS(0,6)

maximum rise time in fast/standard mode or fast mode plus(master mode)

Definition at line 105 of file gd32f3x0_i2c.h.

#define I2C_SADDR0 ( i2cx ) REG32((i2cx) + 0x08U)

I2C slave address register 0

Definition at line 26 of file gd32f3x0_i2c.h.

#define I2C_SADDR0_ADDFORMAT BIT(15)

address mode for the I2C slave

Definition at line 64 of file gd32f3x0_i2c.h.

#define I2C_SADDR0_ADDRESS BITS(1,7)

7-bit address or bits 7:1 of a 10-bit address

Definition at line 62 of file gd32f3x0_i2c.h.

#define I2C_SADDR0_ADDRESS0 BIT(0)

bit 0 of a 10-bit address

Definition at line 61 of file gd32f3x0_i2c.h.

#define I2C_SADDR0_ADDRESS_H BITS(8,9)

highest two bits of a 10-bit address

Definition at line 63 of file gd32f3x0_i2c.h.

#define I2C_SADDR1 ( i2cx ) REG32((i2cx) + 0x0CU)

I2C slave address register

Definition at line 27 of file gd32f3x0_i2c.h.

#define I2C_SADDR1_ADDRESS2 BITS(1,7)

second I2C address for the slave in dual-address mode

Definition at line 68 of file gd32f3x0_i2c.h.

#define I2C_SADDR1_DUADEN BIT(0)

aual-address mode switch

Definition at line 67 of file gd32f3x0_i2c.h.

#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U)

not issue alert through SMBA

Definition at line 168 of file gd32f3x0_i2c.h.

#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT

issue alert through SMBA pin

Definition at line 167 of file gd32f3x0_i2c.h.

#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC

SCL stretching is disabled

Definition at line 137 of file gd32f3x0_i2c.h.

#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U)

SCL stretching is enabled

Definition at line 136 of file gd32f3x0_i2c.h.

#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U)

SMBus mode device type

Definition at line 116 of file gd32f3x0_i2c.h.

#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL

SMBus mode host type

Definition at line 117 of file gd32f3x0_i2c.h.

#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN

SMBus mode

Definition at line 113 of file gd32f3x0_i2c.h.

#define I2C_SRESET_RESET ((uint32_t)0x00000000U)

I2C is not under reset

Definition at line 145 of file gd32f3x0_i2c.h.

#define I2C_SRESET_SET I2C_CTL0_SRESET

I2C is under reset

Definition at line 144 of file gd32f3x0_i2c.h.

#define I2C_STAT0 ( i2cx ) REG32((i2cx) + 0x14U)

I2C transfer status register 0

Definition at line 29 of file gd32f3x0_i2c.h.

#define I2C_STAT0_ADD10SEND BIT(3)

10-bit header sent (master mode)

Definition at line 77 of file gd32f3x0_i2c.h.

#define I2C_STAT0_ADDSEND BIT(1)

address sent (master mode)/matched (slave mode)

Definition at line 75 of file gd32f3x0_i2c.h.

#define I2C_STAT0_AERR BIT(10)

acknowledge failure

Definition at line 83 of file gd32f3x0_i2c.h.

#define I2C_STAT0_BERR BIT(8)

bus error

Definition at line 81 of file gd32f3x0_i2c.h.

#define I2C_STAT0_BTC BIT(2)

byte transfer finished

Definition at line 76 of file gd32f3x0_i2c.h.

#define I2C_STAT0_LOSTARB BIT(9)

arbitration lost (master mode)

Definition at line 82 of file gd32f3x0_i2c.h.

#define I2C_STAT0_OUERR BIT(11)

overrun/underrun

Definition at line 84 of file gd32f3x0_i2c.h.

#define I2C_STAT0_PECERR BIT(12)

PEC error in reception

Definition at line 85 of file gd32f3x0_i2c.h.

#define I2C_STAT0_RBNE BIT(6)

data register not empty (receivers)

Definition at line 79 of file gd32f3x0_i2c.h.

#define I2C_STAT0_SBSEND BIT(0)

start bit (master mode)

Definition at line 74 of file gd32f3x0_i2c.h.

#define I2C_STAT0_SMBALT BIT(15)

SMBus alert status

Definition at line 87 of file gd32f3x0_i2c.h.

#define I2C_STAT0_SMBTO BIT(14)

timeout signal in SMBus mode

Definition at line 86 of file gd32f3x0_i2c.h.

#define I2C_STAT0_STPDET BIT(4)

stop detection (slave mode)

Definition at line 78 of file gd32f3x0_i2c.h.

#define I2C_STAT0_TBE BIT(7)

data register empty (transmitters)

Definition at line 80 of file gd32f3x0_i2c.h.

#define I2C_STAT1 ( i2cx ) REG32((i2cx) + 0x18U)

I2C transfer status register

Definition at line 30 of file gd32f3x0_i2c.h.

#define I2C_STAT1_DEFSMB BIT(5)

SMBus device default address (slave mode)

Definition at line 94 of file gd32f3x0_i2c.h.

#define I2C_STAT1_DUMODF BIT(7)

dual flag (slave mode)

Definition at line 96 of file gd32f3x0_i2c.h.

#define I2C_STAT1_ECV BITS(8,15)

packet error checking value

Definition at line 97 of file gd32f3x0_i2c.h.

#define I2C_STAT1_HSTSMB BIT(6)

SMBus host header (slave mode)

Definition at line 95 of file gd32f3x0_i2c.h.

#define I2C_STAT1_I2CBSY BIT(1)

bus busy

Definition at line 91 of file gd32f3x0_i2c.h.

#define I2C_STAT1_MASTER BIT(0)

master/slave

Definition at line 90 of file gd32f3x0_i2c.h.

#define I2C_STAT1_RXGC BIT(4)

general call address (slave mode)

Definition at line 93 of file gd32f3x0_i2c.h.

#define I2C_STAT1_TRS BIT(2)

transmitter/receiver

Definition at line 92 of file gd32f3x0_i2c.h.

#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU)

transmitter

Definition at line 121 of file gd32f3x0_i2c.h.

#define SADDR0_ADDFORMAT ( regval ) (BIT(15) & ((uint32_t)(regval) << 15))

Definition at line 234 of file gd32f3x0_i2c.h.

Function Documentation

void i2c_ack_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | ack
 | ) |  |

whether or not to send an ACK

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] ack
  • I2C_ACK_ENABLE: ACK will be sent
  • I2C_ACK_DISABLE: ACK will not be sent
[out] | none
Return values
none

Definition at line 180 of file gd32f3x0_i2c.c.

181 {
182 if(I2C_ACK_ENABLE == ack){
183 I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
184 }else{
185 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN);
186 }
187 }
I2C_ACK_ENABLE
#define I2C_ACK_ENABLE
Definition: gd32f3x0_i2c.h:125
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
I2C_CTL0_ACKEN
#define I2C_CTL0_ACKEN
Definition: gd32f3x0_i2c.h:46
void i2c_ackpos_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | pos
 | ) |  |

I2C POAP position configure.

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] pos
  • I2C_ACKPOS_CURRENT: whether to send ACK or not for the current
  • I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte
[out] | none
Return values
none

Definition at line 198 of file gd32f3x0_i2c.c.

199 {
200 /* configure I2C POAP position */
201 if(I2C_ACKPOS_NEXT == pos){
202 I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
203 }else{
204 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP);
205 }
206 }
I2C_CTL0_POAP
#define I2C_CTL0_POAP
Definition: gd32f3x0_i2c.h:47
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
I2C_ACKPOS_NEXT
#define I2C_ACKPOS_NEXT
Definition: gd32f3x0_i2c.h:128
void i2c_clock_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | clkspeed,
 |  | uint32_t | dutycyc
 | ) |  |

configure I2C clock

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] | clkspeed | I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) and fast mode plus (up to 1MHz)
[in] dutycyc duty cycle in fast mode or fast mode plus
  • I2C_DTCY_2: T_low/T_high=2
  • I2C_DTCY_16_9: T_low/T_high=16/9
[out] | none
Return values
none

Definition at line 58 of file gd32f3x0_i2c.c.

59 {
60 uint32_t pclk1,clkc,freq,risetime;
61 uint32_t temp;
62
63 pclk1 = rcu_clock_freq_get(CK_APB1);
64 /* I2C peripheral clock frequency */
65 freq = (uint32_t)(pclk1/1000000U);
66 if(freq >= I2CCLK_MAX){
67 freq = I2CCLK_MAX;
68 }
69 temp = I2C_CTL1(i2c_periph);
70 temp &= ~I2C_CTL1_I2CCLK;
71 temp |= freq;
72
73 I2C_CTL1(i2c_periph) = temp;
74
75 if(100000U >= clkspeed){
76 /* the maximum SCL rise time is 1000ns in standard mode */
77 risetime = (uint32_t)((pclk1/1000000U)+1U);
78 if(risetime >= I2CCLK_MAX){
79 I2C_RT(i2c_periph) = I2CCLK_MAX;
80 }else{
81 I2C_RT(i2c_periph) = risetime;
82 }
83 clkc = (uint32_t)(pclk1/(clkspeed*2U));
84 if(clkc < 0x04U){
85 /* the CLKC in standard mode minmum value is 4 */
86 clkc = 0x04U;
87 }
88 I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc);
89
90 }else if(400000U >= clkspeed){
91 /* the maximum SCL rise time is 300ns in fast mode */
92 I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U);
93 if(I2C_DTCY_2 == dutycyc){
94 /* I2C duty cycle is 2 */
95 clkc = (uint32_t)(pclk1/(clkspeed*3U));
96 I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
97 }else{
98 /* I2C duty cycle is 16/9 */
99 clkc = (uint32_t)(pclk1/(clkspeed*25U));
100 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
101 }
102 if(0U == (clkc & I2C_CKCFG_CLKC)){
103 /* the CLKC in fast mode minmum value is 1 */
104 clkc |= 0x0001U;
105 }
106 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
107 I2C_CKCFG(i2c_periph) |= clkc;
108 }else{
109 /* fast mode plus, the maximum SCL rise time is 120ns */
110 I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)120U)/(uint32_t)1000U)+(uint32_t)1U);
111 if(I2C_DTCY_2 == dutycyc){
112 /* I2C duty cycle is 2 */
113 clkc = (uint32_t)(pclk1/(clkspeed*3U));
114 I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
115 }else{
116 /* I2C duty cycle is 16/9 */
117 clkc = (uint32_t)(pclk1/(clkspeed*25U));
118 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
119 }
120 /* enable fast mode */
121 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
122 I2C_CKCFG(i2c_periph) |= clkc;
123 /* enable I2C fast mode plus */
124 I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN;
125 }
126 }
CK_APB1
Definition: gd32f3x0_rcu.h:456
I2C_FMPCFG
#define I2C_FMPCFG(i2cx)
Definition: gd32f3x0_i2c.h:33
I2C_FMPCFG_FMPEN
#define I2C_FMPCFG_FMPEN
Definition: gd32f3x0_i2c.h:108
I2C_CKCFG_CLKC
#define I2C_CKCFG_CLKC
Definition: gd32f3x0_i2c.h:100
I2C_CKCFG_FAST
#define I2C_CKCFG_FAST
Definition: gd32f3x0_i2c.h:102
I2C_CKCFG
#define I2C_CKCFG(i2cx)
Definition: gd32f3x0_i2c.h:31
I2CCLK_MAX
#define I2CCLK_MAX
Definition: gd32f3x0_i2c.c:15
I2C_CKCFG_DTCY
#define I2C_CKCFG_DTCY
Definition: gd32f3x0_i2c.h:101
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f3x0_i2c.h:25
I2C_RT
#define I2C_RT(i2cx)
Definition: gd32f3x0_i2c.h:32
I2C_DTCY_2
#define I2C_DTCY_2
Definition: gd32f3x0_i2c.h:230
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f3x0_rcu.c:964
I2C_CTL1_I2CCLK
#define I2C_CTL1_I2CCLK
Definition: gd32f3x0_i2c.h:53
uint8_t i2c_data_receive ( uint32_t i2c_periph )

I2C receive data function.

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[out] | none
Return values
data of received

Definition at line 308 of file gd32f3x0_i2c.c.

309 {
310 return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph));
311 }
DATA_RECV
#define DATA_RECV(regval)
Definition: gd32f3x0_i2c.h:182
I2C_DATA
#define I2C_DATA(i2cx)
Definition: gd32f3x0_i2c.h:28
void i2c_data_transmit | ( | uint32_t | i2c_periph,
 |  | uint8_t | data
 | ) |  |

I2C transmit data function.

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] | data | data of transmission
[out] | none
Return values
none

Definition at line 297 of file gd32f3x0_i2c.c.

298 {
299 I2C_DATA(i2c_periph) = DATA_TRANS(data);
300 }
DATA_TRANS
#define DATA_TRANS(regval)
Definition: gd32f3x0_i2c.h:179
I2C_DATA
#define I2C_DATA(i2cx)
Definition: gd32f3x0_i2c.h:28
void i2c_deinit ( uint32_t i2c_periph )

reset I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[out] | none
Return values
none

Definition at line 24 of file gd32f3x0_i2c.c.

25 {
26 switch(i2c_periph){
27 case I2C0:
28 /* reset I2C0 */
29 rcu_periph_reset_enable(RCU_I2C0RST);
30 rcu_periph_reset_disable(RCU_I2C0RST);
31 break;
32 case I2C1:
33 /* reset I2C1 */
34 rcu_periph_reset_enable(RCU_I2C1RST);
35 rcu_periph_reset_disable(RCU_I2C1RST);
36 break;
37 case I2C2:
38 /* reset I2C2 */
39 rcu_periph_reset_enable(RCU_I2C2RST);
40 rcu_periph_reset_disable(RCU_I2C2RST);
41 break;
42 default:
43 break;
44 }
45 }
RCU_I2C1RST
Definition: gd32f3x0_rcu.h:352
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
I2C1
#define I2C1
Definition: gd32f3x0_i2c.h:20
RCU_I2C0RST
Definition: gd32f3x0_rcu.h:351
I2C2
#define I2C2
Definition: gd32f3x0_i2c.h:21
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
RCU_I2C2RST
Definition: gd32f3x0_rcu.h:361
I2C0
#define I2C0
Definition: gd32f3x0_i2c.h:19
void i2c_disable ( uint32_t i2c_periph )

disable I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[out] | none
Return values
none

Definition at line 263 of file gd32f3x0_i2c.c.

264 {
265 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN);
266 }
I2C_CTL0_I2CEN
#define I2C_CTL0_I2CEN
Definition: gd32f3x0_i2c.h:37
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_dma_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | dmastate
 | ) |  |

enable I2C DMA mode

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] dmastate
  • I2C_DMA_ON: DMA mode enable
  • I2C_DMA_OFF: DMA mode disable
[out] | none
Return values
none

Definition at line 322 of file gd32f3x0_i2c.c.

323 {
324 /* configure I2C DMA function */
325 uint32_t ctl = 0U;
326 ctl = I2C_CTL1(i2c_periph);
327 ctl &= ~(I2C_CTL1_DMAON);
328 ctl |= dmastate;
329 I2C_CTL1(i2c_periph) = ctl;
330 }
I2C_CTL1_DMAON
#define I2C_CTL1_DMAON
Definition: gd32f3x0_i2c.h:57
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f3x0_i2c.h:25
void i2c_dma_last_transfer_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | dmalast
 | ) |  |

flag indicating DMA last transfer

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] dmalast
  • I2C_DMALST_ON: next DMA EOT is the last transfer
  • I2C_DMALST_OFF: next DMA EOT is not the last transfer
[out] | none
Return values
none

Definition at line 341 of file gd32f3x0_i2c.c.

342 {
343 /* configure DMA last transfer */
344 uint32_t ctl = 0U;
345 ctl = I2C_CTL1(i2c_periph);
346 ctl &= ~(I2C_CTL1_DMALST);
347 ctl |= dmalast;
348 I2C_CTL1(i2c_periph) = ctl;
349 }
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f3x0_i2c.h:25
I2C_CTL1_DMALST
#define I2C_CTL1_DMALST
Definition: gd32f3x0_i2c.h:58
void i2c_dualaddr_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | dualaddr
 | ) |  |

dual-address mode switch

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] dualaddr
  • I2C_DUADEN_DISABLE: disable dual-address mode
  • I2C_DUADEN_ENABLE: enable dual-address mode
[out] | none
Return values
none

Definition at line 237 of file gd32f3x0_i2c.c.

238 {
239 if(I2C_DUADEN_ENABLE == dualaddr){
240 I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN;
241 }else{
242 I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
243 }
244 }
I2C_SADDR1
#define I2C_SADDR1(i2cx)
Definition: gd32f3x0_i2c.h:27
I2C_DUADEN_ENABLE
#define I2C_DUADEN_ENABLE
Definition: gd32f3x0_i2c.h:133
I2C_SADDR1_DUADEN
#define I2C_SADDR1_DUADEN
Definition: gd32f3x0_i2c.h:67
void i2c_enable ( uint32_t i2c_periph )

enable I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[out] | none
Return values
none

Definition at line 252 of file gd32f3x0_i2c.c.

253 {
254 I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN;
255 }
I2C_CTL0_I2CEN
#define I2C_CTL0_I2CEN
Definition: gd32f3x0_i2c.h:37
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_flag_clear | ( | uint32_t | i2c_periph,
 |  | uint32_t | flag
 | ) |  |

clear I2C flag

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] flag flag type
  • I2C_FLAG_SMBALT: SMBus Alert status
  • I2C_FLAG_SMBTO: timeout signal in SMBus mode
  • I2C_FLAG_PECERR: PEC error when receiving data
  • I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode
  • I2C_FLAG_AERR: acknowledge error
  • I2C_FLAG_LOSTARB: arbitration lost in master mode
  • I2C_FLAG_BERR: a bus error
  • I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1
[out] | none
Return values
none

Definition at line 474 of file gd32f3x0_i2c.c.

475 {
476 if(I2C_FLAG_ADDSEND == flag){
477 /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
478 I2C_STAT0(i2c_periph);
479 I2C_STAT1(i2c_periph);
480 }else{
481 I2C_STAT0(i2c_periph) &= ~(flag);
482 }
483 }
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f3x0_i2c.h:29
I2C_FLAG_ADDSEND
#define I2C_FLAG_ADDSEND
Definition: gd32f3x0_i2c.h:186
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f3x0_i2c.h:30
FlagStatus i2c_flag_get | ( | uint32_t | i2c_periph,
 |  | uint32_t | flag
 | ) |  |

check I2C flag is set or not

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] flag
  • I2C_FLAG_SBSEND: start condition send out
  • I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode
  • I2C_FLAG_BTC: byte transmission finishes
  • I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode
  • I2C_FLAG_STPDET: stop condition detected in slave mode
  • I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving
  • I2C_FLAG_TBE: I2C_DATA is empty during transmitting
  • I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
  • I2C_FLAG_LOSTARB: arbitration lost in master mode
  • I2C_FLAG_AERR: acknowledge error
  • I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode
  • I2C_FLAG_PECERR: PEC error when receiving data
  • I2C_FLAG_SMBTO: timeout signal in SMBus mode
  • I2C_FLAG_SMBALT: SMBus alert status
  • I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode
  • I2C_FLAG_I2CBSY: busy flag
  • I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver
  • I2C_FLAG_RXGC: general call address (00h) received
  • I2C_FLAG_DEFSMB: default address of SMBus device
  • I2C_FLAG_HSTSMB: SMBus host header detected in slave mode
  • I2C_FLAG_DUMODF: dual flag in slave mode indicating which address is matched in dual-address mode
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 436 of file gd32f3x0_i2c.c.

437 {
438 uint32_t reg = 0U;
439 FlagStatus reval = RESET;
440 /* get the flag in which register */
441 reg = (BIT(31) & flag);
442 if((BIT(31) == reg)){
443 if((I2C_STAT1(i2c_periph)&(flag & I2C_FLAG_MASK))){
444 reval = SET;
445 }else{
446 reval = RESET;
447 }
448 }else{
449 if((I2C_STAT0(i2c_periph)&(flag & I2C_FLAG_MASK))){
450 reval = SET;
451 }else{
452 reval = RESET;
453 }
454 }
455 /* return the flag status */
456 return reval;
457 }
I2C_FLAG_MASK
#define I2C_FLAG_MASK
Definition: gd32f3x0_i2c.c:16
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f3x0_i2c.h:29
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f3x0_i2c.h:30
void i2c_interrupt_disable | ( | uint32_t | i2c_periph,
 |  | uint32_t | inttype
 | ) |  |

disable I2C interrupt

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] inttype interrupt type
  • I2C_INT_ERR: error interrupt enable
  • I2C_INT_EV: event interrupt enable
  • I2C_INT_BUF: buffer interrupt enable
[out] | none
Return values
none

Definition at line 510 of file gd32f3x0_i2c.c.

511 {
512 I2C_CTL1(i2c_periph) &= ~(inttype);
513 }
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f3x0_i2c.h:25
void i2c_interrupt_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | inttype
 | ) |  |

enable I2C interrupt

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] inttype interrupt type
  • I2C_INT_ERR: error interrupt enable
  • I2C_INT_EV: event interrupt enable
  • I2C_INT_BUF: buffer interrupt enable
[out] | none
Return values
none

Definition at line 495 of file gd32f3x0_i2c.c.

496 {
497 I2C_CTL1(i2c_periph) |= (inttype);
498 }
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f3x0_i2c.h:25
void i2c_interrupt_flag_clear | ( | uint32_t | i2c_periph,
 |  | uint32_t | intflag
 | ) |  |

clear I2C interrupt flag

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] intflag interrupt flag
  • I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
  • I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
  • I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
  • I2C_INT_FLAG_AERR: acknowledge error interrupt flag
  • I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
  • I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
  • I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
  • I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
[out] | none
Return values
none

Definition at line 592 of file gd32f3x0_i2c.c.

593 {
594 if(I2C_INT_FLAG_ADDSEND == intflag){
595 /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
596 I2C_STAT0(i2c_periph);
597 I2C_STAT1(i2c_periph);
598 }else{
599 I2C_STAT0(i2c_periph) &= ~(intflag);
600 }
601 }
I2C_INT_FLAG_ADDSEND
#define I2C_INT_FLAG_ADDSEND
Definition: gd32f3x0_i2c.h:209
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f3x0_i2c.h:29
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f3x0_i2c.h:30
FlagStatus i2c_interrupt_flag_get | ( | uint32_t | i2c_periph,
 |  | uint32_t | intflag
 | ) |  |

check I2C interrupt flag

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] int_flag interrupt flag
  • I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag
  • I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
  • I2C_INT_FLAG_BTC: byte transmission finishes
  • I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag
  • I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag
  • I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag
  • I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag
  • I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
  • I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
  • I2C_INT_FLAG_AERR: acknowledge error interrupt flag
  • I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
  • I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
  • I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
  • I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
[out] | none
Return values
none

Definition at line 536 of file gd32f3x0_i2c.c.

537 {
538 uint32_t evie, errie, bufie;
539
540 evie = I2C_CTL1(i2c_periph)&I2C_CTL1_EVIE;
541 errie = I2C_CTL1(i2c_periph)&I2C_CTL1_ERRIE;
542 /* check I2C event interrupt enable bit */
543 if((intflag&0x00ffU) && evie){
544 if(intflag&0x001fU){
545 /* check I2C event flags except TBE and RBNE */
546 if(intflag & I2C_STAT0(i2c_periph)){
547 return SET;
548 }else{
549 return RESET;
550 }
551 }else{
552 /* check I2C event flags TBE and RBNE */
553 bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;
554 if(bufie){
555 if(intflag & I2C_STAT0(i2c_periph)){
556 return SET;
557 }else{
558 return RESET;
559 }
560 }else{
561 return RESET;
562 }
563 }
564 /* check I2C error interrupt enable bit */
565 }else if((intflag&0xff00U) && errie){
566 /* check I2C error flags */
567 if(intflag & I2C_STAT0(i2c_periph)){
568 return SET;
569 }else{
570 return RESET;
571 }
572 }else{
573 return RESET;
574 }
575 }
I2C_CTL1_ERRIE
#define I2C_CTL1_ERRIE
Definition: gd32f3x0_i2c.h:54
I2C_CTL1_BUFIE
#define I2C_CTL1_BUFIE
Definition: gd32f3x0_i2c.h:56
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f3x0_i2c.h:25
I2C_CTL1_EVIE
#define I2C_CTL1_EVIE
Definition: gd32f3x0_i2c.h:55
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f3x0_i2c.h:29
void i2c_master_addressing | ( | uint32_t | i2c_periph,
 |  | uint32_t | addr,
 |  | uint32_t | trandirection
 | ) |  |

master send slave address

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] | addr | slave address
[in] trandirection transmitter or receiver
  • I2C_TRANSMITTER: transmitter
  • I2C_RECEIVER: receiver
[out] | none
Return values
none

Definition at line 218 of file gd32f3x0_i2c.c.

219 {
220 if(I2C_TRANSMITTER == trandirection){
221 addr = addr & I2C_TRANSMITTER;
222 }else{
223 addr = addr | I2C_RECEIVER;
224 }
225 I2C_DATA(i2c_periph) = addr;
226 }
I2C_RECEIVER
#define I2C_RECEIVER
Definition: gd32f3x0_i2c.h:120
I2C_TRANSMITTER
#define I2C_TRANSMITTER
Definition: gd32f3x0_i2c.h:121
I2C_DATA
#define I2C_DATA(i2cx)
Definition: gd32f3x0_i2c.h:28
void i2c_mode_addr_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | mode,
 |  | uint32_t | addformat,
 |  | uint32_t | addr
 | ) |  |

configure I2C address

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] mode
  • I2C_I2CMODE_ENABLE: I2C mode
  • I2C_SMBUSMODE_ENABLE: SMBus mode
[in] addformat 7bits or 10bits
  • I2C_ADDFORMAT_7BITS: 7bits
  • I2C_ADDFORMAT_10BITS: 10bits
[in] | addr | I2C address
[out] | none
Return values
none

Definition at line 141 of file gd32f3x0_i2c.c.

142 {
143 /* SMBus/I2C mode selected */
144 uint32_t ctl = 0U;
145 ctl = I2C_CTL0(i2c_periph);
146 ctl &= ~(I2C_CTL0_SMBEN);
147 ctl |= mode;
148 I2C_CTL0(i2c_periph) = ctl;
149 /* configure address */
150 I2C_SADDR0(i2c_periph) = (addformat | addr);
151 }
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
I2C_CTL0_SMBEN
#define I2C_CTL0_SMBEN
Definition: gd32f3x0_i2c.h:38
I2C_SADDR0
#define I2C_SADDR0(i2cx)
Definition: gd32f3x0_i2c.h:26
void i2c_pec_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | pecstate
 | ) |  |

I2C PEC calculation on or off.

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] pecpara
  • I2C_PEC_ENABLE: PEC calculation on
  • I2C_PEC_DISABLE: PEC calculation off
[out] | none
Return values
none

Definition at line 612 of file gd32f3x0_i2c.c.

613 {
614 /* on/off PEC calculation */
615 uint32_t ctl = 0U;
616 ctl = I2C_CTL0(i2c_periph);
617 ctl &= ~(I2C_CTL0_PECEN);
618 ctl |= pecstate;
619 I2C_CTL0(i2c_periph) = ctl;
620 }
I2C_CTL0_PECEN
#define I2C_CTL0_PECEN
Definition: gd32f3x0_i2c.h:41
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_pec_transfer_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | pecpara
 | ) |  |

I2C whether to transfer PEC value.

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] pecpara
  • I2C_PECTRANS_ENABLE: transfer PEC
  • I2C_PECTRANS_DISABLE: not transfer PEC
[out] | none
Return values
none

Definition at line 631 of file gd32f3x0_i2c.c.

632 {
633 /* whether to transfer PEC */
634 uint32_t ctl = 0U;
635 ctl = I2C_CTL0(i2c_periph);
636 ctl &= ~(I2C_CTL0_PECTRANS);
637 ctl |= pecpara;
638 I2C_CTL0(i2c_periph) = ctl;
639 }
I2C_CTL0_PECTRANS
#define I2C_CTL0_PECTRANS
Definition: gd32f3x0_i2c.h:48
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
uint8_t i2c_pec_value_get ( uint32_t i2c_periph )

get packet error checking value

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[out] | none
Return values
PEC value

Definition at line 647 of file gd32f3x0_i2c.c.

648 {
649 return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_ECV)>>8);
650 }
I2C_STAT1_ECV
#define I2C_STAT1_ECV
Definition: gd32f3x0_i2c.h:97
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f3x0_i2c.h:30
void i2c_slave_response_to_gcall_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | gcallpara
 | ) |  |

whether or not to response to a general call

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] gcallpara
  • I2C_GCEN_ENABLE: slave will response to a general call
  • I2C_GCEN_DISABLE: slave will not response to a general call
[out] | none
Return values
none

Definition at line 379 of file gd32f3x0_i2c.c.

380 {
381 /* configure slave response to a general call enable or disable */
382 uint32_t ctl = 0U;
383 ctl = I2C_CTL0(i2c_periph);
384 ctl &= ~(I2C_CTL0_GCEN);
385 ctl |= gcallpara;
386 I2C_CTL0(i2c_periph) = ctl;
387 }
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
I2C_CTL0_GCEN
#define I2C_CTL0_GCEN
Definition: gd32f3x0_i2c.h:42
void i2c_smbus_arp_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | arpstate
 | ) |  |

enable or disable I2C ARP protocol in SMBus switch

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] smbuspara
  • I2C_ARP_ENABLE: enable ARP
  • I2C_ARP_DISABLE: disable ARP
[out] | none
Return values
none

Definition at line 680 of file gd32f3x0_i2c.c.

681 {
682 /* enable or disable I2C ARP protocol*/
683 uint32_t ctl = 0U;
684 ctl = I2C_CTL0(i2c_periph);
685 ctl &= ~(I2C_CTL0_ARPEN);
686 ctl |= arpstate;
687 I2C_CTL0(i2c_periph) = ctl;
688 }
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
I2C_CTL0_ARPEN
#define I2C_CTL0_ARPEN
Definition: gd32f3x0_i2c.h:40
void i2c_smbus_issue_alert | ( | uint32_t | i2c_periph,
 |  | uint32_t | smbuspara
 | ) |  |

I2C issue alert through SMBA pin.

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] smbuspara
  • I2C_SALTSEND_ENABLE: issue alert through SMBA pin
  • I2C_SALTSEND_DISABLE: not issue alert through SMBA pin
[out] | none
Return values
none

Definition at line 661 of file gd32f3x0_i2c.c.

662 {
663 /* issue alert through SMBA pin configure*/
664 uint32_t ctl = 0U;
665 ctl = I2C_CTL0(i2c_periph);
666 ctl &= ~(I2C_CTL0_SALT);
667 ctl |= smbuspara;
668 I2C_CTL0(i2c_periph) = ctl;
669 }
I2C_CTL0_SALT
#define I2C_CTL0_SALT
Definition: gd32f3x0_i2c.h:49
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_smbus_type_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | type
 | ) |  |

SMBus type selection.

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] ack
  • I2C_SMBUS_DEVICE: device
  • I2C_SMBUS_HOST: host
[out] | none
Return values
none

Definition at line 162 of file gd32f3x0_i2c.c.

163 {
164 if(I2C_SMBUS_HOST == type){
165 I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
166 }else{
167 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL);
168 }
169 }
I2C_SMBUS_HOST
#define I2C_SMBUS_HOST
Definition: gd32f3x0_i2c.h:117
I2C_CTL0_SMBSEL
#define I2C_CTL0_SMBSEL
Definition: gd32f3x0_i2c.h:39
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_software_reset_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | sreset
 | ) |  |

software reset I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] sreset
  • I2C_SRESET_SET: I2C is under reset
  • I2C_SRESET_RESET: I2C is not under reset
[out] | none
Return values
none

Definition at line 398 of file gd32f3x0_i2c.c.

399 {
400 /* modify CTL0 and configure software reset I2C state */
401 uint32_t ctl = 0U;
402 ctl = I2C_CTL0(i2c_periph);
403 ctl &= ~(I2C_CTL0_SRESET);
404 ctl |= sreset;
405 I2C_CTL0(i2c_periph) = ctl;
406 }
I2C_CTL0_SRESET
#define I2C_CTL0_SRESET
Definition: gd32f3x0_i2c.h:50
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_start_on_bus ( uint32_t i2c_periph )

generate a START condition on I2C bus

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[out] | none
Return values
none

Definition at line 274 of file gd32f3x0_i2c.c.

275 {
276 I2C_CTL0(i2c_periph) |= I2C_CTL0_START;
277 }
I2C_CTL0_START
#define I2C_CTL0_START
Definition: gd32f3x0_i2c.h:44
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_stop_on_bus ( uint32_t i2c_periph )

generate a STOP condition on I2C bus

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[out] | none
Return values
none

Definition at line 285 of file gd32f3x0_i2c.c.

286 {
287 I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP;
288 }
I2C_CTL0_STOP
#define I2C_CTL0_STOP
Definition: gd32f3x0_i2c.h:45
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_stretch_scl_low_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | stretchpara
 | ) |  |

whether to stretch SCL low when data is not ready in slave mode

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] stretchpara
  • I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled
  • I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled
[out] | none
Return values
none

Definition at line 360 of file gd32f3x0_i2c.c.

361 {
362 /* configure I2C SCL strerching enable or disable */
363 uint32_t ctl = 0U;
364 ctl = I2C_CTL0(i2c_periph);
365 ctl &= ~(I2C_CTL0_DISSTRC);
366 ctl |= stretchpara;
367 I2C_CTL0(i2c_periph) = ctl;
368 }
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
I2C_CTL0_DISSTRC
#define I2C_CTL0_DISSTRC
Definition: gd32f3x0_i2c.h:43
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_misc.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Functions
gd32f3x0_misc.h File Reference

definitions for the MISC More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | NVIC_VECTTAB_RAM ((uint32_t)0x20000000)
#define | NVIC_VECTTAB_FLASH ((uint32_t)0x08000000)
#define | NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80)
#define | NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
#define | NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700)
#define | NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600)
#define | NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500)
#define | NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400)
#define | NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300)
#define | SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)
#define | SCB_SCR_SLEEPDEEP ((uint8_t)0x04)
#define | SCB_SCR_SEVONPEND ((uint8_t)0x10)
#define | SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT
#define | SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP
#define | SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND
#define | SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU)
#define | SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)

Functions

void | nvic_priority_group_set (uint32_t nvic_prigroup)
set the priority group More...
void | nvic_irq_enable (uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority)
enable NVIC request More...
void | nvic_irq_disable (uint8_t nvic_irq)
disable NVIC request More...
void | nvic_vector_table_set (uint32_t nvic_vict_tab, uint32_t offset)
set the NVIC vector table base address More...
void | system_lowpower_set (uint8_t lowpower_mode)
set the state of the low power mode More...
void | system_lowpower_reset (uint8_t lowpower_mode)
reset the state of the low power mode More...
void | systick_clksource_set (uint32_t systick_clksource)
set the systick clock source More...

Detailed Description

definitions for the MISC

Definition in file gd32f3x0_misc.h.

Macro Definition Documentation

#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)

NVIC VECTKEY mask

Definition at line 26 of file gd32f3x0_misc.h.

#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700)

0 bits for pre-emption priority 4 bits for subpriority

Definition at line 29 of file gd32f3x0_misc.h.

#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600)

1 bits for pre-emption priority 3 bits for subpriority

Definition at line 30 of file gd32f3x0_misc.h.

#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500)

2 bits for pre-emption priority 2 bits for subpriority

Definition at line 31 of file gd32f3x0_misc.h.

#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400)

3 bits for pre-emption priority 1 bits for subpriority

Definition at line 32 of file gd32f3x0_misc.h.

#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300)

4 bits for pre-emption priority 0 bits for subpriority

Definition at line 33 of file gd32f3x0_misc.h.

#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000)

Flash base address

Definition at line 20 of file gd32f3x0_misc.h.

#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80)

NVIC vector table offset mask

Definition at line 23 of file gd32f3x0_misc.h.

#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000)

RAM base address

Definition at line 19 of file gd32f3x0_misc.h.

#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP

DEEPSLEEP mode or SLEEP mode

Definition at line 41 of file gd32f3x0_misc.h.

#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT

low power mode by exiting from ISR

Definition at line 40 of file gd32f3x0_misc.h.

#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND

wakeup by all interrupt

Definition at line 42 of file gd32f3x0_misc.h.

#define SCB_SCR_SEVONPEND ((uint8_t)0x10)

choose the interrupt source that can wake up the lowpower mode

Definition at line 38 of file gd32f3x0_misc.h.

#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04)

choose the the system enter the DEEPSLEEP mode or SLEEP mode

Definition at line 37 of file gd32f3x0_misc.h.

#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)

choose the the system whether enter low power mode by exiting from ISR

Definition at line 36 of file gd32f3x0_misc.h.

#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)

systick clock source is from HCLK

Definition at line 46 of file gd32f3x0_misc.h.

#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU)

systick clock source is from HCLK/8

Definition at line 45 of file gd32f3x0_misc.h.

Function Documentation

void nvic_irq_disable ( uint8_t nvic_irq )

disable NVIC request

Parameters
[in] | nvic_irq | the NVIC interrupt request, detailed in IRQn_Type
[out] | none
Return values
none

Definition at line 87 of file gd32f3x0_misc.c.

88 {
89 /* disable the selected IRQ.*/
90 NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F);
91 }
void nvic_irq_enable | ( | uint8_t | nvic_irq,
 |  | uint8_t | nvic_irq_pre_priority,
 |  | uint8_t | nvic_irq_sub_priority
 | ) |  |

enable NVIC request

Parameters
[in] | nvic_irq | the NVIC interrupt request, detailed in IRQn_Type
[in] | nvic_irq_pre_priority | the pre-emption priority needed to set
[in] | nvic_irq_sub_priority | the subpriority needed to set
[out] | none
Return values
none

Definition at line 39 of file gd32f3x0_misc.c.

42 {
43 uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
44
45 /* use the priority group value to get the temp_pre and the temp_sub */
46 switch ((SCB->AIRCR) & (uint32_t)0x700U) {
47 case NVIC_PRIGROUP_PRE0_SUB4:
48 temp_pre = 0U;
49 temp_sub = 0x4U;
50 break;
51 case NVIC_PRIGROUP_PRE1_SUB3:
52 temp_pre = 1U;
53 temp_sub = 0x3U;
54 break;
55 case NVIC_PRIGROUP_PRE2_SUB2:
56 temp_pre = 2U;
57 temp_sub = 0x2U;
58 break;
59 case NVIC_PRIGROUP_PRE3_SUB1:
60 temp_pre = 3U;
61 temp_sub = 0x1U;
62 break;
63 case NVIC_PRIGROUP_PRE4_SUB0:
64 temp_pre = 4U;
65 temp_sub = 0x0U;
66 break;
67 default:
68 break;
69 }
70
71 /* get the temp_priority to fill the NVIC->IP register */
72 temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
73 temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
74 temp_priority = temp_priority << 0x04U;
75 NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
76
77 /* enable the selected IRQ */
78 NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
79 }
NVIC_PRIGROUP_PRE2_SUB2
#define NVIC_PRIGROUP_PRE2_SUB2
Definition: gd32f3x0_misc.h:31
NVIC_PRIGROUP_PRE0_SUB4
#define NVIC_PRIGROUP_PRE0_SUB4
Definition: gd32f3x0_misc.h:29
NVIC_PRIGROUP_PRE4_SUB0
#define NVIC_PRIGROUP_PRE4_SUB0
Definition: gd32f3x0_misc.h:33
NVIC_PRIGROUP_PRE1_SUB3
#define NVIC_PRIGROUP_PRE1_SUB3
Definition: gd32f3x0_misc.h:30
NVIC_PRIGROUP_PRE3_SUB1
#define NVIC_PRIGROUP_PRE3_SUB1
Definition: gd32f3x0_misc.h:32
void nvic_priority_group_set ( uint32_t nvic_prigroup )

set the priority group

Parameters
[in] nvic_prigroup the NVIC priority group
  • NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
  • NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
  • NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
  • NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
  • NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
[out] none
Return values
none

Definition at line 25 of file gd32f3x0_misc.c.

26 {
27 /* set the priority group value */
28 SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
29 }
NVIC_AIRCR_VECTKEY_MASK
#define NVIC_AIRCR_VECTKEY_MASK
Definition: gd32f3x0_misc.h:26
void nvic_vector_table_set | ( | uint32_t | nvic_vict_tab,
 |  | uint32_t | offset
 | ) |  |

set the NVIC vector table base address

Parameters
[in] nvic_vict_tab the RAM or FLASH base address
  • NVIC_VECTTAB_RAM: RAM base address NVIC_VECTTAB_FLASH: Flash base address
[in] | offset | Vector Table offset
[out] | none
Return values
none

Definition at line 102 of file gd32f3x0_misc.c.

103 {
104 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
105 }
NVIC_VECTTAB_OFFSET_MASK
#define NVIC_VECTTAB_OFFSET_MASK
Definition: gd32f3x0_misc.h:23
void system_lowpower_reset ( uint8_t lowpower_mode )

reset the state of the low power mode

Parameters
[in] lowpower_mode the low power mode state
  • SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power mode by exiting from ISR
  • SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
  • SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be woke up by the enable interrupts
[out] none
Return values
none

Definition at line 134 of file gd32f3x0_misc.c.

135 {
136 SCB->SCR &= (~(uint32_t)lowpower_mode);
137 }
void system_lowpower_set ( uint8_t lowpower_mode )

set the state of the low power mode

Parameters
[in] lowpower_mode the low power mode state
  • SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power mode by exiting from ISR
  • SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
  • SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up by all the enable and disable interrupts
[out] none
Return values
none

Definition at line 118 of file gd32f3x0_misc.c.

119 {
120 SCB->SCR |= (uint32_t)lowpower_mode;
121 }
void systick_clksource_set ( uint32_t systick_clksource )

set the systick clock source

Parameters
[in] systick_clksource the systick clock source needed to choose
  • SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
  • SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
[out] none
Return values
none

Definition at line 148 of file gd32f3x0_misc.c.

149 {
150 if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
151 /* set the systick clock source from HCLK */
152 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
153 }else{
154 /* set the systick clock source from HCLK/8 */
155 SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
156 }
157 }
SYSTICK_CLKSOURCE_HCLK_DIV8
#define SYSTICK_CLKSOURCE_HCLK_DIV8
Definition: gd32f3x0_misc.h:45
SYSTICK_CLKSOURCE_HCLK
#define SYSTICK_CLKSOURCE_HCLK
Definition: gd32f3x0_misc.h:46
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_pmu.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Functions
gd32f3x0_pmu.h File Reference

definitions for the PMU More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | PMU PMU_BASE
#define | PMU_CTL REG32((PMU) + 0x00U)
#define | PMU_CS REG32((PMU) + 0x04U)
#define | PMU_CTL_LDOLP BIT(0)
#define | PMU_CTL_STBMOD BIT(1)
#define | PMU_CTL_WURST BIT(2)
#define | PMU_CTL_STBRST BIT(3)
#define | PMU_CTL_LVDEN BIT(4)
#define | PMU_CTL_LVDT BITS(5,7)
#define | PMU_CTL_BKPWEN BIT(8)
#define | PMU_CTL_LDLP BIT(10)
#define | PMU_CTL_LDNP BIT(11)
#define | PMU_CTL_LDOVS BITS(14,15)
#define | PMU_CTL_HDEN BIT(16)
#define | PMU_CTL_HDS BIT(17)
#define | PMU_CTL_LDEN BITS(18,19)
#define | PMU_CS_WUF BIT(0)
#define | PMU_CS_STBF BIT(1)
#define | PMU_CS_LVDF BIT(2)
#define | PMU_CS_WUPEN0 BIT(8)
#define | PMU_CS_WUPEN1 BIT(9)
#define | PMU_CS_WUPEN4 BIT(12)
#define | PMU_CS_WUPEN5 BIT(13)
#define | PMU_CS_WUPEN6 BIT(14)
#define | PMU_CS_LDOVSRF BIT(15)
#define | PMU_CS_HDRF BIT(16)
#define | PMU_CS_HDSRF BIT(17)
#define | PMU_CS_LDRF BITS(18,19)
#define | CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
#define | PMU_LVDT_0 CTL_LVDT(0)
#define | PMU_LVDT_1 CTL_LVDT(1)
#define | PMU_LVDT_2 CTL_LVDT(2)
#define | PMU_LVDT_3 CTL_LVDT(3)
#define | PMU_LVDT_4 CTL_LVDT(4)
#define | PMU_LVDT_5 CTL_LVDT(5)
#define | PMU_LVDT_6 CTL_LVDT(6)
#define | PMU_LVDT_7 CTL_LVDT(7)
#define | CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14))
#define | PMU_LDOVS_LOW CTL_LDOVS(1)
#define | PMU_LDOVS_MID CTL_LDOVS(2)
#define | PMU_LDOVS_HIGH CTL_LDOVS(3)
#define | CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
#define | PMU_LOWDRIVER_DISABLE CTL_LDEN(0)
#define | PMU_LOWDRIVER_ENABLE CTL_LDEN(3)
#define | PMU_HIGHDR_SWITCH_NONE ((uint32_t)0x00000000U)
#define | PMU_HIGHDR_SWITCH_EN PMU_CTL_HDS
#define | PMU_NORMALDR_NORMALPWR ((uint32_t)0x00000000U)
#define | PMU_LOWDR_NORMALPWR PMU_CTL_LDNP
#define | PMU_NORMALDR_LOWPWR ((uint32_t)0x00000000U)
#define | PMU_LOWDR_LOWPWR PMU_CTL_LDLP
#define | PMU_LDO_NORMAL ((uint32_t)0x00000000U)
#define | PMU_LDO_LOWPOWER PMU_CTL_LDOLP
#define | CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
#define | PMU_LDRF_NORMAL CS_LDRF(0)
#define | PMU_LDRF_LOWDRIVER CS_LDRF(3)
#define | PMU_FLAG_WAKEUP PMU_CS_WUF
#define | PMU_FLAG_STANDBY PMU_CS_STBF
#define | PMU_FLAG_LVD PMU_CS_LVDF
#define | PMU_FLAG_LDOVSR PMU_CS_LDOVSRF
#define | PMU_FLAG_HDR PMU_CS_HDRF
#define | PMU_FLAG_HDSR PMU_CS_HDSRF
#define | PMU_FLAG_LDR PMU_CS_LDRF
#define | PMU_WAKEUP_PIN0 PMU_CS_WUPEN0
#define | PMU_WAKEUP_PIN1 PMU_CS_WUPEN1
#define | PMU_WAKEUP_PIN4 PMU_CS_WUPEN4
#define | PMU_WAKEUP_PIN5 PMU_CS_WUPEN5
#define | PMU_WAKEUP_PIN6 PMU_CS_WUPEN6
#define | PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST
#define | PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST
#define | WFI_CMD ((uint8_t)0x00U)
#define | WFE_CMD ((uint8_t)0x01U)

Functions

void | pmu_deinit (void)
reset PMU register More...
void | pmu_lvd_select (uint32_t lvdt_n)
select low voltage detector threshold More...
void | pmu_ldo_output_select (uint32_t ldo_output)
select LDO output voltage these bits set by software when the main PLL closed More...
void | pmu_lvd_disable (void)
disable PMU lvd More...
void | pmu_lowdriver_mode_enable (void)
enable low-driver mode in deep-sleep mode More...
void | pmu_lowdriver_mode_disable (void)
enable low-driver mode in deep-sleep mode More...
void | pmu_highdriver_mode_enable (void)
enable high-driver mode this bit set by software only when IRC8M or HXTAL used as system clock More...
void | pmu_highdriver_mode_disable (void)
disable high-driver mode More...
void | pmu_highdriver_switch_select (uint32_t highdr_switch)
switch high-driver mode this bit set by software only when IRC8M or HXTAL used as system clock More...
void | pmu_lowpower_driver_config (uint32_t mode)
low-driver mode when use low power LDO More...
void | pmu_normalpower_driver_config (uint32_t mode)
low-driver mode when use normal power LDO More...
void | pmu_to_sleepmode (uint8_t sleepmodecmd)
PMU work at sleep mode. More...
void | pmu_to_deepsleepmode (uint32_t ldo, uint8_t deepsleepmodecmd)
PMU work at deepsleep mode. More...
void | pmu_to_standbymode (uint8_t standbymodecmd)
pmu work at standby mode More...
void | pmu_wakeup_pin_enable (uint32_t wakeup_pin)
enable wakeup pin More...
void | pmu_wakeup_pin_disable (uint32_t wakeup_pin)
disable wakeup pin More...
void | pmu_backup_write_enable (void)
enable backup domain write More...
void | pmu_backup_write_disable (void)
disable backup domain write More...
void | pmu_flag_clear (uint32_t flag_clear)
clear flag bit More...
FlagStatus | pmu_flag_get (uint32_t flag)
get flag state More...

Detailed Description

definitions for the PMU

Definition in file gd32f3x0_pmu.h.

Macro Definition Documentation

#define CS_LDRF ( regval ) (BITS(18,19)&((uint32_t)(regval)<<18))

Definition at line 94 of file gd32f3x0_pmu.h.

#define CTL_LDEN ( regval ) (BITS(18,19)&((uint32_t)(regval)<<18))

Definition at line 73 of file gd32f3x0_pmu.h.

#define CTL_LDOVS ( regval ) (BITS(14,15)&((uint32_t)(regval)<<14))

Definition at line 67 of file gd32f3x0_pmu.h.

#define CTL_LVDT ( regval ) (BITS(5,7)&((uint32_t)(regval)<<5))

Definition at line 56 of file gd32f3x0_pmu.h.

#define PMU PMU_BASE

PMU base address

Definition at line 18 of file gd32f3x0_pmu.h.

#define PMU_CS REG32((PMU) + 0x04U)

PMU control and status register

Definition at line 22 of file gd32f3x0_pmu.h.

#define PMU_CS_HDRF BIT(16)

high-driver ready flag

Definition at line 50 of file gd32f3x0_pmu.h.

#define PMU_CS_HDSRF BIT(17)

high-driver switch ready flag

Definition at line 51 of file gd32f3x0_pmu.h.

#define PMU_CS_LDOVSRF BIT(15)

LDO voltage select ready flag

Definition at line 49 of file gd32f3x0_pmu.h.

#define PMU_CS_LDRF BITS(18,19)

low-driver mode ready flag

Definition at line 52 of file gd32f3x0_pmu.h.

#define PMU_CS_LVDF BIT(2)

low voltage detector status flag

Definition at line 43 of file gd32f3x0_pmu.h.

#define PMU_CS_STBF BIT(1)

standby flag

Definition at line 42 of file gd32f3x0_pmu.h.

#define PMU_CS_WUF BIT(0)

wakeup flag

Definition at line 41 of file gd32f3x0_pmu.h.

#define PMU_CS_WUPEN0 BIT(8)

wakeup pin enable

Definition at line 44 of file gd32f3x0_pmu.h.

#define PMU_CS_WUPEN1 BIT(9)

wakeup pin enable

Definition at line 45 of file gd32f3x0_pmu.h.

#define PMU_CS_WUPEN4 BIT(12)

wakeup pin enable

Definition at line 46 of file gd32f3x0_pmu.h.

#define PMU_CS_WUPEN5 BIT(13)

wakeup pin enable

Definition at line 47 of file gd32f3x0_pmu.h.

#define PMU_CS_WUPEN6 BIT(14)

wakeup pin enable

Definition at line 48 of file gd32f3x0_pmu.h.

#define PMU_CTL REG32((PMU) + 0x00U)

PMU control register

Definition at line 21 of file gd32f3x0_pmu.h.

#define PMU_CTL_BKPWEN BIT(8)

backup domain write enable

Definition at line 32 of file gd32f3x0_pmu.h.

#define PMU_CTL_HDEN BIT(16)

high-driver mode enable

Definition at line 36 of file gd32f3x0_pmu.h.

#define PMU_CTL_HDS BIT(17)

high-driver mode switch

Definition at line 37 of file gd32f3x0_pmu.h.

#define PMU_CTL_LDEN BITS(18,19)

low-driver mode enable in deep-sleep mode

Definition at line 38 of file gd32f3x0_pmu.h.

#define PMU_CTL_LDLP BIT(10)

low-driver mode when use low power LDO

Definition at line 33 of file gd32f3x0_pmu.h.

#define PMU_CTL_LDNP BIT(11)

low-driver mode when use normal power LDO

Definition at line 34 of file gd32f3x0_pmu.h.

#define PMU_CTL_LDOLP BIT(0)

LDO low power mode

Definition at line 26 of file gd32f3x0_pmu.h.

#define PMU_CTL_LDOVS BITS(14,15)

LDO output voltage select

Definition at line 35 of file gd32f3x0_pmu.h.

#define PMU_CTL_LVDEN BIT(4)

low voltage detector enable

Definition at line 30 of file gd32f3x0_pmu.h.

#define PMU_CTL_LVDT BITS(5,7)

low voltage detector threshold

Definition at line 31 of file gd32f3x0_pmu.h.

#define PMU_CTL_STBMOD BIT(1)

standby mode

Definition at line 27 of file gd32f3x0_pmu.h.

#define PMU_CTL_STBRST BIT(3)

standby flag reset

Definition at line 29 of file gd32f3x0_pmu.h.

#define PMU_CTL_WURST BIT(2)

wakeup flag reset

Definition at line 28 of file gd32f3x0_pmu.h.

#define PMU_FLAG_HDR PMU_CS_HDRF

high-driver ready flag

Definition at line 103 of file gd32f3x0_pmu.h.

#define PMU_FLAG_HDSR PMU_CS_HDSRF

high-driver switch ready flag

Definition at line 104 of file gd32f3x0_pmu.h.

#define PMU_FLAG_LDOVSR PMU_CS_LDOVSRF

LDO voltage select ready flag

Definition at line 102 of file gd32f3x0_pmu.h.

#define PMU_FLAG_LDR PMU_CS_LDRF

low-driver mode ready flag

Definition at line 105 of file gd32f3x0_pmu.h.

#define PMU_FLAG_LVD PMU_CS_LVDF

LVD flag status

Definition at line 101 of file gd32f3x0_pmu.h.

#define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST

standby flag reset

Definition at line 116 of file gd32f3x0_pmu.h.

#define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST

wakeup flag reset

Definition at line 115 of file gd32f3x0_pmu.h.

#define PMU_FLAG_STANDBY PMU_CS_STBF

standby flag status

Definition at line 100 of file gd32f3x0_pmu.h.

#define PMU_FLAG_WAKEUP PMU_CS_WUF

wakeup flag status

Definition at line 99 of file gd32f3x0_pmu.h.

#define PMU_HIGHDR_SWITCH_EN PMU_CTL_HDS

high-driver mode switch

Definition at line 79 of file gd32f3x0_pmu.h.

#define PMU_HIGHDR_SWITCH_NONE ((uint32_t)0x00000000U)

no high-driver mode switch

Definition at line 78 of file gd32f3x0_pmu.h.

#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP

LDO work at low power status when PMU enter deepsleep mode

Definition at line 91 of file gd32f3x0_pmu.h.

#define PMU_LDO_NORMAL ((uint32_t)0x00000000U)

LDO operates normally when PMU enter deepsleep mode

Definition at line 90 of file gd32f3x0_pmu.h.

#define PMU_LDOVS_HIGH CTL_LDOVS(3)

LDO output voltage high mode

Definition at line 70 of file gd32f3x0_pmu.h.

#define PMU_LDOVS_LOW CTL_LDOVS(1)

LDO output voltage low mode

Definition at line 68 of file gd32f3x0_pmu.h.

#define PMU_LDOVS_MID CTL_LDOVS(2)

LDO output voltage mid mode

Definition at line 69 of file gd32f3x0_pmu.h.

#define PMU_LDRF_LOWDRIVER CS_LDRF(3)

low-driver mode in deep-sleep mode

Definition at line 96 of file gd32f3x0_pmu.h.

#define PMU_LDRF_NORMAL CS_LDRF(0)

normal-driver in deep-sleep mode

Definition at line 95 of file gd32f3x0_pmu.h.

#define PMU_LOWDR_LOWPWR PMU_CTL_LDLP

low-driver mode enabled when LDEN is 11 and use low power LDO

Definition at line 87 of file gd32f3x0_pmu.h.

#define PMU_LOWDR_NORMALPWR PMU_CTL_LDNP

low-driver mode enabled when LDEN is 11 and use normal power LDO

Definition at line 83 of file gd32f3x0_pmu.h.

#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0)

low-driver mode disable in deep-sleep mode

Definition at line 74 of file gd32f3x0_pmu.h.

#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3)

low-driver mode enable in deep-sleep mode

Definition at line 75 of file gd32f3x0_pmu.h.

#define PMU_LVDT_0 CTL_LVDT(0)

voltage threshold is 2.1V

Definition at line 57 of file gd32f3x0_pmu.h.

#define PMU_LVDT_1 CTL_LVDT(1)

voltage threshold is 2.3V

Definition at line 58 of file gd32f3x0_pmu.h.

#define PMU_LVDT_2 CTL_LVDT(2)

voltage threshold is 2.4V

Definition at line 59 of file gd32f3x0_pmu.h.

#define PMU_LVDT_3 CTL_LVDT(3)

voltage threshold is 2.6V

Definition at line 60 of file gd32f3x0_pmu.h.

#define PMU_LVDT_4 CTL_LVDT(4)

voltage threshold is 2.7V

Definition at line 61 of file gd32f3x0_pmu.h.

#define PMU_LVDT_5 CTL_LVDT(5)

voltage threshold is 2.9V

Definition at line 62 of file gd32f3x0_pmu.h.

#define PMU_LVDT_6 CTL_LVDT(6)

voltage threshold is 3.0V

Definition at line 63 of file gd32f3x0_pmu.h.

#define PMU_LVDT_7 CTL_LVDT(7)

voltage threshold is 3.1V

Definition at line 64 of file gd32f3x0_pmu.h.

#define PMU_NORMALDR_LOWPWR ((uint32_t)0x00000000U)

normal-driver when use low power LDO

Definition at line 86 of file gd32f3x0_pmu.h.

#define PMU_NORMALDR_NORMALPWR ((uint32_t)0x00000000U)

normal-driver when use normal power LDO

Definition at line 82 of file gd32f3x0_pmu.h.

#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0

WKUP Pin 0 (PA0) enable

Definition at line 108 of file gd32f3x0_pmu.h.

#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1

WKUP Pin 1 (PC13) enable

Definition at line 109 of file gd32f3x0_pmu.h.

#define PMU_WAKEUP_PIN4 PMU_CS_WUPEN4

WKUP Pin 4 (PC5) enable

Definition at line 110 of file gd32f3x0_pmu.h.

#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5

WKUP Pin 5 (PB5) enable

Definition at line 111 of file gd32f3x0_pmu.h.

#define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6

WKUP Pin 6 (PB15) enable

Definition at line 112 of file gd32f3x0_pmu.h.

#define WFE_CMD ((uint8_t)0x01U)

use WFE command

Definition at line 120 of file gd32f3x0_pmu.h.

#define WFI_CMD ((uint8_t)0x00U)

use WFI command

Definition at line 119 of file gd32f3x0_pmu.h.

Function Documentation

void pmu_backup_write_disable ( void )

disable backup domain write

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 317 of file gd32f3x0_pmu.c.

318 {
319 PMU_CTL &= ~PMU_CTL_BKPWEN;
320 }
PMU_CTL_BKPWEN
#define PMU_CTL_BKPWEN
Definition: gd32f3x0_pmu.h:32
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_backup_write_enable ( void )

enable backup domain write

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 306 of file gd32f3x0_pmu.c.

307 {
308 PMU_CTL |= PMU_CTL_BKPWEN;
309 }
PMU_CTL_BKPWEN
#define PMU_CTL_BKPWEN
Definition: gd32f3x0_pmu.h:32
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_deinit ( void )

reset PMU register

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 21 of file gd32f3x0_pmu.c.

22 {
23 /* reset PMU */
24 rcu_periph_reset_enable(RCU_PMURST);
25 rcu_periph_reset_disable(RCU_PMURST);
26 }
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
RCU_PMURST
Definition: gd32f3x0_rcu.h:353
void pmu_flag_clear ( uint32_t flag_clear )

clear flag bit

Parameters
[in] flag_clear one or more parameters can be selected below
  • PMU_FLAG_RESET_WAKEUP: reset wakeup flag
  • PMU_FLAG_RESET_STANDBY: reset standby flag
[out] none
Return values
none

Definition at line 331 of file gd32f3x0_pmu.c.

332 {
333 if(RESET != (flag_clear & PMU_FLAG_RESET_WAKEUP)){
334 /* reset wakeup flag */
335 PMU_CTL |= PMU_CTL_WURST;
336 }
337 if(RESET != (flag_clear & PMU_FLAG_RESET_STANDBY)){
338 /* reset standby flag */
339 PMU_CTL |= PMU_CTL_STBRST;
340 }
341 }
PMU_FLAG_RESET_STANDBY
#define PMU_FLAG_RESET_STANDBY
Definition: gd32f3x0_pmu.h:116
PMU_FLAG_RESET_WAKEUP
#define PMU_FLAG_RESET_WAKEUP
Definition: gd32f3x0_pmu.h:115
PMU_CTL_WURST
#define PMU_CTL_WURST
Definition: gd32f3x0_pmu.h:28
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_CTL_STBRST
#define PMU_CTL_STBRST
Definition: gd32f3x0_pmu.h:29
FlagStatus pmu_flag_get ( uint32_t flag )

get flag state

Parameters
[in] flag only one among these parameters can be selected
  • PMU_FLAG_WAKEUP: wakeup flag
  • PMU_FLAG_STANDBY: standby flag
  • PMU_FLAG_LVD: lvd flag
  • PMU_FLAG_LDOVSR: LDO voltage select ready flag
  • PMU_FLAG_HDR: high-driver ready flag
  • PMU_FLAG_HDSR: high-driver switch ready flag
  • PMU_FLAG_LDR: low-driver mode ready flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 357 of file gd32f3x0_pmu.c.

358 {
359 FlagStatus ret_status = RESET;
360
361 if(PMU_CS & flag){
362 ret_status = SET;
363 }
364
365 return ret_status;
366 }
PMU_CS
#define PMU_CS
Definition: gd32f3x0_pmu.h:22
void pmu_highdriver_mode_disable ( void )

disable high-driver mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 126 of file gd32f3x0_pmu.c.

127 {
128 PMU_CTL &= ~PMU_CTL_HDEN;
129 }
PMU_CTL_HDEN
#define PMU_CTL_HDEN
Definition: gd32f3x0_pmu.h:36
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_highdriver_mode_enable ( void )

enable high-driver mode this bit set by software only when IRC8M or HXTAL used as system clock

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 115 of file gd32f3x0_pmu.c.

116 {
117 PMU_CTL |= PMU_CTL_HDEN;
118 }
PMU_CTL_HDEN
#define PMU_CTL_HDEN
Definition: gd32f3x0_pmu.h:36
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_highdriver_switch_select ( uint32_t highdr_switch )

switch high-driver mode this bit set by software only when IRC8M or HXTAL used as system clock

Parameters
[in] highdr_switch only one among these parameters can be selected
  • PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch
  • PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch
[out] none
Return values
none

Definition at line 141 of file gd32f3x0_pmu.c.

142 {
143 /* wait for HDRF flag to be set */
144 while(SET != pmu_flag_get(PMU_FLAG_HDR)){
145 }
146 PMU_CTL &= ~PMU_CTL_HDS;
147 PMU_CTL |= highdr_switch;
148 }
pmu_flag_get
FlagStatus pmu_flag_get(uint32_t flag)
get flag state
Definition: gd32f3x0_pmu.c:357
PMU_CTL_HDS
#define PMU_CTL_HDS
Definition: gd32f3x0_pmu.h:37
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_FLAG_HDR
#define PMU_FLAG_HDR
Definition: gd32f3x0_pmu.h:103
void pmu_ldo_output_select ( uint32_t ldo_output )

select LDO output voltage these bits set by software when the main PLL closed

Parameters
[in] ldo_output only one among these parameters can be selected
  • PMU_LDOVS_LOW: LDO output voltage low mode
  • PMU_LDOVS_MID: LDO output voltage mid mode
  • PMU_LDOVS_HIGH: LDO output voltage high mode
[out] none
Return values
none

Definition at line 66 of file gd32f3x0_pmu.c.

67 {
68 PMU_CTL &= ~PMU_CTL_LDOVS;
69 PMU_CTL |= ldo_output;
70 }
PMU_CTL_LDOVS
#define PMU_CTL_LDOVS
Definition: gd32f3x0_pmu.h:35
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_lowdriver_mode_disable ( void )

enable low-driver mode in deep-sleep mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 102 of file gd32f3x0_pmu.c.

103 {
104 PMU_CTL &= ~PMU_CTL_LDEN;
105 PMU_CTL |= PMU_LOWDRIVER_DISABLE;
106 }
PMU_LOWDRIVER_DISABLE
#define PMU_LOWDRIVER_DISABLE
Definition: gd32f3x0_pmu.h:74
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_CTL_LDEN
#define PMU_CTL_LDEN
Definition: gd32f3x0_pmu.h:38
void pmu_lowdriver_mode_enable ( void )

enable low-driver mode in deep-sleep mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 90 of file gd32f3x0_pmu.c.

91 {
92 PMU_CTL &= ~PMU_CTL_LDEN;
93 PMU_CTL |= PMU_LOWDRIVER_ENABLE;
94 }
PMU_LOWDRIVER_ENABLE
#define PMU_LOWDRIVER_ENABLE
Definition: gd32f3x0_pmu.h:75
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_CTL_LDEN
#define PMU_CTL_LDEN
Definition: gd32f3x0_pmu.h:38
void pmu_lowpower_driver_config ( uint32_t mode )

low-driver mode when use low power LDO

Parameters
[in] mode only one among these parameters can be selected
  • PMU_NORMALDR_LOWPWR: normal-driver when use low power LDO
  • PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO
[out] none
Return values
none

Definition at line 159 of file gd32f3x0_pmu.c.

160 {
161 PMU_CTL &= ~PMU_CTL_LDLP;
162 PMU_CTL |= mode;
163 }
PMU_CTL_LDLP
#define PMU_CTL_LDLP
Definition: gd32f3x0_pmu.h:33
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_lvd_disable ( void )

disable PMU lvd

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 78 of file gd32f3x0_pmu.c.

79 {
80 /* disable LVD */
81 PMU_CTL &= ~PMU_CTL_LVDEN;
82 }
PMU_CTL_LVDEN
#define PMU_CTL_LVDEN
Definition: gd32f3x0_pmu.h:30
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_lvd_select ( uint32_t lvdt_n )

select low voltage detector threshold

Parameters
[in] lvdt_n only one among these parameters can be selected
  • PMU_LVDT_0: voltage threshold is 2.1V
  • PMU_LVDT_1: voltage threshold is 2.3V
  • PMU_LVDT_2: voltage threshold is 2.4V
  • PMU_LVDT_3: voltage threshold is 2.6V
  • PMU_LVDT_4: voltage threshold is 2.7V
  • PMU_LVDT_5: voltage threshold is 2.9V
  • PMU_LVDT_6: voltage threshold is 3.0V
  • PMU_LVDT_7: voltage threshold is 3.1V
[out] none
Return values
none

Definition at line 43 of file gd32f3x0_pmu.c.

44 {
45 /* disable LVD */
46 PMU_CTL &= ~PMU_CTL_LVDEN;
47 /* clear LVDT bits */
48 PMU_CTL &= ~PMU_CTL_LVDT;
49 /* set LVDT bits according to lvdt_n */
50 PMU_CTL |= lvdt_n;
51 /* enable LVD */
52 PMU_CTL |= PMU_CTL_LVDEN;
53 }
PMU_CTL_LVDT
#define PMU_CTL_LVDT
Definition: gd32f3x0_pmu.h:31
PMU_CTL_LVDEN
#define PMU_CTL_LVDEN
Definition: gd32f3x0_pmu.h:30
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_normalpower_driver_config ( uint32_t mode )

low-driver mode when use normal power LDO

Parameters
[in] mode only one among these parameters can be selected
  • PMU_NORMALDR_NORMALPWR: normal-driver when use low power LDO
  • PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use low power LDO
[out] none
Return values
none

Definition at line 174 of file gd32f3x0_pmu.c.

175 {
176 PMU_CTL &= ~PMU_CTL_LDNP;
177 PMU_CTL |= mode;
178 }
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_CTL_LDNP
#define PMU_CTL_LDNP
Definition: gd32f3x0_pmu.h:34
void pmu_to_deepsleepmode | ( | uint32_t | ldo,
 |  | uint8_t | deepsleepmodecmd
 | ) |  |

PMU work at deepsleep mode.

Parameters
[in] ldo only one among these parameters can be selected
  • PMU_LDO_NORMAL: LDO operates normally when pmu enter deepsleep mode
  • PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
[in] deepsleepmodecmd only one among these parameters can be selected
  • WFI_CMD: use WFI command
  • WFE_CMD: use WFE command
[out] none
Return values
none

Definition at line 215 of file gd32f3x0_pmu.c.

216 {
217 /* clear stbmod and ldolp bits */
218 PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
219
220 /* set ldolp bit according to pmu_ldo */
221 PMU_CTL |= ldo;
222
223 /* set sleepdeep bit of Cortex-M4 system control register */
224 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
225
226 /* select WFI or WFE command to enter deepsleep mode */
227 if(WFI_CMD == deepsleepmodecmd){
228 __WFI();
229 }else{
230 __SEV();
231 __WFE();
232 __WFE();
233 }
234 /* reset sleepdeep bit of Cortex-M4 system control register */
235 SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
236 }
WFI_CMD
#define WFI_CMD
Definition: gd32f3x0_pmu.h:119
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_CTL_STBMOD
#define PMU_CTL_STBMOD
Definition: gd32f3x0_pmu.h:27
PMU_CTL_LDOLP
#define PMU_CTL_LDOLP
Definition: gd32f3x0_pmu.h:26
void pmu_to_sleepmode ( uint8_t sleepmodecmd )

PMU work at sleep mode.

Parameters
[in] sleepmodecmd only one among these parameters can be selected
  • WFI_CMD: use WFI command
  • WFE_CMD: use WFE command
[out] none
Return values
none

Definition at line 189 of file gd32f3x0_pmu.c.

190 {
191 /* clear sleepdeep bit of Cortex-M4 system control register */
192 SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
193
194 /* select WFI or WFE command to enter sleep mode */
195 if(WFI_CMD == sleepmodecmd){
196 __WFI();
197 }else{
198 __WFE();
199 }
200 }
WFI_CMD
#define WFI_CMD
Definition: gd32f3x0_pmu.h:119
void pmu_to_standbymode ( uint8_t standbymodecmd )

pmu work at standby mode

Parameters
[in] standbymodecmd only one among these parameters can be selected
  • WFI_CMD: use WFI command
  • WFE_CMD: use WFE command
[out] none
Return values
none

Definition at line 247 of file gd32f3x0_pmu.c.

248 {
249 /* set sleepdeep bit of Cortex-M4 system control register */
250 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
251
252 /* set stbmod bit */
253 PMU_CTL |= PMU_CTL_STBMOD;
254
255 /* reset wakeup flag */
256 PMU_CTL |= PMU_CTL_WURST;
257
258 /* select WFI or WFE command to enter standby mode */
259 if(WFI_CMD == standbymodecmd){
260 __WFI();
261 }else{
262 __WFE();
263 }
264 }
PMU_CTL_WURST
#define PMU_CTL_WURST
Definition: gd32f3x0_pmu.h:28
WFI_CMD
#define WFI_CMD
Definition: gd32f3x0_pmu.h:119
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_CTL_STBMOD
#define PMU_CTL_STBMOD
Definition: gd32f3x0_pmu.h:27
void pmu_wakeup_pin_disable ( uint32_t wakeup_pin )

disable wakeup pin

Parameters
[in] wakeup_pin one or more parameters can be selected below
  • PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
  • PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
  • PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5)
  • PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
  • PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
[out] none
Return values
none

Definition at line 295 of file gd32f3x0_pmu.c.

296 {
297 PMU_CS &= ~(wakeup_pin);
298 }
PMU_CS
#define PMU_CS
Definition: gd32f3x0_pmu.h:22
void pmu_wakeup_pin_enable ( uint32_t wakeup_pin )

enable wakeup pin

Parameters
[in] wakeup_pin one or more parameters can be selected below
  • PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
  • PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
  • PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5)
  • PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
  • PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
[out] none
Return values
none

Definition at line 278 of file gd32f3x0_pmu.c.

279 {
280 PMU_CS |= wakeup_pin;
281 }
PMU_CS
#define PMU_CS
Definition: gd32f3x0_pmu.h:22
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_rcu.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Enumerations | Functions
gd32f3x0_rcu.h File Reference

definitions for the RCU More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | RCU RCU_BASE
#define | RCU_CTL0 REG32(RCU + 0x00U)
#define | RCU_CFG0 REG32(RCU + 0x04U)
#define | RCU_INT REG32(RCU + 0x08U)
#define | RCU_APB2RST REG32(RCU + 0x0CU)
#define | RCU_APB1RST REG32(RCU + 0x10U)
#define | RCU_AHBEN REG32(RCU + 0x14U)
#define | RCU_APB2EN REG32(RCU + 0x18U)
#define | RCU_APB1EN REG32(RCU + 0x1CU)
#define | RCU_BDCTL REG32(RCU + 0x20U)
#define | RCU_RSTSCK REG32(RCU + 0x24U)
#define | RCU_AHBRST REG32(RCU + 0x28U)
#define | RCU_CFG1 REG32(RCU + 0x2CU)
#define | RCU_CFG2 REG32(RCU + 0x30U)
#define | RCU_CTL1 REG32(RCU + 0x34U)
#define | RCU_ADDCTL REG32(RCU + 0xC0U)
#define | RCU_ADDINT REG32(RCU + 0xCCU)
#define | RCU_ADDAPB1EN REG32(RCU + 0xF8U)
#define | RCU_ADDAPB1RST REG32(RCU + 0xFCU)
#define | RCU_VKEY REG32(RCU + 0x100U)
#define | RCU_DSV REG32(RCU + 0x134U)
#define | RCU_CTL0_IRC8MEN BIT(0)
#define | RCU_CTL0_IRC8MSTB BIT(1)
#define | RCU_CTL0_IRC8MADJ BITS(3,7)
#define | RCU_CTL0_IRC8MCALIB BITS(8,15)
#define | RCU_CTL0_HXTALEN BIT(16)
#define | RCU_CTL0_HXTALSTB BIT(17)
#define | RCU_CTL0_HXTALBPS BIT(18)
#define | RCU_CTL0_CKMEN BIT(19)
#define | RCU_CTL0_PLLEN BIT(24)
#define | RCU_CTL0_PLLSTB BIT(25)
#define | RCU_CFG0_SCS BITS(0,1)
#define | RCU_CFG0_SCSS BITS(2,3)
#define | RCU_CFG0_AHBPSC BITS(4,7)
#define | RCU_CFG0_APB1PSC BITS(8,10)
#define | RCU_CFG0_APB2PSC BITS(11,13)
#define | RCU_CFG0_ADCPSC BITS(14,15)
#define | RCU_CFG0_PLLSEL BIT(16)
#define | RCU_CFG0_PLLPREDV BIT(17)
#define | RCU_CFG0_PLLMF (BIT(27) | BITS(18,21))
#define | RCU_CFG0_USBFSPSC BITS(22,23)
#define | RCU_CFG0_CKOUTSEL BITS(24,26)
#define | RCU_CFG0_PLLMF4 BIT(27)
#define | RCU_CFG0_CKOUTDIV BITS(28,30)
#define | RCU_CFG0_PLLDV BIT(31)
#define | RCU_INT_IRC40KSTBIF BIT(0)
#define | RCU_INT_LXTALSTBIF BIT(1)
#define | RCU_INT_IRC8MSTBIF BIT(2)
#define | RCU_INT_HXTALSTBIF BIT(3)
#define | RCU_INT_PLLSTBIF BIT(4)
#define | RCU_INT_IRC28MSTBIF BIT(5)
#define | RCU_INT_CKMIF BIT(7)
#define | RCU_INT_IRC40KSTBIE BIT(8)
#define | RCU_INT_LXTALSTBIE BIT(9)
#define | RCU_INT_IRC8MSTBIE BIT(10)
#define | RCU_INT_HXTALSTBIE BIT(11)
#define | RCU_INT_PLLSTBIE BIT(12)
#define | RCU_INT_IRC28MSTBIE BIT(13)
#define | RCU_INT_IRC40KSTBIC BIT(16)
#define | RCU_INT_LXTALSTBIC BIT(17)
#define | RCU_INT_IRC8MSTBIC BIT(18)
#define | RCU_INT_HXTALSTBIC BIT(19)
#define | RCU_INT_PLLSTBIC BIT(20)
#define | RCU_INT_IRC28MSTBIC BIT(21)
#define | RCU_INT_CKMIC BIT(23)
#define | RCU_APB2RST_CFGRST BIT(0)
#define | RCU_APB2RST_ADCRST BIT(9)
#define | RCU_APB2RST_TIMER0RST BIT(11)
#define | RCU_APB2RST_SPI0RST BIT(12)
#define | RCU_APB2RST_USART0RST BIT(14)
#define | RCU_APB2RST_TIMER14RST BIT(16)
#define | RCU_APB2RST_TIMER15RST BIT(17)
#define | RCU_APB2RST_TIMER16RST BIT(18)
#define | RCU_APB1RST_TIMER1RST BIT(0)
#define | RCU_APB1RST_TIMER2RST BIT(1)
#define | RCU_APB1RST_TIMER5RST BIT(4)
#define | RCU_APB1RST_TIMER13RST BIT(8)
#define | RCU_APB1RST_WWDGTRST BIT(11)
#define | RCU_APB1RST_SPI1RST BIT(14)
#define | RCU_APB1RST_SPI2RST BIT(15)
#define | RCU_APB1RST_USART1RST BIT(17)
#define | RCU_APB1RST_I2C0RST BIT(21)
#define | RCU_APB1RST_I2C1RST BIT(22)
#define | RCU_APB1RST_PMURST BIT(28)
#define | RCU_APB1RST_DACRST BIT(29)
#define | RCU_APB1RST_CECRST BIT(30)
#define | RCU_AHBEN_DMAEN BIT(0)
#define | RCU_AHBEN_SRAMSPEN BIT(2)
#define | RCU_AHBEN_FMCSPEN BIT(4)
#define | RCU_AHBEN_CRCEN BIT(6)
#define | RCU_AHBEN_USBFS BIT(12)
#define | RCU_AHBEN_PAEN BIT(17)
#define | RCU_AHBEN_PBEN BIT(18)
#define | RCU_AHBEN_PCEN BIT(19)
#define | RCU_AHBEN_PDEN BIT(20)
#define | RCU_AHBEN_PFEN BIT(22)
#define | RCU_AHBEN_TSIEN BIT(24)
#define | RCU_APB2EN_CFGCMPEN BIT(0)
#define | RCU_APB2EN_ADCEN BIT(9)
#define | RCU_APB2EN_TIMER0EN BIT(11)
#define | RCU_APB2EN_SPI0EN BIT(12)
#define | RCU_APB2EN_USART0EN BIT(14)
#define | RCU_APB2EN_TIMER14EN BIT(16)
#define | RCU_APB2EN_TIMER15EN BIT(17)
#define | RCU_APB2EN_TIMER16EN BIT(18)
#define | RCU_APB1EN_TIMER1EN BIT(0)
#define | RCU_APB1EN_TIMER2EN BIT(1)
#define | RCU_APB1EN_TIMER5EN BIT(4)
#define | RCU_APB1EN_TIMER13EN BIT(8)
#define | RCU_APB1EN_WWDGTEN BIT(11)
#define | RCU_APB1EN_SPI1EN BIT(14)
#define | RCU_APB1EN_SPI2EN BIT(15)
#define | RCU_APB1EN_USART1EN BIT(17)
#define | RCU_APB1EN_I2C0EN BIT(21)
#define | RCU_APB1EN_I2C1EN BIT(22)
#define | RCU_APB1EN_PMUEN BIT(28)
#define | RCU_APB1EN_DACEN BIT(29)
#define | RCU_APB1EN_CECEN BIT(30)
#define | RCU_BDCTL_LXTALEN BIT(0)
#define | RCU_BDCTL_LXTALSTB BIT(1)
#define | RCU_BDCTL_LXTALBPS BIT(2)
#define | RCU_BDCTL_LXTALDRI BITS(3,4)
#define | RCU_BDCTL_RTCSRC BITS(8,9)
#define | RCU_BDCTL_RTCEN BIT(15)
#define | RCU_BDCTL_BKPRST BIT(16)
#define | RCU_RSTSCK_IRC40KEN BIT(0)
#define | RCU_RSTSCK_IRC40KSTB BIT(1)
#define | RCU_RSTSCK_V12RSTF BIT(23)
#define | RCU_RSTSCK_RSTFC BIT(24)
#define | RCU_RSTSCK_OBLRSTF BIT(25)
#define | RCU_RSTSCK_EPRSTF BIT(26)
#define | RCU_RSTSCK_PORRSTF BIT(27)
#define | RCU_RSTSCK_SWRSTF BIT(28)
#define | RCU_RSTSCK_FWDGTRSTF BIT(29)
#define | RCU_RSTSCK_WWDGTRSTF BIT(30)
#define | RCU_RSTSCK_LPRSTF BIT(31)
#define | RCU_AHBRST_USBFSRST BIT(12)
#define | RCU_AHBRST_PARST BIT(17)
#define | RCU_AHBRST_PBRST BIT(18)
#define | RCU_AHBRST_PCRST BIT(19)
#define | RCU_AHBRST_PDRST BIT(20)
#define | RCU_AHBRST_PFRST BIT(22)
#define | RCU_AHBRST_TSIRST BIT(24)
#define | RCU_CFG1_PREDV BITS(0,3)
#define | RCU_CFG1_PLLPRESEL BIT(30)
#define | RCU_CFG1_PLLMF5 BIT(31)
#define | RCU_CFG2_USART0SEL BITS(0,1)
#define | RCU_CFG2_CECSEL BIT(6)
#define | RCU_CFG2_ADCSEL BIT(8)
#define | RCU_CFG2_IRC28MDIV BIT(16)
#define | RCU_CFG2_USBFSPSC2 BIT(30)
#define | RCU_CFG2_ADCPSC2 BIT(31)
#define | RCU_CTL1_IRC28MEN BIT(0)
#define | RCU_CTL1_IRC28MSTB BIT(1)
#define | RCU_CTL1_IRC28MADJ BITS(3,7)
#define | RCU_CTL1_IRC28MCALIB BITS(8,15)
#define | RCU_ADDCTL_CK48MSEL BIT(0)
#define | RCU_ADDCTL_IRC48MEN BIT(16)
#define | RCU_ADDCTL_IRC48MSTB BIT(17)
#define | RCU_ADDCTL_IRC48MCALIB BITS(24,31)
#define | RCU_ADDINT_IRC48MSTBIF BIT(6)
#define | RCU_ADDINT_IRC48MSTBIE BIT(14)
#define | RCU_ADDINT_IRC48MSTBIC BIT(22)
#define | RCU_ADDAPB1EN_I2C2EN BIT(0)
#define | RCU_ADDAPB1EN_CTCEN BIT(27)
#define | RCU_ADDAPB1RST_I2C2RST BIT(0)
#define | RCU_ADDAPB1RST_CTCRST BIT(27)
#define | RCU_VKEY_KEY BITS(0,31)
#define | RCU_DSV_DSLPVS BITS(0,1)
#define | RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx)<<6) | (uint32_t)(bitpos))
#define | RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph)>>6)))
#define | RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
#define | RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4D)
#define | CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define | RCU_CKSYSSRC_IRC8M CFG0_SCS(0)
#define | RCU_CKSYSSRC_HXTAL CFG0_SCS(1)
#define | RCU_CKSYSSRC_PLL CFG0_SCS(2)
#define | CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
#define | RCU_SCSS_IRC8M CFG0_SCSS(0)
#define | RCU_SCSS_HXTAL CFG0_SCSS(1)
#define | RCU_SCSS_PLL CFG0_SCSS(2)
#define | CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
#define | RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0)
#define | RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8)
#define | RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9)
#define | RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10)
#define | RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11)
#define | RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12)
#define | RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13)
#define | RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14)
#define | RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15)
#define | CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
#define | RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0)
#define | RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4)
#define | RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5)
#define | RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6)
#define | RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7)
#define | CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11))
#define | RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0)
#define | RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4)
#define | RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5)
#define | RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6)
#define | RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7)
#define | CFG0_ADCPSC(regval) (BITS(14,15) & ((uint32_t)(regval) << 14))
#define | RCU_ADC_CKAPB2_DIV2 CFG0_ADCPSC(0)
#define | RCU_ADC_CKAPB2_DIV4 CFG0_ADCPSC(1)
#define | RCU_ADC_CKAPB2_DIV6 CFG0_ADCPSC(2)
#define | RCU_ADC_CKAPB2_DIV8 CFG0_ADCPSC(3)
#define | RCU_PLLSRC_IRC8M_DIV2 (uint32_t)0x00000000U
#define | RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL
#define | RCU_PLLPRESEL_HXTAL (uint32_t)0x00000000U
#define | RCU_PLLPRESEL_IRC48M RCU_CFG1_PLLPRESEL
#define | RCU_PLLPREDV (uint32_t)0x00000000U
#define | RCU_PLLPREDV_DIV2 RCU_CFG0_PLLPREDV
#define | CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18))
#define | RCU_PLL_MUL2 CFG0_PLLMF(0)
#define | RCU_PLL_MUL3 CFG0_PLLMF(1)
#define | RCU_PLL_MUL4 CFG0_PLLMF(2)
#define | RCU_PLL_MUL5 CFG0_PLLMF(3)
#define | RCU_PLL_MUL6 CFG0_PLLMF(4)
#define | RCU_PLL_MUL7 CFG0_PLLMF(5)
#define | RCU_PLL_MUL8 CFG0_PLLMF(6)
#define | RCU_PLL_MUL9 CFG0_PLLMF(7)
#define | RCU_PLL_MUL10 CFG0_PLLMF(8)
#define | RCU_PLL_MUL11 CFG0_PLLMF(9)
#define | RCU_PLL_MUL12 CFG0_PLLMF(10)
#define | RCU_PLL_MUL13 CFG0_PLLMF(11)
#define | RCU_PLL_MUL14 CFG0_PLLMF(12)
#define | RCU_PLL_MUL15 CFG0_PLLMF(13)
#define | RCU_PLL_MUL16 CFG0_PLLMF(14)
#define | RCU_PLL_MUL17 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0))
#define | RCU_PLL_MUL18 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1))
#define | RCU_PLL_MUL19 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2))
#define | RCU_PLL_MUL20 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3))
#define | RCU_PLL_MUL21 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4))
#define | RCU_PLL_MUL22 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5))
#define | RCU_PLL_MUL23 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6))
#define | RCU_PLL_MUL24 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7))
#define | RCU_PLL_MUL25 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8))
#define | RCU_PLL_MUL26 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9))
#define | RCU_PLL_MUL27 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10))
#define | RCU_PLL_MUL28 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11))
#define | RCU_PLL_MUL29 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12))
#define | RCU_PLL_MUL30 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13))
#define | RCU_PLL_MUL31 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14))
#define | RCU_PLL_MUL32 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15))
#define | RCU_PLL_MUL33 (CFG0_PLLMF(0) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL34 (CFG0_PLLMF(1) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL35 (CFG0_PLLMF(2) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL36 (CFG0_PLLMF(3) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL37 (CFG0_PLLMF(4) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL38 (CFG0_PLLMF(5) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL39 (CFG0_PLLMF(6) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL40 (CFG0_PLLMF(7) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL41 (CFG0_PLLMF(8) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL42 (CFG0_PLLMF(9) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL43 (CFG0_PLLMF(10) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL44 (CFG0_PLLMF(11) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL45 (CFG0_PLLMF(12) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL46 (CFG0_PLLMF(13) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL47 (CFG0_PLLMF(14) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL48 (CFG0_PLLMF(15) | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL49 (RCU_CFG0_PLLMF4 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL50 (RCU_PLL_MUL18 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL51 (RCU_PLL_MUL19 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL52 (RCU_PLL_MUL20 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL53 (RCU_PLL_MUL21 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL54 (RCU_PLL_MUL22 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL55 (RCU_PLL_MUL23 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL56 (RCU_PLL_MUL24 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL57 (RCU_PLL_MUL25 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL58 (RCU_PLL_MUL26 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL59 (RCU_PLL_MUL27 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL60 (RCU_PLL_MUL28 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL61 (RCU_PLL_MUL29 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL62 (RCU_PLL_MUL30 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL63 (RCU_PLL_MUL31 | RCU_CFG1_PLLMF5)
#define | RCU_PLL_MUL64 (RCU_PLL_MUL32 | RCU_CFG1_PLLMF5)
#define | CFG0_USBFSPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22))
#define | RCU_USBFS_CKPLL_DIV1_5 CFG0_USBFSPSC(0)
#define | RCU_USBFS_CKPLL_DIV1 CFG0_USBFSPSC(1)
#define | RCU_USBFS_CKPLL_DIV2_5 CFG0_USBFSPSC(2)
#define | RCU_USBFS_CKPLL_DIV2 CFG0_USBFSPSC(3)
#define | RCU_USBFS_CKPLL_DIV3 RCU_CFG2_USBFSPSC2
#define | RCU_USBFS_CKPLL_DIV3_5 (CFG0_USBFSPSC(1)|RCU_CFG2_USBFSPSC2)
#define | CFG0_CKOUTSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
#define | RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0)
#define | RCU_CKOUTSRC_IRC28M CFG0_CKOUTSEL(1)
#define | RCU_CKOUTSRC_IRC40K CFG0_CKOUTSEL(2)
#define | RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3)
#define | RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4)
#define | RCU_CKOUTSRC_IRC8M CFG0_CKOUTSEL(5)
#define | RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6)
#define | RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7))
#define | RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7)
#define | CFG0_CKOUTDIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28))
#define | RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0)
#define | RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1)
#define | RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2)
#define | RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3)
#define | RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4)
#define | RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5)
#define | RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6)
#define | RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7)
#define | RCU_PLLDV_CKPLL_DIV2 (uint32_t)0x00000000U
#define | RCU_PLLDV_CKPLL RCU_CFG0_PLLDV
#define | BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3))
#define | RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0)
#define | RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1)
#define | RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2)
#define | RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3)
#define | BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
#define | RCU_RTCSRC_NONE BDCTL_RTCSRC(0)
#define | RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1)
#define | RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2)
#define | RCU_RTCSRC_HXTAL_DIV32 BDCTL_RTCSRC(3)
#define | CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
#define | RCU_PLL_PREDV1 CFG1_PREDV(0)
#define | RCU_PLL_PREDV2 CFG1_PREDV(1)
#define | RCU_PLL_PREDV3 CFG1_PREDV(2)
#define | RCU_PLL_PREDV4 CFG1_PREDV(3)
#define | RCU_PLL_PREDV5 CFG1_PREDV(4)
#define | RCU_PLL_PREDV6 CFG1_PREDV(5)
#define | RCU_PLL_PREDV7 CFG1_PREDV(6)
#define | RCU_PLL_PREDV8 CFG1_PREDV(7)
#define | RCU_PLL_PREDV9 CFG1_PREDV(8)
#define | RCU_PLL_PREDV10 CFG1_PREDV(9)
#define | RCU_PLL_PREDV11 CFG1_PREDV(10)
#define | RCU_PLL_PREDV12 CFG1_PREDV(11)
#define | RCU_PLL_PREDV13 CFG1_PREDV(12)
#define | RCU_PLL_PREDV14 CFG1_PREDV(13)
#define | RCU_PLL_PREDV15 CFG1_PREDV(14)
#define | RCU_PLL_PREDV16 CFG1_PREDV(15)
#define | CFG2_USART0SEL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define | RCU_USART0SRC_CKAPB2 CFG2_USART0SEL(0)
#define | RCU_USART0SRC_CKSYS CFG2_USART0SEL(1)
#define | RCU_USART0SRC_LXTAL CFG2_USART0SEL(2)
#define | RCU_USART0SRC_IRC8M CFG2_USART0SEL(3)
#define | RCU_CECSRC_IRC8M_DIV244 (uint32_t)0x00000000U
#define | RCU_CECSRC_LXTAL RCU_CFG2_CECSEL
#define | RCU_ADCSRC_IRC28M (uint32_t)0x00000000U
#define | RCU_ADCSRC_APB2DIV RCU_CFG2_ADCSEL
#define | RCU_ADC_IRC28M_DIV2 (uint32_t)0x00000000U
#define | RCU_ADC_IRC28M_DIV1 RCU_CFG2_IRC28MDIV
#define | DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define | RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0)
#define | RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1)
#define | RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2)
#define | RCU_DEEPSLEEP_V_0_7 DSV_DSLPVS(3)

Enumerations

enum reg_idx {
IDX_AHBEN = 0x14U, IDX_APB2EN = 0x18U, IDX_APB1EN = 0x1CU, IDX_ADDAPB1EN = 0xF8U,
IDX_AHBRST = 0x28U, IDX_APB2RST = 0x0CU, IDX_APB1RST = 0x10U, IDX_ADDAPB1RST = 0xFCU,
IDX_CTL0 = 0x00U, IDX_BDCTL = 0x20U, IDX_CTL1 = 0x34U, IDX_ADDCTL = 0xC0U,
IDX_RSTSCK = 0x24U, IDX_INT = 0x08U, IDX_ADDINT = 0xCCU, IDX_CFG0 = 0x04U,
IDX_CFG2 = 0x30U
}
enum rcu_periph_enum {
RCU_DMA = RCU_REGIDX_BIT(IDX_AHBEN, 0U), RCU_CRC = RCU_REGIDX_BIT(IDX_AHBEN, 6U), RCU_GPIOA = RCU_REGIDX_BIT(IDX_AHBEN, 17U), RCU_GPIOB = RCU_REGIDX_BIT(IDX_AHBEN, 18U),
RCU_GPIOC = RCU_REGIDX_BIT(IDX_AHBEN, 19U), RCU_GPIOD = RCU_REGIDX_BIT(IDX_AHBEN, 20U), RCU_GPIOF = RCU_REGIDX_BIT(IDX_AHBEN, 22U), RCU_TSI = RCU_REGIDX_BIT(IDX_AHBEN, 24U),
RCU_CFGCMP = RCU_REGIDX_BIT(IDX_APB2EN, 0U), RCU_ADC = RCU_REGIDX_BIT(IDX_APB2EN, 9U), RCU_TIMER0 = RCU_REGIDX_BIT(IDX_APB2EN, 11U), RCU_SPI0 = RCU_REGIDX_BIT(IDX_APB2EN, 12U),
RCU_USART0 = RCU_REGIDX_BIT(IDX_APB2EN, 14U), RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U), RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U), RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U),
RCU_TIMER1 = RCU_REGIDX_BIT(IDX_APB1EN, 0U), RCU_TIMER2 = RCU_REGIDX_BIT(IDX_APB1EN, 1U), RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U), RCU_WWDGT = RCU_REGIDX_BIT(IDX_APB1EN, 11U),
RCU_SPI1 = RCU_REGIDX_BIT(IDX_APB1EN, 14U), RCU_SPI2 = RCU_REGIDX_BIT(IDX_APB1EN, 15U), RCU_USART1 = RCU_REGIDX_BIT(IDX_APB1EN, 17U), RCU_I2C0 = RCU_REGIDX_BIT(IDX_APB1EN, 21U),
RCU_I2C1 = RCU_REGIDX_BIT(IDX_APB1EN, 22U), RCU_PMU = RCU_REGIDX_BIT(IDX_APB1EN, 28U), RCU_RTC = RCU_REGIDX_BIT(IDX_BDCTL, 15U), RCU_I2C2 = RCU_REGIDX_BIT(IDX_ADDAPB1EN, 0U),
RCU_CTC = RCU_REGIDX_BIT(IDX_ADDAPB1EN, 27U)
}
enum rcu_periph_sleep_enum { RCU_SRAM_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 2U), RCU_FMC_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 4U) }
enum rcu_periph_reset_enum {
RCU_GPIOARST = RCU_REGIDX_BIT(IDX_AHBRST, 17U), RCU_GPIOBRST = RCU_REGIDX_BIT(IDX_AHBRST, 18U), RCU_GPIOCRST = RCU_REGIDX_BIT(IDX_AHBRST, 19U), RCU_GPIODRST = RCU_REGIDX_BIT(IDX_AHBRST, 20U),
RCU_GPIOFRST = RCU_REGIDX_BIT(IDX_AHBRST, 22U), RCU_TSIRST = RCU_REGIDX_BIT(IDX_AHBRST, 24U), RCU_CFGCMPRST = RCU_REGIDX_BIT(IDX_APB2RST, 0U), RCU_ADCRST = RCU_REGIDX_BIT(IDX_APB2RST, 9U),
RCU_TIMER0RST = RCU_REGIDX_BIT(IDX_APB2RST, 11U), RCU_SPI0RST = RCU_REGIDX_BIT(IDX_APB2RST, 12U), RCU_USART0RST = RCU_REGIDX_BIT(IDX_APB2RST, 14U), RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U),
RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U), RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U), RCU_TIMER1RST = RCU_REGIDX_BIT(IDX_APB1RST, 0U), RCU_TIMER2RST = RCU_REGIDX_BIT(IDX_APB1RST, 1U),
RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U), RCU_WWDGTRST = RCU_REGIDX_BIT(IDX_APB1RST, 11U), RCU_SPI1RST = RCU_REGIDX_BIT(IDX_APB1RST, 14U), RCU_SPI2RST = RCU_REGIDX_BIT(IDX_APB1RST, 15U),
RCU_USART1RST = RCU_REGIDX_BIT(IDX_APB1RST, 17U), RCU_I2C0RST = RCU_REGIDX_BIT(IDX_APB1RST, 21U), RCU_I2C1RST = RCU_REGIDX_BIT(IDX_APB1RST, 22U), RCU_PMURST = RCU_REGIDX_BIT(IDX_APB1RST, 28U),
RCU_I2C2RST = RCU_REGIDX_BIT(IDX_ADDAPB1RST, 0U), RCU_CTCRST = RCU_REGIDX_BIT(IDX_ADDAPB1RST, 27U)
}
enum rcu_flag_enum {
RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_RSTSCK, 1U), RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_BDCTL, 1U), RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_CTL0, 1U), RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_CTL0, 17U),
RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_CTL0, 25U), RCU_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_CTL1, 1U), RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDCTL, 17U), RCU_FLAG_V12RST = RCU_REGIDX_BIT(IDX_RSTSCK, 23U),
RCU_FLAG_OBLRST = RCU_REGIDX_BIT(IDX_RSTSCK, 25U), RCU_FLAG_EPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 26U), RCU_FLAG_PORRST = RCU_REGIDX_BIT(IDX_RSTSCK, 27U), RCU_FLAG_SWRST = RCU_REGIDX_BIT(IDX_RSTSCK, 28U),
RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 29U), RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 30U), RCU_FLAG_LPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 31U)
}
enum rcu_int_flag_enum {
RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 0U), RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 1U), RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 2U), RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 3U),
RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 4U), RCU_INT_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 5U), RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(IDX_INT, 7U), RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDCTL, 6U)
}
enum rcu_int_flag_clear_enum {
RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 16U), RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 17U), RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 18U), RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 19U),
RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 20U), RCU_INT_FLAG_IRC28MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 21U), RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(IDX_INT, 23U), RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(IDX_ADDCTL, 22U)
}
enum rcu_int_enum {
RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 8U), RCU_INT_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 9U), RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 10U), RCU_INT_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 11U),
RCU_INT_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 12U), RCU_INT_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 13U), RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDINT, 14U)
}
enum rcu_adc_clock_enum {
RCU_ADCCK_IRC28M_DIV2 = 0U, RCU_ADCCK_IRC28M, RCU_ADCCK_APB2_DIV2, RCU_ADCCK_APB2_DIV3,
RCU_ADCCK_APB2_DIV4, RCU_ADCCK_APB2_DIV5, RCU_ADCCK_APB2_DIV6, RCU_ADCCK_APB2_DIV7,
RCU_ADCCK_APB2_DIV8, RCU_ADCCK_APB2_DIV9
}
enum rcu_osci_type_enum {
RCU_HXTAL = RCU_REGIDX_BIT(IDX_CTL0, 16U), RCU_LXTAL = RCU_REGIDX_BIT(IDX_BDCTL, 0U), RCU_IRC8M = RCU_REGIDX_BIT(IDX_CTL0, 0U), RCU_IRC28M = RCU_REGIDX_BIT(IDX_CTL1, 0U),
RCU_IRC48M = RCU_REGIDX_BIT(IDX_ADDCTL, 16U), RCU_IRC40K = RCU_REGIDX_BIT(IDX_RSTSCK, 0U), RCU_PLL_CK = RCU_REGIDX_BIT(IDX_CTL0, 24U)
}
enum rcu_clock_freq_enum {
CK_SYS = 0U, CK_AHB, CK_APB1, CK_APB2,
CK_ADC, CK_CEC, CK_USART
}

Functions

void | rcu_deinit (void)
deinitialize the RCU More...
void | rcu_periph_clock_enable (rcu_periph_enum periph)
enable the peripherals clock More...
void | rcu_periph_clock_disable (rcu_periph_enum periph)
disable the peripherals clock More...
void | rcu_periph_clock_sleep_enable (rcu_periph_sleep_enum periph)
enable the peripherals clock when sleep mode More...
void | rcu_periph_clock_sleep_disable (rcu_periph_sleep_enum periph)
disable the peripherals clock when sleep mode More...
void | rcu_periph_reset_enable (rcu_periph_reset_enum periph_reset)
reset the peripherals More...
void | rcu_periph_reset_disable (rcu_periph_reset_enum periph_reset)
disable reset the peripheral More...
void | rcu_bkp_reset_enable (void)
reset the BKP More...
void | rcu_bkp_reset_disable (void)
disable the BKP reset More...
void | rcu_system_clock_source_config (uint32_t ck_sys)
configure the system clock source More...
uint32_t | rcu_system_clock_source_get (void)
get the system clock source More...
void | rcu_ahb_clock_config (uint32_t ck_ahb)
configure the AHB clock prescaler selection More...
void | rcu_apb1_clock_config (uint32_t ck_apb1)
configure the APB1 clock prescaler selection More...
void | rcu_apb2_clock_config (uint32_t ck_apb2)
configure the APB2 clock prescaler selection More...
void | rcu_adc_clock_config (rcu_adc_clock_enum ck_adc)
configure the ADC clock prescaler selection More...
void | rcu_usbfs_clock_config (uint32_t ck_usbfs)
configure the USBFS clock prescaler selection More...
void | rcu_ckout_config (uint32_t ckout_src, uint32_t ckout_div)
configure the CK_OUT clock source and divider More...
void | rcu_pll_preselection_config (uint32_t pll_presel)
configure the PLL clock source preselection More...
void | rcu_pll_config (uint32_t pll_src, uint32_t pll_mul)
configure the PLL clock source selection and PLL multiply factor More...
void | rcu_usart_clock_config (uint32_t ck_usart)
configure the USART clock source selection More...
void | rcu_cec_clock_config (uint32_t ck_cec)
configure the CEC clock source selection More...
void | rcu_rtc_clock_config (uint32_t rtc_clock_source)
configure the RTC clock source selection More...
void | rcu_hxtal_prediv_config (uint32_t hxtal_prediv)
configure the HXTAL divider used as input of PLL More...
void | rcu_lxtal_drive_capability_config (uint32_t lxtal_dricap)
configure the LXTAL drive capability More...
FlagStatus | rcu_flag_get (rcu_flag_enum flag)
get the clock stabilization and periphral reset flags More...
void | rcu_all_reset_flag_clear (void)
clear the reset flag More...
FlagStatus | rcu_interrupt_flag_get (rcu_int_flag_enum int_flag)
get the clock stabilization interrupt and ckm flags More...
void | rcu_interrupt_flag_clear (rcu_int_flag_clear_enum int_flag_clear)
clear the interrupt flags More...
void | rcu_interrupt_enable (rcu_int_enum stab_int)
enable the stabilization interrupt More...
void | rcu_interrupt_disable (rcu_int_enum stab_int)
disable the stabilization interrupt More...
ErrStatus | rcu_osci_stab_wait (rcu_osci_type_enum osci)
wait until oscillator stabilization flags is SET More...
void | rcu_osci_on (rcu_osci_type_enum osci)
turn on the oscillator More...
void | rcu_osci_off (rcu_osci_type_enum osci)
turn off the oscillator More...
void | rcu_osci_bypass_mode_enable (rcu_osci_type_enum osci)
enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it More...
void | rcu_osci_bypass_mode_disable (rcu_osci_type_enum osci)
disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it More...
void | rcu_hxtal_clock_monitor_enable (void)
enable the HXTAL clock monitor More...
void | rcu_hxtal_clock_monitor_disable (void)
disable the HXTAL clock monitor More...
void | rcu_irc8m_adjust_value_set (uint8_t irc8m_adjval)
set the IRC8M adjust value More...
void | rcu_irc28m_adjust_value_set (uint8_t irc28m_adjval)
set the IRC28M adjust value More...
void | rcu_voltage_key_unlock (void)
unlock the voltage key More...
void | rcu_deepsleep_voltage_set (uint32_t dsvol)
set voltage in deep sleep mode More...
uint32_t | rcu_clock_freq_get (rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency More...

Detailed Description

definitions for the RCU

Definition in file gd32f3x0_rcu.h.

Macro Definition Documentation

#define BDCTL_LXTALDRI ( regval ) (BITS(3,4) & ((uint32_t)(regval) << 3))

Definition at line 625 of file gd32f3x0_rcu.h.

#define BDCTL_RTCSRC ( regval ) (BITS(8,9) & ((uint32_t)(regval) << 8))

Definition at line 632 of file gd32f3x0_rcu.h.

#define CFG0_ADCPSC ( regval ) (BITS(14,15) & ((uint32_t)(regval) << 14))

Definition at line 504 of file gd32f3x0_rcu.h.

#define CFG0_AHBPSC ( regval ) (BITS(4,7) & ((uint32_t)(regval) << 4))

Definition at line 476 of file gd32f3x0_rcu.h.

#define CFG0_APB1PSC ( regval ) (BITS(8,10) & ((uint32_t)(regval) << 8))

Definition at line 488 of file gd32f3x0_rcu.h.

#define CFG0_APB2PSC ( regval ) (BITS(11,13) & ((uint32_t)(regval) << 11))

Definition at line 496 of file gd32f3x0_rcu.h.

#define CFG0_CKOUTDIV ( regval ) (BITS(28,30) & ((uint32_t)(regval) << 28))

Definition at line 610 of file gd32f3x0_rcu.h.

#define CFG0_CKOUTSEL ( regval ) (BITS(24,26) & ((uint32_t)(regval) << 24))

Definition at line 598 of file gd32f3x0_rcu.h.

#define CFG0_PLLMF ( regval ) (BITS(18,21) & ((uint32_t)(regval) << 18))

Definition at line 523 of file gd32f3x0_rcu.h.

#define CFG0_SCS ( regval ) (BITS(0,1) & ((uint32_t)(regval) << 0))

Definition at line 464 of file gd32f3x0_rcu.h.

#define CFG0_SCSS ( regval ) (BITS(2,3) & ((uint32_t)(regval) << 2))

Definition at line 470 of file gd32f3x0_rcu.h.

#define CFG0_USBFSPSC ( regval ) (BITS(22,23) & ((uint32_t)(regval) << 22))

Definition at line 589 of file gd32f3x0_rcu.h.

#define CFG1_PREDV ( regval ) (BITS(0,3) & ((uint32_t)(regval) << 0))

Definition at line 639 of file gd32f3x0_rcu.h.

#define CFG2_USART0SEL ( regval ) (BITS(0,1) & ((uint32_t)(regval) << 0))

Definition at line 658 of file gd32f3x0_rcu.h.

#define DSV_DSLPVS ( regval ) (BITS(0,1) & ((uint32_t)(regval) << 0))

Definition at line 677 of file gd32f3x0_rcu.h.

#define RCU RCU_BASE

Definition at line 18 of file gd32f3x0_rcu.h.

#define RCU_ADC_CKAPB2_DIV2 CFG0_ADCPSC(0)

ADC clock prescaler select CK_APB2/2

Definition at line 505 of file gd32f3x0_rcu.h.

#define RCU_ADC_CKAPB2_DIV4 CFG0_ADCPSC(1)

ADC clock prescaler select CK_APB2/4

Definition at line 506 of file gd32f3x0_rcu.h.

#define RCU_ADC_CKAPB2_DIV6 CFG0_ADCPSC(2)

ADC clock prescaler select CK_APB2/6

Definition at line 507 of file gd32f3x0_rcu.h.

#define RCU_ADC_CKAPB2_DIV8 CFG0_ADCPSC(3)

ADC clock prescaler select CK_APB2/8

Definition at line 508 of file gd32f3x0_rcu.h.

#define RCU_ADC_IRC28M_DIV1 RCU_CFG2_IRC28MDIV

IRC28M select to ADC clock

Definition at line 674 of file gd32f3x0_rcu.h.

#define RCU_ADC_IRC28M_DIV2 (uint32_t)0x00000000U

IRC28M/2 select to ADC clock

Definition at line 673 of file gd32f3x0_rcu.h.

#define RCU_ADCSRC_APB2DIV RCU_CFG2_ADCSEL

ADC clock source select

Definition at line 670 of file gd32f3x0_rcu.h.

#define RCU_ADCSRC_IRC28M (uint32_t)0x00000000U

ADC clock source select

Definition at line 669 of file gd32f3x0_rcu.h.

#define RCU_ADDAPB1EN REG32(RCU + 0xF8U)

APB1 additional enable register

Definition at line 37 of file gd32f3x0_rcu.h.

#define RCU_ADDAPB1EN_CTCEN BIT(27)

CTC unit clock enable

Definition at line 219 of file gd32f3x0_rcu.h.

#define RCU_ADDAPB1EN_I2C2EN BIT(0)

I2C2 unit clock enable

Definition at line 218 of file gd32f3x0_rcu.h.

#define RCU_ADDAPB1RST REG32(RCU + 0xFCU)

APB1 additional reset register

Definition at line 38 of file gd32f3x0_rcu.h.

#define RCU_ADDAPB1RST_CTCRST BIT(27)

CTC unit reset

Definition at line 223 of file gd32f3x0_rcu.h.

#define RCU_ADDAPB1RST_I2C2RST BIT(0)

I2C2 unit reset

Definition at line 222 of file gd32f3x0_rcu.h.

#define RCU_ADDCTL REG32(RCU + 0xC0U)

additional clock control register

Definition at line 35 of file gd32f3x0_rcu.h.

#define RCU_ADDCTL_CK48MSEL BIT(0)

48M clock selection

Definition at line 207 of file gd32f3x0_rcu.h.

#define RCU_ADDCTL_IRC48MCALIB BITS(24,31)

internal 48M RC oscillator calibration value register

Definition at line 210 of file gd32f3x0_rcu.h.

#define RCU_ADDCTL_IRC48MEN BIT(16)

IRC48M internal 48M RC oscillator enable

Definition at line 208 of file gd32f3x0_rcu.h.

#define RCU_ADDCTL_IRC48MSTB BIT(17)

internal 48M RC oscillator stabilization flag

Definition at line 209 of file gd32f3x0_rcu.h.

#define RCU_ADDINT REG32(RCU + 0xCCU)

additional clock interrupt register

Definition at line 36 of file gd32f3x0_rcu.h.

#define RCU_ADDINT_IRC48MSTBIC BIT(22)

IRC48M stabilization interrupt clear

Definition at line 215 of file gd32f3x0_rcu.h.

#define RCU_ADDINT_IRC48MSTBIE BIT(14)

IRC48M stabilization interrupt enable

Definition at line 214 of file gd32f3x0_rcu.h.

#define RCU_ADDINT_IRC48MSTBIF BIT(6)

IRC48M stabilization interrupt flag

Definition at line 213 of file gd32f3x0_rcu.h.

#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0)

AHB prescaler select CK_SYS

Definition at line 477 of file gd32f3x0_rcu.h.

#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13)

AHB prescaler select CK_SYS/128

Definition at line 483 of file gd32f3x0_rcu.h.

#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11)

AHB prescaler select CK_SYS/16

Definition at line 481 of file gd32f3x0_rcu.h.

#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8)

AHB prescaler select CK_SYS/2

Definition at line 478 of file gd32f3x0_rcu.h.

#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14)

AHB prescaler select CK_SYS/256

Definition at line 484 of file gd32f3x0_rcu.h.

#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9)

AHB prescaler select CK_SYS/4

Definition at line 479 of file gd32f3x0_rcu.h.

#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15)

AHB prescaler select CK_SYS/512

Definition at line 485 of file gd32f3x0_rcu.h.

#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12)

AHB prescaler select CK_SYS/64

Definition at line 482 of file gd32f3x0_rcu.h.

#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10)

AHB prescaler select CK_SYS/8

Definition at line 480 of file gd32f3x0_rcu.h.

#define RCU_AHBEN REG32(RCU + 0x14U)

AHB enable register

Definition at line 26 of file gd32f3x0_rcu.h.

#define RCU_AHBEN_CRCEN BIT(6)

CRC clock enable

Definition at line 122 of file gd32f3x0_rcu.h.

#define RCU_AHBEN_DMAEN BIT(0)

DMA clock enable

Definition at line 119 of file gd32f3x0_rcu.h.

#define RCU_AHBEN_FMCSPEN BIT(4)

FMC clock enable

Definition at line 121 of file gd32f3x0_rcu.h.

#define RCU_AHBEN_PAEN BIT(17)

GPIO port A clock enable

Definition at line 124 of file gd32f3x0_rcu.h.

#define RCU_AHBEN_PBEN BIT(18)

GPIO port B clock enable

Definition at line 125 of file gd32f3x0_rcu.h.

#define RCU_AHBEN_PCEN BIT(19)

GPIO port C clock enable

Definition at line 126 of file gd32f3x0_rcu.h.

#define RCU_AHBEN_PDEN BIT(20)

GPIO port D clock enable

Definition at line 127 of file gd32f3x0_rcu.h.

#define RCU_AHBEN_PFEN BIT(22)

GPIO port F clock enable

Definition at line 128 of file gd32f3x0_rcu.h.

#define RCU_AHBEN_SRAMSPEN BIT(2)

SRAM interface clock enable

Definition at line 120 of file gd32f3x0_rcu.h.

#define RCU_AHBEN_TSIEN BIT(24)

TSI clock enable

Definition at line 129 of file gd32f3x0_rcu.h.

#define RCU_AHBEN_USBFS BIT(12)

USBFS clock enable

Definition at line 123 of file gd32f3x0_rcu.h.

#define RCU_AHBRST REG32(RCU + 0x28U)

AHB reset register

Definition at line 31 of file gd32f3x0_rcu.h.

#define RCU_AHBRST_PARST BIT(17)

GPIO port A reset

Definition at line 180 of file gd32f3x0_rcu.h.

#define RCU_AHBRST_PBRST BIT(18)

GPIO port B reset

Definition at line 181 of file gd32f3x0_rcu.h.

#define RCU_AHBRST_PCRST BIT(19)

GPIO port C reset

Definition at line 182 of file gd32f3x0_rcu.h.

#define RCU_AHBRST_PDRST BIT(20)

GPIO port D reset

Definition at line 183 of file gd32f3x0_rcu.h.

#define RCU_AHBRST_PFRST BIT(22)

GPIO port F reset

Definition at line 184 of file gd32f3x0_rcu.h.

#define RCU_AHBRST_TSIRST BIT(24)

TSI unit reset

Definition at line 185 of file gd32f3x0_rcu.h.

#define RCU_AHBRST_USBFSRST BIT(12)

USBFS reset

Definition at line 179 of file gd32f3x0_rcu.h.

#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0)

APB1 prescaler select CK_AHB

Definition at line 489 of file gd32f3x0_rcu.h.

#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7)

APB1 prescaler select CK_AHB/16

Definition at line 493 of file gd32f3x0_rcu.h.

#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4)

APB1 prescaler select CK_AHB/2

Definition at line 490 of file gd32f3x0_rcu.h.

#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5)

APB1 prescaler select CK_AHB/4

Definition at line 491 of file gd32f3x0_rcu.h.

#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6)

APB1 prescaler select CK_AHB/8

Definition at line 492 of file gd32f3x0_rcu.h.

#define RCU_APB1EN REG32(RCU + 0x1CU)

APB1 enable register

Definition at line 28 of file gd32f3x0_rcu.h.

#define RCU_APB1EN_CECEN BIT(30)

HDMI CEC interface clock enable

Definition at line 154 of file gd32f3x0_rcu.h.

#define RCU_APB1EN_DACEN BIT(29)

DAC interface clock enable

Definition at line 153 of file gd32f3x0_rcu.h.

#define RCU_APB1EN_I2C0EN BIT(21)

I2C0 clock enable

Definition at line 150 of file gd32f3x0_rcu.h.

#define RCU_APB1EN_I2C1EN BIT(22)

I2C1 clock enable

Definition at line 151 of file gd32f3x0_rcu.h.

#define RCU_APB1EN_PMUEN BIT(28)

power interface clock enable

Definition at line 152 of file gd32f3x0_rcu.h.

#define RCU_APB1EN_SPI1EN BIT(14)

SPI1 clock enable

Definition at line 147 of file gd32f3x0_rcu.h.

#define RCU_APB1EN_SPI2EN BIT(15)

SPI2 clock enable

Definition at line 148 of file gd32f3x0_rcu.h.

#define RCU_APB1EN_TIMER13EN BIT(8)

TIMER13 timer clock enable

Definition at line 145 of file gd32f3x0_rcu.h.

#define RCU_APB1EN_TIMER1EN BIT(0)

TIMER1 timer clock enable

Definition at line 142 of file gd32f3x0_rcu.h.

#define RCU_APB1EN_TIMER2EN BIT(1)

TIMER2 timer clock enable

Definition at line 143 of file gd32f3x0_rcu.h.

#define RCU_APB1EN_TIMER5EN BIT(4)

TIMER5 timer clock enable

Definition at line 144 of file gd32f3x0_rcu.h.

#define RCU_APB1EN_USART1EN BIT(17)

USART1 clock enable

Definition at line 149 of file gd32f3x0_rcu.h.

#define RCU_APB1EN_WWDGTEN BIT(11)

window watchdog timer clock enable

Definition at line 146 of file gd32f3x0_rcu.h.

#define RCU_APB1RST REG32(RCU + 0x10U)

APB1 reset register

Definition at line 25 of file gd32f3x0_rcu.h.

#define RCU_APB1RST_CECRST BIT(30)

HDMI CEC reset

Definition at line 116 of file gd32f3x0_rcu.h.

#define RCU_APB1RST_DACRST BIT(29)

DAC reset

Definition at line 115 of file gd32f3x0_rcu.h.

#define RCU_APB1RST_I2C0RST BIT(21)

I2C0 reset

Definition at line 112 of file gd32f3x0_rcu.h.

#define RCU_APB1RST_I2C1RST BIT(22)

I2C1 reset

Definition at line 113 of file gd32f3x0_rcu.h.

#define RCU_APB1RST_PMURST BIT(28)

power control reset

Definition at line 114 of file gd32f3x0_rcu.h.

#define RCU_APB1RST_SPI1RST BIT(14)

SPI1 reset

Definition at line 109 of file gd32f3x0_rcu.h.

#define RCU_APB1RST_SPI2RST BIT(15)

SPI2 reset

Definition at line 110 of file gd32f3x0_rcu.h.

#define RCU_APB1RST_TIMER13RST BIT(8)

TIMER13 timer reset

Definition at line 107 of file gd32f3x0_rcu.h.

#define RCU_APB1RST_TIMER1RST BIT(0)

TIMER1 timer reset

Definition at line 104 of file gd32f3x0_rcu.h.

#define RCU_APB1RST_TIMER2RST BIT(1)

TIMER2 timer reset

Definition at line 105 of file gd32f3x0_rcu.h.

#define RCU_APB1RST_TIMER5RST BIT(4)

TIMER5 timer reset

Definition at line 106 of file gd32f3x0_rcu.h.

#define RCU_APB1RST_USART1RST BIT(17)

USART1 reset

Definition at line 111 of file gd32f3x0_rcu.h.

#define RCU_APB1RST_WWDGTRST BIT(11)

window watchdog timer reset

Definition at line 108 of file gd32f3x0_rcu.h.

#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0)

APB2 prescaler select CK_AHB

Definition at line 497 of file gd32f3x0_rcu.h.

#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7)

APB2 prescaler select CK_AHB/16

Definition at line 501 of file gd32f3x0_rcu.h.

#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4)

APB2 prescaler select CK_AHB/2

Definition at line 498 of file gd32f3x0_rcu.h.

#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5)

APB2 prescaler select CK_AHB/4

Definition at line 499 of file gd32f3x0_rcu.h.

#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6)

APB2 prescaler select CK_AHB/8

Definition at line 500 of file gd32f3x0_rcu.h.

#define RCU_APB2EN REG32(RCU + 0x18U)

APB2 enable register

Definition at line 27 of file gd32f3x0_rcu.h.

#define RCU_APB2EN_ADCEN BIT(9)

ADC interface clock enable

Definition at line 133 of file gd32f3x0_rcu.h.

#define RCU_APB2EN_CFGCMPEN BIT(0)

system configuration and comparator clock enable

Definition at line 132 of file gd32f3x0_rcu.h.

#define RCU_APB2EN_SPI0EN BIT(12)

SPI0 clock enable

Definition at line 135 of file gd32f3x0_rcu.h.

#define RCU_APB2EN_TIMER0EN BIT(11)

TIMER0 timer clock enable

Definition at line 134 of file gd32f3x0_rcu.h.

#define RCU_APB2EN_TIMER14EN BIT(16)

TIMER14 timer clock enable

Definition at line 137 of file gd32f3x0_rcu.h.

#define RCU_APB2EN_TIMER15EN BIT(17)

TIMER15 timer clock enable

Definition at line 138 of file gd32f3x0_rcu.h.

#define RCU_APB2EN_TIMER16EN BIT(18)

TIMER16 timer clock enable

Definition at line 139 of file gd32f3x0_rcu.h.

#define RCU_APB2EN_USART0EN BIT(14)

USART0 clock enable

Definition at line 136 of file gd32f3x0_rcu.h.

#define RCU_APB2RST REG32(RCU + 0x0CU)

APB2 reset register

Definition at line 24 of file gd32f3x0_rcu.h.

#define RCU_APB2RST_ADCRST BIT(9)

ADC reset

Definition at line 95 of file gd32f3x0_rcu.h.

#define RCU_APB2RST_CFGRST BIT(0)

system configuration reset

Definition at line 94 of file gd32f3x0_rcu.h.

#define RCU_APB2RST_SPI0RST BIT(12)

SPI0 reset

Definition at line 97 of file gd32f3x0_rcu.h.

#define RCU_APB2RST_TIMER0RST BIT(11)

TIMER0 reset

Definition at line 96 of file gd32f3x0_rcu.h.

#define RCU_APB2RST_TIMER14RST BIT(16)

TIMER14 reset

Definition at line 99 of file gd32f3x0_rcu.h.

#define RCU_APB2RST_TIMER15RST BIT(17)

TIMER15 reset

Definition at line 100 of file gd32f3x0_rcu.h.

#define RCU_APB2RST_TIMER16RST BIT(18)

TIMER16 reset

Definition at line 101 of file gd32f3x0_rcu.h.

#define RCU_APB2RST_USART0RST BIT(14)

USART0 reset

Definition at line 98 of file gd32f3x0_rcu.h.

#define RCU_BDCTL REG32(RCU + 0x20U)

backup domain control register

Definition at line 29 of file gd32f3x0_rcu.h.

#define RCU_BDCTL_BKPRST BIT(16)

backup domain reset

Definition at line 163 of file gd32f3x0_rcu.h.

#define RCU_BDCTL_LXTALBPS BIT(2)

LXTAL bypass mode enable

Definition at line 159 of file gd32f3x0_rcu.h.

#define RCU_BDCTL_LXTALDRI BITS(3,4)

LXTAL drive capability

Definition at line 160 of file gd32f3x0_rcu.h.

#define RCU_BDCTL_LXTALEN BIT(0)

LXTAL enable

Definition at line 157 of file gd32f3x0_rcu.h.

#define RCU_BDCTL_LXTALSTB BIT(1)

external low-speed oscillator stabilization

Definition at line 158 of file gd32f3x0_rcu.h.

#define RCU_BDCTL_RTCEN BIT(15)

RTC clock enable

Definition at line 162 of file gd32f3x0_rcu.h.

#define RCU_BDCTL_RTCSRC BITS(8,9)

RTC clock entry selection

Definition at line 161 of file gd32f3x0_rcu.h.

#define RCU_BIT_POS ( val ) ((uint32_t)(val) & 0x1FU)

Definition at line 235 of file gd32f3x0_rcu.h.

#define RCU_CECSRC_IRC8M_DIV244 (uint32_t)0x00000000U

CK_CEC clock source select IRC8M/244

Definition at line 665 of file gd32f3x0_rcu.h.

#define RCU_CECSRC_LXTAL RCU_CFG2_CECSEL

CK_CEC clock source select LXTAL

Definition at line 666 of file gd32f3x0_rcu.h.

#define RCU_CFG0 REG32(RCU + 0x04U)

configuration register 0

Definition at line 22 of file gd32f3x0_rcu.h.

#define RCU_CFG0_ADCPSC BITS(14,15)

ADC clock prescaler selection

Definition at line 61 of file gd32f3x0_rcu.h.

#define RCU_CFG0_AHBPSC BITS(4,7)

AHB prescaler selection

Definition at line 58 of file gd32f3x0_rcu.h.

#define RCU_CFG0_APB1PSC BITS(8,10)

APB1 prescaler selection

Definition at line 59 of file gd32f3x0_rcu.h.

#define RCU_CFG0_APB2PSC BITS(11,13)

APB2 prescaler selection

Definition at line 60 of file gd32f3x0_rcu.h.

#define RCU_CFG0_CKOUTDIV BITS(28,30)

CK_OUT divider which the CK_OUT frequency can be reduced

Definition at line 68 of file gd32f3x0_rcu.h.

#define RCU_CFG0_CKOUTSEL BITS(24,26)

CK_OUT clock source selection

Definition at line 66 of file gd32f3x0_rcu.h.

#define RCU_CFG0_PLLDV BIT(31)

CK_PLL divide by 1 or 2

Definition at line 69 of file gd32f3x0_rcu.h.

#define RCU_CFG0_PLLMF (BIT(27) | BITS(18,21))

PLL multiply factor

Definition at line 64 of file gd32f3x0_rcu.h.

#define RCU_CFG0_PLLMF4 BIT(27)

bit 4 of PLLMF

Definition at line 67 of file gd32f3x0_rcu.h.

#define RCU_CFG0_PLLPREDV BIT(17)

divider for PLL source clock selection

Definition at line 63 of file gd32f3x0_rcu.h.

#define RCU_CFG0_PLLSEL BIT(16)

PLL clock source selection

Definition at line 62 of file gd32f3x0_rcu.h.

#define RCU_CFG0_SCS BITS(0,1)

system clock switch

Definition at line 56 of file gd32f3x0_rcu.h.

#define RCU_CFG0_SCSS BITS(2,3)

system clock switch status

Definition at line 57 of file gd32f3x0_rcu.h.

#define RCU_CFG0_USBFSPSC BITS(22,23)

USBFS clock prescaler selection

Definition at line 65 of file gd32f3x0_rcu.h.

#define RCU_CFG1 REG32(RCU + 0x2CU)

configuration register 1

Definition at line 32 of file gd32f3x0_rcu.h.

#define RCU_CFG1_PLLMF5 BIT(31)

bit 5 of PLLMF

Definition at line 190 of file gd32f3x0_rcu.h.

#define RCU_CFG1_PLLPRESEL BIT(30)

PLL clock source preselection

Definition at line 189 of file gd32f3x0_rcu.h.

#define RCU_CFG1_PREDV BITS(0,3)

CK_HXTAL divider previous PLL

Definition at line 188 of file gd32f3x0_rcu.h.

#define RCU_CFG2 REG32(RCU + 0x30U)

configuration register 2

Definition at line 33 of file gd32f3x0_rcu.h.

#define RCU_CFG2_ADCPSC2 BIT(31)

bit 2 of ADCPSC

Definition at line 198 of file gd32f3x0_rcu.h.

#define RCU_CFG2_ADCSEL BIT(8)

CK_ADC clock source selection

Definition at line 195 of file gd32f3x0_rcu.h.

#define RCU_CFG2_CECSEL BIT(6)

CK_CEC clock source selection

Definition at line 194 of file gd32f3x0_rcu.h.

#define RCU_CFG2_IRC28MDIV BIT(16)

CK_IRC28M divider 2 or not

Definition at line 196 of file gd32f3x0_rcu.h.

#define RCU_CFG2_USART0SEL BITS(0,1)

CK_USART0 clock source selection

Definition at line 193 of file gd32f3x0_rcu.h.

#define RCU_CFG2_USBFSPSC2 BIT(30)

bit 2 of USBFSPSC

Definition at line 197 of file gd32f3x0_rcu.h.

#define RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0)

CK_OUT is divided by 1

Definition at line 611 of file gd32f3x0_rcu.h.

#define RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7)

CK_OUT is divided by 128

Definition at line 618 of file gd32f3x0_rcu.h.

#define RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4)

CK_OUT is divided by 16

Definition at line 615 of file gd32f3x0_rcu.h.

#define RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1)

CK_OUT is divided by 2

Definition at line 612 of file gd32f3x0_rcu.h.

#define RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5)

CK_OUT is divided by 32

Definition at line 616 of file gd32f3x0_rcu.h.

#define RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2)

CK_OUT is divided by 4

Definition at line 613 of file gd32f3x0_rcu.h.

#define RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6)

CK_OUT is divided by 64

Definition at line 617 of file gd32f3x0_rcu.h.

#define RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3)

CK_OUT is divided by 8

Definition at line 614 of file gd32f3x0_rcu.h.

#define RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7))

CK_OUT clock source select CK_PLL

Definition at line 606 of file gd32f3x0_rcu.h.

#define RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7)

CK_OUT clock source select CK_PLL/2

Definition at line 607 of file gd32f3x0_rcu.h.

#define RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4)

CK_OUT clock source select CKSYS

Definition at line 603 of file gd32f3x0_rcu.h.

#define RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6)

CK_OUT clock source select HXTAL

Definition at line 605 of file gd32f3x0_rcu.h.

#define RCU_CKOUTSRC_IRC28M CFG0_CKOUTSEL(1)

CK_OUT clock source select IRC28M

Definition at line 600 of file gd32f3x0_rcu.h.

#define RCU_CKOUTSRC_IRC40K CFG0_CKOUTSEL(2)

CK_OUT clock source select IRC40K

Definition at line 601 of file gd32f3x0_rcu.h.

#define RCU_CKOUTSRC_IRC8M CFG0_CKOUTSEL(5)

CK_OUT clock source select IRC8M

Definition at line 604 of file gd32f3x0_rcu.h.

#define RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3)

CK_OUT clock source select LXTAL

Definition at line 602 of file gd32f3x0_rcu.h.

#define RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0)

no clock selected

Definition at line 599 of file gd32f3x0_rcu.h.

#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1)

system clock source select HXTAL

Definition at line 466 of file gd32f3x0_rcu.h.

#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0)

system clock source select IRC8M

Definition at line 465 of file gd32f3x0_rcu.h.

#define RCU_CKSYSSRC_PLL CFG0_SCS(2)

system clock source select PLL

Definition at line 467 of file gd32f3x0_rcu.h.

#define RCU_CTL0 REG32(RCU + 0x00U)

control register 0

Definition at line 21 of file gd32f3x0_rcu.h.

#define RCU_CTL0_CKMEN BIT(19)

HXTAL clock monitor enable

Definition at line 51 of file gd32f3x0_rcu.h.

#define RCU_CTL0_HXTALBPS BIT(18)

external crystal oscillator clock bypass mode enable

Definition at line 50 of file gd32f3x0_rcu.h.

#define RCU_CTL0_HXTALEN BIT(16)

external high speed oscillator enable

Definition at line 48 of file gd32f3x0_rcu.h.

#define RCU_CTL0_HXTALSTB BIT(17)

external crystal oscillator clock stabilization flag

Definition at line 49 of file gd32f3x0_rcu.h.

#define RCU_CTL0_IRC8MADJ BITS(3,7)

high speed internal oscillator clock trim adjust value

Definition at line 46 of file gd32f3x0_rcu.h.

#define RCU_CTL0_IRC8MCALIB BITS(8,15)

high speed internal oscillator calibration value register

Definition at line 47 of file gd32f3x0_rcu.h.

#define RCU_CTL0_IRC8MEN BIT(0)

internal high speed oscillator enable

Definition at line 44 of file gd32f3x0_rcu.h.

#define RCU_CTL0_IRC8MSTB BIT(1)

IRC8M high speed internal oscillator stabilization flag

Definition at line 45 of file gd32f3x0_rcu.h.

#define RCU_CTL0_PLLEN BIT(24)

PLL enable

Definition at line 52 of file gd32f3x0_rcu.h.

#define RCU_CTL0_PLLSTB BIT(25)

PLL clock stabilization flag

Definition at line 53 of file gd32f3x0_rcu.h.

#define RCU_CTL1 REG32(RCU + 0x34U)

control register 1

Definition at line 34 of file gd32f3x0_rcu.h.

#define RCU_CTL1_IRC28MADJ BITS(3,7)

internal 28M RC oscillator clock trim adjust value

Definition at line 203 of file gd32f3x0_rcu.h.

#define RCU_CTL1_IRC28MCALIB BITS(8,15)

internal 28M RC oscillator calibration value register

Definition at line 204 of file gd32f3x0_rcu.h.

#define RCU_CTL1_IRC28MEN BIT(0)

IRC28M internal 28M RC oscillator enable

Definition at line 201 of file gd32f3x0_rcu.h.

#define RCU_CTL1_IRC28MSTB BIT(1)

IRC28M internal 28M RC oscillator stabilization flag

Definition at line 202 of file gd32f3x0_rcu.h.

#define RCU_DEEPSLEEP_V_0_7 DSV_DSLPVS(3)

core voltage is 0.7V in deep-sleep mode

Definition at line 681 of file gd32f3x0_rcu.h.

#define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2)

core voltage is 0.8V in deep-sleep mode

Definition at line 680 of file gd32f3x0_rcu.h.

#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1)

core voltage is 0.9V in deep-sleep mode

Definition at line 679 of file gd32f3x0_rcu.h.

#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0)

core voltage is 1.0V in deep-sleep mode

Definition at line 678 of file gd32f3x0_rcu.h.

#define RCU_DSV REG32(RCU + 0x134U)

deep-sleep mode voltage register

Definition at line 40 of file gd32f3x0_rcu.h.

#define RCU_DSV_DSLPVS BITS(0,1)

deep-sleep mode voltage select

Definition at line 229 of file gd32f3x0_rcu.h.

#define RCU_INT REG32(RCU + 0x08U)

interrupt register

Definition at line 23 of file gd32f3x0_rcu.h.

#define RCU_INT_CKMIC BIT(23)

HXTAL clock stuck interrupt clear

Definition at line 91 of file gd32f3x0_rcu.h.

#define RCU_INT_CKMIF BIT(7)

HXTAL clock stuck interrupt flag

Definition at line 78 of file gd32f3x0_rcu.h.

#define RCU_INT_HXTALSTBIC BIT(19)

HXTAL stabilization interrupt clear

Definition at line 88 of file gd32f3x0_rcu.h.

#define RCU_INT_HXTALSTBIE BIT(11)

HXTAL stabilization interrupt enable

Definition at line 82 of file gd32f3x0_rcu.h.

#define RCU_INT_HXTALSTBIF BIT(3)

HXTAL stabilization interrupt flag

Definition at line 75 of file gd32f3x0_rcu.h.

#define RCU_INT_IRC28MSTBIC BIT(21)

IRC28M stabilization interrupt clear

Definition at line 90 of file gd32f3x0_rcu.h.

#define RCU_INT_IRC28MSTBIE BIT(13)

IRC28M stabilization interrupt enable

Definition at line 84 of file gd32f3x0_rcu.h.

#define RCU_INT_IRC28MSTBIF BIT(5)

IRC28M stabilization interrupt flag

Definition at line 77 of file gd32f3x0_rcu.h.

#define RCU_INT_IRC40KSTBIC BIT(16)

IRC40K stabilization interrupt clear

Definition at line 85 of file gd32f3x0_rcu.h.

#define RCU_INT_IRC40KSTBIE BIT(8)

IRC40K stabilization interrupt enable

Definition at line 79 of file gd32f3x0_rcu.h.

#define RCU_INT_IRC40KSTBIF BIT(0)

IRC40K stabilization interrupt flag

Definition at line 72 of file gd32f3x0_rcu.h.

#define RCU_INT_IRC8MSTBIC BIT(18)

IRC8M stabilization interrupt clear

Definition at line 87 of file gd32f3x0_rcu.h.

#define RCU_INT_IRC8MSTBIE BIT(10)

IRC8M stabilization interrupt enable

Definition at line 81 of file gd32f3x0_rcu.h.

#define RCU_INT_IRC8MSTBIF BIT(2)

IRC8M stabilization interrupt flag

Definition at line 74 of file gd32f3x0_rcu.h.

#define RCU_INT_LXTALSTBIC BIT(17)

LXTAL stabilization interrupt clear

Definition at line 86 of file gd32f3x0_rcu.h.

#define RCU_INT_LXTALSTBIE BIT(9)

LXTAL stabilization interrupt enable

Definition at line 80 of file gd32f3x0_rcu.h.

#define RCU_INT_LXTALSTBIF BIT(1)

LXTAL stabilization interrupt flag

Definition at line 73 of file gd32f3x0_rcu.h.

#define RCU_INT_PLLSTBIC BIT(20)

PLL stabilization interrupt clear

Definition at line 89 of file gd32f3x0_rcu.h.

#define RCU_INT_PLLSTBIE BIT(12)

PLL stabilization interrupt enable

Definition at line 83 of file gd32f3x0_rcu.h.

#define RCU_INT_PLLSTBIF BIT(4)

PLL stabilization interrupt flag

Definition at line 76 of file gd32f3x0_rcu.h.

#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3)

higher driving capability

Definition at line 629 of file gd32f3x0_rcu.h.

#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0)

lower driving capability

Definition at line 626 of file gd32f3x0_rcu.h.

#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2)

medium high driving capability

Definition at line 628 of file gd32f3x0_rcu.h.

#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1)

medium low driving capability

Definition at line 627 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL10 CFG0_PLLMF(8)

PLL source clock multiply by 10

Definition at line 532 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL11 CFG0_PLLMF(9)

PLL source clock multiply by 11

Definition at line 533 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL12 CFG0_PLLMF(10)

PLL source clock multiply by 12

Definition at line 534 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL13 CFG0_PLLMF(11)

PLL source clock multiply by 13

Definition at line 535 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL14 CFG0_PLLMF(12)

PLL source clock multiply by 14

Definition at line 536 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL15 CFG0_PLLMF(13)

PLL source clock multiply by 15

Definition at line 537 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL16 CFG0_PLLMF(14)

PLL source clock multiply by 16

Definition at line 538 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL17 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0))

PLL source clock multiply by 17

Definition at line 539 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL18 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1))

PLL source clock multiply by 18

Definition at line 540 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL19 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2))

PLL source clock multiply by 19

Definition at line 541 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL2 CFG0_PLLMF(0)

PLL source clock multiply by 2

Definition at line 524 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL20 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3))

PLL source clock multiply by 20

Definition at line 542 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL21 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4))

PLL source clock multiply by 21

Definition at line 543 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL22 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5))

PLL source clock multiply by 22

Definition at line 544 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL23 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6))

PLL source clock multiply by 23

Definition at line 545 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL24 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7))

PLL source clock multiply by 24

Definition at line 546 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL25 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8))

PLL source clock multiply by 25

Definition at line 547 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL26 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9))

PLL source clock multiply by 26

Definition at line 548 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL27 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10))

PLL source clock multiply by 27

Definition at line 549 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL28 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11))

PLL source clock multiply by 28

Definition at line 550 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL29 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12))

PLL source clock multiply by 29

Definition at line 551 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL3 CFG0_PLLMF(1)

PLL source clock multiply by 3

Definition at line 525 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL30 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13))

PLL source clock multiply by 30

Definition at line 552 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL31 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14))

PLL source clock multiply by 31

Definition at line 553 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL32 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15))

PLL source clock multiply by 32

Definition at line 554 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL33 (CFG0_PLLMF(0) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 33

Definition at line 555 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL34 (CFG0_PLLMF(1) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 34

Definition at line 556 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL35 (CFG0_PLLMF(2) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 35

Definition at line 557 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL36 (CFG0_PLLMF(3) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 36

Definition at line 558 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL37 (CFG0_PLLMF(4) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 37

Definition at line 559 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL38 (CFG0_PLLMF(5) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 38

Definition at line 560 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL39 (CFG0_PLLMF(6) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 39

Definition at line 561 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL4 CFG0_PLLMF(2)

PLL source clock multiply by 4

Definition at line 526 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL40 (CFG0_PLLMF(7) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 40

Definition at line 562 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL41 (CFG0_PLLMF(8) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 41

Definition at line 563 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL42 (CFG0_PLLMF(9) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 42

Definition at line 564 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL43 (CFG0_PLLMF(10) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 43

Definition at line 565 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL44 (CFG0_PLLMF(11) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 44

Definition at line 566 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL45 (CFG0_PLLMF(12) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 45

Definition at line 567 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL46 (CFG0_PLLMF(13) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 46

Definition at line 568 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL47 (CFG0_PLLMF(14) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 47

Definition at line 569 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL48 (CFG0_PLLMF(15) | RCU_CFG1_PLLMF5)

PLL source clock multiply by 48

Definition at line 570 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL49 (RCU_CFG0_PLLMF4 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 49

Definition at line 571 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL5 CFG0_PLLMF(3)

PLL source clock multiply by 5

Definition at line 527 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL50 (RCU_PLL_MUL18 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 50

Definition at line 572 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL51 (RCU_PLL_MUL19 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 51

Definition at line 573 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL52 (RCU_PLL_MUL20 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 52

Definition at line 574 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL53 (RCU_PLL_MUL21 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 53

Definition at line 575 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL54 (RCU_PLL_MUL22 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 54

Definition at line 576 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL55 (RCU_PLL_MUL23 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 55

Definition at line 577 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL56 (RCU_PLL_MUL24 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 56

Definition at line 578 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL57 (RCU_PLL_MUL25 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 57

Definition at line 579 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL58 (RCU_PLL_MUL26 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 58

Definition at line 580 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL59 (RCU_PLL_MUL27 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 59

Definition at line 581 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL6 CFG0_PLLMF(4)

PLL source clock multiply by 6

Definition at line 528 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL60 (RCU_PLL_MUL28 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 60

Definition at line 582 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL61 (RCU_PLL_MUL29 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 61

Definition at line 583 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL62 (RCU_PLL_MUL30 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 62

Definition at line 584 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL63 (RCU_PLL_MUL31 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 63

Definition at line 585 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL64 (RCU_PLL_MUL32 | RCU_CFG1_PLLMF5)

PLL source clock multiply by 64

Definition at line 586 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL7 CFG0_PLLMF(5)

PLL source clock multiply by 7

Definition at line 529 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL8 CFG0_PLLMF(6)

PLL source clock multiply by 8

Definition at line 530 of file gd32f3x0_rcu.h.

#define RCU_PLL_MUL9 CFG0_PLLMF(7)

PLL source clock multiply by 9

Definition at line 531 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV1 CFG1_PREDV(0)

PLL not divided

Definition at line 640 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV10 CFG1_PREDV(9)

PLL divided by 10

Definition at line 649 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV11 CFG1_PREDV(10)

PLL divided by 11

Definition at line 650 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV12 CFG1_PREDV(11)

PLL divided by 12

Definition at line 651 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV13 CFG1_PREDV(12)

PLL divided by 13

Definition at line 652 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV14 CFG1_PREDV(13)

PLL divided by 14

Definition at line 653 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV15 CFG1_PREDV(14)

PLL divided by 15

Definition at line 654 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV16 CFG1_PREDV(15)

PLL divided by 16

Definition at line 655 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV2 CFG1_PREDV(1)

PLL divided by 2

Definition at line 641 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV3 CFG1_PREDV(2)

PLL divided by 3

Definition at line 642 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV4 CFG1_PREDV(3)

PLL divided by 4

Definition at line 643 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV5 CFG1_PREDV(4)

PLL divided by 5

Definition at line 644 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV6 CFG1_PREDV(5)

PLL divided by 6

Definition at line 645 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV7 CFG1_PREDV(6)

PLL divided by 7

Definition at line 646 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV8 CFG1_PREDV(7)

PLL divided by 8

Definition at line 647 of file gd32f3x0_rcu.h.

#define RCU_PLL_PREDV9 CFG1_PREDV(8)

PLL divided by 9

Definition at line 648 of file gd32f3x0_rcu.h.

#define RCU_PLLDV_CKPLL RCU_CFG0_PLLDV

CK_PLL divide by 1 for CK_OUT

Definition at line 622 of file gd32f3x0_rcu.h.

#define RCU_PLLDV_CKPLL_DIV2 (uint32_t)0x00000000U

CK_PLL divide by 2 for CK_OUT

Definition at line 621 of file gd32f3x0_rcu.h.

#define RCU_PLLPREDV (uint32_t)0x00000000U

HXTAL or IRC48M clock selected

Definition at line 519 of file gd32f3x0_rcu.h.

#define RCU_PLLPREDV_DIV2 RCU_CFG0_PLLPREDV

(HXTAL or IRC48M) /2 clock selected

Definition at line 520 of file gd32f3x0_rcu.h.

#define RCU_PLLPRESEL_HXTAL (uint32_t)0x00000000U

PLL clock source preselection HXTAL

Definition at line 515 of file gd32f3x0_rcu.h.

#define RCU_PLLPRESEL_IRC48M RCU_CFG1_PLLPRESEL

PLL clock source preselection IRC48M

Definition at line 516 of file gd32f3x0_rcu.h.

#define RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL

PLL clock source select HXTAL or IRC48M

Definition at line 512 of file gd32f3x0_rcu.h.

#define RCU_PLLSRC_IRC8M_DIV2 (uint32_t)0x00000000U

PLL clock source select IRC8M/2

Definition at line 511 of file gd32f3x0_rcu.h.

#define RCU_REG_VAL ( periph ) (REG32(RCU + ((uint32_t)(periph)>>6)))

Definition at line 234 of file gd32f3x0_rcu.h.

#define RCU_REGIDX_BIT | ( | regidx,
 |  | bitpos
 | ) | (((uint32_t)(regidx)<<6) | (uint32_t)(bitpos))

Definition at line 233 of file gd32f3x0_rcu.h.

#define RCU_RSTSCK REG32(RCU + 0x24U)

reset source /clock register

Definition at line 30 of file gd32f3x0_rcu.h.

#define RCU_RSTSCK_EPRSTF BIT(26)

external pin reset flag

Definition at line 171 of file gd32f3x0_rcu.h.

#define RCU_RSTSCK_FWDGTRSTF BIT(29)

free watchdog timer reset flag

Definition at line 174 of file gd32f3x0_rcu.h.

#define RCU_RSTSCK_IRC40KEN BIT(0)

IRC40K enable

Definition at line 166 of file gd32f3x0_rcu.h.

#define RCU_RSTSCK_IRC40KSTB BIT(1)

IRC40K stabilization

Definition at line 167 of file gd32f3x0_rcu.h.

#define RCU_RSTSCK_LPRSTF BIT(31)

low-power reset flag

Definition at line 176 of file gd32f3x0_rcu.h.

#define RCU_RSTSCK_OBLRSTF BIT(25)

option byte loader reset flag

Definition at line 170 of file gd32f3x0_rcu.h.

#define RCU_RSTSCK_PORRSTF BIT(27)

power reset flag

Definition at line 172 of file gd32f3x0_rcu.h.

#define RCU_RSTSCK_RSTFC BIT(24)

reset flag clear

Definition at line 169 of file gd32f3x0_rcu.h.

#define RCU_RSTSCK_SWRSTF BIT(28)

software reset flag

Definition at line 173 of file gd32f3x0_rcu.h.

#define RCU_RSTSCK_V12RSTF BIT(23)

V12 domain power reset flag

Definition at line 168 of file gd32f3x0_rcu.h.

#define RCU_RSTSCK_WWDGTRSTF BIT(30)

window watchdog timer reset flag

Definition at line 175 of file gd32f3x0_rcu.h.

#define RCU_RTCSRC_HXTAL_DIV32 BDCTL_RTCSRC(3)

HXTAL/32 selected as RTC source clock

Definition at line 636 of file gd32f3x0_rcu.h.

#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2)

IRC40K selected as RTC source clock

Definition at line 635 of file gd32f3x0_rcu.h.

#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1)

LXTAL selected as RTC source clock

Definition at line 634 of file gd32f3x0_rcu.h.

#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0)

no clock selected

Definition at line 633 of file gd32f3x0_rcu.h.

#define RCU_SCSS_HXTAL CFG0_SCSS(1)

system clock source select HXTAL

Definition at line 472 of file gd32f3x0_rcu.h.

#define RCU_SCSS_IRC8M CFG0_SCSS(0)

system clock source select IRC8M

Definition at line 471 of file gd32f3x0_rcu.h.

#define RCU_SCSS_PLL CFG0_SCSS(2)

system clock source select PLL

Definition at line 473 of file gd32f3x0_rcu.h.

#define RCU_USART0SRC_CKAPB2 CFG2_USART0SEL(0)

CK_USART0 select CK_APB2

Definition at line 659 of file gd32f3x0_rcu.h.

#define RCU_USART0SRC_CKSYS CFG2_USART0SEL(1)

CK_USART0 select CK_SYS

Definition at line 660 of file gd32f3x0_rcu.h.

#define RCU_USART0SRC_IRC8M CFG2_USART0SEL(3)

CK_USART0 select IRC8M

Definition at line 662 of file gd32f3x0_rcu.h.

#define RCU_USART0SRC_LXTAL CFG2_USART0SEL(2)

CK_USART0 select LXTAL

Definition at line 661 of file gd32f3x0_rcu.h.

#define RCU_USBFS_CKPLL_DIV1 CFG0_USBFSPSC(1)

USBFS clock prescaler select CK_PLL

Definition at line 591 of file gd32f3x0_rcu.h.

#define RCU_USBFS_CKPLL_DIV1_5 CFG0_USBFSPSC(0)

USBFS clock prescaler select CK_PLL/1.5

Definition at line 590 of file gd32f3x0_rcu.h.

#define RCU_USBFS_CKPLL_DIV2 CFG0_USBFSPSC(3)

USBFS clock prescaler select CK_PLL/2

Definition at line 593 of file gd32f3x0_rcu.h.

#define RCU_USBFS_CKPLL_DIV2_5 CFG0_USBFSPSC(2)

USBFS clock prescaler select CK_PLL/2.5

Definition at line 592 of file gd32f3x0_rcu.h.

#define RCU_USBFS_CKPLL_DIV3 RCU_CFG2_USBFSPSC2

USBFS clock prescaler select CK_PLL/3

Definition at line 594 of file gd32f3x0_rcu.h.

#define RCU_USBFS_CKPLL_DIV3_5 (CFG0_USBFSPSC(1)|RCU_CFG2_USBFSPSC2)

USBFS clock prescaler select CK_PLL/3.5

Definition at line 595 of file gd32f3x0_rcu.h.

#define RCU_VKEY REG32(RCU + 0x100U)

voltage key register

Definition at line 39 of file gd32f3x0_rcu.h.

#define RCU_VKEY_KEY BITS(0,31)

key of RCU_DSV register

Definition at line 226 of file gd32f3x0_rcu.h.

#define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4D)

Definition at line 237 of file gd32f3x0_rcu.h.

Enumeration Type Documentation

enum rcu_adc_clock_enum
Enumerator
RCU_ADCCK_IRC28M_DIV2 | ADC clock source select IRC28M/2
RCU_ADCCK_IRC28M | ADC clock source select IRC28M
RCU_ADCCK_APB2_DIV2 | ADC clock source select APB2/2
RCU_ADCCK_APB2_DIV3 | ADC clock source select APB2/3
RCU_ADCCK_APB2_DIV4 | ADC clock source select APB2/4
RCU_ADCCK_APB2_DIV5 | ADC clock source select APB2/5
RCU_ADCCK_APB2_DIV6 | ADC clock source select APB2/6
RCU_ADCCK_APB2_DIV7 | ADC clock source select APB2/7
RCU_ADCCK_APB2_DIV8 | ADC clock source select APB2/8
RCU_ADCCK_APB2_DIV9 | ADC clock source select APB2/9

Definition at line 425 of file gd32f3x0_rcu.h.

426 {
427 RCU_ADCCK_IRC28M_DIV2 = 0U,
428 RCU_ADCCK_IRC28M,
429 RCU_ADCCK_APB2_DIV2,
430 RCU_ADCCK_APB2_DIV3,
431 RCU_ADCCK_APB2_DIV4,
432 RCU_ADCCK_APB2_DIV5,
433 RCU_ADCCK_APB2_DIV6,
434 RCU_ADCCK_APB2_DIV7,
435 RCU_ADCCK_APB2_DIV8,
436 RCU_ADCCK_APB2_DIV9
437 }rcu_adc_clock_enum;
RCU_ADCCK_APB2_DIV3
Definition: gd32f3x0_rcu.h:430
RCU_ADCCK_APB2_DIV6
Definition: gd32f3x0_rcu.h:433
RCU_ADCCK_IRC28M
Definition: gd32f3x0_rcu.h:428
RCU_ADCCK_APB2_DIV5
Definition: gd32f3x0_rcu.h:432
RCU_ADCCK_APB2_DIV9
Definition: gd32f3x0_rcu.h:436
RCU_ADCCK_APB2_DIV7
Definition: gd32f3x0_rcu.h:434
rcu_adc_clock_enum
rcu_adc_clock_enum
Definition: gd32f3x0_rcu.h:425
RCU_ADCCK_APB2_DIV8
Definition: gd32f3x0_rcu.h:435
RCU_ADCCK_IRC28M_DIV2
Definition: gd32f3x0_rcu.h:427
RCU_ADCCK_APB2_DIV4
Definition: gd32f3x0_rcu.h:431
RCU_ADCCK_APB2_DIV2
Definition: gd32f3x0_rcu.h:429
enum rcu_clock_freq_enum
Enumerator
CK_SYS | system clock
CK_AHB | AHB clock
CK_APB1 | APB1 clock
CK_APB2 | APB2 clock
CK_ADC | ADC clock
CK_CEC | CEC clock
CK_USART | USART clock

Definition at line 452 of file gd32f3x0_rcu.h.

453 {
454 CK_SYS = 0U,
455 CK_AHB,
456 CK_APB1,
457 CK_APB2,
458 CK_ADC,
459 CK_CEC,
460 CK_USART
461 }rcu_clock_freq_enum;
CK_APB1
Definition: gd32f3x0_rcu.h:456
rcu_clock_freq_enum
rcu_clock_freq_enum
Definition: gd32f3x0_rcu.h:452
CK_ADC
Definition: gd32f3x0_rcu.h:458
CK_USART
Definition: gd32f3x0_rcu.h:460
CK_SYS
Definition: gd32f3x0_rcu.h:454
CK_AHB
Definition: gd32f3x0_rcu.h:455
CK_APB2
Definition: gd32f3x0_rcu.h:457
CK_CEC
Definition: gd32f3x0_rcu.h:459
enum rcu_flag_enum
Enumerator
RCU_FLAG_IRC40KSTB | IRC40K stabilization flags
RCU_FLAG_LXTALSTB | LXTAL stabilization flags
RCU_FLAG_IRC8MSTB | IRC8M stabilization flags
RCU_FLAG_HXTALSTB | HXTAL stabilization flags
RCU_FLAG_PLLSTB | PLL stabilization flags
RCU_FLAG_IRC28MSTB | IRC28M stabilization flags
RCU_FLAG_IRC48MSTB | IRC48M stabilization flags
RCU_FLAG_V12RST | V12 reset flags
RCU_FLAG_OBLRST | OBL reset flags
RCU_FLAG_EPRST | EPR reset flags
RCU_FLAG_PORRST | power reset flags
RCU_FLAG_SWRST | SW reset flags
RCU_FLAG_FWDGTRST | FWDGT reset flags
RCU_FLAG_WWDGTRST | WWDGT reset flags
RCU_FLAG_LPRST | LP reset flags

Definition at line 366 of file gd32f3x0_rcu.h.

367 {
368 RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_RSTSCK, 1U),
369 RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_BDCTL, 1U),
370 RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_CTL0, 1U),
371 RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_CTL0, 17U),
372 RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_CTL0, 25U),
373 RCU_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_CTL1, 1U),
374 RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDCTL, 17U),
376 RCU_FLAG_V12RST = RCU_REGIDX_BIT(IDX_RSTSCK, 23U),
377 RCU_FLAG_OBLRST = RCU_REGIDX_BIT(IDX_RSTSCK, 25U),
378 RCU_FLAG_EPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 26U),
379 RCU_FLAG_PORRST = RCU_REGIDX_BIT(IDX_RSTSCK, 27U),
380 RCU_FLAG_SWRST = RCU_REGIDX_BIT(IDX_RSTSCK, 28U),
381 RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 29U),
382 RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 30U),
383 RCU_FLAG_LPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 31U)
384 }rcu_flag_enum;
IDX_RSTSCK
Definition: gd32f3x0_rcu.h:258
RCU_FLAG_HXTALSTB
Definition: gd32f3x0_rcu.h:371
RCU_FLAG_PORRST
Definition: gd32f3x0_rcu.h:379
IDX_ADDCTL
Definition: gd32f3x0_rcu.h:256
RCU_FLAG_WWDGTRST
Definition: gd32f3x0_rcu.h:382
RCU_FLAG_IRC40KSTB
Definition: gd32f3x0_rcu.h:368
IDX_CTL1
Definition: gd32f3x0_rcu.h:255
RCU_FLAG_IRC28MSTB
Definition: gd32f3x0_rcu.h:373
RCU_FLAG_OBLRST
Definition: gd32f3x0_rcu.h:377
RCU_FLAG_LXTALSTB
Definition: gd32f3x0_rcu.h:369
RCU_FLAG_SWRST
Definition: gd32f3x0_rcu.h:380
RCU_FLAG_PLLSTB
Definition: gd32f3x0_rcu.h:372
RCU_FLAG_LPRST
Definition: gd32f3x0_rcu.h:383
RCU_FLAG_V12RST
Definition: gd32f3x0_rcu.h:376
RCU_FLAG_FWDGTRST
Definition: gd32f3x0_rcu.h:381
rcu_flag_enum
rcu_flag_enum
Definition: gd32f3x0_rcu.h:366
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f3x0_rcu.h:233
RCU_FLAG_IRC8MSTB
Definition: gd32f3x0_rcu.h:370
RCU_FLAG_EPRST
Definition: gd32f3x0_rcu.h:378
IDX_CTL0
Definition: gd32f3x0_rcu.h:253
IDX_BDCTL
Definition: gd32f3x0_rcu.h:254
RCU_FLAG_IRC48MSTB
Definition: gd32f3x0_rcu.h:374
enum rcu_int_enum
Enumerator
RCU_INT_IRC40KSTB | IRC40K stabilization interrupt
RCU_INT_LXTALSTB | LXTAL stabilization interrupt
RCU_INT_IRC8MSTB | IRC8M stabilization interrupt
RCU_INT_HXTALSTB | HXTAL stabilization interrupt
RCU_INT_PLLSTB | PLL stabilization interrupt
RCU_INT_IRC28MSTB | IRC28M stabilization interrupt
RCU_INT_IRC48MSTB | IRC48M stabilization interrupt

Definition at line 413 of file gd32f3x0_rcu.h.

414 {
415 RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 8U),
416 RCU_INT_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 9U),
417 RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 10U),
418 RCU_INT_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 11U),
419 RCU_INT_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 12U),
420 RCU_INT_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 13U),
421 RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDINT, 14U)
422 }rcu_int_enum;
RCU_INT_IRC48MSTB
Definition: gd32f3x0_rcu.h:421
RCU_INT_LXTALSTB
Definition: gd32f3x0_rcu.h:416
RCU_INT_IRC28MSTB
Definition: gd32f3x0_rcu.h:420
RCU_INT_IRC40KSTB
Definition: gd32f3x0_rcu.h:415
rcu_int_enum
rcu_int_enum
Definition: gd32f3x0_rcu.h:413
RCU_INT_IRC8MSTB
Definition: gd32f3x0_rcu.h:417
IDX_ADDINT
Definition: gd32f3x0_rcu.h:261
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f3x0_rcu.h:233
RCU_INT_HXTALSTB
Definition: gd32f3x0_rcu.h:418
IDX_INT
Definition: gd32f3x0_rcu.h:260
RCU_INT_PLLSTB
Definition: gd32f3x0_rcu.h:419
enum rcu_int_flag_clear_enum
Enumerator
RCU_INT_FLAG_IRC40KSTB_CLR | IRC40K stabilization interrupt flags clear
RCU_INT_FLAG_LXTALSTB_CLR | LXTAL stabilization interrupt flags clear
RCU_INT_FLAG_IRC8MSTB_CLR | IRC8M stabilization interrupt flags clear
RCU_INT_FLAG_HXTALSTB_CLR | HXTAL stabilization interrupt flags clear
RCU_INT_FLAG_PLLSTB_CLR | PLL stabilization interrupt flags clear
RCU_INT_FLAG_IRC28MSTB_CLR | IRC28M stabilization interrupt flags clear
RCU_INT_FLAG_CKM_CLR | CKM interrupt flags clear
RCU_INT_FLAG_IRC48MSTB_CLR | IRC48M stabilization interrupt flag clear

Definition at line 400 of file gd32f3x0_rcu.h.

401 {
402 RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 16U),
403 RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 17U),
404 RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 18U),
405 RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 19U),
406 RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 20U),
407 RCU_INT_FLAG_IRC28MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 21U),
408 RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(IDX_INT, 23U),
409 RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(IDX_ADDCTL, 22U)
410 }rcu_int_flag_clear_enum;
RCU_INT_FLAG_IRC48MSTB_CLR
Definition: gd32f3x0_rcu.h:409
IDX_ADDCTL
Definition: gd32f3x0_rcu.h:256
RCU_INT_FLAG_HXTALSTB_CLR
Definition: gd32f3x0_rcu.h:405
RCU_INT_FLAG_IRC8MSTB_CLR
Definition: gd32f3x0_rcu.h:404
RCU_INT_FLAG_IRC40KSTB_CLR
Definition: gd32f3x0_rcu.h:402
RCU_INT_FLAG_PLLSTB_CLR
Definition: gd32f3x0_rcu.h:406
RCU_INT_FLAG_CKM_CLR
Definition: gd32f3x0_rcu.h:408
RCU_INT_FLAG_IRC28MSTB_CLR
Definition: gd32f3x0_rcu.h:407
rcu_int_flag_clear_enum
rcu_int_flag_clear_enum
Definition: gd32f3x0_rcu.h:400
RCU_INT_FLAG_LXTALSTB_CLR
Definition: gd32f3x0_rcu.h:403
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f3x0_rcu.h:233
IDX_INT
Definition: gd32f3x0_rcu.h:260
enum rcu_int_flag_enum
Enumerator
RCU_INT_FLAG_IRC40KSTB | IRC40K stabilization interrupt flag
RCU_INT_FLAG_LXTALSTB | LXTAL stabilization interrupt flag
RCU_INT_FLAG_IRC8MSTB | IRC8M stabilization interrupt flag
RCU_INT_FLAG_HXTALSTB | HXTAL stabilization interrupt flag
RCU_INT_FLAG_PLLSTB | PLL stabilization interrupt flag
RCU_INT_FLAG_IRC28MSTB | IRC28M stabilization interrupt flag
RCU_INT_FLAG_CKM | CKM interrupt flag
RCU_INT_FLAG_IRC48MSTB | IRC48M stabilization interrupt flag

Definition at line 387 of file gd32f3x0_rcu.h.

388 {
389 RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 0U),
390 RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 1U),
391 RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 2U),
392 RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 3U),
393 RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 4U),
394 RCU_INT_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 5U),
395 RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(IDX_INT, 7U),
396 RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDCTL, 6U)
397 }rcu_int_flag_enum;
RCU_INT_FLAG_HXTALSTB
Definition: gd32f3x0_rcu.h:392
RCU_INT_FLAG_IRC28MSTB
Definition: gd32f3x0_rcu.h:394
RCU_INT_FLAG_PLLSTB
Definition: gd32f3x0_rcu.h:393
IDX_ADDCTL
Definition: gd32f3x0_rcu.h:256
RCU_INT_FLAG_IRC40KSTB
Definition: gd32f3x0_rcu.h:389
RCU_INT_FLAG_CKM
Definition: gd32f3x0_rcu.h:395
RCU_INT_FLAG_IRC48MSTB
Definition: gd32f3x0_rcu.h:396
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f3x0_rcu.h:233
rcu_int_flag_enum
rcu_int_flag_enum
Definition: gd32f3x0_rcu.h:387
RCU_INT_FLAG_IRC8MSTB
Definition: gd32f3x0_rcu.h:391
IDX_INT
Definition: gd32f3x0_rcu.h:260
RCU_INT_FLAG_LXTALSTB
Definition: gd32f3x0_rcu.h:390
enum rcu_osci_type_enum
Enumerator
RCU_HXTAL | HXTAL
RCU_LXTAL | LXTAL
RCU_IRC8M | IRC8M
RCU_IRC28M | IRC28M
RCU_IRC48M | IRC48M
RCU_IRC40K | IRC40K
RCU_PLL_CK | PLL

Definition at line 440 of file gd32f3x0_rcu.h.

441 {
442 RCU_HXTAL = RCU_REGIDX_BIT(IDX_CTL0, 16U),
443 RCU_LXTAL = RCU_REGIDX_BIT(IDX_BDCTL, 0U),
444 RCU_IRC8M = RCU_REGIDX_BIT(IDX_CTL0, 0U),
445 RCU_IRC28M = RCU_REGIDX_BIT(IDX_CTL1, 0U),
446 RCU_IRC48M = RCU_REGIDX_BIT(IDX_ADDCTL, 16U),
447 RCU_IRC40K = RCU_REGIDX_BIT(IDX_RSTSCK, 0U),
448 RCU_PLL_CK = RCU_REGIDX_BIT(IDX_CTL0, 24U)
449 }rcu_osci_type_enum;
IDX_RSTSCK
Definition: gd32f3x0_rcu.h:258
IDX_ADDCTL
Definition: gd32f3x0_rcu.h:256
RCU_IRC48M
Definition: gd32f3x0_rcu.h:446
IDX_CTL1
Definition: gd32f3x0_rcu.h:255
RCU_HXTAL
Definition: gd32f3x0_rcu.h:442
RCU_IRC28M
Definition: gd32f3x0_rcu.h:445
RCU_IRC8M
Definition: gd32f3x0_rcu.h:444
RCU_PLL_CK
Definition: gd32f3x0_rcu.h:448
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f3x0_rcu.h:233
RCU_LXTAL
Definition: gd32f3x0_rcu.h:443
RCU_IRC40K
Definition: gd32f3x0_rcu.h:447
rcu_osci_type_enum
rcu_osci_type_enum
Definition: gd32f3x0_rcu.h:440
IDX_CTL0
Definition: gd32f3x0_rcu.h:253
IDX_BDCTL
Definition: gd32f3x0_rcu.h:254
enum rcu_periph_enum
Enumerator
RCU_DMA | DMA clock
RCU_CRC | CRC clock
RCU_GPIOA | GPIOA clock
RCU_GPIOB | GPIOB clock
RCU_GPIOC | GPIOC clock
RCU_GPIOD | GPIOD clock
RCU_GPIOF | GPIOF clock
RCU_TSI | TSI clock
RCU_CFGCMP | CFGCMP clock
RCU_ADC | ADC clock
RCU_TIMER0 | TIMER0 clock
RCU_SPI0 | SPI0 clock
RCU_USART0 | USART0 clock
RCU_TIMER14 | TIMER14 clock
RCU_TIMER15 | TIMER15 clock
RCU_TIMER16 | TIMER16 clock
RCU_TIMER1 | TIMER1 clock
RCU_TIMER2 | TIMER2 clock
RCU_TIMER13 | TIMER13 clock
RCU_WWDGT | WWDGT clock
RCU_SPI1 | SPI1 clock
RCU_SPI2 | SPI2 clock
RCU_USART1 | USART1 clock
RCU_I2C0 | I2C0 clock
RCU_I2C1 | I2C1 clock
RCU_PMU | PMU clock
RCU_RTC | RTC clock
RCU_I2C2 | I2C2 clock
RCU_CTC | CTC clock

Definition at line 268 of file gd32f3x0_rcu.h.

269 {
270 /* AHB peripherals */
271 RCU_DMA = RCU_REGIDX_BIT(IDX_AHBEN, 0U),
272 RCU_CRC = RCU_REGIDX_BIT(IDX_AHBEN, 6U),
273 RCU_GPIOA = RCU_REGIDX_BIT(IDX_AHBEN, 17U),
274 RCU_GPIOB = RCU_REGIDX_BIT(IDX_AHBEN, 18U),
275 RCU_GPIOC = RCU_REGIDX_BIT(IDX_AHBEN, 19U),
276 RCU_GPIOD = RCU_REGIDX_BIT(IDX_AHBEN, 20U),
277 RCU_GPIOF = RCU_REGIDX_BIT(IDX_AHBEN, 22U),
278 RCU_TSI = RCU_REGIDX_BIT(IDX_AHBEN, 24U),
280 /* APB2 peripherals */
281 RCU_CFGCMP = RCU_REGIDX_BIT(IDX_APB2EN, 0U),
282 RCU_ADC = RCU_REGIDX_BIT(IDX_APB2EN, 9U),
283 RCU_TIMER0 = RCU_REGIDX_BIT(IDX_APB2EN, 11U),
284 RCU_SPI0 = RCU_REGIDX_BIT(IDX_APB2EN, 12U),
285 RCU_USART0 = RCU_REGIDX_BIT(IDX_APB2EN, 14U),
286 RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U),
287 RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U),
288 RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U),
290 /* APB1 peripherals */
291 RCU_TIMER1 = RCU_REGIDX_BIT(IDX_APB1EN, 0U),
292 RCU_TIMER2 = RCU_REGIDX_BIT(IDX_APB1EN, 1U),
293 RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U),
294 RCU_WWDGT = RCU_REGIDX_BIT(IDX_APB1EN, 11U),
295 RCU_SPI1 = RCU_REGIDX_BIT(IDX_APB1EN, 14U),
296 RCU_SPI2 = RCU_REGIDX_BIT(IDX_APB1EN, 15U),
297 RCU_USART1 = RCU_REGIDX_BIT(IDX_APB1EN, 17U),
298 RCU_I2C0 = RCU_REGIDX_BIT(IDX_APB1EN, 21U),
299 RCU_I2C1 = RCU_REGIDX_BIT(IDX_APB1EN, 22U),
300 RCU_PMU = RCU_REGIDX_BIT(IDX_APB1EN, 28U),
301 #if defined(GD32F350)
302 RCU_DAC = RCU_REGIDX_BIT(IDX_APB1EN, 29U),
303 RCU_CEC = RCU_REGIDX_BIT(IDX_APB1EN, 30U),
304 RCU_TIMER5 = RCU_REGIDX_BIT(IDX_APB1EN, 4U),
305 RCU_USBFS = RCU_REGIDX_BIT(IDX_AHBEN, 12U),
306 #endif /* GD32F350 */
307 RCU_RTC = RCU_REGIDX_BIT(IDX_BDCTL, 15U),
309 /* RCU_ADDAPB1EN */
310 RCU_I2C2 = RCU_REGIDX_BIT(IDX_ADDAPB1EN, 0U),
311 RCU_CTC = RCU_REGIDX_BIT(IDX_ADDAPB1EN, 27U)
312 }rcu_periph_enum;
RCU_TIMER0
Definition: gd32f3x0_rcu.h:283
RCU_DMA
Definition: gd32f3x0_rcu.h:271
RCU_GPIOF
Definition: gd32f3x0_rcu.h:277
RCU_CFGCMP
Definition: gd32f3x0_rcu.h:281
RCU_I2C2
Definition: gd32f3x0_rcu.h:310
RCU_TIMER2
Definition: gd32f3x0_rcu.h:292
RCU_TIMER16
Definition: gd32f3x0_rcu.h:288
RCU_SPI0
Definition: gd32f3x0_rcu.h:284
RCU_TIMER15
Definition: gd32f3x0_rcu.h:287
RCU_GPIOB
Definition: gd32f3x0_rcu.h:274
IDX_ADDAPB1EN
Definition: gd32f3x0_rcu.h:246
RCU_CRC
Definition: gd32f3x0_rcu.h:272
RCU_TIMER14
Definition: gd32f3x0_rcu.h:286
RCU_I2C1
Definition: gd32f3x0_rcu.h:299
RCU_WWDGT
Definition: gd32f3x0_rcu.h:294
IDX_APB2EN
Definition: gd32f3x0_rcu.h:244
IDX_APB1EN
Definition: gd32f3x0_rcu.h:245
RCU_SPI2
Definition: gd32f3x0_rcu.h:296
RCU_I2C0
Definition: gd32f3x0_rcu.h:298
rcu_periph_enum
rcu_periph_enum
Definition: gd32f3x0_rcu.h:268
IDX_AHBEN
Definition: gd32f3x0_rcu.h:243
RCU_USART0
Definition: gd32f3x0_rcu.h:285
RCU_PMU
Definition: gd32f3x0_rcu.h:300
RCU_TIMER1
Definition: gd32f3x0_rcu.h:291
RCU_RTC
Definition: gd32f3x0_rcu.h:307
RCU_USART1
Definition: gd32f3x0_rcu.h:297
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f3x0_rcu.h:233
RCU_ADC
Definition: gd32f3x0_rcu.h:282
RCU_GPIOC
Definition: gd32f3x0_rcu.h:275
RCU_TIMER13
Definition: gd32f3x0_rcu.h:293
RCU_CTC
Definition: gd32f3x0_rcu.h:311
RCU_TSI
Definition: gd32f3x0_rcu.h:278
RCU_SPI1
Definition: gd32f3x0_rcu.h:295
RCU_GPIOA
Definition: gd32f3x0_rcu.h:273
RCU_GPIOD
Definition: gd32f3x0_rcu.h:276
IDX_BDCTL
Definition: gd32f3x0_rcu.h:254
enum rcu_periph_reset_enum
Enumerator
RCU_GPIOARST | GPIOA reset
RCU_GPIOBRST | GPIOB reset
RCU_GPIOCRST | GPIOC reset
RCU_GPIODRST | GPIOD reset
RCU_GPIOFRST | GPIOF reset
RCU_TSIRST | TSI reset
RCU_CFGCMPRST | CFGCMP reset
RCU_ADCRST | ADC reset
RCU_TIMER0RST | TIMER0 reset
RCU_SPI0RST | SPI0 reset
RCU_USART0RST | USART0 reset
RCU_TIMER14RST | TIMER14 reset
RCU_TIMER15RST | TIMER15 reset
RCU_TIMER16RST | TIMER16 reset
RCU_TIMER1RST | TIMER1 reset
RCU_TIMER2RST | TIMER2 reset
RCU_TIMER13RST | TIMER13 reset
RCU_WWDGTRST | WWDGT reset
RCU_SPI1RST | SPI1 reset
RCU_SPI2RST | SPI2 reset
RCU_USART1RST | USART1 reset
RCU_I2C0RST | I2C0 reset
RCU_I2C1RST | I2C1 reset
RCU_PMURST | PMU reset
RCU_I2C2RST | I2C2 reset
RCU_CTCRST | CTC reset

Definition at line 323 of file gd32f3x0_rcu.h.

324 {
325 /* AHB peripherals reset */
326 RCU_GPIOARST = RCU_REGIDX_BIT(IDX_AHBRST, 17U),
327 RCU_GPIOBRST = RCU_REGIDX_BIT(IDX_AHBRST, 18U),
328 RCU_GPIOCRST = RCU_REGIDX_BIT(IDX_AHBRST, 19U),
329 RCU_GPIODRST = RCU_REGIDX_BIT(IDX_AHBRST, 20U),
330 RCU_GPIOFRST = RCU_REGIDX_BIT(IDX_AHBRST, 22U),
331 RCU_TSIRST = RCU_REGIDX_BIT(IDX_AHBRST, 24U),
333 /* APB2 peripherals reset */
334 RCU_CFGCMPRST = RCU_REGIDX_BIT(IDX_APB2RST, 0U),
335 RCU_ADCRST = RCU_REGIDX_BIT(IDX_APB2RST, 9U),
336 RCU_TIMER0RST = RCU_REGIDX_BIT(IDX_APB2RST, 11U),
337 RCU_SPI0RST = RCU_REGIDX_BIT(IDX_APB2RST, 12U),
338 RCU_USART0RST = RCU_REGIDX_BIT(IDX_APB2RST, 14U),
339 RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U),
340 RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U),
341 RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U),
343 /* APB1 peripherals reset */
344 RCU_TIMER1RST = RCU_REGIDX_BIT(IDX_APB1RST, 0U),
345 RCU_TIMER2RST = RCU_REGIDX_BIT(IDX_APB1RST, 1U),
346 RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U),
347 RCU_WWDGTRST = RCU_REGIDX_BIT(IDX_APB1RST, 11U),
348 RCU_SPI1RST = RCU_REGIDX_BIT(IDX_APB1RST, 14U),
349 RCU_SPI2RST = RCU_REGIDX_BIT(IDX_APB1RST, 15U),
350 RCU_USART1RST = RCU_REGIDX_BIT(IDX_APB1RST, 17U),
351 RCU_I2C0RST = RCU_REGIDX_BIT(IDX_APB1RST, 21U),
352 RCU_I2C1RST = RCU_REGIDX_BIT(IDX_APB1RST, 22U),
353 RCU_PMURST = RCU_REGIDX_BIT(IDX_APB1RST, 28U),
354 #if defined(GD32F350)
355 RCU_DACRST = RCU_REGIDX_BIT(IDX_APB1RST, 29U),
356 RCU_CECRST = RCU_REGIDX_BIT(IDX_APB1RST, 30U),
357 RCU_TIMER5RST = RCU_REGIDX_BIT(IDX_APB1RST, 4U),
358 RCU_USBFSRST = RCU_REGIDX_BIT(IDX_AHBRST, 12U),
359 #endif /* GD32F350 */
360 /* RCU_ADDAPB1RST */
361 RCU_I2C2RST = RCU_REGIDX_BIT(IDX_ADDAPB1RST, 0U),
362 RCU_CTCRST = RCU_REGIDX_BIT(IDX_ADDAPB1RST, 27U),
363 }rcu_periph_reset_enum;
RCU_I2C1RST
Definition: gd32f3x0_rcu.h:352
RCU_GPIOCRST
Definition: gd32f3x0_rcu.h:328
RCU_USART0RST
Definition: gd32f3x0_rcu.h:338
RCU_GPIOBRST
Definition: gd32f3x0_rcu.h:327
RCU_TSIRST
Definition: gd32f3x0_rcu.h:331
IDX_APB2RST
Definition: gd32f3x0_rcu.h:249
RCU_USART1RST
Definition: gd32f3x0_rcu.h:350
RCU_I2C0RST
Definition: gd32f3x0_rcu.h:351
RCU_SPI0RST
Definition: gd32f3x0_rcu.h:337
RCU_TIMER1RST
Definition: gd32f3x0_rcu.h:344
RCU_TIMER13RST
Definition: gd32f3x0_rcu.h:346
RCU_CTCRST
Definition: gd32f3x0_rcu.h:362
rcu_periph_reset_enum
rcu_periph_reset_enum
Definition: gd32f3x0_rcu.h:323
RCU_TIMER14RST
Definition: gd32f3x0_rcu.h:339
RCU_CFGCMPRST
Definition: gd32f3x0_rcu.h:334
RCU_ADCRST
Definition: gd32f3x0_rcu.h:335
RCU_I2C2RST
Definition: gd32f3x0_rcu.h:361
RCU_GPIOARST
Definition: gd32f3x0_rcu.h:326
RCU_SPI1RST
Definition: gd32f3x0_rcu.h:348
IDX_ADDAPB1RST
Definition: gd32f3x0_rcu.h:251
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f3x0_rcu.h:233
IDX_APB1RST
Definition: gd32f3x0_rcu.h:250
RCU_TIMER0RST
Definition: gd32f3x0_rcu.h:336
IDX_AHBRST
Definition: gd32f3x0_rcu.h:248
RCU_GPIODRST
Definition: gd32f3x0_rcu.h:329
RCU_WWDGTRST
Definition: gd32f3x0_rcu.h:347
RCU_SPI2RST
Definition: gd32f3x0_rcu.h:349
RCU_TIMER15RST
Definition: gd32f3x0_rcu.h:340
RCU_PMURST
Definition: gd32f3x0_rcu.h:353
RCU_TIMER16RST
Definition: gd32f3x0_rcu.h:341
RCU_GPIOFRST
Definition: gd32f3x0_rcu.h:330
RCU_TIMER2RST
Definition: gd32f3x0_rcu.h:345
enum rcu_periph_sleep_enum
Enumerator
RCU_SRAM_SLP | SRAM clock
RCU_FMC_SLP | FMC clock

Definition at line 315 of file gd32f3x0_rcu.h.

316 {
317 /* AHB peripherals */
318 RCU_SRAM_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 2U),
319 RCU_FMC_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 4U),
320 }rcu_periph_sleep_enum;
RCU_SRAM_SLP
Definition: gd32f3x0_rcu.h:318
RCU_FMC_SLP
Definition: gd32f3x0_rcu.h:319
IDX_AHBEN
Definition: gd32f3x0_rcu.h:243
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f3x0_rcu.h:233
rcu_periph_sleep_enum
rcu_periph_sleep_enum
Definition: gd32f3x0_rcu.h:315
enum reg_idx
Enumerator
IDX_AHBEN
IDX_APB2EN
IDX_APB1EN
IDX_ADDAPB1EN
IDX_AHBRST
IDX_APB2RST
IDX_APB1RST
IDX_ADDAPB1RST
IDX_CTL0
IDX_BDCTL
IDX_CTL1
IDX_ADDCTL
IDX_RSTSCK
IDX_INT
IDX_ADDINT
IDX_CFG0
IDX_CFG2

Definition at line 240 of file gd32f3x0_rcu.h.

241 {
242 /* peripherals enable */
243 IDX_AHBEN = 0x14U,
244 IDX_APB2EN = 0x18U,
245 IDX_APB1EN = 0x1CU,
246 IDX_ADDAPB1EN = 0xF8U,
247 /* peripherals reset */
248 IDX_AHBRST = 0x28U,
249 IDX_APB2RST = 0x0CU,
250 IDX_APB1RST = 0x10U,
251 IDX_ADDAPB1RST = 0xFCU,
252 /* clock stabilization */
253 IDX_CTL0 = 0x00U,
254 IDX_BDCTL = 0x20U,
255 IDX_CTL1 = 0x34U,
256 IDX_ADDCTL = 0xC0U,
257 /* peripheral reset */
258 IDX_RSTSCK = 0x24U,
259 /* clock stabilization and stuck interrupt */
260 IDX_INT = 0x08U,
261 IDX_ADDINT = 0xCCU,
262 /* configuration register */
263 IDX_CFG0 = 0x04U,
264 IDX_CFG2 = 0x30U
265 }reg_idx;
IDX_RSTSCK
Definition: gd32f3x0_rcu.h:258
IDX_CFG2
Definition: gd32f3x0_rcu.h:264
IDX_ADDCTL
Definition: gd32f3x0_rcu.h:256
IDX_CFG0
Definition: gd32f3x0_rcu.h:263
IDX_ADDAPB1EN
Definition: gd32f3x0_rcu.h:246
IDX_APB2RST
Definition: gd32f3x0_rcu.h:249
IDX_CTL1
Definition: gd32f3x0_rcu.h:255
IDX_APB2EN
Definition: gd32f3x0_rcu.h:244
IDX_APB1EN
Definition: gd32f3x0_rcu.h:245
reg_idx
reg_idx
Definition: gd32f3x0_rcu.h:240
IDX_AHBEN
Definition: gd32f3x0_rcu.h:243
IDX_ADDINT
Definition: gd32f3x0_rcu.h:261
IDX_ADDAPB1RST
Definition: gd32f3x0_rcu.h:251
IDX_APB1RST
Definition: gd32f3x0_rcu.h:250
IDX_AHBRST
Definition: gd32f3x0_rcu.h:248
IDX_CTL0
Definition: gd32f3x0_rcu.h:253
IDX_INT
Definition: gd32f3x0_rcu.h:260
IDX_BDCTL
Definition: gd32f3x0_rcu.h:254

Function Documentation

void rcu_adc_clock_config ( rcu_adc_clock_enum ck_adc )

configure the ADC clock prescaler selection

Parameters
[in] ck_adc ADC clock prescaler selection, refer to rcu_adc_clock_enum
  • RCU_ADCCK_IRC28M_DIV2: select CK_IRC28M/2 as CK_ADC
  • RCU_ADCCK_IRC28M: select CK_IRC28M as CK_ADC
  • RCU_ADCCK_APB2_DIV2: select CK_APB2/2 as CK_ADC
  • RCU_ADCCK_APB2_DIV3: select CK_APB2/3 as CK_ADC
  • RCU_ADCCK_APB2_DIV4: select CK_APB2/4 as CK_ADC
  • RCU_ADCCK_APB2_DIV5: select CK_APB2/5 as CK_ADC
  • RCU_ADCCK_APB2_DIV6: select CK_APB2/6 as CK_ADC
  • RCU_ADCCK_APB2_DIV7: select CK_APB2/7 as CK_ADC
  • RCU_ADCCK_APB2_DIV8: select CK_APB2/8 as CK_ADC
  • RCU_ADCCK_APB2_DIV9: select CK_APB2/9 as CK_ADC
[out] none
Return values
none

Definition at line 318 of file gd32f3x0_rcu.c.

319 {
320 /* reset the ADCPSC, ADCSEL, IRC28MDIV bits */
321 RCU_CFG0 &= ~RCU_CFG0_ADCPSC;
322 RCU_CFG2 &= ~(RCU_CFG2_ADCSEL | RCU_CFG2_IRC28MDIV | RCU_CFG2_ADCPSC2);
323
324 /* set the ADC clock according to ck_adc */
325 switch(ck_adc){
326 case RCU_ADCCK_IRC28M_DIV2:
327 RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
328 RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
329 break;
330 case RCU_ADCCK_IRC28M:
331 RCU_CFG2 |= RCU_CFG2_IRC28MDIV;
332 RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
333 break;
334 case RCU_ADCCK_APB2_DIV2:
335 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2;
336 RCU_CFG2 |= RCU_CFG2_ADCSEL;
337 break;
338 case RCU_ADCCK_APB2_DIV3:
339 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2;
340 RCU_CFG2 |= RCU_CFG2_ADCPSC2;
341 RCU_CFG2 |= RCU_CFG2_ADCSEL;
342 break;
343 case RCU_ADCCK_APB2_DIV4:
344 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4;
345 RCU_CFG2 |= RCU_CFG2_ADCSEL;
346 break;
347 case RCU_ADCCK_APB2_DIV5:
348 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4;
349 RCU_CFG2 |= RCU_CFG2_ADCPSC2;
350 RCU_CFG2 |= RCU_CFG2_ADCSEL;
351 break;
352 case RCU_ADCCK_APB2_DIV6:
353 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6;
354 RCU_CFG2 |= RCU_CFG2_ADCSEL;
355 break;
356 case RCU_ADCCK_APB2_DIV7:
357 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6;
358 RCU_CFG2 |= RCU_CFG2_ADCPSC2;
359 RCU_CFG2 |= RCU_CFG2_ADCSEL;
360 break;
361 case RCU_ADCCK_APB2_DIV8:
362 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8;
363 RCU_CFG2 |= RCU_CFG2_ADCSEL;
364 break;
365 case RCU_ADCCK_APB2_DIV9:
366 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8;
367 RCU_CFG2 |= RCU_CFG2_ADCPSC2;
368 RCU_CFG2 |= RCU_CFG2_ADCSEL;
369 break;
370 default:
371 break;
372 }
373 }
RCU_ADCCK_APB2_DIV3
Definition: gd32f3x0_rcu.h:430
RCU_CFG2_ADCPSC2
#define RCU_CFG2_ADCPSC2
Definition: gd32f3x0_rcu.h:198
RCU_ADCCK_APB2_DIV6
Definition: gd32f3x0_rcu.h:433
RCU_ADC_CKAPB2_DIV8
#define RCU_ADC_CKAPB2_DIV8
Definition: gd32f3x0_rcu.h:508
RCU_ADCCK_IRC28M
Definition: gd32f3x0_rcu.h:428
RCU_ADCCK_APB2_DIV5
Definition: gd32f3x0_rcu.h:432
RCU_CFG0_ADCPSC
#define RCU_CFG0_ADCPSC
Definition: gd32f3x0_rcu.h:61
RCU_ADCCK_APB2_DIV9
Definition: gd32f3x0_rcu.h:436
RCU_CFG2_IRC28MDIV
#define RCU_CFG2_IRC28MDIV
Definition: gd32f3x0_rcu.h:196
RCU_ADCCK_APB2_DIV7
Definition: gd32f3x0_rcu.h:434
RCU_CFG2_ADCSEL
#define RCU_CFG2_ADCSEL
Definition: gd32f3x0_rcu.h:195
RCU_ADC_CKAPB2_DIV4
#define RCU_ADC_CKAPB2_DIV4
Definition: gd32f3x0_rcu.h:506
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_ADC_CKAPB2_DIV6
#define RCU_ADC_CKAPB2_DIV6
Definition: gd32f3x0_rcu.h:507
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
RCU_ADCCK_APB2_DIV8
Definition: gd32f3x0_rcu.h:435
RCU_ADC_CKAPB2_DIV2
#define RCU_ADC_CKAPB2_DIV2
Definition: gd32f3x0_rcu.h:505
RCU_ADCCK_IRC28M_DIV2
Definition: gd32f3x0_rcu.h:427
RCU_ADCCK_APB2_DIV4
Definition: gd32f3x0_rcu.h:431
RCU_ADCCK_APB2_DIV2
Definition: gd32f3x0_rcu.h:429
void rcu_ahb_clock_config ( uint32_t ck_ahb )

configure the AHB clock prescaler selection

Parameters
[in] ck_ahb AHB clock prescaler selection
  • RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512
[out] none
Return values
none

Definition at line 253 of file gd32f3x0_rcu.c.

254 {
255 uint32_t ahbpsc = 0U;
256 ahbpsc = RCU_CFG0;
257 /* reset the AHBPSC bits and set according to ck_ahb */
258 ahbpsc &= ~RCU_CFG0_AHBPSC;
259 RCU_CFG0 = (ck_ahb | ahbpsc);
260 }
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG0_AHBPSC
#define RCU_CFG0_AHBPSC
Definition: gd32f3x0_rcu.h:58
void rcu_all_reset_flag_clear ( void )

clear the reset flag

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 574 of file gd32f3x0_rcu.c.

575 {
576 RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
577 }
RCU_RSTSCK
#define RCU_RSTSCK
Definition: gd32f3x0_rcu.h:30
RCU_RSTSCK_RSTFC
#define RCU_RSTSCK_RSTFC
Definition: gd32f3x0_rcu.h:169
void rcu_apb1_clock_config ( uint32_t ck_apb1 )

configure the APB1 clock prescaler selection

Parameters
[in] ck_apb1 APB1 clock prescaler selection
  • RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1
  • RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1
  • RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1
  • RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1
  • RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1
[out] none
Return values
none

Definition at line 273 of file gd32f3x0_rcu.c.

274 {
275 uint32_t apb1psc = 0U;
276 apb1psc = RCU_CFG0;
277 /* reset the APB1PSC and set according to ck_apb1 */
278 apb1psc &= ~RCU_CFG0_APB1PSC;
279 RCU_CFG0 = (ck_apb1 | apb1psc);
280 }
RCU_CFG0_APB1PSC
#define RCU_CFG0_APB1PSC
Definition: gd32f3x0_rcu.h:59
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
void rcu_apb2_clock_config ( uint32_t ck_apb2 )

configure the APB2 clock prescaler selection

Parameters
[in] ck_apb2 APB2 clock prescaler selection
  • RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2
  • RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2
  • RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2
  • RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2
  • RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2
[out] none
Return values
none

Definition at line 293 of file gd32f3x0_rcu.c.

294 {
295 uint32_t apb2psc = 0U;
296 apb2psc = RCU_CFG0;
297 /* reset the APB2PSC and set according to ck_apb2 */
298 apb2psc &= ~RCU_CFG0_APB2PSC;
299 RCU_CFG0 = (ck_apb2 | apb2psc);
300 }
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG0_APB2PSC
#define RCU_CFG0_APB2PSC
Definition: gd32f3x0_rcu.h:60
void rcu_bkp_reset_disable ( void )

disable the BKP reset

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 208 of file gd32f3x0_rcu.c.

209 {
210 RCU_BDCTL &= ~RCU_BDCTL_BKPRST;
211 }
RCU_BDCTL_BKPRST
#define RCU_BDCTL_BKPRST
Definition: gd32f3x0_rcu.h:163
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f3x0_rcu.h:29
void rcu_bkp_reset_enable ( void )

reset the BKP

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 197 of file gd32f3x0_rcu.c.

198 {
199 RCU_BDCTL |= RCU_BDCTL_BKPRST;
200 }
RCU_BDCTL_BKPRST
#define RCU_BDCTL_BKPRST
Definition: gd32f3x0_rcu.h:163
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f3x0_rcu.h:29
void rcu_cec_clock_config ( uint32_t ck_cec )

configure the CEC clock source selection

Parameters
[in] ck_cec CEC clock source selection
  • RCU_CECSRC_IRC8M_DIV244: CK_CEC select CK_IRC8M/244
  • RCU_CECSRC_LXTAL: CK_CEC select CK_LXTAL
[out] none
Return values
none

Definition at line 480 of file gd32f3x0_rcu.c.

481 {
482 /* reset the CECSEL bit and set according to ck_cec */
483 RCU_CFG2 &= ~RCU_CFG2_CECSEL;
484 RCU_CFG2 |= ck_cec;
485 }
RCU_CFG2_CECSEL
#define RCU_CFG2_CECSEL
Definition: gd32f3x0_rcu.h:194
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
void rcu_ckout_config | ( | uint32_t | ckout_src,
 |  | uint32_t | ckout_div
 | ) |  |

configure the CK_OUT clock source and divider

Parameters
[in] ckout_src CK_OUT clock source selection
  • RCU_CKOUTSRC_NONE: no clock selected
  • RCU_CKOUTSRC_IRC28M: IRC28M selected
  • RCU_CKOUTSRC_IRC40K: IRC40K selected
  • RCU_CKOUTSRC_LXTAL: LXTAL selected
  • RCU_CKOUTSRC_CKSYS: CKSYS selected
  • RCU_CKOUTSRC_IRC8M: IRC8M selected
  • RCU_CKOUTSRC_HXTAL: HXTAL selected
  • RCU_CKOUTSRC_CKPLL_DIV1: CK_PLL selected
  • RCU_CKOUTSRC_CKPLL_DIV2: CK_PLL/2 selected
[in] ckout_div CK_OUT divider
  • RCU_CKOUT_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT is divided by x
[out] none
Return values
none

Definition at line 414 of file gd32f3x0_rcu.c.

415 {
416 uint32_t ckout = 0U;
417 ckout = RCU_CFG0;
418 /* reset the CKOUTSEL, CKOUTDIV and PLLDV bits and set according to ckout_src and ckout_div */
419 ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
420 RCU_CFG0 = (ckout | ckout_src | ckout_div);
421 }
RCU_CFG0_CKOUTSEL
#define RCU_CFG0_CKOUTSEL
Definition: gd32f3x0_rcu.h:66
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG0_PLLDV
#define RCU_CFG0_PLLDV
Definition: gd32f3x0_rcu.h:69
RCU_CFG0_CKOUTDIV
#define RCU_CFG0_CKOUTDIV
Definition: gd32f3x0_rcu.h:68
uint32_t rcu_clock_freq_get ( rcu_clock_freq_enum clock )

get the system clock, bus and peripheral clock frequency

Parameters
[in] clock the clock frequency which to get
  • CK_SYS: system clock frequency
  • CK_AHB: AHB clock frequency
  • CK_APB1: APB1 clock frequency
  • CK_APB2: APB2 clock frequency
  • CK_ADC: ADC clock frequency
  • CK_CEC: CEC clock frequency
  • CK_USART: USART clock frequency
[out] none
Return values
clock frequency of system, AHB, APB1, APB2, ADC, CEC or USRAT

Definition at line 964 of file gd32f3x0_rcu.c.

965 {
966 uint32_t sws = 0U, adcps = 0U, adcps2 = 0U, ck_freq = 0U;
967 uint32_t cksys_freq = 0U, ahb_freq = 0U, apb1_freq = 0U, apb2_freq = 0U;
968 uint32_t adc_freq = 0U, cec_freq = 0U, usart_freq = 0U;
969 uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
970 /* exponent of AHB, APB1 and APB2 clock divider */
971 const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
972 const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
973 const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
974
975 sws = GET_BITS(RCU_CFG0, 2, 3);
976 switch(sws){
977 /* IRC8M is selected as CK_SYS */
978 case SEL_IRC8M:
979 cksys_freq = IRC8M_VALUE;
980 break;
981 /* HXTAL is selected as CK_SYS */
982 case SEL_HXTAL:
983 cksys_freq = HXTAL_VALUE;
984 break;
985 /* PLL is selected as CK_SYS */
986 case SEL_PLL:
987 /* get the value of PLLMF[3:0] */
988 pllmf = GET_BITS(RCU_CFG0, 18, 21);
989 pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
990 pllmf5 = GET_BITS(RCU_CFG1, 31, 31);
991 /* high 16 bits */
992 if(1U == pllmf4){
993 pllmf += 17U;
994 }else{
995 pllmf += 2U;
996 }
997 if(1U == pllmf5){
998 pllmf += 31U;
999 }
1000
1001 /* PLL clock source selection, HXTAL or IRC8M/2 */
1002 pllsel = GET_BITS(RCU_CFG0, 16, 16);
1003 pllpresel = GET_BITS(RCU_CFG1, 30, 30);
1004 if(0U != pllsel){
1005 prediv = (GET_BITS(RCU_CFG1,0, 3) + 1U);
1006 if(0U == pllpresel){
1007 cksys_freq = (HXTAL_VALUE / prediv) * pllmf;
1008 }else{
1009 cksys_freq = (IRC48M_VALUE / prediv) * pllmf;
1010 }
1011 }else{
1012 cksys_freq = (IRC8M_VALUE >> 1) * pllmf;
1013 }
1014 break;
1015 /* IRC8M is selected as CK_SYS */
1016 default:
1017 cksys_freq = IRC8M_VALUE;
1018 break;
1019 }
1020 /* calculate AHB clock frequency */
1021 idx = GET_BITS(RCU_CFG0, 4, 7);
1022 clk_exp = ahb_exp[idx];
1023 ahb_freq = cksys_freq >> clk_exp;
1024
1025 /* calculate APB1 clock frequency */
1026 idx = GET_BITS(RCU_CFG0, 8, 10);
1027 clk_exp = apb1_exp[idx];
1028 apb1_freq = ahb_freq >> clk_exp;
1029
1030 /* calculate APB2 clock frequency */
1031 idx = GET_BITS(RCU_CFG0, 11, 13);
1032 clk_exp = apb2_exp[idx];
1033 apb2_freq = ahb_freq >> clk_exp;
1034
1035 /* return the clocks frequency */
1036 switch(clock){
1037 case CK_SYS:
1038 ck_freq = cksys_freq;
1039 break;
1040 case CK_AHB:
1041 ck_freq = ahb_freq;
1042 break;
1043 case CK_APB1:
1044 ck_freq = apb1_freq;
1045 break;
1046 case CK_APB2:
1047 ck_freq = apb2_freq;
1048 break;
1049 case CK_ADC:
1050 /* calculate ADC clock frequency */
1051 if(RCU_ADCSRC_APB2DIV != (RCU_CFG2 & RCU_CFG2_ADCSEL)){
1052 if(RCU_ADC_IRC28M_DIV1 != (RCU_CFG2 & RCU_CFG2_IRC28MDIV)){
1053 adc_freq = IRC28M_VALUE >> 1;
1054 }else{
1055 adc_freq = IRC28M_VALUE;
1056 }
1057 }else{
1058 /* ADC clock select CK_APB2 divided by 2/3/4/5/6/7/8/9 */
1059 adcps = GET_BITS(RCU_CFG0, 14, 15);
1060 adcps2 = GET_BITS(RCU_CFG2, 31, 31);
1061 switch(adcps){
1062 case 0:
1063 if(0U == adcps2){
1064 adc_freq = apb2_freq / 2U;
1065 }else{
1066 adc_freq = apb2_freq / 3U;
1067 }
1068 break;
1069 case 1:
1070 if(0U == adcps2){
1071 adc_freq = apb2_freq / 4U;
1072 }else{
1073 adc_freq = apb2_freq / 5U;
1074 }
1075 break;
1076 case 2:
1077 if(0U == adcps2){
1078 adc_freq = apb2_freq / 6U;
1079 }else{
1080 adc_freq = apb2_freq / 7U;
1081 }
1082 break;
1083 case 3:
1084 if(0U == adcps2){
1085 adc_freq = apb2_freq / 8U;
1086 }else{
1087 adc_freq = apb2_freq / 9U;
1088 }
1089 break;
1090 default:
1091 break;
1092 }
1093 }
1094 ck_freq = adc_freq;
1095 break;
1096 case CK_CEC:
1097 /* calculate CEC clock frequency */
1098 if(RCU_CECSRC_LXTAL != (RCU_CFG2 & RCU_CFG2_CECSEL)){
1099 cec_freq = IRC8M_VALUE / 244U;
1100 }else{
1101 cec_freq = LXTAL_VALUE;
1102 }
1103 ck_freq = cec_freq;
1104 break;
1105 case CK_USART:
1106 /* calculate USART clock frequency */
1107 if(RCU_USART0SRC_CKAPB2 == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
1108 usart_freq = apb2_freq;
1109 }else if(RCU_USART0SRC_CKSYS == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
1110 usart_freq = cksys_freq;
1111 }else if(RCU_USART0SRC_LXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
1112 usart_freq = LXTAL_VALUE;
1113 }else if(RCU_USART0SRC_IRC8M == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
1114 usart_freq = IRC8M_VALUE;
1115 }else{
1116 }
1117 ck_freq = usart_freq;
1118 break;
1119 default:
1120 break;
1121 }
1122 return ck_freq;
1123 }
CK_APB1
Definition: gd32f3x0_rcu.h:456
SEL_HXTAL
#define SEL_HXTAL
Definition: gd32f3x0_rcu.c:16
RCU_USART0SRC_LXTAL
#define RCU_USART0SRC_LXTAL
Definition: gd32f3x0_rcu.h:661
CK_ADC
Definition: gd32f3x0_rcu.h:458
RCU_CFG2_USART0SEL
#define RCU_CFG2_USART0SEL
Definition: gd32f3x0_rcu.h:193
RCU_USART0SRC_CKSYS
#define RCU_USART0SRC_CKSYS
Definition: gd32f3x0_rcu.h:660
RCU_CFG2_IRC28MDIV
#define RCU_CFG2_IRC28MDIV
Definition: gd32f3x0_rcu.h:196
RCU_CECSRC_LXTAL
#define RCU_CECSRC_LXTAL
Definition: gd32f3x0_rcu.h:666
CK_USART
Definition: gd32f3x0_rcu.h:460
CK_SYS
Definition: gd32f3x0_rcu.h:454
CK_AHB
Definition: gd32f3x0_rcu.h:455
RCU_CFG2_ADCSEL
#define RCU_CFG2_ADCSEL
Definition: gd32f3x0_rcu.h:195
RCU_USART0SRC_CKAPB2
#define RCU_USART0SRC_CKAPB2
Definition: gd32f3x0_rcu.h:659
RCU_ADCSRC_APB2DIV
#define RCU_ADCSRC_APB2DIV
Definition: gd32f3x0_rcu.h:670
RCU_CFG1
#define RCU_CFG1
Definition: gd32f3x0_rcu.h:32
CK_APB2
Definition: gd32f3x0_rcu.h:457
CK_CEC
Definition: gd32f3x0_rcu.h:459
RCU_ADC_IRC28M_DIV1
#define RCU_ADC_IRC28M_DIV1
Definition: gd32f3x0_rcu.h:674
SEL_IRC8M
#define SEL_IRC8M
Definition: gd32f3x0_rcu.c:15
RCU_CFG2_CECSEL
#define RCU_CFG2_CECSEL
Definition: gd32f3x0_rcu.h:194
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
RCU_USART0SRC_IRC8M
#define RCU_USART0SRC_IRC8M
Definition: gd32f3x0_rcu.h:662
SEL_PLL
#define SEL_PLL
Definition: gd32f3x0_rcu.c:17
void rcu_deepsleep_voltage_set ( uint32_t dsvol )

set voltage in deep sleep mode

Parameters
[in] dsvol deep sleep mode voltage
  • RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V
  • RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V
  • RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V
  • RCU_DEEPSLEEP_V_0_7: the core voltage is 0.7V
[out] none
Return values
none

Definition at line 944 of file gd32f3x0_rcu.c.

945 {
946 /* reset the DSLPVS bits and set according to dsvol */
947 RCU_DSV &= ~RCU_DSV_DSLPVS;
948 RCU_DSV |= dsvol;
949 }
RCU_DSV_DSLPVS
#define RCU_DSV_DSLPVS
Definition: gd32f3x0_rcu.h:229
RCU_DSV
#define RCU_DSV
Definition: gd32f3x0_rcu.h:40
void rcu_deinit ( void )

deinitialize the RCU

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 29 of file gd32f3x0_rcu.c.

30 {
31 /* enable IRC8M */
32 RCU_CTL0 |= RCU_CTL0_IRC8MEN;
33 while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
34 }
35 /* reset RCU */
36 RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
37 RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
38 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
39 #if (defined(GD32F350))
40 RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC);
41 RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2);
42 #endif /* GD32F350 */
43 RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
44 RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL);
45 RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
46 RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
47 RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
48 RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
49 RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN;
50 RCU_INT = 0x00000000U;
51 RCU_ADDINT = 0x00000000U;
52 }
RCU_CFG1_PLLMF5
#define RCU_CFG1_PLLMF5
Definition: gd32f3x0_rcu.h:190
RCU_CFG2_ADCPSC2
#define RCU_CFG2_ADCPSC2
Definition: gd32f3x0_rcu.h:198
RCU_INT
#define RCU_INT
Definition: gd32f3x0_rcu.h:23
RCU_CFG1_PLLPRESEL
#define RCU_CFG1_PLLPRESEL
Definition: gd32f3x0_rcu.h:189
RCU_CFG2_USBFSPSC2
#define RCU_CFG2_USBFSPSC2
Definition: gd32f3x0_rcu.h:197
RCU_CTL1_IRC28MEN
#define RCU_CTL1_IRC28MEN
Definition: gd32f3x0_rcu.h:201
RCU_CFG2_USART0SEL
#define RCU_CFG2_USART0SEL
Definition: gd32f3x0_rcu.h:193
RCU_CFG0_ADCPSC
#define RCU_CFG0_ADCPSC
Definition: gd32f3x0_rcu.h:61
RCU_CFG2_IRC28MDIV
#define RCU_CFG2_IRC28MDIV
Definition: gd32f3x0_rcu.h:196
RCU_CFG0_APB1PSC
#define RCU_CFG0_APB1PSC
Definition: gd32f3x0_rcu.h:59
RCU_CFG0_PLLMF4
#define RCU_CFG0_PLLMF4
Definition: gd32f3x0_rcu.h:67
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
RCU_CFG2_ADCSEL
#define RCU_CFG2_ADCSEL
Definition: gd32f3x0_rcu.h:195
RCU_CTL1
#define RCU_CTL1
Definition: gd32f3x0_rcu.h:34
RCU_CFG1
#define RCU_CFG1
Definition: gd32f3x0_rcu.h:32
RCU_CTL0_PLLEN
#define RCU_CTL0_PLLEN
Definition: gd32f3x0_rcu.h:52
RCU_CFG0_PLLMF
#define RCU_CFG0_PLLMF
Definition: gd32f3x0_rcu.h:64
RCU_CFG0_SCS
#define RCU_CFG0_SCS
Definition: gd32f3x0_rcu.h:56
RCU_CTL0_IRC8MSTB
#define RCU_CTL0_IRC8MSTB
Definition: gd32f3x0_rcu.h:45
RCU_CTL0_IRC8MEN
#define RCU_CTL0_IRC8MEN
Definition: gd32f3x0_rcu.h:44
RCU_ADDCTL
#define RCU_ADDCTL
Definition: gd32f3x0_rcu.h:35
RCU_CFG0_CKOUTSEL
#define RCU_CFG0_CKOUTSEL
Definition: gd32f3x0_rcu.h:66
RCU_CFG2_CECSEL
#define RCU_CFG2_CECSEL
Definition: gd32f3x0_rcu.h:194
RCU_CFG1_PREDV
#define RCU_CFG1_PREDV
Definition: gd32f3x0_rcu.h:188
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
RCU_CFG0_USBFSPSC
#define RCU_CFG0_USBFSPSC
Definition: gd32f3x0_rcu.h:65
RCU_CTL0_CKMEN
#define RCU_CTL0_CKMEN
Definition: gd32f3x0_rcu.h:51
RCU_CFG0_APB2PSC
#define RCU_CFG0_APB2PSC
Definition: gd32f3x0_rcu.h:60
RCU_CTL0_HXTALEN
#define RCU_CTL0_HXTALEN
Definition: gd32f3x0_rcu.h:48
RCU_CFG0_PLLDV
#define RCU_CFG0_PLLDV
Definition: gd32f3x0_rcu.h:69
RCU_ADDCTL_IRC48MEN
#define RCU_ADDCTL_IRC48MEN
Definition: gd32f3x0_rcu.h:208
RCU_ADDINT
#define RCU_ADDINT
Definition: gd32f3x0_rcu.h:36
RCU_CTL0_HXTALBPS
#define RCU_CTL0_HXTALBPS
Definition: gd32f3x0_rcu.h:50
RCU_CFG0_CKOUTDIV
#define RCU_CFG0_CKOUTDIV
Definition: gd32f3x0_rcu.h:68
RCU_CFG0_PLLSEL
#define RCU_CFG0_PLLSEL
Definition: gd32f3x0_rcu.h:62
RCU_CFG0_AHBPSC
#define RCU_CFG0_AHBPSC
Definition: gd32f3x0_rcu.h:58
FlagStatus rcu_flag_get ( rcu_flag_enum flag )

get the clock stabilization and periphral reset flags

Parameters
[in] flag the clock stabilization and periphral reset flags, refer to rcu_flag_enum only one parameter can be selected which is shown as below:
  • RCU_FLAG_IRC40KSTB: IRC40K stabilization flag
  • RCU_FLAG_LXTALSTB: LXTAL stabilization flag
  • RCU_FLAG_IRC8MSTB: IRC8M stabilization flag
  • RCU_FLAG_HXTALSTB: HXTAL stabilization flag
  • RCU_FLAG_PLLSTB: PLL stabilization flag
  • RCU_FLAG_IRC28MSTB: IRC28M stabilization flag
  • RCU_FLAG_IRC48MSTB: IRC48M stabilization flag
  • RCU_FLAG_V12RST: V12 domain power reset flag
  • RCU_FLAG_OBLRST: option byte loader reset flag
  • RCU_FLAG_EPRST: external pin reset flag
  • RCU_FLAG_PORRST: power reset flag
  • RCU_FLAG_SWRST: software reset flag
  • RCU_FLAG_FWDGTRST: free watchdog timer reset flag
  • RCU_FLAG_WWDGTRST: window watchdog timer reset flag
  • RCU_FLAG_LPRST: low-power reset flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 559 of file gd32f3x0_rcu.c.

560 {
561 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){
562 return SET;
563 }else{
564 return RESET;
565 }
566 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_hxtal_clock_monitor_disable ( void )

disable the HXTAL clock monitor

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 886 of file gd32f3x0_rcu.c.

887 {
888 RCU_CTL0 &= ~RCU_CTL0_CKMEN;
889 }
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
RCU_CTL0_CKMEN
#define RCU_CTL0_CKMEN
Definition: gd32f3x0_rcu.h:51
void rcu_hxtal_clock_monitor_enable ( void )

enable the HXTAL clock monitor

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 875 of file gd32f3x0_rcu.c.

876 {
877 RCU_CTL0 |= RCU_CTL0_CKMEN;
878 }
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
RCU_CTL0_CKMEN
#define RCU_CTL0_CKMEN
Definition: gd32f3x0_rcu.h:51
void rcu_hxtal_prediv_config ( uint32_t hxtal_prediv )

configure the HXTAL divider used as input of PLL

Parameters
[in] hxtal_prediv HXTAL divider used as input of PLL
  • RCU_PLL_PREDVx(x=1..16): HXTAL or IRC48M divided x used as input of PLL
[out] none
Return values
none

Definition at line 511 of file gd32f3x0_rcu.c.

512 {
513 uint32_t prediv = 0U;
514 prediv = RCU_CFG1;
515 /* reset the HXTALPREDV bits and set according to hxtal_prediv */
516 prediv &= ~RCU_CFG1_PREDV;
517 RCU_CFG1 = (prediv | hxtal_prediv);
518 }
RCU_CFG1
#define RCU_CFG1
Definition: gd32f3x0_rcu.h:32
RCU_CFG1_PREDV
#define RCU_CFG1_PREDV
Definition: gd32f3x0_rcu.h:188
void rcu_interrupt_disable ( rcu_int_enum stab_int )

disable the stabilization interrupt

Parameters
[in] stab_int clock stabilization interrupt, refer to rcu_int_enum only one parameter can be selected which is shown as below:
  • RCU_INT_IRC40KSTB: IRC40K stabilization interrupt disable
  • RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable
  • RCU_INT_IRC8MSTB: IRC8M stabilization interrupt disable
  • RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable
  • RCU_INT_PLLSTB: PLL stabilization interrupt disable
  • RCU_INT_IRC28MSTB: IRC28M stabilization interrupt disable
  • RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable
[out] none
Return values
none

Definition at line 657 of file gd32f3x0_rcu.c.

658 {
659 RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int));
660 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_interrupt_enable ( rcu_int_enum stab_int )

enable the stabilization interrupt

Parameters
[in] stab_int clock stabilization interrupt, refer to rcu_int_enum only one parameter can be selected which is shown as below:
  • RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
  • RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
  • RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
  • RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
  • RCU_INT_PLLSTB: PLL stabilization interrupt enable
  • RCU_INT_IRC28MSTB: IRC28M stabilization interrupt enable
  • RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable
[out] none
Return values
none

Definition at line 637 of file gd32f3x0_rcu.c.

638 {
639 RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int));
640 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_interrupt_flag_clear ( rcu_int_flag_clear_enum int_flag_clear )

clear the interrupt flags

Parameters
[in] int_flag_clear clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum only one parameter can be selected which is shown as below:
  • RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear
  • RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear
  • RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear
  • RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear
  • RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear
  • RCU_INT_FLAG_IRC28MSTB_CLR: IRC28M stabilization interrupt flag clear
  • RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear
  • RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear
[out] none
Return values
none

Definition at line 618 of file gd32f3x0_rcu.c.

619 {
620 RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear));
621 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
FlagStatus rcu_interrupt_flag_get ( rcu_int_flag_enum int_flag )

get the clock stabilization interrupt and ckm flags

Parameters
[in] int_flag interrupt and ckm flags, refer to rcu_int_flag_enum only one parameter can be selected which is shown as below:
  • RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag
  • RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag
  • RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag
  • RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag
  • RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag
  • RCU_INT_FLAG_IRC28MSTB: IRC28M stabilization interrupt flag
  • RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag
  • RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 594 of file gd32f3x0_rcu.c.

595 {
596 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){
597 return SET;
598 }else{
599 return RESET;
600 }
601 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_irc28m_adjust_value_set ( uint8_t irc28m_adjval )

set the IRC28M adjust value

Parameters
[in] | irc28m_adjval | IRC28M adjust value, must be between 0 and 0x1F
[out] | none
Return values
none

Definition at line 912 of file gd32f3x0_rcu.c.

913 {
914 uint32_t adjust = 0U;
915 adjust = RCU_CTL1;
916 /* reset the IRC28MADJ bits and set according to irc28m_adjval */
917 adjust &= ~RCU_CTL1_IRC28MADJ;
918 RCU_CTL1 = (adjust | (((uint32_t)irc28m_adjval)<<3));
919 }
RCU_CTL1_IRC28MADJ
#define RCU_CTL1_IRC28MADJ
Definition: gd32f3x0_rcu.h:203
RCU_CTL1
#define RCU_CTL1
Definition: gd32f3x0_rcu.h:34
void rcu_irc8m_adjust_value_set ( uint8_t irc8m_adjval )

set the IRC8M adjust value

Parameters
[in] | irc8m_adjval | IRC8M adjust value, must be between 0 and 0x1F
[out] | none
Return values
none

Definition at line 897 of file gd32f3x0_rcu.c.

898 {
899 uint32_t adjust = 0U;
900 adjust = RCU_CTL0;
901 /* reset the IRC8MADJ bits and set according to irc8m_adjval */
902 adjust &= ~RCU_CTL0_IRC8MADJ;
903 RCU_CTL0 = (adjust | (((uint32_t)irc8m_adjval)<<3));
904 }
RCU_CTL0_IRC8MADJ
#define RCU_CTL0_IRC8MADJ
Definition: gd32f3x0_rcu.h:46
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
void rcu_lxtal_drive_capability_config ( uint32_t lxtal_dricap )

configure the LXTAL drive capability

Parameters
[in] lxtal_dricap drive capability of LXTAL
  • RCU_LXTAL_LOWDRI: lower driving capability
  • RCU_LXTAL_MED_LOWDRI: medium low driving capability
  • RCU_LXTAL_MED_HIGHDRI: medium high driving capability
  • RCU_LXTAL_HIGHDRI: higher driving capability
[out] none
Return values
none

Definition at line 530 of file gd32f3x0_rcu.c.

531 {
532 /* reset the LXTALDRI bits and set according to lxtal_dricap */
533 RCU_BDCTL &= ~RCU_BDCTL_LXTALDRI;
534 RCU_BDCTL |= lxtal_dricap;
535 }
RCU_BDCTL_LXTALDRI
#define RCU_BDCTL_LXTALDRI
Definition: gd32f3x0_rcu.h:160
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f3x0_rcu.h:29
void rcu_osci_bypass_mode_disable ( rcu_osci_type_enum osci )

disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum
  • RCU_HXTAL: HXTAL
  • RCU_LXTAL: LXTAL
[out] none
Return values
none

Definition at line 842 of file gd32f3x0_rcu.c.

843 {
844 uint32_t reg;
845 switch(osci){
846 case RCU_HXTAL:
847 /* HXTALEN must be reset before disable the oscillator bypass mode */
848 reg = RCU_CTL0;
849 RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
850 RCU_CTL0 = (reg & (~RCU_CTL0_HXTALBPS));
851 break;
852 case RCU_LXTAL:
853 /* LXTALEN must be reset before disable the oscillator bypass mode */
854 reg = RCU_BDCTL;
855 RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
856 RCU_BDCTL = (reg & (~RCU_BDCTL_LXTALBPS));
857 break;
858 case RCU_IRC8M:
859 case RCU_IRC28M:
860 case RCU_IRC48M:
861 case RCU_IRC40K:
862 case RCU_PLL_CK:
863 break;
864 default:
865 break;
866 }
867 }
RCU_IRC48M
Definition: gd32f3x0_rcu.h:446
RCU_BDCTL_LXTALEN
#define RCU_BDCTL_LXTALEN
Definition: gd32f3x0_rcu.h:157
RCU_HXTAL
Definition: gd32f3x0_rcu.h:442
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
RCU_IRC28M
Definition: gd32f3x0_rcu.h:445
RCU_BDCTL_LXTALBPS
#define RCU_BDCTL_LXTALBPS
Definition: gd32f3x0_rcu.h:159
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f3x0_rcu.h:29
RCU_IRC8M
Definition: gd32f3x0_rcu.h:444
RCU_PLL_CK
Definition: gd32f3x0_rcu.h:448
RCU_CTL0_HXTALEN
#define RCU_CTL0_HXTALEN
Definition: gd32f3x0_rcu.h:48
RCU_CTL0_HXTALBPS
#define RCU_CTL0_HXTALBPS
Definition: gd32f3x0_rcu.h:50
RCU_LXTAL
Definition: gd32f3x0_rcu.h:443
RCU_IRC40K
Definition: gd32f3x0_rcu.h:447
void rcu_osci_bypass_mode_enable ( rcu_osci_type_enum osci )

enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum
  • RCU_HXTAL: HXTAL
  • RCU_LXTAL: LXTAL
[out] none
Return values
none

Definition at line 807 of file gd32f3x0_rcu.c.

808 {
809 uint32_t reg;
810 switch(osci){
811 case RCU_HXTAL:
812 /* HXTALEN must be reset before enable the oscillator bypass mode */
813 reg = RCU_CTL0;
814 RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
815 RCU_CTL0 = (reg | RCU_CTL0_HXTALBPS);
816 break;
817 case RCU_LXTAL:
818 /* LXTALEN must be reset before enable the oscillator bypass mode */
819 reg = RCU_BDCTL;
820 RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
821 RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
822 break;
823 case RCU_IRC8M:
824 case RCU_IRC28M:
825 case RCU_IRC48M:
826 case RCU_IRC40K:
827 case RCU_PLL_CK:
828 break;
829 default:
830 break;
831 }
832 }
RCU_IRC48M
Definition: gd32f3x0_rcu.h:446
RCU_BDCTL_LXTALEN
#define RCU_BDCTL_LXTALEN
Definition: gd32f3x0_rcu.h:157
RCU_HXTAL
Definition: gd32f3x0_rcu.h:442
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
RCU_IRC28M
Definition: gd32f3x0_rcu.h:445
RCU_BDCTL_LXTALBPS
#define RCU_BDCTL_LXTALBPS
Definition: gd32f3x0_rcu.h:159
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f3x0_rcu.h:29
RCU_IRC8M
Definition: gd32f3x0_rcu.h:444
RCU_PLL_CK
Definition: gd32f3x0_rcu.h:448
RCU_CTL0_HXTALEN
#define RCU_CTL0_HXTALEN
Definition: gd32f3x0_rcu.h:48
RCU_CTL0_HXTALBPS
#define RCU_CTL0_HXTALBPS
Definition: gd32f3x0_rcu.h:50
RCU_LXTAL
Definition: gd32f3x0_rcu.h:443
RCU_IRC40K
Definition: gd32f3x0_rcu.h:447
void rcu_osci_off ( rcu_osci_type_enum osci )

turn off the oscillator

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum
  • RCU_HXTAL: HXTAL
  • RCU_LXTAL: LXTAL
  • RCU_IRC8M: IRC8M
  • RCU_IRC28M: IRC28M
  • RCU_IRC48M: IRC48M
  • RCU_IRC40K: IRC40K
  • RCU_PLL_CK: PLL
[out] none
Return values
none

Definition at line 794 of file gd32f3x0_rcu.c.

795 {
796 RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci));
797 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_osci_on ( rcu_osci_type_enum osci )

turn on the oscillator

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum
  • RCU_HXTAL: HXTAL
  • RCU_LXTAL: LXTAL
  • RCU_IRC8M: IRC8M
  • RCU_IRC28M: IRC28M
  • RCU_IRC48M: IRC48M
  • RCU_IRC40K: IRC40K
  • RCU_PLL_CK: PLL
[out] none
Return values
none

Definition at line 776 of file gd32f3x0_rcu.c.

777 {
778 RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));
779 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
ErrStatus rcu_osci_stab_wait ( rcu_osci_type_enum osci )

wait until oscillator stabilization flags is SET

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum
  • RCU_HXTAL: HXTAL
  • RCU_LXTAL: LXTAL
  • RCU_IRC8M: IRC8M
  • RCU_IRC28M: IRC28M
  • RCU_IRC48M: IRC48M
  • RCU_IRC40K: IRC40K
  • RCU_PLL_CK: PLL
[out] none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 675 of file gd32f3x0_rcu.c.

676 {
677 uint32_t stb_cnt = 0U;
678 ErrStatus reval = ERROR;
679 FlagStatus osci_stat = RESET;
680 switch(osci){
681 case RCU_HXTAL:
682 /* wait until HXTAL is stabilization and osci_stat is not more than timeout */
683 while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){
684 osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
685 stb_cnt++;
686 }
687 if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){
688 reval = SUCCESS;
689 }
690 break;
691 /* wait LXTAL stable */
692 case RCU_LXTAL:
693 while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){
694 osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
695 stb_cnt++;
696 }
697
698 /* check whether flag is set or not */
699 if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){
700 reval = SUCCESS;
701 }
702 break;
703
704 /* wait IRC8M stable */
705 case RCU_IRC8M:
706 while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){
707 osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
708 stb_cnt++;
709 }
710
711 /* check whether flag is set or not */
712 if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){
713 reval = SUCCESS;
714 }
715 break;
716
717 /* wait IRC48M stable */
718 case RCU_IRC48M:
719 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
720 osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB);
721 stb_cnt++;
722 }
723
724 /* check whether flag is set or not */
725 if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)){
726 reval = SUCCESS;
727 }
728 break;
729
730 /* wait IRC40K stable */
731 case RCU_IRC40K:
732 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
733 osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
734 stb_cnt++;
735 }
736
737 /* check whether flag is set or not */
738 if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){
739 reval = SUCCESS;
740 }
741 break;
742
743 /* wait PLL stable */
744 case RCU_PLL_CK:
745 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
746 osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
747 stb_cnt++;
748 }
749
750 /* check whether flag is set or not */
751 if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){
752 reval = SUCCESS;
753 }
754 break;
755
756 default:
757 break;
758 }
759 /* return value */
760 return reval;
761 }
RCU_FLAG_HXTALSTB
Definition: gd32f3x0_rcu.h:371
RCU_FLAG_IRC40KSTB
Definition: gd32f3x0_rcu.h:368
RCU_IRC48M
Definition: gd32f3x0_rcu.h:446
RCU_HXTAL
Definition: gd32f3x0_rcu.h:442
RCU_FLAG_LXTALSTB
Definition: gd32f3x0_rcu.h:369
RCU_FLAG_PLLSTB
Definition: gd32f3x0_rcu.h:372
OSC_STARTUP_TIMEOUT
#define OSC_STARTUP_TIMEOUT
Definition: gd32f3x0_rcu.c:20
RCU_IRC8M
Definition: gd32f3x0_rcu.h:444
rcu_flag_get
FlagStatus rcu_flag_get(rcu_flag_enum flag)
get the clock stabilization and periphral reset flags
Definition: gd32f3x0_rcu.c:559
RCU_PLL_CK
Definition: gd32f3x0_rcu.h:448
RCU_FLAG_IRC8MSTB
Definition: gd32f3x0_rcu.h:370
LXTAL_STARTUP_TIMEOUT
#define LXTAL_STARTUP_TIMEOUT
Definition: gd32f3x0_rcu.c:21
RCU_LXTAL
Definition: gd32f3x0_rcu.h:443
RCU_IRC40K
Definition: gd32f3x0_rcu.h:447
RCU_FLAG_IRC48MSTB
Definition: gd32f3x0_rcu.h:374
void rcu_periph_clock_disable ( rcu_periph_enum periph )

disable the peripherals clock

Parameters
[in] periph RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOx (x=A,B,C,D,F): GPIO ports clock
  • RCU_DMA: DMA clock
  • RCU_CRC: CRC clock
  • RCU_TSI: TSI clock
  • RCU_CFGCMP: CFGCMP clock
  • RCU_ADC: ADC clock
  • RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock (RCU_TIMER5 only for GD32F350)
  • RCU_SPIx (x=0,1,2): SPI clock
  • RCU_USARTx (x=0,1): USART clock
  • RCU_WWDGT: WWDGT clock
  • RCU_I2Cx (x=0,1,2): I2C clock
  • RCU_USBFS: USBFS clock (only for GD32F350)
  • RCU_PMU: PMU clock
  • RCU_DAC: DAC clock (only for GD32F350)
  • RCU_CEC: CEC clock (only for GD32F350)
  • RCU_CTC: CTC clock
  • RCU_RTC: RTC clock
[out] none
Return values
none

Definition at line 107 of file gd32f3x0_rcu.c.

108 {
109 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
110 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_periph_clock_enable ( rcu_periph_enum periph )

enable the peripherals clock

Parameters
[in] periph RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOx (x=A,B,C,D,F): GPIO ports clock
  • RCU_DMA: DMA clock
  • RCU_CRC: CRC clock
  • RCU_TSI: TSI clock
  • RCU_CFGCMP: CFGCMP clock
  • RCU_ADC: ADC clock
  • RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock (RCU_TIMER5 only for GD32F350)
  • RCU_SPIx (x=0,1,2): SPI clock
  • RCU_USARTx (x=0,1): USART clock
  • RCU_WWDGT: WWDGT clock
  • RCU_I2Cx (x=0,1,2): I2C clock
  • RCU_USBFS: USBFS clock (only for GD32F350)
  • RCU_PMU: PMU clock
  • RCU_DAC: DAC clock (only for GD32F350)
  • RCU_CEC: CEC clock (only for GD32F350)
  • RCU_CTC: CTC clock
  • RCU_RTC: RTC clock
[out] none
Return values
none

Definition at line 78 of file gd32f3x0_rcu.c.

79 {
80 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
81 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_periph_clock_sleep_disable ( rcu_periph_sleep_enum periph )

disable the peripherals clock when sleep mode

Parameters
[in] periph RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below:
  • RCU_FMC_SLP: FMC clock
  • RCU_SRAM_SLP: SRAM clock
[out] none
Return values
none

Definition at line 135 of file gd32f3x0_rcu.c.

136 {
137 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
138 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_periph_clock_sleep_enable ( rcu_periph_sleep_enum periph )

enable the peripherals clock when sleep mode

Parameters
[in] periph RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below:
  • RCU_FMC_SLP: FMC clock
  • RCU_SRAM_SLP: SRAM clock
[out] none
Return values
none

Definition at line 121 of file gd32f3x0_rcu.c.

122 {
123 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
124 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_periph_reset_disable ( rcu_periph_reset_enum periph_reset )

disable reset the peripheral

Parameters
[in] periph_reset RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOxRST (x=A,B,C,D,F): reset GPIO ports
  • RCU_TSIRST: reset TSI
  • RCU_CFGCMPRST: reset CFGCMP
  • RCU_ADCRST: reset ADC
  • RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER (RCU_TIMER5 only for GD32F350)
  • RCU_SPIxRST (x=0,1,2): reset SPI
  • RCU_USARTxRST (x=0,1): reset USART
  • RCU_WWDGTRST: reset WWDGT
  • RCU_I2CxRST (x=0,1,2): reset I2C
  • RCU_USBFSRST: reset USBFS (only for GD32F350)
  • RCU_PMURST: reset PMU
  • RCU_DACRST: reset DAC (only for GD32F350)
  • RCU_CECRST: reset CEC (only for GD32F350)
  • RCU_CTCRST: reset CTC
[out] none
Return values
none

Definition at line 186 of file gd32f3x0_rcu.c.

187 {
188 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset));
189 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_periph_reset_enable ( rcu_periph_reset_enum periph_reset )

reset the peripherals

Parameters
[in] periph_reset RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOxRST (x=A,B,C,D,F): reset GPIO ports
  • RCU_TSIRST: reset TSI
  • RCU_CFGCMPRST: reset CFGCMP
  • RCU_ADCRST: reset ADC
  • RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER (RCU_TIMER5 only for GD32F350)
  • RCU_SPIxRST (x=0,1,2): reset SPI
  • RCU_USARTxRST (x=0,1): reset USART
  • RCU_WWDGTRST: reset WWDGT
  • RCU_I2CxRST (x=0,1,2): reset I2C
  • RCU_USBFSRST: reset USBFS (only for GD32F350)
  • RCU_PMURST: reset PMU
  • RCU_DACRST: reset DAC (only for GD32F350)
  • RCU_CECRST: reset CEC (only for GD32F350)
  • RCU_CTCRST: reset CTC
[out] none
Return values
none

Definition at line 160 of file gd32f3x0_rcu.c.

161 {
162 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
163 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_pll_config | ( | uint32_t | pll_src,
 |  | uint32_t | pll_mul
 | ) |  |

configure the PLL clock source selection and PLL multiply factor

Parameters
[in] pll_src PLL clock source selection
  • RCU_PLLSRC_IRC8M_DIV2: select CK_IRC8M/2 as PLL source clock
  • RCU_PLLSRC_HXTAL_IRC48M: select HXTAL or IRC48M as PLL source clock
[in] pll_mul PLL multiply factor
  • RCU_PLL_MULx(x=2..64): PLL source clock * x
[out] none
Return values
none

Definition at line 447 of file gd32f3x0_rcu.c.

448 {
449 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
450 RCU_CFG1 &= ~(RCU_CFG1_PLLMF5);
451 RCU_CFG0 |= (pll_src | (pll_mul & (~RCU_CFG1_PLLMF5)));
452 RCU_CFG1 |= (pll_mul & RCU_CFG1_PLLMF5);
453 }
RCU_CFG1_PLLMF5
#define RCU_CFG1_PLLMF5
Definition: gd32f3x0_rcu.h:190
RCU_CFG1
#define RCU_CFG1
Definition: gd32f3x0_rcu.h:32
RCU_CFG0_PLLMF
#define RCU_CFG0_PLLMF
Definition: gd32f3x0_rcu.h:64
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG0_PLLSEL
#define RCU_CFG0_PLLSEL
Definition: gd32f3x0_rcu.h:62
void rcu_pll_preselection_config ( uint32_t pll_presel )

configure the PLL clock source preselection

Parameters
[in] pll_presel PLL clock source preselection
  • RCU_PLLPRESEL_IRC48M: select IRC48M as PLL preselection clock
  • RCU_PLLPRESEL_HXTAL: select HXTAL as PLL preselection clock
[out] none
Return values
none

Definition at line 431 of file gd32f3x0_rcu.c.

432 {
433 RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL);
434 RCU_CFG1 |= pll_presel;
435 }
RCU_CFG1_PLLPRESEL
#define RCU_CFG1_PLLPRESEL
Definition: gd32f3x0_rcu.h:189
RCU_CFG1
#define RCU_CFG1
Definition: gd32f3x0_rcu.h:32
void rcu_rtc_clock_config ( uint32_t rtc_clock_source )

configure the RTC clock source selection

Parameters
[in] rtc_clock_source RTC clock source selection
  • RCU_RTCSRC_NONE: no clock selected
  • RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock
  • RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock
  • RCU_RTCSRC_HXTAL_DIV32: CK_HXTAL/32 selected as RTC source clock
[out] none
Return values
none

Definition at line 497 of file gd32f3x0_rcu.c.

498 {
499 /* reset the RTCSRC bits and set according to rtc_clock_source */
500 RCU_BDCTL &= ~RCU_BDCTL_RTCSRC;
501 RCU_BDCTL |= rtc_clock_source;
502 }
RCU_BDCTL_RTCSRC
#define RCU_BDCTL_RTCSRC
Definition: gd32f3x0_rcu.h:161
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f3x0_rcu.h:29
void rcu_system_clock_source_config ( uint32_t ck_sys )

configure the system clock source

Parameters
[in] ck_sys system clock source select only one parameter can be selected which is shown as below:
  • RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source
  • RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source
  • RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source
[out] none
Return values
none

Definition at line 223 of file gd32f3x0_rcu.c.

224 {
225 uint32_t cksys_source = 0U;
226 cksys_source = RCU_CFG0;
227 /* reset the SCS bits and set according to ck_sys */
228 cksys_source &= ~RCU_CFG0_SCS;
229 RCU_CFG0 = (ck_sys | cksys_source);
230 }
RCU_CFG0_SCS
#define RCU_CFG0_SCS
Definition: gd32f3x0_rcu.h:56
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
uint32_t rcu_system_clock_source_get ( void )

get the system clock source

Parameters
[in] | none
[out] | none
Return values
which clock is selected as CK_SYS source
  • RCU_SCSS_IRC8M: select CK_IRC8M as the CK_SYS source
  • RCU_SCSS_HXTAL: select CK_HXTAL as the CK_SYS source
  • RCU_SCSS_PLL: select CK_PLL as the CK_SYS source

Definition at line 241 of file gd32f3x0_rcu.c.

242 {
243 return (RCU_CFG0 & RCU_CFG0_SCSS);
244 }
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG0_SCSS
#define RCU_CFG0_SCSS
Definition: gd32f3x0_rcu.h:57
void rcu_usart_clock_config ( uint32_t ck_usart )

configure the USART clock source selection

Parameters
[in] ck_usart USART clock source selection
  • RCU_USART0SRC_CKAPB2: CK_USART0 select CK_APB2
  • RCU_USART0SRC_CKSYS: CK_USART0 select CK_SYS
  • RCU_USART0SRC_LXTAL: CK_USART0 select CK_LXTAL
  • RCU_USART0SRC_IRC8M: CK_USART0 select CK_IRC8M
[out] none
Return values
none

Definition at line 465 of file gd32f3x0_rcu.c.

466 {
467 /* reset the USART0SEL bits and set according to ck_usart */
468 RCU_CFG2 &= ~RCU_CFG2_USART0SEL;
469 RCU_CFG2 |= ck_usart;
470 }
RCU_CFG2_USART0SEL
#define RCU_CFG2_USART0SEL
Definition: gd32f3x0_rcu.h:193
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
void rcu_usbfs_clock_config ( uint32_t ck_usbfs )

configure the USBFS clock prescaler selection

Parameters
[in] ck_usbfs USBFS clock prescaler selection
  • RCU_USBFS_CKPLL_DIV1_5: select CK_PLL/1.5 as CK_USBFS
  • RCU_USBFS_CKPLL_DIV1: select CK_PLL as CK_USBFS
  • RCU_USBFS_CKPLL_DIV2_5: select CK_PLL/2.5 as CK_USBFS
  • RCU_USBFS_CKPLL_DIV2: select CK_PLL/2 as CK_USBFS
  • RCU_USBFS_CKPLL_DIV3: select CK_PLL/3 as CK_USBFS
  • RCU_USBFS_CKPLL_DIV3_5: select CK_PLL/3.5 as CK_USBFS
[out] none
Return values
none

Definition at line 387 of file gd32f3x0_rcu.c.

388 {
389 /* reset the USBFSPSC bits and set according to ck_usbfs */
390 RCU_CFG0 &= ~RCU_CFG0_USBFSPSC;
391 RCU_CFG2 &= ~RCU_CFG2_USBFSPSC2;
392
393 RCU_CFG0 |= (ck_usbfs & (~RCU_CFG2_USBFSPSC2));
394 RCU_CFG2 |= (ck_usbfs & RCU_CFG2_USBFSPSC2);
395 }
RCU_CFG2_USBFSPSC2
#define RCU_CFG2_USBFSPSC2
Definition: gd32f3x0_rcu.h:197
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
RCU_CFG0_USBFSPSC
#define RCU_CFG0_USBFSPSC
Definition: gd32f3x0_rcu.h:65
void rcu_voltage_key_unlock ( void )

unlock the voltage key

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 927 of file gd32f3x0_rcu.c.

928 {
929 /* reset the KEY bits and set 0x1A2B3C4D */
930 RCU_VKEY &= ~RCU_VKEY_KEY;
931 RCU_VKEY |= RCU_VKEY_UNLOCK;
932 }
RCU_VKEY
#define RCU_VKEY
Definition: gd32f3x0_rcu.h:39
RCU_VKEY_UNLOCK
#define RCU_VKEY_UNLOCK
Definition: gd32f3x0_rcu.h:237
RCU_VKEY_KEY
#define RCU_VKEY_KEY
Definition: gd32f3x0_rcu.h:226
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Data Structures | Macros | Functions
gd32f3x0_rtc.h File Reference

definitions for the RTC More...

#include "gd32f3x0.h"

Go to the source code of this file.

Data Structures

struct | rtc_parameter_struct
struct | rtc_alarm_struct
struct | rtc_timestamp_struct
struct | rtc_tamper_struct

Macros

#define | RTC RTC_BASE
#define | RTC_TIME REG32((RTC) + 0x00U)
#define | RTC_DATE REG32((RTC) + 0x04U)
#define | RTC_CTL REG32((RTC) + 0x08U)
#define | RTC_STAT REG32((RTC) + 0x0CU)
#define | RTC_PSC REG32((RTC) + 0x10U)
#define | RTC_ALRM0TD REG32((RTC) + 0x1CU)
#define | RTC_WPK REG32((RTC) + 0x24U)
#define | RTC_SS REG32((RTC) + 0x28U)
#define | RTC_SHIFTCTL REG32((RTC) + 0x2CU)
#define | RTC_TTS REG32((RTC) + 0x30U)
#define | RTC_DTS REG32((RTC) + 0x34U)
#define | RTC_SSTS REG32((RTC) + 0x38U)
#define | RTC_HRFC REG32((RTC) + 0x3CU)
#define | RTC_TAMP REG32((RTC) + 0x40U)
#define | RTC_ALRM0SS REG32((RTC) + 0x44U)
#define | RTC_BKP0 REG32((RTC) + 0x50U)
#define | RTC_BKP1 REG32((RTC) + 0x54U)
#define | RTC_BKP2 REG32((RTC) + 0x58U)
#define | RTC_BKP3 REG32((RTC) + 0x5CU)
#define | RTC_BKP4 REG32((RTC) + 0x60U)
#define | RTC_TIME_SCU BITS(0,3)
#define | RTC_TIME_SCT BITS(4,6)
#define | RTC_TIME_MNU BITS(8,11)
#define | RTC_TIME_MNT BITS(12,14)
#define | RTC_TIME_HRU BITS(16,19)
#define | RTC_TIME_HRT BITS(20,21)
#define | RTC_TIME_PM BIT(22)
#define | RTC_DATE_DAYU BITS(0,3)
#define | RTC_DATE_DAYT BITS(4,5)
#define | RTC_DATE_MONU BITS(8,11)
#define | RTC_DATE_MONT BIT(12)
#define | RTC_DATE_DOW BITS(13,15)
#define | RTC_DATE_YRU BITS(16,19)
#define | RTC_DATE_YRT BITS(20,23)
#define | RTC_CTL_TSEG BIT(3)
#define | RTC_CTL_REFEN BIT(4)
#define | RTC_CTL_BPSHAD BIT(5)
#define | RTC_CTL_CS BIT(6)
#define | RTC_CTL_ALRM0EN BIT(8)
#define | RTC_CTL_TSEN BIT(11)
#define | RTC_CTL_ALRM0IE BIT(12)
#define | RTC_CTL_TSIE BIT(15)
#define | RTC_CTL_A1H BIT(16)
#define | RTC_CTL_S1H BIT(17)
#define | RTC_CTL_DSM BIT(18)
#define | RTC_CTL_COS BIT(19)
#define | RTC_CTL_OPOL BIT(20)
#define | RTC_CTL_OS BITS(21,22)
#define | RTC_CTL_COEN BIT(23)
#define | RTC_STAT_ALRM0WF BIT(0)
#define | RTC_STAT_SOPF BIT(3)
#define | RTC_STAT_YCM BIT(4)
#define | RTC_STAT_RSYNF BIT(5)
#define | RTC_STAT_INITF BIT(6)
#define | RTC_STAT_INITM BIT(7)
#define | RTC_STAT_ALRM0F BIT(8)
#define | RTC_STAT_TSF BIT(11)
#define | RTC_STAT_TSOVRF BIT(12)
#define | RTC_STAT_TP0F BIT(13)
#define | RTC_STAT_TP1F BIT(14)
#define | RTC_STAT_SCPF BIT(16)
#define | RTC_PSC_FACTOR_S BITS(0,14)
#define | RTC_PSC_FACTOR_A BITS(16,22)
#define | RTC_ALRM0TD_SCU BITS(0,3)
#define | RTC_ALRM0TD_SCT BITS(4,6)
#define | RTC_ALRM0TD_MSKS BIT(7)
#define | RTC_ALRM0TD_MNU BITS(8,11)
#define | RTC_ALRM0TD_MNT BITS(12,14)
#define | RTC_ALRM0TD_MSKM BIT(15)
#define | RTC_ALRM0TD_HRU BITS(16,19)
#define | RTC_ALRM0TD_HRT BITS(20,21)
#define | RTC_ALRM0TD_PM BIT(22)
#define | RTC_ALRM0TD_MSKH BIT(23)
#define | RTC_ALRM0TD_DAYU BITS(24,27)
#define | RTC_ALRM0TD_DAYT BITS(28,29)
#define | RTC_ALRM0TD_DOWS BIT(30)
#define | RTC_ALRM0TD_MSKD BIT(31)
#define | RTC_WPK_WPK BITS(0,7)
#define | RTC_SS_SSC BITS(0,15)
#define | RTC_SHIFTCTL_SFS BITS(0,14)
#define | RTC_SHIFTCTL_A1S BIT(31)
#define | RTC_TTS_SCU BITS(0,3)
#define | RTC_TTS_SCT BITS(4,6)
#define | RTC_TTS_MNU BITS(8,11)
#define | RTC_TTS_MNT BITS(12,14)
#define | RTC_TTS_HRU BITS(16,19)
#define | RTC_TTS_HRT BITS(20,21)
#define | RTC_TTS_PM BIT(22)
#define | RTC_DTS_DAYU BITS(0,3)
#define | RTC_DTS_DAYT BITS(4,5)
#define | RTC_DTS_MONU BITS(8,11)
#define | RTC_DTS_MONT BIT(12)
#define | RTC_DTS_DOW BITS(13,15)
#define | RTC_SSTS_SSC BITS(0,15)
#define | RTC_HRFC_CMSK BITS(0,8)
#define | RTC_HRFC_CWND16 BIT(13)
#define | RTC_HRFC_CWND8 BIT(14)
#define | RTC_HRFC_FREQI BIT(15)
#define | RTC_TAMP_TP0EN BIT(0)
#define | RTC_TAMP_TP0EG BIT(1)
#define | RTC_TAMP_TPIE BIT(2)
#define | RTC_TAMP_TP1EN BIT(3)
#define | RTC_TAMP_TP1EG BIT(4)
#define | RTC_TAMP_TPTS BIT(7)
#define | RTC_TAMP_FREQ BITS(8,10)
#define | RTC_TAMP_FLT BITS(11,12)
#define | RTC_TAMP_PRCH BITS(13,14)
#define | RTC_TAMP_DISPU BIT(15)
#define | RTC_TAMP_PC13VAL BIT(18)
#define | RTC_TAMP_PC13MDE BIT(19)
#define | RTC_TAMP_PC14VAL BIT(20)
#define | RTC_TAMP_PC14MDE BIT(21)
#define | RTC_TAMP_PC15VAL BIT(22)
#define | RTC_TAMP_PC15MDE BIT(23)
#define | RTC_ALRM0SS_SSC BITS(0,14)
#define | RTC_ALRM0SS_MASKSSC BITS(24,27)
#define | RTC_BKP0_DATA BITS(0,31)
#define | RTC_BKP1_DATA BITS(0,31)
#define | RTC_BKP2_DATA BITS(0,31)
#define | RTC_BKP3_DATA BITS(0,31)
#define | RTC_BKP4_DATA BITS(0,31)
#define | TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
#define | GET_TIME_SC(regval) GET_BITS((regval),0,6)
#define | TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U))
#define | GET_TIME_MN(regval) GET_BITS((regval),8,14)
#define | TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U))
#define | GET_TIME_HR(regval) GET_BITS((regval),16,21)
#define | RTC_AM ((uint32_t)0x00000000U)
#define | RTC_PM RTC_TIME_PM
#define | DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U))
#define | GET_DATE_DAY(regval) GET_BITS((regval),0,5)
#define | DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U))
#define | GET_DATE_MON(regval) GET_BITS((regval),8,12)
#define | RTC_JAN ((uint8_t)0x01U)
#define | RTC_FEB ((uint8_t)0x02U)
#define | RTC_MAR ((uint8_t)0x03U)
#define | RTC_APR ((uint8_t)0x04U)
#define | RTC_MAY ((uint8_t)0x05U)
#define | RTC_JUN ((uint8_t)0x06U)
#define | RTC_JUL ((uint8_t)0x07U)
#define | RTC_AUG ((uint8_t)0x08U)
#define | RTC_SEP ((uint8_t)0x09U)
#define | RTC_OCT ((uint8_t)0x10U)
#define | RTC_NOV ((uint8_t)0x11U)
#define | RTC_DEC ((uint8_t)0x12U)
#define | DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U))
#define | GET_DATE_DOW(regval) GET_BITS((regval),13,15)
#define | RTC_MONDAY ((uint8_t)0x01U)
#define | RTC_TUESDAY ((uint8_t)0x02U)
#define | RTC_WEDSDAY ((uint8_t)0x03U)
#define | RTC_THURSDAY ((uint8_t)0x04U)
#define | RTC_FRIDAY ((uint8_t)0x05U)
#define | RTC_SATURDAY ((uint8_t)0x06U)
#define | RTC_SUNDAY ((uint8_t)0x07U)
#define | DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16U))
#define | GET_DATE_YR(regval) GET_BITS((regval),16,23)
#define | CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21U))
#define | RTC_OS_DISABLE CTL_OS(0)
#define | RTC_OS_ENABLE CTL_OS(1)
#define | RTC_CALIBRATION_512HZ RTC_CTL_COEN
#define | RTC_CALIBRATION_1HZ RTC_CTL_COEN | RTC_CTL_COS
#define | RTC_ALARM_HIGH RTC_CTL_OS_ENABLE
#define | RTC_ALARM_LOW RTC_CTL_OS_ENABLE | RTC_CTL_OPOL
#define | RTC_24HOUR ((uint32_t)0x00000000U)
#define | RTC_12HOUR RTC_CTL_CS
#define | RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U)
#define | RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG
#define | PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U))
#define | GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14)
#define | PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16U))
#define | GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22)
#define | ALRM0TD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0U))
#define | GET_ALRM0TD_SC(regval) GET_BITS((regval),0,6)
#define | ALRM0TD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U))
#define | GET_ALRM0TD_MN(regval) GET_BITS((regval),8,14)
#define | ALRM0TD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U))
#define | GET_ALRM0TD_HR(regval) GET_BITS((regval),16,21)
#define | ALRM0TD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24U))
#define | GET_ALRM0TD_DAY(regval) GET_BITS((regval),24,29)
#define | RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U)
#define | RTC_ALARM_DATE_MASK RTC_ALRM0TD_MSKD
#define | RTC_ALARM_HOUR_MASK RTC_ALRM0TD_MSKH
#define | RTC_ALARM_MINUTE_MASK RTC_ALRM0TD_MSKM
#define | RTC_ALARM_SECOND_MASK RTC_ALRM0TD_MSKS
#define | RTC_ALARM_ALL_MASK (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS)
#define | RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U)
#define | RTC_ALARM_WEEKDAY_SELECTED RTC_ALRM0TD_DOWS
#define | WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U))
#define | SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U))
#define | SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U))
#define | RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U)
#define | RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S
#define | TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
#define | GET_TTS_SC(regval) GET_BITS((regval),0,6)
#define | TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U))
#define | GET_TTS_MN(regval) GET_BITS((regval),8,14)
#define | TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U))
#define | GET_TTS_HR(regval) GET_BITS((regval),16,21)
#define | DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U))
#define | GET_DTS_DAY(regval) GET_BITS((regval),0,5)
#define | DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U))
#define | GET_DTS_MON(regval) GET_BITS((regval),8,11)
#define | DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U))
#define | GET_DTS_DOW(regval) GET_BITS((regval),13,15)
#define | SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U))
#define | HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0U))
#define | RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U)
#define | RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16
#define | RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8
#define | RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI
#define | RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U)
#define | TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U))
#define | RTC_FREQ_DIV32768 TAMP_FREQ(0)
#define | RTC_FREQ_DIV16384 TAMP_FREQ(1)
#define | RTC_FREQ_DIV8192 TAMP_FREQ(2)
#define | RTC_FREQ_DIV4096 TAMP_FREQ(3)
#define | RTC_FREQ_DIV2048 TAMP_FREQ(4)
#define | RTC_FREQ_DIV1024 TAMP_FREQ(5)
#define | RTC_FREQ_DIV512 TAMP_FREQ(6)
#define | RTC_FREQ_DIV256 TAMP_FREQ(7)
#define | TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11U))
#define | RTC_FLT_EDGE TAMP_FLT(0)
#define | RTC_FLT_2S TAMP_FLT(1)
#define | RTC_FLT_4S TAMP_FLT(2)
#define | RTC_FLT_8S TAMP_FLT(3)
#define | TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13U))
#define | RTC_PRCH_1C TAMP_PRCH(0)
#define | RTC_PRCH_2C TAMP_PRCH(1)
#define | RTC_PRCH_4C TAMP_PRCH(2)
#define | RTC_PRCH_8C TAMP_PRCH(3)
#define | RTC_TAMPER0 RTC_TAMP_TP0EN
#define | RTC_TAMPER1 RTC_TAMP_TP1EN
#define | RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U)
#define | RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG
#define | RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U)
#define | RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG
#define | RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */
#define | RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U)
#define | RTC_ALARM_OUTPUT_PP RTC_TAMP_PC13VAL
#define | ALRM0SS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0U))
#define | ALRM0SS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U))
#define | RTC_MASKSSC_0_14 ALRM0SS_MASKSSC(0)
#define | RTC_MASKSSC_1_14 ALRM0SS_MASKSSC(1)
#define | RTC_MASKSSC_2_14 ALRM0SS_MASKSSC(2)
#define | RTC_MASKSSC_3_14 ALRM0SS_MASKSSC(3)
#define | RTC_MASKSSC_4_14 ALRM0SS_MASKSSC(4)
#define | RTC_MASKSSC_5_14 ALRM0SS_MASKSSC(5)
#define | RTC_MASKSSC_6_14 ALRM0SS_MASKSSC(6)
#define | RTC_MASKSSC_7_14 ALRM0SS_MASKSSC(7)
#define | RTC_MASKSSC_8_14 ALRM0SS_MASKSSC(8)
#define | RTC_MASKSSC_9_14 ALRM0SS_MASKSSC(9)
#define | RTC_MASKSSC_10_14 ALRM0SS_MASKSSC(10)
#define | RTC_MASKSSC_11_14 ALRM0SS_MASKSSC(11)
#define | RTC_MASKSSC_12_14 ALRM0SS_MASKSSC(12)
#define | RTC_MASKSSC_13_14 ALRM0SS_MASKSSC(13)
#define | RTC_MASKSSC_14 ALRM0SS_MASKSSC(14)
#define | RTC_MASKSSC_NONE ALRM0SS_MASKSSC(15)
#define | RTC_INT_TIMESTAMP RTC_CTL_TSIE
#define | RTC_INT_ALARM RTC_CTL_ALRM0IE
#define | RTC_INT_TAMP RTC_TAMP_TPIE
#define | RTC_UNLOCK_KEY1 ((uint8_t)0xCAU)
#define | RTC_UNLOCK_KEY2 ((uint8_t)0x53U)
#define | RTC_LOCK_KEY ((uint8_t)0xFFU)
#define | RTC_REGISTER_RESET ((uint32_t)0x00000000U)
#define | RTC_DATE_RESET ((uint32_t)0x00002101U)
#define | RTC_STAT_RESET ((uint32_t)0x00000007U)
#define | RTC_PSC_RESET ((uint32_t)0x007F00FFU)
#define | RTC_INITM_TIMEOUT ((uint32_t)0x00004000U)
#define | RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U)
#define | RTC_HRFC_TIMEOUT ((uint32_t)0x00001000U)
#define | RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U)
#define | RTC_ALRM0WF_TIMEOUT ((uint32_t)0x00008000U)
#define | RTC_FLAG_RECALIBRATION RTC_STAT_SCPF
#define | RTC_FLAG_TAMP1 RTC_STAT_TP1F
#define | RTC_FLAG_TAMP0 RTC_STAT_TP0F
#define | RTC_FLAG_TIMESTAMP_OVERFLOW RTC_STAT_TSOVRF
#define | RTC_FLAG_TIMESTAMP RTC_STAT_TSF
#define | RTC_FLAG_ALARM0 RTC_STAT_ALRM0F
#define | RTC_FLAG_INIT RTC_STAT_INITF
#define | RTC_FLAG_RSYN RTC_STAT_RSYNF
#define | RTC_FLAG_YCM RTC_STAT_YCM
#define | RTC_FLAG_SHIFT RTC_STAT_SOPF
#define | RTC_FLAG_ALARM0_WRITTEN RTC_STAT_ALRM0WF

Functions

ErrStatus | rtc_deinit (void)
reset most of the RTC registers More...
ErrStatus | rtc_init (rtc_parameter_struct *rtc_initpara_struct)
initialize RTC registers More...
ErrStatus | rtc_init_mode_enter (void)
enter RTC init mode More...
void | rtc_init_mode_exit (void)
exit RTC init mode More...
ErrStatus | rtc_register_sync_wait (void)
wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated More...
void | rtc_current_time_get (rtc_parameter_struct *rtc_initpara_struct)
get current time and date More...
uint32_t | rtc_subsecond_get (void)
get current subsecond value More...
void | rtc_alarm_config (rtc_alarm_struct *rtc_alarm_time)
configure RTC alarm More...
void | rtc_alarm_subsecond_config (uint32_t mask_subsecond, uint32_t subsecond)
configure subsecond of RTC alarm More...
void | rtc_alarm_get (rtc_alarm_struct *rtc_alarm_time)
get RTC alarm More...
uint32_t | rtc_alarm_subsecond_get (void)
get RTC alarm subsecond More...
void | rtc_alarm_enable (void)
enable RTC alarm More...
ErrStatus | rtc_alarm_disable (void)
disable RTC alarm More...
void | rtc_timestamp_enable (uint32_t edge)
enable RTC time-stamp More...
void | rtc_timestamp_disable (void)
disable RTC time-stamp More...
void | rtc_timestamp_get (rtc_timestamp_struct *rtc_timestamp)
get RTC timestamp time and date More...
uint32_t | rtc_timestamp_subsecond_get (void)
get RTC time-stamp subsecond More...
void | rtc_tamper_enable (rtc_tamper_struct *rtc_tamper)
enable RTC tamper More...
void | rtc_tamper_disable (uint32_t source)
disable RTC tamper More...
void | rtc_interrupt_enable (uint32_t interrupt)
enable specified RTC interrupt More...
void | rtc_interrupt_disable (uint32_t interrupt)
disble specified RTC interrupt More...
FlagStatus | rtc_flag_get (uint32_t flag)
check specified flag More...
void | rtc_flag_clear (uint32_t flag)
clear specified flag More...
void | rtc_alter_output_config (uint32_t source, uint32_t mode)
configure rtc alternate output source More...
ErrStatus | rtc_calibration_config (uint32_t window, uint32_t plus, uint32_t minus)
configure RTC calibration register More...
void | rtc_hour_adjust (uint32_t operation)
ajust the daylight saving time by adding or substracting one hour from the current time More...
ErrStatus | rtc_second_ajust (uint32_t add, uint32_t minus)
ajust RTC second or subsecond value of current time More...
void | rtc_bypass_shadow_enable (void)
enable RTC bypass shadow registers function More...
void | rtc_bypass_shadow_disable (void)
disable RTC bypass shadow registers function More...
ErrStatus | rtc_refclock_detection_enable (void)
enable RTC reference clock detection function More...
ErrStatus | rtc_refclock_detection_disable (void)
disable RTC reference clock detection function More...

Detailed Description

definitions for the RTC

Definition in file gd32f3x0_rtc.h.

Macro Definition Documentation

#define ALRM0SS_MASKSSC ( regval ) (BITS(24,27) & ((uint32_t)(regval) << 24U))

write value to RTC_ALRM0SS_MASKSSC bit field

Definition at line 412 of file gd32f3x0_rtc.h.

#define ALRM0SS_SSC ( regval ) (BITS(0,14) & ((uint32_t)(regval)<< 0U))

write value to RTC_ALRM0SS_SSC bit field

Definition at line 410 of file gd32f3x0_rtc.h.

#define ALRM0TD_DAY ( regval ) (BITS(24,29) & ((uint32_t)(regval) << 24U))

write value to RTC_ALRM0TD_DAY bit field

Definition at line 315 of file gd32f3x0_rtc.h.

#define ALRM0TD_HR ( regval ) (BITS(16,21) & ((uint32_t)(regval) << 16U))

write value to RTC_ALRM0TD_HR bit field

Definition at line 312 of file gd32f3x0_rtc.h.

#define ALRM0TD_MN ( regval ) (BITS(8,14) & ((uint32_t)(regval) << 8U))

write value to RTC_ALRM0TD_MN bit field

Definition at line 309 of file gd32f3x0_rtc.h.

#define ALRM0TD_SC ( regval ) (BITS(0,6) & ((uint32_t)(regval)<< 0U))

write value to RTC_ALRM0TD_SC bit field

Definition at line 306 of file gd32f3x0_rtc.h.

#define CTL_OS ( regval ) (BITS(21,22) & ((uint32_t)(regval) << 21U))

write value to RTC_CTL_OS bit field

Definition at line 283 of file gd32f3x0_rtc.h.

#define DATE_DAY ( regval ) (BITS(0,5) & ((uint32_t)(regval) << 0U))

write value to RTC_DATE_DAY bit field

Definition at line 251 of file gd32f3x0_rtc.h.

#define DATE_DOW ( regval ) (BITS(13,15) & ((uint32_t)(regval) << 13U))

write value to RTC_DATE_DOW bit field

Definition at line 269 of file gd32f3x0_rtc.h.

#define DATE_MON ( regval ) (BITS(8,12) & ((uint32_t)(regval) << 8U))

write value to RTC_DATE_MON bit field

Definition at line 254 of file gd32f3x0_rtc.h.

#define DATE_YR ( regval ) (BITS(16,23) & ((uint32_t)(regval) << 16U))

write value to RTC_DATE_YR bit field

Definition at line 279 of file gd32f3x0_rtc.h.

#define DTS_DAY ( regval ) (BITS(0,5) & ((uint32_t)(regval) << 0U))

write value to RTC_DTS_DAY bit field

Definition at line 351 of file gd32f3x0_rtc.h.

#define DTS_DOW ( regval ) (BITS(13,15) & ((uint32_t)(regval) << 13U))

write value to RTC_DTS_DOW bit field

Definition at line 357 of file gd32f3x0_rtc.h.

#define DTS_MON ( regval ) (BITS(8,12) & ((uint32_t)(regval) << 8U))

write value to RTC_DTS_MON bit field

Definition at line 354 of file gd32f3x0_rtc.h.

#define GET_ALRM0TD_DAY ( regval ) GET_BITS((regval),24,29)

get value of RTC_ALRM0TD_DAY bit field

Definition at line 316 of file gd32f3x0_rtc.h.

#define GET_ALRM0TD_HR ( regval ) GET_BITS((regval),16,21)

get value of RTC_ALRM0TD_HR bit field

Definition at line 313 of file gd32f3x0_rtc.h.

#define GET_ALRM0TD_MN ( regval ) GET_BITS((regval),8,14)

get value of RTC_ALRM0TD_MN bit field

Definition at line 310 of file gd32f3x0_rtc.h.

#define GET_ALRM0TD_SC ( regval ) GET_BITS((regval),0,6)

get value of RTC_ALRM0TD_SC bit field

Definition at line 307 of file gd32f3x0_rtc.h.

#define GET_DATE_DAY ( regval ) GET_BITS((regval),0,5)

get value of RTC_DATE_DAY bit field

Definition at line 252 of file gd32f3x0_rtc.h.

#define GET_DATE_DOW ( regval ) GET_BITS((regval),13,15)

get value of RTC_DATE_DOW bit field

Definition at line 270 of file gd32f3x0_rtc.h.

#define GET_DATE_MON ( regval ) GET_BITS((regval),8,12)

get value of RTC_DATE_MON bit field

Definition at line 255 of file gd32f3x0_rtc.h.

#define GET_DATE_YR ( regval ) GET_BITS((regval),16,23)

get value of RTC_DATE_YR bit field

Definition at line 280 of file gd32f3x0_rtc.h.

#define GET_DTS_DAY ( regval ) GET_BITS((regval),0,5)

get value of RTC_DTS_DAY bit field

Definition at line 352 of file gd32f3x0_rtc.h.

#define GET_DTS_DOW ( regval ) GET_BITS((regval),13,15)

get value of RTC_DTS_DOW bit field

Definition at line 358 of file gd32f3x0_rtc.h.

#define GET_DTS_MON ( regval ) GET_BITS((regval),8,11)

get value of RTC_DTS_MON bit field

Definition at line 355 of file gd32f3x0_rtc.h.

#define GET_PSC_FACTOR_A ( regval ) GET_BITS((regval),16,22)

get value of RTC_PSC_FACTOR_A bit field

Definition at line 303 of file gd32f3x0_rtc.h.

#define GET_PSC_FACTOR_S ( regval ) GET_BITS((regval),0,14)

get value of RTC_PSC_FACTOR_S bit field

Definition at line 300 of file gd32f3x0_rtc.h.

#define GET_TIME_HR ( regval ) GET_BITS((regval),16,21)

get value of RTC_TIME_HR bit field

Definition at line 245 of file gd32f3x0_rtc.h.

#define GET_TIME_MN ( regval ) GET_BITS((regval),8,14)

get value of RTC_TIME_MN bit field

Definition at line 242 of file gd32f3x0_rtc.h.

#define GET_TIME_SC ( regval ) GET_BITS((regval),0,6)

get value of RTC_TIME_SC bit field

Definition at line 239 of file gd32f3x0_rtc.h.

#define GET_TTS_HR ( regval ) GET_BITS((regval),16,21)

get value of RTC_TTS_HR bit field

Definition at line 348 of file gd32f3x0_rtc.h.

#define GET_TTS_MN ( regval ) GET_BITS((regval),8,14)

get value of RTC_TTS_MN bit field

Definition at line 345 of file gd32f3x0_rtc.h.

#define GET_TTS_SC ( regval ) GET_BITS((regval),0,6)

get value of RTC_TTS_SC bit field

Definition at line 342 of file gd32f3x0_rtc.h.

#define HRFC_CMSK ( regval ) (BITS(0,8) & ((uint32_t)(regval) << 0U))

write value to RTC_HRFC_CMSK bit field

Definition at line 364 of file gd32f3x0_rtc.h.

#define PSC_FACTOR_A ( regval ) (BITS(16,22) & ((uint32_t)(regval) << 16U))

write value to RTC_PSC_FACTOR_A bit field

Definition at line 302 of file gd32f3x0_rtc.h.

#define PSC_FACTOR_S ( regval ) (BITS(0,14) & ((uint32_t)(regval) << 0U))

write value to RTC_PSC_FACTOR_S bit field

Definition at line 299 of file gd32f3x0_rtc.h.

#define RTC RTC_BASE

Definition at line 18 of file gd32f3x0_rtc.h.

#define RTC_12HOUR RTC_CTL_CS

12-hour format

Definition at line 293 of file gd32f3x0_rtc.h.

#define RTC_24HOUR ((uint32_t)0x00000000U)

24-hour format

Definition at line 292 of file gd32f3x0_rtc.h.

#define RTC_ALARM_ALL_MASK (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS)

alarm all mask

Definition at line 323 of file gd32f3x0_rtc.h.

#define RTC_ALARM_DATE_MASK RTC_ALRM0TD_MSKD

alarm date mask

Definition at line 319 of file gd32f3x0_rtc.h.

#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U)

alarm date format selected

Definition at line 325 of file gd32f3x0_rtc.h.

#define RTC_ALARM_HIGH RTC_CTL_OS_ENABLE

enable alarm flag output with high level

Definition at line 289 of file gd32f3x0_rtc.h.

#define RTC_ALARM_HOUR_MASK RTC_ALRM0TD_MSKH

alarm hour mask

Definition at line 320 of file gd32f3x0_rtc.h.

#define RTC_ALARM_LOW RTC_CTL_OS_ENABLE | RTC_CTL_OPOL

enable alarm flag output with low level

Definition at line 290 of file gd32f3x0_rtc.h.

#define RTC_ALARM_MINUTE_MASK RTC_ALRM0TD_MSKM

alarm minute mask

Definition at line 321 of file gd32f3x0_rtc.h.

#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U)

alarm none mask

Definition at line 318 of file gd32f3x0_rtc.h.

#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U)

RTC alarm output open-drain mode

Definition at line 406 of file gd32f3x0_rtc.h.

#define RTC_ALARM_OUTPUT_PP RTC_TAMP_PC13VAL

RTC alarm output push-pull mode

Definition at line 407 of file gd32f3x0_rtc.h.

#define RTC_ALARM_SECOND_MASK RTC_ALRM0TD_MSKS

alarm second mask

Definition at line 322 of file gd32f3x0_rtc.h.

#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRM0TD_DOWS

alarm weekday format selected

Definition at line 326 of file gd32f3x0_rtc.h.

#define RTC_ALRM0SS REG32((RTC) + 0x44U)

RTC alarm 0 sub second register

Definition at line 35 of file gd32f3x0_rtc.h.

#define RTC_ALRM0SS_MASKSSC BITS(24,27)

mask control bit of SS

Definition at line 167 of file gd32f3x0_rtc.h.

#define RTC_ALRM0SS_SSC BITS(0,14)

alarm sub second value

Definition at line 166 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD REG32((RTC) + 0x1CU)

RTC alarm 0 time and date register

Definition at line 26 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD_DAYT BITS(28,29)

date tens in BCD code

Definition at line 108 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD_DAYU BITS(24,27)

date units or week day in BCD code

Definition at line 107 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD_DOWS BIT(30)

day of week selection

Definition at line 109 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD_HRT BITS(20,21)

hour units in BCD code

Definition at line 104 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD_HRU BITS(16,19)

hour units in BCD code

Definition at line 103 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD_MNT BITS(12,14)

minutes tens in BCD code

Definition at line 101 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD_MNU BITS(8,11)

minutes units in BCD code

Definition at line 100 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD_MSKD BIT(31)

alarm date mask bit

Definition at line 110 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD_MSKH BIT(23)

alarm hour mask bit

Definition at line 106 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD_MSKM BIT(15)

alarm minutes mask bit

Definition at line 102 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD_MSKS BIT(7)

alarm second mask bit

Definition at line 99 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD_PM BIT(22)

AM/PM flag

Definition at line 105 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD_SCT BITS(4,6)

second tens in BCD code

Definition at line 98 of file gd32f3x0_rtc.h.

#define RTC_ALRM0TD_SCU BITS(0,3)

second units in BCD code

Definition at line 97 of file gd32f3x0_rtc.h.

#define RTC_ALRM0WF_TIMEOUT ((uint32_t)0x00008000U)

alarm configuration can be write flag timeout

Definition at line 451 of file gd32f3x0_rtc.h.

#define RTC_AM ((uint32_t)0x00000000U)

AM format

Definition at line 247 of file gd32f3x0_rtc.h.

#define RTC_APR ((uint8_t)0x04U)

April

Definition at line 259 of file gd32f3x0_rtc.h.

#define RTC_AUG ((uint8_t)0x08U)

August

Definition at line 263 of file gd32f3x0_rtc.h.

#define RTC_BKP0 REG32((RTC) + 0x50U)

RTC backup 0 register

Definition at line 36 of file gd32f3x0_rtc.h.

#define RTC_BKP0_DATA BITS(0,31)

backup domain registers

Definition at line 170 of file gd32f3x0_rtc.h.

#define RTC_BKP1 REG32((RTC) + 0x54U)

RTC backup 1 register

Definition at line 37 of file gd32f3x0_rtc.h.

#define RTC_BKP1_DATA BITS(0,31)

backup domain registers

Definition at line 173 of file gd32f3x0_rtc.h.

#define RTC_BKP2 REG32((RTC) + 0x58U)

RTC backup 2 register

Definition at line 38 of file gd32f3x0_rtc.h.

#define RTC_BKP2_DATA BITS(0,31)

backup domain registers

Definition at line 176 of file gd32f3x0_rtc.h.

#define RTC_BKP3 REG32((RTC) + 0x5CU)

RTC backup 3 register

Definition at line 39 of file gd32f3x0_rtc.h.

#define RTC_BKP3_DATA BITS(0,31)

backup domain registers

Definition at line 179 of file gd32f3x0_rtc.h.

#define RTC_BKP4 REG32((RTC) + 0x60U)

RTC backup 4 register

Definition at line 40 of file gd32f3x0_rtc.h.

#define RTC_BKP4_DATA BITS(0,31)

backup domain registers

Definition at line 182 of file gd32f3x0_rtc.h.

#define RTC_CALIBRATION_1HZ RTC_CTL_COEN | RTC_CTL_COS

calibration output of 1Hz is enable

Definition at line 288 of file gd32f3x0_rtc.h.

#define RTC_CALIBRATION_512HZ RTC_CTL_COEN

calibration output of 512Hz is enable

Definition at line 287 of file gd32f3x0_rtc.h.

#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U)

no effect

Definition at line 371 of file gd32f3x0_rtc.h.

#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI

increase RTC frequency by 488.5ppm

Definition at line 370 of file gd32f3x0_rtc.h.

#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16

2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz

Definition at line 367 of file gd32f3x0_rtc.h.

#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U)

2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz

Definition at line 366 of file gd32f3x0_rtc.h.

#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8

2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz

Definition at line 368 of file gd32f3x0_rtc.h.

#define RTC_CTL REG32((RTC) + 0x08U)

RTC control register

Definition at line 23 of file gd32f3x0_rtc.h.

#define RTC_CTL_A1H BIT(16)

add 1 hour(summer time change)

Definition at line 70 of file gd32f3x0_rtc.h.

#define RTC_CTL_ALRM0EN BIT(8)

alarm function enable

Definition at line 66 of file gd32f3x0_rtc.h.

#define RTC_CTL_ALRM0IE BIT(12)

RTC alarm interrupt enable

Definition at line 68 of file gd32f3x0_rtc.h.

#define RTC_CTL_BPSHAD BIT(5)

shadow registers bypass control

Definition at line 64 of file gd32f3x0_rtc.h.

#define RTC_CTL_COEN BIT(23)

calibration output enable

Definition at line 76 of file gd32f3x0_rtc.h.

#define RTC_CTL_COS BIT(19)

calibration output selection

Definition at line 73 of file gd32f3x0_rtc.h.

#define RTC_CTL_CS BIT(6)

display format of clock system

Definition at line 65 of file gd32f3x0_rtc.h.

#define RTC_CTL_DSM BIT(18)

daylight saving mark

Definition at line 72 of file gd32f3x0_rtc.h.

#define RTC_CTL_OPOL BIT(20)

output polarity

Definition at line 74 of file gd32f3x0_rtc.h.

#define RTC_CTL_OS BITS(21,22)

output selection

Definition at line 75 of file gd32f3x0_rtc.h.

#define RTC_CTL_REFEN BIT(4)

reference clock detection function enable

Definition at line 63 of file gd32f3x0_rtc.h.

#define RTC_CTL_S1H BIT(17)

subtract 1 hour(winter time change)

Definition at line 71 of file gd32f3x0_rtc.h.

#define RTC_CTL_TSEG BIT(3)

valid event edge of time-stamp

Definition at line 62 of file gd32f3x0_rtc.h.

#define RTC_CTL_TSEN BIT(11)

time-stamp function enable

Definition at line 67 of file gd32f3x0_rtc.h.

#define RTC_CTL_TSIE BIT(15)

time-stamp interrupt enable

Definition at line 69 of file gd32f3x0_rtc.h.

#define RTC_DATE REG32((RTC) + 0x04U)

RTC date register

Definition at line 22 of file gd32f3x0_rtc.h.

#define RTC_DATE_DAYT BITS(4,5)

date tens in BCD code

Definition at line 54 of file gd32f3x0_rtc.h.

#define RTC_DATE_DAYU BITS(0,3)

date units in BCD code

Definition at line 53 of file gd32f3x0_rtc.h.

#define RTC_DATE_DOW BITS(13,15)

day of week units

Definition at line 57 of file gd32f3x0_rtc.h.

#define RTC_DATE_MONT BIT(12)

month tens in BCD code

Definition at line 56 of file gd32f3x0_rtc.h.

#define RTC_DATE_MONU BITS(8,11)

month units in BCD code

Definition at line 55 of file gd32f3x0_rtc.h.

#define RTC_DATE_RESET ((uint32_t)0x00002101U)

RTC_DATE register reset value

Definition at line 442 of file gd32f3x0_rtc.h.

#define RTC_DATE_YRT BITS(20,23)

year tens in BCD code

Definition at line 59 of file gd32f3x0_rtc.h.

#define RTC_DATE_YRU BITS(16,19)

year units in BCD code

Definition at line 58 of file gd32f3x0_rtc.h.

#define RTC_DEC ((uint8_t)0x12U)

December

Definition at line 267 of file gd32f3x0_rtc.h.

#define RTC_DTS REG32((RTC) + 0x34U)

RTC date of timestamp register

Definition at line 31 of file gd32f3x0_rtc.h.

#define RTC_DTS_DAYT BITS(4,5)

date tens in BCD code

Definition at line 133 of file gd32f3x0_rtc.h.

#define RTC_DTS_DAYU BITS(0,3)

date units in BCD code

Definition at line 132 of file gd32f3x0_rtc.h.

#define RTC_DTS_DOW BITS(13,15)

day of week units

Definition at line 136 of file gd32f3x0_rtc.h.

#define RTC_DTS_MONT BIT(12)

month tens in BCD code

Definition at line 135 of file gd32f3x0_rtc.h.

#define RTC_DTS_MONU BITS(8,11)

month units in BCD code

Definition at line 134 of file gd32f3x0_rtc.h.

#define RTC_FEB ((uint8_t)0x02U)

February

Definition at line 257 of file gd32f3x0_rtc.h.

#define RTC_FLAG_ALARM0 RTC_STAT_ALRM0F

alarm event flag

Definition at line 459 of file gd32f3x0_rtc.h.

#define RTC_FLAG_ALARM0_WRITTEN RTC_STAT_ALRM0WF

alarm written available flag

Definition at line 464 of file gd32f3x0_rtc.h.

#define RTC_FLAG_INIT RTC_STAT_INITF

init mode event flag

Definition at line 460 of file gd32f3x0_rtc.h.

#define RTC_FLAG_RECALIBRATION RTC_STAT_SCPF

recalibration pending flag

Definition at line 454 of file gd32f3x0_rtc.h.

#define RTC_FLAG_RSYN RTC_STAT_RSYNF

registers synchronized flag

Definition at line 461 of file gd32f3x0_rtc.h.

#define RTC_FLAG_SHIFT RTC_STAT_SOPF

shift operation pending flag

Definition at line 463 of file gd32f3x0_rtc.h.

#define RTC_FLAG_TAMP0 RTC_STAT_TP0F

tamper 0 event flag

Definition at line 456 of file gd32f3x0_rtc.h.

#define RTC_FLAG_TAMP1 RTC_STAT_TP1F

tamper 1 event flag

Definition at line 455 of file gd32f3x0_rtc.h.

#define RTC_FLAG_TIMESTAMP RTC_STAT_TSF

time-stamp event flag

Definition at line 458 of file gd32f3x0_rtc.h.

#define RTC_FLAG_TIMESTAMP_OVERFLOW RTC_STAT_TSOVRF

time-stamp overflow event flag

Definition at line 457 of file gd32f3x0_rtc.h.

#define RTC_FLAG_YCM RTC_STAT_YCM

year parameter configured event flag

Definition at line 462 of file gd32f3x0_rtc.h.

#define RTC_FLT_2S TAMP_FLT(1)

detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event

Definition at line 386 of file gd32f3x0_rtc.h.

#define RTC_FLT_4S TAMP_FLT(2)

detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event

Definition at line 387 of file gd32f3x0_rtc.h.

#define RTC_FLT_8S TAMP_FLT(3)

detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event

Definition at line 388 of file gd32f3x0_rtc.h.

#define RTC_FLT_EDGE TAMP_FLT(0)

detecting tamper event using edge mode. precharge duration is disabled automatically

Definition at line 385 of file gd32f3x0_rtc.h.

#define RTC_FREQ_DIV1024 TAMP_FREQ(5)

sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz)

Definition at line 380 of file gd32f3x0_rtc.h.

#define RTC_FREQ_DIV16384 TAMP_FREQ(1)

sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz)

Definition at line 376 of file gd32f3x0_rtc.h.

#define RTC_FREQ_DIV2048 TAMP_FREQ(4)

sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz)

Definition at line 379 of file gd32f3x0_rtc.h.

#define RTC_FREQ_DIV256 TAMP_FREQ(7)

sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz)

Definition at line 382 of file gd32f3x0_rtc.h.

#define RTC_FREQ_DIV32768 TAMP_FREQ(0)

sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz)

Definition at line 375 of file gd32f3x0_rtc.h.

#define RTC_FREQ_DIV4096 TAMP_FREQ(3)

sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz)

Definition at line 378 of file gd32f3x0_rtc.h.

#define RTC_FREQ_DIV512 TAMP_FREQ(6)

sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz)

Definition at line 381 of file gd32f3x0_rtc.h.

#define RTC_FREQ_DIV8192 TAMP_FREQ(2)

sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz)

Definition at line 377 of file gd32f3x0_rtc.h.

#define RTC_FRIDAY ((uint8_t)0x05U)

Friday

Definition at line 275 of file gd32f3x0_rtc.h.

#define RTC_HRFC REG32((RTC) + 0x3CU)

RTC high resolution frequency compensation registor

Definition at line 33 of file gd32f3x0_rtc.h.

#define RTC_HRFC_CMSK BITS(0,8)

calibration mask number

Definition at line 142 of file gd32f3x0_rtc.h.

#define RTC_HRFC_CWND16 BIT(13)

calibration window select 16 seconds

Definition at line 143 of file gd32f3x0_rtc.h.

#define RTC_HRFC_CWND8 BIT(14)

calibration window select 16 seconds

Definition at line 144 of file gd32f3x0_rtc.h.

#define RTC_HRFC_FREQI BIT(15)

increase RTC frequency by 488.5ppm

Definition at line 145 of file gd32f3x0_rtc.h.

#define RTC_HRFC_TIMEOUT ((uint32_t)0x00001000U)

recalibration pending flag timeout

Definition at line 449 of file gd32f3x0_rtc.h.

#define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U)

initialization state flag timeout

Definition at line 447 of file gd32f3x0_rtc.h.

#define RTC_INT_ALARM RTC_CTL_ALRM0IE

RTC alarm interrupt enable

Definition at line 432 of file gd32f3x0_rtc.h.

#define RTC_INT_TAMP RTC_TAMP_TPIE

tamper detection interrupt enable

Definition at line 433 of file gd32f3x0_rtc.h.

#define RTC_INT_TIMESTAMP RTC_CTL_TSIE

time-stamp interrupt enable

Definition at line 431 of file gd32f3x0_rtc.h.

#define RTC_JAN ((uint8_t)0x01U)

Janurary

Definition at line 256 of file gd32f3x0_rtc.h.

#define RTC_JUL ((uint8_t)0x07U)

July

Definition at line 262 of file gd32f3x0_rtc.h.

#define RTC_JUN ((uint8_t)0x06U)

June

Definition at line 261 of file gd32f3x0_rtc.h.

#define RTC_LOCK_KEY ((uint8_t)0xFFU)

RTC lock key

Definition at line 438 of file gd32f3x0_rtc.h.

#define RTC_MAR ((uint8_t)0x03U)

March

Definition at line 258 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_0_14 ALRM0SS_MASKSSC(0)

mask alarm subsecond configuration

Definition at line 413 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_10_14 ALRM0SS_MASKSSC(10)

mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared

Definition at line 423 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_11_14 ALRM0SS_MASKSSC(11)

mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared

Definition at line 424 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_12_14 ALRM0SS_MASKSSC(12)

mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared

Definition at line 425 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_13_14 ALRM0SS_MASKSSC(13)

mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared

Definition at line 426 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_14 ALRM0SS_MASKSSC(14)

mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared

Definition at line 427 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_1_14 ALRM0SS_MASKSSC(1)

mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared

Definition at line 414 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_2_14 ALRM0SS_MASKSSC(2)

mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared

Definition at line 415 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_3_14 ALRM0SS_MASKSSC(3)

mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared

Definition at line 416 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_4_14 ALRM0SS_MASKSSC(4)

mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared

Definition at line 417 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_5_14 ALRM0SS_MASKSSC(5)

mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared

Definition at line 418 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_6_14 ALRM0SS_MASKSSC(6)

mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared

Definition at line 419 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_7_14 ALRM0SS_MASKSSC(7)

mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared

Definition at line 420 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_8_14 ALRM0SS_MASKSSC(8)

mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared

Definition at line 421 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_9_14 ALRM0SS_MASKSSC(9)

mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared

Definition at line 422 of file gd32f3x0_rtc.h.

#define RTC_MASKSSC_NONE ALRM0SS_MASKSSC(15)

mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared

Definition at line 428 of file gd32f3x0_rtc.h.

#define RTC_MAY ((uint8_t)0x05U)

May

Definition at line 260 of file gd32f3x0_rtc.h.

#define RTC_MONDAY ((uint8_t)0x01U)

Monday

Definition at line 271 of file gd32f3x0_rtc.h.

#define RTC_NOV ((uint8_t)0x11U)

November

Definition at line 266 of file gd32f3x0_rtc.h.

#define RTC_OCT ((uint8_t)0x10U)

October

Definition at line 265 of file gd32f3x0_rtc.h.

#define RTC_OS_DISABLE CTL_OS(0)

disable output RTC_ALARM

Definition at line 284 of file gd32f3x0_rtc.h.

#define RTC_OS_ENABLE CTL_OS(1)

enable alarm flag output

Definition at line 285 of file gd32f3x0_rtc.h.

#define RTC_PM RTC_TIME_PM

PM format

Definition at line 248 of file gd32f3x0_rtc.h.

#define RTC_PRCH_1C TAMP_PRCH(0)

1 RTC clock prechagre time before each sampling

Definition at line 391 of file gd32f3x0_rtc.h.

#define RTC_PRCH_2C TAMP_PRCH(1)

2 RTC clock prechagre time before each sampling

Definition at line 392 of file gd32f3x0_rtc.h.

#define RTC_PRCH_4C TAMP_PRCH(2)

4 RTC clock prechagre time before each sampling

Definition at line 393 of file gd32f3x0_rtc.h.

#define RTC_PRCH_8C TAMP_PRCH(3)

8 RTC clock prechagre time before each sampling

Definition at line 394 of file gd32f3x0_rtc.h.

#define RTC_PSC REG32((RTC) + 0x10U)

RTC time prescaler register

Definition at line 25 of file gd32f3x0_rtc.h.

#define RTC_PSC_FACTOR_A BITS(16,22)

asynchronous prescaler factor

Definition at line 94 of file gd32f3x0_rtc.h.

#define RTC_PSC_FACTOR_S BITS(0,14)

synchronous prescaler factor

Definition at line 93 of file gd32f3x0_rtc.h.

#define RTC_PSC_RESET ((uint32_t)0x007F00FFU)

RTC_PSC register reset value

Definition at line 444 of file gd32f3x0_rtc.h.

#define RTC_REGISTER_RESET ((uint32_t)0x00000000U)

RTC common register reset value

Definition at line 441 of file gd32f3x0_rtc.h.

#define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U)

register synchronization flag timeout

Definition at line 448 of file gd32f3x0_rtc.h.

#define RTC_SATURDAY ((uint8_t)0x06U)

Saturday

Definition at line 276 of file gd32f3x0_rtc.h.

#define RTC_SEP ((uint8_t)0x09U)

September

Definition at line 264 of file gd32f3x0_rtc.h.

#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U)

not add 1 second

Definition at line 337 of file gd32f3x0_rtc.h.

#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S

add one second to the clock

Definition at line 338 of file gd32f3x0_rtc.h.

#define RTC_SHIFTCTL REG32((RTC) + 0x2CU)

RTC shift function control register

Definition at line 29 of file gd32f3x0_rtc.h.

#define RTC_SHIFTCTL_A1S BIT(31)

one second add

Definition at line 120 of file gd32f3x0_rtc.h.

#define RTC_SHIFTCTL_SFS BITS(0,14)

subtract a fraction of a second

Definition at line 119 of file gd32f3x0_rtc.h.

#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U)

shift function operation pending flag timeout

Definition at line 450 of file gd32f3x0_rtc.h.

#define RTC_SS REG32((RTC) + 0x28U)

RTC sub second register

Definition at line 28 of file gd32f3x0_rtc.h.

#define RTC_SS_SSC BITS(0,15)

sub second value

Definition at line 116 of file gd32f3x0_rtc.h.

#define RTC_SSTS REG32((RTC) + 0x38U)

RTC sub second of timestamp register

Definition at line 32 of file gd32f3x0_rtc.h.

#define RTC_SSTS_SSC BITS(0,15)

timestamp sub second units

Definition at line 139 of file gd32f3x0_rtc.h.

#define RTC_STAT REG32((RTC) + 0x0CU)

RTC status register

Definition at line 24 of file gd32f3x0_rtc.h.

#define RTC_STAT_ALRM0F BIT(8)

alarm occurs flag

Definition at line 85 of file gd32f3x0_rtc.h.

#define RTC_STAT_ALRM0WF BIT(0)

alarm configuration can be write flag

Definition at line 79 of file gd32f3x0_rtc.h.

#define RTC_STAT_INITF BIT(6)

initialization state flag

Definition at line 83 of file gd32f3x0_rtc.h.

#define RTC_STAT_INITM BIT(7)

enter initialization mode

Definition at line 84 of file gd32f3x0_rtc.h.

#define RTC_STAT_RESET ((uint32_t)0x00000007U)

RTC_STAT register reset value

Definition at line 443 of file gd32f3x0_rtc.h.

#define RTC_STAT_RSYNF BIT(5)

register synchronization flag

Definition at line 82 of file gd32f3x0_rtc.h.

#define RTC_STAT_SCPF BIT(16)

recalibration pending flag

Definition at line 90 of file gd32f3x0_rtc.h.

#define RTC_STAT_SOPF BIT(3)

shift function operation pending flag

Definition at line 80 of file gd32f3x0_rtc.h.

#define RTC_STAT_TP0F BIT(13)

RTC tamp 0 detected flag

Definition at line 88 of file gd32f3x0_rtc.h.

#define RTC_STAT_TP1F BIT(14)

RTC tamp 1 detected flag

Definition at line 89 of file gd32f3x0_rtc.h.

#define RTC_STAT_TSF BIT(11)

time-stamp flag

Definition at line 86 of file gd32f3x0_rtc.h.

#define RTC_STAT_TSOVRF BIT(12)

time-stamp overflow flag

Definition at line 87 of file gd32f3x0_rtc.h.

#define RTC_STAT_YCM BIT(4)

year configuration mark status flag

Definition at line 81 of file gd32f3x0_rtc.h.

#define RTC_SUNDAY ((uint8_t)0x07U)

Sunday

Definition at line 277 of file gd32f3x0_rtc.h.

#define RTC_TAMP REG32((RTC) + 0x40U)

RTC tamper register

Definition at line 34 of file gd32f3x0_rtc.h.

#define RTC_TAMP_DISPU BIT(15)

RTC tamp x pull up disable bit

Definition at line 157 of file gd32f3x0_rtc.h.

#define RTC_TAMP_FLT BITS(11,12)

RTC tamp x filter count setting

Definition at line 155 of file gd32f3x0_rtc.h.

#define RTC_TAMP_FREQ BITS(8,10)

sample frequency of tamper event detection

Definition at line 154 of file gd32f3x0_rtc.h.

#define RTC_TAMP_PC13MDE BIT(19)

PC13 mode

Definition at line 159 of file gd32f3x0_rtc.h.

#define RTC_TAMP_PC13VAL BIT(18)

alarm output type control/PC13 output value

Definition at line 158 of file gd32f3x0_rtc.h.

#define RTC_TAMP_PC14MDE BIT(21)

PC14 mode

Definition at line 161 of file gd32f3x0_rtc.h.

#define RTC_TAMP_PC14VAL BIT(20)

PC14 output value

Definition at line 160 of file gd32f3x0_rtc.h.

#define RTC_TAMP_PC15MDE BIT(23)

PC15 mode

Definition at line 163 of file gd32f3x0_rtc.h.

#define RTC_TAMP_PC15VAL BIT(22)

PC15 output value

Definition at line 162 of file gd32f3x0_rtc.h.

#define RTC_TAMP_PRCH BITS(13,14)

precharge duration time of RTC tamp x

Definition at line 156 of file gd32f3x0_rtc.h.

#define RTC_TAMP_TP0EG BIT(1)

tamper 0 event trigger edge for RTC tamp 0 input

Definition at line 149 of file gd32f3x0_rtc.h.

#define RTC_TAMP_TP0EN BIT(0)

tamper 0 detection enable

Definition at line 148 of file gd32f3x0_rtc.h.

#define RTC_TAMP_TP1EG BIT(4)

tamper 1 event trigger edge for RTC tamp 1 input

Definition at line 152 of file gd32f3x0_rtc.h.

#define RTC_TAMP_TP1EN BIT(3)

tamper 1 detection enable

Definition at line 151 of file gd32f3x0_rtc.h.

#define RTC_TAMP_TPIE BIT(2)

tamper detection interrupt enable

Definition at line 150 of file gd32f3x0_rtc.h.

#define RTC_TAMP_TPTS BIT(7)

make tamper function used for timestamp function

Definition at line 153 of file gd32f3x0_rtc.h.

#define RTC_TAMPER0 RTC_TAMP_TP0EN

tamper 0 detection enable

Definition at line 396 of file gd32f3x0_rtc.h.

#define RTC_TAMPER1 RTC_TAMP_TP1EN

tamper 1 detection enable

Definition at line 397 of file gd32f3x0_rtc.h.

#define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG

tamper detection is in falling edge mode

Definition at line 400 of file gd32f3x0_rtc.h.

#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U)

tamper detection is in rising edge mode

Definition at line 399 of file gd32f3x0_rtc.h.

#define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG

tamper detection is in high level mode

Definition at line 402 of file gd32f3x0_rtc.h.

#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U)

tamper detection is in low level mode

Definition at line 401 of file gd32f3x0_rtc.h.

#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */

Definition at line 404 of file gd32f3x0_rtc.h.

#define RTC_THURSDAY ((uint8_t)0x04U)

Thursday

Definition at line 274 of file gd32f3x0_rtc.h.

#define RTC_TIME REG32((RTC) + 0x00U)

RTC time of day register

Definition at line 21 of file gd32f3x0_rtc.h.

#define RTC_TIME_HRT BITS(20,21)

hour tens in BCD code

Definition at line 49 of file gd32f3x0_rtc.h.

#define RTC_TIME_HRU BITS(16,19)

hour units in BCD code

Definition at line 48 of file gd32f3x0_rtc.h.

#define RTC_TIME_MNT BITS(12,14)

minute tens in BCD code

Definition at line 47 of file gd32f3x0_rtc.h.

#define RTC_TIME_MNU BITS(8,11)

minute units in BCD code

Definition at line 46 of file gd32f3x0_rtc.h.

#define RTC_TIME_PM BIT(22)

AM/PM notation

Definition at line 50 of file gd32f3x0_rtc.h.

#define RTC_TIME_SCT BITS(4,6)

second tens in BCD code

Definition at line 45 of file gd32f3x0_rtc.h.

#define RTC_TIME_SCU BITS(0,3)

second units in BCD code

Definition at line 44 of file gd32f3x0_rtc.h.

#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG

falling edge is valid event edge for time-stamp event

Definition at line 296 of file gd32f3x0_rtc.h.

#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U)

rising edge is valid event edge for time-stamp event

Definition at line 295 of file gd32f3x0_rtc.h.

#define RTC_TTS REG32((RTC) + 0x30U)

RTC time of timestamp register

Definition at line 30 of file gd32f3x0_rtc.h.

#define RTC_TTS_HRT BITS(20,21)

hour tens in BCD code

Definition at line 128 of file gd32f3x0_rtc.h.

#define RTC_TTS_HRU BITS(16,19)

hour units in BCD code

Definition at line 127 of file gd32f3x0_rtc.h.

#define RTC_TTS_MNT BITS(12,14)

minute tens in BCD code

Definition at line 126 of file gd32f3x0_rtc.h.

#define RTC_TTS_MNU BITS(8,11)

minute units in BCD code

Definition at line 125 of file gd32f3x0_rtc.h.

#define RTC_TTS_PM BIT(22)

AM/PM notation

Definition at line 129 of file gd32f3x0_rtc.h.

#define RTC_TTS_SCT BITS(4,6)

second units in BCD code

Definition at line 124 of file gd32f3x0_rtc.h.

#define RTC_TTS_SCU BITS(0,3)

second units in BCD code

Definition at line 123 of file gd32f3x0_rtc.h.

#define RTC_TUESDAY ((uint8_t)0x02U)

Tuesday

Definition at line 272 of file gd32f3x0_rtc.h.

#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU)

RTC unlock key1

Definition at line 436 of file gd32f3x0_rtc.h.

#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U)

RTC unlock key2

Definition at line 437 of file gd32f3x0_rtc.h.

#define RTC_WEDSDAY ((uint8_t)0x03U)

Wednesday

Definition at line 273 of file gd32f3x0_rtc.h.

#define RTC_WPK REG32((RTC) + 0x24U)

RTC write protection key register

Definition at line 27 of file gd32f3x0_rtc.h.

#define RTC_WPK_WPK BITS(0,7)

key for write protection

Definition at line 113 of file gd32f3x0_rtc.h.

#define SHIFTCTL_SFS ( regval ) (BITS(0,14) & ((uint32_t)(regval) << 0U))

write value to RTC_SHIFTCTL_SFS bit field

Definition at line 335 of file gd32f3x0_rtc.h.

#define SS_SSC ( regval ) (BITS(0,15) & ((uint32_t)(regval) << 0U))

write value to RTC_SS_SSC bit field

Definition at line 332 of file gd32f3x0_rtc.h.

#define SSTS_SSC ( regval ) (BITS(0,15) & ((uint32_t)(regval) << 0U))

write value to RTC_SSTS_SSC bit field

Definition at line 361 of file gd32f3x0_rtc.h.

#define TAMP_FLT ( regval ) (BITS(11,12) & ((uint32_t)(regval) << 11U))

write value to RTC_TAMP_FLT bit field

Definition at line 384 of file gd32f3x0_rtc.h.

#define TAMP_FREQ ( regval ) (BITS(8,10) & ((uint32_t)(regval) << 8U))

write value to RTC_TAMP_FREQ bit field

Definition at line 374 of file gd32f3x0_rtc.h.

#define TAMP_PRCH ( regval ) (BITS(13,14) & ((uint32_t)(regval) << 13U))

write value to RTC_TAMP_PRCH bit field

Definition at line 390 of file gd32f3x0_rtc.h.

#define TIME_HR ( regval ) (BITS(16,21) & ((uint32_t)(regval) << 16U))

write value to RTC_TIME_HR bit field

Definition at line 244 of file gd32f3x0_rtc.h.

#define TIME_MN ( regval ) (BITS(8,14) & ((uint32_t)(regval) << 8U))

write value to RTC_TIME_MN bit field

Definition at line 241 of file gd32f3x0_rtc.h.

#define TIME_SC ( regval ) (BITS(0,6) & ((uint32_t)(regval) << 0U))

write value to RTC_TIME_SC bit field

Definition at line 238 of file gd32f3x0_rtc.h.

#define TTS_HR ( regval ) (BITS(16,21) & ((uint32_t)(regval) << 16U))

write value to RTC_TTS_HR bit field

Definition at line 347 of file gd32f3x0_rtc.h.

#define TTS_MN ( regval ) (BITS(8,14) & ((uint32_t)(regval) << 8U))

write value to RTC_TTS_MN bit field

Definition at line 344 of file gd32f3x0_rtc.h.

#define TTS_SC ( regval ) (BITS(0,6) & ((uint32_t)(regval) << 0U))

write value to RTC_TTS_SC bit field

Definition at line 341 of file gd32f3x0_rtc.h.

#define WPK_WPK ( regval ) (BITS(0,7) & ((uint32_t)(regval) << 0U))

write value to RTC_WPK_WPK bit field

Definition at line 329 of file gd32f3x0_rtc.h.

Function Documentation

void rtc_alarm_config ( rtc_alarm_struct * rtc_alarm_time )

configure RTC alarm

Parameters
[in] | rtc_alarm_time | pointer to a rtc_alarm_struct structure which contains parameters for RTC alarm configuration members of the structure and the member values are shown as below: rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format rtc_alarm_minute: 0x0 - 0x59(BCD format) rtc_alarm_second: 0x0 - 0x59(BCD format) rtc_am_pm: RTC_AM, RTC_PM
[out] | none
Return values
none

Definition at line 291 of file gd32f3x0_rtc.c.

292 {
293 uint32_t reg_alrm0td = 0x00U;
294
295 reg_alrm0td = (rtc_alarm_time->rtc_alarm_mask | \
296 rtc_alarm_time->rtc_weekday_or_date | \
297 rtc_alarm_time->rtc_am_pm | \
298 ALRM0TD_DAY(rtc_alarm_time->rtc_alarm_day) | \
299 ALRM0TD_HR(rtc_alarm_time->rtc_alarm_hour) | \
300 ALRM0TD_MN(rtc_alarm_time->rtc_alarm_minute) | \
301 ALRM0TD_SC(rtc_alarm_time->rtc_alarm_second));
302
303 /* disable the write protection */
304 RTC_WPK = RTC_UNLOCK_KEY1;
305 RTC_WPK = RTC_UNLOCK_KEY2;
306
307 RTC_ALRM0TD = (uint32_t)reg_alrm0td;
308
309 /* enable the write protection */
310 RTC_WPK = RTC_LOCK_KEY;
311 }
rtc_alarm_struct::rtc_alarm_hour
uint8_t rtc_alarm_hour
Definition: gd32f3x0_rtc.h:207
ALRM0TD_HR
#define ALRM0TD_HR(regval)
Definition: gd32f3x0_rtc.h:312
rtc_alarm_struct::rtc_alarm_mask
uint32_t rtc_alarm_mask
Definition: gd32f3x0_rtc.h:204
ALRM0TD_MN
#define ALRM0TD_MN(regval)
Definition: gd32f3x0_rtc.h:309
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
rtc_alarm_struct::rtc_alarm_day
uint8_t rtc_alarm_day
Definition: gd32f3x0_rtc.h:206
RTC_ALRM0TD
#define RTC_ALRM0TD
Definition: gd32f3x0_rtc.h:26
ALRM0TD_DAY
#define ALRM0TD_DAY(regval)
Definition: gd32f3x0_rtc.h:315
ALRM0TD_SC
#define ALRM0TD_SC(regval)
Definition: gd32f3x0_rtc.h:306
rtc_alarm_struct::rtc_alarm_minute
uint8_t rtc_alarm_minute
Definition: gd32f3x0_rtc.h:208
rtc_alarm_struct::rtc_alarm_second
uint8_t rtc_alarm_second
Definition: gd32f3x0_rtc.h:209
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
ErrStatus rtc_alarm_disable ( void )

disable RTC alarm

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 372 of file gd32f3x0_rtc.c.

373 {
374 volatile uint32_t time_index = RTC_ALRM0WF_TIMEOUT;
375 ErrStatus error_status = ERROR;
376 uint32_t flag_status = RESET;
377
378 /* disable the write protection */
379 RTC_WPK = RTC_UNLOCK_KEY1;
380 RTC_WPK = RTC_UNLOCK_KEY2;
381
382 /* clear the state of alarm */
383 RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN);
384
385 /* wait until ALRM0WF flag to be set after the alarm is disabled */
386 do{
387 flag_status = RTC_STAT & RTC_STAT_ALRM0WF;
388 }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status));
389
390 if((uint32_t)RESET != flag_status){
391 error_status = SUCCESS;
392 }
393
394 /* enable the write protection */
395 RTC_WPK = RTC_LOCK_KEY;
396
397 return error_status;
398 }
RTC_CTL_ALRM0EN
#define RTC_CTL_ALRM0EN
Definition: gd32f3x0_rtc.h:66
RTC_STAT_ALRM0WF
#define RTC_STAT_ALRM0WF
Definition: gd32f3x0_rtc.h:79
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
RTC_ALRM0WF_TIMEOUT
#define RTC_ALRM0WF_TIMEOUT
Definition: gd32f3x0_rtc.h:451
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_alarm_enable ( void )

enable RTC alarm

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 354 of file gd32f3x0_rtc.c.

355 {
356 /* disable the write protection */
357 RTC_WPK = RTC_UNLOCK_KEY1;
358 RTC_WPK = RTC_UNLOCK_KEY2;
359
360 RTC_CTL |= RTC_CTL_ALRM0EN;
361
362 /* enable the write protection */
363 RTC_WPK = RTC_LOCK_KEY;
364 }
RTC_CTL_ALRM0EN
#define RTC_CTL_ALRM0EN
Definition: gd32f3x0_rtc.h:66
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_alarm_get ( rtc_alarm_struct * rtc_alarm_time )

get RTC alarm

Parameters
[in] | none
[out] | rtc_alarm_time | pointer to a rtc_alarm_struct structure which contains parameters for RTC alarm configuration members of the structure and the member values are shown as below: rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format rtc_alarm_minute: 0x0 - 0x59(BCD format) rtc_alarm_second: 0x0 - 0x59(BCD format) rtc_am_pm: RTC_AM, RTC_PM
Return values
none

Definition at line 418 of file gd32f3x0_rtc.c.

419 {
420 uint32_t reg_alrm0td = 0x00U;
421
422 /* get the value of RTC_ALRM0TD register */
423 reg_alrm0td = RTC_ALRM0TD;
424
425 /* get alarm parameters and construct the rtc_alarm_struct structure */
426 rtc_alarm_time->rtc_alarm_mask = reg_alrm0td & RTC_ALARM_ALL_MASK;
427 rtc_alarm_time->rtc_am_pm = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_PM);
428 rtc_alarm_time->rtc_weekday_or_date = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_DOWS);
429 rtc_alarm_time->rtc_alarm_day = (uint8_t)GET_ALRM0TD_DAY(reg_alrm0td);
430 rtc_alarm_time->rtc_alarm_hour = (uint8_t)GET_ALRM0TD_HR(reg_alrm0td);
431 rtc_alarm_time->rtc_alarm_minute = (uint8_t)GET_ALRM0TD_MN(reg_alrm0td);
432 rtc_alarm_time->rtc_alarm_second = (uint8_t)GET_ALRM0TD_SC(reg_alrm0td);
433 }
GET_ALRM0TD_SC
#define GET_ALRM0TD_SC(regval)
Definition: gd32f3x0_rtc.h:307
rtc_alarm_struct::rtc_alarm_hour
uint8_t rtc_alarm_hour
Definition: gd32f3x0_rtc.h:207
RTC_ALRM0TD_PM
#define RTC_ALRM0TD_PM
Definition: gd32f3x0_rtc.h:105
GET_ALRM0TD_MN
#define GET_ALRM0TD_MN(regval)
Definition: gd32f3x0_rtc.h:310
rtc_alarm_struct::rtc_alarm_mask
uint32_t rtc_alarm_mask
Definition: gd32f3x0_rtc.h:204
RTC_ALRM0TD_DOWS
#define RTC_ALRM0TD_DOWS
Definition: gd32f3x0_rtc.h:109
rtc_alarm_struct::rtc_alarm_day
uint8_t rtc_alarm_day
Definition: gd32f3x0_rtc.h:206
RTC_ALRM0TD
#define RTC_ALRM0TD
Definition: gd32f3x0_rtc.h:26
rtc_alarm_struct::rtc_alarm_minute
uint8_t rtc_alarm_minute
Definition: gd32f3x0_rtc.h:208
rtc_alarm_struct::rtc_weekday_or_date
uint32_t rtc_weekday_or_date
Definition: gd32f3x0_rtc.h:205
GET_ALRM0TD_DAY
#define GET_ALRM0TD_DAY(regval)
Definition: gd32f3x0_rtc.h:316
RTC_ALARM_ALL_MASK
#define RTC_ALARM_ALL_MASK
Definition: gd32f3x0_rtc.h:323
rtc_alarm_struct::rtc_alarm_second
uint8_t rtc_alarm_second
Definition: gd32f3x0_rtc.h:209
rtc_alarm_struct::rtc_am_pm
uint32_t rtc_am_pm
Definition: gd32f3x0_rtc.h:210
GET_ALRM0TD_HR
#define GET_ALRM0TD_HR(regval)
Definition: gd32f3x0_rtc.h:313
void rtc_alarm_subsecond_config | ( | uint32_t | mask_subsecond,
 |  | uint32_t | subsecond
 | ) |  |

configure subsecond of RTC alarm

Parameters
[in] mask_subsecond alarm subsecond mask
  • RTC_MASKSSC_0_14: mask alarm subsecond configuration
  • RTC_MASKSSC_1_14: mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared
  • RTC_MASKSSC_2_14: mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared
  • RTC_MASKSSC_3_14: mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared
  • RTC_MASKSSC_4_14: mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared
  • RTC_MASKSSC_5_14: mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared
  • RTC_MASKSSC_6_14: mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared
  • RTC_MASKSSC_7_14: mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared
  • RTC_MASKSSC_8_14: mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared
  • RTC_MASKSSC_9_14: mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared
  • RTC_MASKSSC_10_14: mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared
  • RTC_MASKSSC_11_14: mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared
  • RTC_MASKSSC_12_14: mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared
  • RTC_MASKSSC_13_14: mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared
  • RTC_MASKSSC_14: mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared
  • RTC_MASKSSC_NONE: mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared
[in] | subsecond | alarm subsecond value(0x000 - 0x7FFF)
[out] | none
Return values
none

Definition at line 336 of file gd32f3x0_rtc.c.

337 {
338 /* disable the write protection */
339 RTC_WPK = RTC_UNLOCK_KEY1;
340 RTC_WPK = RTC_UNLOCK_KEY2;
341
342 RTC_ALRM0SS = mask_subsecond | subsecond;
343
344 /* enable the write protection */
345 RTC_WPK = RTC_LOCK_KEY;
346 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_ALRM0SS
#define RTC_ALRM0SS
Definition: gd32f3x0_rtc.h:35
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
uint32_t rtc_alarm_subsecond_get ( void )

get RTC alarm subsecond

Parameters
[in] | none
[out] | none
Return values
RTC alarm subsecond value

Definition at line 441 of file gd32f3x0_rtc.c.

442 {
443 return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC));
444 }
RTC_ALRM0SS
#define RTC_ALRM0SS
Definition: gd32f3x0_rtc.h:35
RTC_ALRM0SS_SSC
#define RTC_ALRM0SS_SSC
Definition: gd32f3x0_rtc.h:166
void rtc_alter_output_config | ( | uint32_t | source,
 |  | uint32_t | mode
 | ) |  |

configure rtc alternate output source

Parameters
[in] source specify signal to output
  • RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC is the default value, output 512Hz signal
  • RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC is the default value, output 512Hz signal
  • RTC_ALARM_HIGH: when the alarm flag is set, the output pin is high
  • RTC_ALARM_LOW: when the Alarm flag is set, the output pin is low
[in] mode specify the output pin (PC13) mode when output alarm signal
  • RTC_ALARM_OUTPUT_OD: open drain mode
  • RTC_ALARM_OUTPUT_PP: push pull mode
[out] none
Return values
none

Definition at line 718 of file gd32f3x0_rtc.c.

719 {
720 /* disable the write protection */
721 RTC_WPK = RTC_UNLOCK_KEY1;
722 RTC_WPK = RTC_UNLOCK_KEY2;
723
724 RTC_CTL &= (uint32_t)~(RTC_CTL_COEN | RTC_CTL_OS | RTC_CTL_OPOL | RTC_CTL_COS);
725
726 RTC_CTL |= (uint32_t)(source);
727
728 /* alarm output */
729 if((uint32_t)RESET != (source & RTC_OS_ENABLE)){
730 RTC_TAMP &= (uint32_t)~(RTC_TAMP_PC13VAL);
731 RTC_TAMP |= (uint32_t)(mode);
732 }
733
734 /* enable the write protection */
735 RTC_WPK = RTC_LOCK_KEY;
736 }
RTC_CTL_COEN
#define RTC_CTL_COEN
Definition: gd32f3x0_rtc.h:76
RTC_CTL_OPOL
#define RTC_CTL_OPOL
Definition: gd32f3x0_rtc.h:74
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_TAMP
#define RTC_TAMP
Definition: gd32f3x0_rtc.h:34
RTC_CTL_OS
#define RTC_CTL_OS
Definition: gd32f3x0_rtc.h:75
RTC_TAMP_PC13VAL
#define RTC_TAMP_PC13VAL
Definition: gd32f3x0_rtc.h:158
RTC_OS_ENABLE
#define RTC_OS_ENABLE
Definition: gd32f3x0_rtc.h:285
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_CTL_COS
#define RTC_CTL_COS
Definition: gd32f3x0_rtc.h:73
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_bypass_shadow_disable ( void )

disable RTC bypass shadow registers function

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 782 of file gd32f3x0_rtc.c.

783 {
784 /* disable the write protection */
785 RTC_WPK = RTC_UNLOCK_KEY1;
786 RTC_WPK = RTC_UNLOCK_KEY2;
787
788 RTC_CTL &= (uint8_t)~RTC_CTL_BPSHAD;
789
790 /* enable the write protection */
791 RTC_WPK = RTC_LOCK_KEY;
792 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL_BPSHAD
#define RTC_CTL_BPSHAD
Definition: gd32f3x0_rtc.h:64
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_bypass_shadow_enable ( void )

enable RTC bypass shadow registers function

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 764 of file gd32f3x0_rtc.c.

765 {
766 /* disable the write protection */
767 RTC_WPK = RTC_UNLOCK_KEY1;
768 RTC_WPK = RTC_UNLOCK_KEY2;
769
770 RTC_CTL |= (uint8_t)RTC_CTL_BPSHAD;
771
772 /* enable the write protection */
773 RTC_WPK = RTC_LOCK_KEY;
774 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL_BPSHAD
#define RTC_CTL_BPSHAD
Definition: gd32f3x0_rtc.h:64
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
ErrStatus rtc_calibration_config | ( | uint32_t | window,
 |  | uint32_t | plus,
 |  | uint32_t | minus
 | ) |  |

configure RTC calibration register

Parameters
[in] window select calibration window
  • RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz
  • RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz
  • RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz
[in] plus add RTC clock or not
  • RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock
  • RTC_CALIBRATION_PLUS_RESET: no effect
[in] | minus | the RTC clock to minus during the calibration window(0x0 - 0x1FF)
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 903 of file gd32f3x0_rtc.c.

904 {
905 uint32_t time_index = RTC_HRFC_TIMEOUT;
906 ErrStatus error_status = ERROR;
907 uint32_t flag_status = RESET;
908
909 /* disable the write protection */
910 RTC_WPK = RTC_UNLOCK_KEY1;
911 RTC_WPK = RTC_UNLOCK_KEY2;
912
913 /* check if a calibration operation is ongoing */
914 do{
915 flag_status = RTC_STAT & RTC_STAT_SCPF;
916 }while((--time_index > 0x00U) && ((uint32_t)RESET != flag_status));
917
918 if((uint32_t)RESET == flag_status){
919 RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus));
920 error_status = SUCCESS;
921 }
922
923 /* enable the write protection */
924 RTC_WPK = RTC_LOCK_KEY;
925
926 return error_status;
927 }
RTC_HRFC_TIMEOUT
#define RTC_HRFC_TIMEOUT
Definition: gd32f3x0_rtc.h:449
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_HRFC
#define RTC_HRFC
Definition: gd32f3x0_rtc.h:33
RTC_STAT_SCPF
#define RTC_STAT_SCPF
Definition: gd32f3x0_rtc.h:90
HRFC_CMSK
#define HRFC_CMSK(regval)
Definition: gd32f3x0_rtc.h:364
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_current_time_get ( rtc_parameter_struct * rtc_initpara_struct )

get current time and date

Parameters
[in] | none
[out] | rtc_initpara_struct | pointer to a rtc_parameter_struct structure which contains parameters for initialization of the rtc peripheral members of the structure and the member values are shown as below: rtc_year: 0x0 - 0x99(BCD format) rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC rtc_date: 0x1 - 0x31(BCD format) rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose rtc_minute: 0x0 - 0x59(BCD format) rtc_second: 0x0 - 0x59(BCD format) rtc_factor_asyn: 0x0 - 0x7F rtc_factor_syn: 0x0 - 0x7FFF rtc_am_pm: RTC_AM, RTC_PM rtc_display_format: RTC_24HOUR, RTC_12HOUR
Return values
none

Definition at line 233 of file gd32f3x0_rtc.c.

234 {
235 uint32_t temp_tr = 0x00U, temp_dr = 0x00U, temp_pscr = 0x00U, temp_ctlr = 0x00U;
236
237 temp_tr = (uint32_t)RTC_TIME;
238 temp_dr = (uint32_t)RTC_DATE;
239 temp_pscr = (uint32_t)RTC_PSC;
240 temp_ctlr = (uint32_t)RTC_CTL;
241
242 /* get current time and construct rtc_parameter_struct structure */
243 rtc_initpara_struct->rtc_year = (uint8_t)GET_DATE_YR(temp_dr);
244 rtc_initpara_struct->rtc_month = (uint8_t)GET_DATE_MON(temp_dr);
245 rtc_initpara_struct->rtc_date = (uint8_t)GET_DATE_DAY(temp_dr);
246 rtc_initpara_struct->rtc_day_of_week = (uint8_t)GET_DATE_DOW(temp_dr);
247 rtc_initpara_struct->rtc_hour = (uint8_t)GET_TIME_HR(temp_tr);
248 rtc_initpara_struct->rtc_minute = (uint8_t)GET_TIME_MN(temp_tr);
249 rtc_initpara_struct->rtc_second = (uint8_t)GET_TIME_SC(temp_tr);
250 rtc_initpara_struct->rtc_factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr);
251 rtc_initpara_struct->rtc_factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr);
252 rtc_initpara_struct->rtc_am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM);
253 rtc_initpara_struct->rtc_display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS);
254 }
RTC_TIME
#define RTC_TIME
Definition: gd32f3x0_rtc.h:21
rtc_parameter_struct::rtc_minute
uint8_t rtc_minute
Definition: gd32f3x0_rtc.h:193
RTC_TIME_PM
#define RTC_TIME_PM
Definition: gd32f3x0_rtc.h:50
RTC_CTL_CS
#define RTC_CTL_CS
Definition: gd32f3x0_rtc.h:65
rtc_parameter_struct::rtc_year
uint8_t rtc_year
Definition: gd32f3x0_rtc.h:188
rtc_parameter_struct::rtc_am_pm
uint32_t rtc_am_pm
Definition: gd32f3x0_rtc.h:197
rtc_parameter_struct::rtc_display_format
uint32_t rtc_display_format
Definition: gd32f3x0_rtc.h:198
RTC_PSC
#define RTC_PSC
Definition: gd32f3x0_rtc.h:25
rtc_parameter_struct::rtc_date
uint8_t rtc_date
Definition: gd32f3x0_rtc.h:190
GET_TIME_HR
#define GET_TIME_HR(regval)
Definition: gd32f3x0_rtc.h:245
GET_DATE_DOW
#define GET_DATE_DOW(regval)
Definition: gd32f3x0_rtc.h:270
rtc_parameter_struct::rtc_hour
uint8_t rtc_hour
Definition: gd32f3x0_rtc.h:192
GET_PSC_FACTOR_S
#define GET_PSC_FACTOR_S(regval)
Definition: gd32f3x0_rtc.h:300
rtc_parameter_struct::rtc_second
uint8_t rtc_second
Definition: gd32f3x0_rtc.h:194
GET_DATE_YR
#define GET_DATE_YR(regval)
Definition: gd32f3x0_rtc.h:280
rtc_parameter_struct::rtc_day_of_week
uint8_t rtc_day_of_week
Definition: gd32f3x0_rtc.h:191
rtc_parameter_struct::rtc_factor_asyn
uint16_t rtc_factor_asyn
Definition: gd32f3x0_rtc.h:195
RTC_DATE
#define RTC_DATE
Definition: gd32f3x0_rtc.h:22
GET_PSC_FACTOR_A
#define GET_PSC_FACTOR_A(regval)
Definition: gd32f3x0_rtc.h:303
GET_TIME_MN
#define GET_TIME_MN(regval)
Definition: gd32f3x0_rtc.h:242
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
GET_DATE_MON
#define GET_DATE_MON(regval)
Definition: gd32f3x0_rtc.h:255
rtc_parameter_struct::rtc_factor_syn
uint16_t rtc_factor_syn
Definition: gd32f3x0_rtc.h:196
GET_TIME_SC
#define GET_TIME_SC(regval)
Definition: gd32f3x0_rtc.h:239
rtc_parameter_struct::rtc_month
uint8_t rtc_month
Definition: gd32f3x0_rtc.h:189
GET_DATE_DAY
#define GET_DATE_DAY(regval)
Definition: gd32f3x0_rtc.h:252
ErrStatus rtc_deinit ( void )

reset most of the RTC registers

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 20 of file gd32f3x0_rtc.c.

21 {
22 ErrStatus error_status = ERROR;
23
24 /* RTC_TAMP register is not under write protection */
25 RTC_TAMP = RTC_REGISTER_RESET;
26
27 /* disable the write protection */
28 RTC_WPK = RTC_UNLOCK_KEY1;
29 RTC_WPK = RTC_UNLOCK_KEY2;
30
31 /* reset RTC_CTL register, this can be done without the init mode */
32 RTC_CTL &= RTC_REGISTER_RESET;
33
34 /* enter init mode */
35 error_status = rtc_init_mode_enter();
36
37 if(ERROR != error_status){
38 /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition.
39 in order to read calendar from shadow register, not the real registers being reset */
40 RTC_TIME = RTC_REGISTER_RESET;
41 RTC_DATE = RTC_DATE_RESET;
42
43 RTC_PSC = RTC_PSC_RESET;
44
45 /* reset RTC_STAT register, also exit init mode.
46 at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */
47 RTC_STAT = RTC_STAT_RESET;
48
49 /* to write RTC_ALRM0SS register, ALRM0EN bit in RTC_CTL register should be reset as the condition */
50 RTC_ALRM0TD = RTC_REGISTER_RESET;
51 RTC_ALRM0SS = RTC_REGISTER_RESET;
52
53 /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */
54 RTC_SHIFTCTL = RTC_REGISTER_RESET;
55 RTC_HRFC = RTC_REGISTER_RESET;
56
57 error_status = rtc_register_sync_wait();
58 }
59
60 /* enable the write protection */
61 RTC_WPK = RTC_LOCK_KEY;
62
63 return error_status;
64 }
RTC_TIME
#define RTC_TIME
Definition: gd32f3x0_rtc.h:21
RTC_SHIFTCTL
#define RTC_SHIFTCTL
Definition: gd32f3x0_rtc.h:29
RTC_REGISTER_RESET
#define RTC_REGISTER_RESET
Definition: gd32f3x0_rtc.h:441
RTC_PSC_RESET
#define RTC_PSC_RESET
Definition: gd32f3x0_rtc.h:444
RTC_STAT_RESET
#define RTC_STAT_RESET
Definition: gd32f3x0_rtc.h:443
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_TAMP
#define RTC_TAMP
Definition: gd32f3x0_rtc.h:34
RTC_PSC
#define RTC_PSC
Definition: gd32f3x0_rtc.h:25
RTC_ALRM0SS
#define RTC_ALRM0SS
Definition: gd32f3x0_rtc.h:35
RTC_ALRM0TD
#define RTC_ALRM0TD
Definition: gd32f3x0_rtc.h:26
RTC_HRFC
#define RTC_HRFC
Definition: gd32f3x0_rtc.h:33
RTC_DATE_RESET
#define RTC_DATE_RESET
Definition: gd32f3x0_rtc.h:442
RTC_DATE
#define RTC_DATE
Definition: gd32f3x0_rtc.h:22
rtc_init_mode_enter
ErrStatus rtc_init_mode_enter(void)
enter RTC init mode
Definition: gd32f3x0_rtc.c:138
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
rtc_register_sync_wait
ErrStatus rtc_register_sync_wait(void)
wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers ...
Definition: gd32f3x0_rtc.c:180
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_flag_clear ( uint32_t flag )

clear specified flag

Parameters
[in] flag specify which flag to clear
  • RTC_FLAG_TAMP1: tamper 1 event flag
  • RTC_FLAG_TAMP0: tamper 0 event flag
  • RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag
  • RTC_FLAG_TIMESTAMP: time-stamp event flag
  • RTC_FLAG_ALARM0: alarm event flag
  • RTC_FLAG_RSYN: time and date registers synchronized event flag
[out] none
Return values
none

Definition at line 698 of file gd32f3x0_rtc.c.

699 {
700 RTC_STAT &= (uint32_t)(~flag);
701 }
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
FlagStatus rtc_flag_get ( uint32_t flag )

check specified flag

Parameters
[in] flag specify which flag to check
  • RTC_FLAG_RECALIBRATION: recalibration pending flag
  • RTC_FLAG_TAMP1: tamper 1 event flag
  • RTC_FLAG_TAMP0: tamper 0 event flag
  • RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag
  • RTC_FLAG_TIMESTAMP: time-stamp event flag
  • RTC_FLAG_ALARM0: alarm event flag
  • RTC_FLAG_INIT: init mode event flag
  • RTC_FLAG_RSYN: time and date registers synchronized event flag
  • RTC_FLAG_YCM: year parameter configured event flag
  • RTC_FLAG_SHIFT: shift operation pending flag
  • RTC_FLAG_ALARM0_WRITTEN: alarm writen available flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 676 of file gd32f3x0_rtc.c.

677 {
678 FlagStatus flag_state = RESET;
679
680 if((uint32_t)RESET != (RTC_STAT & flag)){
681 flag_state = SET;
682 }
683 return flag_state;
684 }
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
void rtc_hour_adjust ( uint32_t operation )

ajust the daylight saving time by adding or substracting one hour from the current time

Parameters
[in] operation hour ajustment operation
  • RTC_CTL_A1H: add one hour
  • RTC_CTL_S1H: substract one hour
[out] none
Return values
none

Definition at line 746 of file gd32f3x0_rtc.c.

747 {
748 /* disable the write protection */
749 RTC_WPK = RTC_UNLOCK_KEY1;
750 RTC_WPK = RTC_UNLOCK_KEY2;
751
752 RTC_CTL |= (uint32_t)(operation);
753
754 /* enable the write protection */
755 RTC_WPK = RTC_LOCK_KEY;
756 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
ErrStatus rtc_init ( rtc_parameter_struct * rtc_initpara_struct )

initialize RTC registers

Parameters
[in] | rtc_initpara_struct | pointer to a rtc_parameter_struct structure which contains parameters for initialization of the rtc peripheral members of the structure and the member values are shown as below: rtc_year: 0x0 - 0x99(BCD format) rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC rtc_date: 0x1 - 0x31(BCD format) rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose rtc_minute: 0x0 - 0x59(BCD format) rtc_second: 0x0 - 0x59(BCD format) rtc_factor_asyn: 0x0 - 0x7F rtc_factor_syn: 0x0 - 0x7FFF rtc_am_pm: RTC_AM, RTC_PM rtc_display_format: RTC_24HOUR, RTC_12HOUR
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 87 of file gd32f3x0_rtc.c.

88 {
89 ErrStatus error_status = ERROR;
90 uint32_t reg_time = 0x00U, reg_date = 0x00U;
91
92 reg_date = (DATE_YR(rtc_initpara_struct->rtc_year) | \
93 DATE_DOW(rtc_initpara_struct->rtc_day_of_week) | \
94 DATE_MON(rtc_initpara_struct->rtc_month) | \
95 DATE_DAY(rtc_initpara_struct->rtc_date));
96
97 reg_time = (rtc_initpara_struct->rtc_am_pm| \
98 TIME_HR(rtc_initpara_struct->rtc_hour) | \
99 TIME_MN(rtc_initpara_struct->rtc_minute) | \
100 TIME_SC(rtc_initpara_struct->rtc_second));
101
102 /* 1st: disable the write protection */
103 RTC_WPK = RTC_UNLOCK_KEY1;
104 RTC_WPK = RTC_UNLOCK_KEY2;
105
106 /* 2nd: enter init mode */
107 error_status = rtc_init_mode_enter();
108
109 if(ERROR != error_status){
110 RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->rtc_factor_asyn)| \
111 PSC_FACTOR_S(rtc_initpara_struct->rtc_factor_syn));
112
113 RTC_TIME = (uint32_t)reg_time;
114 RTC_DATE = (uint32_t)reg_date;
115
116 RTC_CTL &= (uint32_t)(~RTC_CTL_CS);
117 RTC_CTL |= rtc_initpara_struct->rtc_display_format;
118
119 /* 3rd: exit init mode */
120 rtc_init_mode_exit();
121
122 /* 4th: wait the RSYNF flag to set */
123 error_status = rtc_register_sync_wait();
124 }
125
126 /* 5th: enable the write protection */
127 RTC_WPK = RTC_LOCK_KEY;
128
129 return error_status;
130 }
RTC_TIME
#define RTC_TIME
Definition: gd32f3x0_rtc.h:21
PSC_FACTOR_S
#define PSC_FACTOR_S(regval)
Definition: gd32f3x0_rtc.h:299
rtc_parameter_struct::rtc_minute
uint8_t rtc_minute
Definition: gd32f3x0_rtc.h:193
RTC_CTL_CS
#define RTC_CTL_CS
Definition: gd32f3x0_rtc.h:65
rtc_parameter_struct::rtc_year
uint8_t rtc_year
Definition: gd32f3x0_rtc.h:188
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
rtc_parameter_struct::rtc_am_pm
uint32_t rtc_am_pm
Definition: gd32f3x0_rtc.h:197
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
TIME_HR
#define TIME_HR(regval)
Definition: gd32f3x0_rtc.h:244
DATE_DOW
#define DATE_DOW(regval)
Definition: gd32f3x0_rtc.h:269
rtc_parameter_struct::rtc_display_format
uint32_t rtc_display_format
Definition: gd32f3x0_rtc.h:198
RTC_PSC
#define RTC_PSC
Definition: gd32f3x0_rtc.h:25
rtc_parameter_struct::rtc_date
uint8_t rtc_date
Definition: gd32f3x0_rtc.h:190
PSC_FACTOR_A
#define PSC_FACTOR_A(regval)
Definition: gd32f3x0_rtc.h:302
rtc_parameter_struct::rtc_hour
uint8_t rtc_hour
Definition: gd32f3x0_rtc.h:192
rtc_parameter_struct::rtc_second
uint8_t rtc_second
Definition: gd32f3x0_rtc.h:194
rtc_parameter_struct::rtc_day_of_week
uint8_t rtc_day_of_week
Definition: gd32f3x0_rtc.h:191
DATE_DAY
#define DATE_DAY(regval)
Definition: gd32f3x0_rtc.h:251
TIME_SC
#define TIME_SC(regval)
Definition: gd32f3x0_rtc.h:238
DATE_MON
#define DATE_MON(regval)
Definition: gd32f3x0_rtc.h:254
rtc_init_mode_exit
void rtc_init_mode_exit(void)
exit RTC init mode
Definition: gd32f3x0_rtc.c:168
rtc_parameter_struct::rtc_factor_asyn
uint16_t rtc_factor_asyn
Definition: gd32f3x0_rtc.h:195
RTC_DATE
#define RTC_DATE
Definition: gd32f3x0_rtc.h:22
DATE_YR
#define DATE_YR(regval)
Definition: gd32f3x0_rtc.h:279
rtc_init_mode_enter
ErrStatus rtc_init_mode_enter(void)
enter RTC init mode
Definition: gd32f3x0_rtc.c:138
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
rtc_register_sync_wait
ErrStatus rtc_register_sync_wait(void)
wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers ...
Definition: gd32f3x0_rtc.c:180
rtc_parameter_struct::rtc_factor_syn
uint16_t rtc_factor_syn
Definition: gd32f3x0_rtc.h:196
rtc_parameter_struct::rtc_month
uint8_t rtc_month
Definition: gd32f3x0_rtc.h:189
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
TIME_MN
#define TIME_MN(regval)
Definition: gd32f3x0_rtc.h:241
ErrStatus rtc_init_mode_enter ( void )

enter RTC init mode

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 138 of file gd32f3x0_rtc.c.

139 {
140 uint32_t time_index = RTC_INITM_TIMEOUT;
141 uint32_t flag_status = RESET;
142 ErrStatus error_status = ERROR;
143
144 /* check whether it has been in init mode */
145 if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)){
146 RTC_STAT |= RTC_STAT_INITM;
147
148 /* wait until the INITF flag to be set */
149 do{
150 flag_status = RTC_STAT & RTC_STAT_INITF;
151 }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status));
152
153 if((uint32_t)RESET != flag_status){
154 error_status = SUCCESS;
155 }
156 }else{
157 error_status = SUCCESS;
158 }
159 return error_status;
160 }
RTC_INITM_TIMEOUT
#define RTC_INITM_TIMEOUT
Definition: gd32f3x0_rtc.h:447
RTC_STAT_INITM
#define RTC_STAT_INITM
Definition: gd32f3x0_rtc.h:84
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
RTC_STAT_INITF
#define RTC_STAT_INITF
Definition: gd32f3x0_rtc.h:83
void rtc_init_mode_exit ( void )

exit RTC init mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 168 of file gd32f3x0_rtc.c.

169 {
170 RTC_STAT &= (uint32_t)(~RTC_STAT_INITM);
171 }
RTC_STAT_INITM
#define RTC_STAT_INITM
Definition: gd32f3x0_rtc.h:84
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
void rtc_interrupt_disable ( uint32_t interrupt )

disble specified RTC interrupt

Parameters
[in] interrupt specify which interrupt source to be disabled
  • RTC_INT_TIMESTAMP: timestamp interrupt
  • RTC_INT_ALARM: alarm interrupt
  • RTC_INT_TAMP: tamp interrupt
[out] none
Return values
none

Definition at line 644 of file gd32f3x0_rtc.c.

645 {
646 /* disable the write protection */
647 RTC_WPK = RTC_UNLOCK_KEY1;
648 RTC_WPK = RTC_UNLOCK_KEY2;
649
650 /* disable the interrupts in RTC_CTL register */
651 RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE);
652 /* disable the interrupts in RTC_TAMP register */
653 RTC_TAMP &= (uint32_t)~(interrupt & RTC_TAMP_TPIE);
654
655 /* enable the write protection */
656 RTC_WPK = RTC_LOCK_KEY;
657 }
RTC_TAMP_TPIE
#define RTC_TAMP_TPIE
Definition: gd32f3x0_rtc.h:150
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_TAMP
#define RTC_TAMP
Definition: gd32f3x0_rtc.h:34
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_interrupt_enable ( uint32_t interrupt )

enable specified RTC interrupt

Parameters
[in] interrupt specify which interrupt source to be enabled
  • RTC_INT_TIMESTAMP: timestamp interrupt
  • RTC_INT_ALARM: alarm interrupt
  • RTC_INT_TAMP: tamp interrupt
[out] none
Return values
none

Definition at line 620 of file gd32f3x0_rtc.c.

621 {
622 /* disable the write protection */
623 RTC_WPK = RTC_UNLOCK_KEY1;
624 RTC_WPK = RTC_UNLOCK_KEY2;
625
626 /* enable the interrupts in RTC_CTL register */
627 RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE);
628 /* enable the interrupts in RTC_TAMP register */
629 RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE);
630
631 /* enable the write protection */
632 RTC_WPK = RTC_LOCK_KEY;
633 }
RTC_TAMP_TPIE
#define RTC_TAMP_TPIE
Definition: gd32f3x0_rtc.h:150
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_TAMP
#define RTC_TAMP
Definition: gd32f3x0_rtc.h:34
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
ErrStatus rtc_refclock_detection_disable ( void )

disable RTC reference clock detection function

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 829 of file gd32f3x0_rtc.c.

830 {
831 ErrStatus error_status = ERROR;
832
833 /* disable the write protection */
834 RTC_WPK = RTC_UNLOCK_KEY1;
835 RTC_WPK = RTC_UNLOCK_KEY2;
836
837 /* enter init mode */
838 error_status = rtc_init_mode_enter();
839
840 if(ERROR != error_status){
841 RTC_CTL &= (uint32_t)~RTC_CTL_REFEN;
842 /* exit init mode */
843 rtc_init_mode_exit();
844 }
845
846 /* enable the write protection */
847 RTC_WPK = RTC_LOCK_KEY;
848
849 return error_status;
850 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
rtc_init_mode_exit
void rtc_init_mode_exit(void)
exit RTC init mode
Definition: gd32f3x0_rtc.c:168
RTC_CTL_REFEN
#define RTC_CTL_REFEN
Definition: gd32f3x0_rtc.h:63
rtc_init_mode_enter
ErrStatus rtc_init_mode_enter(void)
enter RTC init mode
Definition: gd32f3x0_rtc.c:138
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
ErrStatus rtc_refclock_detection_enable ( void )

enable RTC reference clock detection function

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 800 of file gd32f3x0_rtc.c.

801 {
802 ErrStatus error_status = ERROR;
803
804 /* disable the write protection */
805 RTC_WPK = RTC_UNLOCK_KEY1;
806 RTC_WPK = RTC_UNLOCK_KEY2;
807
808 /* enter init mode */
809 error_status = rtc_init_mode_enter();
810
811 if(ERROR != error_status){
812 RTC_CTL |= (uint32_t)RTC_CTL_REFEN;
813 /* exit init mode */
814 rtc_init_mode_exit();
815 }
816
817 /* enable the write protection */
818 RTC_WPK = RTC_LOCK_KEY;
819
820 return error_status;
821 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
rtc_init_mode_exit
void rtc_init_mode_exit(void)
exit RTC init mode
Definition: gd32f3x0_rtc.c:168
RTC_CTL_REFEN
#define RTC_CTL_REFEN
Definition: gd32f3x0_rtc.h:63
rtc_init_mode_enter
ErrStatus rtc_init_mode_enter(void)
enter RTC init mode
Definition: gd32f3x0_rtc.c:138
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
ErrStatus rtc_register_sync_wait ( void )

wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 180 of file gd32f3x0_rtc.c.

181 {
182 volatile uint32_t time_index = RTC_RSYNF_TIMEOUT;
183 uint32_t flag_status = RESET;
184 ErrStatus error_status = ERROR;
185
186 if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)){
187 /* disable the write protection */
188 RTC_WPK = RTC_UNLOCK_KEY1;
189 RTC_WPK = RTC_UNLOCK_KEY2;
190
191 /* firstly clear RSYNF flag */
192 RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF);
193
194 /* wait until RSYNF flag to be set */
195 do{
196 flag_status = RTC_STAT & RTC_STAT_RSYNF;
197 }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status));
198
199 if((uint32_t)RESET != flag_status){
200 error_status = SUCCESS;
201 }
202
203 /* enable the write protection */
204 RTC_WPK = RTC_LOCK_KEY;
205 }else{
206 error_status = SUCCESS;
207 }
208
209 return error_status;
210 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL_BPSHAD
#define RTC_CTL_BPSHAD
Definition: gd32f3x0_rtc.h:64
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_RSYNF_TIMEOUT
#define RTC_RSYNF_TIMEOUT
Definition: gd32f3x0_rtc.h:448
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
RTC_STAT_RSYNF
#define RTC_STAT_RSYNF
Definition: gd32f3x0_rtc.h:82
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
ErrStatus rtc_second_ajust | ( | uint32_t | add,
 |  | uint32_t | minus
 | ) |  |

ajust RTC second or subsecond value of current time

Parameters
[in] add add 1s to current time or not
  • RTC_SHIFT_ADD1S_RESET: no effect
  • RTC_SHIFT_ADD1S_SET: add 1s to current time
[in] | minus | number of subsecond to minus from current time(0x0 - 0x7FFF)
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 861 of file gd32f3x0_rtc.c.

862 {
863 uint32_t time_index = RTC_SHIFTCTL_TIMEOUT;
864 ErrStatus error_status = ERROR;
865 uint32_t flag_status = RESET;
866 uint32_t temp=0U;
867
868 /* disable the write protection */
869 RTC_WPK = RTC_UNLOCK_KEY1;
870 RTC_WPK = RTC_UNLOCK_KEY2;
871
872 /* check if a shift operation is ongoing */
873 do{
874 flag_status = RTC_STAT & RTC_STAT_SOPF;
875 }while((--time_index > 0x00U) && ((uint32_t)RESET != flag_status));
876
877 temp = RTC_CTL & RTC_CTL_REFEN;
878 /* check if the function of reference clock detection is disabled */
879 if(((uint32_t)RESET == flag_status) && (RESET == temp)){
880 RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus));
881 error_status = rtc_register_sync_wait();
882 }
883
884 /* enable the write protection */
885 RTC_WPK = RTC_LOCK_KEY;
886
887 return error_status;
888 }
SHIFTCTL_SFS
#define SHIFTCTL_SFS(regval)
Definition: gd32f3x0_rtc.h:335
RTC_SHIFTCTL
#define RTC_SHIFTCTL
Definition: gd32f3x0_rtc.h:29
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_SHIFTCTL_TIMEOUT
#define RTC_SHIFTCTL_TIMEOUT
Definition: gd32f3x0_rtc.h:450
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_STAT_SOPF
#define RTC_STAT_SOPF
Definition: gd32f3x0_rtc.h:80
RTC_CTL_REFEN
#define RTC_CTL_REFEN
Definition: gd32f3x0_rtc.h:63
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
rtc_register_sync_wait
ErrStatus rtc_register_sync_wait(void)
wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers ...
Definition: gd32f3x0_rtc.c:180
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
uint32_t rtc_subsecond_get ( void )

get current subsecond value

Parameters
[in] | none
[out] | none
Return values
current subsecond value

Definition at line 262 of file gd32f3x0_rtc.c.

263 {
264 uint32_t reg = 0x00U;
265 /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */
266 reg = (uint32_t)RTC_SS;
267 /* read RTC_DATE to unlock the 3 shadow registers */
268 (void) (RTC_DATE);
269
270 return reg;
271 }
RTC_SS
#define RTC_SS
Definition: gd32f3x0_rtc.h:28
RTC_DATE
#define RTC_DATE
Definition: gd32f3x0_rtc.h:22
void rtc_tamper_disable ( uint32_t source )

disable RTC tamper

Parameters
[in] source specify which tamper source to be disabled
  • RTC_TAMPER0
  • RTC_TAMPER1
[out] none
Return values
none

Definition at line 604 of file gd32f3x0_rtc.c.

605 {
606 /* disable tamper */
607 RTC_TAMP &= (uint32_t)~source;
608
609 }
RTC_TAMP
#define RTC_TAMP
Definition: gd32f3x0_rtc.h:34
void rtc_tamper_enable ( rtc_tamper_struct * rtc_tamper )

enable RTC tamper

Parameters
[in] | rtc_tamper | pointer to a rtc_tamper_struct structure which contains parameters for RTC tamper configuration members of the structure and the member values are shown as below: rtc_tamper_source: RTC_TAMPER0, RTC_TAMPER1 rtc_tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH rtc_tamper_filter: RTC_FLT_EDGE, RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S rtc_tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192, RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024, RTC_FREQ_DIV512, RTC_FREQ_DIV256 rtc_tamper_precharge_enable: DISABLE, ENABLE rtc_tamper_precharge_time: RTC_PRCH_1C, RTC_PRCH_2C, RTC_PRCH_4C, RTC_PRCH_8C rtc_tamper_with_timestamp: DISABLE, ENABLE
[out] | none
Return values
none

Definition at line 557 of file gd32f3x0_rtc.c.

558 {
559 /* disable tamper */
560 RTC_TAMP &= (uint32_t)~(rtc_tamper->rtc_tamper_source);
561
562 /* tamper filter must be used when the tamper source is voltage level detection */
563 RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT;
564
565 /* the tamper source is voltage level detection */
566 if(rtc_tamper->rtc_tamper_filter != RTC_FLT_EDGE ){
567 RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT);
568
569 /* check if the tamper pin need precharge, if need, then configure the precharge time */
570 if(DISABLE == rtc_tamper->rtc_tamper_precharge_enable){
571 RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU;
572 }else{
573 RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_precharge_time);
574 }
575
576 RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_sample_frequency);
577 RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_filter);
578 }
579
580 RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS;
581
582 if(DISABLE != rtc_tamper->rtc_tamper_with_timestamp){
583 /* the tamper event also cause a time-stamp event */
584 RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS;
585 }
586
587 /* configure the tamper trigger */
588 RTC_TAMP &= ((uint32_t)~((rtc_tamper->rtc_tamper_source) << RTC_TAMPER_TRIGGER_POS));
589 if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->rtc_tamper_trigger){
590 RTC_TAMP |= (uint32_t)((rtc_tamper->rtc_tamper_source)<< RTC_TAMPER_TRIGGER_POS);
591 }
592 /* enable tamper */
593 RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_source);
594 }
rtc_tamper_struct::rtc_tamper_sample_frequency
uint32_t rtc_tamper_sample_frequency
Definition: gd32f3x0_rtc.h:231
rtc_tamper_struct::rtc_tamper_with_timestamp
ControlStatus rtc_tamper_with_timestamp
Definition: gd32f3x0_rtc.h:234
RTC_TAMP
#define RTC_TAMP
Definition: gd32f3x0_rtc.h:34
RTC_TAMPER_TRIGGER_POS
#define RTC_TAMPER_TRIGGER_POS
Definition: gd32f3x0_rtc.h:404
RTC_TAMP_TPTS
#define RTC_TAMP_TPTS
Definition: gd32f3x0_rtc.h:153
RTC_TAMP_FLT
#define RTC_TAMP_FLT
Definition: gd32f3x0_rtc.h:155
RTC_TAMP_DISPU
#define RTC_TAMP_DISPU
Definition: gd32f3x0_rtc.h:157
rtc_tamper_struct::rtc_tamper_trigger
uint32_t rtc_tamper_trigger
Definition: gd32f3x0_rtc.h:229
rtc_tamper_struct::rtc_tamper_source
uint32_t rtc_tamper_source
Definition: gd32f3x0_rtc.h:228
RTC_TAMP_FREQ
#define RTC_TAMP_FREQ
Definition: gd32f3x0_rtc.h:154
rtc_tamper_struct::rtc_tamper_precharge_enable
ControlStatus rtc_tamper_precharge_enable
Definition: gd32f3x0_rtc.h:232
rtc_tamper_struct::rtc_tamper_precharge_time
uint32_t rtc_tamper_precharge_time
Definition: gd32f3x0_rtc.h:233
RTC_TAMPER_TRIGGER_EDGE_RISING
#define RTC_TAMPER_TRIGGER_EDGE_RISING
Definition: gd32f3x0_rtc.h:399
RTC_FLT_EDGE
#define RTC_FLT_EDGE
Definition: gd32f3x0_rtc.h:385
rtc_tamper_struct::rtc_tamper_filter
uint32_t rtc_tamper_filter
Definition: gd32f3x0_rtc.h:230
RTC_TAMP_PRCH
#define RTC_TAMP_PRCH
Definition: gd32f3x0_rtc.h:156
void rtc_timestamp_disable ( void )

disable RTC time-stamp

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 480 of file gd32f3x0_rtc.c.

481 {
482 /* disable the write protection */
483 RTC_WPK = RTC_UNLOCK_KEY1;
484 RTC_WPK = RTC_UNLOCK_KEY2;
485
486 /* clear the TSEN bit */
487 RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN);
488
489 /* enable the write protection */
490 RTC_WPK = RTC_LOCK_KEY;
491 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL_TSEN
#define RTC_CTL_TSEN
Definition: gd32f3x0_rtc.h:67
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_timestamp_enable ( uint32_t edge )

enable RTC time-stamp

Parameters
[in] edge specify which edge to detect of time-stamp
  • RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event
  • RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event
[out] none
Return values
none

Definition at line 454 of file gd32f3x0_rtc.c.

455 {
456 uint32_t reg_ctl = 0x00U;
457
458 /* clear the bits to be configured in RTC_CTL */
459 reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN)));
460
461 /* new configuration */
462 reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN);
463
464 /* disable the write protection */
465 RTC_WPK = RTC_UNLOCK_KEY1;
466 RTC_WPK = RTC_UNLOCK_KEY2;
467
468 RTC_CTL = (uint32_t)reg_ctl;
469
470 /* enable the write protection */
471 RTC_WPK = RTC_LOCK_KEY;
472 }
RTC_CTL_TSEG
#define RTC_CTL_TSEG
Definition: gd32f3x0_rtc.h:62
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL_TSEN
#define RTC_CTL_TSEN
Definition: gd32f3x0_rtc.h:67
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_timestamp_get ( rtc_timestamp_struct * rtc_timestamp )

get RTC timestamp time and date

Parameters
[in] | none
[out] | rtc_timestamp | pointer to a rtc_timestamp_struct structure which contains parameters for RTC time-stamp configuration members of the structure and the member values are shown as below: rtc_timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC rtc_timestamp_date: 0x1 - 0x31(BCD format) rtc_timestamp_day: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set rtc_timestamp_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format rtc_timestamp_minute: 0x0 - 0x59(BCD format) rtc_timestamp_second: 0x0 - 0x59(BCD format) rtc_am_pm: RTC_AM, RTC_PM
Return values
none

Definition at line 510 of file gd32f3x0_rtc.c.

511 {
512 uint32_t temp_tts = 0x00U, temp_dts = 0x00U;
513
514 /* get the value of time_stamp registers */
515 temp_tts = (uint32_t)RTC_TTS;
516 temp_dts = (uint32_t)RTC_DTS;
517
518 /* get timestamp time and construct the rtc_timestamp_struct structure */
519 rtc_timestamp->rtc_am_pm = (uint32_t)(temp_tts & RTC_TTS_PM);
520 rtc_timestamp->rtc_timestamp_month = (uint8_t)GET_DTS_MON(temp_dts);
521 rtc_timestamp->rtc_timestamp_date = (uint8_t)GET_DTS_DAY(temp_dts);
522 rtc_timestamp->rtc_timestamp_day = (uint8_t)GET_DTS_DOW(temp_dts);
523 rtc_timestamp->rtc_timestamp_hour = (uint8_t)GET_TTS_HR(temp_tts);
524 rtc_timestamp->rtc_timestamp_minute = (uint8_t)GET_TTS_MN(temp_tts);
525 rtc_timestamp->rtc_timestamp_second = (uint8_t)GET_TTS_SC(temp_tts);
526 }
GET_DTS_DAY
#define GET_DTS_DAY(regval)
Definition: gd32f3x0_rtc.h:352
GET_TTS_SC
#define GET_TTS_SC(regval)
Definition: gd32f3x0_rtc.h:342
rtc_timestamp_struct::rtc_timestamp_second
uint8_t rtc_timestamp_second
Definition: gd32f3x0_rtc.h:221
rtc_timestamp_struct::rtc_timestamp_date
uint8_t rtc_timestamp_date
Definition: gd32f3x0_rtc.h:217
RTC_TTS_PM
#define RTC_TTS_PM
Definition: gd32f3x0_rtc.h:129
GET_TTS_MN
#define GET_TTS_MN(regval)
Definition: gd32f3x0_rtc.h:345
rtc_timestamp_struct::rtc_am_pm
uint32_t rtc_am_pm
Definition: gd32f3x0_rtc.h:222
rtc_timestamp_struct::rtc_timestamp_day
uint8_t rtc_timestamp_day
Definition: gd32f3x0_rtc.h:218
RTC_DTS
#define RTC_DTS
Definition: gd32f3x0_rtc.h:31
GET_TTS_HR
#define GET_TTS_HR(regval)
Definition: gd32f3x0_rtc.h:348
rtc_timestamp_struct::rtc_timestamp_minute
uint8_t rtc_timestamp_minute
Definition: gd32f3x0_rtc.h:220
RTC_TTS
#define RTC_TTS
Definition: gd32f3x0_rtc.h:30
GET_DTS_MON
#define GET_DTS_MON(regval)
Definition: gd32f3x0_rtc.h:355
rtc_timestamp_struct::rtc_timestamp_month
uint8_t rtc_timestamp_month
Definition: gd32f3x0_rtc.h:216
rtc_timestamp_struct::rtc_timestamp_hour
uint8_t rtc_timestamp_hour
Definition: gd32f3x0_rtc.h:219
GET_DTS_DOW
#define GET_DTS_DOW(regval)
Definition: gd32f3x0_rtc.h:358
uint32_t rtc_timestamp_subsecond_get ( void )

get RTC time-stamp subsecond

Parameters
[in] | none
[out] | none
Return values
RTC time-stamp subsecond value

Definition at line 534 of file gd32f3x0_rtc.c.

535 {
536 return ((uint32_t)RTC_SSTS);
537 }
RTC_SSTS
#define RTC_SSTS
Definition: gd32f3x0_rtc.h:32
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_spi.h File Reference

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Data Structures | Macros | Functions
gd32f3x0_spi.h File Reference

definitions for the SPI More...

#include "gd32f3x0.h"

Go to the source code of this file.

Data Structures

struct spi_parameter_struct

Macros

#define | SPI0 (SPI_BASE + 0x0000F800U)
#define | SPI1 SPI_BASE
#define | SPI2 (SPI_BASE + 0x00000400U)
#define | SPI_CTL0(spix) REG32((spix) + 0x00U)
#define | SPI_CTL1(spix) REG32((spix) + 0x04U)
#define | SPI_STAT(spix) REG32((spix) + 0x08U)
#define | SPI_DATA(spix) REG32((spix) + 0x0CU)
#define | SPI_CRCPOLY(spix) REG32((spix) + 0x10U)
#define | SPI_RCRC(spix) REG32((spix) + 0x14U)
#define | SPI_TCRC(spix) REG32((spix) + 0x18U)
#define | SPI_I2SCTL(spix) REG32((spix) + 0x1CU)
#define | SPI_I2SPSC(spix) REG32((spix) + 0x20U)
#define | SPI_QCTL(spix) REG32((spix) + 0x80U)
#define | SPI_CTL0_CKPH BIT(0)
#define | SPI_CTL0_CKPL BIT(1)
#define | SPI_CTL0_MSTMOD BIT(2)
#define | SPI_CTL0_PSC BITS(3,5)
#define | SPI_CTL0_SPIEN BIT(6)
#define | SPI_CTL0_LF BIT(7)
#define | SPI_CTL0_SWNSS BIT(8)
#define | SPI_CTL0_SWNSSEN BIT(9)
#define | SPI_CTL0_RO BIT(10)
#define | SPI_CTL0_FF16 BIT(11)
#define | SPI_CTL0_CRCNT BIT(12)
#define | SPI_CTL0_CRCEN BIT(13)
#define | SPI_CTL0_BDOEN BIT(14)
#define | SPI_CTL0_BDEN BIT(15)
#define | SPI_CTL1_DMAREN BIT(0)
#define | SPI_CTL1_DMATEN BIT(1)
#define | SPI_CTL1_NSSDRV BIT(2)
#define | SPI_CTL1_NSSP BIT(3)
#define | SPI_CTL1_TMOD BIT(4)
#define | SPI_CTL1_ERRIE BIT(5)
#define | SPI_CTL1_RBNEIE BIT(6)
#define | SPI_CTL1_TBEIE BIT(7)
#define | SPI_STAT_RBNE BIT(0)
#define | SPI_STAT_TBE BIT(1)
#define | SPI_STAT_I2SCH BIT(2)
#define | SPI_STAT_TXURERR BIT(3)
#define | SPI_STAT_CRCERR BIT(4)
#define | SPI_STAT_CONFERR BIT(5)
#define | SPI_STAT_RXORERR BIT(6)
#define | SPI_STAT_TRANS BIT(7)
#define | SPI_STAT_FERR BIT(8)
#define | SPI_DATA_DATA BITS(0,15)
#define | SPI_CRCPOLY_CPR BITS(0,15)
#define | SPI_RCRC_RCR BITS(0,15)
#define | SPI_TCRC_TCR BITS(0,15)
#define | SPI_I2SCTL_CHLEN BIT(0)
#define | SPI_I2SCTL_DTLEN BITS(1,2)
#define | SPI_I2SCTL_CKPL BIT(3)
#define | SPI_I2SCTL_I2SSTD BITS(4,5)
#define | SPI_I2SCTL_PCMSMOD BIT(7)
#define | SPI_I2SCTL_I2SOPMOD BITS(8,9)
#define | SPI_I2SCTL_I2SEN BIT(10)
#define | SPI_I2SCTL_I2SSEL BIT(11)
#define | SPI_I2SPSC_DIV BITS(0,7)
#define | SPI_I2SPSC_OF BIT(8)
#define | SPI_I2SPSC_MCKOEN BIT(9)
#define | SPI_QCTL_QMOD BIT(0)
#define | SPI_QCTL_QRD BIT(1)
#define | SPI_QCTL_IO23_DRV BIT(2)
#define | SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS)
#define | SPI_SLAVE ((uint32_t)0x00000000U)
#define | SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U)
#define | SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO
#define | SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN
#define | SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN)
#define | SPI_FRAMESIZE_16BIT SPI_CTL0_FF16
#define | SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U)
#define | SPI_NSS_SOFT SPI_CTL0_SWNSSEN
#define | SPI_NSS_HARD ((uint32_t)0x00000000U)
#define | SPI_ENDIAN_MSB ((uint32_t)0x00000000U)
#define | SPI_ENDIAN_LSB SPI_CTL0_LF
#define | SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U)
#define | SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL
#define | SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH
#define | SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH)
#define | CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
#define | SPI_PSC_2 CTL0_PSC(0)
#define | SPI_PSC_4 CTL0_PSC(1)
#define | SPI_PSC_8 CTL0_PSC(2)
#define | SPI_PSC_16 CTL0_PSC(3)
#define | SPI_PSC_32 CTL0_PSC(4)
#define | SPI_PSC_64 CTL0_PSC(5)
#define | SPI_PSC_128 CTL0_PSC(6)
#define | SPI_PSC_256 CTL0_PSC(7)
#define | SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN
#define | SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN)
#define | SPI_DMA_TRANSMIT ((uint8_t)0x00U)
#define | SPI_DMA_RECEIVE ((uint8_t)0x01U)
#define | SPI_CRC_TX ((uint8_t)0x00U)
#define | SPI_CRC_RX ((uint8_t)0x01U)
#define | SPI_I2S_INT_TBE ((uint8_t)0x00U)
#define | SPI_I2S_INT_RBNE ((uint8_t)0x01U)
#define | SPI_I2S_INT_ERR ((uint8_t)0x02U)
#define | SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U)
#define | SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U)
#define | SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U)
#define | SPI_INT_FLAG_CONFERR ((uint8_t)0x03U)
#define | SPI_INT_FLAG_CRCERR ((uint8_t)0x04U)
#define | I2S_INT_FLAG_TXURERR ((uint8_t)0x05U)
#define | SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U)
#define | SPI_FLAG_RBNE SPI_STAT_RBNE
#define | SPI_FLAG_TBE SPI_STAT_TBE
#define | SPI_FLAG_CRCERR SPI_STAT_CRCERR
#define | SPI_FLAG_CONFERR SPI_STAT_CONFERR
#define | SPI_FLAG_RXORERR SPI_STAT_RXORERR
#define | SPI_FLAG_TRANS SPI_STAT_TRANS
#define | SPI_FLAG_FERR SPI_STAT_FERR

Functions

void | spi_i2s_deinit (uint32_t spi_periph)
reset SPI and I2S More...
void | spi_init (uint32_t spi_periph, spi_parameter_struct *spi_struct)
initialize SPI parameter More...
void | spi_enable (uint32_t spi_periph)
enable SPI More...
void | spi_disable (uint32_t spi_periph)
disable SPI More...
void | spi_nss_output_enable (uint32_t spi_periph)
enable SPI NSS output More...
void | spi_nss_output_disable (uint32_t spi_periph)
disable SPI NSS output More...
void | spi_nss_internal_high (uint32_t spi_periph)
SPI NSS pin high level in software mode. More...
void | spi_nss_internal_low (uint32_t spi_periph)
SPI NSS pin low level in software mode. More...
void | spi_dma_enable (uint32_t spi_periph, uint8_t dma)
enable SPI DMA send or receive More...
void | spi_dma_disable (uint32_t spi_periph, uint8_t dma)
disable SPI DMA send or receive More...
void | spi_i2s_data_frame_format_config (uint32_t spi_periph, uint16_t frame_format)
configure SPI/I2S data frame format More...
void | spi_i2s_data_transmit (uint32_t spi_periph, uint16_t data)
SPI transmit data. More...
uint16_t | spi_i2s_data_receive (uint32_t spi_periph)
SPI receive data. More...
void | spi_bidirectional_transfer_config (uint32_t spi_periph, uint32_t transfer_direction)
configure SPI bidirectional transfer direction More...
void | spi_i2s_interrupt_enable (uint32_t spi_periph, uint8_t interrupt)
enable SPI and I2S interrupt More...
void | spi_i2s_interrupt_disable (uint32_t spi_periph, uint8_t interrupt)
disable SPI and I2S interrupt More...
FlagStatus | spi_i2s_interrupt_flag_get (uint32_t spi_periph, uint8_t interrupt)
get SPI and I2S interrupt flag status More...
FlagStatus | spi_i2s_flag_get (uint32_t spi_periph, uint32_t flag)
get SPI and I2S flag status More...
void | spi_crc_error_clear (uint32_t spi_periph)
clear SPI CRC error flag status More...
void | spi_crc_polynomial_set (uint32_t spi_periph, uint16_t crc_poly)
set CRC polynomial More...
uint16_t | spi_crc_polynomial_get (uint32_t spi_periph)
get SPI CRC polynomial More...
void | spi_crc_on (uint32_t spi_periph)
turn on CRC function More...
void | spi_crc_off (uint32_t spi_periph)
turn off CRC function More...
void | spi_crc_next (uint32_t spi_periph)
SPI next data is CRC value. More...
uint16_t | spi_crc_get (uint32_t spi_periph, uint8_t crc)
get SPI CRC send value or receive value More...
void | spi_ti_mode_enable (uint32_t spi_periph)
enable SPI TI mode More...
void | spi_ti_mode_disable (uint32_t spi_periph)
disable SPI TI mode More...
void | spi_nssp_mode_enable (uint32_t spi_periph)
enable SPI NSS pulse mode More...
void | spi_nssp_mode_disable (uint32_t spi_periph)
disable SPI NSS pulse mode More...
void | qspi_enable (uint32_t spi_periph)
enable quad wire SPI More...
void | qspi_disable (uint32_t spi_periph)
disable quad wire SPI More...
void | qspi_write_enable (uint32_t spi_periph)
enable quad wire SPI write More...
void | qspi_read_enable (uint32_t spi_periph)
enable quad wire SPI read More...
void | qspi_io23_output_enable (uint32_t spi_periph)
enable SPI_IO2 and SPI_IO3 pin output More...
void | qspi_io23_output_disable (uint32_t spi_periph)
disable SPI_IO2 and SPI_IO3 pin output More...

Detailed Description

definitions for the SPI

Definition in file gd32f3x0_spi.h.

Macro Definition Documentation

#define CTL0_PSC ( regval ) (BITS(3,5) & ((uint32_t)(regval) << 3))

Definition at line 146 of file gd32f3x0_spi.h.

#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U)

underrun error interrupt flag

Definition at line 222 of file gd32f3x0_spi.h.

#define SPI0 (SPI_BASE + 0x0000F800U)

Definition at line 18 of file gd32f3x0_spi.h.

#define SPI1 SPI_BASE

Definition at line 19 of file gd32f3x0_spi.h.

#define SPI2 (SPI_BASE + 0x00000400U)

Definition at line 20 of file gd32f3x0_spi.h.

#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN)

SPI work in receive-only mode

Definition at line 158 of file gd32f3x0_spi.h.

#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN

SPI work in transmit-only mode

Definition at line 157 of file gd32f3x0_spi.h.

#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL

SPI clock polarity is high level and phase is first edge

Definition at line 141 of file gd32f3x0_spi.h.

#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH)

SPI clock polarity is high level and phase is second edge

Definition at line 143 of file gd32f3x0_spi.h.

#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U)

SPI clock polarity is low level and phase is first edge

Definition at line 140 of file gd32f3x0_spi.h.

#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH

SPI clock polarity is low level and phase is second edge

Definition at line 142 of file gd32f3x0_spi.h.

#define SPI_CRC_RX ((uint8_t)0x01U)

SPI receive CRC value

Definition at line 209 of file gd32f3x0_spi.h.

#define SPI_CRC_TX ((uint8_t)0x00U)

SPI transmit CRC value

Definition at line 208 of file gd32f3x0_spi.h.

#define SPI_CRCPOLY ( spix ) REG32((spix) + 0x10U)

SPI CRC polynomial register

Definition at line 27 of file gd32f3x0_spi.h.

#define SPI_CRCPOLY_CPR BITS(0,15)

CRC polynomial register

Definition at line 76 of file gd32f3x0_spi.h.

#define SPI_CTL0 ( spix ) REG32((spix) + 0x00U)

SPI control register 0

Definition at line 23 of file gd32f3x0_spi.h.

#define SPI_CTL0_BDEN BIT(15)

bidirectional enable

Definition at line 49 of file gd32f3x0_spi.h.

#define SPI_CTL0_BDOEN BIT(14)

bidirectional transmit output enable

Definition at line 48 of file gd32f3x0_spi.h.

#define SPI_CTL0_CKPH BIT(0)

clock phase selection

Definition at line 36 of file gd32f3x0_spi.h.

#define SPI_CTL0_CKPL BIT(1)

clock polarity selection

Definition at line 37 of file gd32f3x0_spi.h.

#define SPI_CTL0_CRCEN BIT(13)

CRC calculation enable

Definition at line 47 of file gd32f3x0_spi.h.

#define SPI_CTL0_CRCNT BIT(12)

CRC next transfer

Definition at line 46 of file gd32f3x0_spi.h.

#define SPI_CTL0_FF16 BIT(11)

data frame size

Definition at line 45 of file gd32f3x0_spi.h.

#define SPI_CTL0_LF BIT(7)

LSB first mode

Definition at line 41 of file gd32f3x0_spi.h.

#define SPI_CTL0_MSTMOD BIT(2)

master mode enable

Definition at line 38 of file gd32f3x0_spi.h.

#define SPI_CTL0_PSC BITS(3,5)

master clock prescaler selection

Definition at line 39 of file gd32f3x0_spi.h.

#define SPI_CTL0_RO BIT(10)

receive only

Definition at line 44 of file gd32f3x0_spi.h.

#define SPI_CTL0_SPIEN BIT(6)

SPI enable

Definition at line 40 of file gd32f3x0_spi.h.

#define SPI_CTL0_SWNSS BIT(8)

NSS pin selection in NSS software mode

Definition at line 42 of file gd32f3x0_spi.h.

#define SPI_CTL0_SWNSSEN BIT(9)

NSS software mode selection

Definition at line 43 of file gd32f3x0_spi.h.

#define SPI_CTL1 ( spix ) REG32((spix) + 0x04U)

SPI control register 1

Definition at line 24 of file gd32f3x0_spi.h.

#define SPI_CTL1_DMAREN BIT(0)

receive buffer dma enable

Definition at line 52 of file gd32f3x0_spi.h.

#define SPI_CTL1_DMATEN BIT(1)

transmit buffer dma enable

Definition at line 53 of file gd32f3x0_spi.h.

#define SPI_CTL1_ERRIE BIT(5)

errors interrupt enable

Definition at line 57 of file gd32f3x0_spi.h.

#define SPI_CTL1_NSSDRV BIT(2)

drive NSS output

Definition at line 54 of file gd32f3x0_spi.h.

#define SPI_CTL1_NSSP BIT(3)

SPI NSS pulse mode enable

Definition at line 55 of file gd32f3x0_spi.h.

#define SPI_CTL1_RBNEIE BIT(6)

receive buffer not empty interrupt enable

Definition at line 58 of file gd32f3x0_spi.h.

#define SPI_CTL1_TBEIE BIT(7)

transmit buffer empty interrupt enable

Definition at line 59 of file gd32f3x0_spi.h.

#define SPI_CTL1_TMOD BIT(4)

SPI TI mode enable

Definition at line 56 of file gd32f3x0_spi.h.

#define SPI_DATA ( spix ) REG32((spix) + 0x0CU)

SPI data register

Definition at line 26 of file gd32f3x0_spi.h.

#define SPI_DATA_DATA BITS(0,15)

data transfer register

Definition at line 73 of file gd32f3x0_spi.h.

#define SPI_DMA_RECEIVE ((uint8_t)0x01U)

SPI receive data use DMA

Definition at line 205 of file gd32f3x0_spi.h.

#define SPI_DMA_TRANSMIT ((uint8_t)0x00U)

SPI transmit data use DMA

Definition at line 204 of file gd32f3x0_spi.h.

#define SPI_ENDIAN_LSB SPI_CTL0_LF

SPI transmit way is little endian: transmit LSB first

Definition at line 137 of file gd32f3x0_spi.h.

#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U)

SPI transmit way is big endian: transmit MSB first

Definition at line 136 of file gd32f3x0_spi.h.

#define SPI_FLAG_CONFERR SPI_STAT_CONFERR

mode config error flag

Definition at line 229 of file gd32f3x0_spi.h.

#define SPI_FLAG_CRCERR SPI_STAT_CRCERR

CRC error flag

Definition at line 228 of file gd32f3x0_spi.h.

#define SPI_FLAG_FERR SPI_STAT_FERR

format error interrupt flag

Definition at line 232 of file gd32f3x0_spi.h.

#define SPI_FLAG_RBNE SPI_STAT_RBNE

receive buffer not empty flag

Definition at line 226 of file gd32f3x0_spi.h.

#define SPI_FLAG_RXORERR SPI_STAT_RXORERR

receive overrun error flag

Definition at line 230 of file gd32f3x0_spi.h.

#define SPI_FLAG_TBE SPI_STAT_TBE

transmit buffer empty flag

Definition at line 227 of file gd32f3x0_spi.h.

#define SPI_FLAG_TRANS SPI_STAT_TRANS

transmit on-going flag

Definition at line 231 of file gd32f3x0_spi.h.

#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16

SPI frame size is 16 bits

Definition at line 128 of file gd32f3x0_spi.h.

#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U)

SPI frame size is 8 bits

Definition at line 129 of file gd32f3x0_spi.h.

#define SPI_I2S_INT_ERR ((uint8_t)0x02U)

error interrupt

Definition at line 214 of file gd32f3x0_spi.h.

#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U)

format error interrupt flag

Definition at line 223 of file gd32f3x0_spi.h.

#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U)

receive buffer not empty interrupt flag

Definition at line 218 of file gd32f3x0_spi.h.

#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U)

overrun interrupt flag

Definition at line 219 of file gd32f3x0_spi.h.

#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U)

transmit buffer empty interrupt flag

Definition at line 217 of file gd32f3x0_spi.h.

#define SPI_I2S_INT_RBNE ((uint8_t)0x01U)

receive buffer not empty interrupt

Definition at line 213 of file gd32f3x0_spi.h.

#define SPI_I2S_INT_TBE ((uint8_t)0x00U)

transmit buffer empty interrupt

Definition at line 212 of file gd32f3x0_spi.h.

#define SPI_I2SCTL ( spix ) REG32((spix) + 0x1CU)

SPI I2S control register

Definition at line 30 of file gd32f3x0_spi.h.

#define SPI_I2SCTL_CHLEN BIT(0)

channel length

Definition at line 85 of file gd32f3x0_spi.h.

#define SPI_I2SCTL_CKPL BIT(3)

idle state clock polarity

Definition at line 87 of file gd32f3x0_spi.h.

#define SPI_I2SCTL_DTLEN BITS(1,2)

data length

Definition at line 86 of file gd32f3x0_spi.h.

#define SPI_I2SCTL_I2SEN BIT(10)

I2S enable

Definition at line 91 of file gd32f3x0_spi.h.

#define SPI_I2SCTL_I2SOPMOD BITS(8,9)

I2S operation mode

Definition at line 90 of file gd32f3x0_spi.h.

#define SPI_I2SCTL_I2SSEL BIT(11)

I2S mode selection

Definition at line 92 of file gd32f3x0_spi.h.

#define SPI_I2SCTL_I2SSTD BITS(4,5)

I2S standard selection

Definition at line 88 of file gd32f3x0_spi.h.

#define SPI_I2SCTL_PCMSMOD BIT(7)

PCM frame synchronization mode

Definition at line 89 of file gd32f3x0_spi.h.

#define SPI_I2SPSC ( spix ) REG32((spix) + 0x20U)

SPI I2S clock prescaler register

Definition at line 31 of file gd32f3x0_spi.h.

#define SPI_I2SPSC_DIV BITS(0,7)

dividing factor for the prescaler

Definition at line 95 of file gd32f3x0_spi.h.

#define SPI_I2SPSC_MCKOEN BIT(9)

I2S MCK output enable

Definition at line 97 of file gd32f3x0_spi.h.

#define SPI_I2SPSC_OF BIT(8)

odd factor for the prescaler

Definition at line 96 of file gd32f3x0_spi.h.

#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U)

config error interrupt flag

Definition at line 220 of file gd32f3x0_spi.h.

#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U)

CRC error interrupt flag

Definition at line 221 of file gd32f3x0_spi.h.

#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS)

SPI as master

Definition at line 118 of file gd32f3x0_spi.h.

#define SPI_NSS_HARD ((uint32_t)0x00000000U)

SPI NSS control by hardware

Definition at line 133 of file gd32f3x0_spi.h.

#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN

SPI NSS control by sofrware

Definition at line 132 of file gd32f3x0_spi.h.

#define SPI_PSC_128 CTL0_PSC(6)

SPI clock prescale factor is 128

Definition at line 153 of file gd32f3x0_spi.h.

#define SPI_PSC_16 CTL0_PSC(3)

SPI clock prescale factor is 16

Definition at line 150 of file gd32f3x0_spi.h.

#define SPI_PSC_2 CTL0_PSC(0)

SPI clock prescale factor is 2

Definition at line 147 of file gd32f3x0_spi.h.

#define SPI_PSC_256 CTL0_PSC(7)

SPI clock prescale factor is 256

Definition at line 154 of file gd32f3x0_spi.h.

#define SPI_PSC_32 CTL0_PSC(4)

SPI clock prescale factor is 32

Definition at line 151 of file gd32f3x0_spi.h.

#define SPI_PSC_4 CTL0_PSC(1)

SPI clock prescale factor is 4

Definition at line 148 of file gd32f3x0_spi.h.

#define SPI_PSC_64 CTL0_PSC(5)

SPI clock prescale factor is 64

Definition at line 152 of file gd32f3x0_spi.h.

#define SPI_PSC_8 CTL0_PSC(2)

SPI clock prescale factor is 8

Definition at line 149 of file gd32f3x0_spi.h.

#define SPI_QCTL ( spix ) REG32((spix) + 0x80U)

SPI quad mode control register(only SPI1)

Definition at line 32 of file gd32f3x0_spi.h.

#define SPI_QCTL_IO23_DRV BIT(2)

drive SPI_IO2 and SPI_IO3 enable

Definition at line 102 of file gd32f3x0_spi.h.

#define SPI_QCTL_QMOD BIT(0)

quad-SPI mode enable

Definition at line 100 of file gd32f3x0_spi.h.

#define SPI_QCTL_QRD BIT(1)

quad-SPI mode read select

Definition at line 101 of file gd32f3x0_spi.h.

#define SPI_RCRC ( spix ) REG32((spix) + 0x14U)

SPI receive CRC register

Definition at line 28 of file gd32f3x0_spi.h.

#define SPI_RCRC_RCR BITS(0,15)

RX CRC register

Definition at line 79 of file gd32f3x0_spi.h.

#define SPI_SLAVE ((uint32_t)0x00000000U)

SPI as slave

Definition at line 119 of file gd32f3x0_spi.h.

#define SPI_STAT ( spix ) REG32((spix) + 0x08U)

SPI status register

Definition at line 25 of file gd32f3x0_spi.h.

#define SPI_STAT_CONFERR BIT(5)

SPI configuration error bit

Definition at line 67 of file gd32f3x0_spi.h.

#define SPI_STAT_CRCERR BIT(4)

SPI CRC error bit

Definition at line 66 of file gd32f3x0_spi.h.

#define SPI_STAT_FERR BIT(8)

format error bit

Definition at line 70 of file gd32f3x0_spi.h.

#define SPI_STAT_I2SCH BIT(2)

I2S channel side

Definition at line 64 of file gd32f3x0_spi.h.

#define SPI_STAT_RBNE BIT(0)

receive buffer not empty

Definition at line 62 of file gd32f3x0_spi.h.

#define SPI_STAT_RXORERR BIT(6)

SPI reception overrun error bit

Definition at line 68 of file gd32f3x0_spi.h.

#define SPI_STAT_TBE BIT(1)

transmit buffer empty

Definition at line 63 of file gd32f3x0_spi.h.

#define SPI_STAT_TRANS BIT(7)

transmitting on-going bit

Definition at line 69 of file gd32f3x0_spi.h.

#define SPI_STAT_TXURERR BIT(3)

I2S transmission underrun error bit

Definition at line 65 of file gd32f3x0_spi.h.

#define SPI_TCRC ( spix ) REG32((spix) + 0x18U)

SPI transmit CRC register

Definition at line 29 of file gd32f3x0_spi.h.

#define SPI_TCRC_TCR BITS(0,15)

RX CRC register

Definition at line 82 of file gd32f3x0_spi.h.

#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN

bidirectional receive data

Definition at line 124 of file gd32f3x0_spi.h.

#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN)

bidirectional transmit data

Definition at line 125 of file gd32f3x0_spi.h.

#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U)

SPI receive and send data at fullduplex communication

Definition at line 122 of file gd32f3x0_spi.h.

#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO

SPI only receive data

Definition at line 123 of file gd32f3x0_spi.h.

Function Documentation

void qspi_disable ( uint32_t spi_periph )

disable quad wire SPI

Parameters
[in] | spi_periph | SPI1
[out] | none
Return values
none

Definition at line 692 of file gd32f3x0_spi.c.

693 {
694 SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD);
695 }
SPI_QCTL
#define SPI_QCTL(spix)
Definition: gd32f3x0_spi.h:32
SPI_QCTL_QMOD
#define SPI_QCTL_QMOD
Definition: gd32f3x0_spi.h:100
void qspi_enable ( uint32_t spi_periph )

enable quad wire SPI

Parameters
[in] | spi_periph | SPI1
[out] | none
Return values
none

Definition at line 681 of file gd32f3x0_spi.c.

682 {
683 SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD;
684 }
SPI_QCTL
#define SPI_QCTL(spix)
Definition: gd32f3x0_spi.h:32
SPI_QCTL_QMOD
#define SPI_QCTL_QMOD
Definition: gd32f3x0_spi.h:100
void qspi_io23_output_disable ( uint32_t spi_periph )

disable SPI_IO2 and SPI_IO3 pin output

Parameters
[in] | spi_periph | SPI1
[out] | none
Return values
none

Definition at line 736 of file gd32f3x0_spi.c.

737 {
738 SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV);
739 }
SPI_QCTL
#define SPI_QCTL(spix)
Definition: gd32f3x0_spi.h:32
SPI_QCTL_IO23_DRV
#define SPI_QCTL_IO23_DRV
Definition: gd32f3x0_spi.h:102
void qspi_io23_output_enable ( uint32_t spi_periph )

enable SPI_IO2 and SPI_IO3 pin output

Parameters
[in] | spi_periph | SPI1
[out] | none
Return values
none

Definition at line 725 of file gd32f3x0_spi.c.

726 {
727 SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV;
728 }
SPI_QCTL
#define SPI_QCTL(spix)
Definition: gd32f3x0_spi.h:32
SPI_QCTL_IO23_DRV
#define SPI_QCTL_IO23_DRV
Definition: gd32f3x0_spi.h:102
void qspi_read_enable ( uint32_t spi_periph )

enable quad wire SPI read

Parameters
[in] | spi_periph | SPI1
[out] | none
Return values
none

Definition at line 714 of file gd32f3x0_spi.c.

715 {
716 SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD;
717 }
SPI_QCTL
#define SPI_QCTL(spix)
Definition: gd32f3x0_spi.h:32
SPI_QCTL_QRD
#define SPI_QCTL_QRD
Definition: gd32f3x0_spi.h:101
void qspi_write_enable ( uint32_t spi_periph )

enable quad wire SPI write

Parameters
[in] | spi_periph | SPI1
[out] | none
Return values
none

Definition at line 703 of file gd32f3x0_spi.c.

704 {
705 SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD);
706 }
SPI_QCTL
#define SPI_QCTL(spix)
Definition: gd32f3x0_spi.h:32
SPI_QCTL_QRD
#define SPI_QCTL_QRD
Definition: gd32f3x0_spi.h:101
void spi_bidirectional_transfer_config | ( | uint32_t | spi_periph,
 |  | uint32_t | transfer_direction
 | ) |  |

configure SPI bidirectional transfer direction

Parameters
[in] spi_periph SPIx(x=0,1,2)
[in] transfer_direction SPI transfer direction
  • SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode
  • SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode
Return values
none

Definition at line 376 of file gd32f3x0_spi.c.

377 {
378 if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){
379 /* set the transmit only mode */
380 SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
381 }else{
382 /* set the receive only mode */
383 SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
384 }
385 }
SPI_BIDIRECTIONAL_RECEIVE
#define SPI_BIDIRECTIONAL_RECEIVE
Definition: gd32f3x0_spi.h:158
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
SPI_BIDIRECTIONAL_TRANSMIT
#define SPI_BIDIRECTIONAL_TRANSMIT
Definition: gd32f3x0_spi.h:157
void spi_crc_error_clear ( uint32_t spi_periph )

clear SPI CRC error flag status

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 551 of file gd32f3x0_spi.c.

552 {
553 SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR);
554 }
SPI_FLAG_CRCERR
#define SPI_FLAG_CRCERR
Definition: gd32f3x0_spi.h:228
SPI_STAT
#define SPI_STAT(spix)
Definition: gd32f3x0_spi.h:25
uint16_t spi_crc_get | ( | uint32_t | spi_periph,
 |  | uint8_t | crc
 | ) |  |

get SPI CRC send value or receive value

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] crc SPI crc value
  • SPI_CRC_TX: get transmit crc value
  • SPI_CRC_RX: get receive crc value
[out] | none
Return values
16-bit CRC value

Definition at line 622 of file gd32f3x0_spi.c.

623 {
624 if(SPI_CRC_TX == crc){
625 return ((uint16_t)(SPI_TCRC(spi_periph)));
626 }else{
627 return ((uint16_t)(SPI_RCRC(spi_periph)));
628 }
629 }
SPI_RCRC
#define SPI_RCRC(spix)
Definition: gd32f3x0_spi.h:28
SPI_CRC_TX
#define SPI_CRC_TX
Definition: gd32f3x0_spi.h:208
SPI_TCRC
#define SPI_TCRC(spix)
Definition: gd32f3x0_spi.h:29
void spi_crc_next ( uint32_t spi_periph )

SPI next data is CRC value.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 608 of file gd32f3x0_spi.c.

609 {
610 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
611 }
SPI_CTL0_CRCNT
#define SPI_CTL0_CRCNT
Definition: gd32f3x0_spi.h:46
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
void spi_crc_off ( uint32_t spi_periph )

turn off CRC function

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 573 of file gd32f3x0_spi.c.

574 {
575 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
576 }
SPI_CTL0_CRCEN
#define SPI_CTL0_CRCEN
Definition: gd32f3x0_spi.h:47
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
void spi_crc_on ( uint32_t spi_periph )

turn on CRC function

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 562 of file gd32f3x0_spi.c.

563 {
564 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
565 }
SPI_CTL0_CRCEN
#define SPI_CTL0_CRCEN
Definition: gd32f3x0_spi.h:47
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
uint16_t spi_crc_polynomial_get ( uint32_t spi_periph )

get SPI CRC polynomial

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
16-bit CRC polynomial

Definition at line 597 of file gd32f3x0_spi.c.

598 {
599 return ((uint16_t)SPI_CRCPOLY(spi_periph));
600 }
SPI_CRCPOLY
#define SPI_CRCPOLY(spix)
Definition: gd32f3x0_spi.h:27
void spi_crc_polynomial_set | ( | uint32_t | spi_periph,
 |  | uint16_t | crc_poly
 | ) |  |

set CRC polynomial

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] | crc_poly | CRC polynomial value
[out] | none
Return values
none

Definition at line 585 of file gd32f3x0_spi.c.

586 {
587 /* set SPI CRC polynomial */
588 SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
589 }
SPI_CRCPOLY
#define SPI_CRCPOLY(spix)
Definition: gd32f3x0_spi.h:27
void spi_disable ( uint32_t spi_periph )

disable SPI

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 110 of file gd32f3x0_spi.c.

111 {
112 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN);
113 }
SPI_CTL0_SPIEN
#define SPI_CTL0_SPIEN
Definition: gd32f3x0_spi.h:40
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
void spi_dma_disable | ( | uint32_t | spi_periph,
 |  | uint8_t | dma
 | ) |  |

disable SPI DMA send or receive

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] dma SPI DMA mode
  • SPI_DMA_TRANSMIT: SPI transmit data use DMA
  • SPI_DMA_RECEIVE: SPI receive data use DMA
[out] | none
Return values
none

Definition at line 319 of file gd32f3x0_spi.c.

320 {
321 if(SPI_DMA_TRANSMIT == dma){
322 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
323 }else{
324 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
325 }
326 }
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_CTL1_DMATEN
#define SPI_CTL1_DMATEN
Definition: gd32f3x0_spi.h:53
SPI_DMA_TRANSMIT
#define SPI_DMA_TRANSMIT
Definition: gd32f3x0_spi.h:204
SPI_CTL1_DMAREN
#define SPI_CTL1_DMAREN
Definition: gd32f3x0_spi.h:52
void spi_dma_enable | ( | uint32_t | spi_periph,
 |  | uint8_t | dma
 | ) |  |

enable SPI DMA send or receive

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] dma SPI DMA mode
  • SPI_DMA_TRANSMIT: SPI transmit data use DMA
  • SPI_DMA_RECEIVE: SPI receive data use DMA
[out] | none
Return values
none

Definition at line 301 of file gd32f3x0_spi.c.

302 {
303 if(SPI_DMA_TRANSMIT == dma){
304 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
305 }else{
306 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
307 }
308 }
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_CTL1_DMATEN
#define SPI_CTL1_DMATEN
Definition: gd32f3x0_spi.h:53
SPI_DMA_TRANSMIT
#define SPI_DMA_TRANSMIT
Definition: gd32f3x0_spi.h:204
SPI_CTL1_DMAREN
#define SPI_CTL1_DMAREN
Definition: gd32f3x0_spi.h:52
void spi_enable ( uint32_t spi_periph )

enable SPI

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 99 of file gd32f3x0_spi.c.

100 {
101 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN;
102 }
SPI_CTL0_SPIEN
#define SPI_CTL0_SPIEN
Definition: gd32f3x0_spi.h:40
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
void spi_i2s_data_frame_format_config | ( | uint32_t | spi_periph,
 |  | uint16_t | frame_format
 | ) |  |

configure SPI/I2S data frame format

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] frame_format SPI frame size
  • SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits
  • SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits
[out] | none
Return values
none

Definition at line 337 of file gd32f3x0_spi.c.

338 {
339 /* clear SPI_CTL0_FF16 bit */
340 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
341 /* confige SPI_CTL0_FF16 bit */
342 SPI_CTL0(spi_periph) |= (uint32_t)frame_format;
343 }
SPI_CTL0_FF16
#define SPI_CTL0_FF16
Definition: gd32f3x0_spi.h:45
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
uint16_t spi_i2s_data_receive ( uint32_t spi_periph )

SPI receive data.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
16-bit data

Definition at line 363 of file gd32f3x0_spi.c.

364 {
365 return ((uint16_t)SPI_DATA(spi_periph));
366 }
SPI_DATA
#define SPI_DATA(spix)
Definition: gd32f3x0_spi.h:26
void spi_i2s_data_transmit | ( | uint32_t | spi_periph,
 |  | uint16_t | data
 | ) |  |

SPI transmit data.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] | data | 16-bit data
[out] | none
Return values
none

Definition at line 352 of file gd32f3x0_spi.c.

353 {
354 SPI_DATA(spi_periph) = (uint32_t)data;
355 }
SPI_DATA
#define SPI_DATA(spix)
Definition: gd32f3x0_spi.h:26
void spi_i2s_deinit ( uint32_t spi_periph )

reset SPI and I2S

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 25 of file gd32f3x0_spi.c.

26 {
27 switch(spi_periph){
28 case SPI0:
29 /* reset SPI0 and I2S0 */
30 rcu_periph_reset_enable(RCU_SPI0RST);
31 rcu_periph_reset_disable(RCU_SPI0RST);
32 break;
33 case SPI1:
34 /* reset SPI1 */
35 rcu_periph_reset_enable(RCU_SPI1RST);
36 rcu_periph_reset_disable(RCU_SPI1RST);
37 break;
38 case SPI2:
39 /* reset SPI2 and I2S2 */
40 rcu_periph_reset_enable(RCU_SPI2RST);
41 rcu_periph_reset_disable(RCU_SPI2RST);
42 break;
43 default :
44 break;
45 }
46 }
SPI1
#define SPI1
Definition: gd32f3x0_spi.h:19
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
RCU_SPI0RST
Definition: gd32f3x0_rcu.h:337
SPI0
#define SPI0
Definition: gd32f3x0_spi.h:18
SPI2
#define SPI2
Definition: gd32f3x0_spi.h:20
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
RCU_SPI1RST
Definition: gd32f3x0_rcu.h:348
RCU_SPI2RST
Definition: gd32f3x0_rcu.h:349
FlagStatus spi_i2s_flag_get | ( | uint32_t | spi_periph,
 |  | uint32_t | flag
 | ) |  |

get SPI and I2S flag status

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] flag SPI/I2S flag status
  • SPI_FLAG_TBE: transmit buffer empty flag
  • SPI_FLAG_RBNE: receive buffer not empty flag
  • SPI_FLAG_TRANS: transmit on-going flag
  • SPI_FLAG_RXORERR: receive overrun error flag
  • SPI_FLAG_CONFERR: mode config error flag
  • SPI_FLAG_CRCERR: CRC error flag
  • SPI_FLAG_FERR: format error interrupt flag
  • I2S_FLAG_TBE: transmit buffer empty flag
  • I2S_FLAG_RBNE: receive buffer not empty flag
  • I2S_FLAG_TRANS: transmit on-going flag
  • I2S_FLAG_RXORERR: overrun error flag
  • I2S_FLAG_TXURERR: underrun error flag
  • I2S_FLAG_CH: channel side flag
  • I2S_FLAG_FERR: format error interrupt flag
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 536 of file gd32f3x0_spi.c.

537 {
538 if(SPI_STAT(spi_periph) & flag){
539 return SET;
540 }else{
541 return RESET;
542 }
543 }
SPI_STAT
#define SPI_STAT(spix)
Definition: gd32f3x0_spi.h:25
void spi_i2s_interrupt_disable | ( | uint32_t | spi_periph,
 |  | uint8_t | interrupt
 | ) |  |

disable SPI and I2S interrupt

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] interrupt SPI/I2S interrupt
  • SPI_I2S_INT_TBE: transmit buffer empty interrupt
  • SPI_I2S_INT_RBNE: receive buffer not empty interrupt
  • SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, transmission underrun error and format error interrupt
[out] | none
Return values
none

Definition at line 429 of file gd32f3x0_spi.c.

430 {
431 switch(interrupt){
432 /* SPI/I2S transmit buffer empty interrupt */
433 case SPI_I2S_INT_TBE:
434 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
435 break;
436 /* SPI/I2S receive buffer not empty interrupt */
437 case SPI_I2S_INT_RBNE:
438 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
439 break;
440 /* SPI/I2S error */
441 case SPI_I2S_INT_ERR:
442 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
443 break;
444 default :
445 break;
446 }
447 }
SPI_I2S_INT_ERR
#define SPI_I2S_INT_ERR
Definition: gd32f3x0_spi.h:214
SPI_CTL1_ERRIE
#define SPI_CTL1_ERRIE
Definition: gd32f3x0_spi.h:57
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_I2S_INT_RBNE
#define SPI_I2S_INT_RBNE
Definition: gd32f3x0_spi.h:213
SPI_CTL1_TBEIE
#define SPI_CTL1_TBEIE
Definition: gd32f3x0_spi.h:59
SPI_I2S_INT_TBE
#define SPI_I2S_INT_TBE
Definition: gd32f3x0_spi.h:212
SPI_CTL1_RBNEIE
#define SPI_CTL1_RBNEIE
Definition: gd32f3x0_spi.h:58
void spi_i2s_interrupt_enable | ( | uint32_t | spi_periph,
 |  | uint8_t | interrupt
 | ) |  |

enable SPI and I2S interrupt

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] interrupt SPI/I2S interrupt
  • SPI_I2S_INT_TBE: transmit buffer empty interrupt
  • SPI_I2S_INT_RBNE: receive buffer not empty interrupt
  • SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, transmission underrun error and format error interrupt
[out] | none
Return values
none

Definition at line 398 of file gd32f3x0_spi.c.

399 {
400 switch(interrupt){
401 /* SPI/I2S transmit buffer empty interrupt */
402 case SPI_I2S_INT_TBE:
403 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
404 break;
405 /* SPI/I2S receive buffer not empty interrupt */
406 case SPI_I2S_INT_RBNE:
407 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE;
408 break;
409 /* SPI/I2S error */
410 case SPI_I2S_INT_ERR:
411 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE;
412 break;
413 default:
414 break;
415 }
416 }
SPI_I2S_INT_ERR
#define SPI_I2S_INT_ERR
Definition: gd32f3x0_spi.h:214
SPI_CTL1_ERRIE
#define SPI_CTL1_ERRIE
Definition: gd32f3x0_spi.h:57
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_I2S_INT_RBNE
#define SPI_I2S_INT_RBNE
Definition: gd32f3x0_spi.h:213
SPI_CTL1_TBEIE
#define SPI_CTL1_TBEIE
Definition: gd32f3x0_spi.h:59
SPI_I2S_INT_TBE
#define SPI_I2S_INT_TBE
Definition: gd32f3x0_spi.h:212
SPI_CTL1_RBNEIE
#define SPI_CTL1_RBNEIE
Definition: gd32f3x0_spi.h:58
FlagStatus spi_i2s_interrupt_flag_get | ( | uint32_t | spi_periph,
 |  | uint8_t | interrupt
 | ) |  |

get SPI and I2S interrupt flag status

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] interrupt SPI/I2S interrupt flag status
  • SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag
  • SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag
  • SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag
  • SPI_INT_FLAG_CONFERR: config error interrupt flag
  • SPI_INT_FLAG_CRCERR: CRC error interrupt flag
  • I2S_INT_FLAG_TXURERR: underrun error interrupt flag
  • SPI_I2S_INT_FLAG_FERR: format error interrupt flag
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 463 of file gd32f3x0_spi.c.

464 {
465 uint32_t reg1 = SPI_STAT(spi_periph);
466 uint32_t reg2 = SPI_CTL1(spi_periph);
467
468 switch(interrupt){
469 /* SPI/I2S transmit buffer empty interrupt */
470 case SPI_I2S_INT_FLAG_TBE:
471 reg1 = reg1 & SPI_STAT_TBE;
472 reg2 = reg2 & SPI_CTL1_TBEIE;
473 break;
474 /* SPI/I2S receive buffer not empty interrupt */
475 case SPI_I2S_INT_FLAG_RBNE:
476 reg1 = reg1 & SPI_STAT_RBNE;
477 reg2 = reg2 & SPI_CTL1_RBNEIE;
478 break;
479 /* SPI/I2S overrun interrupt */
480 case SPI_I2S_INT_FLAG_RXORERR:
481 reg1 = reg1 & SPI_STAT_RXORERR;
482 reg2 = reg2 & SPI_CTL1_ERRIE;
483 break;
484 /* SPI config error interrupt */
485 case SPI_INT_FLAG_CONFERR:
486 reg1 = reg1 & SPI_STAT_CONFERR;
487 reg2 = reg2 & SPI_CTL1_ERRIE;
488 break;
489 /* SPI CRC error interrupt */
490 case SPI_INT_FLAG_CRCERR:
491 reg1 = reg1 & SPI_STAT_CRCERR;
492 reg2 = reg2 & SPI_CTL1_ERRIE;
493 break;
494 /* I2S underrun error interrupt */
495 case I2S_INT_FLAG_TXURERR:
496 reg1 = reg1 & SPI_STAT_TXURERR;
497 reg2 = reg2 & SPI_CTL1_ERRIE;
498 break;
499 /* SPI/I2S format error interrupt */
500 case SPI_I2S_INT_FLAG_FERR:
501 reg1 = reg1 & SPI_STAT_FERR;
502 reg2 = reg2 & SPI_CTL1_ERRIE;
503 break;
504 default :
505 break;
506 }
507 /*get SPI/I2S interrupt flag status */
508 if(reg1 && reg2){
509 return SET;
510 }else{
511 return RESET;
512 }
513 }
SPI_STAT_CONFERR
#define SPI_STAT_CONFERR
Definition: gd32f3x0_spi.h:67
SPI_CTL1_ERRIE
#define SPI_CTL1_ERRIE
Definition: gd32f3x0_spi.h:57
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_STAT_TBE
#define SPI_STAT_TBE
Definition: gd32f3x0_spi.h:63
SPI_STAT
#define SPI_STAT(spix)
Definition: gd32f3x0_spi.h:25
SPI_I2S_INT_FLAG_RBNE
#define SPI_I2S_INT_FLAG_RBNE
Definition: gd32f3x0_spi.h:218
SPI_INT_FLAG_CONFERR
#define SPI_INT_FLAG_CONFERR
Definition: gd32f3x0_spi.h:220
SPI_I2S_INT_FLAG_TBE
#define SPI_I2S_INT_FLAG_TBE
Definition: gd32f3x0_spi.h:217
SPI_STAT_CRCERR
#define SPI_STAT_CRCERR
Definition: gd32f3x0_spi.h:66
SPI_CTL1_TBEIE
#define SPI_CTL1_TBEIE
Definition: gd32f3x0_spi.h:59
SPI_STAT_RBNE
#define SPI_STAT_RBNE
Definition: gd32f3x0_spi.h:62
SPI_I2S_INT_FLAG_FERR
#define SPI_I2S_INT_FLAG_FERR
Definition: gd32f3x0_spi.h:223
SPI_I2S_INT_FLAG_RXORERR
#define SPI_I2S_INT_FLAG_RXORERR
Definition: gd32f3x0_spi.h:219
SPI_INT_FLAG_CRCERR
#define SPI_INT_FLAG_CRCERR
Definition: gd32f3x0_spi.h:221
I2S_INT_FLAG_TXURERR
#define I2S_INT_FLAG_TXURERR
Definition: gd32f3x0_spi.h:222
SPI_STAT_TXURERR
#define SPI_STAT_TXURERR
Definition: gd32f3x0_spi.h:65
SPI_STAT_FERR
#define SPI_STAT_FERR
Definition: gd32f3x0_spi.h:70
SPI_CTL1_RBNEIE
#define SPI_CTL1_RBNEIE
Definition: gd32f3x0_spi.h:58
SPI_STAT_RXORERR
#define SPI_STAT_RXORERR
Definition: gd32f3x0_spi.h:68
void spi_init | ( | uint32_t | spi_periph,
 |  | spi_parameter_struct * | spi_struct
 | ) |  |

initialize SPI parameter

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] | spi_struct | SPI parameter initialization stuct members of the structure and the member values are shown as below: device_mode: SPI_MASTER, SPI_SLAVE trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT nss: SPI_NSS_SOFT, SPI_NSS_HARD endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256)
[out] | none
Return values
none

Definition at line 65 of file gd32f3x0_spi.c.

66 {
67 uint32_t reg = 0U;
68 reg = SPI_CTL0(spi_periph);
69 reg &= SPI_INIT_MASK;
70
71 /* select SPI as master or slave */
72 reg |= spi_struct->device_mode;
73 /* select SPI transfer mode */
74 reg |= spi_struct->trans_mode;
75 /* select SPI frame size */
76 reg |= spi_struct->frame_size;
77 /* select SPI NSS use hardware or software */
78 reg |= spi_struct->nss;
79 /* select SPI LSB or MSB */
80 reg |= spi_struct->endian;
81 /* select SPI polarity and phase */
82 reg |= spi_struct->clock_polarity_phase;
83 /* select SPI prescale to adjust transmit speed */
84 reg |= spi_struct->prescale;
85
86 /* write to SPI_CTL0 register */
87 SPI_CTL0(spi_periph) = (uint32_t)reg;
88
89 /* select SPI mode */
90 SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL);
91 }
spi_parameter_struct::nss
uint32_t nss
Definition: gd32f3x0_spi.h:111
spi_parameter_struct::device_mode
uint32_t device_mode
Definition: gd32f3x0_spi.h:108
spi_parameter_struct::frame_size
uint32_t frame_size
Definition: gd32f3x0_spi.h:110
spi_parameter_struct::trans_mode
uint32_t trans_mode
Definition: gd32f3x0_spi.h:109
SPI_INIT_MASK
#define SPI_INIT_MASK
Definition: gd32f3x0_spi.c:14
SPI_I2SCTL_I2SSEL
#define SPI_I2SCTL_I2SSEL
Definition: gd32f3x0_spi.h:92
spi_parameter_struct::endian
uint32_t endian
Definition: gd32f3x0_spi.h:112
spi_parameter_struct::clock_polarity_phase
uint32_t clock_polarity_phase
Definition: gd32f3x0_spi.h:113
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
SPI_I2SCTL
#define SPI_I2SCTL(spix)
Definition: gd32f3x0_spi.h:30
spi_parameter_struct::prescale
uint32_t prescale
Definition: gd32f3x0_spi.h:114
void spi_nss_internal_high ( uint32_t spi_periph )

SPI NSS pin high level in software mode.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 276 of file gd32f3x0_spi.c.

277 {
278 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS;
279 }
SPI_CTL0_SWNSS
#define SPI_CTL0_SWNSS
Definition: gd32f3x0_spi.h:42
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
void spi_nss_internal_low ( uint32_t spi_periph )

SPI NSS pin low level in software mode.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 287 of file gd32f3x0_spi.c.

288 {
289 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS);
290 }
SPI_CTL0_SWNSS
#define SPI_CTL0_SWNSS
Definition: gd32f3x0_spi.h:42
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
void spi_nss_output_disable ( uint32_t spi_periph )

disable SPI NSS output

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 265 of file gd32f3x0_spi.c.

266 {
267 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
268 }
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_CTL1_NSSDRV
#define SPI_CTL1_NSSDRV
Definition: gd32f3x0_spi.h:54
void spi_nss_output_enable ( uint32_t spi_periph )

enable SPI NSS output

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 254 of file gd32f3x0_spi.c.

255 {
256 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
257 }
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_CTL1_NSSDRV
#define SPI_CTL1_NSSDRV
Definition: gd32f3x0_spi.h:54
void spi_nssp_mode_disable ( uint32_t spi_periph )

disable SPI NSS pulse mode

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 670 of file gd32f3x0_spi.c.

671 {
672 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP);
673 }
SPI_CTL1_NSSP
#define SPI_CTL1_NSSP
Definition: gd32f3x0_spi.h:55
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
void spi_nssp_mode_enable ( uint32_t spi_periph )

enable SPI NSS pulse mode

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 659 of file gd32f3x0_spi.c.

660 {
661 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP;
662 }
SPI_CTL1_NSSP
#define SPI_CTL1_NSSP
Definition: gd32f3x0_spi.h:55
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
void spi_ti_mode_disable ( uint32_t spi_periph )

disable SPI TI mode

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 648 of file gd32f3x0_spi.c.

649 {
650 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD);
651 }
SPI_CTL1_TMOD
#define SPI_CTL1_TMOD
Definition: gd32f3x0_spi.h:56
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
void spi_ti_mode_enable ( uint32_t spi_periph )

enable SPI TI mode

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 637 of file gd32f3x0_spi.c.

638 {
639 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD;
640 }
SPI_CTL1_TMOD
#define SPI_CTL1_TMOD
Definition: gd32f3x0_spi.h:56
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_syscfg.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Functions
gd32f3x0_syscfg.h File Reference

definitions for the SYSCFG More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | SYSCFG SYSCFG_BASE
#define | SYSCFG_CFG0 REG32(SYSCFG + 0x00U)
#define | SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U)
#define | SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU)
#define | SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U)
#define | SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U)
#define | SYSCFG_CFG2 REG32(SYSCFG + 0x18U)
#define | SYSCFG_CPSCTL REG32(SYSCFG + 0x20U)
#define | SYSCFG_CFG0_BOOT_MODE BITS(0,1)
#define | SYSCFG_CFG0_ADC_DMA_RMP BIT(8)
#define | SYSCFG_CFG0_USART0_TX_DMA_RMP BIT(9)
#define | SYSCFG_CFG0_USART0_RX_DMA_RMP BIT(10)
#define | SYSCFG_CFG0_TIMER15_DMA_RMP BIT(11)
#define | SYSCFG_CFG0_TIMER16_DMA_RMP BIT(12)
#define | SYSCFG_CFG0_PB9_HCCE BIT(19)
#define | SYSCFG_EXTISS0_EXTI0_SS BITS(0,3)
#define | SYSCFG_EXTISS0_EXTI1_SS BITS(4,7)
#define | SYSCFG_EXTISS0_EXTI2_SS BITS(8,11)
#define | SYSCFG_EXTISS0_EXTI3_SS BITS(12,15)
#define | SYSCFG_EXTISS1_EXTI4_SS BITS(0,3)
#define | SYSCFG_EXTISS1_EXTI5_SS BITS(4,7)
#define | SYSCFG_EXTISS1_EXTI6_SS BITS(8,11)
#define | SYSCFG_EXTISS1_EXTI7_SS BITS(12,15)
#define | SYSCFG_EXTISS2_EXTI8_SS BITS(0,3)
#define | SYSCFG_EXTISS2_EXTI9_SS BITS(4,7)
#define | SYSCFG_EXTISS2_EXTI10_SS BITS(8,11)
#define | SYSCFG_EXTISS2_EXTI11_SS BITS(12,15)
#define | SYSCFG_EXTISS3_EXTI12_SS BITS(0,3)
#define | SYSCFG_EXTISS3_EXTI13_SS BITS(4,7)
#define | SYSCFG_EXTISS3_EXTI14_SS BITS(8,11)
#define | SYSCFG_EXTISS3_EXTI15_SS BITS(12,15)
#define | SYSCFG_CFG2_LOCKUP_LOCK BIT(0)
#define | SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK BIT(1)
#define | SYSCFG_CFG2_LVD_LOCK BIT(2)
#define | SYSCFG_CFG2_SRAM_PCEF BIT(8)
#define | SYSCFG_CPSCTL_CPS_EN BIT(0)
#define | SYSCFG_CPSCTL_CPS_RDY BIT(8)
#define | SYSCFG_DMA_REMAP_ADC SYSCFG_CFG0_ADC_DMA_RMP
#define | SYSCFG_DMA_REMAP_USART0TX SYSCFG_CFG0_USART0_TX_DMA_RMP
#define | SYSCFG_DMA_REMAP_USART0RX SYSCFG_CFG0_USART0_RX_DMA_RMP
#define | SYSCFG_DMA_REMAP_TIMER15 SYSCFG_CFG0_TIMER15_DMA_RMP
#define | SYSCFG_DMA_REMAP_TIMER16 SYSCFG_CFG0_TIMER16_DMA_RMP
#define | SYSCFG_HIGH_CURRENT_ENABLE SYSCFG_CFG0_PB9_HCCE
#define | SYSCFG_HIGH_CURRENT_DISABLE (~SYSCFG_CFG0_PB9_HCCE)
#define | EXTISS0 ((uint8_t)0x00U)
#define | EXTISS1 ((uint8_t)0x01U)
#define | EXTISS2 ((uint8_t)0x02U)
#define | EXTISS3 ((uint8_t)0x03U)
#define | EXTI_SS_MASK BITS(0,3)
#define | EXTI_SS_JSTEP ((uint8_t)(0x04U))
#define | EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP))
#define | EXTI_SOURCE_GPIOA ((uint8_t)0x00U)
#define | EXTI_SOURCE_GPIOB ((uint8_t)0x01U)
#define | EXTI_SOURCE_GPIOC ((uint8_t)0x02U)
#define | EXTI_SOURCE_GPIOD ((uint8_t)0x03U)
#define | EXTI_SOURCE_GPIOF ((uint8_t)0x05U)
#define | EXTI_SOURCE_PIN0 ((uint8_t)0x00U)
#define | EXTI_SOURCE_PIN1 ((uint8_t)0x01U)
#define | EXTI_SOURCE_PIN2 ((uint8_t)0x02U)
#define | EXTI_SOURCE_PIN3 ((uint8_t)0x03U)
#define | EXTI_SOURCE_PIN4 ((uint8_t)0x04U)
#define | EXTI_SOURCE_PIN5 ((uint8_t)0x05U)
#define | EXTI_SOURCE_PIN6 ((uint8_t)0x06U)
#define | EXTI_SOURCE_PIN7 ((uint8_t)0x07U)
#define | EXTI_SOURCE_PIN8 ((uint8_t)0x08U)
#define | EXTI_SOURCE_PIN9 ((uint8_t)0x09U)
#define | EXTI_SOURCE_PIN10 ((uint8_t)0x0AU)
#define | EXTI_SOURCE_PIN11 ((uint8_t)0x0BU)
#define | EXTI_SOURCE_PIN12 ((uint8_t)0x0CU)
#define | EXTI_SOURCE_PIN13 ((uint8_t)0x0DU)
#define | EXTI_SOURCE_PIN14 ((uint8_t)0x0EU)
#define | EXTI_SOURCE_PIN15 ((uint8_t)0x0FU)
#define | SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK
#define | SYSCFG_LOCK_SRAM_PARITY_ERROR SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK
#define | SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK
#define | SYSCFG_SRAM_PCEF SYSCFG_CFG2_SRAM_PCEF
#define | SYSCFG_COMPENSATION(regval) (BIT(0) & ((uint32_t)(regval) << 0))
#define | SYSCFG_COMPENSATION_DISABLE SYSCFG_COMPENSATION(0)
#define | SYSCFG_COMPENSATION_ENABLE SYSCFG_COMPENSATION(1)

Functions

void | syscfg_deinit (void)
reset the SYSCFG registers More...
void | syscfg_dma_remap_enable (uint32_t syscfg_dma_remap)
enable the DMA channels remapping More...
void | syscfg_dma_remap_disable (uint32_t syscfg_dma_remap)
disable the DMA channels remapping More...
void | syscfg_high_current_enable (void)
enable PB9 high current capability More...
void | syscfg_high_current_disable (void)
disable PB9 high current capability More...
void | syscfg_exti_line_config (uint8_t exti_port, uint8_t exti_pin)
configure the GPIO pin as EXTI Line More...
void | syscfg_lock_config (uint32_t syscfg_lock)
connect TIMER0/14/15/16 break input to the selected parameter More...
FlagStatus | syscfg_flag_get (uint32_t syscfg_flag)
check if the specified flag in SYSCFG_CFG2 is set or not. More...
void | syscfg_flag_clear (uint32_t syscfg_flag)
clear the flag in SYSCFG_CFG2 by writing 1. More...
void | syscfg_compensation_config (uint32_t syscfg_compensation)
configure the I/O compensation cell More...
FlagStatus | syscfg_cps_rdy_flag_get (void)
check if the I/O compensation cell ready flag is set or not More...

Detailed Description

definitions for the SYSCFG

Definition in file gd32f3x0_syscfg.h.

Macro Definition Documentation

#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U)

EXTI GPIOA configuration

Definition at line 100 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U)

EXTI GPIOB configuration

Definition at line 101 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U)

EXTI GPIOC configuration

Definition at line 102 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_GPIOD ((uint8_t)0x03U)

EXTI GPIOD configuration

Definition at line 103 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U)

EXTI GPIOF configuration

Definition at line 104 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U)

EXTI GPIO pin0 configuration

Definition at line 107 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U)

EXTI GPIO pin1 configuration

Definition at line 108 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU)

EXTI GPIO pin10 configuration

Definition at line 117 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU)

EXTI GPIO pin11 configuration

Definition at line 118 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU)

EXTI GPIO pin12 configuration

Definition at line 119 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU)

EXTI GPIO pin13 configuration

Definition at line 120 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU)

EXTI GPIO pin14 configuration

Definition at line 121 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU)

EXTI GPIO pin15 configuration

Definition at line 122 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U)

EXTI GPIO pin2 configuration

Definition at line 109 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U)

EXTI GPIO pin3 configuration

Definition at line 110 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U)

EXTI GPIO pin4 configuration

Definition at line 111 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U)

EXTI GPIO pin5 configuration

Definition at line 112 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U)

EXTI GPIO pin6 configuration

Definition at line 113 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U)

EXTI GPIO pin7 configuration

Definition at line 114 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U)

EXTI GPIO pin8 configuration

Definition at line 115 of file gd32f3x0_syscfg.h.

#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U)

EXTI GPIO pin9 configuration

Definition at line 116 of file gd32f3x0_syscfg.h.

#define EXTI_SS_JSTEP ((uint8_t)(0x04U))

EXTI source select jumping step

Definition at line 94 of file gd32f3x0_syscfg.h.

#define EXTI_SS_MASK BITS(0,3)

EXTI source select mask

Definition at line 91 of file gd32f3x0_syscfg.h.

#define EXTI_SS_MSTEP ( pin ) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP))

EXTI source select moving step

Definition at line 97 of file gd32f3x0_syscfg.h.

#define EXTISS0 ((uint8_t)0x00U)

EXTI source select register 0

Definition at line 85 of file gd32f3x0_syscfg.h.

#define EXTISS1 ((uint8_t)0x01U)

EXTI source select register 1

Definition at line 86 of file gd32f3x0_syscfg.h.

#define EXTISS2 ((uint8_t)0x02U)

EXTI source select register 2

Definition at line 87 of file gd32f3x0_syscfg.h.

#define EXTISS3 ((uint8_t)0x03U)

EXTI source select register 3

Definition at line 88 of file gd32f3x0_syscfg.h.

#define SYSCFG SYSCFG_BASE

Definition at line 18 of file gd32f3x0_syscfg.h.

#define SYSCFG_CFG0 REG32(SYSCFG + 0x00U)

system configuration register 0

Definition at line 21 of file gd32f3x0_syscfg.h.

#define SYSCFG_CFG0_ADC_DMA_RMP BIT(8)

ADC DMA remap config

Definition at line 31 of file gd32f3x0_syscfg.h.

#define SYSCFG_CFG0_BOOT_MODE BITS(0,1)

SYSCFG memory remap config

Definition at line 30 of file gd32f3x0_syscfg.h.

#define SYSCFG_CFG0_PB9_HCCE BIT(19)

PB9 pin high current capability enable

Definition at line 36 of file gd32f3x0_syscfg.h.

#define SYSCFG_CFG0_TIMER15_DMA_RMP BIT(11)

TIMER 15 DMA remap config

Definition at line 34 of file gd32f3x0_syscfg.h.

#define SYSCFG_CFG0_TIMER16_DMA_RMP BIT(12)

TIMER 16 DMA remap config

Definition at line 35 of file gd32f3x0_syscfg.h.

#define SYSCFG_CFG0_USART0_RX_DMA_RMP BIT(10)

USART0 Rx DMA remap config

Definition at line 33 of file gd32f3x0_syscfg.h.

#define SYSCFG_CFG0_USART0_TX_DMA_RMP BIT(9)

USART0 Tx DMA remap config

Definition at line 32 of file gd32f3x0_syscfg.h.

#define SYSCFG_CFG2 REG32(SYSCFG + 0x18U)

system configuration register 2

Definition at line 26 of file gd32f3x0_syscfg.h.

#define SYSCFG_CFG2_LOCKUP_LOCK BIT(0)

enable and lock the LOCKUP (Hardfault) output of Cortex-M4 with break input of TIMER0/14/15/16

Definition at line 63 of file gd32f3x0_syscfg.h.

#define SYSCFG_CFG2_LVD_LOCK BIT(2)

enable and lock the LVD connection with TIMER0 break input and also the LVD_EN and LVDSEL[2:0] bits of the power control interface

Definition at line 65 of file gd32f3x0_syscfg.h.

#define SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK BIT(1)

enable and lock the SRAM_PARITY error signal with break input of TIMER0/14/15/16

Definition at line 64 of file gd32f3x0_syscfg.h.

#define SYSCFG_CFG2_SRAM_PCEF BIT(8)

SRAM parity check error flag

Definition at line 66 of file gd32f3x0_syscfg.h.

#define SYSCFG_COMPENSATION ( regval ) (BIT(0) & ((uint32_t)(regval) << 0))

Definition at line 133 of file gd32f3x0_syscfg.h.

#define SYSCFG_COMPENSATION_DISABLE SYSCFG_COMPENSATION(0)

I/O compensation cell is power-down

Definition at line 134 of file gd32f3x0_syscfg.h.

#define SYSCFG_COMPENSATION_ENABLE SYSCFG_COMPENSATION(1)

I/O compensation cell is enabled

Definition at line 135 of file gd32f3x0_syscfg.h.

#define SYSCFG_CPSCTL REG32(SYSCFG + 0x20U)

system I/O compensation control register

Definition at line 27 of file gd32f3x0_syscfg.h.

#define SYSCFG_CPSCTL_CPS_EN BIT(0)

I/O compensation cell enable

Definition at line 69 of file gd32f3x0_syscfg.h.

#define SYSCFG_CPSCTL_CPS_RDY BIT(8)

I/O compensation cell is ready or not

Definition at line 70 of file gd32f3x0_syscfg.h.

#define SYSCFG_DMA_REMAP_ADC SYSCFG_CFG0_ADC_DMA_RMP

ADC DMA remap

Definition at line 74 of file gd32f3x0_syscfg.h.

#define SYSCFG_DMA_REMAP_TIMER15 SYSCFG_CFG0_TIMER15_DMA_RMP

TIMER15 DMA remap

Definition at line 77 of file gd32f3x0_syscfg.h.

#define SYSCFG_DMA_REMAP_TIMER16 SYSCFG_CFG0_TIMER16_DMA_RMP

TIMER16 DMA remap

Definition at line 78 of file gd32f3x0_syscfg.h.

#define SYSCFG_DMA_REMAP_USART0RX SYSCFG_CFG0_USART0_RX_DMA_RMP

USART0_RX DMA remap

Definition at line 76 of file gd32f3x0_syscfg.h.

#define SYSCFG_DMA_REMAP_USART0TX SYSCFG_CFG0_USART0_TX_DMA_RMP

USART0_TX DMA remap

Definition at line 75 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U)

EXTI sources selection register 0

Definition at line 22 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3)

EXTI 0 configuration

Definition at line 39 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7)

EXTI 1 configuration

Definition at line 40 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11)

EXTI 2 configuration

Definition at line 41 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15)

EXTI 3 configuration

Definition at line 42 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU)

EXTI sources selection register 1

Definition at line 23 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3)

EXTI 4 configuration

Definition at line 45 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7)

EXTI 5 configuration

Definition at line 46 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11)

EXTI 6 configuration

Definition at line 47 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15)

EXTI 7 configuration

Definition at line 48 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U)

EXTI sources selection register 2

Definition at line 24 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11)

EXTI 10 configuration

Definition at line 53 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15)

EXTI 11 configuration

Definition at line 54 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3)

EXTI 8 configuration

Definition at line 51 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7)

EXTI 9 configuration

Definition at line 52 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U)

EXTI sources selection register 3

Definition at line 25 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3)

EXTI 12 configuration

Definition at line 57 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7)

EXTI 13 configuration

Definition at line 58 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11)

EXTI 14 configuration

Definition at line 59 of file gd32f3x0_syscfg.h.

#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15)

EXTI 15 configuration

Definition at line 60 of file gd32f3x0_syscfg.h.

#define SYSCFG_HIGH_CURRENT_DISABLE (~SYSCFG_CFG0_PB9_HCCE)

high current disable

Definition at line 82 of file gd32f3x0_syscfg.h.

#define SYSCFG_HIGH_CURRENT_ENABLE SYSCFG_CFG0_PB9_HCCE

high current enable

Definition at line 81 of file gd32f3x0_syscfg.h.

#define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK

LOCKUP output lock

Definition at line 125 of file gd32f3x0_syscfg.h.

#define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK

LVD lock

Definition at line 127 of file gd32f3x0_syscfg.h.

#define SYSCFG_LOCK_SRAM_PARITY_ERROR SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK

SRAM parity error lock

Definition at line 126 of file gd32f3x0_syscfg.h.

#define SYSCFG_SRAM_PCEF SYSCFG_CFG2_SRAM_PCEF

SRAM parity check error flag

Definition at line 130 of file gd32f3x0_syscfg.h.

Function Documentation

void syscfg_compensation_config ( uint32_t syscfg_compensation )

configure the I/O compensation cell

Parameters
[in] syscfg_compensation specifies the I/O compensation cell mode
  • SYSCFG_COMPENSATION_ENABLE: I/O compensation cell is enabled
  • SYSCFG_COMPENSATION_DISABLE: I/O compensation cell is disabled
[out] none
Return values
none

Definition at line 174 of file gd32f3x0_syscfg.c.

175 {
176 uint32_t reg;
177
178 reg = SYSCFG_CPSCTL;
179 /* reset the SYSCFG_CPSCTL_CPS_EN bit and set according to syscfg_compensation */
180 reg &= ~SYSCFG_CPSCTL_CPS_EN;
181 SYSCFG_CPSCTL = (reg | syscfg_compensation);
182 }
SYSCFG_CPSCTL_CPS_EN
#define SYSCFG_CPSCTL_CPS_EN
Definition: gd32f3x0_syscfg.h:69
SYSCFG_CPSCTL
#define SYSCFG_CPSCTL
Definition: gd32f3x0_syscfg.h:27
FlagStatus syscfg_cps_rdy_flag_get ( void )

check if the I/O compensation cell ready flag is set or not

Parameters
[in] | none
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 190 of file gd32f3x0_syscfg.c.

191 {
192 if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)){
193 return SET;
194 }else{
195 return RESET;
196 }
197 }
SYSCFG_CPSCTL_CPS_RDY
#define SYSCFG_CPSCTL_CPS_RDY
Definition: gd32f3x0_syscfg.h:70
SYSCFG_CPSCTL
#define SYSCFG_CPSCTL
Definition: gd32f3x0_syscfg.h:27
void syscfg_deinit ( void )

reset the SYSCFG registers

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_syscfg.c.

21 {
22 rcu_periph_reset_enable(RCU_CFGCMPRST);
23 rcu_periph_reset_disable(RCU_CFGCMPRST);
24 }
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
RCU_CFGCMPRST
Definition: gd32f3x0_rcu.h:334
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
void syscfg_dma_remap_disable ( uint32_t syscfg_dma_remap )

disable the DMA channels remapping

Parameters
[in] syscfg_dma_remap specify the DMA channels to remap
  • SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
  • SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
  • SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
  • SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1)
  • SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1
[out] none
Return values
none

Definition at line 53 of file gd32f3x0_syscfg.c.

54 {
55 SYSCFG_CFG0 &= ~syscfg_dma_remap;
56 }
SYSCFG_CFG0
#define SYSCFG_CFG0
Definition: gd32f3x0_syscfg.h:21
void syscfg_dma_remap_enable ( uint32_t syscfg_dma_remap )

enable the DMA channels remapping

Parameters
[in] syscfg_dma_remap specify the DMA channels to remap
  • SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
  • SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
  • SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
  • SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1)
  • SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1
[out] none
Return values
none

Definition at line 37 of file gd32f3x0_syscfg.c.

38 {
39 SYSCFG_CFG0 |= syscfg_dma_remap;
40 }
SYSCFG_CFG0
#define SYSCFG_CFG0
Definition: gd32f3x0_syscfg.h:21
void syscfg_exti_line_config | ( | uint8_t | exti_port,
 |  | uint8_t | exti_pin
 | ) |  |

configure the GPIO pin as EXTI Line

Parameters
[in] exti_port specify the GPIO port used in EXTI
  • EXTI_SOURCE_GPIOx(x = A,B,C,D,F): EXTI GPIO port
[in] exti_pin specify the EXTI line
  • EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin
[out] none
Return values
none

Definition at line 89 of file gd32f3x0_syscfg.c.

90 {
91 uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin)));
92 uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin));
93
94 switch(exti_pin / EXTI_SS_JSTEP){
95 case EXTISS0:
96 /* clear EXTI source line(0..3) */
97 SYSCFG_EXTISS0 &= clear_exti_mask;
98 /* configure EXTI soure line(0..3) */
99 SYSCFG_EXTISS0 |= config_exti_mask;
100 break;
101 case EXTISS1:
102 /* clear EXTI soure line(4..7) */
103 SYSCFG_EXTISS1 &= clear_exti_mask;
104 /* configure EXTI soure line(4..7) */
105 SYSCFG_EXTISS1 |= config_exti_mask;
106 break;
107 case EXTISS2:
108 /* clear EXTI soure line(8..11) */
109 SYSCFG_EXTISS2 &= clear_exti_mask;
110 /* configure EXTI soure line(8..11) */
111 SYSCFG_EXTISS2 |= config_exti_mask;
112 break;
113 case EXTISS3:
114 /* clear EXTI soure line(12..15) */
115 SYSCFG_EXTISS3 &= clear_exti_mask;
116 /* configure EXTI soure line(12..15) */
117 SYSCFG_EXTISS3 |= config_exti_mask;
118 break;
119 default:
120 break;
121 }
122 }
SYSCFG_EXTISS1
#define SYSCFG_EXTISS1
Definition: gd32f3x0_syscfg.h:23
SYSCFG_EXTISS0
#define SYSCFG_EXTISS0
Definition: gd32f3x0_syscfg.h:22
EXTI_SS_MASK
#define EXTI_SS_MASK
Definition: gd32f3x0_syscfg.h:91
EXTISS2
#define EXTISS2
Definition: gd32f3x0_syscfg.h:87
EXTI_SS_JSTEP
#define EXTI_SS_JSTEP
Definition: gd32f3x0_syscfg.h:94
EXTI_SS_MSTEP
#define EXTI_SS_MSTEP(pin)
Definition: gd32f3x0_syscfg.h:97
EXTISS1
#define EXTISS1
Definition: gd32f3x0_syscfg.h:86
SYSCFG_EXTISS3
#define SYSCFG_EXTISS3
Definition: gd32f3x0_syscfg.h:25
EXTISS0
#define EXTISS0
Definition: gd32f3x0_syscfg.h:85
SYSCFG_EXTISS2
#define SYSCFG_EXTISS2
Definition: gd32f3x0_syscfg.h:24
EXTISS3
#define EXTISS3
Definition: gd32f3x0_syscfg.h:88
void syscfg_flag_clear ( uint32_t syscfg_flag )

clear the flag in SYSCFG_CFG2 by writing 1.

Parameters
[in] syscfg_flag Specify the flag in SYSCFG_CFG2 to clear.
  • SYSCFG_SRAM_PCEF: SRAM parity check error flag.
[out] none
Return values
none

Definition at line 161 of file gd32f3x0_syscfg.c.

162 {
163 SYSCFG_CFG2 |= (uint32_t) syscfg_flag;
164 }
SYSCFG_CFG2
#define SYSCFG_CFG2
Definition: gd32f3x0_syscfg.h:26
FlagStatus syscfg_flag_get ( uint32_t syscfg_flag )

check if the specified flag in SYSCFG_CFG2 is set or not.

Parameters
[in] syscfg_flag specify the flag in SYSCFG_CFG2 to check.
  • SYSCFG_SRAM_PCEF: SRAM parity check error flag.
[out] none
Return values
the syscfg_flag state returned (SET or RESET).

Definition at line 145 of file gd32f3x0_syscfg.c.

146 {
147 if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET){
148 return SET;
149 }else{
150 return RESET;
151 }
152 }
SYSCFG_CFG2
#define SYSCFG_CFG2
Definition: gd32f3x0_syscfg.h:26
void syscfg_high_current_disable ( void )

disable PB9 high current capability

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 75 of file gd32f3x0_syscfg.c.

76 {
77 SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE;
78 }
SYSCFG_CFG0
#define SYSCFG_CFG0
Definition: gd32f3x0_syscfg.h:21
SYSCFG_HIGH_CURRENT_DISABLE
#define SYSCFG_HIGH_CURRENT_DISABLE
Definition: gd32f3x0_syscfg.h:82
void syscfg_high_current_enable ( void )

enable PB9 high current capability

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 64 of file gd32f3x0_syscfg.c.

65 {
66 SYSCFG_CFG0 |= SYSCFG_HIGH_CURRENT_ENABLE;
67 }
SYSCFG_CFG0
#define SYSCFG_CFG0
Definition: gd32f3x0_syscfg.h:21
SYSCFG_HIGH_CURRENT_ENABLE
#define SYSCFG_HIGH_CURRENT_ENABLE
Definition: gd32f3x0_syscfg.h:81
void syscfg_lock_config ( uint32_t syscfg_lock )

connect TIMER0/14/15/16 break input to the selected parameter

Parameters
[in] syscfg_lock Specify the parameter to be connected
  • SYSCFG_LOCK_LOCKUP: Cortex-M4 lockup output connected to the break input
  • SYSCFG_LOCK_SRAM_PARITY_ERROR: SRAM_PARITY check error connected to the break input
  • SYSCFG_LOCK_LVD: LVD interrupt connected to the break input
[out] none
Return values
none

Definition at line 133 of file gd32f3x0_syscfg.c.

134 {
135 SYSCFG_CFG2 |= syscfg_lock;
136 }
SYSCFG_CFG2
#define SYSCFG_CFG2
Definition: gd32f3x0_syscfg.h:26
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Data Structures | Macros | Functions
gd32f3x0_timer.h File Reference

definitions for the TIMER More...

#include "gd32f3x0.h"

Go to the source code of this file.

Data Structures

struct | timer_parameter_struct
struct | timer_break_parameter_struct
struct | timer_oc_parameter_struct
struct | timer_ic_parameter_struct

Macros

#define | TIMER0 (TIMER_BASE + 0x00012C00U)
#define | TIMER1 (TIMER_BASE + 0x00000000U)
#define | TIMER2 (TIMER_BASE + 0x00000400U)
#define | TIMER13 (TIMER_BASE + 0x00002000U)
#define | TIMER14 (TIMER_BASE + 0x00014000U)
#define | TIMER15 (TIMER_BASE + 0x00014400U)
#define | TIMER16 (TIMER_BASE + 0x00014800U)
#define | TIMER_CTL0(timerx) REG32((timerx) + 0x00U)
#define | TIMER_CTL1(timerx) REG32((timerx) + 0x04U)
#define | TIMER_SMCFG(timerx) REG32((timerx) + 0x08U)
#define | TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU)
#define | TIMER_INTF(timerx) REG32((timerx) + 0x10U)
#define | TIMER_SWEVG(timerx) REG32((timerx) + 0x14U)
#define | TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U)
#define | TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU)
#define | TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U)
#define | TIMER_CNT(timerx) REG32((timerx) + 0x24U)
#define | TIMER_PSC(timerx) REG32((timerx) + 0x28U)
#define | TIMER_CAR(timerx) REG32((timerx) + 0x2CU)
#define | TIMER_CREP(timerx) REG32((timerx) + 0x30U)
#define | TIMER_CH0CV(timerx) REG32((timerx) + 0x34U)
#define | TIMER_CH1CV(timerx) REG32((timerx) + 0x38U)
#define | TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU)
#define | TIMER_CH3CV(timerx) REG32((timerx) + 0x40U)
#define | TIMER_CCHP(timerx) REG32((timerx) + 0x44U)
#define | TIMER_DMACFG(timerx) REG32((timerx) + 0x48U)
#define | TIMER_DMATB(timerx) REG32((timerx) + 0x4CU)
#define | TIMER_IRMP(timerx) REG32((timerx) + 0x50U)
#define | TIMER_CFG(timerx) REG32((timerx) + 0xFCU)
#define | TIMER_CTL0_CEN BIT(0)
#define | TIMER_CTL0_UPDIS BIT(1)
#define | TIMER_CTL0_UPS BIT(2)
#define | TIMER_CTL0_SPM BIT(3)
#define | TIMER_CTL0_DIR BIT(4)
#define | TIMER_CTL0_CAM BITS(5,6)
#define | TIMER_CTL0_ARSE BIT(7)
#define | TIMER_CTL0_CKDIV BITS(8,9)
#define | TIMER_CTL1_CCSE BIT(0)
#define | TIMER_CTL1_CCUC BIT(2)
#define | TIMER_CTL1_DMAS BIT(3)
#define | TIMER_CTL1_MMC BITS(4,6)
#define | TIMER_CTL1_TI0S BIT(7)
#define | TIMER_CTL1_ISO0 BIT(8)
#define | TIMER_CTL1_ISO0N BIT(9)
#define | TIMER_CTL1_ISO1 BIT(10)
#define | TIMER_CTL1_ISO1N BIT(11)
#define | TIMER_CTL1_ISO2 BIT(12)
#define | TIMER_CTL1_ISO2N BIT(13)
#define | TIMER_CTL1_ISO3 BIT(14)
#define | TIMER_SMCFG_SMC BITS(0,2)
#define | TIMER_SMCFG_OCRC BIT(3)
#define | TIMER_SMCFG_TRGS BITS(4,6)
#define | TIMER_SMCFG_MSM BIT(7)
#define | TIMER_SMCFG_ETFC BITS(8,11)
#define | TIMER_SMCFG_ETPSC BITS(12,13)
#define | TIMER_SMCFG_SMC1 BIT(14)
#define | TIMER_SMCFG_ETP BIT(15)
#define | TIMER_DMAINTEN_UPIE BIT(0)
#define | TIMER_DMAINTEN_CH0IE BIT(1)
#define | TIMER_DMAINTEN_CH1IE BIT(2)
#define | TIMER_DMAINTEN_CH2IE BIT(3)
#define | TIMER_DMAINTEN_CH3IE BIT(4)
#define | TIMER_DMAINTEN_CMTIE BIT(5)
#define | TIMER_DMAINTEN_TRGIE BIT(6)
#define | TIMER_DMAINTEN_BRKIE BIT(7)
#define | TIMER_DMAINTEN_UPDEN BIT(8)
#define | TIMER_DMAINTEN_CH0DEN BIT(9)
#define | TIMER_DMAINTEN_CH1DEN BIT(10)
#define | TIMER_DMAINTEN_CH2DEN BIT(11)
#define | TIMER_DMAINTEN_CH3DEN BIT(12)
#define | TIMER_DMAINTEN_CMTDEN BIT(13)
#define | TIMER_DMAINTEN_TRGDEN BIT(14)
#define | TIMER_INTF_UPIF BIT(0)
#define | TIMER_INTF_CH0IF BIT(1)
#define | TIMER_INTF_CH1IF BIT(2)
#define | TIMER_INTF_CH2IF BIT(3)
#define | TIMER_INTF_CH3IF BIT(4)
#define | TIMER_INTF_CMTIF BIT(5)
#define | TIMER_INTF_TRGIF BIT(6)
#define | TIMER_INTF_BRKIF BIT(7)
#define | TIMER_INTF_CH0OF BIT(9)
#define | TIMER_INTF_CH1OF BIT(10)
#define | TIMER_INTF_CH2OF BIT(11)
#define | TIMER_INTF_CH3OF BIT(12)
#define | TIMER_SWEVG_UPG BIT(0)
#define | TIMER_SWEVG_CH0G BIT(1)
#define | TIMER_SWEVG_CH1G BIT(2)
#define | TIMER_SWEVG_CH2G BIT(3)
#define | TIMER_SWEVG_CH3G BIT(4)
#define | TIMER_SWEVG_CMTG BIT(5)
#define | TIMER_SWEVG_TRGG BIT(6)
#define | TIMER_SWEVG_BRKG BIT(7)
#define | TIMER_CHCTL0_CH0MS BITS(0,1)
#define | TIMER_CHCTL0_CH0COMFEN BIT(2)
#define | TIMER_CHCTL0_CH0COMSEN BIT(3)
#define | TIMER_CHCTL0_CH0COMCTL BITS(4,6)
#define | TIMER_CHCTL0_CH0COMCEN BIT(7)
#define | TIMER_CHCTL0_CH1MS BITS(8,9)
#define | TIMER_CHCTL0_CH1COMFEN BIT(10)
#define | TIMER_CHCTL0_CH1COMSEN BIT(11)
#define | TIMER_CHCTL0_CH1COMCTL BITS(12,14)
#define | TIMER_CHCTL0_CH1COMCEN BIT(15)
#define | TIMER_CHCTL0_CH0CAPPSC BITS(2,3)
#define | TIMER_CHCTL0_CH0CAPFLT BITS(4,7)
#define | TIMER_CHCTL0_CH1CAPPSC BITS(10,11)
#define | TIMER_CHCTL0_CH1CAPFLT BITS(12,15)
#define | TIMER_CHCTL1_CH2MS BITS(0,1)
#define | TIMER_CHCTL1_CH2COMFEN BIT(2)
#define | TIMER_CHCTL1_CH2COMSEN BIT(3)
#define | TIMER_CHCTL1_CH2COMCTL BITS(4,6)
#define | TIMER_CHCTL1_CH2COMCEN BIT(7)
#define | TIMER_CHCTL1_CH3MS BITS(8,9)
#define | TIMER_CHCTL1_CH3COMFEN BIT(10)
#define | TIMER_CHCTL1_CH3COMSEN BIT(11)
#define | TIMER_CHCTL1_CH3COMCTL BITS(12,14)
#define | TIMER_CHCTL1_CH3COMCEN BIT(15)
#define | TIMER_CHCTL1_CH2CAPPSC BITS(2,3)
#define | TIMER_CHCTL1_CH2CAPFLT BITS(4,7)
#define | TIMER_CHCTL1_CH3CAPPSC BITS(10,11)
#define | TIMER_CHCTL1_CH3CAPFLT BITS(12,15)
#define | TIMER_CHCTL2_CH0EN BIT(0)
#define | TIMER_CHCTL2_CH0P BIT(1)
#define | TIMER_CHCTL2_CH0NEN BIT(2)
#define | TIMER_CHCTL2_CH0NP BIT(3)
#define | TIMER_CHCTL2_CH1EN BIT(4)
#define | TIMER_CHCTL2_CH1P BIT(5)
#define | TIMER_CHCTL2_CH1NEN BIT(6)
#define | TIMER_CHCTL2_CH1NP BIT(7)
#define | TIMER_CHCTL2_CH2EN BIT(8)
#define | TIMER_CHCTL2_CH2P BIT(9)
#define | TIMER_CHCTL2_CH2NEN BIT(10)
#define | TIMER_CHCTL2_CH2NP BIT(11)
#define | TIMER_CHCTL2_CH3EN BIT(12)
#define | TIMER_CHCTL2_CH3P BIT(13)
#define | TIMER_CHCTL2_CH3NP BIT(15)
#define | TIMER_CNT_CNT16 BITS(0,15)
#define | TIMER_CNT_CNT32 BITS(0,31)
#define | TIMER_PSC_PSC BITS(0,15)
#define | TIMER_CAR_CARL16 BITS(0,15)
#define | TIMER_CAR_CARL32 BITS(0,31)
#define | TIMER_CREP_CREP BITS(0,7)
#define | TIMER_CH0CV_CH0VAL16 BITS(0,15)
#define | TIMER_CH0CV_CH0VAL32 BITS(0,31)
#define | TIMER_CH1CV_CH1VAL16 BITS(0,15)
#define | TIMER_CH1CV_CH1VAL32 BITS(0,31)
#define | TIMER_CH2CV_CH2VAL16 BITS(0,15)
#define | TIMER_CH2CV_CH2VAL32 BITS(0,31)
#define | TIMER_CH3CV_CH3VAL16 BITS(0,15)
#define | TIMER_CH3CV_CH3VAL32 BITS(0,31)
#define | TIMER_CCHP_DTCFG BITS(0,7)
#define | TIMER_CCHP_PROT BITS(8,9)
#define | TIMER_CCHP_IOS BIT(10)
#define | TIMER_CCHP_ROS BIT(11)
#define | TIMER_CCHP_BRKEN BIT(12)
#define | TIMER_CCHP_BRKP BIT(13)
#define | TIMER_CCHP_OAEN BIT(14)
#define | TIMER_CCHP_POEN BIT(15)
#define | TIMER_DMACFG_DMATA BITS(0,4)
#define | TIMER_DMACFG_DMATC BITS(8,12)
#define | TIMER_DMATB_DMATB BITS(0,15)
#define | TIMER13_IRMP_CI0_RMP BITS(0,1)
#define | TIMER_CFG_OUTSEL BIT(0)
#define | TIMER_CFG_CHVSEL BIT(1)
#define | TIMER_INT_UP TIMER_DMAINTEN_UPIE
#define | TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE
#define | TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE
#define | TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE
#define | TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE
#define | TIMER_INT_CMT TIMER_DMAINTEN_CMTIE
#define | TIMER_INT_TRG TIMER_DMAINTEN_TRGIE
#define | TIMER_INT_BRK TIMER_DMAINTEN_BRKIE
#define | TIMER_FLAG_UP TIMER_INTF_UPIF
#define | TIMER_FLAG_CH0 TIMER_INTF_CH0IF
#define | TIMER_FLAG_CH1 TIMER_INTF_CH1IF
#define | TIMER_FLAG_CH2 TIMER_INTF_CH2IF
#define | TIMER_FLAG_CH3 TIMER_INTF_CH3IF
#define | TIMER_FLAG_CMT TIMER_INTF_CMTIF
#define | TIMER_FLAG_TRG TIMER_INTF_TRGIF
#define | TIMER_FLAG_BRK TIMER_INTF_BRKIF
#define | TIMER_FLAG_CH0O TIMER_INTF_CH0OF
#define | TIMER_FLAG_CH1O TIMER_INTF_CH1OF
#define | TIMER_FLAG_CH2O TIMER_INTF_CH2OF
#define | TIMER_FLAG_CH3O TIMER_INTF_CH3OF
#define | TIMER_INT_FLAG_UP TIMER_INTF_UPIF
#define | TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF
#define | TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF
#define | TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF
#define | TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF
#define | TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF
#define | TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF
#define | TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF
#define | TIMER_DMA_UPD ((uint16_t)0x0100U)
#define | TIMER_DMA_CH0D ((uint16_t)0x0200U)
#define | TIMER_DMA_CH1D ((uint16_t)0x0400U)
#define | TIMER_DMA_CH2D ((uint16_t)0x0800U)
#define | TIMER_DMA_CH3D ((uint16_t)0x1000U)
#define | TIMER_DMA_CMTD ((uint16_t)0x2000U)
#define | TIMER_DMA_TRGD ((uint16_t)0x4000U)
#define | TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U)
#define | TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U)
#define | DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U))
#define | TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0)
#define | TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1)
#define | TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2)
#define | TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3)
#define | TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4)
#define | TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5)
#define | TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6)
#define | TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7)
#define | TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8)
#define | TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9)
#define | TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10)
#define | TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11)
#define | TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12)
#define | TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13)
#define | TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14)
#define | TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15)
#define | TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16)
#define | TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17)
#define | TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18)
#define | TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19)
#define | DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U))
#define | TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0)
#define | TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1)
#define | TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2)
#define | TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3)
#define | TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4)
#define | TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5)
#define | TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6)
#define | TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7)
#define | TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8)
#define | TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9)
#define | TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10)
#define | TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11)
#define | TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12)
#define | TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13)
#define | TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14)
#define | TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15)
#define | TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16)
#define | TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17)
#define | TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U)
#define | TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U)
#define | TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U)
#define | TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U)
#define | TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U)
#define | TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U)
#define | TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U)
#define | TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U)
#define | CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))
#define | TIMER_COUNTER_EDGE CTL0_CAM(0)
#define | TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1)
#define | TIMER_COUNTER_CENTER_UP CTL0_CAM(2)
#define | TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3)
#define | TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U)
#define | TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U)
#define | TIMER_COUNTER_UP ((uint16_t)0x0000U)
#define | TIMER_COUNTER_DOWN ((uint16_t)0x0010U)
#define | CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
#define | TIMER_CKDIV_DIV1 CTL0_CKDIV(0)
#define | TIMER_CKDIV_DIV2 CTL0_CKDIV(1)
#define | TIMER_CKDIV_DIV4 CTL0_CKDIV(2)
#define | TIMER_SP_MODE_SINGLE ((uint8_t)0x00U)
#define | TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U)
#define | TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U)
#define | TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U)
#define | TIMER_ROS_STATE_ENABLE ((uint32_t)0x00000800U)
#define | TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U)
#define | TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U)
#define | TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U)
#define | TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U)
#define | TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U)
#define | TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U)
#define | TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U)
#define | CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
#define | TIMER_CCHP_PROT_OFF CCHP_PROT(0)
#define | TIMER_CCHP_PROT_0 CCHP_PROT(1)
#define | TIMER_CCHP_PROT_1 CCHP_PROT(2)
#define | TIMER_CCHP_PROT_2 CCHP_PROT(3)
#define | TIMER_BREAK_ENABLE ((uint16_t)0x1000U)
#define | TIMER_BREAK_DISABLE ((uint16_t)0x0000U)
#define | TIMER_CH_0 ((uint16_t)0x0000U)
#define | TIMER_CH_1 ((uint16_t)0x0001U)
#define | TIMER_CH_2 ((uint16_t)0x0002U)
#define | TIMER_CH_3 ((uint16_t)0x0003U)
#define | TIMER_CCX_ENABLE ((uint32_t)0x00000001U)
#define | TIMER_CCX_DISABLE ((uint32_t)0x00000000U)
#define | TIMER_CCXN_ENABLE ((uint16_t)0x0004U)
#define | TIMER_CCXN_DISABLE ((uint16_t)0x0000U)
#define | TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U)
#define | TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U)
#define | TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U)
#define | TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U)
#define | TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100)
#define | TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000)
#define | TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U)
#define | TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U)
#define | TIMER_OC_MODE_TIMING ((uint16_t)0x0000U)
#define | TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U)
#define | TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U)
#define | TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U)
#define | TIMER_OC_MODE_LOW ((uint16_t)0x0040U)
#define | TIMER_OC_MODE_HIGH ((uint16_t)0x0050U)
#define | TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U)
#define | TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U)
#define | TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U)
#define | TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U)
#define | TIMER_OC_FAST_ENABLE ((uint16_t)0x0004)
#define | TIMER_OC_FAST_DISABLE ((uint16_t)0x0000)
#define | TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U)
#define | TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U)
#define | TIMER_UPDATECTL_CCU ((uint8_t)0x00U)
#define | TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U)
#define | TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U)
#define | TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U)
#define | TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU)
#define | TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U)
#define | TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U)
#define | TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U)
#define | TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U)
#define | TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U)
#define | TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U)
#define | TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU)
#define | SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
#define | TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0)
#define | TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1)
#define | TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2)
#define | TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3)
#define | TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4)
#define | TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5)
#define | TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6)
#define | TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7)
#define | CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
#define | TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0)
#define | TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1)
#define | TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2)
#define | TIMER_TRI_OUT_SRC_CC0 CTL1_MMC(3)
#define | TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4)
#define | TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5)
#define | TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6)
#define | TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7)
#define | SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U))
#define | TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0)
#define | TIMER_ENCODER_MODE0 SMCFG_SMC(1)
#define | TIMER_ENCODER_MODE1 SMCFG_SMC(2)
#define | TIMER_ENCODER_MODE2 SMCFG_SMC(3)
#define | TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4)
#define | TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5)
#define | TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6)
#define | TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7)
#define | TIMER_OCPRE_CLEAR_SOURCE_CLR ((uint8_t)0x00U)
#define | TIMER_OCPRE_CLEAR_SOURCE_ETIF ((uint8_t)0x01U)
#define | TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U)
#define | TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U)
#define | SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U))
#define | TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0)
#define | TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1)
#define | TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2)
#define | TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3)
#define | TIMER_ETP_FALLING TIMER_SMCFG_ETP
#define | TIMER_ETP_RISING ((uint32_t)0x00000000U)
#define | TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U)
#define | TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U)
#define | TIMER_CCSEL_DISABLE ((uint16_t)0x0000U)
#define | TIMER_CCSEL_ENABLE ((uint16_t)0x0002U)
#define | TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U)
#define | TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U)
#define | TIMER13_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U))
#define | TIMER13_CI0_RMP_GPIO TIMER13_IRMP(0)
#define | TIMER13_CI0_RMP_RTCCLK TIMER13_IRMP(1)
#define | TIMER13_CI0_RMP_HXTAL_DIV32 TIMER13_IRMP(2)
#define | TIMER13_CI0_RMP_CKOUTSEL TIMER13_IRMP(3)

Functions

void | timer_deinit (uint32_t timer_periph)
deinit a TIMER More...
void | timer_init (uint32_t timer_periph, timer_parameter_struct *initpara)
initialize TIMER counter More...
void | timer_enable (uint32_t timer_periph)
enable a TIMER More...
void | timer_disable (uint32_t timer_periph)
disable a TIMER More...
void | timer_auto_reload_shadow_enable (uint32_t timer_periph)
enable the auto reload shadow function More...
void | timer_auto_reload_shadow_disable (uint32_t timer_periph)
disable the auto reload shadow function More...
void | timer_update_event_enable (uint32_t timer_periph)
enable the update event More...
void | timer_update_event_disable (uint32_t timer_periph)
disable the update event More...
void | timer_counter_alignment (uint32_t timer_periph, uint16_t aligned)
set TIMER counter alignment mode More...
void | timer_counter_up_direction (uint32_t timer_periph)
set TIMER counter up direction More...
void | timer_counter_down_direction (uint32_t timer_periph)
set TIMER counter down direction More...
void | timer_prescaler_config (uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
configure TIMER prescaler More...
void | timer_repetition_value_config (uint32_t timer_periph, uint16_t repetition)
configure TIMER repetition register value More...
void | timer_autoreload_value_config (uint32_t timer_periph, uint32_t autoreload)
configure TIMER autoreload register value More...
void | timer_counter_value_config (uint32_t timer_periph, uint32_t counter)
configure TIMER counter register value More...
uint32_t | timer_counter_read (uint32_t timer_periph)
read TIMER counter value More...
uint16_t | timer_prescaler_read (uint32_t timer_periph)
read TIMER prescaler value More...
void | timer_single_pulse_mode_config (uint32_t timer_periph, uint8_t spmode)
configure TIMER single pulse mode More...
void | timer_update_source_config (uint32_t timer_periph, uint8_t update)
configure TIMER update source More...
void | timer_ocpre_clear_source_config (uint32_t timer_periph, uint8_t ocpreclear)
configure TIMER OCPRE clear source selection More...
void | timer_interrupt_enable (uint32_t timer_periph, uint32_t interrupt)
enable the TIMER interrupt More...
void | timer_interrupt_disable (uint32_t timer_periph, uint32_t interrupt)
disable the TIMER interrupt More...
FlagStatus | timer_interrupt_flag_get (uint32_t timer_periph, uint32_t interrupt)
get timer interrupt flag More...
void | timer_interrupt_flag_clear (uint32_t timer_periph, uint32_t interrupt)
clear TIMER interrupt flag More...
FlagStatus | timer_flag_get (uint32_t timer_periph, uint32_t flag)
get TIMER flags More...
void | timer_flag_clear (uint32_t timer_periph, uint32_t flag)
clear TIMER flags More...
void | timer_dma_enable (uint32_t timer_periph, uint16_t dma)
enable the TIMER DMA More...
void | timer_dma_disable (uint32_t timer_periph, uint16_t dma)
disable the TIMER DMA More...
void | timer_channel_dma_request_source_select (uint32_t timer_periph, uint8_t dma_request)
channel DMA request source selection More...
void | timer_dma_transfer_config (uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
configure the TIMER DMA transfer More...
void | timer_event_software_generate (uint32_t timer_periph, uint16_t event)
software generate events More...
void | timer_break_config (uint32_t timer_periph, timer_break_parameter_struct *breakpara)
configure TIMER break function More...
void | timer_break_enable (uint32_t timer_periph)
enable TIMER break function More...
void | timer_break_disable (uint32_t timer_periph)
disable TIMER break function More...
void | timer_automatic_output_enable (uint32_t timer_periph)
enable TIMER output automatic function More...
void | timer_automatic_output_disable (uint32_t timer_periph)
disable TIMER output automatic function More...
void | timer_primary_output_config (uint32_t timer_periph, ControlStatus newvalue)
configure TIMER primary output function More...
void | timer_channel_control_shadow_config (uint32_t timer_periph, ControlStatus newvalue)
channel capture/compare control shadow register enable More...
void | timer_channel_control_shadow_update_config (uint32_t timer_periph, uint8_t ccuctl)
configure TIMER channel control shadow register update control More...
void | timer_channel_output_config (uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara)
configure TIMER channel output function More...
void | timer_channel_output_mode_config (uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
configure TIMER channel output compare mode More...
void | timer_channel_output_pulse_value_config (uint32_t timer_periph, uint16_t channel, uint32_t pulse)
configure TIMER channel output pulse value More...
void | timer_channel_output_shadow_config (uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
configure TIMER channel output shadow function More...
void | timer_channel_output_fast_config (uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
configure TIMER channel output fast function More...
void | timer_channel_output_clear_config (uint32_t timer_periph, uint16_t channel, uint16_t occlear)
configure TIMER channel output clear function More...
void | timer_channel_output_polarity_config (uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
configure TIMER channel output polarity More...
void | timer_channel_complementary_output_polarity_config (uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
configure TIMER channel complementary output polarity More...
void | timer_channel_output_state_config (uint32_t timer_periph, uint16_t channel, uint32_t state)
configure TIMER channel enable state More...
void | timer_channel_complementary_output_state_config (uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
configure TIMER channel complementary output enable state More...
void | timer_input_capture_config (uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara)
configure TIMER input capture parameter More...
void | timer_channel_input_capture_prescaler_config (uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value More...
uint32_t | timer_channel_capture_value_register_read (uint32_t timer_periph, uint16_t channel)
read TIMER channel capture compare register value More...
void | timer_input_pwm_capture_config (uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm)
configure TIMER input pwm capture function More...
void | timer_hall_mode_config (uint32_t timer_periph, uint8_t hallmode)
configure TIMER hall sensor mode More...
void | timer_input_trigger_source_select (uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source More...
void | timer_master_output_trigger_source_select (uint32_t timer_periph, uint32_t outrigger)
select TIMER master mode output trigger source More...
void | timer_slave_mode_select (uint32_t timer_periph, uint32_t slavemode)
select TIMER slave mode More...
void | timer_master_slave_mode_config (uint32_t timer_periph, uint8_t masterslave)
configure TIMER master slave mode More...
void | timer_external_trigger_config (uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input More...
void | timer_quadrature_decoder_mode_config (uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
configure TIMER quadrature decoder mode More...
void | timer_internal_clock_config (uint32_t timer_periph)
configure TIMER internal clock mode More...
void | timer_internal_trigger_as_external_clock_config (uint32_t timer_periph, uint32_t intrigger)
configure TIMER the internal trigger as external clock input More...
void | timer_external_trigger_as_external_clock_config (uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter)
configure TIMER the external trigger as external clock input More...
void | timer_external_clock_mode0_config (uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode0 More...
void | timer_external_clock_mode1_config (uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode1 More...
void | timer_external_clock_mode1_disable (uint32_t timer_periph)
disable TIMER the external clock mode1 More...
void | timer_channel_remap_config (uint32_t timer_periph, uint32_t remap)
configure TIMER channel remap function More...
void | timer_write_cc_register_config (uint32_t timer_periph, uint16_t ccsel)
configure TIMER write CHxVAL register selection More...
void | timer_output_value_selection_config (uint32_t timer_periph, uint16_t outsel)
configure TIMER output value selection More...

Detailed Description

definitions for the TIMER

Definition in file gd32f3x0_timer.h.

Macro Definition Documentation

#define CCHP_PROT ( regval ) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))

Definition at line 427 of file gd32f3x0_timer.h.

#define CTL0_CAM ( regval ) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))

Definition at line 382 of file gd32f3x0_timer.h.

#define CTL0_CKDIV ( regval ) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))

Definition at line 397 of file gd32f3x0_timer.h.

#define CTL1_MMC ( regval ) (BITS(4, 6) & ((uint32_t)(regval) << 4U))

Definition at line 521 of file gd32f3x0_timer.h.

#define DMACFG_DMATA ( regval ) (BITS(0, 4) & ((uint32_t)(regval) << 0U))

Definition at line 328 of file gd32f3x0_timer.h.

#define DMACFG_DMATC ( regval ) (BITS(8, 12) & ((uint32_t)(regval) << 8U))

Definition at line 351 of file gd32f3x0_timer.h.

#define SMCFG_ETPSC ( regval ) (BITS(12, 13) & ((uint32_t)(regval) << 12U))

Definition at line 551 of file gd32f3x0_timer.h.

#define SMCFG_SMC ( regval ) (BITS(0, 2) & ((uint32_t)(regval) << 0U))

Definition at line 532 of file gd32f3x0_timer.h.

#define SMCFG_TRGSEL ( regval ) (BITS(4, 6) & ((uint32_t)(regval) << 4U))

Definition at line 510 of file gd32f3x0_timer.h.

#define TIMER0 (TIMER_BASE + 0x00012C00U)

Definition at line 18 of file gd32f3x0_timer.h.

#define TIMER1 (TIMER_BASE + 0x00000000U)

Definition at line 19 of file gd32f3x0_timer.h.

#define TIMER13 (TIMER_BASE + 0x00002000U)

Definition at line 24 of file gd32f3x0_timer.h.

#define TIMER13_CI0_RMP_CKOUTSEL TIMER13_IRMP(3)

timer13 channel 0 input is connected to CKOUTSEL

Definition at line 578 of file gd32f3x0_timer.h.

#define TIMER13_CI0_RMP_GPIO TIMER13_IRMP(0)

timer13 channel 0 input is connected to GPIO(TIMER13_CH0)

Definition at line 575 of file gd32f3x0_timer.h.

#define TIMER13_CI0_RMP_HXTAL_DIV32 TIMER13_IRMP(2)

timer13 channel 0 input is connected to HXTAL/32 clock

Definition at line 577 of file gd32f3x0_timer.h.

#define TIMER13_CI0_RMP_RTCCLK TIMER13_IRMP(1)

timer13 channel 0 input is connected to the RTCCLK

Definition at line 576 of file gd32f3x0_timer.h.

#define TIMER13_IRMP ( regval ) (BITS(0, 1) & ((uint32_t)(regval) << 0U))

Definition at line 574 of file gd32f3x0_timer.h.

#define TIMER13_IRMP_CI0_RMP BITS(0,1)

TIMER13 channel 0 input remap

Definition at line 230 of file gd32f3x0_timer.h.

#define TIMER14 (TIMER_BASE + 0x00014000U)

Definition at line 25 of file gd32f3x0_timer.h.

#define TIMER15 (TIMER_BASE + 0x00014400U)

Definition at line 26 of file gd32f3x0_timer.h.

#define TIMER16 (TIMER_BASE + 0x00014800U)

Definition at line 27 of file gd32f3x0_timer.h.

#define TIMER2 (TIMER_BASE + 0x00000400U)

Definition at line 20 of file gd32f3x0_timer.h.

#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U)

break input disable

Definition at line 435 of file gd32f3x0_timer.h.

#define TIMER_BREAK_ENABLE ((uint16_t)0x1000U)

break input enable

Definition at line 434 of file gd32f3x0_timer.h.

#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U)

break input polarity is high

Definition at line 420 of file gd32f3x0_timer.h.

#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U)

break input polarity is low

Definition at line 419 of file gd32f3x0_timer.h.

#define TIMER_CAR ( timerx ) REG32((timerx) + 0x2CU)

TIMER counter auto reload register

Definition at line 41 of file gd32f3x0_timer.h.

#define TIMER_CAR_CARL16 BITS(0,15)

16 bit counter auto reload value

Definition at line 190 of file gd32f3x0_timer.h.

#define TIMER_CAR_CARL32 BITS(0,31)

32 bit(TIMER1) counter auto reload value

Definition at line 191 of file gd32f3x0_timer.h.

#define TIMER_CCHP ( timerx ) REG32((timerx) + 0x44U)

TIMER complementary channel protection register

Definition at line 47 of file gd32f3x0_timer.h.

#define TIMER_CCHP_BRKEN BIT(12)

break enable

Definition at line 217 of file gd32f3x0_timer.h.

#define TIMER_CCHP_BRKP BIT(13)

break polarity

Definition at line 218 of file gd32f3x0_timer.h.

#define TIMER_CCHP_DTCFG BITS(0,7)

dead time configure

Definition at line 213 of file gd32f3x0_timer.h.

#define TIMER_CCHP_IOS BIT(10)

idle mode off-state configure

Definition at line 215 of file gd32f3x0_timer.h.

#define TIMER_CCHP_OAEN BIT(14)

output automatic enable

Definition at line 219 of file gd32f3x0_timer.h.

#define TIMER_CCHP_POEN BIT(15)

primary output enable

Definition at line 220 of file gd32f3x0_timer.h.

#define TIMER_CCHP_PROT BITS(8,9)

complementary register protect control

Definition at line 214 of file gd32f3x0_timer.h.

#define TIMER_CCHP_PROT_0 CCHP_PROT(1)

PROT mode 0

Definition at line 429 of file gd32f3x0_timer.h.

#define TIMER_CCHP_PROT_1 CCHP_PROT(2)

PROT mode 1

Definition at line 430 of file gd32f3x0_timer.h.

#define TIMER_CCHP_PROT_2 CCHP_PROT(3)

PROT mode 2

Definition at line 431 of file gd32f3x0_timer.h.

#define TIMER_CCHP_PROT_OFF CCHP_PROT(0)

protect disable

Definition at line 428 of file gd32f3x0_timer.h.

#define TIMER_CCHP_ROS BIT(11)

run mode off-state configure

Definition at line 216 of file gd32f3x0_timer.h.

#define TIMER_CCSEL_DISABLE ((uint16_t)0x0000U)

write CC register selection disable

Definition at line 566 of file gd32f3x0_timer.h.

#define TIMER_CCSEL_ENABLE ((uint16_t)0x0002U)

write CC register selection enable

Definition at line 567 of file gd32f3x0_timer.h.

#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U)

channel disable

Definition at line 445 of file gd32f3x0_timer.h.

#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U)

channel enable

Definition at line 444 of file gd32f3x0_timer.h.

#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U)

channel complementary disable

Definition at line 449 of file gd32f3x0_timer.h.

#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U)

channel complementary enable

Definition at line 448 of file gd32f3x0_timer.h.

#define TIMER_CFG ( timerx ) REG32((timerx) + 0xFCU)

TIMER configuration register

Definition at line 51 of file gd32f3x0_timer.h.

#define TIMER_CFG_CHVSEL BIT(1)

write CHxVAL register selection

Definition at line 234 of file gd32f3x0_timer.h.

#define TIMER_CFG_OUTSEL BIT(0)

the output value selection

Definition at line 233 of file gd32f3x0_timer.h.

#define TIMER_CH0CV ( timerx ) REG32((timerx) + 0x34U)

TIMER channel 0 capture/compare value register

Definition at line 43 of file gd32f3x0_timer.h.

#define TIMER_CH0CV_CH0VAL16 BITS(0,15)

16 bit capture/compare value of channel 0

Definition at line 197 of file gd32f3x0_timer.h.

#define TIMER_CH0CV_CH0VAL32 BITS(0,31)

32 bit(TIMER1) capture/compare value of channel 0

Definition at line 198 of file gd32f3x0_timer.h.

#define TIMER_CH1CV ( timerx ) REG32((timerx) + 0x38U)

TIMER channel 1 capture/compare value register

Definition at line 44 of file gd32f3x0_timer.h.

#define TIMER_CH1CV_CH1VAL16 BITS(0,15)

16 bit capture/compare value of channel 1

Definition at line 201 of file gd32f3x0_timer.h.

#define TIMER_CH1CV_CH1VAL32 BITS(0,31)

32 bit(TIMER1) capture/compare value of channel 1

Definition at line 202 of file gd32f3x0_timer.h.

#define TIMER_CH2CV ( timerx ) REG32((timerx) + 0x3CU)

TIMER channel 2 capture/compare value register

Definition at line 45 of file gd32f3x0_timer.h.

#define TIMER_CH2CV_CH2VAL16 BITS(0,15)

16 bit capture/compare value of channel 2

Definition at line 205 of file gd32f3x0_timer.h.

#define TIMER_CH2CV_CH2VAL32 BITS(0,31)

32 bit(TIMER1) capture/compare value of channel 2

Definition at line 206 of file gd32f3x0_timer.h.

#define TIMER_CH3CV ( timerx ) REG32((timerx) + 0x40U)

TIMER channel 3 capture/compare value register

Definition at line 46 of file gd32f3x0_timer.h.

#define TIMER_CH3CV_CH3VAL16 BITS(0,15)

16 bit capture/compare value of channel 3

Definition at line 209 of file gd32f3x0_timer.h.

#define TIMER_CH3CV_CH3VAL32 BITS(0,31)

32 bit(TIMER1) capture/compare value of channel 3

Definition at line 210 of file gd32f3x0_timer.h.

#define TIMER_CH_0 ((uint16_t)0x0000U)

TIMER channel 0(TIMERx(x=0..2,13..16))

Definition at line 438 of file gd32f3x0_timer.h.

#define TIMER_CH_1 ((uint16_t)0x0001U)

TIMER channel 1(TIMERx(x=0..2,14))

Definition at line 439 of file gd32f3x0_timer.h.

#define TIMER_CH_2 ((uint16_t)0x0002U)

TIMER channel 2(TIMERx(x=0..2))

Definition at line 440 of file gd32f3x0_timer.h.

#define TIMER_CH_3 ((uint16_t)0x0003U)

TIMER channel 3(TIMERx(x=0..2))

Definition at line 441 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0 ( timerx ) REG32((timerx) + 0x18U)

TIMER channel control register 0

Definition at line 36 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7)

channel 0 input capture filter control

Definition at line 143 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3)

channel 0 input capture prescaler

Definition at line 142 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0_CH0COMCEN BIT(7)

channel 0 output compare clear enable

Definition at line 135 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0_CH0COMCTL BITS(4,6)

channel 0 output compare mode

Definition at line 134 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0_CH0COMFEN BIT(2)

channel 0 output compare fast enable

Definition at line 132 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0_CH0COMSEN BIT(3)

channel 0 output compare shadow enable

Definition at line 133 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0_CH0MS BITS(0,1)

channel 0 mode selection

Definition at line 131 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15)

channel 1 input capture filter control

Definition at line 145 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11)

channel 1 input capture prescaler

Definition at line 144 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0_CH1COMCEN BIT(15)

channel 1 output compare clear enable

Definition at line 140 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0_CH1COMCTL BITS(12,14)

channel 1 output compare mode

Definition at line 139 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0_CH1COMFEN BIT(10)

channel 1 output compare fast enable

Definition at line 137 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0_CH1COMSEN BIT(11)

channel 1 output compare shadow enable

Definition at line 138 of file gd32f3x0_timer.h.

#define TIMER_CHCTL0_CH1MS BITS(8,9)

channel 1 mode selection

Definition at line 136 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1 ( timerx ) REG32((timerx) + 0x1CU)

TIMER channel control register 1

Definition at line 37 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7)

channel 2 input capture filter control

Definition at line 161 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3)

channel 2 input capture prescaler

Definition at line 160 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1_CH2COMCEN BIT(7)

channel 2 output compare clear enable

Definition at line 153 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1_CH2COMCTL BITS(4,6)

channel 2 output compare mode

Definition at line 152 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1_CH2COMFEN BIT(2)

channel 2 output compare fast enable

Definition at line 150 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1_CH2COMSEN BIT(3)

channel 2 output compare shadow enable

Definition at line 151 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1_CH2MS BITS(0,1)

channel 2 mode selection

Definition at line 149 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15)

channel 3 input capture filter control

Definition at line 163 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11)

channel 3 input capture prescaler

Definition at line 162 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1_CH3COMCEN BIT(15)

channel 3 output compare clear enable

Definition at line 158 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1_CH3COMCTL BITS(12,14)

channel 3 output compare mode

Definition at line 157 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1_CH3COMFEN BIT(10)

channel 3 output compare fast enable

Definition at line 155 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1_CH3COMSEN BIT(11)

channel 3 output compare shadow enable

Definition at line 156 of file gd32f3x0_timer.h.

#define TIMER_CHCTL1_CH3MS BITS(8,9)

channel 3 mode selection

Definition at line 154 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2 ( timerx ) REG32((timerx) + 0x20U)

TIMER channel control register 2

Definition at line 38 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH0EN BIT(0)

channel 0 enable

Definition at line 166 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH0NEN BIT(2)

channel 0 complementary output enable

Definition at line 168 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH0NP BIT(3)

channel 0 complementary output polarity

Definition at line 169 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH0P BIT(1)

channel 0 polarity

Definition at line 167 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH1EN BIT(4)

channel 1 enable

Definition at line 170 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH1NEN BIT(6)

channel 1 complementary output enable

Definition at line 172 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH1NP BIT(7)

channel 1 complementary output polarity

Definition at line 173 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH1P BIT(5)

channel 1 polarity

Definition at line 171 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH2EN BIT(8)

channel 2 enable

Definition at line 174 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH2NEN BIT(10)

channel 2 complementary output enable

Definition at line 176 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH2NP BIT(11)

channel 2 complementary output polarity

Definition at line 177 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH2P BIT(9)

channel 2 polarity

Definition at line 175 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH3EN BIT(12)

channel 3 enable

Definition at line 178 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH3NP BIT(15)

channel 3 complementary output polarity

Definition at line 180 of file gd32f3x0_timer.h.

#define TIMER_CHCTL2_CH3P BIT(13)

channel 3 polarity

Definition at line 179 of file gd32f3x0_timer.h.

#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0)

clock division value is 1, fDTS=fTIMER_CK

Definition at line 398 of file gd32f3x0_timer.h.

#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1)

clock division value is 2, fDTS= fTIMER_CK/2

Definition at line 399 of file gd32f3x0_timer.h.

#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2)

clock division value is 4, fDTS= fTIMER_CK/4

Definition at line 400 of file gd32f3x0_timer.h.

#define TIMER_CNT ( timerx ) REG32((timerx) + 0x24U)

TIMER counter register

Definition at line 39 of file gd32f3x0_timer.h.

#define TIMER_CNT_CNT16 BITS(0,15)

16 bit timer counter

Definition at line 183 of file gd32f3x0_timer.h.

#define TIMER_CNT_CNT32 BITS(0,31)

32 bit(TIMER1) timer counter

Definition at line 184 of file gd32f3x0_timer.h.

#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3)

center-aligned and counting up/down assert mode

Definition at line 386 of file gd32f3x0_timer.h.

#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1)

center-aligned and counting down assert mode

Definition at line 384 of file gd32f3x0_timer.h.

#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2)

center-aligned and counting up assert mode

Definition at line 385 of file gd32f3x0_timer.h.

#define TIMER_COUNTER_DOWN ((uint16_t)0x0010U)

counter down direction

Definition at line 394 of file gd32f3x0_timer.h.

#define TIMER_COUNTER_EDGE CTL0_CAM(0)

edge-aligned mode

Definition at line 383 of file gd32f3x0_timer.h.

#define TIMER_COUNTER_UP ((uint16_t)0x0000U)

counter up direction

Definition at line 393 of file gd32f3x0_timer.h.

#define TIMER_CREP ( timerx ) REG32((timerx) + 0x30U)

TIMER counter repetition register

Definition at line 42 of file gd32f3x0_timer.h.

#define TIMER_CREP_CREP BITS(0,7)

counter repetition value

Definition at line 194 of file gd32f3x0_timer.h.

#define TIMER_CTL0 ( timerx ) REG32((timerx) + 0x00U)

TIMER control register 0

Definition at line 30 of file gd32f3x0_timer.h.

#define TIMER_CTL0_ARSE BIT(7)

auto-reload shadow enable

Definition at line 61 of file gd32f3x0_timer.h.

#define TIMER_CTL0_CAM BITS(5,6)

center-aligned mode selection

Definition at line 60 of file gd32f3x0_timer.h.

#define TIMER_CTL0_CEN BIT(0)

TIMER counter enable

Definition at line 55 of file gd32f3x0_timer.h.

#define TIMER_CTL0_CKDIV BITS(8,9)

clock division

Definition at line 62 of file gd32f3x0_timer.h.

#define TIMER_CTL0_DIR BIT(4)

timer counter direction

Definition at line 59 of file gd32f3x0_timer.h.

#define TIMER_CTL0_SPM BIT(3)

single pulse mode

Definition at line 58 of file gd32f3x0_timer.h.

#define TIMER_CTL0_UPDIS BIT(1)

update disable

Definition at line 56 of file gd32f3x0_timer.h.

#define TIMER_CTL0_UPS BIT(2)

update source

Definition at line 57 of file gd32f3x0_timer.h.

#define TIMER_CTL1 ( timerx ) REG32((timerx) + 0x04U)

TIMER control register 1

Definition at line 31 of file gd32f3x0_timer.h.

#define TIMER_CTL1_CCSE BIT(0)

commutation control shadow enable

Definition at line 65 of file gd32f3x0_timer.h.

#define TIMER_CTL1_CCUC BIT(2)

commutation control shadow register update control

Definition at line 66 of file gd32f3x0_timer.h.

#define TIMER_CTL1_DMAS BIT(3)

DMA request source selection

Definition at line 67 of file gd32f3x0_timer.h.

#define TIMER_CTL1_ISO0 BIT(8)

idle state of channel 0 output

Definition at line 70 of file gd32f3x0_timer.h.

#define TIMER_CTL1_ISO0N BIT(9)

idle state of channel 0 complementary output

Definition at line 71 of file gd32f3x0_timer.h.

#define TIMER_CTL1_ISO1 BIT(10)

idle state of channel 1 output

Definition at line 72 of file gd32f3x0_timer.h.

#define TIMER_CTL1_ISO1N BIT(11)

idle state of channel 1 complementary output

Definition at line 73 of file gd32f3x0_timer.h.

#define TIMER_CTL1_ISO2 BIT(12)

idle state of channel 2 output

Definition at line 74 of file gd32f3x0_timer.h.

#define TIMER_CTL1_ISO2N BIT(13)

idle state of channel 2 complementary output

Definition at line 75 of file gd32f3x0_timer.h.

#define TIMER_CTL1_ISO3 BIT(14)

idle state of channel 3 output

Definition at line 76 of file gd32f3x0_timer.h.

#define TIMER_CTL1_MMC BITS(4,6)

master mode control

Definition at line 68 of file gd32f3x0_timer.h.

#define TIMER_CTL1_TI0S BIT(7)

channel 0 trigger input selection(hall mode selection)

Definition at line 69 of file gd32f3x0_timer.h.

#define TIMER_DMA_CH0D ((uint16_t)0x0200U)

channel 0 DMA enable

Definition at line 316 of file gd32f3x0_timer.h.

#define TIMER_DMA_CH1D ((uint16_t)0x0400U)

channel 1 DMA enable

Definition at line 317 of file gd32f3x0_timer.h.

#define TIMER_DMA_CH2D ((uint16_t)0x0800U)

channel 2 DMA enable

Definition at line 318 of file gd32f3x0_timer.h.

#define TIMER_DMA_CH3D ((uint16_t)0x1000U)

channel 3 DMA enable

Definition at line 319 of file gd32f3x0_timer.h.

#define TIMER_DMA_CMTD ((uint16_t)0x2000U)

commutation DMA request enable

Definition at line 320 of file gd32f3x0_timer.h.

#define TIMER_DMA_TRGD ((uint16_t)0x4000U)

trigger DMA enable

Definition at line 321 of file gd32f3x0_timer.h.

#define TIMER_DMA_UPD ((uint16_t)0x0100U)

update DMA enable

Definition at line 315 of file gd32f3x0_timer.h.

#define TIMER_DMACFG ( timerx ) REG32((timerx) + 0x48U)

TIMER DMA configuration register

Definition at line 48 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA BITS(0,4)

DMA transfer access start address

Definition at line 223 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11)

DMA transfer address is TIMER_CAR

Definition at line 340 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17)

DMA transfer address is TIMER_CCHP

Definition at line 346 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13)

DMA transfer address is TIMER_CH0CV

Definition at line 342 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14)

DMA transfer address is TIMER_CH1CV

Definition at line 343 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15)

DMA transfer address is TIMER_CH2CV

Definition at line 344 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16)

DMA transfer address is TIMER_CH3CV

Definition at line 345 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6)

DMA transfer address is TIMER_CHCTL0

Definition at line 335 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7)

DMA transfer address is TIMER_CHCTL1

Definition at line 336 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8)

DMA transfer address is TIMER_CHCTL2

Definition at line 337 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9)

DMA transfer address is TIMER_CNT

Definition at line 338 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12)

DMA transfer address is TIMER_CREP

Definition at line 341 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0)

DMA transfer address is TIMER_CTL0

Definition at line 329 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1)

DMA transfer address is TIMER_CTL1

Definition at line 330 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18)

DMA transfer address is TIMER_DMACFG

Definition at line 347 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3)

DMA transfer address is TIMER_DMAINTEN

Definition at line 332 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19)

DMA transfer address is TIMER_DMATB

Definition at line 348 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4)

DMA transfer address is TIMER_INTF

Definition at line 333 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10)

DMA transfer address is TIMER_PSC

Definition at line 339 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2)

DMA transfer address is TIMER_SMCFG

Definition at line 331 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5)

DMA transfer address is TIMER_SWEVG

Definition at line 334 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC BITS(8,12)

DMA transfer count

Definition at line 224 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9)

DMA transfer 10 times

Definition at line 361 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10)

DMA transfer 11 times

Definition at line 362 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11)

DMA transfer 12 times

Definition at line 363 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12)

DMA transfer 13 times

Definition at line 364 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13)

DMA transfer 14 times

Definition at line 365 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14)

DMA transfer 15 times

Definition at line 366 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15)

DMA transfer 16 times

Definition at line 367 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16)

DMA transfer 17 times

Definition at line 368 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17)

DMA transfer 18 times

Definition at line 369 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0)

DMA transfer 1 time

Definition at line 352 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1)

DMA transfer 2 times

Definition at line 353 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2)

DMA transfer 3 times

Definition at line 354 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3)

DMA transfer 4 times

Definition at line 355 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4)

DMA transfer 5 times

Definition at line 356 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5)

DMA transfer 6 times

Definition at line 357 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6)

DMA transfer 7 times

Definition at line 358 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7)

DMA transfer 8 times

Definition at line 359 of file gd32f3x0_timer.h.

#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8)

DMA transfer 9 times

Definition at line 360 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN ( timerx ) REG32((timerx) + 0x0CU)

TIMER DMA and interrupt enable register

Definition at line 33 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_BRKIE BIT(7)

break interrupt enable

Definition at line 96 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_CH0DEN BIT(9)

channel 0 DMA request enable

Definition at line 98 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_CH0IE BIT(1)

channel 0 interrupt enable

Definition at line 90 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_CH1DEN BIT(10)

channel 1 DMA request enable

Definition at line 99 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_CH1IE BIT(2)

channel 1 interrupt enable

Definition at line 91 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_CH2DEN BIT(11)

channel 2 DMA request enable

Definition at line 100 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_CH2IE BIT(3)

channel 2 interrupt enable

Definition at line 92 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_CH3DEN BIT(12)

channel 3 DMA request enable

Definition at line 101 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_CH3IE BIT(4)

channel 3 interrupt enable

Definition at line 93 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_CMTDEN BIT(13)

channel control update DMA request enable

Definition at line 102 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_CMTIE BIT(5)

commutation DMA request enable

Definition at line 94 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_TRGDEN BIT(14)

trigger DMA request enable

Definition at line 103 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_TRGIE BIT(6)

trigger interrupt enable

Definition at line 95 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_UPDEN BIT(8)

update DMA request enable

Definition at line 97 of file gd32f3x0_timer.h.

#define TIMER_DMAINTEN_UPIE BIT(0)

update interrupt enable

Definition at line 89 of file gd32f3x0_timer.h.

#define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U)

DMA request of channel y is sent when channel y event occurs

Definition at line 325 of file gd32f3x0_timer.h.

#define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U)

DMA request of channel y is sent when update event occurs

Definition at line 324 of file gd32f3x0_timer.h.

#define TIMER_DMATB ( timerx ) REG32((timerx) + 0x4CU)

TIMER DMA transfer buffer register

Definition at line 49 of file gd32f3x0_timer.h.

#define TIMER_DMATB_DMATB BITS(0,15)

DMA transfer buffer address

Definition at line 227 of file gd32f3x0_timer.h.

#define TIMER_ENCODER_MODE0 SMCFG_SMC(1)

encoder mode 0

Definition at line 534 of file gd32f3x0_timer.h.

#define TIMER_ENCODER_MODE1 SMCFG_SMC(2)

encoder mode 1

Definition at line 535 of file gd32f3x0_timer.h.

#define TIMER_ENCODER_MODE2 SMCFG_SMC(3)

encoder mode 2

Definition at line 536 of file gd32f3x0_timer.h.

#define TIMER_ETP_FALLING TIMER_SMCFG_ETP

active low or falling edge active

Definition at line 558 of file gd32f3x0_timer.h.

#define TIMER_ETP_RISING ((uint32_t)0x00000000U)

active high or rising edge active

Definition at line 559 of file gd32f3x0_timer.h.

#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U)

break event generation

Definition at line 379 of file gd32f3x0_timer.h.

#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U)

channel 0 capture or compare event generation

Definition at line 373 of file gd32f3x0_timer.h.

#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U)

channel 1 capture or compare event generation

Definition at line 374 of file gd32f3x0_timer.h.

#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U)

channel 2 capture or compare event generation

Definition at line 375 of file gd32f3x0_timer.h.

#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U)

channel 3 capture or compare event generation

Definition at line 376 of file gd32f3x0_timer.h.

#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U)

channel commutation event generation

Definition at line 377 of file gd32f3x0_timer.h.

#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U)

trigger event generation

Definition at line 378 of file gd32f3x0_timer.h.

#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U)

update event generation

Definition at line 372 of file gd32f3x0_timer.h.

#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1)

divided by 2

Definition at line 553 of file gd32f3x0_timer.h.

#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2)

divided by 4

Definition at line 554 of file gd32f3x0_timer.h.

#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3)

divided by 8

Definition at line 555 of file gd32f3x0_timer.h.

#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0)

no divided

Definition at line 552 of file gd32f3x0_timer.h.

#define TIMER_FLAG_BRK TIMER_INTF_BRKIF

break flag

Definition at line 298 of file gd32f3x0_timer.h.

#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF

channel 0 flag

Definition at line 292 of file gd32f3x0_timer.h.

#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF

channel 0 overcapture flag

Definition at line 299 of file gd32f3x0_timer.h.

#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF

channel 1 flag

Definition at line 293 of file gd32f3x0_timer.h.

#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF

channel 1 overcapture flag

Definition at line 300 of file gd32f3x0_timer.h.

#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF

channel 2 flag

Definition at line 294 of file gd32f3x0_timer.h.

#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF

channel 2 overcapture flag

Definition at line 301 of file gd32f3x0_timer.h.

#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF

channel 3 flag

Definition at line 295 of file gd32f3x0_timer.h.

#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF

channel 3 overcapture flag

Definition at line 302 of file gd32f3x0_timer.h.

#define TIMER_FLAG_CMT TIMER_INTF_CMTIF

channel commutation flag

Definition at line 296 of file gd32f3x0_timer.h.

#define TIMER_FLAG_TRG TIMER_INTF_TRGIF

trigger flag

Definition at line 297 of file gd32f3x0_timer.h.

#define TIMER_FLAG_UP TIMER_INTF_UPIF

update flag

Definition at line 291 of file gd32f3x0_timer.h.

#define TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U)

TIMER hall sensor mode disable

Definition at line 563 of file gd32f3x0_timer.h.

#define TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U)

TIMER hall sensor mode enable

Definition at line 562 of file gd32f3x0_timer.h.

#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU)

input capture both edge

Definition at line 496 of file gd32f3x0_timer.h.

#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U)

input capture falling edge

Definition at line 495 of file gd32f3x0_timer.h.

#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U)

input capture rising edge

Definition at line 494 of file gd32f3x0_timer.h.

#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U)

no prescaler

Definition at line 504 of file gd32f3x0_timer.h.

#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U)

divided by 2

Definition at line 505 of file gd32f3x0_timer.h.

#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U)

divided by 4

Definition at line 506 of file gd32f3x0_timer.h.

#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU)

divided by 8

Definition at line 507 of file gd32f3x0_timer.h.

#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U)

channel y is configured as input and icy is mapped on CIy

Definition at line 499 of file gd32f3x0_timer.h.

#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U)

channel y is configured as input and icy is mapped on opposite input

Definition at line 500 of file gd32f3x0_timer.h.

#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U)

channel y is configured as input and icy is mapped on ITS

Definition at line 501 of file gd32f3x0_timer.h.

#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE

break interrupt

Definition at line 288 of file gd32f3x0_timer.h.

#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE

channel 0 interrupt

Definition at line 282 of file gd32f3x0_timer.h.

#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE

channel 1 interrupt

Definition at line 283 of file gd32f3x0_timer.h.

#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE

channel 2 interrupt

Definition at line 284 of file gd32f3x0_timer.h.

#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE

channel 3 interrupt

Definition at line 285 of file gd32f3x0_timer.h.

#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE

channel commutation interrupt flag

Definition at line 286 of file gd32f3x0_timer.h.

#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF

Definition at line 312 of file gd32f3x0_timer.h.

#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF

channel 0 interrupt flag

Definition at line 306 of file gd32f3x0_timer.h.

#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF

channel 1 interrupt flag

Definition at line 307 of file gd32f3x0_timer.h.

#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF

channel 2 interrupt flag

Definition at line 308 of file gd32f3x0_timer.h.

#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF

channel 3 interrupt flag

Definition at line 309 of file gd32f3x0_timer.h.

#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF

channel commutation interrupt flag

Definition at line 310 of file gd32f3x0_timer.h.

#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF

trigger interrupt flag

Definition at line 311 of file gd32f3x0_timer.h.

#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF

update interrupt flag

Definition at line 305 of file gd32f3x0_timer.h.

#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE

trigger interrupt

Definition at line 287 of file gd32f3x0_timer.h.

#define TIMER_INT_UP TIMER_DMAINTEN_UPIE

update interrupt

Definition at line 281 of file gd32f3x0_timer.h.

#define TIMER_INTF ( timerx ) REG32((timerx) + 0x10U)

TIMER interrupt flag register

Definition at line 34 of file gd32f3x0_timer.h.

#define TIMER_INTF_BRKIF BIT(7)

break interrupt flag

Definition at line 113 of file gd32f3x0_timer.h.

#define TIMER_INTF_CH0IF BIT(1)

channel 0 interrupt flag

Definition at line 107 of file gd32f3x0_timer.h.

#define TIMER_INTF_CH0OF BIT(9)

channel 0 overcapture flag

Definition at line 114 of file gd32f3x0_timer.h.

#define TIMER_INTF_CH1IF BIT(2)

channel 1 interrupt flag

Definition at line 108 of file gd32f3x0_timer.h.

#define TIMER_INTF_CH1OF BIT(10)

channel 1 overcapture flag

Definition at line 115 of file gd32f3x0_timer.h.

#define TIMER_INTF_CH2IF BIT(3)

channel 2 interrupt flag

Definition at line 109 of file gd32f3x0_timer.h.

#define TIMER_INTF_CH2OF BIT(11)

channel 2 overcapture flag

Definition at line 116 of file gd32f3x0_timer.h.

#define TIMER_INTF_CH3IF BIT(4)

channel 3 interrupt flag

Definition at line 110 of file gd32f3x0_timer.h.

#define TIMER_INTF_CH3OF BIT(12)

channel 3 overcapture flag

Definition at line 117 of file gd32f3x0_timer.h.

#define TIMER_INTF_CMTIF BIT(5)

channel commutation interrupt flag

Definition at line 111 of file gd32f3x0_timer.h.

#define TIMER_INTF_TRGIF BIT(6)

trigger interrupt flag

Definition at line 112 of file gd32f3x0_timer.h.

#define TIMER_INTF_UPIF BIT(0)

update interrupt flag

Definition at line 106 of file gd32f3x0_timer.h.

#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U)

when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled

Definition at line 416 of file gd32f3x0_timer.h.

#define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U)

when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits

Definition at line 415 of file gd32f3x0_timer.h.

#define TIMER_IRMP ( timerx ) REG32((timerx) + 0x50U)

TIMER channel input remap register

Definition at line 50 of file gd32f3x0_timer.h.

#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U)

master slave mode disable

Definition at line 548 of file gd32f3x0_timer.h.

#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U)

master slave mode enable

Definition at line 547 of file gd32f3x0_timer.h.

#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U)

channel output clear function disable

Definition at line 487 of file gd32f3x0_timer.h.

#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U)

channel output clear function enable

Definition at line 486 of file gd32f3x0_timer.h.

#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000)

channel output fast function disable

Definition at line 483 of file gd32f3x0_timer.h.

#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004)

channel output fast function enable

Definition at line 482 of file gd32f3x0_timer.h.

#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100)

idle state of channel output is high

Definition at line 460 of file gd32f3x0_timer.h.

#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000)

idle state of channel output is low

Definition at line 461 of file gd32f3x0_timer.h.

#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U)

active mode

Definition at line 469 of file gd32f3x0_timer.h.

#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U)

force high mode

Definition at line 473 of file gd32f3x0_timer.h.

#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U)

inactive mode

Definition at line 470 of file gd32f3x0_timer.h.

#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U)

force low mode

Definition at line 472 of file gd32f3x0_timer.h.

#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U)

PWM0 mode

Definition at line 474 of file gd32f3x0_timer.h.

#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U)

PWM1 mode

Definition at line 475 of file gd32f3x0_timer.h.

#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U)

timing mode

Definition at line 468 of file gd32f3x0_timer.h.

#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U)

toggle mode

Definition at line 471 of file gd32f3x0_timer.h.

#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U)

channel output polarity is high

Definition at line 452 of file gd32f3x0_timer.h.

#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U)

channel output polarity is low

Definition at line 453 of file gd32f3x0_timer.h.

#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U)

channel output shadow state disable

Definition at line 479 of file gd32f3x0_timer.h.

#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U)

channel output shadow state enable

Definition at line 478 of file gd32f3x0_timer.h.

#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U)

idle state of channel complementary output is high

Definition at line 464 of file gd32f3x0_timer.h.

#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U)

idle state of channel complementary output is low

Definition at line 465 of file gd32f3x0_timer.h.

#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U)

channel complementary output polarity is high

Definition at line 456 of file gd32f3x0_timer.h.

#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U)

channel complementary output polarity is low

Definition at line 457 of file gd32f3x0_timer.h.

#define TIMER_OCPRE_CLEAR_SOURCE_CLR ((uint8_t)0x00U)

OCPRE_CLR_INT is connected to the OCPRE_CLR input

Definition at line 543 of file gd32f3x0_timer.h.

#define TIMER_OCPRE_CLEAR_SOURCE_ETIF ((uint8_t)0x01U)

OCPRE_CLR_INT is connected to ETIF

Definition at line 544 of file gd32f3x0_timer.h.

#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U)

output automatic disable

Definition at line 424 of file gd32f3x0_timer.h.

#define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U)

output automatic enable

Definition at line 423 of file gd32f3x0_timer.h.

#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U)

output value selection disable

Definition at line 570 of file gd32f3x0_timer.h.

#define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U)

output value selection enable

Definition at line 571 of file gd32f3x0_timer.h.

#define TIMER_PSC ( timerx ) REG32((timerx) + 0x28U)

TIMER prescaler register

Definition at line 40 of file gd32f3x0_timer.h.

#define TIMER_PSC_PSC BITS(0,15)

prescaler value of the counter clock

Definition at line 187 of file gd32f3x0_timer.h.

#define TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U)

the prescaler is loaded right now

Definition at line 389 of file gd32f3x0_timer.h.

#define TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U)

the prescaler is loaded at the next update event

Definition at line 390 of file gd32f3x0_timer.h.

#define TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U)

when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled

Definition at line 412 of file gd32f3x0_timer.h.

#define TIMER_ROS_STATE_ENABLE ((uint32_t)0x00000800U)

when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits

Definition at line 411 of file gd32f3x0_timer.h.

#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0)

slave mode disable

Definition at line 533 of file gd32f3x0_timer.h.

#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6)

event mode

Definition at line 539 of file gd32f3x0_timer.h.

#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7)

external clock mode 0

Definition at line 540 of file gd32f3x0_timer.h.

#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5)

pause mode

Definition at line 538 of file gd32f3x0_timer.h.

#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4)

restart mode

Definition at line 537 of file gd32f3x0_timer.h.

#define TIMER_SMCFG ( timerx ) REG32((timerx) + 0x08U)

TIMER slave mode configuration register

Definition at line 32 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_ETFC BITS(8,11)

external trigger filter control

Definition at line 83 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_ETP BIT(15)

external trigger polarity

Definition at line 86 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_ETPSC BITS(12,13)

external trigger prescaler

Definition at line 84 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_MSM BIT(7)

master-slave mode

Definition at line 82 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_OCRC BIT(3)

OCPRE clear source selection

Definition at line 80 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_SMC BITS(0,2)

slave mode control

Definition at line 79 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_SMC1 BIT(14)

part of SMC for enable external clock mode 1

Definition at line 85 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_TRGS BITS(4,6)

trigger selection

Definition at line 81 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4)

TI0 Edge Detector

Definition at line 515 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5)

filtered TIMER input 0

Definition at line 516 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6)

filtered TIMER input 1

Definition at line 517 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7)

external trigger

Definition at line 518 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0)

internal trigger 0

Definition at line 511 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1)

internal trigger 1

Definition at line 512 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2)

internal trigger 2

Definition at line 513 of file gd32f3x0_timer.h.

#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3)

internal trigger 3

Definition at line 514 of file gd32f3x0_timer.h.

#define TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U)

repetitive pulse mode

Definition at line 404 of file gd32f3x0_timer.h.

#define TIMER_SP_MODE_SINGLE ((uint8_t)0x00U)

single pulse mode

Definition at line 403 of file gd32f3x0_timer.h.

#define TIMER_SWEVG ( timerx ) REG32((timerx) + 0x14U)

TIMER software event generation register

Definition at line 35 of file gd32f3x0_timer.h.

#define TIMER_SWEVG_BRKG BIT(7)

break event generation

Definition at line 127 of file gd32f3x0_timer.h.

#define TIMER_SWEVG_CH0G BIT(1)

channel 0 capture or compare event generation

Definition at line 121 of file gd32f3x0_timer.h.

#define TIMER_SWEVG_CH1G BIT(2)

channel 1 capture or compare event generation

Definition at line 122 of file gd32f3x0_timer.h.

#define TIMER_SWEVG_CH2G BIT(3)

channel 2 capture or compare event generation

Definition at line 123 of file gd32f3x0_timer.h.

#define TIMER_SWEVG_CH3G BIT(4)

channel 3 capture or compare event generation

Definition at line 124 of file gd32f3x0_timer.h.

#define TIMER_SWEVG_CMTG BIT(5)

channel commutation event generation

Definition at line 125 of file gd32f3x0_timer.h.

#define TIMER_SWEVG_TRGG BIT(6)

trigger event generation

Definition at line 126 of file gd32f3x0_timer.h.

#define TIMER_SWEVG_UPG BIT(0)

update event generate

Definition at line 120 of file gd32f3x0_timer.h.

#define TIMER_TRI_OUT_SRC_CC0 CTL1_MMC(3)

a capture or a compare match occurred in channal0 as trigger output TRGO

Definition at line 525 of file gd32f3x0_timer.h.

#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1)

the counter enable signal TIMER_CTL0_CEN as trigger output

Definition at line 523 of file gd32f3x0_timer.h.

#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4)

O0CPRE as trigger output

Definition at line 526 of file gd32f3x0_timer.h.

#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5)

O1CPRE as trigger output

Definition at line 527 of file gd32f3x0_timer.h.

#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6)

O2CPRE as trigger output

Definition at line 528 of file gd32f3x0_timer.h.

#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7)

O3CPRE as trigger output

Definition at line 529 of file gd32f3x0_timer.h.

#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0)

the UPG bit as trigger output

Definition at line 522 of file gd32f3x0_timer.h.

#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2)

update event as trigger output

Definition at line 524 of file gd32f3x0_timer.h.

#define TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U)

update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger

Definition at line 408 of file gd32f3x0_timer.h.

#define TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U)

update generate only by counter overflow/underflow

Definition at line 407 of file gd32f3x0_timer.h.

#define TIMER_UPDATECTL_CCU ((uint8_t)0x00U)

the shadow registers update by when CMTG bit is set

Definition at line 490 of file gd32f3x0_timer.h.

#define TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U)

the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs

Definition at line 491 of file gd32f3x0_timer.h.

Function Documentation

void timer_auto_reload_shadow_disable ( uint32_t timer_periph )

disable the auto reload shadow function

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
none

Definition at line 153 of file gd32f3x0_timer.c.

154 {
155 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
156 }
TIMER_CTL0_ARSE
#define TIMER_CTL0_ARSE
Definition: gd32f3x0_timer.h:61
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
void timer_auto_reload_shadow_enable ( uint32_t timer_periph )

enable the auto reload shadow function

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
none

Definition at line 142 of file gd32f3x0_timer.c.

143 {
144 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
145 }
TIMER_CTL0_ARSE
#define TIMER_CTL0_ARSE
Definition: gd32f3x0_timer.h:61
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
void timer_automatic_output_disable ( uint32_t timer_periph )

disable TIMER output automatic function

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 671 of file gd32f3x0_timer.c.

672 {
673 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
674 }
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f3x0_timer.h:47
TIMER_CCHP_OAEN
#define TIMER_CCHP_OAEN
Definition: gd32f3x0_timer.h:219
void timer_automatic_output_enable ( uint32_t timer_periph )

enable TIMER output automatic function

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 660 of file gd32f3x0_timer.c.

661 {
662 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
663 }
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f3x0_timer.h:47
TIMER_CCHP_OAEN
#define TIMER_CCHP_OAEN
Definition: gd32f3x0_timer.h:219
void timer_autoreload_value_config | ( | uint32_t | timer_periph,
 |  | uint32_t | autoreload
 | ) |  |

configure TIMER autoreload register value

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[in] | autoreload | the counter auto-reload value
[out] | none
Return values
none

Definition at line 257 of file gd32f3x0_timer.c.

258 {
259 TIMER_CAR(timer_periph) = (uint32_t)autoreload;
260 }
TIMER_CAR
#define TIMER_CAR(timerx)
Definition: gd32f3x0_timer.h:41
void timer_break_config | ( | uint32_t | timer_periph,
 |  | timer_break_parameter_struct * | breakpara
 | ) |  |

configure TIMER break function

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[in] | breakpara | TIMER break parameter struct runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE deadtime: 0~255 breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE
[out] | none
Return values
none

Definition at line 621 of file gd32f3x0_timer.c.

622 {
623 TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))|
624 ((uint32_t)(breakpara->ideloffstate))|
625 ((uint32_t)(breakpara->deadtime))|
626 ((uint32_t)(breakpara->breakpolarity))|
627 ((uint32_t)(breakpara->outputautostate)) |
628 ((uint32_t)(breakpara->protectmode))|
629 ((uint32_t)(breakpara->breakstate))) ;
630 }
timer_break_parameter_struct::deadtime
uint16_t deadtime
Definition: gd32f3x0_timer.h:253
timer_break_parameter_struct::ideloffstate
uint32_t ideloffstate
Definition: gd32f3x0_timer.h:252
timer_break_parameter_struct::outputautostate
uint16_t outputautostate
Definition: gd32f3x0_timer.h:255
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f3x0_timer.h:47
timer_break_parameter_struct::runoffstate
uint16_t runoffstate
Definition: gd32f3x0_timer.h:251
timer_break_parameter_struct::breakpolarity
uint16_t breakpolarity
Definition: gd32f3x0_timer.h:254
timer_break_parameter_struct::breakstate
uint16_t breakstate
Definition: gd32f3x0_timer.h:257
timer_break_parameter_struct::protectmode
uint16_t protectmode
Definition: gd32f3x0_timer.h:256
void timer_break_disable ( uint32_t timer_periph )

disable TIMER break function

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 649 of file gd32f3x0_timer.c.

650 {
651 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
652 }
TIMER_CCHP_BRKEN
#define TIMER_CCHP_BRKEN
Definition: gd32f3x0_timer.h:217
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f3x0_timer.h:47
void timer_break_enable ( uint32_t timer_periph )

enable TIMER break function

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 638 of file gd32f3x0_timer.c.

639 {
640 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
641 }
TIMER_CCHP_BRKEN
#define TIMER_CCHP_BRKEN
Definition: gd32f3x0_timer.h:217
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f3x0_timer.h:47
uint32_t timer_channel_capture_value_register_read | ( | uint32_t | timer_periph,
 |  | uint16_t | channel
 | ) |  |

read TIMER channel capture compare register value

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[out] | none
Return values
channel capture compare register value

Definition at line 1399 of file gd32f3x0_timer.c.

1400 {
1401 uint32_t count_value = 0U;
1402
1403 switch(channel){
1404 case TIMER_CH_0:
1405 count_value = TIMER_CH0CV(timer_periph);
1406 break;
1407 case TIMER_CH_1:
1408 count_value = TIMER_CH1CV(timer_periph);
1409 break;
1410 case TIMER_CH_2:
1411 count_value = TIMER_CH2CV(timer_periph);
1412 break;
1413 case TIMER_CH_3:
1414 count_value = TIMER_CH3CV(timer_periph);
1415 break;
1416 default:
1417 break;
1418 }
1419 return (count_value);
1420 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CH0CV
#define TIMER_CH0CV(timerx)
Definition: gd32f3x0_timer.h:43
TIMER_CH3CV
#define TIMER_CH3CV(timerx)
Definition: gd32f3x0_timer.h:46
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CH1CV
#define TIMER_CH1CV(timerx)
Definition: gd32f3x0_timer.h:44
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CH2CV
#define TIMER_CH2CV(timerx)
Definition: gd32f3x0_timer.h:45
void timer_channel_complementary_output_polarity_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocnpolarity
 | ) |  |

configure TIMER channel complementary output polarity

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel2(TIMERx(x=1,2))
[in] ocnpolarity channel complementary output polarity
  • TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
  • TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
[out] | none
Return values
none

Definition at line 1135 of file gd32f3x0_timer.c.

1136 {
1137 switch(channel){
1138 /* configure TIMER_CH_0 */
1139 case TIMER_CH_0:
1140 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
1141 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
1142 break;
1143 /* configure TIMER_CH_1 */
1144 case TIMER_CH_1:
1145 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
1146 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
1147 break;
1148 /* configure TIMER_CH_2 */
1149 case TIMER_CH_2:
1150 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
1151 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
1152 break;
1153 /* configure TIMER_CH_3 */
1154 case TIMER_CH_3:
1155 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3NP);
1156 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 12U);
1157 break;
1158 default:
1159 break;
1160 }
1161 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL2_CH3NP
#define TIMER_CHCTL2_CH3NP
Definition: gd32f3x0_timer.h:180
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f3x0_timer.h:173
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f3x0_timer.h:169
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
TIMER_CHCTL2_CH2NP
#define TIMER_CHCTL2_CH2NP
Definition: gd32f3x0_timer.h:177
void timer_channel_complementary_output_state_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocnstate
 | ) |  |

configure TIMER channel complementary output enable state

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0,14..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0))
[in] ocnstate TIMER channel complementary output enable state
  • TIMER_CCXN_ENABLE: channel complementary enable
  • TIMER_CCXN_DISABLE: channel complementary disable
[out] | none
Return values
none

Definition at line 1218 of file gd32f3x0_timer.c.

1219 {
1220 switch(channel){
1221 /* configure TIMER_CH_0 */
1222 case TIMER_CH_0:
1223 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
1224 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
1225 break;
1226 /* configure TIMER_CH_1 */
1227 case TIMER_CH_1:
1228 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
1229 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
1230 break;
1231 /* configure TIMER_CH_2 */
1232 case TIMER_CH_2:
1233 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
1234 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
1235 break;
1236 default:
1237 break;
1238 }
1239 }
TIMER_CHCTL2_CH1NEN
#define TIMER_CHCTL2_CH1NEN
Definition: gd32f3x0_timer.h:172
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL2_CH2NEN
#define TIMER_CHCTL2_CH2NEN
Definition: gd32f3x0_timer.h:176
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
TIMER_CHCTL2_CH0NEN
#define TIMER_CHCTL2_CH0NEN
Definition: gd32f3x0_timer.h:168
void timer_channel_control_shadow_config | ( | uint32_t | timer_periph,
 |  | ControlStatus | newvalue
 | ) |  |

channel capture/compare control shadow register enable

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 699 of file gd32f3x0_timer.c.

700 {
701 if(ENABLE == newvalue){
702 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
703 }else{
704 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
705 }
706 }
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f3x0_timer.h:31
TIMER_CTL1_CCSE
#define TIMER_CTL1_CCSE
Definition: gd32f3x0_timer.h:65
void timer_channel_control_shadow_update_config | ( | uint32_t | timer_periph,
 |  | uint8_t | ccuctl
 | ) |  |

configure TIMER channel control shadow register update control

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[in] ccuctl channel control shadow register update control
  • TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
  • TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs
[out] | none
Return values
none

Definition at line 717 of file gd32f3x0_timer.c.

718 {
719 if(TIMER_UPDATECTL_CCU == ccuctl){
720 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
721 }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
722 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
723 }else{
724 }
725 }
TIMER_UPDATECTL_CCU
#define TIMER_UPDATECTL_CCU
Definition: gd32f3x0_timer.h:490
TIMER_CTL1_CCUC
#define TIMER_CTL1_CCUC
Definition: gd32f3x0_timer.h:66
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f3x0_timer.h:31
TIMER_UPDATECTL_CCUTRI
#define TIMER_UPDATECTL_CCUTRI
Definition: gd32f3x0_timer.h:491
void timer_channel_dma_request_source_select | ( | uint32_t | timer_periph,
 |  | uint8_t | dma_request
 | ) |  |

channel DMA request source selection

Parameters
[in] | timer_periph | TIMERx(x=0..2,14..16)
[in] dma_request channel DMA request source selection
  • TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs
  • TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs
[out] | none
Return values
none

Definition at line 542 of file gd32f3x0_timer.c.

543 {
544 if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
545 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
546 }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
547 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
548 }else{
549 }
550 }
TIMER_CTL1_DMAS
#define TIMER_CTL1_DMAS
Definition: gd32f3x0_timer.h:67
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f3x0_timer.h:31
TIMER_DMAREQUEST_CHANNELEVENT
#define TIMER_DMAREQUEST_CHANNELEVENT
Definition: gd32f3x0_timer.h:325
TIMER_DMAREQUEST_UPDATEEVENT
#define TIMER_DMAREQUEST_UPDATEEVENT
Definition: gd32f3x0_timer.h:324
void timer_channel_input_capture_prescaler_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | prescaler
 | ) |  |

configure TIMER channel input capture prescaler value

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] prescaler channel input capture prescaler value
  • TIMER_IC_PSC_DIV1: no prescaler
  • TIMER_IC_PSC_DIV2: divided by 2
  • TIMER_IC_PSC_DIV4: divided by 4
  • TIMER_IC_PSC_DIV8: divided by 8
[out] | none
Return values
none

Definition at line 1360 of file gd32f3x0_timer.c.

1361 {
1362 switch(channel){
1363 /* configure TIMER_CH_0 */
1364 case TIMER_CH_0:
1365 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
1366 TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
1367 break;
1368 /* configure TIMER_CH_1 */
1369 case TIMER_CH_1:
1370 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
1371 TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
1372 break;
1373 /* configure TIMER_CH_2 */
1374 case TIMER_CH_2:
1375 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
1376 TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
1377 break;
1378 /* configure TIMER_CH_3 */
1379 case TIMER_CH_3:
1380 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
1381 TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
1382 break;
1383 default:
1384 break;
1385 }
1386 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CHCTL0_CH1CAPPSC
#define TIMER_CHCTL0_CH1CAPPSC
Definition: gd32f3x0_timer.h:144
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL1_CH2CAPPSC
#define TIMER_CHCTL1_CH2CAPPSC
Definition: gd32f3x0_timer.h:160
TIMER_CHCTL0_CH0CAPPSC
#define TIMER_CHCTL0_CH0CAPPSC
Definition: gd32f3x0_timer.h:142
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL1_CH3CAPPSC
#define TIMER_CHCTL1_CH3CAPPSC
Definition: gd32f3x0_timer.h:162
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
void timer_channel_output_clear_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | occlear
 | ) |  |

configure TIMER channel output clear function

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] occlear channel output clear function
  • TIMER_OC_CLEAR_ENABLE: channel output clear function enable
  • TIMER_OC_CLEAR_DISABLE: channel output clear function disable
[out] | none
Return values
none

Definition at line 1051 of file gd32f3x0_timer.c.

1052 {
1053 switch(channel){
1054 /* configure TIMER_CH_0 */
1055 case TIMER_CH_0:
1056 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
1057 TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
1058 break;
1059 /* configure TIMER_CH_1 */
1060 case TIMER_CH_1:
1061 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
1062 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1063 break;
1064 /* configure TIMER_CH_2 */
1065 case TIMER_CH_2:
1066 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
1067 TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
1068 break;
1069 /* configure TIMER_CH_3 */
1070 case TIMER_CH_3:
1071 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
1072 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1073 break;
1074 default:
1075 break;
1076 }
1077 }
TIMER_CHCTL0_CH0COMCEN
#define TIMER_CHCTL0_CH0COMCEN
Definition: gd32f3x0_timer.h:135
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL1_CH3COMCEN
#define TIMER_CHCTL1_CH3COMCEN
Definition: gd32f3x0_timer.h:158
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL0_CH1COMCEN
#define TIMER_CHCTL0_CH1COMCEN
Definition: gd32f3x0_timer.h:140
TIMER_CHCTL1_CH2COMCEN
#define TIMER_CHCTL1_CH2COMCEN
Definition: gd32f3x0_timer.h:153
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
void timer_channel_output_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | timer_oc_parameter_struct * | ocpara
 | ) |  |

configure TIMER channel output function

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel 0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel 1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel 2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel 3(TIMERx(x=0..2))
[in] | ocpara | TIMER channeln output parameter struct outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH
[out] | none
Return values
none

Definition at line 745 of file gd32f3x0_timer.c.

746 {
747 switch(channel){
748 /* configure TIMER_CH_0 */
749 case TIMER_CH_0:
750 /* reset the CH0EN bit */
751 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
752 /* set the CH0EN bit */
753 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
754 /* reset the CH0P bit */
755 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
756 /* set the CH0P bit */
757 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
758
759 if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){
760 /* reset the CH0NEN bit */
761 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
762 /* set the CH0NEN bit */
763 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
764 /* reset the CH0NP bit */
765 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
766 /* set the CH0NP bit */
767 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
768 /* reset the ISO0 bit */
769 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
770 /* set the ISO0 bit */
771 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
772 /* reset the ISO0N bit */
773 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
774 /* set the ISO0N bit */
775 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
776 }
777 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
778 break;
779 /* configure TIMER_CH_1 */
780 case TIMER_CH_1:
781 /* reset the CH1EN bit */
782 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
783 /* set the CH1EN bit */
784 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 4U);
785 /* reset the CH1P bit */
786 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
787 /* set the CH1P bit */
788 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U);
789
790 if(TIMER0 == timer_periph){
791 /* reset the CH1NEN bit */
792 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
793 /* set the CH1NEN bit */
794 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U);
795 /* reset the CH1NP bit */
796 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
797 /* set the CH1NP bit */
798 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U);
799 /* reset the ISO1 bit */
800 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
801 /* set the ISO1 bit */
802 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
803 /* reset the ISO1N bit */
804 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
805 /* set the ISO1N bit */
806 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U);
807 }
808
809 if(TIMER14 == timer_periph){
810 /* reset the ISO1 bit */
811 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
812 /* set the ISO1 bit */
813 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
814 }
815
816 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
817 break;
818 /* configure TIMER_CH_2 */
819 case TIMER_CH_2:
820 /* reset the CH2EN bit */
821 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
822 /* set the CH2EN bit */
823 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 8U);
824 /* reset the CH2P bit */
825 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
826 /* set the CH2P bit */
827 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U);
828
829 if(TIMER0 == timer_periph){
830 /* reset the CH2NEN bit */
831 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
832 /* set the CH2NEN bit */
833 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U);
834 /* reset the CH2NP bit */
835 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
836 /* set the CH2NP bit */
837 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U);
838 /* reset the ISO2 bit */
839 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
840 /* set the ISO2 bit */
841 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U);
842 /* reset the ISO2N bit */
843 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
844 /* set the ISO2N bit */
845 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U);
846 }
847 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
848 break;
849 /* configure TIMER_CH_3 */
850 case TIMER_CH_3:
851 /* reset the CH3EN bit */
852 TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN);
853 /* set the CH3EN bit */
854 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 12U);
855 /* reset the CH3P bit */
856 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
857 /* set the CH3P bit */
858 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U);
859
860 if(TIMER0 == timer_periph){
861 /* reset the ISO3 bit */
862 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
863 /* set the ISO3 bit */
864 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U);
865 }
866 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
867 break;
868 default:
869 break;
870 }
871 }
TIMER0
#define TIMER0
Definition: gd32f3x0_timer.h:18
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f3x0_timer.h:171
TIMER_CHCTL2_CH1NEN
#define TIMER_CHCTL2_CH1NEN
Definition: gd32f3x0_timer.h:172
timer_oc_parameter_struct::ocnidlestate
uint16_t ocnidlestate
Definition: gd32f3x0_timer.h:268
TIMER_CTL1_ISO1
#define TIMER_CTL1_ISO1
Definition: gd32f3x0_timer.h:72
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CHCTL1_CH3MS
#define TIMER_CHCTL1_CH3MS
Definition: gd32f3x0_timer.h:154
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER16
#define TIMER16
Definition: gd32f3x0_timer.h:27
TIMER_CHCTL2_CH2NEN
#define TIMER_CHCTL2_CH2NEN
Definition: gd32f3x0_timer.h:176
TIMER_CTL1_ISO3
#define TIMER_CTL1_ISO3
Definition: gd32f3x0_timer.h:76
TIMER14
#define TIMER14
Definition: gd32f3x0_timer.h:25
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f3x0_timer.h:31
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
timer_oc_parameter_struct::ocpolarity
uint16_t ocpolarity
Definition: gd32f3x0_timer.h:265
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f3x0_timer.h:173
TIMER_CTL1_ISO1N
#define TIMER_CTL1_ISO1N
Definition: gd32f3x0_timer.h:73
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f3x0_timer.h:169
TIMER_CHCTL1_CH2MS
#define TIMER_CHCTL1_CH2MS
Definition: gd32f3x0_timer.h:149
TIMER_CHCTL2_CH2EN
#define TIMER_CHCTL2_CH2EN
Definition: gd32f3x0_timer.h:174
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f3x0_timer.h:166
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f3x0_timer.h:167
TIMER_CHCTL2_CH3EN
#define TIMER_CHCTL2_CH3EN
Definition: gd32f3x0_timer.h:178
TIMER_CHCTL2_CH2P
#define TIMER_CHCTL2_CH2P
Definition: gd32f3x0_timer.h:175
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
TIMER15
#define TIMER15
Definition: gd32f3x0_timer.h:26
timer_oc_parameter_struct::outputstate
uint32_t outputstate
Definition: gd32f3x0_timer.h:263
timer_oc_parameter_struct::ocidlestate
uint16_t ocidlestate
Definition: gd32f3x0_timer.h:267
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f3x0_timer.h:131
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f3x0_timer.h:170
TIMER_CHCTL2_CH3P
#define TIMER_CHCTL2_CH3P
Definition: gd32f3x0_timer.h:179
TIMER_CTL1_ISO0
#define TIMER_CTL1_ISO0
Definition: gd32f3x0_timer.h:70
TIMER_CHCTL2_CH0NEN
#define TIMER_CHCTL2_CH0NEN
Definition: gd32f3x0_timer.h:168
TIMER_CTL1_ISO2N
#define TIMER_CTL1_ISO2N
Definition: gd32f3x0_timer.h:75
TIMER_CTL1_ISO0N
#define TIMER_CTL1_ISO0N
Definition: gd32f3x0_timer.h:71
TIMER_CHCTL2_CH2NP
#define TIMER_CHCTL2_CH2NP
Definition: gd32f3x0_timer.h:177
timer_oc_parameter_struct::ocnpolarity
uint16_t ocnpolarity
Definition: gd32f3x0_timer.h:266
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f3x0_timer.h:136
TIMER_CTL1_ISO2
#define TIMER_CTL1_ISO2
Definition: gd32f3x0_timer.h:74
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
timer_oc_parameter_struct::outputnstate
uint16_t outputnstate
Definition: gd32f3x0_timer.h:264
void timer_channel_output_fast_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocfast
 | ) |  |

configure TIMER channel output fast function

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] ocfast channel output fast function
  • TIMER_OC_FAST_ENABLE: channel output fast function enable
  • TIMER_OC_FAST_DISABLE: channel output fast function disable
[out] | none
Return values
none

Definition at line 1009 of file gd32f3x0_timer.c.

1010 {
1011 switch(channel){
1012 /* configure TIMER_CH_0 */
1013 case TIMER_CH_0:
1014 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
1015 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
1016 break;
1017 /* configure TIMER_CH_1 */
1018 case TIMER_CH_1:
1019 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN);
1020 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1021 break;
1022 /* configure TIMER_CH_2 */
1023 case TIMER_CH_2:
1024 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN);
1025 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
1026 break;
1027 /* configure TIMER_CH_3 */
1028 case TIMER_CH_3:
1029 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN);
1030 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1031 break;
1032 default:
1033 break;
1034 }
1035 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL1_CH3COMFEN
#define TIMER_CHCTL1_CH3COMFEN
Definition: gd32f3x0_timer.h:155
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL1_CH2COMFEN
#define TIMER_CHCTL1_CH2COMFEN
Definition: gd32f3x0_timer.h:150
TIMER_CHCTL0_CH0COMFEN
#define TIMER_CHCTL0_CH0COMFEN
Definition: gd32f3x0_timer.h:132
TIMER_CHCTL0_CH1COMFEN
#define TIMER_CHCTL0_CH1COMFEN
Definition: gd32f3x0_timer.h:137
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
void timer_channel_output_mode_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocmode
 | ) |  |

configure TIMER channel output compare mode

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] ocmode channel output compare mode
  • TIMER_OC_MODE_TIMING: timing mode
  • TIMER_OC_MODE_ACTIVE: active mode
  • TIMER_OC_MODE_INACTIVE: inactive mode
  • TIMER_OC_MODE_TOGGLE: toggle mode
  • TIMER_OC_MODE_LOW: force low mode
  • TIMER_OC_MODE_HIGH: force high mode
  • TIMER_OC_MODE_PWM0: PWM0 mode
  • TIMER_OC_MODE_PWM1: PWM1 mode
[out] | none
Return values
none

Definition at line 893 of file gd32f3x0_timer.c.

894 {
895 switch(channel){
896 /* configure TIMER_CH_0 */
897 case TIMER_CH_0:
898 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
899 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
900 break;
901 /* configure TIMER_CH_1 */
902 case TIMER_CH_1:
903 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
904 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
905 break;
906 /* configure TIMER_CH_2 */
907 case TIMER_CH_2:
908 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
909 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
910 break;
911 /* configure TIMER_CH_3 */
912 case TIMER_CH_3:
913 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
914 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
915 break;
916 default:
917 break;
918 }
919 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL1_CH3COMCTL
#define TIMER_CHCTL1_CH3COMCTL
Definition: gd32f3x0_timer.h:157
TIMER_CHCTL0_CH1COMCTL
#define TIMER_CHCTL0_CH1COMCTL
Definition: gd32f3x0_timer.h:139
TIMER_CHCTL0_CH0COMCTL
#define TIMER_CHCTL0_CH0COMCTL
Definition: gd32f3x0_timer.h:134
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
TIMER_CHCTL1_CH2COMCTL
#define TIMER_CHCTL1_CH2COMCTL
Definition: gd32f3x0_timer.h:152
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
void timer_channel_output_polarity_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocpolarity
 | ) |  |

configure TIMER channel output polarity

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] ocpolarity channel output polarity
  • TIMER_OC_POLARITY_HIGH: channel output polarity is high
  • TIMER_OC_POLARITY_LOW: channel output polarity is low
[out] | none
Return values
none

Definition at line 1093 of file gd32f3x0_timer.c.

1094 {
1095 switch(channel){
1096 /* configure TIMER_CH_0 */
1097 case TIMER_CH_0:
1098 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
1099 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
1100 break;
1101 /* configure TIMER_CH_1 */
1102 case TIMER_CH_1:
1103 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
1104 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
1105 break;
1106 /* configure TIMER_CH_2 */
1107 case TIMER_CH_2:
1108 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
1109 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
1110 break;
1111 /* configure TIMER_CH_3 */
1112 case TIMER_CH_3:
1113 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
1114 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
1115 break;
1116 default:
1117 break;
1118 }
1119 }
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f3x0_timer.h:171
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f3x0_timer.h:167
TIMER_CHCTL2_CH2P
#define TIMER_CHCTL2_CH2P
Definition: gd32f3x0_timer.h:175
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
TIMER_CHCTL2_CH3P
#define TIMER_CHCTL2_CH3P
Definition: gd32f3x0_timer.h:179
void timer_channel_output_pulse_value_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint32_t | pulse
 | ) |  |

configure TIMER channel output pulse value

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] | pulse | channel output pulse value
[out] | none
Return values
none

Definition at line 933 of file gd32f3x0_timer.c.

934 {
935 switch(channel){
936 case TIMER_CH_0:
937 TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
938 break;
939 case TIMER_CH_1:
940 TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
941 break;
942 case TIMER_CH_2:
943 TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
944 break;
945 case TIMER_CH_3:
946 TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
947 break;
948 default:
949 break;
950 }
951 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CH0CV
#define TIMER_CH0CV(timerx)
Definition: gd32f3x0_timer.h:43
TIMER_CH3CV
#define TIMER_CH3CV(timerx)
Definition: gd32f3x0_timer.h:46
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CH1CV
#define TIMER_CH1CV(timerx)
Definition: gd32f3x0_timer.h:44
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CH2CV
#define TIMER_CH2CV(timerx)
Definition: gd32f3x0_timer.h:45
void timer_channel_output_shadow_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocshadow
 | ) |  |

configure TIMER channel output shadow function

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] ocshadow channel output shadow state
  • TIMER_OC_SHADOW_ENABLE: channel output shadow state enable
  • TIMER_OC_SHADOW_DISABLE: channel output shadow state disable
[out] | none
Return values
none

Definition at line 967 of file gd32f3x0_timer.c.

968 {
969 switch(channel){
970 /* configure TIMER_CH_0 */
971 case TIMER_CH_0:
972 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
973 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
974 break;
975 /* configure TIMER_CH_1 */
976 case TIMER_CH_1:
977 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
978 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
979 break;
980 /* configure TIMER_CH_2 */
981 case TIMER_CH_2:
982 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
983 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
984 break;
985 /* configure TIMER_CH_3 */
986 case TIMER_CH_3:
987 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
988 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
989 break;
990 default:
991 break;
992 }
993 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
TIMER_CHCTL1_CH2COMSEN
#define TIMER_CHCTL1_CH2COMSEN
Definition: gd32f3x0_timer.h:151
TIMER_CHCTL0_CH0COMSEN
#define TIMER_CHCTL0_CH0COMSEN
Definition: gd32f3x0_timer.h:133
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL1_CH3COMSEN
#define TIMER_CHCTL1_CH3COMSEN
Definition: gd32f3x0_timer.h:156
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL0_CH1COMSEN
#define TIMER_CHCTL0_CH1COMSEN
Definition: gd32f3x0_timer.h:138
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
void timer_channel_output_state_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint32_t | state
 | ) |  |

configure TIMER channel enable state

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] state TIMER channel enable state
  • TIMER_CCX_ENABLE: channel enable
  • TIMER_CCX_DISABLE: channel disable
[out] | none
Return values
none

Definition at line 1177 of file gd32f3x0_timer.c.

1178 {
1179 switch(channel){
1180 /* configure TIMER_CH_0 */
1181 case TIMER_CH_0:
1182 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1183 TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
1184 break;
1185 /* configure TIMER_CH_1 */
1186 case TIMER_CH_1:
1187 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1188 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
1189 break;
1190 /* configure TIMER_CH_2 */
1191 case TIMER_CH_2:
1192 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1193 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
1194 break;
1195 /* configure TIMER_CH_3 */
1196 case TIMER_CH_3:
1197 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1198 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
1199 break;
1200 default:
1201 break;
1202 }
1203 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL2_CH2EN
#define TIMER_CHCTL2_CH2EN
Definition: gd32f3x0_timer.h:174
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f3x0_timer.h:166
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL2_CH3EN
#define TIMER_CHCTL2_CH3EN
Definition: gd32f3x0_timer.h:178
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f3x0_timer.h:170
void timer_channel_remap_config | ( | uint32_t | timer_periph,
 |  | uint32_t | remap
 | ) |  |

configure TIMER channel remap function

Parameters
[in] | timer_periph | TIMERx(x=13)
[in] remap
  • TIMER13_CI0_RMP_GPIO: timer13 channel 0 input is connected to GPIO(TIMER13_CH0)
  • TIMER13_CI0_RMP_RTCCLK: timer13 channel 0 input is connected to the RTCCLK
  • TIMER13_CI0_RMP_HXTAL_DIV32: timer13 channel 0 input is connected to HXTAL/32 clock
  • TIMER13_CI0_RMP_CKOUTSEL: timer13 channel 0 input is connected to CKOUTSEL
[out] | none
Return values
none

Definition at line 1848 of file gd32f3x0_timer.c.

1849 {
1850 TIMER_IRMP(timer_periph) = (uint32_t)remap;
1851 }
TIMER_IRMP
#define TIMER_IRMP(timerx)
Definition: gd32f3x0_timer.h:50
void timer_counter_alignment | ( | uint32_t | timer_periph,
 |  | uint16_t | aligned
 | ) |  |

set TIMER counter alignment mode

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[in] aligned
  • TIMER_COUNTER_EDGE: edge-aligned mode
  • TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
  • TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
  • TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
[out] | none
Return values
none

Definition at line 191 of file gd32f3x0_timer.c.

192 {
193 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM;
194 TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
195 }
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
TIMER_CTL0_CAM
#define TIMER_CTL0_CAM
Definition: gd32f3x0_timer.h:60
void timer_counter_down_direction ( uint32_t timer_periph )

set TIMER counter down direction

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[out] | none
Return values
none

Definition at line 214 of file gd32f3x0_timer.c.

215 {
216 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
217 }
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
TIMER_CTL0_DIR
#define TIMER_CTL0_DIR
Definition: gd32f3x0_timer.h:59
uint32_t timer_counter_read ( uint32_t timer_periph )

read TIMER counter value

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
counter value

Definition at line 280 of file gd32f3x0_timer.c.

281 {
282 uint32_t count_value = 0U;
283 count_value = TIMER_CNT(timer_periph);
284 return (count_value);
285 }
TIMER_CNT
#define TIMER_CNT(timerx)
Definition: gd32f3x0_timer.h:39
void timer_counter_up_direction ( uint32_t timer_periph )

set TIMER counter up direction

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[out] | none
Return values
none

Definition at line 203 of file gd32f3x0_timer.c.

204 {
205 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
206 }
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
TIMER_CTL0_DIR
#define TIMER_CTL0_DIR
Definition: gd32f3x0_timer.h:59
void timer_counter_value_config | ( | uint32_t | timer_periph,
 |  | uint32_t | counter
 | ) |  |

configure TIMER counter register value

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[in] | counter | the counter value
[out] | none
Return values
none

Definition at line 269 of file gd32f3x0_timer.c.

270 {
271 TIMER_CNT(timer_periph) = (uint32_t)counter;
272 }
TIMER_CNT
#define TIMER_CNT(timerx)
Definition: gd32f3x0_timer.h:39
void timer_deinit ( uint32_t timer_periph )

deinit a TIMER

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_timer.c.

21 {
22 switch(timer_periph){
23 case TIMER0:
24 /* reset TIMER0 */
25 rcu_periph_reset_enable(RCU_TIMER0RST);
26 rcu_periph_reset_disable(RCU_TIMER0RST);
27 break;
28 case TIMER1:
29 /* reset TIMER1 */
30 rcu_periph_reset_enable(RCU_TIMER1RST);
31 rcu_periph_reset_disable(RCU_TIMER1RST);
32 break;
33 case TIMER2:
34 /* reset TIMER2 */
35 rcu_periph_reset_enable(RCU_TIMER2RST);
36 rcu_periph_reset_disable(RCU_TIMER2RST);
37 break;
38 #ifdef GD32F350
39 case TIMER5:
40 /* reset TIMER5 */
41 rcu_periph_reset_enable(RCU_TIMER5RST);
42 rcu_periph_reset_disable(RCU_TIMER5RST);
43 break;
44 #endif
45 case TIMER13:
46 /* reset TIMER13 */
47 rcu_periph_reset_enable(RCU_TIMER13RST);
48 rcu_periph_reset_disable(RCU_TIMER13RST);
49 break;
50 case TIMER14:
51 /* reset TIMER14 */
52 rcu_periph_reset_enable(RCU_TIMER14RST);
53 rcu_periph_reset_disable(RCU_TIMER14RST);
54 break;
55 case TIMER15:
56 /* reset TIMER15 */
57 rcu_periph_reset_enable(RCU_TIMER15RST);
58 rcu_periph_reset_disable(RCU_TIMER15RST);
59 break;
60 case TIMER16:
61 /* reset TIMER16 */
62 rcu_periph_reset_enable(RCU_TIMER16RST);
63 rcu_periph_reset_disable(RCU_TIMER16RST);
64 break;
65 default:
66 break;
67 }
68 }
TIMER0
#define TIMER0
Definition: gd32f3x0_timer.h:18
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
TIMER16
#define TIMER16
Definition: gd32f3x0_timer.h:27
TIMER14
#define TIMER14
Definition: gd32f3x0_timer.h:25
TIMER2
#define TIMER2
Definition: gd32f3x0_timer.h:20
RCU_TIMER1RST
Definition: gd32f3x0_rcu.h:344
RCU_TIMER13RST
Definition: gd32f3x0_rcu.h:346
RCU_TIMER14RST
Definition: gd32f3x0_rcu.h:339
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
TIMER15
#define TIMER15
Definition: gd32f3x0_timer.h:26
TIMER1
#define TIMER1
Definition: gd32f3x0_timer.h:19
TIMER13
#define TIMER13
Definition: gd32f3x0_timer.h:24
RCU_TIMER0RST
Definition: gd32f3x0_rcu.h:336
RCU_TIMER15RST
Definition: gd32f3x0_rcu.h:340
RCU_TIMER16RST
Definition: gd32f3x0_rcu.h:341
RCU_TIMER2RST
Definition: gd32f3x0_rcu.h:345
void timer_disable ( uint32_t timer_periph )

disable a TIMER

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
none

Definition at line 131 of file gd32f3x0_timer.c.

132 {
133 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
134 }
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
TIMER_CTL0_CEN
#define TIMER_CTL0_CEN
Definition: gd32f3x0_timer.h:55
void timer_dma_disable | ( | uint32_t | timer_periph,
 |  | uint16_t | dma
 | ) |  |

disable the TIMER DMA

Parameters
[in] | timer_periph | please refer to the following parameters
[in] dma timer DMA source enable
  • TIMER_DMA_UPD: update DMA, TIMERx(x=0..2,14..16),TIMER5 just for GD32F350
  • TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0..2,14..16)
  • TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0..2,14)
  • TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0..2)
  • TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0..2)
  • TIMER_DMA_CMTD: commutation DMA request , TIMERx(x=0,14)
  • TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0..2,14)
[out] | none
Return values
none

Definition at line 528 of file gd32f3x0_timer.c.

529 {
530 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma));
531 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f3x0_timer.h:33
void timer_dma_enable | ( | uint32_t | timer_periph,
 |  | uint16_t | dma
 | ) |  |

enable the TIMER DMA

Parameters
[in] | timer_periph | please refer to the following parameters
[in] dma timer DMA source enable
  • TIMER_DMA_UPD: update DMA, TIMERx(x=0..2,14..16),TIMER5 just for GD32F350
  • TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0..2,14..16)
  • TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0..2,14)
  • TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0..2)
  • TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0..2)
  • TIMER_DMA_CMTD: commutation DMA request, TIMERx(x=0,14)
  • TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0..2,14)
[out] | none
Return values
none

Definition at line 509 of file gd32f3x0_timer.c.

510 {
511 TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
512 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f3x0_timer.h:33
void timer_dma_transfer_config | ( | uint32_t | timer_periph,
 |  | uint32_t | dma_baseaddr,
 |  | uint32_t | dma_lenth
 | ) |  |

configure the TIMER DMA transfer

Parameters
[in] | timer_periph | TIMERx(x=0..2,14..16)
[in] dma_baseaddr
  • TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0..2,14)
  • TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0..2)
  • TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0,14..16)
  • TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0..2,14)
  • TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0..2)
  • TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0..2)
  • TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0,14..16)
  • TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB, TIMERx(x=0..2,14..16)
[in] dma_lenth
  • TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time
[out] | none
Return values
none

Definition at line 581 of file gd32f3x0_timer.c.

582 {
583 TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
584 TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
585 }
TIMER_DMACFG
#define TIMER_DMACFG(timerx)
Definition: gd32f3x0_timer.h:48
TIMER_DMACFG_DMATC
#define TIMER_DMACFG_DMATC
Definition: gd32f3x0_timer.h:224
TIMER_DMACFG_DMATA
#define TIMER_DMACFG_DMATA
Definition: gd32f3x0_timer.h:223
void timer_enable ( uint32_t timer_periph )

enable a TIMER

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
none

Definition at line 120 of file gd32f3x0_timer.c.

121 {
122 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
123 }
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
TIMER_CTL0_CEN
#define TIMER_CTL0_CEN
Definition: gd32f3x0_timer.h:55
void timer_event_software_generate | ( | uint32_t | timer_periph,
 |  | uint16_t | event
 | ) |  |

software generate events

Parameters
[in] | timer_periph | please refer to the following parameters
[in] event the timer software event generation sources
  • TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..2,13..16), TIMER5 just for GD32F350
  • TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..2,13..16)
  • TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..2,14)
  • TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..2)
  • TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..2)
  • TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,14..16)
  • TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..2,14)
  • TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 602 of file gd32f3x0_timer.c.

603 {
604 TIMER_SWEVG(timer_periph) |= (uint32_t)event;
605 }
TIMER_SWEVG
#define TIMER_SWEVG(timerx)
Definition: gd32f3x0_timer.h:35
void timer_external_clock_mode0_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extprescaler,
 |  | uint32_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER the external clock mode0

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[in] extprescaler
  • TIMER_EXT_TRI_PSC_OFF: no divided
  • TIMER_EXT_TRI_PSC_DIV2: divided by 2
  • TIMER_EXT_TRI_PSC_DIV4: divided by 4
  • TIMER_EXT_TRI_PSC_DIV8: divided by 8
[in] expolarity
  • TIMER_ETP_FALLING: active low or falling edge active
  • TIMER_ETP_RISING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1790 of file gd32f3x0_timer.c.

1792 {
1793 /* configure TIMER external trigger input */
1794 timer_external_trigger_config(timer_periph, extprescaler, expolarity, extfilter);
1795
1796 /* reset the SMC bit,TRGS bit */
1797 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
1798 /* set the SMC bit,TRGS bit */
1799 TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
1800 }
TIMER_SMCFG_TRGS
#define TIMER_SMCFG_TRGS
Definition: gd32f3x0_timer.h:81
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_TRGSEL_ETIFP
#define TIMER_SMCFG_TRGSEL_ETIFP
Definition: gd32f3x0_timer.h:518
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f3x0_timer.h:79
timer_external_trigger_config
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input
Definition: gd32f3x0_timer.c:1649
TIMER_SLAVE_MODE_EXTERNAL0
#define TIMER_SLAVE_MODE_EXTERNAL0
Definition: gd32f3x0_timer.h:540
void timer_external_clock_mode1_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extprescaler,
 |  | uint32_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER the external clock mode1

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[in] extprescaler
  • TIMER_EXT_TRI_PSC_OFF: no divided
  • TIMER_EXT_TRI_PSC_DIV2: divided by 2
  • TIMER_EXT_TRI_PSC_DIV4: divided by 4
  • TIMER_EXT_TRI_PSC_DIV8: divided by 8
[in] expolarity
  • TIMER_ETP_FALLING: active low or falling edge active
  • TIMER_ETP_RISING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1817 of file gd32f3x0_timer.c.

1819 {
1820 /* configure TIMER external trigger input */
1821 timer_external_trigger_config(timer_periph, extprescaler, expolarity, extfilter);
1822
1823 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
1824 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_SMC1
#define TIMER_SMCFG_SMC1
Definition: gd32f3x0_timer.h:85
timer_external_trigger_config
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input
Definition: gd32f3x0_timer.c:1649
void timer_external_clock_mode1_disable ( uint32_t timer_periph )

disable TIMER the external clock mode1

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[out] | none
Return values
none

Definition at line 1832 of file gd32f3x0_timer.c.

1833 {
1834 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
1835 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_SMC1
#define TIMER_SMCFG_SMC1
Definition: gd32f3x0_timer.h:85
void timer_external_trigger_as_external_clock_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extrigger,
 |  | uint16_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER the external trigger as external clock input

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[in] extrigger
  • TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 Edge Detector
  • TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
  • TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
[in] expolarity
  • TIMER_IC_POLARITY_RISING: active low or falling edge active
  • TIMER_IC_POLARITY_FALLING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1729 of file gd32f3x0_timer.c.

1731 {
1732 if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
1733 /* reset the CH1EN bit */
1734 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1735 /* reset the CH1NP bit */
1736 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1737 /* set the CH1NP bit */
1738 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)expolarity << 4U);
1739 /* reset the CH1MS bit */
1740 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1741 /* set the CH1MS bit */
1742 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U);
1743 /* reset the CH1CAPFLT bit */
1744 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1745 /* set the CH1CAPFLT bit */
1746 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U);
1747 /* set the CH1EN bit */
1748 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1749 }else{
1750 /* reset the CH0EN bit */
1751 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1752 /* reset the CH0P and CH0NP bits */
1753 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1754 /* set the CH0P and CH0NP bits */
1755 TIMER_CHCTL2(timer_periph) |= (uint32_t)expolarity;
1756 /* reset the CH0MS bit */
1757 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1758 /* set the CH0MS bit */
1759 TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
1760 /* reset the CH0CAPFLT bit */
1761 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1762 /* reset the CH0CAPFLT bit */
1763 TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter;
1764 /* set the CH0EN bit */
1765 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1766 }
1767 /* select TIMER input trigger source */
1768 timer_input_trigger_source_select(timer_periph,extrigger);
1769 /* reset the SMC bit */
1770 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1771 /* set the SMC bit */
1772 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1773 }
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f3x0_timer.h:171
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f3x0_timer.h:173
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f3x0_timer.h:169
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f3x0_timer.h:166
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f3x0_timer.h:167
TIMER_CHCTL0_CH0CAPFLT
#define TIMER_CHCTL0_CH0CAPFLT
Definition: gd32f3x0_timer.h:143
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f3x0_timer.h:79
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
timer_input_trigger_source_select
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source
Definition: gd32f3x0_timer.c:1565
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f3x0_timer.h:131
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f3x0_timer.h:170
TIMER_CHCTL0_CH1CAPFLT
#define TIMER_CHCTL0_CH1CAPFLT
Definition: gd32f3x0_timer.h:145
TIMER_SMCFG_TRGSEL_CI1FE1
#define TIMER_SMCFG_TRGSEL_CI1FE1
Definition: gd32f3x0_timer.h:517
TIMER_IC_SELECTION_DIRECTTI
#define TIMER_IC_SELECTION_DIRECTTI
Definition: gd32f3x0_timer.h:499
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f3x0_timer.h:136
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
TIMER_SLAVE_MODE_EXTERNAL0
#define TIMER_SLAVE_MODE_EXTERNAL0
Definition: gd32f3x0_timer.h:540
void timer_external_trigger_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extprescaler,
 |  | uint32_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER external trigger input

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[in] extprescaler
  • TIMER_EXT_TRI_PSC_OFF: no divided
  • TIMER_EXT_TRI_PSC_DIV2: divided by 2
  • TIMER_EXT_TRI_PSC_DIV4: divided by 4
  • TIMER_EXT_TRI_PSC_DIV8: divided by 8
[in] expolarity
  • TIMER_ETP_FALLING: active low or falling edge active
  • TIMER_ETP_RISING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1649 of file gd32f3x0_timer.c.

1651 {
1652 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC));
1653 TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | expolarity);
1654 TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U);
1655 }
TIMER_SMCFG_ETPSC
#define TIMER_SMCFG_ETPSC
Definition: gd32f3x0_timer.h:84
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_ETP
#define TIMER_SMCFG_ETP
Definition: gd32f3x0_timer.h:86
TIMER_SMCFG_ETFC
#define TIMER_SMCFG_ETFC
Definition: gd32f3x0_timer.h:83
void timer_flag_clear | ( | uint32_t | timer_periph,
 |  | uint32_t | flag
 | ) |  |

clear TIMER flags

Parameters
[in] | timer_periph | please refer to the following parameters
[in] flag the timer interrupt flags
  • TIMER_FLAG_UP: update flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
  • TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..2,13..16)
  • TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..2,14)
  • TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..2)
  • TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..2)
  • TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16)
  • TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..2,14)
  • TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16)
  • TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..2,13..16)
  • TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..2,14)
  • TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..2)
  • TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..2)
[out] | none
Return values
none

Definition at line 490 of file gd32f3x0_timer.c.

491 {
492 TIMER_INTF(timer_periph) &= (~(uint32_t)flag);
493 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f3x0_timer.h:34
FlagStatus timer_flag_get | ( | uint32_t | timer_periph,
 |  | uint32_t | flag
 | ) |  |

get TIMER flags

Parameters
[in] | timer_periph | please refer to the following parameters
[in] flag the timer interrupt flags
  • TIMER_FLAG_UP: update flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
  • TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..2,13..16)
  • TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..2,14)
  • TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..2)
  • TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..2)
  • TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16)
  • TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..2,14)
  • TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16)
  • TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..2,13..16)
  • TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..2,14)
  • TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..2)
  • TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..2)
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 462 of file gd32f3x0_timer.c.

463 {
464 if(RESET != (TIMER_INTF(timer_periph) & flag)){
465 return SET;
466 }else{
467 return RESET;
468 }
469 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f3x0_timer.h:34
void timer_hall_mode_config | ( | uint32_t | timer_periph,
 |  | uint8_t | hallmode
 | ) |  |

configure TIMER hall sensor mode

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[in] hallmode
  • TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
  • TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
[out] | none
Return values
none

Definition at line 1541 of file gd32f3x0_timer.c.

1542 {
1543 if(TIMER_HALLINTERFACE_ENABLE == hallmode){
1544 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
1545 }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
1546 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
1547 }else{
1548 }
1549 }
TIMER_CTL1_TI0S
#define TIMER_CTL1_TI0S
Definition: gd32f3x0_timer.h:69
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f3x0_timer.h:31
TIMER_HALLINTERFACE_ENABLE
#define TIMER_HALLINTERFACE_ENABLE
Definition: gd32f3x0_timer.h:562
TIMER_HALLINTERFACE_DISABLE
#define TIMER_HALLINTERFACE_DISABLE
Definition: gd32f3x0_timer.h:563
void timer_init | ( | uint32_t | timer_periph,
 |  | timer_parameter_struct * | initpara
 | ) |  |

initialize TIMER counter

Parameters
[in] | periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[in] | timer_initpara | init parameter struct prescaler: prescaler value of the counter clock,0~65535 alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN period: counter auto reload value,(TIMER1 32 bit) clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 repetitioncounter: counter repetition value,0~255
[out] | none
Return values
none

Definition at line 83 of file gd32f3x0_timer.c.

84 {
85 /* configure the counter prescaler value */
86 TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
87
88 /* configure the counter direction and aligned mode */
89 if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph)){
90 TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM);
91 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode;
92 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection;
93 }
94
95 /* configure the autoreload value */
96 TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
97
98 if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER13 == timer_periph)
99 || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){
100 /* reset the CKDIV bit */
101 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV;
102 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision;
103 }
104
105 if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){
106 /* configure the repetition counter value */
107 TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
108 }
109
110 /* generate an update event */
111 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
112 }
TIMER0
#define TIMER0
Definition: gd32f3x0_timer.h:18
TIMER16
#define TIMER16
Definition: gd32f3x0_timer.h:27
TIMER_CAR
#define TIMER_CAR(timerx)
Definition: gd32f3x0_timer.h:41
TIMER_SWEVG_UPG
#define TIMER_SWEVG_UPG
Definition: gd32f3x0_timer.h:120
TIMER14
#define TIMER14
Definition: gd32f3x0_timer.h:25
TIMER_CTL0_CKDIV
#define TIMER_CTL0_CKDIV
Definition: gd32f3x0_timer.h:62
TIMER2
#define TIMER2
Definition: gd32f3x0_timer.h:20
TIMER_PSC
#define TIMER_PSC(timerx)
Definition: gd32f3x0_timer.h:40
TIMER_CREP
#define TIMER_CREP(timerx)
Definition: gd32f3x0_timer.h:42
timer_parameter_struct::clockdivision
uint16_t clockdivision
Definition: gd32f3x0_timer.h:244
TIMER15
#define TIMER15
Definition: gd32f3x0_timer.h:26
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
TIMER1
#define TIMER1
Definition: gd32f3x0_timer.h:19
TIMER_SWEVG
#define TIMER_SWEVG(timerx)
Definition: gd32f3x0_timer.h:35
TIMER13
#define TIMER13
Definition: gd32f3x0_timer.h:24
TIMER_CTL0_CAM
#define TIMER_CTL0_CAM
Definition: gd32f3x0_timer.h:60
timer_parameter_struct::repetitioncounter
uint8_t repetitioncounter
Definition: gd32f3x0_timer.h:245
TIMER_CTL0_DIR
#define TIMER_CTL0_DIR
Definition: gd32f3x0_timer.h:59
timer_parameter_struct::prescaler
uint16_t prescaler
Definition: gd32f3x0_timer.h:240
timer_parameter_struct::period
uint32_t period
Definition: gd32f3x0_timer.h:243
timer_parameter_struct::alignedmode
uint16_t alignedmode
Definition: gd32f3x0_timer.h:241
timer_parameter_struct::counterdirection
uint16_t counterdirection
Definition: gd32f3x0_timer.h:242
void timer_input_capture_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | timer_ic_parameter_struct * | icpara
 | ) |  |

configure TIMER input capture parameter

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] | icpara | TIMER channel intput parameter struct icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 icfilter: 0~15
[out] | none
Return values
none

Definition at line 1257 of file gd32f3x0_timer.c.

1258 {
1259 switch(channel){
1260 /* configure TIMER_CH_0 */
1261 case TIMER_CH_0:
1262 /* reset the CH0EN bit */
1263 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1264
1265 /* reset the CH0P and CH0NP bits */
1266 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1267 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
1268 /* reset the CH0MS bit */
1269 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1270 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
1271 /* reset the CH0CAPFLT bit */
1272 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1273 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1274
1275 /* set the CH0EN bit */
1276 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1277 break;
1278
1279 /* configure TIMER_CH_1 */
1280 case TIMER_CH_1:
1281 /* reset the CH1EN bit */
1282 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1283
1284 /* reset the CH1P and CH1NP bits */
1285 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1286 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U);
1287 /* reset the CH1MS bit */
1288 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1289 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1290 /* reset the CH1CAPFLT bit */
1291 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1292 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1293
1294 /* set the CH1EN bit */
1295 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1296 break;
1297 /* configure TIMER_CH_2 */
1298 case TIMER_CH_2:
1299 /* reset the CH2EN bit */
1300 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1301
1302 /* reset the CH2P and CH2NP bits */
1303 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP));
1304 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U);
1305
1306 /* reset the CH2MS bit */
1307 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
1308 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection));
1309
1310 /* reset the CH2CAPFLT bit */
1311 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
1312 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1313
1314 /* set the CH2EN bit */
1315 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
1316 break;
1317 /* configure TIMER_CH_3 */
1318 case TIMER_CH_3:
1319 /* reset the CH3EN bit */
1320 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1321
1322 /* reset the CH3P and CH3NP bits */
1323 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P|TIMER_CHCTL2_CH3NP));
1324 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U);
1325
1326 /* reset the CH3MS bit */
1327 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
1328 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1329
1330 /* reset the CH3CAPFLT bit */
1331 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
1332 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1333
1334 /* set the CH3EN bit */
1335 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
1336 break;
1337 default:
1338 break;
1339 }
1340 /* configure TIMER channel input capture prescaler value */
1341 timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler));
1342 }
timer_channel_input_capture_prescaler_config
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value
Definition: gd32f3x0_timer.c:1360
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f3x0_timer.h:171
timer_ic_parameter_struct::icselection
uint16_t icselection
Definition: gd32f3x0_timer.h:275
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CHCTL1_CH3MS
#define TIMER_CHCTL1_CH3MS
Definition: gd32f3x0_timer.h:154
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL2_CH3NP
#define TIMER_CHCTL2_CH3NP
Definition: gd32f3x0_timer.h:180
TIMER_CHCTL1_CH3CAPFLT
#define TIMER_CHCTL1_CH3CAPFLT
Definition: gd32f3x0_timer.h:163
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f3x0_timer.h:173
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f3x0_timer.h:169
TIMER_CHCTL1_CH2MS
#define TIMER_CHCTL1_CH2MS
Definition: gd32f3x0_timer.h:149
TIMER_CHCTL2_CH2EN
#define TIMER_CHCTL2_CH2EN
Definition: gd32f3x0_timer.h:174
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f3x0_timer.h:166
timer_ic_parameter_struct::icprescaler
uint16_t icprescaler
Definition: gd32f3x0_timer.h:276
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f3x0_timer.h:167
TIMER_CHCTL0_CH0CAPFLT
#define TIMER_CHCTL0_CH0CAPFLT
Definition: gd32f3x0_timer.h:143
TIMER_CHCTL2_CH3EN
#define TIMER_CHCTL2_CH3EN
Definition: gd32f3x0_timer.h:178
TIMER_CHCTL2_CH2P
#define TIMER_CHCTL2_CH2P
Definition: gd32f3x0_timer.h:175
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
timer_ic_parameter_struct::icpolarity
uint16_t icpolarity
Definition: gd32f3x0_timer.h:274
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f3x0_timer.h:131
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f3x0_timer.h:170
TIMER_CHCTL2_CH3P
#define TIMER_CHCTL2_CH3P
Definition: gd32f3x0_timer.h:179
TIMER_CHCTL0_CH1CAPFLT
#define TIMER_CHCTL0_CH1CAPFLT
Definition: gd32f3x0_timer.h:145
TIMER_CHCTL2_CH2NP
#define TIMER_CHCTL2_CH2NP
Definition: gd32f3x0_timer.h:177
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f3x0_timer.h:136
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
TIMER_CHCTL1_CH2CAPFLT
#define TIMER_CHCTL1_CH2CAPFLT
Definition: gd32f3x0_timer.h:161
timer_ic_parameter_struct::icfilter
uint16_t icfilter
Definition: gd32f3x0_timer.h:277
void timer_input_pwm_capture_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | timer_ic_parameter_struct * | icpwm
 | ) |  |

configure TIMER input pwm capture function

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[in] channel
  • TIMER_CH_0: TIMER channel0
  • TIMER_CH_1: TIMER channel1
[in] | icpwm:TIMER | channel intput pwm parameter struct icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 icfilter: 0~15
[out] | none
Return values
none

Definition at line 1436 of file gd32f3x0_timer.c.

1437 {
1438 uint16_t icpolarity = 0x0U;
1439 uint16_t icselection = 0x0U;
1440
1441 if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
1442 icpolarity = TIMER_IC_POLARITY_FALLING;
1443 }else{
1444 icpolarity = TIMER_IC_POLARITY_RISING;
1445 }
1446
1447 if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
1448 icselection = TIMER_IC_SELECTION_INDIRECTTI;
1449 }else{
1450 icselection = TIMER_IC_SELECTION_DIRECTTI;
1451 }
1452
1453 if(TIMER_CH_0 == channel){
1454 /* reset the CH0EN bit */
1455 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1456 /* reset the CH0P and CH0NP bits */
1457 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1458 /* set the CH0P and CH0NP bits */
1459 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
1460 /* reset the CH0MS bit */
1461 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1462 /* set the CH0MS bit */
1463 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
1464 /* reset the CH0CAPFLT bit */
1465 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1466 /* set the CH0CAPFLT bit */
1467 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1468 /* set the CH0EN bit */
1469 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1470 /* configure TIMER channel input capture prescaler value */
1471 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler));
1472
1473 /* reset the CH1EN bit */
1474 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1475 /* reset the CH1P and CH1NP bits */
1476 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1477 /* set the CH1P and CH1NP bits */
1478 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U);
1479 /* reset the CH1MS bit */
1480 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1481 /* set the CH1MS bit */
1482 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U);
1483 /* reset the CH1CAPFLT bit */
1484 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1485 /* set the CH1CAPFLT bit */
1486 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1487 /* set the CH1EN bit */
1488 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1489 /* configure TIMER channel input capture prescaler value */
1490 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler));
1491 }else{
1492 /* reset the CH1EN bit */
1493 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1494 /* reset the CH1P and CH1NP bits */
1495 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1496 /* set the CH1P and CH1NP bits */
1497 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U);
1498 /* reset the CH1MS bit */
1499 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1500 /* set the CH1MS bit */
1501 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U);
1502 /* reset the CH1CAPFLT bit */
1503 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1504 /* set the CH1CAPFLT bit */
1505 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1506 /* set the CH1EN bit */
1507 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1508 /* configure TIMER channel input capture prescaler value */
1509 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
1510
1511 /* reset the CH0EN bit */
1512 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1513 /* reset the CH0P and CH0NP bits */
1514 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1515 /* set the CH0P and CH0NP bits */
1516 TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
1517 /* reset the CH0MS bit */
1518 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1519 /* set the CH0MS bit */
1520 TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
1521 /* reset the CH0CAPFLT bit */
1522 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1523 /* set the CH0CAPFLT bit */
1524 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1525 /* set the CH0EN bit */
1526 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1527 /* configure TIMER channel input capture prescaler value */
1528 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
1529 }
1530 }
TIMER_IC_POLARITY_RISING
#define TIMER_IC_POLARITY_RISING
Definition: gd32f3x0_timer.h:494
timer_channel_input_capture_prescaler_config
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value
Definition: gd32f3x0_timer.c:1360
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f3x0_timer.h:171
timer_ic_parameter_struct::icselection
uint16_t icselection
Definition: gd32f3x0_timer.h:275
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f3x0_timer.h:173
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f3x0_timer.h:169
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f3x0_timer.h:166
timer_ic_parameter_struct::icprescaler
uint16_t icprescaler
Definition: gd32f3x0_timer.h:276
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f3x0_timer.h:167
TIMER_CHCTL0_CH0CAPFLT
#define TIMER_CHCTL0_CH0CAPFLT
Definition: gd32f3x0_timer.h:143
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_IC_SELECTION_INDIRECTTI
#define TIMER_IC_SELECTION_INDIRECTTI
Definition: gd32f3x0_timer.h:500
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
timer_ic_parameter_struct::icpolarity
uint16_t icpolarity
Definition: gd32f3x0_timer.h:274
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f3x0_timer.h:131
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f3x0_timer.h:170
TIMER_CHCTL0_CH1CAPFLT
#define TIMER_CHCTL0_CH1CAPFLT
Definition: gd32f3x0_timer.h:145
TIMER_IC_SELECTION_DIRECTTI
#define TIMER_IC_SELECTION_DIRECTTI
Definition: gd32f3x0_timer.h:499
TIMER_IC_POLARITY_FALLING
#define TIMER_IC_POLARITY_FALLING
Definition: gd32f3x0_timer.h:495
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f3x0_timer.h:136
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
timer_ic_parameter_struct::icfilter
uint16_t icfilter
Definition: gd32f3x0_timer.h:277
void timer_input_trigger_source_select | ( | uint32_t | timer_periph,
 |  | uint32_t | intrigger
 | ) |  |

select TIMER input trigger source

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[in] intrigger
  • TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..2,14))
  • TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..2,14))
  • TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..2))
  • TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 Edge Detector(TIMERx(x=0..2,14))
  • TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..2,14))
  • TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..2,14))
  • TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0..2))
[out] | none
Return values
none

Definition at line 1565 of file gd32f3x0_timer.c.

1566 {
1567 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
1568 TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
1569 }
TIMER_SMCFG_TRGS
#define TIMER_SMCFG_TRGS
Definition: gd32f3x0_timer.h:81
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
void timer_internal_clock_config ( uint32_t timer_periph )

configure TIMER internal clock mode

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[out] | none
Return values
none

Definition at line 1693 of file gd32f3x0_timer.c.

1694 {
1695 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1696 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f3x0_timer.h:79
void timer_internal_trigger_as_external_clock_config | ( | uint32_t | timer_periph,
 |  | uint32_t | intrigger
 | ) |  |

configure TIMER the internal trigger as external clock input

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[in] intrigger
  • TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..2,14))
  • TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..2,14))
  • TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..2))
[out] | none
Return values
none

Definition at line 1708 of file gd32f3x0_timer.c.

1709 {
1710 timer_input_trigger_source_select(timer_periph, intrigger);
1711 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1712 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1713 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f3x0_timer.h:79
timer_input_trigger_source_select
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source
Definition: gd32f3x0_timer.c:1565
TIMER_SLAVE_MODE_EXTERNAL0
#define TIMER_SLAVE_MODE_EXTERNAL0
Definition: gd32f3x0_timer.h:540
void timer_interrupt_disable | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

disable the TIMER interrupt

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt timer interrupt source enable
  • TIMER_INT_UP: update interrupt enable, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
  • TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..2,13..16)
  • TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..2,14)
  • TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..2)
  • TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..2)
  • TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,14..16)
  • TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..2,14)
  • TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 392 of file gd32f3x0_timer.c.

393 {
394 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
395 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f3x0_timer.h:33
void timer_interrupt_enable | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

enable the TIMER interrupt

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt timer interrupt enable source
  • TIMER_INT_UP: update interrupt enable, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
  • TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..2,13..16)
  • TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..2,14)
  • TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..2)
  • TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..2)
  • TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,14..16)
  • TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..2,14)
  • TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 372 of file gd32f3x0_timer.c.

373 {
374 TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
375 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f3x0_timer.h:33
void timer_interrupt_flag_clear | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

clear TIMER interrupt flag

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt the timer interrupt bits
  • TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
  • TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..2,13..16)
  • TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..2,14)
  • TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..2)
  • TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..2)
  • TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,14..16)
  • TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0..2,14)
  • TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 438 of file gd32f3x0_timer.c.

439 {
440 TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt);
441 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f3x0_timer.h:34
FlagStatus timer_interrupt_flag_get | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

get timer interrupt flag

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt the timer interrupt bits
  • TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
  • TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..2,13..16)
  • TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..2,14)
  • TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..2)
  • TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..2)
  • TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,14..16)
  • TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0..2,14)
  • TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,14..16)
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 412 of file gd32f3x0_timer.c.

413 {
414 uint32_t val;
415 val = (TIMER_DMAINTEN(timer_periph) & interrupt);
416 if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){
417 return SET;
418 }else{
419 return RESET;
420 }
421 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f3x0_timer.h:34
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f3x0_timer.h:33
void timer_master_output_trigger_source_select | ( | uint32_t | timer_periph,
 |  | uint32_t | outrigger
 | ) |  |

select TIMER master mode output trigger source

Parameters
[in] | timer_periph | TIMERx(x=0..2,14),TIMER5 just for GD32F350
[in] outrigger
  • TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350)
  • TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350)
  • TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350)
  • TIMER_TRI_OUT_SRC_CC0: a capture or a compare match occurred in channal0 as trigger output TRGO
  • TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..2,14))
  • TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..2,14))
  • TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..2,14))
  • TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..2,14))
[out] | none
Return values
none

Definition at line 1586 of file gd32f3x0_timer.c.

1587 {
1588 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
1589 TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
1590 }
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f3x0_timer.h:31
TIMER_CTL1_MMC
#define TIMER_CTL1_MMC
Definition: gd32f3x0_timer.h:68
void timer_master_slave_mode_config | ( | uint32_t | timer_periph,
 |  | uint8_t | masterslave
 | ) |  |

configure TIMER master slave mode

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[in] masterslave
  • TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
  • TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
[out] | none
Return values
none

Definition at line 1624 of file gd32f3x0_timer.c.

1625 {
1626 if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
1627 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
1628 }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
1629 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
1630 }else{
1631 }
1632 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_MASTER_SLAVE_MODE_ENABLE
#define TIMER_MASTER_SLAVE_MODE_ENABLE
Definition: gd32f3x0_timer.h:547
TIMER_MASTER_SLAVE_MODE_DISABLE
#define TIMER_MASTER_SLAVE_MODE_DISABLE
Definition: gd32f3x0_timer.h:548
TIMER_SMCFG_MSM
#define TIMER_SMCFG_MSM
Definition: gd32f3x0_timer.h:82
void timer_ocpre_clear_source_config | ( | uint32_t | timer_periph,
 |  | uint8_t | ocpreclear
 | ) |  |

configure TIMER OCPRE clear source selection

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[in] ocpreclear
  • TIMER_OCPRE_CLEAR_SOURCE_CLR: OCPRE_CLR_INT is connected to the OCPRE_CLR input
  • TIMER_OCPRE_CLEAR_SOURCE_ETIF: OCPRE_CLR_INT is connected to ETIF
[out] | none
Return values
none

Definition at line 347 of file gd32f3x0_timer.c.

348 {
349 if(TIMER_OCPRE_CLEAR_SOURCE_ETIF == ocpreclear){
350 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_OCRC;
351 }else if(TIMER_OCPRE_CLEAR_SOURCE_CLR == ocpreclear){
352 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_OCRC;
353 }else{
354 }
355 }
TIMER_SMCFG_OCRC
#define TIMER_SMCFG_OCRC
Definition: gd32f3x0_timer.h:80
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_OCPRE_CLEAR_SOURCE_ETIF
#define TIMER_OCPRE_CLEAR_SOURCE_ETIF
Definition: gd32f3x0_timer.h:544
TIMER_OCPRE_CLEAR_SOURCE_CLR
#define TIMER_OCPRE_CLEAR_SOURCE_CLR
Definition: gd32f3x0_timer.h:543
void timer_output_value_selection_config | ( | uint32_t | timer_periph,
 |  | uint16_t | outsel
 | ) |  |

configure TIMER output value selection

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[in] outsel
  • TIMER_OUTSEL_DISABLE: no effect
  • TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled
[out] | none
Return values
none

Definition at line 1881 of file gd32f3x0_timer.c.

1882 {
1883 if(TIMER_OUTSEL_ENABLE == outsel){
1884 TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL;
1885 }else if(TIMER_OUTSEL_DISABLE == outsel){
1886 TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL;
1887 }else{
1888 }
1889 }
TIMER_OUTSEL_ENABLE
#define TIMER_OUTSEL_ENABLE
Definition: gd32f3x0_timer.h:571
TIMER_CFG
#define TIMER_CFG(timerx)
Definition: gd32f3x0_timer.h:51
TIMER_OUTSEL_DISABLE
#define TIMER_OUTSEL_DISABLE
Definition: gd32f3x0_timer.h:570
TIMER_CFG_OUTSEL
#define TIMER_CFG_OUTSEL
Definition: gd32f3x0_timer.h:233
void timer_prescaler_config | ( | uint32_t | timer_periph,
 |  | uint16_t | prescaler,
 |  | uint8_t | pscreload
 | ) |  |

configure TIMER prescaler

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[in] | prescaler | prescaler value
[in] pscreload prescaler reload mode
  • TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
  • TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
[out] | none
Return values
none

Definition at line 229 of file gd32f3x0_timer.c.

230 {
231 TIMER_PSC(timer_periph) = (uint32_t)prescaler;
232
233 if(TIMER_PSC_RELOAD_NOW == pscreload){
234 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
235 }
236 }
TIMER_SWEVG_UPG
#define TIMER_SWEVG_UPG
Definition: gd32f3x0_timer.h:120
TIMER_PSC_RELOAD_NOW
#define TIMER_PSC_RELOAD_NOW
Definition: gd32f3x0_timer.h:389
TIMER_PSC
#define TIMER_PSC(timerx)
Definition: gd32f3x0_timer.h:40
TIMER_SWEVG
#define TIMER_SWEVG(timerx)
Definition: gd32f3x0_timer.h:35
uint16_t timer_prescaler_read ( uint32_t timer_periph )

read TIMER prescaler value

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
prescaler register value

Definition at line 293 of file gd32f3x0_timer.c.

294 {
295 uint16_t prescaler_value = 0U;
296 prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
297 return (prescaler_value);
298 }
TIMER_PSC
#define TIMER_PSC(timerx)
Definition: gd32f3x0_timer.h:40
void timer_primary_output_config | ( | uint32_t | timer_periph,
 |  | ControlStatus | newvalue
 | ) |  |

configure TIMER primary output function

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 683 of file gd32f3x0_timer.c.

684 {
685 if(ENABLE == newvalue){
686 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
687 }else{
688 TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
689 }
690 }
TIMER_CCHP_POEN
#define TIMER_CCHP_POEN
Definition: gd32f3x0_timer.h:220
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f3x0_timer.h:47
void timer_quadrature_decoder_mode_config | ( | uint32_t | timer_periph,
 |  | uint32_t | decomode,
 |  | uint16_t | ic0polarity,
 |  | uint16_t | ic1polarity
 | ) |  |

configure TIMER quadrature decoder mode

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[in] decomode
  • TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
  • TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
  • TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
[in] ic0polarity
  • TIMER_IC_POLARITY_RISING: capture rising edge
  • TIMER_IC_POLARITY_FALLING: capture falling edge
[in] ic1polarity
  • TIMER_IC_POLARITY_RISING: capture rising edge
  • TIMER_IC_POLARITY_FALLING: capture falling edge
[out] | none
Return values
none

Definition at line 1673 of file gd32f3x0_timer.c.

1675 {
1676 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1677 TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
1678
1679 TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS)));
1680 TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U));
1681
1682 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1683 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1684 TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity << 4U));
1685 }
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f3x0_timer.h:171
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f3x0_timer.h:173
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f3x0_timer.h:169
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f3x0_timer.h:167
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f3x0_timer.h:79
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f3x0_timer.h:131
TIMER_IC_SELECTION_DIRECTTI
#define TIMER_IC_SELECTION_DIRECTTI
Definition: gd32f3x0_timer.h:499
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f3x0_timer.h:136
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
void timer_repetition_value_config | ( | uint32_t | timer_periph,
 |  | uint16_t | repetition
 | ) |  |

configure TIMER repetition register value

Parameters
[in] | timer_periph | TIMERx(x=0,15,16)
[in] | repetition | the counter repetition value,0~255
[out] | none
Return values
none

Definition at line 245 of file gd32f3x0_timer.c.

246 {
247 TIMER_CREP(timer_periph) = (uint32_t)repetition;
248 }
TIMER_CREP
#define TIMER_CREP(timerx)
Definition: gd32f3x0_timer.h:42
void timer_single_pulse_mode_config | ( | uint32_t | timer_periph,
 |  | uint8_t | spmode
 | ) |  |

configure TIMER single pulse mode

Parameters
[in] | timer_periph | TIMERx(x=0..2,14..16),TIMER5 just for GD32F350
[in] spmode
  • TIMER_SP_MODE_SINGLE: single pulse mode
  • TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
[out] | none
Return values
none

Definition at line 309 of file gd32f3x0_timer.c.

310 {
311 if(TIMER_SP_MODE_SINGLE == spmode){
312 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
313 }else if(TIMER_SP_MODE_REPETITIVE == spmode){
314 TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
315 }else{
316 }
317 }
TIMER_SP_MODE_REPETITIVE
#define TIMER_SP_MODE_REPETITIVE
Definition: gd32f3x0_timer.h:404
TIMER_SP_MODE_SINGLE
#define TIMER_SP_MODE_SINGLE
Definition: gd32f3x0_timer.h:403
TIMER_CTL0_SPM
#define TIMER_CTL0_SPM
Definition: gd32f3x0_timer.h:58
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
void timer_slave_mode_select | ( | uint32_t | timer_periph,
 |  | uint32_t | slavemode
 | ) |  |

select TIMER slave mode

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[in] slavemode
  • TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..2,14))
  • TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..2))
  • TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..2))
  • TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..2))
  • TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..2,14))
  • TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..2,14))
  • TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..2,14))
  • TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0(TIMERx(x=0..2,14))
[out] | none
Return values
none

Definition at line 1608 of file gd32f3x0_timer.c.

1609 {
1610 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1611
1612 TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
1613 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f3x0_timer.h:79
void timer_update_event_disable ( uint32_t timer_periph )

disable the update event

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
none

Definition at line 175 of file gd32f3x0_timer.c.

176 {
177 TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
178 }
TIMER_CTL0_UPDIS
#define TIMER_CTL0_UPDIS
Definition: gd32f3x0_timer.h:56
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
void timer_update_event_enable ( uint32_t timer_periph )

enable the update event

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
none

Definition at line 164 of file gd32f3x0_timer.c.

165 {
166 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
167 }
TIMER_CTL0_UPDIS
#define TIMER_CTL0_UPDIS
Definition: gd32f3x0_timer.h:56
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
void timer_update_source_config | ( | uint32_t | timer_periph,
 |  | uint8_t | update
 | ) |  |

configure TIMER update source

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[in] update
  • TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger
  • TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
[out] | none
Return values
none

Definition at line 328 of file gd32f3x0_timer.c.

329 {
330 if(TIMER_UPDATE_SRC_REGULAR == update){
331 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
332 }else if(TIMER_UPDATE_SRC_GLOBAL == update){
333 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
334 }else{
335 }
336 }
TIMER_UPDATE_SRC_REGULAR
#define TIMER_UPDATE_SRC_REGULAR
Definition: gd32f3x0_timer.h:407
TIMER_CTL0_UPS
#define TIMER_CTL0_UPS
Definition: gd32f3x0_timer.h:57
TIMER_UPDATE_SRC_GLOBAL
#define TIMER_UPDATE_SRC_GLOBAL
Definition: gd32f3x0_timer.h:408
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
void timer_write_cc_register_config | ( | uint32_t | timer_periph,
 |  | uint16_t | ccsel
 | ) |  |

configure TIMER write CHxVAL register selection

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16)
[in] ccsel
  • TIMER_CCSEL_DISABLE: no effect
  • TIMER_CCSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored
[out] | none
Return values
none

Definition at line 1862 of file gd32f3x0_timer.c.

1863 {
1864 if(TIMER_CCSEL_ENABLE == ccsel){
1865 TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL;
1866 }else if(TIMER_CCSEL_DISABLE == ccsel){
1867 TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL;
1868 }else{
1869 }
1870 }
TIMER_CFG_CHVSEL
#define TIMER_CFG_CHVSEL
Definition: gd32f3x0_timer.h:234
TIMER_CCSEL_ENABLE
#define TIMER_CCSEL_ENABLE
Definition: gd32f3x0_timer.h:567
TIMER_CFG
#define TIMER_CFG(timerx)
Definition: gd32f3x0_timer.h:51
TIMER_CCSEL_DISABLE
#define TIMER_CCSEL_DISABLE
Definition: gd32f3x0_timer.h:566
Generated on Tue Jun 27 2017 14:36:12 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_tsi.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Functions
gd32f3x0_tsi.h File Reference

definitions for the TSI More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | TSI TSI_BASE
#define | TSI_CTL0 REG32(TSI + 0x00U)
#define | TSI_INTEN REG32(TSI + 0x04U)
#define | TSI_INTC REG32(TSI + 0x08U)
#define | TSI_INTF REG32(TSI + 0x0CU)
#define | TSI_PHM REG32(TSI + 0x10U)
#define | TSI_ASW REG32(TSI + 0x18U)
#define | TSI_SAMPCFG REG32(TSI + 0x20U)
#define | TSI_CHCFG REG32(TSI + 0x28U)
#define | TSI_GCTL REG32(TSI + 0x30U)
#define | TSI_G0CYCN REG32(TSI + 0x34U)
#define | TSI_G1CYCN REG32(TSI + 0x38U)
#define | TSI_G2CYCN REG32(TSI + 0x3CU)
#define | TSI_G3CYCN REG32(TSI + 0x40U)
#define | TSI_G4CYCN REG32(TSI + 0x44U)
#define | TSI_G5CYCN REG32(TSI + 0x48U)
#define | TSI_CTL1 REG32(TSI + 0x300U)
#define | TSI_CTL0_TSIEN BIT(0)
#define | TSI_CTL0_TSIS BIT(1)
#define | TSI_CTL0_TRGMOD BIT(2)
#define | TSI_CTL0_EGSEL BIT(3)
#define | TSI_CTL0_PINMOD BIT(4)
#define | TSI_CTL0_MCN BITS(5,7)
#define | TSI_CTL0_CTCDIV BITS(12,14)
#define | TSI_CTL0_ECDIV BIT(15)
#define | TSI_CTL0_ECEN BIT(16)
#define | TSI_CTL0_ECDT BITS(17,23)
#define | TSI_CTL0_CTDT BITS(24,27)
#define | TSI_CTL0_CDT BITS(28,31)
#define | TSI_INTEN_CTCFIE BIT(0)
#define | TSI_INTEN_MNERRIE BIT(1)
#define | TSI_INTC_CCTCF BIT(0)
#define | TSI_INTC_CMNERR BIT(1)
#define | TSI_INTF_CTCF BIT(0)
#define | TSI_INTF_MNERR BIT(1)
#define | TSI_INT_CCTCF TSI_INTEN_CTCFIE
#define | TSI_INT_MNERR TSI_INTEN_MNERRIE
#define | TSI_INT_FLAG_CTCF TSI_INTF_CTCF
#define | TSI_INT_FLAG_MNERR TSI_INTF_MNERR
#define | TSI_INT_FLAG_CTCF_CLR TSI_INTC_CCTCF
#define | TSI_INT_FLAG_MNERR_CLR TSI_INTC_CMNERR
#define | TSI_FLAG_CTCF TSI_INTF_CTCF
#define | TSI_FLAG_MNERR TSI_INTF_MNERR
#define | TSI_FLAG_CTCF_CLR TSI_INTC_CCTCF
#define | TSI_FLAG_MNERR_CLR TSI_INTC_CMNERR
#define | TSI_PHM_G0P0 BIT(0)
#define | TSI_PHM_G0P1 BIT(1)
#define | TSI_PHM_G0P2 BIT(2)
#define | TSI_PHM_G0P3 BIT(3)
#define | TSI_PHM_G1P0 BIT(4)
#define | TSI_PHM_G1P1 BIT(5)
#define | TSI_PHM_G1P2 BIT(6)
#define | TSI_PHM_G1P3 BIT(7)
#define | TSI_PHM_G2P0 BIT(8)
#define | TSI_PHM_G2P1 BIT(9)
#define | TSI_PHM_G2P2 BIT(10)
#define | TSI_PHM_G2P3 BIT(11)
#define | TSI_PHM_G3P0 BIT(12)
#define | TSI_PHM_G3P1 BIT(13)
#define | TSI_PHM_G3P2 BIT(14)
#define | TSI_PHM_G3P3 BIT(15)
#define | TSI_PHM_G4P0 BIT(16)
#define | TSI_PHM_G4P1 BIT(17)
#define | TSI_PHM_G4P2 BIT(18)
#define | TSI_PHM_G4P3 BIT(19)
#define | TSI_PHM_G5P0 BIT(20)
#define | TSI_PHM_G5P1 BIT(21)
#define | TSI_PHM_G5P2 BIT(22)
#define | TSI_PHM_G5P3 BIT(23)
#define | TSI_ASW_G0P0 BIT(0)
#define | TSI_ASW_G0P1 BIT(1)
#define | TSI_ASW_G0P2 BIT(2)
#define | TSI_ASW_G0P3 BIT(3)
#define | TSI_ASW_G1P0 BIT(4)
#define | TSI_ASW_G1P1 BIT(5)
#define | TSI_ASW_G1P2 BIT(6)
#define | TSI_ASW_G1P3 BIT(7)
#define | TSI_ASW_G2P0 BIT(8)
#define | TSI_ASW_G2P1 BIT(9)
#define | TSI_ASW_G2P2 BIT(10)
#define | TSI_ASW_G2P3 BIT(11)
#define | TSI_ASW_G3P0 BIT(12)
#define | TSI_ASW_G3P1 BIT(13)
#define | TSI_ASW_G3P2 BIT(14)
#define | TSI_ASW_G3P3 BIT(15)
#define | TSI_ASW_G4P0 BIT(16)
#define | TSI_ASW_G4P1 BIT(17)
#define | TSI_ASW_G4P2 BIT(18)
#define | TSI_ASW_G4P3 BIT(19)
#define | TSI_ASW_G5P0 BIT(20)
#define | TSI_ASW_G5P1 BIT(21)
#define | TSI_ASW_G5P2 BIT(22)
#define | TSI_ASW_G5P3 BIT(23)
#define | TSI_SAMPCFG_G0P0 BIT(0)
#define | TSI_SAMPCFG_G0P1 BIT(1)
#define | TSI_SAMPCFG_G0P2 BIT(2)
#define | TSI_SAMPCFG_G0P3 BIT(3)
#define | TSI_SAMPCFG_G1P0 BIT(4)
#define | TSI_SAMPCFG_G1P1 BIT(5)
#define | TSI_SAMPCFG_G1P2 BIT(6)
#define | TSI_SAMPCFG_G1P3 BIT(7)
#define | TSI_SAMPCFG_G2P0 BIT(8)
#define | TSI_SAMPCFG_G2P1 BIT(9)
#define | TSI_SAMPCFG_G2P2 BIT(10)
#define | TSI_SAMPCFG_G2P3 BIT(11)
#define | TSI_SAMPCFG_G3P0 BIT(12)
#define | TSI_SAMPCFG_G3P1 BIT(13)
#define | TSI_SAMPCFG_G3P2 BIT(14)
#define | TSI_SAMPCFG_G3P3 BIT(15)
#define | TSI_SAMPCFG_G4P0 BIT(16)
#define | TSI_SAMPCFG_G4P1 BIT(17)
#define | TSI_SAMPCFG_G4P2 BIT(18)
#define | TSI_SAMPCFG_G4P3 BIT(19)
#define | TSI_SAMPCFG_G5P0 BIT(20)
#define | TSI_SAMPCFG_G5P1 BIT(21)
#define | TSI_SAMPCFG_G5P2 BIT(22)
#define | TSI_SAMPCFG_G5P3 BIT(23)
#define | TSI_CHCFG_G0P0 BIT(0)
#define | TSI_CHCFG_G0P1 BIT(1)
#define | TSI_CHCFG_G0P2 BIT(2)
#define | TSI_CHCFG_G0P3 BIT(3)
#define | TSI_CHCFG_G1P0 BIT(4)
#define | TSI_CHCFG_G1P1 BIT(5)
#define | TSI_CHCFG_G1P2 BIT(6)
#define | TSI_CHCFG_G1P3 BIT(7)
#define | TSI_CHCFG_G2P0 BIT(8)
#define | TSI_CHCFG_G2P1 BIT(9)
#define | TSI_CHCFG_G2P2 BIT(10)
#define | TSI_CHCFG_G2P3 BIT(11)
#define | TSI_CHCFG_G3P0 BIT(12)
#define | TSI_CHCFG_G3P1 BIT(13)
#define | TSI_CHCFG_G3P2 BIT(14)
#define | TSI_CHCFG_G3P3 BIT(15)
#define | TSI_CHCFG_G4P0 BIT(16)
#define | TSI_CHCFG_G4P1 BIT(17)
#define | TSI_CHCFG_G4P2 BIT(18)
#define | TSI_CHCFG_G4P3 BIT(19)
#define | TSI_CHCFG_G5P0 BIT(20)
#define | TSI_CHCFG_G5P1 BIT(21)
#define | TSI_CHCFG_G5P2 BIT(22)
#define | TSI_CHCFG_G5P3 BIT(23)
#define | TSI_GCTL_GE0 BIT(0)
#define | TSI_GCTL_GE1 BIT(1)
#define | TSI_GCTL_GE2 BIT(2)
#define | TSI_GCTL_GE3 BIT(3)
#define | TSI_GCTL_GE4 BIT(4)
#define | TSI_GCTL_GE5 BIT(5)
#define | TSI_GCTL_GC0 BIT(16)
#define | TSI_GCTL_GC1 BIT(17)
#define | TSI_GCTL_GC2 BIT(18)
#define | TSI_GCTL_GC3 BIT(19)
#define | TSI_GCTL_GC4 BIT(20)
#define | TSI_GCTL_GC5 BIT(21)
#define | TSI_CTL1_CTCDIV BIT(24)
#define | TSI_CTL1_ECDIV BITS(28,29)
#define | TSI_CTCDIV_DIV1 ((uint32_t)0x00000000U)
#define | TSI_CTCDIV_DIV2 ((uint32_t)0x00000001U)
#define | TSI_CTCDIV_DIV4 ((uint32_t)0x00000002U)
#define | TSI_CTCDIV_DIV8 ((uint32_t)0x00000003U)
#define | TSI_CTCDIV_DIV16 ((uint32_t)0x00000004U)
#define | TSI_CTCDIV_DIV32 ((uint32_t)0x00000005U)
#define | TSI_CTCDIV_DIV64 ((uint32_t)0x00000006U)
#define | TSI_CTCDIV_DIV128 ((uint32_t)0x00000007U)
#define | TSI_CTCDIV_DIV256 ((uint32_t)0x00000008U)
#define | TSI_CTCDIV_DIV512 ((uint32_t)0x00000009U)
#define | TSI_CTCDIV_DIV1024 ((uint32_t)0x0000000AU)
#define | TSI_CTCDIV_DIV2048 ((uint32_t)0x0000000BU)
#define | TSI_CTCDIV_DIV4096 ((uint32_t)0x0000000CU)
#define | TSI_CTCDIV_DIV8192 ((uint32_t)0x0000000DU)
#define | TSI_CTCDIV_DIV16384 ((uint32_t)0x0000000EU)
#define | TSI_CTCDIV_DIV32768 ((uint32_t)0x0000000FU)
#define | CTL_CTDT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U))
#define | TSI_TRANSFER_1CTCLK CTL_CTDT(0)
#define | TSI_TRANSFER_2CTCLK CTL_CTDT(1)
#define | TSI_TRANSFER_3CTCLK CTL_CTDT(2)
#define | TSI_TRANSFER_4CTCLK CTL_CTDT(3)
#define | TSI_TRANSFER_5CTCLK CTL_CTDT(4)
#define | TSI_TRANSFER_6CTCLK CTL_CTDT(5)
#define | TSI_TRANSFER_7CTCLK CTL_CTDT(6)
#define | TSI_TRANSFER_8CTCLK CTL_CTDT(7)
#define | TSI_TRANSFER_9CTCLK CTL_CTDT(8)
#define | TSI_TRANSFER_10CTCLK CTL_CTDT(9)
#define | TSI_TRANSFER_11CTCLK CTL_CTDT(10)
#define | TSI_TRANSFER_12CTCLK CTL_CTDT(11)
#define | TSI_TRANSFER_13CTCLK CTL_CTDT(12)
#define | TSI_TRANSFER_14CTCLK CTL_CTDT(13)
#define | TSI_TRANSFER_15CTCLK CTL_CTDT(14)
#define | TSI_TRANSFER_16CTCLK CTL_CTDT(15)
#define | CTL_CDT(regval) (BITS(28,31) & ((uint32_t)(regval) << 28U))
#define | TSI_CHARGE_1CTCLK CTL_CDT(0)
#define | TSI_CHARGE_2CTCLK CTL_CDT(1)
#define | TSI_CHARGE_3CTCLK CTL_CDT(2)
#define | TSI_CHARGE_4CTCLK CTL_CDT(3)
#define | TSI_CHARGE_5CTCLK CTL_CDT(4)
#define | TSI_CHARGE_6CTCLK CTL_CDT(5)
#define | TSI_CHARGE_7CTCLK CTL_CDT(6)
#define | TSI_CHARGE_8CTCLK CTL_CDT(7)
#define | TSI_CHARGE_9CTCLK CTL_CDT(8)
#define | TSI_CHARGE_10CTCLK CTL_CDT(9)
#define | TSI_CHARGE_11CTCLK CTL_CDT(10)
#define | TSI_CHARGE_12CTCLK CTL_CDT(11)
#define | TSI_CHARGE_13CTCLK CTL_CDT(12)
#define | TSI_CHARGE_14CTCLK CTL_CDT(13)
#define | TSI_CHARGE_15CTCLK CTL_CDT(14)
#define | TSI_CHARGE_16CTCLK CTL_CDT(15)
#define | CTL_MCN(regval) (BITS(5,7) & ((uint32_t)(regval) << 5U))
#define | TSI_MAXNUM255 CTL_MCN(0)
#define | TSI_MAXNUM511 CTL_MCN(1)
#define | TSI_MAXNUM1023 CTL_MCN(2)
#define | TSI_MAXNUM2047 CTL_MCN(3)
#define | TSI_MAXNUM4095 CTL_MCN(4)
#define | TSI_MAXNUM8191 CTL_MCN(5)
#define | TSI_MAXNUM16383 CTL_MCN(6)
#define | TSI_EXTEND_DIV1 ((uint32_t)0x00000000U)
#define | TSI_EXTEND_DIV2 ((uint32_t)0x00000001U)
#define | TSI_EXTEND_DIV3 ((uint32_t)0x00000002U)
#define | TSI_EXTEND_DIV4 ((uint32_t)0x00000003U)
#define | TSI_EXTEND_DIV5 ((uint32_t)0x00000004U)
#define | TSI_EXTEND_DIV6 ((uint32_t)0x00000005U)
#define | TSI_EXTEND_DIV7 ((uint32_t)0x00000006U)
#define | TSI_EXTEND_DIV8 ((uint32_t)0x00000007U)
#define | TSI_EXTENDMAX(regval) (BITS(17,23) & ((uint32_t)(regval) << 17U)) /* value range 1..128,extend charge state maximum duration time */
#define | TSI_FALLING_TRIGGER 0x00U
#define | TSI_RISING_TRIGGER 0x01U
#define | TSI_OUTPUT_LOW 0x00U
#define | TSI_INPUT_FLOATING 0x01U

Functions

void | tsi_deinit (void)
reset TSI peripheral More...
void | tsi_init (uint32_t prescaler, uint32_t charge_duration, uint32_t transfer_duration, uint32_t max_number)
initialize TSI plus prescaler,charge plus,transfer plus,max cycle number More...
void | tsi_enable (void)
enable TSI module More...
void | tsi_disable (void)
disable TSI module More...
void | tsi_sample_pin_enable (uint32_t sample)
enable sample pin More...
void | tsi_sample_pin_disable (uint32_t sample)
disable sample pin More...
void | tsi_channel_pin_enable (uint32_t channel)
enable channel pin More...
void | tsi_channel_pin_disable (uint32_t channel)
disable channel pin More...
void | tsi_sofeware_mode_config (void)
configure TSI triggering by software More...
void | tsi_software_start (void)
start a charge-transfer sequence when TSI is in software trigger mode More...
void | tsi_software_stop (void)
stop a charge-transfer sequence when TSI is in software trigger mode More...
void | tsi_hardware_mode_config (uint8_t trigger_edge)
configure TSI triggering by hardware More...
void | tsi_pin_mode_config (uint8_t pin_mode)
configure TSI pin mode when charge-transfer sequence is IDLE More...
void | tsi_extend_charge_config (ControlStatus extend, uint8_t prescaler, uint32_t max_duration)
configure extend charge state More...
void | tsi_plus_config (uint32_t prescaler, uint32_t charge_duration, uint32_t transfer_duration)
configure charge plus and transfer plus More...
void | tsi_max_number_config (uint32_t max_number)
configure the max cycle number of a charge-transfer sequence More...
void | tsi_hysteresis_on (uint32_t group_pin)
switch on hysteresis pin More...
void | tsi_hysteresis_off (uint32_t group_pin)
switch off hysteresis pin More...
void | tsi_analog_on (uint32_t group_pin)
switch on analog pin More...
void | tsi_analog_off (uint32_t group_pin)
switch off analog pin More...
void | tsi_interrupt_enable (uint32_t source)
enable TSI interrupt More...
void | tsi_interrupt_disable (uint32_t source)
disable TSI interrupt More...
void | tsi_interrupt_flag_clear (uint32_t flag)
clear TSI interrupt flag More...
FlagStatus | tsi_interrupt_flag_get (uint32_t flag)
get TSI interrupt flag More...
void | tsi_flag_clear (uint32_t flag)
clear flag More...
FlagStatus | tsi_flag_get (uint32_t flag)
get flag More...
void | tsi_group_enable (uint32_t group)
enbale group More...
void | tsi_group_disable (uint32_t group)
disbale group More...
FlagStatus | tsi_group_status_get (uint32_t group)
get group complete status More...
uint16_t | tsi_group0_cycle_get (void)
get the cycle number for group0 as soon as a charge-transfer sequence completes More...
uint16_t | tsi_group1_cycle_get (void)
get the cycle number for group1 as soon as a charge-transfer sequence completes More...
uint16_t | tsi_group2_cycle_get (void)
get the cycle number for group2 as soon as a charge-transfer sequence completes More...
uint16_t | tsi_group3_cycle_get (void)
get the cycle number for group3 as soon as a charge-transfer sequence completes More...
uint16_t | tsi_group4_cycle_get (void)
get the cycle number for group4 as soon as a charge-transfer sequence completes More...
uint16_t | tsi_group5_cycle_get (void)
get the cycle number for group5 as soon as a charge-transfer sequence completes More...

Detailed Description

definitions for the TSI

Definition in file gd32f3x0_tsi.h.

Macro Definition Documentation

#define CTL_CDT ( regval ) (BITS(28,31) & ((uint32_t)(regval) << 28U))

Definition at line 246 of file gd32f3x0_tsi.h.

#define CTL_CTDT ( regval ) (BITS(24,27) & ((uint32_t)(regval) << 24U))

Definition at line 227 of file gd32f3x0_tsi.h.

#define CTL_MCN ( regval ) (BITS(5,7) & ((uint32_t)(regval) << 5U))

Definition at line 265 of file gd32f3x0_tsi.h.

#define TSI TSI_BASE

TSI base address

Definition at line 18 of file gd32f3x0_tsi.h.

#define TSI_ASW REG32(TSI + 0x18U)

TSI analog switch register

Definition at line 26 of file gd32f3x0_tsi.h.

#define TSI_ASW_G0P0 BIT(0)

pin G0P0 analog switch state

Definition at line 112 of file gd32f3x0_tsi.h.

#define TSI_ASW_G0P1 BIT(1)

pin G0P1 analog switch state

Definition at line 113 of file gd32f3x0_tsi.h.

#define TSI_ASW_G0P2 BIT(2)

pin G0P2 analog switch state

Definition at line 114 of file gd32f3x0_tsi.h.

#define TSI_ASW_G0P3 BIT(3)

pin G0P3 analog switch state

Definition at line 115 of file gd32f3x0_tsi.h.

#define TSI_ASW_G1P0 BIT(4)

pin G1P0 analog switch state

Definition at line 116 of file gd32f3x0_tsi.h.

#define TSI_ASW_G1P1 BIT(5)

pin G1P1 analog switch state

Definition at line 117 of file gd32f3x0_tsi.h.

#define TSI_ASW_G1P2 BIT(6)

pin G1P2 analog switch state

Definition at line 118 of file gd32f3x0_tsi.h.

#define TSI_ASW_G1P3 BIT(7)

pin G1P3 analog switch state

Definition at line 119 of file gd32f3x0_tsi.h.

#define TSI_ASW_G2P0 BIT(8)

pin G2P0 analog switch state

Definition at line 120 of file gd32f3x0_tsi.h.

#define TSI_ASW_G2P1 BIT(9)

pin G2P1 analog switch state

Definition at line 121 of file gd32f3x0_tsi.h.

#define TSI_ASW_G2P2 BIT(10)

pin G2P2 analog switch state

Definition at line 122 of file gd32f3x0_tsi.h.

#define TSI_ASW_G2P3 BIT(11)

pin G2P3 analog switch state

Definition at line 123 of file gd32f3x0_tsi.h.

#define TSI_ASW_G3P0 BIT(12)

pin G3P0 analog switch state

Definition at line 124 of file gd32f3x0_tsi.h.

#define TSI_ASW_G3P1 BIT(13)

pin G3P1 analog switch state

Definition at line 125 of file gd32f3x0_tsi.h.

#define TSI_ASW_G3P2 BIT(14)

pin G3P2 analog switch state

Definition at line 126 of file gd32f3x0_tsi.h.

#define TSI_ASW_G3P3 BIT(15)

pin G3P3 analog switch state

Definition at line 127 of file gd32f3x0_tsi.h.

#define TSI_ASW_G4P0 BIT(16)

pin G4P0 analog switch state

Definition at line 128 of file gd32f3x0_tsi.h.

#define TSI_ASW_G4P1 BIT(17)

pin G4P1 analog switch state

Definition at line 129 of file gd32f3x0_tsi.h.

#define TSI_ASW_G4P2 BIT(18)

pin G4P2 analog switch state

Definition at line 130 of file gd32f3x0_tsi.h.

#define TSI_ASW_G4P3 BIT(19)

pin G4P3 analog switch state

Definition at line 131 of file gd32f3x0_tsi.h.

#define TSI_ASW_G5P0 BIT(20)

pin G5P0 analog switch state

Definition at line 132 of file gd32f3x0_tsi.h.

#define TSI_ASW_G5P1 BIT(21)

pin G5P1 analog switch state

Definition at line 133 of file gd32f3x0_tsi.h.

#define TSI_ASW_G5P2 BIT(22)

pin G5P2 analog switch state

Definition at line 134 of file gd32f3x0_tsi.h.

#define TSI_ASW_G5P3 BIT(23)

pin G5P3 analog switch state

Definition at line 135 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_10CTCLK CTL_CDT(9)

the duration time of charge state is 10 CTCLK

Definition at line 256 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_11CTCLK CTL_CDT(10)

the duration time of charge state is 11 CTCLK

Definition at line 257 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_12CTCLK CTL_CDT(11)

the duration time of charge state is 12 CTCLK

Definition at line 258 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_13CTCLK CTL_CDT(12)

the duration time of charge state is 13 CTCLK

Definition at line 259 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_14CTCLK CTL_CDT(13)

the duration time of charge state is 14 CTCLK

Definition at line 260 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_15CTCLK CTL_CDT(14)

the duration time of charge state is 15 CTCLK

Definition at line 261 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_16CTCLK CTL_CDT(15)

the duration time of charge state is 16 CTCLK

Definition at line 262 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_1CTCLK CTL_CDT(0)

the duration time of charge state is 1 CTCLK

Definition at line 247 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_2CTCLK CTL_CDT(1)

the duration time of charge state is 2 CTCLK

Definition at line 248 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_3CTCLK CTL_CDT(2)

the duration time of charge state is 3 CTCLK

Definition at line 249 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_4CTCLK CTL_CDT(3)

the duration time of charge state is 4 CTCLK

Definition at line 250 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_5CTCLK CTL_CDT(4)

the duration time of charge state is 5 CTCLK

Definition at line 251 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_6CTCLK CTL_CDT(5)

the duration time of charge state is 6 CTCLK

Definition at line 252 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_7CTCLK CTL_CDT(6)

the duration time of charge state is 7 CTCLK

Definition at line 253 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_8CTCLK CTL_CDT(7)

the duration time of charge state is 8 CTCLK

Definition at line 254 of file gd32f3x0_tsi.h.

#define TSI_CHARGE_9CTCLK CTL_CDT(8)

the duration time of charge state is 9 CTCLK

Definition at line 255 of file gd32f3x0_tsi.h.

#define TSI_CHCFG REG32(TSI + 0x28U)

TSI channel configuration register

Definition at line 28 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G0P0 BIT(0)

pin G0P0 channel pin mode

Definition at line 164 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G0P1 BIT(1)

pin G0P1 channel pin mode

Definition at line 165 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G0P2 BIT(2)

pin G0P2 channel pin mode

Definition at line 166 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G0P3 BIT(3)

pin G0P3 channel pin mode

Definition at line 167 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G1P0 BIT(4)

pin G1P0 channel pin mode

Definition at line 168 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G1P1 BIT(5)

pin G1P1 channel pin mode

Definition at line 169 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G1P2 BIT(6)

pin G1P2 channel pin mode

Definition at line 170 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G1P3 BIT(7)

pin G1P3 channel pin mode

Definition at line 171 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G2P0 BIT(8)

pin G2P0 channel pin mode

Definition at line 172 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G2P1 BIT(9)

pin G2P1 channel pin mode

Definition at line 173 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G2P2 BIT(10)

pin G2P2 channel pin mode

Definition at line 174 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G2P3 BIT(11)

pin G2P3 channel pin mode

Definition at line 175 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G3P0 BIT(12)

pin G3P0 channel pin mode

Definition at line 176 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G3P1 BIT(13)

pin G3P1 channel pin mode

Definition at line 177 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G3P2 BIT(14)

pin G3P2 channel pin mode

Definition at line 178 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G3P3 BIT(15)

pin G3P3 channel pin mode

Definition at line 179 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G4P0 BIT(16)

pin G4P0 channel pin mode

Definition at line 180 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G4P1 BIT(17)

pin G4P1 channel pin mode

Definition at line 181 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G4P2 BIT(18)

pin G4P2 channel pin mode

Definition at line 182 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G4P3 BIT(19)

pin G4P3 channel pin mode

Definition at line 183 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G5P0 BIT(20)

pin G5P0 channel pin mode

Definition at line 184 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G5P1 BIT(21)

pin G5P1 channel pin mode

Definition at line 185 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G5P2 BIT(22)

pin G5P2 channel pin mode

Definition at line 186 of file gd32f3x0_tsi.h.

#define TSI_CHCFG_G5P3 BIT(23)

pin G5P3 channel pin mode

Definition at line 187 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV1 ((uint32_t)0x00000000U)

fCTCLK = fHCLK

Definition at line 209 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV1024 ((uint32_t)0x0000000AU)

fCTCLK = fHCLK/1024

Definition at line 219 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV128 ((uint32_t)0x00000007U)

fCTCLK = fHCLK/128

Definition at line 216 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV16 ((uint32_t)0x00000004U)

fCTCLK = fHCLK/16

Definition at line 213 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV16384 ((uint32_t)0x0000000EU)

fCTCLK = fHCLK/16384

Definition at line 223 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV2 ((uint32_t)0x00000001U)

fCTCLK = fHCLK/2

Definition at line 210 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV2048 ((uint32_t)0x0000000BU)

fCTCLK = fHCLK/2048

Definition at line 220 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV256 ((uint32_t)0x00000008U)

fCTCLK = fHCLK/256

Definition at line 217 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV32 ((uint32_t)0x00000005U)

fCTCLK = fHCLK/32

Definition at line 214 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV32768 ((uint32_t)0x0000000FU)

fCTCLK = fHCLK/32768

Definition at line 224 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV4 ((uint32_t)0x00000002U)

fCTCLK = fHCLK/4

Definition at line 211 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV4096 ((uint32_t)0x0000000CU)

fCTCLK = fHCLK/4096

Definition at line 221 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV512 ((uint32_t)0x00000009U)

fCTCLK = fHCLK/512

Definition at line 218 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV64 ((uint32_t)0x00000006U)

fCTCLK = fHCLK/64

Definition at line 215 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV8 ((uint32_t)0x00000003U)

fCTCLK = fHCLK/8

Definition at line 212 of file gd32f3x0_tsi.h.

#define TSI_CTCDIV_DIV8192 ((uint32_t)0x0000000DU)

fCTCLK = fHCLK/8192

Definition at line 222 of file gd32f3x0_tsi.h.

#define TSI_CTL0 REG32(TSI + 0x00U)

TSI control register0

Definition at line 21 of file gd32f3x0_tsi.h.

#define TSI_CTL0_CDT BITS(28,31)

charge state duration time

Definition at line 51 of file gd32f3x0_tsi.h.

#define TSI_CTL0_CTCDIV BITS(12,14)

CTCLK clock division factor

Definition at line 46 of file gd32f3x0_tsi.h.

#define TSI_CTL0_CTDT BITS(24,27)

charge transfer state duration time

Definition at line 50 of file gd32f3x0_tsi.h.

#define TSI_CTL0_ECDIV BIT(15)

ECCLK clock division factor

Definition at line 47 of file gd32f3x0_tsi.h.

#define TSI_CTL0_ECDT BITS(17,23)

extend charge State maximum duration time

Definition at line 49 of file gd32f3x0_tsi.h.

#define TSI_CTL0_ECEN BIT(16)

extend charge state enable

Definition at line 48 of file gd32f3x0_tsi.h.

#define TSI_CTL0_EGSEL BIT(3)

edge selection

Definition at line 43 of file gd32f3x0_tsi.h.

#define TSI_CTL0_MCN BITS(5,7)

max cycle number of a sequence

Definition at line 45 of file gd32f3x0_tsi.h.

#define TSI_CTL0_PINMOD BIT(4)

pin mode

Definition at line 44 of file gd32f3x0_tsi.h.

#define TSI_CTL0_TRGMOD BIT(2)

trigger mode selection

Definition at line 42 of file gd32f3x0_tsi.h.

#define TSI_CTL0_TSIEN BIT(0)

TSI enable

Definition at line 40 of file gd32f3x0_tsi.h.

#define TSI_CTL0_TSIS BIT(1)

TSI start

Definition at line 41 of file gd32f3x0_tsi.h.

#define TSI_CTL1 REG32(TSI + 0x300U)

TSI control registers1

Definition at line 36 of file gd32f3x0_tsi.h.

#define TSI_CTL1_CTCDIV BIT(24)

CTCLK clock division factor

Definition at line 204 of file gd32f3x0_tsi.h.

#define TSI_CTL1_ECDIV BITS(28,29)

ECCLK clock division factor

Definition at line 205 of file gd32f3x0_tsi.h.

#define TSI_EXTEND_DIV1 ((uint32_t)0x00000000U)

fECCLK = fHCLK

Definition at line 275 of file gd32f3x0_tsi.h.

#define TSI_EXTEND_DIV2 ((uint32_t)0x00000001U)

fECCLK = fHCLK/2

Definition at line 276 of file gd32f3x0_tsi.h.

#define TSI_EXTEND_DIV3 ((uint32_t)0x00000002U)

fECCLK = fHCLK/3

Definition at line 277 of file gd32f3x0_tsi.h.

#define TSI_EXTEND_DIV4 ((uint32_t)0x00000003U)

fECCLK = fHCLK/4

Definition at line 278 of file gd32f3x0_tsi.h.

#define TSI_EXTEND_DIV5 ((uint32_t)0x00000004U)

fECCLK = fHCLK/5

Definition at line 279 of file gd32f3x0_tsi.h.

#define TSI_EXTEND_DIV6 ((uint32_t)0x00000005U)

fECCLK = fHCLK/6

Definition at line 280 of file gd32f3x0_tsi.h.

#define TSI_EXTEND_DIV7 ((uint32_t)0x00000006U)

fECCLK = fHCLK/7

Definition at line 281 of file gd32f3x0_tsi.h.

#define TSI_EXTEND_DIV8 ((uint32_t)0x00000007U)

fECCLK = fHCLK/8

Definition at line 282 of file gd32f3x0_tsi.h.

#define TSI_EXTENDMAX ( regval ) (BITS(17,23) & ((uint32_t)(regval) << 17U)) /* value range 1..128,extend charge state maximum duration time */

Definition at line 285 of file gd32f3x0_tsi.h.

#define TSI_FALLING_TRIGGER 0x00U

falling edge trigger TSI charge transfer sequence

Definition at line 288 of file gd32f3x0_tsi.h.

#define TSI_FLAG_CTCF TSI_INTF_CTCF

charge transfer complete flag

Definition at line 78 of file gd32f3x0_tsi.h.

#define TSI_FLAG_CTCF_CLR TSI_INTC_CCTCF

clear charge transfer complete flag

Definition at line 82 of file gd32f3x0_tsi.h.

#define TSI_FLAG_MNERR TSI_INTF_MNERR

max cycle number error

Definition at line 79 of file gd32f3x0_tsi.h.

#define TSI_FLAG_MNERR_CLR TSI_INTC_CMNERR

clear max cycle number error

Definition at line 83 of file gd32f3x0_tsi.h.

#define TSI_G0CYCN REG32(TSI + 0x34U)

TSI group 0 cycle number register

Definition at line 30 of file gd32f3x0_tsi.h.

#define TSI_G1CYCN REG32(TSI + 0x38U)

TSI group 1 cycle number register

Definition at line 31 of file gd32f3x0_tsi.h.

#define TSI_G2CYCN REG32(TSI + 0x3CU)

TSI group 2 cycle number register

Definition at line 32 of file gd32f3x0_tsi.h.

#define TSI_G3CYCN REG32(TSI + 0x40U)

TSI group 3 cycle number register

Definition at line 33 of file gd32f3x0_tsi.h.

#define TSI_G4CYCN REG32(TSI + 0x44U)

TSI group 4 cycle number register

Definition at line 34 of file gd32f3x0_tsi.h.

#define TSI_G5CYCN REG32(TSI + 0x48U)

TSI group 5 cycle number register

Definition at line 35 of file gd32f3x0_tsi.h.

#define TSI_GCTL REG32(TSI + 0x30U)

TSI group control register

Definition at line 29 of file gd32f3x0_tsi.h.

#define TSI_GCTL_GC0 BIT(16)

group0 complete

Definition at line 196 of file gd32f3x0_tsi.h.

#define TSI_GCTL_GC1 BIT(17)

group1 complete

Definition at line 197 of file gd32f3x0_tsi.h.

#define TSI_GCTL_GC2 BIT(18)

group2 complete

Definition at line 198 of file gd32f3x0_tsi.h.

#define TSI_GCTL_GC3 BIT(19)

group3 complete

Definition at line 199 of file gd32f3x0_tsi.h.

#define TSI_GCTL_GC4 BIT(20)

group4 complete

Definition at line 200 of file gd32f3x0_tsi.h.

#define TSI_GCTL_GC5 BIT(21)

group5 complete

Definition at line 201 of file gd32f3x0_tsi.h.

#define TSI_GCTL_GE0 BIT(0)

group0 enable

Definition at line 190 of file gd32f3x0_tsi.h.

#define TSI_GCTL_GE1 BIT(1)

group1 enable

Definition at line 191 of file gd32f3x0_tsi.h.

#define TSI_GCTL_GE2 BIT(2)

group2 enable

Definition at line 192 of file gd32f3x0_tsi.h.

#define TSI_GCTL_GE3 BIT(3)

group3 enable

Definition at line 193 of file gd32f3x0_tsi.h.

#define TSI_GCTL_GE4 BIT(4)

group4 enable

Definition at line 194 of file gd32f3x0_tsi.h.

#define TSI_GCTL_GE5 BIT(5)

group5 enable

Definition at line 195 of file gd32f3x0_tsi.h.

#define TSI_INPUT_FLOATING 0x01U

TSI pin will keep input_floating when IDLE

Definition at line 293 of file gd32f3x0_tsi.h.

#define TSI_INT_CCTCF TSI_INTEN_CTCFIE

charge transfer complete flag interrupt enable

Definition at line 66 of file gd32f3x0_tsi.h.

#define TSI_INT_FLAG_CTCF TSI_INTF_CTCF

charge transfer complete flag

Definition at line 70 of file gd32f3x0_tsi.h.

#define TSI_INT_FLAG_CTCF_CLR TSI_INTC_CCTCF

clear charge transfer complete flag

Definition at line 74 of file gd32f3x0_tsi.h.

#define TSI_INT_FLAG_MNERR TSI_INTF_MNERR

max cycle number error

Definition at line 71 of file gd32f3x0_tsi.h.

#define TSI_INT_FLAG_MNERR_CLR TSI_INTC_CMNERR

clear max cycle number error

Definition at line 75 of file gd32f3x0_tsi.h.

#define TSI_INT_MNERR TSI_INTEN_MNERRIE

max cycle number error interrupt enable

Definition at line 67 of file gd32f3x0_tsi.h.

#define TSI_INTC REG32(TSI + 0x08U)

TSI interrupt flag clear register

Definition at line 23 of file gd32f3x0_tsi.h.

#define TSI_INTC_CCTCF BIT(0)

clear charge transfer complete flag

Definition at line 58 of file gd32f3x0_tsi.h.

#define TSI_INTC_CMNERR BIT(1)

clear max cycle number error

Definition at line 59 of file gd32f3x0_tsi.h.

#define TSI_INTEN REG32(TSI + 0x04U)

TSI interrupt enable register

Definition at line 22 of file gd32f3x0_tsi.h.

#define TSI_INTEN_CTCFIE BIT(0)

charge transfer complete flag interrupt enable

Definition at line 54 of file gd32f3x0_tsi.h.

#define TSI_INTEN_MNERRIE BIT(1)

max cycle number error interrupt enable

Definition at line 55 of file gd32f3x0_tsi.h.

#define TSI_INTF REG32(TSI + 0x0CU)

TSI interrupt flag register

Definition at line 24 of file gd32f3x0_tsi.h.

#define TSI_INTF_CTCF BIT(0)

charge transfer complete flag

Definition at line 62 of file gd32f3x0_tsi.h.

#define TSI_INTF_MNERR BIT(1)

max cycle number error

Definition at line 63 of file gd32f3x0_tsi.h.

#define TSI_MAXNUM1023 CTL_MCN(2)

the max cycle number of a sequence is 1023

Definition at line 268 of file gd32f3x0_tsi.h.

#define TSI_MAXNUM16383 CTL_MCN(6)

the max cycle number of a sequence is 16383

Definition at line 272 of file gd32f3x0_tsi.h.

#define TSI_MAXNUM2047 CTL_MCN(3)

the max cycle number of a sequence is 2047

Definition at line 269 of file gd32f3x0_tsi.h.

#define TSI_MAXNUM255 CTL_MCN(0)

the max cycle number of a sequence is 255

Definition at line 266 of file gd32f3x0_tsi.h.

#define TSI_MAXNUM4095 CTL_MCN(4)

the max cycle number of a sequence is 4095

Definition at line 270 of file gd32f3x0_tsi.h.

#define TSI_MAXNUM511 CTL_MCN(1)

the max cycle number of a sequence is 511

Definition at line 267 of file gd32f3x0_tsi.h.

#define TSI_MAXNUM8191 CTL_MCN(5)

the max cycle number of a sequence is 8191

Definition at line 271 of file gd32f3x0_tsi.h.

#define TSI_OUTPUT_LOW 0x00U

TSI pin will output low when IDLE

Definition at line 292 of file gd32f3x0_tsi.h.

#define TSI_PHM REG32(TSI + 0x10U)

TSI pin hysteresis mode register

Definition at line 25 of file gd32f3x0_tsi.h.

#define TSI_PHM_G0P0 BIT(0)

pin G0P0 Schmitt trigger hysteresis state

Definition at line 86 of file gd32f3x0_tsi.h.

#define TSI_PHM_G0P1 BIT(1)

pin G0P1 Schmitt trigger hysteresis state

Definition at line 87 of file gd32f3x0_tsi.h.

#define TSI_PHM_G0P2 BIT(2)

pin G0P2 Schmitt trigger hysteresis state

Definition at line 88 of file gd32f3x0_tsi.h.

#define TSI_PHM_G0P3 BIT(3)

pin G0P3 Schmitt trigger hysteresis state

Definition at line 89 of file gd32f3x0_tsi.h.

#define TSI_PHM_G1P0 BIT(4)

pin G1P0 Schmitt trigger hysteresis state

Definition at line 90 of file gd32f3x0_tsi.h.

#define TSI_PHM_G1P1 BIT(5)

pin G1P1 Schmitt trigger hysteresis state

Definition at line 91 of file gd32f3x0_tsi.h.

#define TSI_PHM_G1P2 BIT(6)

pin G1P2 Schmitt trigger hysteresis state

Definition at line 92 of file gd32f3x0_tsi.h.

#define TSI_PHM_G1P3 BIT(7)

pin G1P3 Schmitt trigger hysteresis state

Definition at line 93 of file gd32f3x0_tsi.h.

#define TSI_PHM_G2P0 BIT(8)

pin G2P0 Schmitt trigger hysteresis state

Definition at line 94 of file gd32f3x0_tsi.h.

#define TSI_PHM_G2P1 BIT(9)

pin G2P1 Schmitt trigger hysteresis state

Definition at line 95 of file gd32f3x0_tsi.h.

#define TSI_PHM_G2P2 BIT(10)

pin G2P2 Schmitt trigger hysteresis state

Definition at line 96 of file gd32f3x0_tsi.h.

#define TSI_PHM_G2P3 BIT(11)

pin G2P3 Schmitt trigger hysteresis state

Definition at line 97 of file gd32f3x0_tsi.h.

#define TSI_PHM_G3P0 BIT(12)

pin G3P0 Schmitt trigger hysteresis state

Definition at line 98 of file gd32f3x0_tsi.h.

#define TSI_PHM_G3P1 BIT(13)

pin G3P1 Schmitt trigger hysteresis state

Definition at line 99 of file gd32f3x0_tsi.h.

#define TSI_PHM_G3P2 BIT(14)

pin G3P2 Schmitt trigger hysteresis state

Definition at line 100 of file gd32f3x0_tsi.h.

#define TSI_PHM_G3P3 BIT(15)

pin G3P3 Schmitt trigger hysteresis state

Definition at line 101 of file gd32f3x0_tsi.h.

#define TSI_PHM_G4P0 BIT(16)

pin G4P0 Schmitt trigger hysteresis state

Definition at line 102 of file gd32f3x0_tsi.h.

#define TSI_PHM_G4P1 BIT(17)

pin G4P1 Schmitt trigger hysteresis state

Definition at line 103 of file gd32f3x0_tsi.h.

#define TSI_PHM_G4P2 BIT(18)

pin G4P2 Schmitt trigger hysteresis state

Definition at line 104 of file gd32f3x0_tsi.h.

#define TSI_PHM_G4P3 BIT(19)

pin G4P3 Schmitt trigger hysteresis state

Definition at line 105 of file gd32f3x0_tsi.h.

#define TSI_PHM_G5P0 BIT(20)

pin G5P0 Schmitt trigger hysteresis state

Definition at line 106 of file gd32f3x0_tsi.h.

#define TSI_PHM_G5P1 BIT(21)

pin G5P1 Schmitt trigger hysteresis state

Definition at line 107 of file gd32f3x0_tsi.h.

#define TSI_PHM_G5P2 BIT(22)

pin G5P2 Schmitt trigger hysteresis state

Definition at line 108 of file gd32f3x0_tsi.h.

#define TSI_PHM_G5P3 BIT(23)

pin G5P3 Schmitt trigger hysteresis state

Definition at line 109 of file gd32f3x0_tsi.h.

#define TSI_RISING_TRIGGER 0x01U

rising edge trigger TSI charge transfer sequence

Definition at line 289 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG REG32(TSI + 0x20U)

TSI sample configuration register

Definition at line 27 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G0P0 BIT(0)

pin G0P0 sample pin mode

Definition at line 138 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G0P1 BIT(1)

pin G0P1 sample pin mode

Definition at line 139 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G0P2 BIT(2)

pin G0P2 sample pin mode

Definition at line 140 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G0P3 BIT(3)

pin G0P3 sample pin mode

Definition at line 141 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G1P0 BIT(4)

pin G1P0 sample pin mode

Definition at line 142 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G1P1 BIT(5)

pin G1P1 sample pin mode

Definition at line 143 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G1P2 BIT(6)

pin G1P2 sample pin mode

Definition at line 144 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G1P3 BIT(7)

pin G1P3 sample pin mode

Definition at line 145 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G2P0 BIT(8)

pin G2P0 sample pin mode

Definition at line 146 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G2P1 BIT(9)

pin G2P1 sample pin mode

Definition at line 147 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G2P2 BIT(10)

pin G2P2 sample pin mode

Definition at line 148 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G2P3 BIT(11)

pin G2P3 sample pin mode

Definition at line 149 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G3P0 BIT(12)

pin G3P0 sample pin mode

Definition at line 150 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G3P1 BIT(13)

pin G3P1 sample pin mode

Definition at line 151 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G3P2 BIT(14)

pin G3P2 sample pin mode

Definition at line 152 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G3P3 BIT(15)

pin G3P3 sample pin mode

Definition at line 153 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G4P0 BIT(16)

pin G4P0 sample pin mode

Definition at line 154 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G4P1 BIT(17)

pin G4P1 sample pin mode

Definition at line 155 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G4P2 BIT(18)

pin G4P2 sample pin mode

Definition at line 156 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G4P3 BIT(19)

pin G4P3 sample pin mode

Definition at line 157 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G5P0 BIT(20)

pin G5P0 sample pin mode

Definition at line 158 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G5P1 BIT(21)

pin G5P1 sample pin mode

Definition at line 159 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G5P2 BIT(22)

pin G5P2 sample pin mode

Definition at line 160 of file gd32f3x0_tsi.h.

#define TSI_SAMPCFG_G5P3 BIT(23)

pin G5P3 sample pin mode

Definition at line 161 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_10CTCLK CTL_CTDT(9)

the duration time of transfer state is 10 CTCLK

Definition at line 237 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_11CTCLK CTL_CTDT(10)

the duration time of transfer state is 11 CTCLK

Definition at line 238 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_12CTCLK CTL_CTDT(11)

the duration time of transfer state is 12 CTCLK

Definition at line 239 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_13CTCLK CTL_CTDT(12)

the duration time of transfer state is 13 CTCLK

Definition at line 240 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_14CTCLK CTL_CTDT(13)

the duration time of transfer state is 14 CTCLK

Definition at line 241 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_15CTCLK CTL_CTDT(14)

the duration time of transfer state is 15 CTCLK

Definition at line 242 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_16CTCLK CTL_CTDT(15)

the duration time of transfer state is 16 CTCLK

Definition at line 243 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_1CTCLK CTL_CTDT(0)

the duration time of transfer state is 1 CTCLK

Definition at line 228 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_2CTCLK CTL_CTDT(1)

the duration time of transfer state is 2 CTCLK

Definition at line 229 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_3CTCLK CTL_CTDT(2)

the duration time of transfer state is 3 CTCLK

Definition at line 230 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_4CTCLK CTL_CTDT(3)

the duration time of transfer state is 4 CTCLK

Definition at line 231 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_5CTCLK CTL_CTDT(4)

the duration time of transfer state is 5 CTCLK

Definition at line 232 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_6CTCLK CTL_CTDT(5)

the duration time of transfer state is 6 CTCLK

Definition at line 233 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_7CTCLK CTL_CTDT(6)

the duration time of transfer state is 7 CTCLK

Definition at line 234 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_8CTCLK CTL_CTDT(7)

the duration time of transfer state is 8 CTCLK

Definition at line 235 of file gd32f3x0_tsi.h.

#define TSI_TRANSFER_9CTCLK CTL_CTDT(8)

the duration time of transfer state is 9 CTCLK

Definition at line 236 of file gd32f3x0_tsi.h.

Function Documentation

void tsi_analog_off ( uint32_t group_pin )

switch off analog pin

Parameters
[in] group_pin select pin which will be switched off analog
  • TSI_ASW_GxPy(x=0..5,y=0..3):pin y of group x switch off analog
[out] none
Return values
none

Definition at line 541 of file gd32f3x0_tsi.c.

542 {
543 TSI_ASW &= ~group_pin;
544 }
TSI_ASW
#define TSI_ASW
Definition: gd32f3x0_tsi.h:26
void tsi_analog_on ( uint32_t group_pin )

switch on analog pin

Parameters
[in] group_pin select pin which will be switched on analog
  • TSI_ASW_GxPy(x=0..5,y=0..3):pin y of group x switch on analog
[out] none
Return values
none

Definition at line 529 of file gd32f3x0_tsi.c.

530 {
531 TSI_ASW |= group_pin;
532 }
TSI_ASW
#define TSI_ASW
Definition: gd32f3x0_tsi.h:26
void tsi_channel_pin_disable ( uint32_t channel )

disable channel pin

Parameters
[in] channel channel pin
  • TSI_CHCFG_GxPy( x=0..5,y=0..3): pin y of group x
[out] none
Return values
none

Definition at line 140 of file gd32f3x0_tsi.c.

141 {
142 TSI_CHCFG &= ~channel;
143 }
TSI_CHCFG
#define TSI_CHCFG
Definition: gd32f3x0_tsi.h:28
void tsi_channel_pin_enable ( uint32_t channel )

enable channel pin

Parameters
[in] channel channel pin
  • TSI_CHCFG_GxPy( x=0..5,y=0..3): pin y of group x
[out] none
Return values
none

Definition at line 128 of file gd32f3x0_tsi.c.

129 {
130 TSI_CHCFG |= channel;
131 }
TSI_CHCFG
#define TSI_CHCFG
Definition: gd32f3x0_tsi.h:28
void tsi_deinit ( void )

reset TSI peripheral

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_tsi.c.

21 {
22 rcu_periph_reset_enable(RCU_TSIRST);
23 rcu_periph_reset_disable(RCU_TSIRST);
24 }
RCU_TSIRST
Definition: gd32f3x0_rcu.h:331
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
void tsi_disable ( void )

disable TSI module

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 322 of file gd32f3x0_tsi.c.

323 {
324 TSI_CTL0 &= ~TSI_CTL0_TSIEN;
325 }
TSI_CTL0_TSIEN
#define TSI_CTL0_TSIEN
Definition: gd32f3x0_tsi.h:40
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
void tsi_enable ( void )

enable TSI module

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 311 of file gd32f3x0_tsi.c.

312 {
313 TSI_CTL0 |= TSI_CTL0_TSIEN;
314 }
TSI_CTL0_TSIEN
#define TSI_CTL0_TSIEN
Definition: gd32f3x0_tsi.h:40
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
void tsi_extend_charge_config | ( | ControlStatus | extend,
 |  | uint8_t | prescaler,
 |  | uint32_t | max_duration
 | ) |  |

configure extend charge state

Parameters
[in] extend enable or disable extend charge state
  • ENABLE: enable extend charge state
  • DISABLE: disable extend charge state
[in] prescaler ECCLK clock division factor
  • TSI_EXTEND_DIV1: fECCLK = fHCLK
  • TSI_EXTEND_DIV2: fECCLK = fHCLK/2
  • TSI_EXTEND_DIV3: fECCLK = fHCLK/3
  • TSI_EXTEND_DIV4: fECCLK = fHCLK/4
  • TSI_EXTEND_DIV5: fECCLK = fHCLK/5
  • TSI_EXTEND_DIV6: fECCLK = fHCLK/6
  • TSI_EXTEND_DIV7: fECCLK = fHCLK/7
  • TSI_EXTEND_DIV8: fECCLK = fHCLK/8
[in] | max_duration | value range 1...128,extend charge state maximum duration time is 1*tECCLK~128*tECCLK
[out] | none
Return values
none

Definition at line 345 of file gd32f3x0_tsi.c.

346 {
347 uint32_t ctl0,ctl1;
348 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
349 if(DISABLE == extend){
350 /*disable extend charge state*/
351 TSI_CTL0 &= ~TSI_CTL0_ECEN;
352 }else{
353 if(TSI_EXTEND_DIV3 > prescaler){
354 /*configure extend charge state maximum duration time*/
355 ctl0 = TSI_CTL0;
356 ctl0 &= ~TSI_CTL0_ECDT;
357 ctl0 |= TSI_EXTENDMAX((max_duration-1U));
358 TSI_CTL0 = ctl0;
359 /*configure ECCLK clock division factor*/
360 ctl0 = TSI_CTL0;
361 ctl0 &= ~TSI_CTL0_ECDIV;
362 ctl0 |= (uint32_t)prescaler<<15U;
363 TSI_CTL0 = ctl0;
364 /*enable extend charge state*/
365 TSI_CTL0 |= TSI_CTL0_ECEN;
366 }else{
367 /*configure extend charge state maximum duration time*/
368 ctl0 = TSI_CTL0;
369 ctl0 &= ~TSI_CTL0_ECDT;
370 ctl0 |= TSI_EXTENDMAX((max_duration-1U));
371 TSI_CTL0 = ctl0;
372 /*configure ECCLK clock division factor*/
373 ctl0 = TSI_CTL0;
374 ctl0 &= ~TSI_CTL0_ECDIV;
375 ctl0 |= (prescaler & 0x01U)<<15U;
376 TSI_CTL0 = ctl0;
377 ctl1 = TSI_CTL1;
378 ctl1 &= ~TSI_CTL1_ECDIV;
379 ctl1 |= (prescaler & 0x06U)<<28U;
380 TSI_CTL1 = ctl1;
381 /*enable extend charge state*/
382 TSI_CTL0 |= TSI_CTL0_ECEN;
383 }
384 }
385 }
386 }
TSI_CTL0_ECDIV
#define TSI_CTL0_ECDIV
Definition: gd32f3x0_tsi.h:47
TSI_CTL0_ECDT
#define TSI_CTL0_ECDT
Definition: gd32f3x0_tsi.h:49
TSI_CTL0_ECEN
#define TSI_CTL0_ECEN
Definition: gd32f3x0_tsi.h:48
TSI_CTL1_ECDIV
#define TSI_CTL1_ECDIV
Definition: gd32f3x0_tsi.h:205
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
TSI_CTL1
#define TSI_CTL1
Definition: gd32f3x0_tsi.h:36
TSI_EXTENDMAX
#define TSI_EXTENDMAX(regval)
Definition: gd32f3x0_tsi.h:285
TSI_EXTEND_DIV3
#define TSI_EXTEND_DIV3
Definition: gd32f3x0_tsi.h:277
void tsi_flag_clear ( uint32_t flag )

clear flag

Parameters
[in] source select flag which will be cleared
  • TSI_FLAG_CTCF_CLR: clear charge-transfer complete flag
  • TSI_FLAG_MNERR_CLR: clear max cycle number error
[out] none
Return values
none

Definition at line 474 of file gd32f3x0_tsi.c.

475 {
476 TSI_INTC |= flag;
477 }
TSI_INTC
#define TSI_INTC
Definition: gd32f3x0_tsi.h:23
FlagStatus tsi_flag_get ( uint32_t flag )

get flag

Parameters
[in] status
  • TSI_FLAG_CTCF: charge-transfer complete flag
  • TSI_FLAG_MNERR: max Cycle Number Error
[out] none
Return values
FlagStatus:SET or RESET

Definition at line 487 of file gd32f3x0_tsi.c.

488 {
489 FlagStatus flag_status;
490 if(TSI_INTF & flag){
491 flag_status = SET;
492 }else{
493 flag_status = RESET;
494 }
495 return flag_status;
496 }
TSI_INTF
#define TSI_INTF
Definition: gd32f3x0_tsi.h:24
uint16_t tsi_group0_cycle_get ( void )

get the cycle number for group0 as soon as a charge-transfer sequence completes

Parameters
[in] | none
[out] | none
Return values
group0 cycle number

Definition at line 594 of file gd32f3x0_tsi.c.

595 {
596 return (uint16_t)TSI_G0CYCN;
597 }
TSI_G0CYCN
#define TSI_G0CYCN
Definition: gd32f3x0_tsi.h:30
uint16_t tsi_group1_cycle_get ( void )

get the cycle number for group1 as soon as a charge-transfer sequence completes

Parameters
[in] | none
[out] | none
Return values
group1 cycle number

Definition at line 605 of file gd32f3x0_tsi.c.

606 {
607 return (uint16_t)TSI_G1CYCN;
608 }
TSI_G1CYCN
#define TSI_G1CYCN
Definition: gd32f3x0_tsi.h:31
uint16_t tsi_group2_cycle_get ( void )

get the cycle number for group2 as soon as a charge-transfer sequence completes

Parameters
[in] | none
[out] | none
Return values
group2 cycle number

Definition at line 616 of file gd32f3x0_tsi.c.

617 {
618 return (uint16_t)TSI_G2CYCN;
619 }
TSI_G2CYCN
#define TSI_G2CYCN
Definition: gd32f3x0_tsi.h:32
uint16_t tsi_group3_cycle_get ( void )

get the cycle number for group3 as soon as a charge-transfer sequence completes

Parameters
[in] | none
[out] | none
Return values
group3 cycle number

Definition at line 627 of file gd32f3x0_tsi.c.

628 {
629 return (uint16_t)TSI_G3CYCN;
630 }
TSI_G3CYCN
#define TSI_G3CYCN
Definition: gd32f3x0_tsi.h:33
uint16_t tsi_group4_cycle_get ( void )

get the cycle number for group4 as soon as a charge-transfer sequence completes

Parameters
[in] | none
[out] | none
Return values
group4 cycle number

Definition at line 638 of file gd32f3x0_tsi.c.

639 {
640 return (uint16_t)TSI_G4CYCN;
641 }
TSI_G4CYCN
#define TSI_G4CYCN
Definition: gd32f3x0_tsi.h:34
uint16_t tsi_group5_cycle_get ( void )

get the cycle number for group5 as soon as a charge-transfer sequence completes

Parameters
[in] | none
[out] | none
Return values
group5 cycle number

Definition at line 649 of file gd32f3x0_tsi.c.

650 {
651 return (uint16_t)TSI_G5CYCN;
652 }
TSI_G5CYCN
#define TSI_G5CYCN
Definition: gd32f3x0_tsi.h:35
void tsi_group_disable ( uint32_t group )

disbale group

Parameters
[in] group select group to be disabled
  • TSI_GCTL_GEx(x=0..5):the x group will be disabled
[out] none
Return values
none

Definition at line 565 of file gd32f3x0_tsi.c.

566 {
567 TSI_GCTL &= ~group;
568 }
TSI_GCTL
#define TSI_GCTL
Definition: gd32f3x0_tsi.h:29
void tsi_group_enable ( uint32_t group )

enbale group

Parameters
[in] group select group to be enabled
  • TSI_GCTL_GEx(x=0..5): the x group will be enabled
[out] none
Return values
none

Definition at line 553 of file gd32f3x0_tsi.c.

554 {
555 TSI_GCTL |= group;
556 }
TSI_GCTL
#define TSI_GCTL
Definition: gd32f3x0_tsi.h:29
FlagStatus tsi_group_status_get ( uint32_t group )

get group complete status

Parameters
[in] group select group
  • TSI_GCTL_GCx(x=0..5): get the complete status of group x
[out] none
Return values
FlagStatus group complete status,SET or RESET

Definition at line 577 of file gd32f3x0_tsi.c.

578 {
579 FlagStatus flag_status;
580 if(TSI_GCTL & group){
581 flag_status = SET;
582 }else{
583 flag_status = RESET;
584 }
585 return flag_status;
586 }
TSI_GCTL
#define TSI_GCTL
Definition: gd32f3x0_tsi.h:29
void tsi_hardware_mode_config ( uint8_t trigger_edge )

configure TSI triggering by hardware

Parameters
[in] trigger_edge the edge type in hardware trigger mode
  • TSI_FALLING_TRIGGER: falling edge trigger TSI charge transfer sequence
  • TSI_RISING_TRIGGER: rising edge trigger TSI charge transfer sequence
[out] none
Return values
none

Definition at line 225 of file gd32f3x0_tsi.c.

226 {
227 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
228 /*enable hardware mode*/
229 TSI_CTL0 |= TSI_CTL0_TRGMOD;
230 /*configure the edge type in hardware trigger mode*/
231 if(TSI_FALLING_TRIGGER == trigger_edge){
232 TSI_CTL0 &= ~TSI_CTL0_EGSEL;
233 }else{
234 TSI_CTL0 |= TSI_CTL0_EGSEL;
235 }
236 }
237 }
TSI_CTL0_EGSEL
#define TSI_CTL0_EGSEL
Definition: gd32f3x0_tsi.h:43
TSI_CTL0_TRGMOD
#define TSI_CTL0_TRGMOD
Definition: gd32f3x0_tsi.h:42
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
TSI_FALLING_TRIGGER
#define TSI_FALLING_TRIGGER
Definition: gd32f3x0_tsi.h:288
void tsi_hysteresis_off ( uint32_t group_pin )

switch off hysteresis pin

Parameters
[in] group_pin select pin which will be switched off hysteresis
  • TSI_PHM_GxPy(x=0..5,y=0..3): pin y of group x switch off hysteresis
[out] none
Return values
none

Definition at line 517 of file gd32f3x0_tsi.c.

518 {
519 TSI_PHM &= ~group_pin;
520 }
TSI_PHM
#define TSI_PHM
Definition: gd32f3x0_tsi.h:25
void tsi_hysteresis_on ( uint32_t group_pin )

switch on hysteresis pin

Parameters
[in] group_pin select pin which will be switched on hysteresis
  • TSI_PHM_GxPy(x=0..5,y=0..3): pin y of group x switch on hysteresis
[out] none
Return values
none

Definition at line 505 of file gd32f3x0_tsi.c.

506 {
507 TSI_PHM |= group_pin;
508 }
TSI_PHM
#define TSI_PHM
Definition: gd32f3x0_tsi.h:25
void tsi_init | ( | uint32_t | prescaler,
 |  | uint32_t | charge_duration,
 |  | uint32_t | transfer_duration,
 |  | uint32_t | max_number
 | ) |  |

initialize TSI plus prescaler,charge plus,transfer plus,max cycle number

Parameters
[in] prescaler CTCLK clock division factor
  • TSI_CTCDIV_DIV1: fCTCLK = fHCLK
  • TSI_CTCDIV_DIV2: fCTCLK = fHCLK/2
  • TSI_CTCDIV_DIV4: fCTCLK = fHCLK/4
  • TSI_CTCDIV_DIV8: fCTCLK = fHCLK/8
  • TSI_CTCDIV_DIV16: fCTCLK = fHCLK/16
  • TSI_CTCDIV_DIV32: fCTCLK = fHCLK/32
  • TSI_CTCDIV_DIV64: fCTCLK = fHCLK/64
  • TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128
  • TSI_CTCDIV_DIV256: fCTCLK = fHCLK/256
  • TSI_CTCDIV_DIV512: fCTCLK = fHCLK/512
  • TSI_CTCDIV_DIV1024: fCTCLK = fHCLK/1024
  • TSI_CTCDIV_DIV2048: fCTCLK = fHCLK/2048
  • TSI_CTCDIV_DIV4096: fCTCLK = fHCLK/4096
  • TSI_CTCDIV_DIV8192: fCTCLK = fHCLK/8192
  • TSI_CTCDIV_DIV16384: fCTCLK = fHCLK/16384
  • TSI_CTCDIV_DIV32768: fCTCLK = fHCLK/32768
[in] charge_duration charge state duration time
  • TSI_CHARGE_1CTCLK(x=1..16): the duration time of charge state is x CTCLK
[in] transfer_duration charge transfer state duration time
  • TSI_TRANSFER_xCTCLK(x=1..16): the duration time of transfer state is x CTCLK
[in] max_number max cycle number
  • TSI_MAXNUM255: the max cycle number of a sequence is 255
  • TSI_MAXNUM511: the max cycle number of a sequence is 511
  • TSI_MAXNUM1023: the max cycle number of a sequence is 1023
  • TSI_MAXNUM2047: the max cycle number of a sequence is 2047
  • TSI_MAXNUM4095: the max cycle number of a sequence is 4095
  • TSI_MAXNUM8191: the max cycle number of a sequence is 8191
  • TSI_MAXNUM16383: the max cycle number of a sequence is 16383
[out] none
Return values
none

Definition at line 60 of file gd32f3x0_tsi.c.

61 {
62 uint32_t ctl0,ctl1;
63 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
64 if(TSI_CTCDIV_DIV256 > prescaler){
65 /* config TSI_CTL0 */
66 ctl0 = TSI_CTL0;
67 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
68 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT|TSI_CTL0_MCN);
69 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration|max_number);
70 TSI_CTL0 = ctl0;
71
72 /* config TSI_CTL1 */
73 ctl1 = TSI_CTL1;
74 ctl1 &= ~TSI_CTL1_CTCDIV;
75 TSI_CTL1 = ctl1;
76 }else{
77 /* config TSI_CTL0 */
78 ctl0 = TSI_CTL0;
79 prescaler &= ~0x08U;
80 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
81 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT|TSI_CTL0_MCN);
82 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration|max_number);
83 TSI_CTL0 = ctl0;
84
85 /* config TSI_CTL1 */
86 ctl1 = TSI_CTL1;
87 ctl1 |= TSI_CTL1_CTCDIV;
88 TSI_CTL1 = ctl1;
89 }
90 }
91 }
TSI_CTL0_CTCDIV
#define TSI_CTL0_CTCDIV
Definition: gd32f3x0_tsi.h:46
TSI_CTL0_MCN
#define TSI_CTL0_MCN
Definition: gd32f3x0_tsi.h:45
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_CDT
#define TSI_CTL0_CDT
Definition: gd32f3x0_tsi.h:51
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
TSI_CTCDIV_DIV256
#define TSI_CTCDIV_DIV256
Definition: gd32f3x0_tsi.h:217
TSI_CTL1_CTCDIV
#define TSI_CTL1_CTCDIV
Definition: gd32f3x0_tsi.h:204
TSI_CTL0_CTDT
#define TSI_CTL0_CTDT
Definition: gd32f3x0_tsi.h:50
TSI_CTL1
#define TSI_CTL1
Definition: gd32f3x0_tsi.h:36
void tsi_interrupt_disable ( uint32_t source )

disable TSI interrupt

Parameters
[in] source select interrupt which will be disabled
  • TSI_INT_CCTCF: charge-transfer complete flag interrupt disable
  • TSI_INT_MNERR: max cycle number error interrupt disable
[out] none
Return values
none

Definition at line 409 of file gd32f3x0_tsi.c.

410 {
411 TSI_INTEN &= ~source;
412 }
TSI_INTEN
#define TSI_INTEN
Definition: gd32f3x0_tsi.h:22
void tsi_interrupt_enable ( uint32_t source )

enable TSI interrupt

Parameters
[in] source select interrupt which will be enabled
  • TSI_INT_CCTCF: charge-transfer complete flag interrupt enable
  • TSI_INT_MNERR: max cycle number error interrupt enable
[out] none
Return values
none

Definition at line 396 of file gd32f3x0_tsi.c.

397 {
398 TSI_INTEN |= source;
399 }
TSI_INTEN
#define TSI_INTEN
Definition: gd32f3x0_tsi.h:22
void tsi_interrupt_flag_clear ( uint32_t flag )

clear TSI interrupt flag

Parameters
[in] source select flag which will be cleared
  • TSI_INT_FLAG_CTCF_CLR: clear charge-transfer complete flag
  • TSI_INT_FLAG_MNERR_CLR: clear max cycle number error
[out] none
Return values
none

Definition at line 422 of file gd32f3x0_tsi.c.

423 {
424 TSI_INTC |= flag;
425 }
TSI_INTC
#define TSI_INTC
Definition: gd32f3x0_tsi.h:23
FlagStatus tsi_interrupt_flag_get ( uint32_t flag )

get TSI interrupt flag

Parameters
[in] status
  • TSI_INT_FLAG_CTCF: charge-transfer complete flag
  • TSI_INT_FLAG_MNERR: max Cycle Number Error
[out] none
Return values
FlagStatus:SET or RESET

Definition at line 435 of file gd32f3x0_tsi.c.

436 {
437 FlagStatus flag_status;
438 uint32_t tsi_inten;
439 tsi_inten = TSI_INTEN;
440 if(TSI_INT_FLAG_CTCF == flag){
441 if(TSI_INT_CCTCF & tsi_inten){
442 if(TSI_INTF & flag){
443 flag_status = SET;
444 }else{
445 flag_status = RESET;
446 }
447 }else{
448 flag_status = RESET;
449 }
450 }else if(TSI_INT_FLAG_MNERR == flag){
451 if(TSI_INT_MNERR & tsi_inten){
452 if(TSI_INTF & flag){
453 flag_status = SET;
454 }else{
455 flag_status = RESET;
456 }
457 }else{
458 flag_status = RESET;
459 }
460 }else{
461 flag_status = RESET;
462 }
463 return flag_status;
464 }
TSI_INTEN
#define TSI_INTEN
Definition: gd32f3x0_tsi.h:22
TSI_INT_MNERR
#define TSI_INT_MNERR
Definition: gd32f3x0_tsi.h:67
TSI_INTF
#define TSI_INTF
Definition: gd32f3x0_tsi.h:24
TSI_INT_CCTCF
#define TSI_INT_CCTCF
Definition: gd32f3x0_tsi.h:66
TSI_INT_FLAG_MNERR
#define TSI_INT_FLAG_MNERR
Definition: gd32f3x0_tsi.h:71
TSI_INT_FLAG_CTCF
#define TSI_INT_FLAG_CTCF
Definition: gd32f3x0_tsi.h:70
void tsi_max_number_config ( uint32_t max_number )

configure the max cycle number of a charge-transfer sequence

Parameters
[in] max_number max cycle number
  • TSI_MAXNUM255: the max cycle number of a sequence is 255
  • TSI_MAXNUM511: the max cycle number of a sequence is 511
  • TSI_MAXNUM1023: the max cycle number of a sequence is 1023
  • TSI_MAXNUM2047: the max cycle number of a sequence is 2047
  • TSI_MAXNUM4095: the max cycle number of a sequence is 4095
  • TSI_MAXNUM8191: the max cycle number of a sequence is 8191
  • TSI_MAXNUM16383: the max cycle number of a sequence is 16383
[out] none
Return values
none

Definition at line 271 of file gd32f3x0_tsi.c.

272 {
273 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
274 uint32_t maxnum;
275 maxnum = TSI_CTL0;
276 /*configure the max cycle number of a charge-transfer sequence*/
277 maxnum &= ~TSI_CTL0_MCN;
278 maxnum |= max_number;
279 TSI_CTL0 = maxnum;
280 }
281 }
TSI_CTL0_MCN
#define TSI_CTL0_MCN
Definition: gd32f3x0_tsi.h:45
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
void tsi_pin_mode_config ( uint8_t pin_mode )

configure TSI pin mode when charge-transfer sequence is IDLE

Parameters
[in] pin_mode pin mode when charge-transfer sequence is IDLE
  • TSI_OUTPUT_LOW: TSI pin will output low when IDLE
  • TSI_INPUT_FLOATING: TSI pin will keep input_floating when IDLE
[out] none
Return values
none

Definition at line 247 of file gd32f3x0_tsi.c.

248 {
249 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
250 if(TSI_OUTPUT_LOW == pin_mode){
251 TSI_CTL0 &= ~TSI_CTL0_PINMOD;
252 }else{
253 TSI_CTL0 |= TSI_CTL0_PINMOD;
254 }
255 }
256 }
TSI_OUTPUT_LOW
#define TSI_OUTPUT_LOW
Definition: gd32f3x0_tsi.h:292
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_PINMOD
#define TSI_CTL0_PINMOD
Definition: gd32f3x0_tsi.h:44
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
void tsi_plus_config | ( | uint32_t | prescaler,
 |  | uint32_t | charge_duration,
 |  | uint32_t | transfer_duration
 | ) |  |

configure charge plus and transfer plus

Parameters
[in] prescaler CTCLK clock division factor
  • TSI_CTCDIV_DIV1: fCTCLK = fHCLK
  • TSI_CTCDIV_DIV2: fCTCLK = fHCLK/2
  • TSI_CTCDIV_DIV4: fCTCLK = fHCLK/4
  • TSI_CTCDIV_DIV8: fCTCLK = fHCLK/8
  • TSI_CTCDIV_DIV16: fCTCLK = fHCLK/16
  • TSI_CTCDIV_DIV32: fCTCLK = fHCLK/32
  • TSI_CTCDIV_DIV64: fCTCLK = fHCLK/64
  • TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128
  • TSI_CTCDIV_DIV256: fCTCLK = fHCLK/256
  • TSI_CTCDIV_DIV512: fCTCLK = fHCLK/512
  • TSI_CTCDIV_DIV1024: fCTCLK = fHCLK/1024
  • TSI_CTCDIV_DIV2048: fCTCLK = fHCLK/2048
  • TSI_CTCDIV_DIV4096: fCTCLK = fHCLK/4096
  • TSI_CTCDIV_DIV8192: fCTCLK = fHCLK/8192
  • TSI_CTCDIV_DIV16384: fCTCLK = fHCLK/16384
  • TSI_CTCDIV_DIV32768: fCTCLK = fHCLK/32768
[in] charge_duration charge state duration time
  • TSI_CHARGE_xCTCLK(x=1..16): the duration time of charge state is x CTCLK
[in] transfer_duration charge transfer state duration time
  • TSI_TRANSFER_xCTCLK(x=1..16): the duration time of transfer state is x CTCLK
[out] none
Return values
none

Definition at line 171 of file gd32f3x0_tsi.c.

172 {
173 uint32_t ctl0,ctl1;
174 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
175 if(TSI_CTCDIV_DIV256 > prescaler){
176 /* config TSI_CTL0 */
177 ctl0 = TSI_CTL0;
178 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
179 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT);
180 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration);
181 TSI_CTL0 = ctl0;
182
183 /* config TSI_CTL1 */
184 ctl1 = TSI_CTL1;
185 ctl1 &= ~TSI_CTL1_CTCDIV;
186 TSI_CTL1 = ctl1;
187 }else{
188 /* config TSI_CTL */
189 ctl0 = TSI_CTL0;
190 prescaler &= ~0x08U;
191 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
192 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT);
193 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration);
194 TSI_CTL0 = ctl0;
195
196 /* config TSI_CTL2 */
197 ctl1 = TSI_CTL1;
198 ctl1 |= TSI_CTL1_CTCDIV;
199 TSI_CTL1 = ctl1;
200 }
201 }
202 }
TSI_CTL0_CTCDIV
#define TSI_CTL0_CTCDIV
Definition: gd32f3x0_tsi.h:46
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_CDT
#define TSI_CTL0_CDT
Definition: gd32f3x0_tsi.h:51
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
TSI_CTCDIV_DIV256
#define TSI_CTCDIV_DIV256
Definition: gd32f3x0_tsi.h:217
TSI_CTL1_CTCDIV
#define TSI_CTL1_CTCDIV
Definition: gd32f3x0_tsi.h:204
TSI_CTL0_CTDT
#define TSI_CTL0_CTDT
Definition: gd32f3x0_tsi.h:50
TSI_CTL1
#define TSI_CTL1
Definition: gd32f3x0_tsi.h:36
void tsi_sample_pin_disable ( uint32_t sample )

disable sample pin

Parameters
[in] sample sample pin
  • TSI_SAMPCFG_GxPy( x=0..5,y=0..3): pin y of group x is sample pin
[out] none
Return values
none

Definition at line 114 of file gd32f3x0_tsi.c.

115 {
116 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
117 TSI_SAMPCFG &= ~sample;
118 }
119 }
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_SAMPCFG
#define TSI_SAMPCFG
Definition: gd32f3x0_tsi.h:27
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
void tsi_sample_pin_enable ( uint32_t sample )

enable sample pin

Parameters
[in] sample sample pin
  • TSI_SAMPCFG_GxPy( x=0..5,y=0..3):pin y of group x is sample pin
[out] none
Return values
none

Definition at line 100 of file gd32f3x0_tsi.c.

101 {
102 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
103 TSI_SAMPCFG |= sample;
104 }
105 }
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_SAMPCFG
#define TSI_SAMPCFG
Definition: gd32f3x0_tsi.h:27
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
void tsi_sofeware_mode_config ( void )

configure TSI triggering by software

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 210 of file gd32f3x0_tsi.c.

211 {
212 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
213 TSI_CTL0 &= ~TSI_CTL0_TRGMOD;
214 }
215 }
TSI_CTL0_TRGMOD
#define TSI_CTL0_TRGMOD
Definition: gd32f3x0_tsi.h:42
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
void tsi_software_start ( void )

start a charge-transfer sequence when TSI is in software trigger mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 289 of file gd32f3x0_tsi.c.

290 {
291 TSI_CTL0 |= TSI_CTL0_TSIS;
292 }
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
void tsi_software_stop ( void )

stop a charge-transfer sequence when TSI is in software trigger mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 300 of file gd32f3x0_tsi.c.

301 {
302 TSI_CTL0 &= ~TSI_CTL0_TSIS;
303 }
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_usart.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Enumerations | Functions
gd32f3x0_usart.h File Reference

definitions for the USART More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | USART0 (USART_BASE + 0x0000F400U)
#define | USART1 USART_BASE
#define | USART_CTL0(usartx) REG32((usartx) + 0x00U)
#define | USART_CTL1(usartx) REG32((usartx) + 0x04U)
#define | USART_CTL2(usartx) REG32((usartx) + 0x08U)
#define | USART_BAUD(usartx) REG32((usartx) + 0x0CU)
#define | USART_GP(usartx) REG32((usartx) + 0x10U)
#define | USART_RT(usartx) REG32((usartx) + 0x14U)
#define | USART_CMD(usartx) REG32((usartx) + 0x18U)
#define | USART_STAT(usartx) REG32((usartx) + 0x1CU)
#define | USART_INTC(usartx) REG32((usartx) + 0x20U)
#define | USART_RDATA(usartx) REG32((usartx) + 0x24U)
#define | USART_TDATA(usartx) REG32((usartx) + 0x28U)
#define | USART_RFCS(usartx) REG32((usartx) + 0xD0U)
#define | USART_CTL0_UEN BIT(0)
#define | USART_CTL0_UESM BIT(1)
#define | USART_CTL0_REN BIT(2)
#define | USART_CTL0_TEN BIT(3)
#define | USART_CTL0_IDLEIE BIT(4)
#define | USART_CTL0_RBNEIE BIT(5)
#define | USART_CTL0_TCIE BIT(6)
#define | USART_CTL0_TBEIE BIT(7)
#define | USART_CTL0_PERRIE BIT(8)
#define | USART_CTL0_PM BIT(9)
#define | USART_CTL0_PCEN BIT(10)
#define | USART_CTL0_WM BIT(11)
#define | USART_CTL0_WL BIT(12)
#define | USART_CTL0_MEN BIT(13)
#define | USART_CTL0_AMIE BIT(14)
#define | USART_CTL0_OVSMOD BIT(15)
#define | USART_CTL0_DED BITS(16,20)
#define | USART_CTL0_DEA BITS(21,25)
#define | USART_CTL0_RTIE BIT(26)
#define | USART_CTL0_EBIE BIT(27)
#define | USART_CTL1_ADDM BIT(4)
#define | USART_CTL1_LBLEN BIT(5)
#define | USART_CTL1_LBDIE BIT(6)
#define | USART_CTL1_CLEN BIT(8)
#define | USART_CTL1_CPH BIT(9)
#define | USART_CTL1_CPL BIT(10)
#define | USART_CTL1_CKEN BIT(11)
#define | USART_CTL1_STB BITS(12,13)
#define | USART_CTL1_LMEN BIT(14)
#define | USART_CTL1_STRP BIT(15)
#define | USART_CTL1_RINV BIT(16)
#define | USART_CTL1_TINV BIT(17)
#define | USART_CTL1_DINV BIT(18)
#define | USART_CTL1_MSBF BIT(19)
#define | USART_CTL1_ABDEN BIT(20)
#define | USART_CTL1_ABDM BITS(21,22)
#define | USART_CTL1_RTEN BIT(23)
#define | USART_CTL1_ADDR BITS(24,31)
#define | USART_CTL2_ERRIE BIT(0)
#define | USART_CTL2_IREN BIT(1)
#define | USART_CTL2_IRLP BIT(2)
#define | USART_CTL2_HDEN BIT(3)
#define | USART_CTL2_NKEN BIT(4)
#define | USART_CTL2_SCEN BIT(5)
#define | USART_CTL2_DENR BIT(6)
#define | USART_CTL2_DENT BIT(7)
#define | USART_CTL2_RTSEN BIT(8)
#define | USART_CTL2_CTSEN BIT(9)
#define | USART_CTL2_CTSIE BIT(10)
#define | USART_CTL2_OSB BIT(11)
#define | USART_CTL2_OVRD BIT(12)
#define | USART_CTL2_DDRE BIT(13)
#define | USART_CTL2_DEM BIT(14)
#define | USART_CTL2_DEP BIT(15)
#define | USART_CTL2_SCRTNUM BITS(17,19)
#define | USART_CTL2_WUM BITS(20,21)
#define | USART_CTL2_WUIE BIT(22)
#define | USART_BAUD_FRADIV BITS(0,3)
#define | USART_BAUD_INTDIV BITS(4,15)
#define | USART_GP_PSC BITS(0,7)
#define | USART_GP_GUAT BITS(8,15)
#define | USART_RT_RT BITS(0,23)
#define | USART_RT_BL BITS(24,31)
#define | USART_CMD_ABDCMD BIT(0)
#define | USART_CMD_SBKCMD BIT(1)
#define | USART_CMD_MMCMD BIT(2)
#define | USART_CMD_RXFCMD BIT(3)
#define | USART_CMD_TXFCMD BIT(4)
#define | USART_STAT_PERR BIT(0)
#define | USART_STAT_FERR BIT(1)
#define | USART_STAT_NERR BIT(2)
#define | USART_STAT_ORERR BIT(3)
#define | USART_STAT_IDLEF BIT(4)
#define | USART_STAT_RBNE BIT(5)
#define | USART_STAT_TC BIT(6)
#define | USART_STAT_TBE BIT(7)
#define | USART_STAT_LBDF BIT(8)
#define | USART_STAT_CTSF BIT(9)
#define | USART_STAT_CTS BIT(10)
#define | USART_STAT_RTF BIT(11)
#define | USART_STAT_EBF BIT(12)
#define | USART_STAT_ABDE BIT(14)
#define | USART_STAT_ABDF BIT(15)
#define | USART_STAT_BSY BIT(16)
#define | USART_STAT_AMF BIT(17)
#define | USART_STAT_SBF BIT(18)
#define | USART_STAT_RWU BIT(19)
#define | USART_STAT_WUF BIT(20)
#define | USART_STAT_TEA BIT(21)
#define | USART_STAT_REA BIT(22)
#define | USART_INTC_PEC BIT(0)
#define | USART_INTC_FEC BIT(1)
#define | USART_INTC_NEC BIT(2)
#define | USART_INTC_OREC BIT(3)
#define | USART_INTC_IDLEC BIT(4)
#define | USART_INTC_TCC BIT(6)
#define | USART_INTC_LBDC BIT(8)
#define | USART_INTC_CTSC BIT(9)
#define | USART_INTC_RTC BIT(11)
#define | USART_INTC_EBC BIT(12)
#define | USART_INTC_AMC BIT(17)
#define | USART_INTC_WUC BIT(20)
#define | USART_RDATA_RDATA BITS(0,8)
#define | USART_TDATA_TDATA BITS(0,8)
#define | USART_RFCS_ELNACK BIT(0)
#define | USART_RFCS_RFEN BIT(8)
#define | USART_RFCS_RFFIE BIT(9)
#define | USART_RFCS_RFE BIT(10)
#define | USART_RFCS_RFF BIT(11)
#define | USART_RFCS_RFCNT BITS(12,14)
#define | USART_RFCS_RFFINT BIT(15)
#define | USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define | USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
#define | USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
#define | USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2)
#define | USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
#define | USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
#define | USART_CTL0_REG_OFFSET 0x00U
#define | USART_CTL1_REG_OFFSET 0x04U
#define | USART_CTL2_REG_OFFSET 0x08U
#define | USART_STAT_REG_OFFSET 0x1CU
#define | USART_RFCS_REG_OFFSET 0xD0U
#define | CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
#define | USART_RECEIVE_ENABLE CTL0_REN(1)
#define | USART_RECEIVE_DISABLE CTL0_REN(0)
#define | CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
#define | USART_TRANSMIT_ENABLE CTL0_TEN(1)
#define | USART_TRANSMIT_DISABLE CTL0_TEN(0)
#define | CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
#define | USART_PM_NONE CTL0_PM(0)
#define | USART_PM_EVEN CTL0_PM(2)
#define | USART_PM_ODD CTL0_PM(3)
#define | CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11))
#define | USART_WM_IDLE CTL0_WM(0)
#define | USART_WM_ADDR CTL0_WM(1)
#define | CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12))
#define | USART_WL_8BIT CTL0_WL(0)
#define | USART_WL_9BIT CTL0_WL(1)
#define | CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15))
#define | USART_OVSMOD_8 CTL0_OVSMOD(1)
#define | USART_OVSMOD_16 CTL0_OVSMOD(0)
#define | CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4))
#define | USART_ADDM_4BIT CTL1_ADDM(0)
#define | USART_ADDM_FULLBIT CTL1_ADDM(1)
#define | CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5))
#define | USART_LBLEN_10B CTL1_LBLEN(0)
#define | USART_LBLEN_11B CTL1_LBLEN(1)
#define | CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
#define | USART_CLEN_NONE CTL1_CLEN(0)
#define | USART_CLEN_EN CTL1_CLEN(1)
#define | CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9))
#define | USART_CPH_1CK CTL1_CPH(0)
#define | USART_CPH_2CK CTL1_CPH(1)
#define | CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10))
#define | USART_CPL_LOW CTL1_CPL(0)
#define | USART_CPL_HIGH CTL1_CPL(1)
#define | CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
#define | USART_STB_1BIT CTL1_STB(0)
#define | USART_STB_0_5BIT CTL1_STB(1)
#define | USART_STB_2BIT CTL1_STB(2)
#define | USART_STB_1_5BIT CTL1_STB(3)
#define | CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19))
#define | USART_MSBF_LSB CTL1_MSBF(0)
#define | USART_MSBF_MSB CTL1_MSBF(1)
#define | CTL1_ABDM(regval) (BITS(21,22) & ((uint32_t)(regval) << 21))
#define | USART_ABDM_FTOR CTL1_ABDM(0)
#define | USART_ABDM_FTOF CTL1_ABDM(1)
#define | CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
#define | USART_IRLP_LOW CTL2_IRLP(1)
#define | USART_IRLP_NORMAL CTL2_IRLP(0)
#define | CTL2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6))
#define | USART_DENR_ENABLE CTL2_DENR(1)
#define | USART_DENR_DISABLE CTL2_DENR(0)
#define | CTL2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
#define | USART_DENT_ENABLE CTL2_DENT(1)
#define | USART_DENT_DISABLE CTL2_DENT(0)
#define | CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
#define | USART_RTS_ENABLE CTL2_RTSEN(1)
#define | USART_RTS_DISABLE CTL2_RTSEN(0)
#define | CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
#define | USART_CTS_ENABLE CTL2_CTSEN(1)
#define | USART_CTS_DISABLE CTL2_CTSEN(0)
#define | CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11))
#define | USART_OSB_1BIT CTL2_OSB(1)
#define | USART_OSB_3BIT CTL2_OSB(0)
#define | CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15))
#define | USART_DEP_HIGH CTL2_DEP(0)
#define | USART_DEP_LOW CTL2_DEP(1)
#define | CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
#define | USART_WUM_ADDR CTL2_WUM(0)
#define | USART_WUM_STARTB CTL2_WUM(2)
#define | USART_WUM_RBNE CTL2_WUM(3)

Enumerations

enum usart_flag_enum {
USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U), USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U), USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U), USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U),
USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U), USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U), USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U), USART_FLAG_ABD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 15U),
USART_FLAG_ABDE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 14U), USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U), USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U), USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U),
USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U),
USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U),
USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), USART_FLAG_RFFINT = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 15U), USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U),
USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U)
}
enum usart_interrupt_flag_enum {
USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U), USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U), USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U), USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U),
USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U),
USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U), USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U),
USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), USART_INT_FLAG_RFF = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U)
}
enum usart_interrupt_enum {
USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U), USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U), USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U), USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U),
USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U),
USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U), USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U),
USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U)
}
enum usart_invert_enum {
USART_DINV_ENABLE, USART_DINV_DISABLE, USART_TXPIN_ENABLE, USART_TXPIN_DISABLE,
USART_RXPIN_ENABLE, USART_RXPIN_DISABLE, USART_SWAP_ENABLE, USART_SWAP_DISABLE
}

Functions

void | usart_deinit (uint32_t usart_periph)
reset USART More...
void | usart_baudrate_set (uint32_t usart_periph, uint32_t baudval)
configure USART baud rate value More...
void | usart_parity_config (uint32_t usart_periph, uint32_t paritycfg)
configure USART parity More...
void | usart_word_length_set (uint32_t usart_periph, uint32_t wlen)
configure USART word length More...
void | usart_stop_bit_set (uint32_t usart_periph, uint32_t stblen)
configure USART stop bit length More...
void | usart_enable (uint32_t usart_periph)
enable USART More...
void | usart_disable (uint32_t usart_periph)
disable USART More...
void | usart_transmit_config (uint32_t usart_periph, uint32_t txconfig)
configure USART transmitter More...
void | usart_receive_config (uint32_t usart_periph, uint32_t rxconfig)
configure USART receiver More...
void | usart_data_transmit (uint32_t usart_periph, uint32_t data)
USART transmit data function. More...
uint16_t | usart_data_receive (uint32_t usart_periph)
USART receive data function. More...
void | usart_data_first_config (uint32_t usart_periph, uint32_t msbf)
data is transmitted/received with the LSB/MSB first More...
void | usart_invert_config (uint32_t usart_periph, usart_invert_enum invertpara)
USART inverted configure. More...
void | usart_overrun_enable (uint32_t usart_periph)
overrun function is enabled More...
void | usart_overrun_disable (uint32_t usart_periph)
overrun function is disabled More...
void | usart_oversample_config (uint32_t usart_periph, uint32_t oversamp)
configure the USART oversample mode More...
void | usart_sample_bit_config (uint32_t usart_periph, uint32_t osb)
sample bit method configure More...
void | usart_autobaud_detection_enable (uint32_t usart_periph)
auto baud rate detection enable More...
void | usart_autobaud_detection_disable (uint32_t usart_periph)
auto baud rate detection disable More...
void | usart_autobaud_detection_mode_config (uint32_t usart_periph, uint32_t abdmod)
auto baud rate detection mode configure More...
void | usart_mute_mode_enable (uint32_t usart_periph)
mute mode enable More...
void | usart_mute_mode_disable (uint32_t usart_periph)
mute mode disable More...
void | usart_mute_mode_wakeup_config (uint32_t usart_periph, uint32_t wmethod)
wakeup method in mute mode configure More...
void | usart_address_detection_mode_config (uint32_t usart_periph, uint32_t addmod)
address detection mode configure More...
void | usart_address_config (uint32_t usart_periph, uint8_t addr)
address of the USART terminal More...
void | usart_receiver_timeout_enable (uint32_t usart_periph)
receiver timeout enable More...
void | usart_receiver_timeout_disable (uint32_t usart_periph)
receiver timeout disable More...
void | usart_receiver_timeout_config (uint32_t usart_periph, uint32_t rtimeout)
receiver timeout threshold configure More...
void | usart_lin_mode_enable (uint32_t usart_periph)
LIN mode enable. More...
void | usart_lin_mode_disable (uint32_t usart_periph)
LIN mode disable. More...
void | usart_lin_break_dection_length_config (uint32_t usart_periph, uint32_t lblen)
LIN break detection length. More...
void | usart_halfduplex_enable (uint32_t usart_periph)
half-duplex enable More...
void | usart_halfduplex_disable (uint32_t usart_periph)
half-duplex disable More...
void | usart_clock_enable (uint32_t usart_periph)
clock enable More...
void | usart_clock_disable (uint32_t usart_periph)
clock disable More...
void | usart_synchronous_clock_config (uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
configure USART synchronous mode parameters More...
void | usart_smartcard_mode_enable (uint32_t usart_periph)
smartcard mode enable More...
void | usart_smartcard_mode_disable (uint32_t usart_periph)
smartcard mode disable More...
void | usart_smartcard_mode_nack_enable (uint32_t usart_periph)
NACK enable in smartcard mode. More...
void | usart_smartcard_mode_nack_disable (uint32_t usart_periph)
NACK disable in smartcard mode. More...
void | usart_guard_time_config (uint32_t usart_periph, uint32_t guat)
guard time value configure in smartcard mode More...
void | usart_block_length_config (uint32_t usart_periph, uint32_t bl)
block length configure More...
void | usart_smartcard_autoretry_config (uint32_t usart_periph, uint32_t scrtnum)
smartcard auto-retry number configure More...
void | usart_smartcard_mode_early_nack_enable (uint32_t usart_periph)
early NACK enable in smartcard mode More...
void | usart_smartcard_mode_early_nack_disable (uint32_t usart_periph)
early NACK disable in smartcard mode More...
void | usart_irda_mode_enable (uint32_t usart_periph)
IrDA mode enable. More...
void | usart_irda_mode_disable (uint32_t usart_periph)
IrDA mode disable. More...
void | usart_irda_lowpower_config (uint32_t usart_periph, uint32_t irlp)
IrDA low-power configure. More...
void | usart_prescaler_config (uint32_t usart_periph, uint32_t psc)
configure the peripheral clock prescaler in USART IrDA low-power mode More...
void | usart_hardware_flow_rts_config (uint32_t usart_periph, uint32_t rtsconfig)
configure hardware flow control RTS More...
void | usart_hardware_flow_cts_config (uint32_t usart_periph, uint32_t ctsconfig)
configure hardware flow control CTS More...
void | usart_rs485_driver_enable (uint32_t usart_periph)
RS485 driver enable. More...
void | usart_rs485_driver_disable (uint32_t usart_periph)
RS485 driver disable. More...
void | usart_driver_assertime_config (uint32_t usart_periph, uint32_t deatime)
driver enable assertion time configure More...
void | usart_driver_deassertime_config (uint32_t usart_periph, uint32_t dedtime)
driver enable de-assertion time configure More...
void | usart_depolarity_config (uint32_t usart_periph, uint32_t dep)
configure driver enable polarity mode More...
void | usart_dma_receive_config (uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA reception More...
void | usart_dma_transmit_config (uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA transmission More...
void | usart_reception_error_dma_disable (uint32_t usart_periph)
disable DMA on reception error More...
void | usart_reception_error_dma_enable (uint32_t usart_periph)
enable DMA on reception error More...
void | usart_wakeup_enable (uint32_t usart_periph)
USART be able to wake up the MCU from deep-sleep mode. More...
void | usart_wakeup_disable (uint32_t usart_periph)
USART be not able to wake up the MCU from deep-sleep mode. More...
void | usart_wakeup_mode_config (uint32_t usart_periph, uint32_t wum)
wakeup mode from deep-sleep mode More...
void | usart_receive_fifo_enable (uint32_t usart_periph)
receive FIFO enable More...
void | usart_receive_fifo_disable (uint32_t usart_periph)
receive FIFO disable More...
uint8_t | usart_receive_fifo_counter_number (uint32_t usart_periph)
read receive FIFO counter number More...
FlagStatus | usart_flag_get (uint32_t usart_periph, usart_flag_enum flag)
get flag in STAT/RFCS register More...
void | usart_flag_clear (uint32_t usart_periph, usart_flag_enum flag)
clear USART status More...
void | usart_interrupt_enable (uint32_t usart_periph, uint32_t inttype)
enable USART interrupt More...
void | usart_interrupt_disable (uint32_t usart_periph, uint32_t inttype)
disable USART interrupt More...
void | usart_command_enable (uint32_t usart_periph, uint32_t cmdtype)
enable USART command More...
FlagStatus | usart_interrupt_flag_get (uint32_t usart_periph, uint32_t int_flag)
get USART interrupt and flag status More...
void | usart_interrupt_flag_clear (uint32_t usart_periph, uint32_t flag)
clear USART interrupt flag More...

Detailed Description

definitions for the USART

Definition in file gd32f3x0_usart.h.

Macro Definition Documentation

#define CTL0_OVSMOD ( regval ) (BIT(15) & ((uint32_t)(regval) << 15))

Definition at line 310 of file gd32f3x0_usart.h.

#define CTL0_PM ( regval ) (BITS(9,10) & ((uint32_t)(regval) << 9))

Definition at line 294 of file gd32f3x0_usart.h.

#define CTL0_REN ( regval ) (BIT(2) & ((uint32_t)(regval) << 2))

Definition at line 284 of file gd32f3x0_usart.h.

#define CTL0_TEN ( regval ) (BIT(3) & ((uint32_t)(regval) << 3))

Definition at line 289 of file gd32f3x0_usart.h.

#define CTL0_WL ( regval ) (BIT(12) & ((uint32_t)(regval) << 12))

Definition at line 305 of file gd32f3x0_usart.h.

#define CTL0_WM ( regval ) (BIT(11) & ((uint32_t)(regval) << 11))

Definition at line 300 of file gd32f3x0_usart.h.

#define CTL1_ABDM ( regval ) (BITS(21,22) & ((uint32_t)(regval) << 21))

Definition at line 352 of file gd32f3x0_usart.h.

#define CTL1_ADDM ( regval ) (BIT(4) & ((uint32_t)(regval) << 4))

Definition at line 315 of file gd32f3x0_usart.h.

#define CTL1_CLEN ( regval ) (BIT(8) & ((uint32_t)(regval) << 8))

Definition at line 325 of file gd32f3x0_usart.h.

#define CTL1_CPH ( regval ) (BIT(9) & ((uint32_t)(regval) << 9))

Definition at line 330 of file gd32f3x0_usart.h.

#define CTL1_CPL ( regval ) (BIT(10) & ((uint32_t)(regval) << 10))

Definition at line 335 of file gd32f3x0_usart.h.

#define CTL1_LBLEN ( regval ) (BIT(5) & ((uint32_t)(regval) << 5))

Definition at line 320 of file gd32f3x0_usart.h.

#define CTL1_MSBF ( regval ) (BIT(19) & ((uint32_t)(regval) << 19))

Definition at line 347 of file gd32f3x0_usart.h.

#define CTL1_STB ( regval ) (BITS(12,13) & ((uint32_t)(regval) << 12))

Definition at line 340 of file gd32f3x0_usart.h.

#define CTL2_CTSEN ( regval ) (BIT(9) & ((uint32_t)(regval) << 9))

Definition at line 377 of file gd32f3x0_usart.h.

#define CTL2_DENR ( regval ) (BIT(6) & ((uint32_t)(regval) << 6))

Definition at line 362 of file gd32f3x0_usart.h.

#define CTL2_DENT ( regval ) (BIT(7) & ((uint32_t)(regval) << 7))

Definition at line 367 of file gd32f3x0_usart.h.

#define CTL2_DEP ( regval ) (BIT(15) & ((uint32_t)(regval) << 15))

Definition at line 387 of file gd32f3x0_usart.h.

#define CTL2_IRLP ( regval ) (BIT(2) & ((uint32_t)(regval) << 2))

Definition at line 357 of file gd32f3x0_usart.h.

#define CTL2_OSB ( regval ) (BIT(11) & ((uint32_t)(regval) << 11))

Definition at line 382 of file gd32f3x0_usart.h.

#define CTL2_RTSEN ( regval ) (BIT(8) & ((uint32_t)(regval) << 8))

Definition at line 372 of file gd32f3x0_usart.h.

#define CTL2_WUM ( regval ) (BITS(20,21) & ((uint32_t)(regval) << 20))

Definition at line 392 of file gd32f3x0_usart.h.

#define USART0 (USART_BASE + 0x0000F400U)

Definition at line 18 of file gd32f3x0_usart.h.

#define USART1 USART_BASE

Definition at line 19 of file gd32f3x0_usart.h.

#define USART_ABDM_FTOF CTL1_ABDM(1)

falling edge to falling edge measurement

Definition at line 354 of file gd32f3x0_usart.h.

#define USART_ABDM_FTOR CTL1_ABDM(0)

falling edge to rising edge measurement

Definition at line 353 of file gd32f3x0_usart.h.

#define USART_ADDM_4BIT CTL1_ADDM(0)

4-bit address detection

Definition at line 316 of file gd32f3x0_usart.h.

#define USART_ADDM_FULLBIT CTL1_ADDM(1)

full-bit address detection

Definition at line 317 of file gd32f3x0_usart.h.

#define USART_BAUD ( usartx ) REG32((usartx) + 0x0CU)

USART baud rate register

Definition at line 25 of file gd32f3x0_usart.h.

#define USART_BAUD_FRADIV BITS(0,3)

fraction of baud-rate divider

Definition at line 100 of file gd32f3x0_usart.h.

#define USART_BAUD_INTDIV BITS(4,15)

integer of baud-rate divider

Definition at line 101 of file gd32f3x0_usart.h.

#define USART_BIT_POS ( val ) ((uint32_t)(val) & 0x1FU)

Definition at line 176 of file gd32f3x0_usart.h.

#define USART_BIT_POS2 ( val ) (((uint32_t)(val) & 0x1F0000U) >> 16)

Definition at line 180 of file gd32f3x0_usart.h.

#define USART_CLEN_EN CTL1_CLEN(1)

clock pulse of the last data bit (MSB) is output to the CK pin

Definition at line 327 of file gd32f3x0_usart.h.

#define USART_CLEN_NONE CTL1_CLEN(0)

clock pulse of the last data bit (MSB) is not output to the CK pin

Definition at line 326 of file gd32f3x0_usart.h.

#define USART_CMD ( usartx ) REG32((usartx) + 0x18U)

USART command register

Definition at line 28 of file gd32f3x0_usart.h.

#define USART_CMD_ABDCMD BIT(0)

auto baudrate detection command

Definition at line 112 of file gd32f3x0_usart.h.

#define USART_CMD_MMCMD BIT(2)

mute mode command

Definition at line 114 of file gd32f3x0_usart.h.

#define USART_CMD_RXFCMD BIT(3)

receive data flush command

Definition at line 115 of file gd32f3x0_usart.h.

#define USART_CMD_SBKCMD BIT(1)

send break command

Definition at line 113 of file gd32f3x0_usart.h.

#define USART_CMD_TXFCMD BIT(4)

transmit data flush request

Definition at line 116 of file gd32f3x0_usart.h.

#define USART_CPH_1CK CTL1_CPH(0)

first clock transition is the first data capture edge

Definition at line 331 of file gd32f3x0_usart.h.

#define USART_CPH_2CK CTL1_CPH(1)

second clock transition is the first data capture edge

Definition at line 332 of file gd32f3x0_usart.h.

#define USART_CPL_HIGH CTL1_CPL(1)

steady high value on CK pin

Definition at line 337 of file gd32f3x0_usart.h.

#define USART_CPL_LOW CTL1_CPL(0)

steady low value on CK pin

Definition at line 336 of file gd32f3x0_usart.h.

#define USART_CTL0 ( usartx ) REG32((usartx) + 0x00U)

USART control register 0

Definition at line 22 of file gd32f3x0_usart.h.

#define USART_CTL0_AMIE BIT(14)

address match interrupt enable

Definition at line 51 of file gd32f3x0_usart.h.

#define USART_CTL0_DEA BITS(21,25)

driver enable assertion time

Definition at line 54 of file gd32f3x0_usart.h.

#define USART_CTL0_DED BITS(16,20)

driver enable deassertion time

Definition at line 53 of file gd32f3x0_usart.h.

#define USART_CTL0_EBIE BIT(27)

end of block interrupt enable

Definition at line 56 of file gd32f3x0_usart.h.

#define USART_CTL0_IDLEIE BIT(4)

idle line detected interrupt enable

Definition at line 41 of file gd32f3x0_usart.h.

#define USART_CTL0_MEN BIT(13)

mute mode enable

Definition at line 50 of file gd32f3x0_usart.h.

#define USART_CTL0_OVSMOD BIT(15)

oversample mode

Definition at line 52 of file gd32f3x0_usart.h.

#define USART_CTL0_PCEN BIT(10)

parity control enable

Definition at line 47 of file gd32f3x0_usart.h.

#define USART_CTL0_PERRIE BIT(8)

parity error interrupt enable

Definition at line 45 of file gd32f3x0_usart.h.

#define USART_CTL0_PM BIT(9)

parity mode

Definition at line 46 of file gd32f3x0_usart.h.

#define USART_CTL0_RBNEIE BIT(5)

read data buffer not empty interrupt and overrun error interrupt enable

Definition at line 42 of file gd32f3x0_usart.h.

#define USART_CTL0_REG_OFFSET 0x00U

CTL0 register offset

Definition at line 183 of file gd32f3x0_usart.h.

#define USART_CTL0_REN BIT(2)

receiver enable

Definition at line 39 of file gd32f3x0_usart.h.

#define USART_CTL0_RTIE BIT(26)

receiver timeout interrupt enable

Definition at line 55 of file gd32f3x0_usart.h.

#define USART_CTL0_TBEIE BIT(7)

transmitter register empty interrupt enable

Definition at line 44 of file gd32f3x0_usart.h.

#define USART_CTL0_TCIE BIT(6)

transmission complete interrupt enable

Definition at line 43 of file gd32f3x0_usart.h.

#define USART_CTL0_TEN BIT(3)

transmitter enable

Definition at line 40 of file gd32f3x0_usart.h.

#define USART_CTL0_UEN BIT(0)

USART enable

Definition at line 37 of file gd32f3x0_usart.h.

#define USART_CTL0_UESM BIT(1)

USART enable in deep-sleep mode

Definition at line 38 of file gd32f3x0_usart.h.

#define USART_CTL0_WL BIT(12)

word length

Definition at line 49 of file gd32f3x0_usart.h.

#define USART_CTL0_WM BIT(11)

wakeup method in mute mode

Definition at line 48 of file gd32f3x0_usart.h.

#define USART_CTL1 ( usartx ) REG32((usartx) + 0x04U)

USART control register 1

Definition at line 23 of file gd32f3x0_usart.h.

#define USART_CTL1_ABDEN BIT(20)

auto baud rate enable

Definition at line 73 of file gd32f3x0_usart.h.

#define USART_CTL1_ABDM BITS(21,22)

auto baud rate mode

Definition at line 74 of file gd32f3x0_usart.h.

#define USART_CTL1_ADDM BIT(4)

address detection mode

Definition at line 59 of file gd32f3x0_usart.h.

#define USART_CTL1_ADDR BITS(24,31)

address of the USART terminal

Definition at line 76 of file gd32f3x0_usart.h.

#define USART_CTL1_CKEN BIT(11)

ck pin enable

Definition at line 65 of file gd32f3x0_usart.h.

#define USART_CTL1_CLEN BIT(8)

last bit clock pulse

Definition at line 62 of file gd32f3x0_usart.h.

#define USART_CTL1_CPH BIT(9)

clock phase

Definition at line 63 of file gd32f3x0_usart.h.

#define USART_CTL1_CPL BIT(10)

clock polarity

Definition at line 64 of file gd32f3x0_usart.h.

#define USART_CTL1_DINV BIT(18)

data bit level inversion

Definition at line 71 of file gd32f3x0_usart.h.

#define USART_CTL1_LBDIE BIT(6)

LIN break detection interrupt enable

Definition at line 61 of file gd32f3x0_usart.h.

#define USART_CTL1_LBLEN BIT(5)

LIN break frame length

Definition at line 60 of file gd32f3x0_usart.h.

#define USART_CTL1_LMEN BIT(14)

LIN mode enable

Definition at line 67 of file gd32f3x0_usart.h.

#define USART_CTL1_MSBF BIT(19)

most significant bit first

Definition at line 72 of file gd32f3x0_usart.h.

#define USART_CTL1_REG_OFFSET 0x04U

CTL1 register offset

Definition at line 184 of file gd32f3x0_usart.h.

#define USART_CTL1_RINV BIT(16)

RX pin level inversion

Definition at line 69 of file gd32f3x0_usart.h.

#define USART_CTL1_RTEN BIT(23)

receiver timeout enable

Definition at line 75 of file gd32f3x0_usart.h.

#define USART_CTL1_STB BITS(12,13)

stop bits length

Definition at line 66 of file gd32f3x0_usart.h.

#define USART_CTL1_STRP BIT(15)

swap TX/RX pins

Definition at line 68 of file gd32f3x0_usart.h.

#define USART_CTL1_TINV BIT(17)

TX pin level inversion

Definition at line 70 of file gd32f3x0_usart.h.

#define USART_CTL2 ( usartx ) REG32((usartx) + 0x08U)

USART control register 2

Definition at line 24 of file gd32f3x0_usart.h.

#define USART_CTL2_CTSEN BIT(9)

CTS enable

Definition at line 88 of file gd32f3x0_usart.h.

#define USART_CTL2_CTSIE BIT(10)

CTS interrupt enable

Definition at line 89 of file gd32f3x0_usart.h.

#define USART_CTL2_DDRE BIT(13)

disable DMA on reception error

Definition at line 92 of file gd32f3x0_usart.h.

#define USART_CTL2_DEM BIT(14)

driver enable mode

Definition at line 93 of file gd32f3x0_usart.h.

#define USART_CTL2_DENR BIT(6)

DMA enable for reception

Definition at line 85 of file gd32f3x0_usart.h.

#define USART_CTL2_DENT BIT(7)

DMA enable for transmission

Definition at line 86 of file gd32f3x0_usart.h.

#define USART_CTL2_DEP BIT(15)

driver enable polarity mode

Definition at line 94 of file gd32f3x0_usart.h.

#define USART_CTL2_ERRIE BIT(0)

error interrupt enable in multibuffer communication

Definition at line 79 of file gd32f3x0_usart.h.

#define USART_CTL2_HDEN BIT(3)

half-duplex enable

Definition at line 82 of file gd32f3x0_usart.h.

#define USART_CTL2_IREN BIT(1)

IrDA mode enable

Definition at line 80 of file gd32f3x0_usart.h.

#define USART_CTL2_IRLP BIT(2)

IrDA low-power

Definition at line 81 of file gd32f3x0_usart.h.

#define USART_CTL2_NKEN BIT(4)

NACK enable in smartcard mode

Definition at line 83 of file gd32f3x0_usart.h.

#define USART_CTL2_OSB BIT(11)

one sample bit mode

Definition at line 90 of file gd32f3x0_usart.h.

#define USART_CTL2_OVRD BIT(12)

overrun disable

Definition at line 91 of file gd32f3x0_usart.h.

#define USART_CTL2_REG_OFFSET 0x08U

CTL2 register offset

Definition at line 185 of file gd32f3x0_usart.h.

#define USART_CTL2_RTSEN BIT(8)

RTS enable

Definition at line 87 of file gd32f3x0_usart.h.

#define USART_CTL2_SCEN BIT(5)

smartcard mode enable

Definition at line 84 of file gd32f3x0_usart.h.

#define USART_CTL2_SCRTNUM BITS(17,19)

smartcard auto-retry number

Definition at line 95 of file gd32f3x0_usart.h.

#define USART_CTL2_WUIE BIT(22)

wakeup from deep-sleep mode interrupt enable

Definition at line 97 of file gd32f3x0_usart.h.

#define USART_CTL2_WUM BITS(20,21)

wakeup mode from deep-sleep mode

Definition at line 96 of file gd32f3x0_usart.h.

#define USART_CTS_DISABLE CTL2_CTSEN(0)

CTS hardware flow control disabled

Definition at line 379 of file gd32f3x0_usart.h.

#define USART_CTS_ENABLE CTL2_CTSEN(1)

CTS hardware flow control enabled

Definition at line 378 of file gd32f3x0_usart.h.

#define USART_DENR_DISABLE CTL2_DENR(0)

disable for reception

Definition at line 364 of file gd32f3x0_usart.h.

#define USART_DENR_ENABLE CTL2_DENR(1)

enable for reception

Definition at line 363 of file gd32f3x0_usart.h.

#define USART_DENT_DISABLE CTL2_DENT(0)

disable for transmission

Definition at line 369 of file gd32f3x0_usart.h.

#define USART_DENT_ENABLE CTL2_DENT(1)

enable for transmission

Definition at line 368 of file gd32f3x0_usart.h.

#define USART_DEP_HIGH CTL2_DEP(0)

DE signal is active high

Definition at line 388 of file gd32f3x0_usart.h.

#define USART_DEP_LOW CTL2_DEP(1)

DE signal is active low

Definition at line 389 of file gd32f3x0_usart.h.

#define USART_GP ( usartx ) REG32((usartx) + 0x10U)

USART guard time and prescaler register

Definition at line 26 of file gd32f3x0_usart.h.

#define USART_GP_GUAT BITS(8,15)

guard time value in smartcard mode

Definition at line 105 of file gd32f3x0_usart.h.

#define USART_GP_PSC BITS(0,7)

prescaler value for dividing the system clock

Definition at line 104 of file gd32f3x0_usart.h.

#define USART_INTC ( usartx ) REG32((usartx) + 0x20U)

USART status clear register

Definition at line 30 of file gd32f3x0_usart.h.

#define USART_INTC_AMC BIT(17)

address match clear

Definition at line 153 of file gd32f3x0_usart.h.

#define USART_INTC_CTSC BIT(9)

CTS change clear

Definition at line 150 of file gd32f3x0_usart.h.

#define USART_INTC_EBC BIT(12)

end of timeout clear

Definition at line 152 of file gd32f3x0_usart.h.

#define USART_INTC_FEC BIT(1)

frame error flag clear

Definition at line 144 of file gd32f3x0_usart.h.

#define USART_INTC_IDLEC BIT(4)

idle line detected clear

Definition at line 147 of file gd32f3x0_usart.h.

#define USART_INTC_LBDC BIT(8)

LIN break detected clear

Definition at line 149 of file gd32f3x0_usart.h.

#define USART_INTC_NEC BIT(2)

noise detected clear

Definition at line 145 of file gd32f3x0_usart.h.

#define USART_INTC_OREC BIT(3)

overrun error clear

Definition at line 146 of file gd32f3x0_usart.h.

#define USART_INTC_PEC BIT(0)

parity error clear

Definition at line 143 of file gd32f3x0_usart.h.

#define USART_INTC_RTC BIT(11)

receiver timeout clear

Definition at line 151 of file gd32f3x0_usart.h.

#define USART_INTC_TCC BIT(6)

transmission complete clear

Definition at line 148 of file gd32f3x0_usart.h.

#define USART_INTC_WUC BIT(20)

wakeup from deep-sleep mode clear

Definition at line 154 of file gd32f3x0_usart.h.

#define USART_IRLP_LOW CTL2_IRLP(1)

low-power

Definition at line 358 of file gd32f3x0_usart.h.

#define USART_IRLP_NORMAL CTL2_IRLP(0)

normal

Definition at line 359 of file gd32f3x0_usart.h.

#define USART_LBLEN_10B CTL1_LBLEN(0)

10 bits break detection

Definition at line 321 of file gd32f3x0_usart.h.

#define USART_LBLEN_11B CTL1_LBLEN(1)

11 bits break detection

Definition at line 322 of file gd32f3x0_usart.h.

#define USART_MSBF_LSB CTL1_MSBF(0)

LSB first

Definition at line 348 of file gd32f3x0_usart.h.

#define USART_MSBF_MSB CTL1_MSBF(1)

MSB first

Definition at line 349 of file gd32f3x0_usart.h.

#define USART_OSB_1BIT CTL2_OSB(1)

1 sample bit

Definition at line 383 of file gd32f3x0_usart.h.

#define USART_OSB_3BIT CTL2_OSB(0)

3 sample bits

Definition at line 384 of file gd32f3x0_usart.h.

#define USART_OVSMOD_16 CTL0_OVSMOD(0)

oversampling by 16

Definition at line 312 of file gd32f3x0_usart.h.

#define USART_OVSMOD_8 CTL0_OVSMOD(1)

oversampling by 8

Definition at line 311 of file gd32f3x0_usart.h.

#define USART_PM_EVEN CTL0_PM(2)

even parity

Definition at line 296 of file gd32f3x0_usart.h.

#define USART_PM_NONE CTL0_PM(0)

no parity

Definition at line 295 of file gd32f3x0_usart.h.

#define USART_PM_ODD CTL0_PM(3)

odd parity

Definition at line 297 of file gd32f3x0_usart.h.

#define USART_RDATA ( usartx ) REG32((usartx) + 0x24U)

USART receive data register

Definition at line 31 of file gd32f3x0_usart.h.

#define USART_RDATA_RDATA BITS(0,8)

receive data value

Definition at line 157 of file gd32f3x0_usart.h.

#define USART_RECEIVE_DISABLE CTL0_REN(0)

disable receiver

Definition at line 286 of file gd32f3x0_usart.h.

#define USART_RECEIVE_ENABLE CTL0_REN(1)

enable receiver

Definition at line 285 of file gd32f3x0_usart.h.

#define USART_REG_VAL | ( | usartx,
 |  | offset
 | ) | (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))

Definition at line 175 of file gd32f3x0_usart.h.

#define USART_REG_VAL2 | ( | usartx,
 |  | offset
 | ) | (REG32((usartx) + ((uint32_t)(offset) >> 22)))

Definition at line 179 of file gd32f3x0_usart.h.

#define USART_REGIDX_BIT | ( | regidx,
 |  | bitpos
 | ) | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))

Definition at line 174 of file gd32f3x0_usart.h.

#define USART_REGIDX_BIT2 | ( | regidx,
 |  | bitpos,
 |  | regidx2,
 |  | bitpos2
 | ) |
Value:
(((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))

Definition at line 177 of file gd32f3x0_usart.h.

#define USART_RFCS ( usartx ) REG32((usartx) + 0xD0U)

USART receive FIFO control and status register

Definition at line 33 of file gd32f3x0_usart.h.

#define USART_RFCS_ELNACK BIT(0)

early NACK

Definition at line 163 of file gd32f3x0_usart.h.

#define USART_RFCS_REG_OFFSET 0xD0U

RFCS register offset

Definition at line 187 of file gd32f3x0_usart.h.

#define USART_RFCS_RFCNT BITS(12,14)

receive FIFO counter number

Definition at line 168 of file gd32f3x0_usart.h.

#define USART_RFCS_RFE BIT(10)

receive FIFO empty flag

Definition at line 166 of file gd32f3x0_usart.h.

#define USART_RFCS_RFEN BIT(8)

receive FIFO enable

Definition at line 164 of file gd32f3x0_usart.h.

#define USART_RFCS_RFF BIT(11)

receive FIFO full flag

Definition at line 167 of file gd32f3x0_usart.h.

#define USART_RFCS_RFFIE BIT(9)

receive FIFO full interrupt enable

Definition at line 165 of file gd32f3x0_usart.h.

#define USART_RFCS_RFFINT BIT(15)

receive FIFO full interrupt flag

Definition at line 169 of file gd32f3x0_usart.h.

#define USART_RT ( usartx ) REG32((usartx) + 0x14U)

USART receiver timeout register

Definition at line 27 of file gd32f3x0_usart.h.

#define USART_RT_BL BITS(24,31)

block length

Definition at line 109 of file gd32f3x0_usart.h.

#define USART_RT_RT BITS(0,23)

receiver timeout threshold

Definition at line 108 of file gd32f3x0_usart.h.

#define USART_RTS_DISABLE CTL2_RTSEN(0)

RTS hardware flow control disabled

Definition at line 374 of file gd32f3x0_usart.h.

#define USART_RTS_ENABLE CTL2_RTSEN(1)

RTS hardware flow control enabled

Definition at line 373 of file gd32f3x0_usart.h.

#define USART_STAT ( usartx ) REG32((usartx) + 0x1CU)

USART status register

Definition at line 29 of file gd32f3x0_usart.h.

#define USART_STAT_ABDE BIT(14)

auto baudrate detection error

Definition at line 132 of file gd32f3x0_usart.h.

#define USART_STAT_ABDF BIT(15)

auto baudrate detection flag

Definition at line 133 of file gd32f3x0_usart.h.

#define USART_STAT_AMF BIT(17)

address match flag

Definition at line 135 of file gd32f3x0_usart.h.

#define USART_STAT_BSY BIT(16)

busy flag

Definition at line 134 of file gd32f3x0_usart.h.

#define USART_STAT_CTS BIT(10)

CTS level

Definition at line 129 of file gd32f3x0_usart.h.

#define USART_STAT_CTSF BIT(9)

CTS change flag

Definition at line 128 of file gd32f3x0_usart.h.

#define USART_STAT_EBF BIT(12)

end of block flag

Definition at line 131 of file gd32f3x0_usart.h.

#define USART_STAT_FERR BIT(1)

frame error flag

Definition at line 120 of file gd32f3x0_usart.h.

#define USART_STAT_IDLEF BIT(4)

idle line detected flag

Definition at line 123 of file gd32f3x0_usart.h.

#define USART_STAT_LBDF BIT(8)

LIN break detected flag

Definition at line 127 of file gd32f3x0_usart.h.

#define USART_STAT_NERR BIT(2)

noise error flag

Definition at line 121 of file gd32f3x0_usart.h.

#define USART_STAT_ORERR BIT(3)

overrun error

Definition at line 122 of file gd32f3x0_usart.h.

#define USART_STAT_PERR BIT(0)

parity error flag

Definition at line 119 of file gd32f3x0_usart.h.

#define USART_STAT_RBNE BIT(5)

read data buffer not empty

Definition at line 124 of file gd32f3x0_usart.h.

#define USART_STAT_REA BIT(22)

receive enable acknowledge flag

Definition at line 140 of file gd32f3x0_usart.h.

#define USART_STAT_REG_OFFSET 0x1CU

STAT register offset

Definition at line 186 of file gd32f3x0_usart.h.

#define USART_STAT_RTF BIT(11)

receiver timeout flag

Definition at line 130 of file gd32f3x0_usart.h.

#define USART_STAT_RWU BIT(19)

receiver wakeup from mute mode

Definition at line 137 of file gd32f3x0_usart.h.

#define USART_STAT_SBF BIT(18)

send break flag

Definition at line 136 of file gd32f3x0_usart.h.

#define USART_STAT_TBE BIT(7)

transmit data register empty

Definition at line 126 of file gd32f3x0_usart.h.

#define USART_STAT_TC BIT(6)

transmission completed

Definition at line 125 of file gd32f3x0_usart.h.

#define USART_STAT_TEA BIT(21)

transmit enable acknowledge flag

Definition at line 139 of file gd32f3x0_usart.h.

#define USART_STAT_WUF BIT(20)

wakeup from deep-sleep mode flag

Definition at line 138 of file gd32f3x0_usart.h.

#define USART_STB_0_5BIT CTL1_STB(1)

0.5 bit

Definition at line 342 of file gd32f3x0_usart.h.

#define USART_STB_1_5BIT CTL1_STB(3)

1.5 bits

Definition at line 344 of file gd32f3x0_usart.h.

#define USART_STB_1BIT CTL1_STB(0)

1 bit

Definition at line 341 of file gd32f3x0_usart.h.

#define USART_STB_2BIT CTL1_STB(2)

2 bits

Definition at line 343 of file gd32f3x0_usart.h.

#define USART_TDATA ( usartx ) REG32((usartx) + 0x28U)

USART transmit data register

Definition at line 32 of file gd32f3x0_usart.h.

#define USART_TDATA_TDATA BITS(0,8)

transmit data value

Definition at line 160 of file gd32f3x0_usart.h.

#define USART_TRANSMIT_DISABLE CTL0_TEN(0)

disable transmitter

Definition at line 291 of file gd32f3x0_usart.h.

#define USART_TRANSMIT_ENABLE CTL0_TEN(1)

enable transmitter

Definition at line 290 of file gd32f3x0_usart.h.

#define USART_WL_8BIT CTL0_WL(0)

8 bits

Definition at line 306 of file gd32f3x0_usart.h.

#define USART_WL_9BIT CTL0_WL(1)

9 bits

Definition at line 307 of file gd32f3x0_usart.h.

#define USART_WM_ADDR CTL0_WM(1)

address match

Definition at line 302 of file gd32f3x0_usart.h.

#define USART_WM_IDLE CTL0_WM(0)

idle line

Definition at line 301 of file gd32f3x0_usart.h.

#define USART_WUM_ADDR CTL2_WUM(0)

WUF active on address match

Definition at line 393 of file gd32f3x0_usart.h.

#define USART_WUM_RBNE CTL2_WUM(3)

WUF active on RBNE

Definition at line 395 of file gd32f3x0_usart.h.

#define USART_WUM_STARTB CTL2_WUM(2)

WUF active on start bit

Definition at line 394 of file gd32f3x0_usart.h.

Enumeration Type Documentation

enum usart_flag_enum
Enumerator
USART_FLAG_REA | receive enable acknowledge flag
USART_FLAG_TEA | transmit enable acknowledge flag
USART_FLAG_WU | wakeup from Deep-sleep mode flag
USART_FLAG_RWU | receiver wakeup from mute mode
USART_FLAG_SB | send break flag
USART_FLAG_AM | ADDR match flag
USART_FLAG_BSY | busy flag
USART_FLAG_ABD | auto baudrate detection flag
USART_FLAG_ABDE | auto baudrate detection error
USART_FLAG_EB | end of block flag
USART_FLAG_RT | receiver timeout flag
USART_FLAG_CTS | CTS level
USART_FLAG_CTSF | CTS change flag
USART_FLAG_LBD | LIN break detected flag
USART_FLAG_TBE | transmit data buffer empty
USART_FLAG_TC | transmission complete
USART_FLAG_RBNE | read data buffer not empty
USART_FLAG_IDLE | IDLE line detected flag
USART_FLAG_ORERR | overrun error
USART_FLAG_NERR | noise error flag
USART_FLAG_FERR | frame error flag
USART_FLAG_PERR | parity error flag
USART_FLAG_RFFINT | receive FIFO full interrupt flag
USART_FLAG_RFF | receive FIFO full flag
USART_FLAG_RFE | receive FIFO empty flag

Definition at line 190 of file gd32f3x0_usart.h.

190 {
191 /* flags in STAT register */
192 USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U),
193 USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U),
194 USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U),
195 USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U),
196 USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U),
197 USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U),
198 USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U),
199 USART_FLAG_ABD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 15U),
200 USART_FLAG_ABDE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 14U),
201 USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U),
202 USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U),
203 USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U),
204 USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U),
205 USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U),
206 USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U),
207 USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U),
208 USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U),
209 USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U),
210 USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U),
211 USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U),
212 USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U),
213 USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U),
214 /* flags in RFCS register */
215 USART_FLAG_RFFINT = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 15U),
216 USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U),
217 USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U),
218 }usart_flag_enum;
USART_FLAG_ABDE
Definition: gd32f3x0_usart.h:200
USART_STAT_REG_OFFSET
#define USART_STAT_REG_OFFSET
Definition: gd32f3x0_usart.h:186
USART_FLAG_EB
Definition: gd32f3x0_usart.h:201
USART_FLAG_NERR
Definition: gd32f3x0_usart.h:211
USART_FLAG_BSY
Definition: gd32f3x0_usart.h:198
USART_FLAG_RFE
Definition: gd32f3x0_usart.h:217
USART_FLAG_CTS
Definition: gd32f3x0_usart.h:203
USART_FLAG_RFFINT
Definition: gd32f3x0_usart.h:215
USART_FLAG_TC
Definition: gd32f3x0_usart.h:207
USART_FLAG_REA
Definition: gd32f3x0_usart.h:192
USART_FLAG_PERR
Definition: gd32f3x0_usart.h:213
usart_flag_enum
usart_flag_enum
Definition: gd32f3x0_usart.h:190
USART_FLAG_CTSF
Definition: gd32f3x0_usart.h:204
USART_REGIDX_BIT
#define USART_REGIDX_BIT(regidx, bitpos)
Definition: gd32f3x0_usart.h:174
USART_FLAG_SB
Definition: gd32f3x0_usart.h:196
USART_RFCS_REG_OFFSET
#define USART_RFCS_REG_OFFSET
Definition: gd32f3x0_usart.h:187
USART_FLAG_ABD
Definition: gd32f3x0_usart.h:199
USART_FLAG_RFF
Definition: gd32f3x0_usart.h:216
USART_FLAG_ORERR
Definition: gd32f3x0_usart.h:210
USART_FLAG_TBE
Definition: gd32f3x0_usart.h:206
USART_FLAG_AM
Definition: gd32f3x0_usart.h:197
USART_FLAG_FERR
Definition: gd32f3x0_usart.h:212
USART_FLAG_RT
Definition: gd32f3x0_usart.h:202
USART_FLAG_WU
Definition: gd32f3x0_usart.h:194
USART_FLAG_TEA
Definition: gd32f3x0_usart.h:193
USART_FLAG_RBNE
Definition: gd32f3x0_usart.h:208
USART_FLAG_IDLE
Definition: gd32f3x0_usart.h:209
USART_FLAG_LBD
Definition: gd32f3x0_usart.h:205
USART_FLAG_RWU
Definition: gd32f3x0_usart.h:195
enum usart_interrupt_enum
Enumerator
USART_INT_EB | end of block interrupt
USART_INT_RT | receiver timeout interrupt
USART_INT_AM | address match interrupt
USART_INT_PERR | parity error interrupt
USART_INT_TBE | transmitter buffer empty interrupt
USART_INT_TC | transmission complete interrupt
USART_INT_RBNE | read data buffer not empty interrupt and overrun error interrupt
USART_INT_IDLE | IDLE line detected interrupt
USART_INT_LBD | LIN break detected interrupt
USART_INT_WU | wakeup from deep-sleep mode interrupt
USART_INT_CTS | CTS interrupt
USART_INT_ERR | error interrupt
USART_INT_RFF | receive FIFO full interrupt

Definition at line 246 of file gd32f3x0_usart.h.

247 {
248 /* interrupt in CTL0 register */
249 USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U),
250 USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U),
251 USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U),
252 USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U),
253 USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U),
254 USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U),
255 USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U),
256 USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U),
257 /* interrupt in CTL1 register */
258 USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U),
259 /* interrupt in CTL2 register */
260 USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U),
261 USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U),
262 USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U),
263 /* interrupt in RFCS register */
264 USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U),
265 }usart_interrupt_enum;
USART_INT_IDLE
Definition: gd32f3x0_usart.h:256
USART_CTL0_REG_OFFSET
#define USART_CTL0_REG_OFFSET
Definition: gd32f3x0_usart.h:183
USART_INT_LBD
Definition: gd32f3x0_usart.h:258
USART_INT_AM
Definition: gd32f3x0_usart.h:251
USART_INT_RFF
Definition: gd32f3x0_usart.h:264
USART_CTL2_REG_OFFSET
#define USART_CTL2_REG_OFFSET
Definition: gd32f3x0_usart.h:185
USART_REGIDX_BIT
#define USART_REGIDX_BIT(regidx, bitpos)
Definition: gd32f3x0_usart.h:174
USART_INT_WU
Definition: gd32f3x0_usart.h:260
USART_RFCS_REG_OFFSET
#define USART_RFCS_REG_OFFSET
Definition: gd32f3x0_usart.h:187
usart_interrupt_enum
usart_interrupt_enum
Definition: gd32f3x0_usart.h:246
USART_INT_EB
Definition: gd32f3x0_usart.h:249
USART_INT_PERR
Definition: gd32f3x0_usart.h:252
USART_INT_CTS
Definition: gd32f3x0_usart.h:261
USART_CTL1_REG_OFFSET
#define USART_CTL1_REG_OFFSET
Definition: gd32f3x0_usart.h:184
USART_INT_TBE
Definition: gd32f3x0_usart.h:253
USART_INT_RT
Definition: gd32f3x0_usart.h:250
USART_INT_ERR
Definition: gd32f3x0_usart.h:262
USART_INT_RBNE
Definition: gd32f3x0_usart.h:255
USART_INT_TC
Definition: gd32f3x0_usart.h:254
enum usart_interrupt_flag_enum
Enumerator
USART_INT_FLAG_EB | end of block interrupt and flag
USART_INT_FLAG_RT | receiver timeout interrupt and flag
USART_INT_FLAG_AM | address match interrupt and flag
USART_INT_FLAG_PERR | parity error interrupt and flag
USART_INT_FLAG_TBE | transmitter buffer empty interrupt and flag
USART_INT_FLAG_TC | transmission complete interrupt and flag
USART_INT_FLAG_RBNE | read data buffer not empty interrupt and flag
USART_INT_FLAG_RBNE_ORERR | read data buffer not empty interrupt and overrun error flag
USART_INT_FLAG_IDLE | IDLE line detected interrupt and flag
USART_INT_FLAG_LBD | LIN break detected interrupt and flag
USART_INT_FLAG_WU | wakeup from deep-sleep mode interrupt and flag
USART_INT_FLAG_CTS | CTS interrupt and flag
USART_INT_FLAG_ERR_NERR | error interrupt and noise error flag
USART_INT_FLAG_ERR_ORERR | error interrupt and overrun error
USART_INT_FLAG_ERR_FERR | error interrupt and frame error flag
USART_INT_FLAG_RFF | receive FIFO full interrupt and flag

Definition at line 221 of file gd32f3x0_usart.h.

222 {
223 /* interrupt flags in CTL0 register */
224 USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U),
225 USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U),
226 USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U),
227 USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U),
228 USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U),
229 USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U),
230 USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U),
231 USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U),
232 USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U),
233 /* interrupt flags in CTL1 register */
234 USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U),
235 /* interrupt flags in CTL2 register */
236 USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U),
237 USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U),
238 USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U),
239 USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U),
240 USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U),
241 /* interrupt flags in RFCS register */
242 USART_INT_FLAG_RFF = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U),
243 }usart_interrupt_flag_enum;
USART_STAT_REG_OFFSET
#define USART_STAT_REG_OFFSET
Definition: gd32f3x0_usart.h:186
USART_INT_FLAG_WU
Definition: gd32f3x0_usart.h:236
USART_INT_FLAG_ERR_FERR
Definition: gd32f3x0_usart.h:240
USART_INT_FLAG_PERR
Definition: gd32f3x0_usart.h:227
USART_INT_FLAG_ERR_NERR
Definition: gd32f3x0_usart.h:238
USART_INT_FLAG_CTS
Definition: gd32f3x0_usart.h:237
USART_CTL0_REG_OFFSET
#define USART_CTL0_REG_OFFSET
Definition: gd32f3x0_usart.h:183
USART_INT_FLAG_RFF
Definition: gd32f3x0_usart.h:242
USART_INT_FLAG_RBNE_ORERR
Definition: gd32f3x0_usart.h:231
USART_INT_FLAG_EB
Definition: gd32f3x0_usart.h:224
USART_REGIDX_BIT2
#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2)
Definition: gd32f3x0_usart.h:177
USART_INT_FLAG_LBD
Definition: gd32f3x0_usart.h:234
USART_CTL2_REG_OFFSET
#define USART_CTL2_REG_OFFSET
Definition: gd32f3x0_usart.h:185
USART_RFCS_REG_OFFSET
#define USART_RFCS_REG_OFFSET
Definition: gd32f3x0_usart.h:187
USART_INT_FLAG_TBE
Definition: gd32f3x0_usart.h:228
USART_INT_FLAG_RT
Definition: gd32f3x0_usart.h:225
USART_INT_FLAG_TC
Definition: gd32f3x0_usart.h:229
USART_INT_FLAG_AM
Definition: gd32f3x0_usart.h:226
USART_CTL1_REG_OFFSET
#define USART_CTL1_REG_OFFSET
Definition: gd32f3x0_usart.h:184
USART_INT_FLAG_IDLE
Definition: gd32f3x0_usart.h:232
USART_INT_FLAG_ERR_ORERR
Definition: gd32f3x0_usart.h:239
USART_INT_FLAG_RBNE
Definition: gd32f3x0_usart.h:230
usart_interrupt_flag_enum
usart_interrupt_flag_enum
Definition: gd32f3x0_usart.h:221
enum usart_invert_enum
Enumerator
USART_DINV_ENABLE | data bit level inversion
USART_DINV_DISABLE | data bit level not inversion
USART_TXPIN_ENABLE | TX pin level inversion
USART_TXPIN_DISABLE | TX pin level not inversion
USART_RXPIN_ENABLE | RX pin level inversion
USART_RXPIN_DISABLE | RX pin level not inversion
USART_SWAP_ENABLE | swap TX/RX pins
USART_SWAP_DISABLE | not swap TX/RX pins

Definition at line 268 of file gd32f3x0_usart.h.

268 {
269 /* data bit level inversion */
270 USART_DINV_ENABLE,
271 USART_DINV_DISABLE,
272 /* TX pin level inversion */
273 USART_TXPIN_ENABLE,
274 USART_TXPIN_DISABLE,
275 /* RX pin level inversion */
276 USART_RXPIN_ENABLE,
277 USART_RXPIN_DISABLE,
278 /* swap TX/RX pins */
279 USART_SWAP_ENABLE,
280 USART_SWAP_DISABLE,
281 }usart_invert_enum;
USART_DINV_DISABLE
Definition: gd32f3x0_usart.h:271
usart_invert_enum
usart_invert_enum
Definition: gd32f3x0_usart.h:268
USART_TXPIN_ENABLE
Definition: gd32f3x0_usart.h:273
USART_TXPIN_DISABLE
Definition: gd32f3x0_usart.h:274
USART_RXPIN_ENABLE
Definition: gd32f3x0_usart.h:276
USART_SWAP_DISABLE
Definition: gd32f3x0_usart.h:280
USART_DINV_ENABLE
Definition: gd32f3x0_usart.h:270
USART_SWAP_ENABLE
Definition: gd32f3x0_usart.h:279
USART_RXPIN_DISABLE
Definition: gd32f3x0_usart.h:277

Function Documentation

void usart_address_config | ( | uint32_t | usart_periph,
 |  | uint8_t | addr
 | ) |  |

address of the USART terminal

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] | addr | 0x00-0xFF, address of USART terminal
[out] | none
Return values
none

Definition at line 430 of file gd32f3x0_usart.c.

431 {
432 /* disable USART */
433 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
434
435 USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR);
436 USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (((uint32_t)addr) << 24));
437 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_ADDR
#define USART_CTL1_ADDR
Definition: gd32f3x0_usart.h:76
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_address_detection_mode_config | ( | uint32_t | usart_periph,
 |  | uint32_t | addmod
 | ) |  |

address detection mode configure

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] addmod address detection mode
  • USART_ADDM_4BIT: 4 bits
  • USART_ADDM_FULLBIT: full bits
[out] | none
Return values
none

Definition at line 414 of file gd32f3x0_usart.c.

415 {
416 /* disable USART */
417 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
418
419 USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDM);
420 USART_CTL1(usart_periph) |= USART_CTL1_ADDM & (addmod);
421 }
USART_CTL1_ADDM
#define USART_CTL1_ADDM
Definition: gd32f3x0_usart.h:59
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_autobaud_detection_disable ( uint32_t usart_periph )

auto baud rate detection disable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 344 of file gd32f3x0_usart.c.

345 {
346 USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDEN);
347 }
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_ABDEN
#define USART_CTL1_ABDEN
Definition: gd32f3x0_usart.h:73
void usart_autobaud_detection_enable ( uint32_t usart_periph )

auto baud rate detection enable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 333 of file gd32f3x0_usart.c.

334 {
335 USART_CTL1(usart_periph) |= USART_CTL1_ABDEN;
336 }
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_ABDEN
#define USART_CTL1_ABDEN
Definition: gd32f3x0_usart.h:73
void usart_autobaud_detection_mode_config | ( | uint32_t | usart_periph,
 |  | uint32_t | abdmod
 | ) |  |

auto baud rate detection mode configure

Parameters
[in] | usart_periph | USARTx(x=0)
[in] abdmod auto baud rate detection mode
  • USART_ABDM_FTOR: falling edge to rising edge measurement
  • USART_ABDM_FTOF: falling edge to falling edge measurement
[out] | none
Return values
none

Definition at line 358 of file gd32f3x0_usart.c.

359 {
360 /* reset ABDM bits */
361 USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDM);
362 USART_CTL1(usart_periph) |= abdmod;
363 }
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_ABDM
#define USART_CTL1_ABDM
Definition: gd32f3x0_usart.h:74
void usart_baudrate_set | ( | uint32_t | usart_periph,
 |  | uint32_t | baudval
 | ) |  |

configure USART baud rate value

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] | baudval | baud rate value
[out] | none
Return values
none

Definition at line 43 of file gd32f3x0_usart.c.

44 {
45 uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U;
46 switch(usart_periph){
47 case USART0:
48 uclk = rcu_clock_freq_get(CK_USART);
49 break;
50 case USART1:
51 uclk = rcu_clock_freq_get(CK_APB1);
52 break;
53 default:
54 break;
55 }
56 if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){
57 /* when oversampling by 8,configure the value of USART_BAUD */
58 udiv = ((2U*uclk)+baudval/2U)/baudval;
59 intdiv = udiv & 0xfff0U;
60 fradiv = udiv & 0x7U;
61 USART_BAUD(usart_periph) |= ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
62 }else{
63 /* when oversampling by 16,configure the value of USART_BAUD */
64 udiv = (uclk+baudval/2U)/baudval;
65 intdiv = udiv & 0xfff0U;
66 fradiv = udiv & 0xfU;
67 USART_BAUD(usart_periph) |= ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
68 }
69 }
CK_APB1
Definition: gd32f3x0_rcu.h:456
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
CK_USART
Definition: gd32f3x0_rcu.h:460
USART_CTL0_OVSMOD
#define USART_CTL0_OVSMOD
Definition: gd32f3x0_usart.h:52
USART1
#define USART1
Definition: gd32f3x0_usart.h:19
USART0
#define USART0
Definition: gd32f3x0_usart.h:18
USART_BAUD
#define USART_BAUD(usartx)
Definition: gd32f3x0_usart.h:25
USART_BAUD_INTDIV
#define USART_BAUD_INTDIV
Definition: gd32f3x0_usart.h:101
USART_BAUD_FRADIV
#define USART_BAUD_FRADIV
Definition: gd32f3x0_usart.h:100
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f3x0_rcu.c:964
void usart_block_length_config | ( | uint32_t | usart_periph,
 |  | uint32_t | bl
 | ) |  |

block length configure

Parameters
[in] | usart_periph | USARTx(x=0)
[in] | bl | 0x00-0xFF
[out] | none
Return values
none

Definition at line 681 of file gd32f3x0_usart.c.

682 {
683 USART_RT(usart_periph) &= ~(USART_RT_BL);
684 USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << 24));
685 }
USART_RT
#define USART_RT(usartx)
Definition: gd32f3x0_usart.h:27
USART_RT_BL
#define USART_RT_BL
Definition: gd32f3x0_usart.h:109
void usart_clock_disable ( uint32_t usart_periph )

clock disable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 567 of file gd32f3x0_usart.c.

568 {
569 /* disable USART */
570 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
571
572 USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN);
573 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_CKEN
#define USART_CTL1_CKEN
Definition: gd32f3x0_usart.h:65
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_clock_enable ( uint32_t usart_periph )

clock enable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 553 of file gd32f3x0_usart.c.

554 {
555 /* disable USART */
556 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
557
558 USART_CTL1(usart_periph) |= USART_CTL1_CKEN;
559 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_CKEN
#define USART_CTL1_CKEN
Definition: gd32f3x0_usart.h:65
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_command_enable | ( | uint32_t | usart_periph,
 |  | uint32_t | cmdtype
 | ) |  |

enable USART command

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] cmdtype command type
  • USART_CMD_ABDCMD: auto baudrate detection command
  • USART_CMD_SBKCMD: send break command
  • USART_CMD_MMCMD: mute mode command
  • USART_CMD_RXFCMD: receive data flush command
  • USART_CMD_TXFCMD: transmit data flush request
[out] | none
Return values
none

Definition at line 1161 of file gd32f3x0_usart.c.

1162 {
1163 USART_CMD(usart_periph) |= (cmdtype);
1164 }
USART_CMD
#define USART_CMD(usartx)
Definition: gd32f3x0_usart.h:28
void usart_data_first_config | ( | uint32_t | usart_periph,
 |  | uint32_t | msbf
 | ) |  |

data is transmitted/received with the LSB/MSB first

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] msbf LSB/MSB
  • USART_MSBF_LSB: LSB first
  • USART_MSBF_MSB: MSB first
[out] | none
Return values
none

Definition at line 216 of file gd32f3x0_usart.c.

217 {
218 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
219 /* configure LSB or MSB first */
220 USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF);
221 USART_CTL1(usart_periph) |= (USART_CTL1_MSBF & msbf);
222 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_MSBF
#define USART_CTL1_MSBF
Definition: gd32f3x0_usart.h:72
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
uint16_t usart_data_receive ( uint32_t usart_periph )

USART receive data function.

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
data of received

Definition at line 202 of file gd32f3x0_usart.c.

203 {
204 return (uint16_t)(GET_BITS(USART_RDATA(usart_periph), 0U, 8U));
205 }
USART_RDATA
#define USART_RDATA(usartx)
Definition: gd32f3x0_usart.h:31
void usart_data_transmit | ( | uint32_t | usart_periph,
 |  | uint32_t | data
 | ) |  |

USART transmit data function.

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] | data | data of transmission
[out] | none
Return values
none

Definition at line 191 of file gd32f3x0_usart.c.

192 {
193 USART_TDATA(usart_periph) = (USART_TDATA_TDATA & data);
194 }
USART_TDATA_TDATA
#define USART_TDATA_TDATA
Definition: gd32f3x0_usart.h:160
USART_TDATA
#define USART_TDATA(usartx)
Definition: gd32f3x0_usart.h:32
void usart_deinit ( uint32_t usart_periph )

reset USART

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_usart.c.

21 {
22 switch(usart_periph){
23 case USART0:
24 rcu_periph_reset_enable(RCU_USART0RST);
25 rcu_periph_reset_disable(RCU_USART0RST);
26 break;
27 case USART1:
28 rcu_periph_reset_enable(RCU_USART1RST);
29 rcu_periph_reset_disable(RCU_USART1RST);
30 break;
31 default:
32 break;
33 }
34 }
RCU_USART0RST
Definition: gd32f3x0_rcu.h:338
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
RCU_USART1RST
Definition: gd32f3x0_rcu.h:350
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
USART1
#define USART1
Definition: gd32f3x0_usart.h:19
USART0
#define USART0
Definition: gd32f3x0_usart.h:18
void usart_depolarity_config | ( | uint32_t | usart_periph,
 |  | uint32_t | dep
 | ) |  |

configure driver enable polarity mode

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] dep DE signal
  • USART_DEP_HIGH: DE signal is active high
  • USART_DEP_LOW: DE signal is active low
[out] | none
Return values
none

Definition at line 889 of file gd32f3x0_usart.c.

890 {
891 /* disable USART */
892 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
893 /* reset DEP bit */
894 USART_CTL2(usart_periph) &= ~(USART_CTL2_DEP);
895 USART_CTL2(usart_periph) |= (USART_CTL2_DEP & dep);
896 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_DEP
#define USART_CTL2_DEP
Definition: gd32f3x0_usart.h:94
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_disable ( uint32_t usart_periph )

disable USART

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 147 of file gd32f3x0_usart.c.

148 {
149 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
150 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_dma_receive_config | ( | uint32_t | usart_periph,
 |  | uint32_t | dmacmd
 | ) |  |

configure USART DMA reception

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] dmacmd enable or disable DMA for reception
  • USART_DENR_ENABLE: DMA enable for reception
  • USART_DENR_DISABLE: DMA disable for reception
[out] | none
Return values
none

Definition at line 907 of file gd32f3x0_usart.c.

908 {
909 USART_CTL2(usart_periph) &= ~USART_CTL2_DENR;
910 /* configure DMA reception */
911 USART_CTL2(usart_periph) |= dmacmd;
912 }
USART_CTL2_DENR
#define USART_CTL2_DENR
Definition: gd32f3x0_usart.h:85
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_dma_transmit_config | ( | uint32_t | usart_periph,
 |  | uint32_t | dmacmd
 | ) |  |

configure USART DMA transmission

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] dmacmd enable or disable DMA for transmission
  • USART_DENT_ENABLE: DMA enable for transmission
  • USART_DENT_DISABLE: DMA disable for transmission
[out] | none
Return values
none

Definition at line 923 of file gd32f3x0_usart.c.

924 {
925 USART_CTL2(usart_periph) &= ~USART_CTL2_DENT;
926 /* configure DMA transmission */
927 USART_CTL2(usart_periph) |= dmacmd;
928 }
USART_CTL2_DENT
#define USART_CTL2_DENT
Definition: gd32f3x0_usart.h:86
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_driver_assertime_config | ( | uint32_t | usart_periph,
 |  | uint32_t | deatime
 | ) |  |

driver enable assertion time configure

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] | deatime | 0x00-0x1F
[out] | none
Return values
none

Definition at line 855 of file gd32f3x0_usart.c.

856 {
857 /* disable USART */
858 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
859
860 USART_CTL0(usart_periph) &= ~(USART_CTL0_DEA);
861 USART_CTL0(usart_periph) |= (USART_CTL0_DEA & ((deatime) << 21));
862 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_DEA
#define USART_CTL0_DEA
Definition: gd32f3x0_usart.h:54
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_driver_deassertime_config | ( | uint32_t | usart_periph,
 |  | uint32_t | dedtime
 | ) |  |

driver enable de-assertion time configure

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] | dedtime | 0x00-0x1F
[out] | none
Return values
none

Definition at line 871 of file gd32f3x0_usart.c.

872 {
873 /* disable USART */
874 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
875
876 USART_CTL0(usart_periph) &= ~(USART_CTL0_DED);
877 USART_CTL0(usart_periph) |= (USART_CTL0_DED & ((dedtime) << 16));
878 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL0_DED
#define USART_CTL0_DED
Definition: gd32f3x0_usart.h:53
void usart_enable ( uint32_t usart_periph )

enable USART

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 136 of file gd32f3x0_usart.c.

137 {
138 USART_CTL0(usart_periph) |= USART_CTL0_UEN;
139 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_flag_clear | ( | uint32_t | usart_periph,
 |  | usart_flag_enum | flag
 | ) |  |

clear USART status

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] flag flag type
  • USART_FLAG_PERR: parity error flag
  • USART_FLAG_FERR: frame error flag
  • USART_FLAG_NERR: noise detected flag
  • USART_FLAG_ORERR:overrun error flag
  • USART_FLAG_IDLE: idle line detected flag
  • USART_FLAG_TC: transmission complete flag
  • USART_FLAG_LBD: LIN break detected flag
  • USART_FLAG_CTSF: CTS change flag
  • USART_FLAG_RT: receiver timeout flag
  • USART_FLAG_EB: end of block flag
  • USART_FLAG_AM: address match flag
  • USART_FLAG_WU: wakeup from deep-sleep mode flag
[out] | none
Return values
none

Definition at line 1092 of file gd32f3x0_usart.c.

1093 {
1094 USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag));
1095 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f3x0_usart.h:176
USART_INTC
#define USART_INTC(usartx)
Definition: gd32f3x0_usart.h:30
FlagStatus usart_flag_get | ( | uint32_t | usart_periph,
 |  | usart_flag_enum | flag
 | ) |  |

get flag in STAT/RFCS register

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] flag flag type
  • USART_FLAG_PERR: parity error flag
  • USART_FLAG_FERR: frame error flag
  • USART_FLAG_NERR: noise error flag
  • USART_FLAG_ORERR: overrun error
  • USART_FLAG_IDLE: idle line detected flag
  • USART_FLAG_RBNE: read data buffer not empty
  • USART_FLAG_TC: transmission completed
  • USART_FLAG_TBE: transmit data register empty
  • USART_FLAG_LBD: LIN break detected flag
  • USART_FLAG_CTSF: CTS change flag
  • USART_FLAG_CTS: CTS level
  • USART_FLAG_RT: receiver timeout flag
  • USART_FLAG_EB: end of block flag
  • USART_FLAG_ABDE: auto baudrate detection error
  • USART_FLAG_ABD: auto baudrate detection flag
  • USART_FLAG_BSY: busy flag
  • USART_FLAG_AM: address match flag
  • USART_FLAG_SB: send break flag
  • USART_FLAG_RWU: receiver wakeup from mute mode.
  • USART_FLAG_WU: wakeup from deep-sleep mode flag
  • USART_FLAG_TEA: transmit enable acknowledge flag
  • USART_FLAG_REA: receive enable acknowledge flag
  • USART_FLAG_RFFINT:receive FIFO full interrupt flag
  • USART_FLAG_RFE: receive FIFO empty flag
  • USART_FLAG_RFF: receive FIFO full flag
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 1064 of file gd32f3x0_usart.c.

1065 {
1066 if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){
1067 return SET;
1068 }else{
1069 return RESET;
1070 }
1071 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f3x0_usart.h:176
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f3x0_usart.h:175
void usart_guard_time_config | ( | uint32_t | usart_periph,
 |  | uint32_t | guat
 | ) |  |

guard time value configure in smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0)
[in] | guat | 0x00-0xFF
[out] | none
Return values
none

Definition at line 665 of file gd32f3x0_usart.c.

666 {
667 /* disable USART */
668 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
669
670 USART_GP(usart_periph) &= ~(USART_GP_GUAT);
671 USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << 8));
672 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_GP
#define USART_GP(usartx)
Definition: gd32f3x0_usart.h:26
USART_GP_GUAT
#define USART_GP_GUAT
Definition: gd32f3x0_usart.h:105
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_halfduplex_disable ( uint32_t usart_periph )

half-duplex disable

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 539 of file gd32f3x0_usart.c.

540 {
541 /* disable USART */
542 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
543
544 USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN);
545 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2_HDEN
#define USART_CTL2_HDEN
Definition: gd32f3x0_usart.h:82
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_halfduplex_enable ( uint32_t usart_periph )

half-duplex enable

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 525 of file gd32f3x0_usart.c.

526 {
527 /* disable USART */
528 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
529
530 USART_CTL2(usart_periph) |= USART_CTL2_HDEN;
531 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2_HDEN
#define USART_CTL2_HDEN
Definition: gd32f3x0_usart.h:82
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_hardware_flow_cts_config | ( | uint32_t | usart_periph,
 |  | uint32_t | ctsconfig
 | ) |  |

configure hardware flow control CTS

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] ctsconfig enable or disable CTS
  • USART_CTS_ENABLE: enable CTS
  • USART_CTS_DISABLE: disable CTS
[out] | none
Return values
none

Definition at line 811 of file gd32f3x0_usart.c.

812 {
813 /* disable USART */
814 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
815
816 USART_CTL2(usart_periph) &= ~USART_CTL2_CTSEN;
817 USART_CTL2(usart_periph) |= ctsconfig;
818 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_CTSEN
#define USART_CTL2_CTSEN
Definition: gd32f3x0_usart.h:88
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_hardware_flow_rts_config | ( | uint32_t | usart_periph,
 |  | uint32_t | rtsconfig
 | ) |  |

configure hardware flow control RTS

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] rtsconfig enable or disable RTS
  • USART_RTS_ENABLE: enable RTS
  • USART_RTS_DISABLE: disable RTS
[out] | none
Return values
none

Definition at line 793 of file gd32f3x0_usart.c.

794 {
795 /* disable USART */
796 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
797
798 USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN);
799 USART_CTL2(usart_periph) |= rtsconfig;
800 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_RTSEN
#define USART_CTL2_RTSEN
Definition: gd32f3x0_usart.h:87
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_interrupt_disable | ( | uint32_t | usart_periph,
 |  | uint32_t | inttype
 | ) |  |

disable USART interrupt

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] inttype interrupt type
  • USART_INT_IDLE: idle interrupt
  • USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt
  • USART_INT_TC: transmission complete interrupt
  • USART_INT_TBE: transmit data register empty interrupt
  • USART_INT_PERR: parity error interrupt
  • USART_INT_AM: address match interrupt
  • USART_INT_RT: receiver timeout interrupt
  • USART_INT_EB: end of block interrupt
  • USART_INT_LBD: LIN break detection interrupt
  • USART_INT_ERR: error interrupt enable in multibuffer communication
  • USART_INT_CTS: CTS interrupt
  • USART_INT_WU: wakeup from deep-sleep mode interrupt
  • USART_INT_RFF: receive FIFO full interrupt enable
[out] | none
Return values
none

Definition at line 1144 of file gd32f3x0_usart.c.

1145 {
1146 USART_REG_VAL(usart_periph, inttype) &= ~BIT(USART_BIT_POS(inttype));
1147 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f3x0_usart.h:176
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f3x0_usart.h:175
void usart_interrupt_enable | ( | uint32_t | usart_periph,
 |  | uint32_t | inttype
 | ) |  |

enable USART interrupt

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] inttype interrupt type
  • USART_INT_IDLE: idle interrupt
  • USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt enable interrupt
  • USART_INT_TC: transmission complete interrupt
  • USART_INT_TBE: transmit data register empty interrupt
  • USART_INT_PERR: parity error interrupt
  • USART_INT_AM: address match interrupt
  • USART_INT_RT: receiver timeout interrupt
  • USART_INT_EB: end of block interrupt
  • USART_INT_LBD: LIN break detection interrupt
  • USART_INT_ERR: error interrupt enable in multibuffer communication
  • USART_INT_CTS: CTS interrupt
  • USART_INT_WU: wakeup from deep-sleep mode interrupt
  • USART_INT_RFF: receive FIFO full interrupt enable
[out] | none
Return values
none

Definition at line 1118 of file gd32f3x0_usart.c.

1119 {
1120 USART_REG_VAL(usart_periph, inttype) |= BIT(USART_BIT_POS(inttype));
1121 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f3x0_usart.h:176
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f3x0_usart.h:175
void usart_interrupt_flag_clear | ( | uint32_t | usart_periph,
 |  | uint32_t | flag
 | ) |  |

clear USART interrupt flag

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] flag USART interrupt flag
  • USART_INT_FLAG_PERR: parity error flag
  • USART_INT_FLAG_FERR: frame error flag
  • USART_INT_FLAG_NERR: noise detected flag
  • USART_INT_FLAG_ORERR:overrun error flag
  • USART_INT_FLAG_IDLE: idle line detected flag
  • USART_INT_FLAG_TC: transmission complete flag
  • USART_INT_FLAG_LBD: LIN break detected flag
  • USART_INT_FLAG_CTS: CTS change flag
  • USART_INT_FLAG_RT: receiver timeout flag
  • USART_INT_FLAG_EB: end of block flag
  • USART_INT_FLAG_AM: address match flag
  • USART_INT_FLAG_WU: wakeup from deep-sleep mode flag
[out] | none
Return values
none

Definition at line 1223 of file gd32f3x0_usart.c.

1224 {
1225 USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(flag));
1226 }
USART_BIT_POS2
#define USART_BIT_POS2(val)
Definition: gd32f3x0_usart.h:180
USART_INTC
#define USART_INTC(usartx)
Definition: gd32f3x0_usart.h:30
FlagStatus usart_interrupt_flag_get | ( | uint32_t | usart_periph,
 |  | uint32_t | int_flag
 | ) |  |

get USART interrupt and flag status

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] int_flag interrupt and flag type, refer to usart_interrupt_flag_enum
  • USART_INT_FLAG_EB: end of block interrupt and flag
  • USART_INT_FLAG_RT: receiver timeout interrupt and flag
  • USART_INT_FLAG_AM: address match interrupt and flag
  • USART_INT_FLAG_PERR: parity error interrupt and flag
  • USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag
  • USART_INT_FLAG_TC: transmission complete interrupt and flag
  • USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag
  • USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag
  • USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag
  • USART_INT_FLAG_LBD: LIN break detected interrupt and flag
  • USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt and flag
  • USART_INT_FLAG_CTS: CTS interrupt and flag
  • USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag
  • USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error
  • USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag
  • USART_INT_FLAG_RFF: receive FIFO full interrupt and flag
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 1189 of file gd32f3x0_usart.c.

1190 {
1191 uint32_t intenable = 0U, flagstatus = 0U;
1192 /* get the interrupt enable bit status */
1193 intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)));
1194 /* get the corresponding flag bit status */
1195 flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
1196
1197 if(flagstatus && intenable){
1198 return SET;
1199 }else{
1200 return RESET;
1201 }
1202 }
USART_BIT_POS2
#define USART_BIT_POS2(val)
Definition: gd32f3x0_usart.h:180
USART_REG_VAL2
#define USART_REG_VAL2(usartx, offset)
Definition: gd32f3x0_usart.h:179
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f3x0_usart.h:176
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f3x0_usart.h:175
void usart_invert_config | ( | uint32_t | usart_periph,
 |  | usart_invert_enum | invertpara
 | ) |  |

USART inverted configure.

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] | invertpara | refer to usart_invert_enum
[out] | none
Return values
none

Definition at line 231 of file gd32f3x0_usart.c.

232 {
233 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
234 /* inverted or not the specified signal */
235 switch(invertpara){
236 case USART_DINV_ENABLE:
237 USART_CTL1(usart_periph) |= USART_CTL1_DINV;
238 break;
239 case USART_DINV_DISABLE:
240 USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV);
241 break;
242 case USART_TXPIN_DISABLE:
243 USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV);
244 break;
245 case USART_RXPIN_DISABLE:
246 USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV);
247 break;
248 case USART_SWAP_DISABLE:
249 USART_CTL1(usart_periph) &= ~(USART_CTL1_STRP);
250 break;
251 case USART_TXPIN_ENABLE:
252 USART_CTL1(usart_periph) |= USART_CTL1_TINV;
253 break;
254 case USART_RXPIN_ENABLE:
255 USART_CTL1(usart_periph) |= USART_CTL1_RINV;
256 break;
257 case USART_SWAP_ENABLE:
258 USART_CTL1(usart_periph) |= USART_CTL1_STRP;
259 break;
260 default:
261 break;
262 }
263 }
USART_DINV_DISABLE
Definition: gd32f3x0_usart.h:271
USART_CTL1_TINV
#define USART_CTL1_TINV
Definition: gd32f3x0_usart.h:70
USART_CTL1_RINV
#define USART_CTL1_RINV
Definition: gd32f3x0_usart.h:69
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_TXPIN_ENABLE
Definition: gd32f3x0_usart.h:273
USART_CTL1_STRP
#define USART_CTL1_STRP
Definition: gd32f3x0_usart.h:68
USART_CTL1_DINV
#define USART_CTL1_DINV
Definition: gd32f3x0_usart.h:71
USART_TXPIN_DISABLE
Definition: gd32f3x0_usart.h:274
USART_RXPIN_ENABLE
Definition: gd32f3x0_usart.h:276
USART_SWAP_DISABLE
Definition: gd32f3x0_usart.h:280
USART_DINV_ENABLE
Definition: gd32f3x0_usart.h:270
USART_SWAP_ENABLE
Definition: gd32f3x0_usart.h:279
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_RXPIN_DISABLE
Definition: gd32f3x0_usart.h:277
void usart_irda_lowpower_config | ( | uint32_t | usart_periph,
 |  | uint32_t | irlp
 | ) |  |

IrDA low-power configure.

Parameters
[in] | usart_periph | USARTx(x=0)
[in] irlp IrDA low-power or normal
  • USART_IRLP_LOW: low-power
  • USART_IRLP_NORMAL: normal
[out] | none
Return values
none

Definition at line 761 of file gd32f3x0_usart.c.

762 {
763 /* disable USART */
764 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
765
766 USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp);
767 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_IRLP
#define USART_CTL2_IRLP
Definition: gd32f3x0_usart.h:81
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_irda_mode_disable ( uint32_t usart_periph )

IrDA mode disable.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 744 of file gd32f3x0_usart.c.

745 {
746 /* disable USART */
747 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
748
749 USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN);
750 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_IREN
#define USART_CTL2_IREN
Definition: gd32f3x0_usart.h:80
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_irda_mode_enable ( uint32_t usart_periph )

IrDA mode enable.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 730 of file gd32f3x0_usart.c.

731 {
732 /* disable USART */
733 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
734
735 USART_CTL2(usart_periph) |= USART_CTL2_IREN;
736 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_IREN
#define USART_CTL2_IREN
Definition: gd32f3x0_usart.h:80
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_lin_break_dection_length_config | ( | uint32_t | usart_periph,
 |  | uint32_t | lblen
 | ) |  |

LIN break detection length.

Parameters
[in] | usart_periph | USARTx(x=0)
[in] lblen LIN break detection length
  • USART_LBLEN_10B: 10 bits break detection
  • USART_LBLEN_11B: 11 bits break detection
[out] | none
Return values
none

Definition at line 511 of file gd32f3x0_usart.c.

512 {
513 /* disable USART */
514 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
515
516 USART_CTL1(usart_periph) |= USART_CTL1_LBLEN & (lblen);
517 }
USART_CTL1_LBLEN
#define USART_CTL1_LBLEN
Definition: gd32f3x0_usart.h:60
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_lin_mode_disable ( uint32_t usart_periph )

LIN mode disable.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 494 of file gd32f3x0_usart.c.

495 {
496 /* disable USART */
497 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
498
499 USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN);
500 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_LMEN
#define USART_CTL1_LMEN
Definition: gd32f3x0_usart.h:67
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_lin_mode_enable ( uint32_t usart_periph )

LIN mode enable.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 480 of file gd32f3x0_usart.c.

481 {
482 /* disable USART */
483 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
484
485 USART_CTL1(usart_periph) |= USART_CTL1_LMEN;
486 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_LMEN
#define USART_CTL1_LMEN
Definition: gd32f3x0_usart.h:67
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_mute_mode_disable ( uint32_t usart_periph )

mute mode disable

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 382 of file gd32f3x0_usart.c.

383 {
384 USART_CTL0(usart_periph) &= ~(USART_CTL0_MEN);
385 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_MEN
#define USART_CTL0_MEN
Definition: gd32f3x0_usart.h:50
void usart_mute_mode_enable ( uint32_t usart_periph )

mute mode enable

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 371 of file gd32f3x0_usart.c.

372 {
373 USART_CTL0(usart_periph) |= USART_CTL0_MEN;
374 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_MEN
#define USART_CTL0_MEN
Definition: gd32f3x0_usart.h:50
void usart_mute_mode_wakeup_config | ( | uint32_t | usart_periph,
 |  | uint32_t | wmethod
 | ) |  |

wakeup method in mute mode configure

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] wmethod two methods be used to enter or exit the mute mode
  • USART_WM_IDLE: idle line
  • USART_WM_ADDR: address mark
[out] | none
Return values
none

Definition at line 396 of file gd32f3x0_usart.c.

397 {
398 /* disable USART */
399 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
400
401 USART_CTL0(usart_periph) &= ~(USART_CTL0_WM);
402 USART_CTL0(usart_periph) |= wmethod;
403 }
USART_CTL0_WM
#define USART_CTL0_WM
Definition: gd32f3x0_usart.h:48
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_overrun_disable ( uint32_t usart_periph )

overrun function is disabled

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 284 of file gd32f3x0_usart.c.

285 {
286 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
287 /* disable overrun function */
288 USART_CTL2(usart_periph) |= USART_CTL2_OVRD;
289 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_OVRD
#define USART_CTL2_OVRD
Definition: gd32f3x0_usart.h:91
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_overrun_enable ( uint32_t usart_periph )

overrun function is enabled

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 271 of file gd32f3x0_usart.c.

272 {
273 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
274 /* enable overrun function */
275 USART_CTL2(usart_periph) &= ~(USART_CTL2_OVRD);
276 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_OVRD
#define USART_CTL2_OVRD
Definition: gd32f3x0_usart.h:91
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_oversample_config | ( | uint32_t | usart_periph,
 |  | uint32_t | oversamp
 | ) |  |

configure the USART oversample mode

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] oversamp oversample value
  • USART_OVSMOD_8: oversampling by 8
  • USART_OVSMOD_16: oversampling by 16
[out] | none
Return values
none

Definition at line 300 of file gd32f3x0_usart.c.

301 {
302 /* disable USART */
303 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
304 /* clear OVSMOD bit */
305 USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD);
306 USART_CTL0(usart_periph) |= oversamp;
307 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_OVSMOD
#define USART_CTL0_OVSMOD
Definition: gd32f3x0_usart.h:52
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_parity_config | ( | uint32_t | usart_periph,
 |  | uint32_t | paritycfg
 | ) |  |

configure USART parity

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] paritycfg USART parity configure
  • USART_PM_NONE: no parity
  • USART_PM_ODD: odd parity
  • USART_PM_EVEN: even parity
[out] | none
Return values
none

Definition at line 81 of file gd32f3x0_usart.c.

82 {
83 /* disable USART */
84 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
85 /* clear USART_CTL0 PM,PCEN bits */
86 USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN);
87 /* configure USART parity mode */
88 USART_CTL0(usart_periph) |= paritycfg;
89 }
USART_CTL0_PM
#define USART_CTL0_PM
Definition: gd32f3x0_usart.h:46
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_PCEN
#define USART_CTL0_PCEN
Definition: gd32f3x0_usart.h:47
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_prescaler_config | ( | uint32_t | usart_periph,
 |  | uint32_t | psc
 | ) |  |

configure the peripheral clock prescaler in USART IrDA low-power mode

Parameters
[in] | usart_periph | USARTx(x=0)
[in] | psc | 0x00-0xFF
[out] | none
Return values
none

Definition at line 776 of file gd32f3x0_usart.c.

777 {
778 /* disable USART */
779 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
780 USART_GP(usart_periph) &= ~(USART_GP_PSC);
781 USART_GP(usart_periph) |= psc;
782 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_GP
#define USART_GP(usartx)
Definition: gd32f3x0_usart.h:26
USART_GP_PSC
#define USART_GP_PSC
Definition: gd32f3x0_usart.h:104
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_receive_config | ( | uint32_t | usart_periph,
 |  | uint32_t | rxconfig
 | ) |  |

configure USART receiver

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] rxconfig enable or disable USART receiver
  • USART_RECEIVE_ENABLE: enable USART reception
  • USART_RECEIVE_DISABLE: disable USART reception
[out] | none
Return values
none

Definition at line 177 of file gd32f3x0_usart.c.

178 {
179 USART_CTL0(usart_periph) &= ~USART_CTL0_REN;
180 /* configure receiver mode */
181 USART_CTL0(usart_periph) |= rxconfig;
182 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_REN
#define USART_CTL0_REN
Definition: gd32f3x0_usart.h:39
uint8_t usart_receive_fifo_counter_number ( uint32_t usart_periph )

read receive FIFO counter number

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
receive FIFO counter number

Definition at line 1027 of file gd32f3x0_usart.c.

1028 {
1029 return (uint8_t)(GET_BITS(USART_RFCS(usart_periph), 12U, 14U));
1030 }
USART_RFCS
#define USART_RFCS(usartx)
Definition: gd32f3x0_usart.h:33
void usart_receive_fifo_disable ( uint32_t usart_periph )

receive FIFO disable

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 1016 of file gd32f3x0_usart.c.

1017 {
1018 USART_RFCS(usart_periph) &= ~(USART_RFCS_RFEN);
1019 }
USART_RFCS
#define USART_RFCS(usartx)
Definition: gd32f3x0_usart.h:33
USART_RFCS_RFEN
#define USART_RFCS_RFEN
Definition: gd32f3x0_usart.h:164
void usart_receive_fifo_enable ( uint32_t usart_periph )

receive FIFO enable

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 1005 of file gd32f3x0_usart.c.

1006 {
1007 USART_RFCS(usart_periph) |= USART_RFCS_RFEN;
1008 }
USART_RFCS
#define USART_RFCS(usartx)
Definition: gd32f3x0_usart.h:33
USART_RFCS_RFEN
#define USART_RFCS_RFEN
Definition: gd32f3x0_usart.h:164
void usart_receiver_timeout_config | ( | uint32_t | usart_periph,
 |  | uint32_t | rtimeout
 | ) |  |

receiver timeout threshold configure

Parameters
[in] | usart_periph | USARTx(x=0)
[in] | rtimeout | 0x000000-0xFFFFFF, receiver timeout value in terms of number of baud clocks
[out] | none
Return values
none

Definition at line 468 of file gd32f3x0_usart.c.

469 {
470 USART_RT(usart_periph) &= ~(USART_RT_RT);
471 USART_RT(usart_periph) |= rtimeout;
472 }
USART_RT_RT
#define USART_RT_RT
Definition: gd32f3x0_usart.h:108
USART_RT
#define USART_RT(usartx)
Definition: gd32f3x0_usart.h:27
void usart_receiver_timeout_disable ( uint32_t usart_periph )

receiver timeout disable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 456 of file gd32f3x0_usart.c.

457 {
458 USART_CTL1(usart_periph) &= ~(USART_CTL1_RTEN);
459 }
USART_CTL1_RTEN
#define USART_CTL1_RTEN
Definition: gd32f3x0_usart.h:75
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
void usart_receiver_timeout_enable ( uint32_t usart_periph )

receiver timeout enable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 445 of file gd32f3x0_usart.c.

446 {
447 USART_CTL1(usart_periph) |= USART_CTL1_RTEN;
448 }
USART_CTL1_RTEN
#define USART_CTL1_RTEN
Definition: gd32f3x0_usart.h:75
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
void usart_reception_error_dma_disable ( uint32_t usart_periph )

disable DMA on reception error

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 936 of file gd32f3x0_usart.c.

937 {
938 /* disable USART */
939 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
940
941 USART_CTL2(usart_periph) |= USART_CTL2_DDRE;
942 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2_DDRE
#define USART_CTL2_DDRE
Definition: gd32f3x0_usart.h:92
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_reception_error_dma_enable ( uint32_t usart_periph )

enable DMA on reception error

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 950 of file gd32f3x0_usart.c.

951 {
952 /* disable USART */
953 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
954
955 USART_CTL2(usart_periph) &= ~(USART_CTL2_DDRE);
956 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2_DDRE
#define USART_CTL2_DDRE
Definition: gd32f3x0_usart.h:92
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_rs485_driver_disable ( uint32_t usart_periph )

RS485 driver disable.

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 840 of file gd32f3x0_usart.c.

841 {
842 /* disable USART */
843 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
844
845 USART_CTL2(usart_periph) &= ~(USART_CTL2_DEM);
846 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_DEM
#define USART_CTL2_DEM
Definition: gd32f3x0_usart.h:93
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_rs485_driver_enable ( uint32_t usart_periph )

RS485 driver enable.

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 826 of file gd32f3x0_usart.c.

827 {
828 /* disable USART */
829 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
830
831 USART_CTL2(usart_periph) |= USART_CTL2_DEM;
832 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_DEM
#define USART_CTL2_DEM
Definition: gd32f3x0_usart.h:93
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_sample_bit_config | ( | uint32_t | usart_periph,
 |  | uint32_t | osb
 | ) |  |

sample bit method configure

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] osb sample bit
  • USART_OSB_1BIT: 1 bit
  • USART_OSB_3BIT: 3 bits
[out] | none
Return values
none

Definition at line 318 of file gd32f3x0_usart.c.

319 {
320 /* disable USART */
321 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
322
323 USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB);
324 USART_CTL2(usart_periph) |= osb;
325 }
USART_CTL2_OSB
#define USART_CTL2_OSB
Definition: gd32f3x0_usart.h:90
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_smartcard_autoretry_config | ( | uint32_t | usart_periph,
 |  | uint32_t | scrtnum
 | ) |  |

smartcard auto-retry number configure

Parameters
[in] | usart_periph | USARTx(x=0)
[in] | scrtnum | 0x0-0x7, smartcard auto-retry number
[out] | none
Return values
none

Definition at line 694 of file gd32f3x0_usart.c.

695 {
696 /* disable USART */
697 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
698 USART_CTL2(usart_periph) &= ~(USART_CTL2_SCRTNUM);
699 USART_CTL2(usart_periph) |= (USART_CTL2_SCRTNUM & (scrtnum << 17));
700 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_SCRTNUM
#define USART_CTL2_SCRTNUM
Definition: gd32f3x0_usart.h:95
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_smartcard_mode_disable ( uint32_t usart_periph )

smartcard mode disable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 622 of file gd32f3x0_usart.c.

623 {
624 /* disable USART */
625 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
626
627 USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN);
628 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_SCEN
#define USART_CTL2_SCEN
Definition: gd32f3x0_usart.h:84
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_smartcard_mode_early_nack_disable ( uint32_t usart_periph )

early NACK disable in smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 719 of file gd32f3x0_usart.c.

720 {
721 USART_RFCS(usart_periph) &= ~USART_RFCS_ELNACK;
722 }
USART_RFCS
#define USART_RFCS(usartx)
Definition: gd32f3x0_usart.h:33
USART_RFCS_ELNACK
#define USART_RFCS_ELNACK
Definition: gd32f3x0_usart.h:163
void usart_smartcard_mode_early_nack_enable ( uint32_t usart_periph )

early NACK enable in smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 708 of file gd32f3x0_usart.c.

709 {
710 USART_RFCS(usart_periph) |= USART_RFCS_ELNACK;
711 }
USART_RFCS
#define USART_RFCS(usartx)
Definition: gd32f3x0_usart.h:33
USART_RFCS_ELNACK
#define USART_RFCS_ELNACK
Definition: gd32f3x0_usart.h:163
void usart_smartcard_mode_enable ( uint32_t usart_periph )

smartcard mode enable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 608 of file gd32f3x0_usart.c.

609 {
610 /* disable USART */
611 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
612
613 USART_CTL2(usart_periph) |= USART_CTL2_SCEN;
614 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_SCEN
#define USART_CTL2_SCEN
Definition: gd32f3x0_usart.h:84
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_smartcard_mode_nack_disable ( uint32_t usart_periph )

NACK disable in smartcard mode.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 650 of file gd32f3x0_usart.c.

651 {
652 /* disable USART */
653 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
654
655 USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN);
656 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_NKEN
#define USART_CTL2_NKEN
Definition: gd32f3x0_usart.h:83
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_smartcard_mode_nack_enable ( uint32_t usart_periph )

NACK enable in smartcard mode.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 636 of file gd32f3x0_usart.c.

637 {
638 /* disable USART */
639 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
640
641 USART_CTL2(usart_periph) |= USART_CTL2_NKEN;
642 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_NKEN
#define USART_CTL2_NKEN
Definition: gd32f3x0_usart.h:83
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_stop_bit_set | ( | uint32_t | usart_periph,
 |  | uint32_t | stblen
 | ) |  |

configure USART stop bit length

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] stblen USART stop bit configure
  • USART_STB_1BIT: 1 bit
  • USART_STB_0_5BIT: 0.5bit
  • USART_STB_2BIT: 2 bits
  • USART_STB_1_5BIT: 1.5bit
[out] | none
Return values
none

Definition at line 121 of file gd32f3x0_usart.c.

122 {
123 /* disable USART */
124 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
125 /* clear USART_CTL1 STB bits */
126 USART_CTL1(usart_periph) &= ~USART_CTL1_STB;
127 USART_CTL1(usart_periph) |= stblen;
128 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_STB
#define USART_CTL1_STB
Definition: gd32f3x0_usart.h:66
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_synchronous_clock_config | ( | uint32_t | usart_periph,
 |  | uint32_t | clen,
 |  | uint32_t | cph,
 |  | uint32_t | cpl
 | ) |  |

configure USART synchronous mode parameters

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] clen last bit clock pulse
  • USART_CLEN_NONE: clock pulse of the last data bit (MSB) is not output to the CK pin
  • USART_CLEN_EN: clock pulse of the last data bit (MSB) is output to the CK pin
[in] cph clock phase
  • USART_CPH_1CK: first clock transition is the first data capture edge
  • USART_CPH_2CK: second clock transition is the first data capture edge
[in] cpl clock polarity
  • USART_CPL_LOW: steady low value on CK pin
  • USART_CPL_HIGH: steady high value on CK pin
[out] | none
Return values
none

Definition at line 590 of file gd32f3x0_usart.c.

591 {
592 /* disable USART */
593 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
594 /* reset USART_CTL1 CLEN,CPH,CPL bits */
595 USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL);
596
597 USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen);
598 USART_CTL1(usart_periph) |= (USART_CTL1_CPH & cph);
599 USART_CTL1(usart_periph) |= (USART_CTL1_CPL & cpl);
600 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_CLEN
#define USART_CTL1_CLEN
Definition: gd32f3x0_usart.h:62
USART_CTL1_CPH
#define USART_CTL1_CPH
Definition: gd32f3x0_usart.h:63
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL1_CPL
#define USART_CTL1_CPL
Definition: gd32f3x0_usart.h:64
void usart_transmit_config | ( | uint32_t | usart_periph,
 |  | uint32_t | txconfig
 | ) |  |

configure USART transmitter

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] txconfig enable or disable USART transmitter
  • USART_TRANSMIT_ENABLE: enable USART transmission
  • USART_TRANSMIT_DISABLE: enable USART transmission
[out] | none
Return values
none

Definition at line 161 of file gd32f3x0_usart.c.

162 {
163 USART_CTL0(usart_periph) &= ~USART_CTL0_TEN;
164 /* configure transfer mode */
165 USART_CTL0(usart_periph) |= txconfig;
166 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_TEN
#define USART_CTL0_TEN
Definition: gd32f3x0_usart.h:40
void usart_wakeup_disable ( uint32_t usart_periph )

USART be not able to wake up the MCU from deep-sleep mode.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 975 of file gd32f3x0_usart.c.

976 {
977 USART_CTL0(usart_periph) &= ~(USART_CTL0_UESM);
978 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UESM
#define USART_CTL0_UESM
Definition: gd32f3x0_usart.h:38
void usart_wakeup_enable ( uint32_t usart_periph )

USART be able to wake up the MCU from deep-sleep mode.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 964 of file gd32f3x0_usart.c.

965 {
966 USART_CTL0(usart_periph) |= USART_CTL0_UESM;
967 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UESM
#define USART_CTL0_UESM
Definition: gd32f3x0_usart.h:38
void usart_wakeup_mode_config | ( | uint32_t | usart_periph,
 |  | uint32_t | wum
 | ) |  |

wakeup mode from deep-sleep mode

Parameters
[in] | usart_periph | USARTx(x=0)
[in] wum wakeup mode
  • USART_WUM_ADDR: WUF active on address match
  • USART_WUM_STARTB: WUF active on start bit
  • USART_WUM_RBNE: WUF active on RBNE
[out] | none
Return values
none

Definition at line 990 of file gd32f3x0_usart.c.

991 {
992 /* disable USART */
993 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
994 /* reset WUM bit */
995 USART_CTL2(usart_periph) &= ~(USART_CTL2_WUM);
996 USART_CTL2(usart_periph) |= USART_CTL2_WUM & (wum);
997 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_WUM
#define USART_CTL2_WUM
Definition: gd32f3x0_usart.h:96
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_word_length_set | ( | uint32_t | usart_periph,
 |  | uint32_t | wlen
 | ) |  |

configure USART word length

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] wlen USART word length configure
  • USART_WL_8BIT: 8 bits
  • USART_WL_9BIT: 9 bits
[out] | none
Return values
none

Definition at line 100 of file gd32f3x0_usart.c.

101 {
102 /* disable USART */
103 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
104 /* clear USART_CTL0 WL bit */
105 USART_CTL0(usart_periph) &= ~USART_CTL0_WL;
106 /* configure USART word length */
107 USART_CTL0(usart_periph) |= wlen;
108 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_WL
#define USART_CTL0_WL
Definition: gd32f3x0_usart.h:49
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_wwdgt.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
Macros | Functions
gd32f3x0_wwdgt.h File Reference

definitions for the WWDGT More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | WWDGT WWDGT_BASE
#define | WWDGT_CTL REG32((WWDGT) + 0x00U)
#define | WWDGT_CFG REG32((WWDGT) + 0x04U)
#define | WWDGT_STAT REG32((WWDGT) + 0x08U)
#define | WWDGT_CTL_CNT BITS(0,6)
#define | WWDGT_CTL_WDGTEN BIT(7)
#define | WWDGT_CFG_WIN BITS(0,6)
#define | WWDGT_CFG_PSC BITS(7,8)
#define | WWDGT_CFG_EWIE BIT(9)
#define | WWDGT_STAT_EWIF BIT(0)
#define | CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
#define | CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
#define | CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U))
#define | WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0))
#define | WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1))
#define | WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2))
#define | WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3))

Functions

void | wwdgt_deinit (void)
reset the window watchdog timer configuration More...
void | wwdgt_enable (void)
start the window watchdog timer counter More...
void | wwdgt_counter_update (uint16_t counter_value)
configure the window watchdog timer counter value More...
void | wwdgt_config (uint16_t counter, uint16_t window, uint32_t prescaler)
configure counter value, window value, and prescaler divider value More...
void | wwdgt_interrupt_enable (void)
enable early wakeup interrupt of WWDGT More...
FlagStatus | wwdgt_flag_get (void)
check early wakeup interrupt state of WWDGT More...
void | wwdgt_flag_clear (void)
clear early wakeup interrupt state of WWDGT More...

Detailed Description

definitions for the WWDGT

Definition in file gd32f3x0_wwdgt.h.

Macro Definition Documentation

#define CFG_PSC ( regval ) (BITS(7,8) & ((uint32_t)(regval) << 7U))

write value to WWDGT_CFG_PSC bit field

Definition at line 45 of file gd32f3x0_wwdgt.h.

#define CFG_WIN ( regval ) (BITS(0,6) & ((uint32_t)(regval) << 0U))

write value to WWDGT_CFG_WIN bit field

Definition at line 43 of file gd32f3x0_wwdgt.h.

#define CTL_CNT ( regval ) (BITS(0,6) & ((uint32_t)(regval) << 0U))

write value to WWDGT_CTL_CNT bit field

Definition at line 40 of file gd32f3x0_wwdgt.h.

#define WWDGT WWDGT_BASE

Definition at line 18 of file gd32f3x0_wwdgt.h.

#define WWDGT_CFG REG32((WWDGT) + 0x04U)

WWDGT configuration register

Definition at line 22 of file gd32f3x0_wwdgt.h.

#define WWDGT_CFG_EWIE BIT(9)

WWDGT early wakeup interrupt enable

Definition at line 33 of file gd32f3x0_wwdgt.h.

#define WWDGT_CFG_PSC BITS(7,8)

WWDGT prescaler divider value

Definition at line 32 of file gd32f3x0_wwdgt.h.

#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0))

the time base of WWDGT = (PCLK1/4096)/1

Definition at line 46 of file gd32f3x0_wwdgt.h.

#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1))

the time base of WWDGT = (PCLK1/4096)/2

Definition at line 47 of file gd32f3x0_wwdgt.h.

#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2))

the time base of WWDGT = (PCLK1/4096)/4

Definition at line 48 of file gd32f3x0_wwdgt.h.

#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3))

the time base of WWDGT = (PCLK1/4096)/8

Definition at line 49 of file gd32f3x0_wwdgt.h.

#define WWDGT_CFG_WIN BITS(0,6)

WWDGT counter window value

Definition at line 31 of file gd32f3x0_wwdgt.h.

#define WWDGT_CTL REG32((WWDGT) + 0x00U)

WWDGT control register

Definition at line 21 of file gd32f3x0_wwdgt.h.

#define WWDGT_CTL_CNT BITS(0,6)

WWDGT counter value

Definition at line 27 of file gd32f3x0_wwdgt.h.

#define WWDGT_CTL_WDGTEN BIT(7)

WWDGT counter enable

Definition at line 28 of file gd32f3x0_wwdgt.h.

#define WWDGT_STAT REG32((WWDGT) + 0x08U)

WWDGT status register

Definition at line 23 of file gd32f3x0_wwdgt.h.

#define WWDGT_STAT_EWIF BIT(0)

WWDGT early wakeup interrupt flag

Definition at line 36 of file gd32f3x0_wwdgt.h.

Function Documentation

void wwdgt_config | ( | uint16_t | counter,
 |  | uint16_t | window,
 |  | uint32_t | prescaler
 | ) |  |

configure counter value, window value, and prescaler divider value

Parameters
[in] | counter | 0x00 - 0x7F
[in] | window | 0x00 - 0x7F
[in] prescaler wwdgt prescaler value
  • WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
  • WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
  • WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
  • WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
[out] | none
Return values
none

Definition at line 66 of file gd32f3x0_wwdgt.c.

67 {
68 uint32_t reg_cfg = 0x0U, reg_ctl = 0x0U;
69
70 /* clear WIN and PSC bits, clear CNT bit */
71 reg_cfg = WWDGT_CFG &(~((uint32_t)WWDGT_CFG_WIN|(uint32_t)WWDGT_CFG_PSC));
72 reg_ctl = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT);
73
74 /* configure WIN and PSC bits, configure CNT bit */
75 reg_cfg |= (uint32_t)(CFG_WIN(window));
76 reg_cfg |= (uint32_t)(prescaler);
77 reg_ctl |= (uint32_t)(CTL_CNT(counter));
78
79 WWDGT_CFG = (uint32_t)reg_cfg;
80 WWDGT_CTL = (uint32_t)reg_ctl;
81 }
CTL_CNT
#define CTL_CNT(regval)
Definition: gd32f3x0_wwdgt.h:40
WWDGT_CFG_WIN
#define WWDGT_CFG_WIN
Definition: gd32f3x0_wwdgt.h:31
WWDGT_CFG
#define WWDGT_CFG
Definition: gd32f3x0_wwdgt.h:22
WWDGT_CTL
#define WWDGT_CTL
Definition: gd32f3x0_wwdgt.h:21
CFG_WIN
#define CFG_WIN(regval)
Definition: gd32f3x0_wwdgt.h:43
WWDGT_CTL_CNT
#define WWDGT_CTL_CNT
Definition: gd32f3x0_wwdgt.h:27
WWDGT_CFG_PSC
#define WWDGT_CFG_PSC
Definition: gd32f3x0_wwdgt.h:32
void wwdgt_counter_update ( uint16_t counter_value )

configure the window watchdog timer counter value

Parameters
[in] | counter_value | 0x00 - 0x7F
[out] | none
Return values
none

Definition at line 33 of file gd32f3x0_wwdgt.c.

34 {
35 uint32_t reg = 0x0U;
36
37 reg = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT);
38 reg |= (uint32_t)(CTL_CNT(counter_value));
39
40 WWDGT_CTL = (uint32_t)reg;
41 }
CTL_CNT
#define CTL_CNT(regval)
Definition: gd32f3x0_wwdgt.h:40
WWDGT_CTL
#define WWDGT_CTL
Definition: gd32f3x0_wwdgt.h:21
WWDGT_CTL_CNT
#define WWDGT_CTL_CNT
Definition: gd32f3x0_wwdgt.h:27
void wwdgt_deinit ( void )

reset the window watchdog timer configuration

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 21 of file gd32f3x0_wwdgt.c.

22 {
23 rcu_periph_reset_enable(RCU_WWDGTRST);
24 rcu_periph_reset_disable(RCU_WWDGTRST);
25 }
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
RCU_WWDGTRST
Definition: gd32f3x0_rcu.h:347
void wwdgt_enable ( void )

start the window watchdog timer counter

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 49 of file gd32f3x0_wwdgt.c.

50 {
51 WWDGT_CTL |= WWDGT_CTL_WDGTEN;
52 }
WWDGT_CTL_WDGTEN
#define WWDGT_CTL_WDGTEN
Definition: gd32f3x0_wwdgt.h:28
WWDGT_CTL
#define WWDGT_CTL
Definition: gd32f3x0_wwdgt.h:21
void wwdgt_flag_clear ( void )

clear early wakeup interrupt state of WWDGT

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 114 of file gd32f3x0_wwdgt.c.

115 {
116 WWDGT_STAT &= (uint32_t)(~(uint32_t)WWDGT_STAT_EWIF);
117 }
WWDGT_STAT_EWIF
#define WWDGT_STAT_EWIF
Definition: gd32f3x0_wwdgt.h:36
WWDGT_STAT
#define WWDGT_STAT
Definition: gd32f3x0_wwdgt.h:23
FlagStatus wwdgt_flag_get ( void )

check early wakeup interrupt state of WWDGT

Parameters
[in] | none
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 100 of file gd32f3x0_wwdgt.c.

101 {
102 if(WWDGT_STAT & WWDGT_STAT_EWIF){
103 return SET;
104 }
105 return RESET;
106 }
WWDGT_STAT_EWIF
#define WWDGT_STAT_EWIF
Definition: gd32f3x0_wwdgt.h:36
WWDGT_STAT
#define WWDGT_STAT
Definition: gd32f3x0_wwdgt.h:23
void wwdgt_interrupt_enable ( void )

enable early wakeup interrupt of WWDGT

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 89 of file gd32f3x0_wwdgt.c.

90 {
91 WWDGT_CFG |= WWDGT_CFG_EWIE;
92 }
WWDGT_CFG
#define WWDGT_CFG
Definition: gd32f3x0_wwdgt.h:22
WWDGT_CFG_EWIE
#define WWDGT_CFG_EWIE
Definition: gd32f3x0_wwdgt.h:33
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source Directory Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Source Directory Reference

Files

file | gd32f3x0_adc.c [code]
ADC driver.
file | gd32f3x0_cec.c [code]
CEC driver.
file | gd32f3x0_cmp.c [code]
CMP driver.
file | gd32f3x0_crc.c [code]
CRC driver.
file | gd32f3x0_ctc.c [code]
CTC driver.
file | gd32f3x0_dac.c [code]
DAC driver.
file | gd32f3x0_dbg.c [code]
DBG driver.
file | gd32f3x0_dma.c [code]
DMA driver.
file | gd32f3x0_exti.c [code]
EXTI driver.
file | gd32f3x0_fmc.c [code]
FMC driver.
file | gd32f3x0_fwdgt.c [code]
FWDGT driver.
file | gd32f3x0_gpio.c [code]
GPIO driver.
file | gd32f3x0_i2c.c [code]
I2C driver.
file | gd32f3x0_misc.c [code]
MISC driver.
file | gd32f3x0_pmu.c [code]
PMU driver.
file | gd32f3x0_rcu.c [code]
RCU driver.
file | gd32f3x0_rtc.c [code]
RTC driver.
file | gd32f3x0_spi.c [code]
SPI driver.
file | gd32f3x0_syscfg.c [code]
SYSCFG driver.
file | gd32f3x0_timer.c [code]
TIMER driver.
file | gd32f3x0_tsi.c [code]
tsi driver
file | gd32f3x0_usart.c [code]
USART driver.
file | gd32f3x0_wwdgt.c [code]
WWDGT driver.


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_adc.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_adc.c File Reference

ADC driver. More...

#include "gd32f3x0_adc.h"

Go to the source code of this file.

Functions

void | adc_deinit (void)
reset ADC More...
void | adc_enable (void)
enable ADC interface More...
void | adc_disable (void)
disable ADC interface More...
void | adc_calibration_enable (void)
ADC calibration and reset calibration. More...
void | adc_dma_mode_enable (void)
enable DMA request More...
void | adc_dma_mode_disable (void)
disable DMA request More...
void | adc_tempsensor_vrefint_enable (void)
enable the temperature sensor and Vrefint channel More...
void | adc_tempsensor_vrefint_disable (void)
disable the temperature sensor and Vrefint channel More...
void | adc_vbat_enable (void)
enable the vbat channel More...
void | adc_vbat_disable (void)
disable the vbat channel More...
void | adc_resolution_config (uint32_t resolution)
configure ADC resolution More...
void | adc_discontinuous_mode_config (uint8_t channel_group, uint8_t length)
configure ADC discontinuous mode More...
void | adc_special_function_config (uint32_t function, ControlStatus newvalue)
configure ADC special function More...
void | adc_data_alignment_config (uint32_t data_alignment)
configure ADC data alignment More...
void | adc_channel_length_config (uint8_t channel_group, uint32_t length)
configure the length of regular channel group or inserted channel group More...
void | adc_regular_channel_config (uint8_t rank, uint8_t channel, uint32_t sample_time)
configure ADC regular channel More...
void | adc_inserted_channel_config (uint8_t rank, uint8_t channel, uint32_t sample_time)
configure ADC inserted channel More...
void | adc_inserted_channel_offset_config (uint8_t inserted_channel, uint16_t offset)
configure ADC inserted channel offset More...
void | adc_external_trigger_config (uint8_t channel_group, ControlStatus newvalue)
enable or disable ADC external trigger More...
void | adc_external_trigger_source_config (uint8_t channel_group, uint32_t external_trigger_source)
configure ADC external trigger source More...
void | adc_software_trigger_enable (uint8_t channel_group)
enable ADC software trigger More...
uint16_t | adc_regular_data_read (void)
read ADC regular group data register More...
uint16_t | adc_inserted_data_read (uint8_t inserted_channel)
read ADC inserted group data register More...
FlagStatus | adc_flag_get (uint32_t flag)
get the ADC flag bits More...
void | adc_flag_clear (uint32_t flag)
clear the ADC flag More...
FlagStatus | adc_interrupt_flag_get (uint32_t flag)
get the ADC interrupt flag More...
void | adc_interrupt_flag_clear (uint32_t flag)
clear ADC interrupt flag More...
void | adc_interrupt_enable (uint32_t interrupt)
enable ADC interrupt More...
void | adc_interrupt_disable (uint32_t interrupt)
disable ADC interrupt More...
void | adc_watchdog_single_channel_enable (uint8_t channel)
configure ADC analog watchdog single channel More...
void | adc_watchdog_group_channel_enable (uint8_t channel_group)
configure ADC analog watchdog group channel More...
void | adc_watchdog_disable (void)
disable ADC analog watchdog More...
void | adc_watchdog_threshold_config (uint16_t low_threshold, uint16_t high_threshold)
configure ADC analog watchdog threshold More...
void | adc_oversample_mode_config (uint8_t mode, uint16_t shift, uint8_t ratio)
configure ADC oversample mode More...
void | adc_oversample_mode_enable (void)
enable ADC oversample mode More...
void | adc_oversample_mode_disable (void)
disable ADC oversample mode More...

Detailed Description

ADC driver.

Definition in file gd32f3x0_adc.c.

Function Documentation

void adc_calibration_enable ( void )

ADC calibration and reset calibration.

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 56 of file gd32f3x0_adc.c.

57 {
58 /* reset the selected ADC calibration register */
59 ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB;
60 /* check the RSTCLB bit state */
61 while((ADC_CTL1 & ADC_CTL1_RSTCLB)){
62 }
63
64 /* enable ADC calibration process */
65 ADC_CTL1 |= ADC_CTL1_CLB;
66 /* check the CLB bit state */
67 while((ADC_CTL1 & ADC_CTL1_CLB)){
68 }
69 }
ADC_CTL1_RSTCLB
#define ADC_CTL1_RSTCLB
Definition: gd32f3x0_adc.h:70
ADC_CTL1_CLB
#define ADC_CTL1_CLB
Definition: gd32f3x0_adc.h:69
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_channel_length_config | ( | uint8_t | channel_group,
 |  | uint32_t | length
 | ) |  |

configure the length of regular channel group or inserted channel group

Parameters
[in] channel_group select the channel group only one parameter can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[in] | length | the length of the channel regular channel 1-16 inserted channel 1-4
[out] | none
Return values
none

Definition at line 262 of file gd32f3x0_adc.c.

263 {
264 switch(channel_group){
265 case ADC_REGULAR_CHANNEL:
266 /* configure the length of regular channel group */
267 ADC_RSQ0 &= ~((uint32_t)ADC_RSQ0_RL);
268 ADC_RSQ0 |= RSQ0_RL((uint32_t)(length-1U));
269 break;
270 case ADC_INSERTED_CHANNEL:
271 /* configure the length of inserted channel group */
272 ADC_ISQ &= ~((uint32_t)ADC_ISQ_IL);
273 ADC_ISQ |= ISQ_IL((uint32_t)(length-1U));
274 break;
275 default:
276 break;
277 }
278 }
ADC_ISQ_IL
#define ADC_ISQ_IL
Definition: gd32f3x0_adc.h:100
ADC_ISQ
#define ADC_ISQ
Definition: gd32f3x0_adc.h:35
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f3x0_adc.h:217
ISQ_IL
#define ISQ_IL(regval)
Definition: gd32f3x0_adc.h:180
ADC_RSQ0
#define ADC_RSQ0
Definition: gd32f3x0_adc.h:32
ADC_RSQ0_RL
#define ADC_RSQ0_RL
Definition: gd32f3x0_adc.h:96
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:218
RSQ0_RL
#define RSQ0_RL(regval)
Definition: gd32f3x0_adc.h:177
void adc_data_alignment_config ( uint32_t data_alignment )

configure ADC data alignment

Parameters
[in] data_alignment data alignment select only one parameter can be selected
  • ADC_DATAALIGN_RIGHT: LSB alignment
  • ADC_DATAALIGN_LEFT: MSB alignment
[out] none
Return values
none

Definition at line 241 of file gd32f3x0_adc.c.

242 {
243 if(ADC_DATAALIGN_RIGHT != data_alignment){
244 ADC_CTL1 |= ADC_CTL1_DAL;
245 }else{
246 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DAL);
247 }
248 }
ADC_CTL1_DAL
#define ADC_CTL1_DAL
Definition: gd32f3x0_adc.h:72
ADC_DATAALIGN_RIGHT
#define ADC_DATAALIGN_RIGHT
Definition: gd32f3x0_adc.h:131
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_deinit ( void )

reset ADC

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_adc.c.

21 {
22 rcu_periph_reset_enable(RCU_ADCRST);
23 rcu_periph_reset_disable(RCU_ADCRST);
24 }
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
RCU_ADCRST
Definition: gd32f3x0_rcu.h:335
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
void adc_disable ( void )

disable ADC interface

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 45 of file gd32f3x0_adc.c.

46 {
47 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ADCON);
48 }
ADC_CTL1_ADCON
#define ADC_CTL1_ADCON
Definition: gd32f3x0_adc.h:67
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_discontinuous_mode_config | ( | uint8_t | channel_group,
 |  | uint8_t | length
 | ) |  |

configure ADC discontinuous mode

Parameters
[in] channel_group select the channel group only one among these parameters can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
  • ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular and inserted channel
[in] | length | number of conversions in discontinuous mode,the number can be 1..8 for regular channel, the number has no effect for inserted channel
[out] | none
Return values
none

Definition at line 170 of file gd32f3x0_adc.c.

171 {
172 ADC_CTL0 &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
173
174 switch(channel_group){
175 case ADC_REGULAR_CHANNEL:
176 /* configure the number of conversions in discontinuous mode */
177 ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DISNUM);
178 ADC_CTL0 |= CTL0_DISNUM(((uint32_t)length - 1U));
179 ADC_CTL0 |= (uint32_t)ADC_CTL0_DISRC;
180 break;
181 case ADC_INSERTED_CHANNEL:
182 ADC_CTL0 |= (uint32_t)ADC_CTL0_DISIC;
183 break;
184 case ADC_CHANNEL_DISCON_DISABLE:
185 default:
186 break;
187 }
188 }
CTL0_DISNUM
#define CTL0_DISNUM(regval)
Definition: gd32f3x0_adc.h:123
ADC_CTL0_DISRC
#define ADC_CTL0_DISRC
Definition: gd32f3x0_adc.h:59
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f3x0_adc.h:217
ADC_CTL0_DISNUM
#define ADC_CTL0_DISNUM
Definition: gd32f3x0_adc.h:61
ADC_CHANNEL_DISCON_DISABLE
#define ADC_CHANNEL_DISCON_DISABLE
Definition: gd32f3x0_adc.h:220
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:218
ADC_CTL0_DISIC
#define ADC_CTL0_DISIC
Definition: gd32f3x0_adc.h:60
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_dma_mode_disable ( void )

disable DMA request

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 88 of file gd32f3x0_adc.c.

89 {
90 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DMA);
91 }
ADC_CTL1_DMA
#define ADC_CTL1_DMA
Definition: gd32f3x0_adc.h:71
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_dma_mode_enable ( void )

enable DMA request

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 77 of file gd32f3x0_adc.c.

78 {
79 ADC_CTL1 |= (uint32_t)(ADC_CTL1_DMA);
80 }
ADC_CTL1_DMA
#define ADC_CTL1_DMA
Definition: gd32f3x0_adc.h:71
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_enable ( void )

enable ADC interface

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 32 of file gd32f3x0_adc.c.

33 {
34 if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)){
35 ADC_CTL1 |= (uint32_t)ADC_CTL1_ADCON;
36 }
37 }
ADC_CTL1_ADCON
#define ADC_CTL1_ADCON
Definition: gd32f3x0_adc.h:67
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_external_trigger_config | ( | uint8_t | channel_group,
 |  | ControlStatus | newvalue
 | ) |  |

enable or disable ADC external trigger

Parameters
[in] channel_group select the channel group one or more parameters can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 423 of file gd32f3x0_adc.c.

424 {
425 if(newvalue){
426 /* external trigger enable for regular channel */
427 if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
428 ADC_CTL1 |= ADC_CTL1_ETERC;
429 }
430 /* external trigger enable for inserted channel */
431 if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
432 ADC_CTL1 |= ADC_CTL1_ETEIC;
433 }
434 }else{
435 /* external trigger disable for regular channel */
436 if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
437 ADC_CTL1 &= ~ADC_CTL1_ETERC;
438 }
439 /* external trigger disable for inserted channel */
440 if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
441 ADC_CTL1 &= ~ADC_CTL1_ETEIC;
442 }
443 }
444 }
ADC_CTL1_ETEIC
#define ADC_CTL1_ETEIC
Definition: gd32f3x0_adc.h:74
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f3x0_adc.h:217
ADC_CTL1_ETERC
#define ADC_CTL1_ETERC
Definition: gd32f3x0_adc.h:76
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:218
void adc_external_trigger_source_config | ( | uint8_t | channel_group,
 |  | uint32_t | external_trigger_source
 | ) |  |

configure ADC external trigger source

Parameters
[in] channel_group select the channel group only one parameter can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[in] external_trigger_source regular or inserted group trigger source only one parameter can be selected for regular channel:
  • ADC_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select
  • ADC_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select
  • ADC_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select
  • ADC_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select
  • ADC_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select
  • ADC_EXTTRIG_REGULAR_T14_CH1: TIMER14 CH1 event select
  • ADC_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11
  • ADC_EXTTRIG_REGULAR_NONE: software trigger for inserted channel:
  • ADC_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select
  • ADC_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select
  • ADC_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select
  • ADC_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select
  • ADC_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select
  • ADC_EXTTRIG_INSERTED_T14_TRGO: TIMER14 TRGO event select
  • ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15
  • ADC_EXTTRIG_INSERTED_NONE: software trigger
[out] none
Return values
none

Definition at line 475 of file gd32f3x0_adc.c.

476 {
477 switch(channel_group){
478 case ADC_REGULAR_CHANNEL:
479 /* external trigger select for regular channel */
480 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSRC);
481 ADC_CTL1 |= (uint32_t)external_trigger_source;
482 break;
483 case ADC_INSERTED_CHANNEL:
484 /* external trigger select for inserted channel */
485 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSIC);
486 ADC_CTL1 |= (uint32_t)external_trigger_source;
487 break;
488 default:
489 break;
490 }
491 }
ADC_CTL1_ETSIC
#define ADC_CTL1_ETSIC
Definition: gd32f3x0_adc.h:73
ADC_CTL1_ETSRC
#define ADC_CTL1_ETSRC
Definition: gd32f3x0_adc.h:75
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f3x0_adc.h:217
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:218
void adc_flag_clear ( uint32_t flag )

clear the ADC flag

Parameters
[in] flag the adc flag one or more parameters can be selected
  • ADC_FLAG_WDE: analog watchdog event flag
  • ADC_FLAG_EOC: end of group conversion flag
  • ADC_FLAG_EOIC: end of inserted group conversion flag
  • ADC_FLAG_STIC: start flag of inserted channel group
  • ADC_FLAG_STRC: start flag of regular channel group
[out] none
Return values
none

Definition at line 594 of file gd32f3x0_adc.c.

595 {
596 ADC_STAT &= ~((uint32_t)flag);
597 }
ADC_STAT
#define ADC_STAT
Definition: gd32f3x0_adc.h:21
FlagStatus adc_flag_get ( uint32_t flag )

get the ADC flag bits

Parameters
[in] flag the adc flag bits only one parameter can be selected
  • ADC_FLAG_WDE: analog watchdog event flag
  • ADC_FLAG_EOC: end of group conversion flag
  • ADC_FLAG_EOIC: end of inserted group conversion flag
  • ADC_FLAG_STIC: start flag of inserted channel group
  • ADC_FLAG_STRC: start flag of regular channel group
[out] none
Return values
FlagStatus SET or RESET

Definition at line 572 of file gd32f3x0_adc.c.

573 {
574 FlagStatus reval = RESET;
575
576 if(ADC_STAT & flag){
577 reval = SET;
578 }
579 return reval;
580 }
ADC_STAT
#define ADC_STAT
Definition: gd32f3x0_adc.h:21
void adc_inserted_channel_config | ( | uint8_t | rank,
 |  | uint8_t | channel,
 |  | uint32_t | sample_time
 | ) |  |

configure ADC inserted channel

Parameters
[in] | rank | the inserted group sequencer rank,this parameter must be between 0 to 3
[in] channel the selected ADC channel only one among these parameters can be selected
  • ADC_CHANNEL_x(x=0..18): ADC Channelx
[in] sample_time The sample time value only one parameter can be selected
  • ADC_SAMPLETIME_1POINT5: 1.5 cycles
  • ADC_SAMPLETIME_7POINT5: 7.5 cycles
  • ADC_SAMPLETIME_13POINT5: 13.5 cycles
  • ADC_SAMPLETIME_28POINT5: 28.5 cycles
  • ADC_SAMPLETIME_41POINT5: 41.5 cycles
  • ADC_SAMPLETIME_55POINT5: 55.5 cycles
  • ADC_SAMPLETIME_71POINT5: 71.5 cycles
  • ADC_SAMPLETIME_239POINT5: 239.5 cycles
[out] | none
Return values
none

Definition at line 357 of file gd32f3x0_adc.c.

358 {
359 uint8_t inserted_length;
360 uint32_t isq,sampt;
361
362 inserted_length = (uint8_t)GET_BITS(ADC_ISQ , 20U , 21U);
363
364 isq = ADC_ISQ;
365 isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U - (inserted_length - rank)*5U)));
366 isq |= ((uint32_t)channel << (15U - (inserted_length - rank)*5U));
367 ADC_ISQ = isq;
368
369 /* configure ADC sampling time */
370 if(channel < 10U){
371 sampt = ADC_SAMPT1;
372 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel)));
373 sampt |= (uint32_t) sample_time << (3U*channel);
374 ADC_SAMPT1 = sampt;
375 }else if(channel < 19U){
376 sampt = ADC_SAMPT0;
377 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel - 10U))));
378 sampt |= ((uint32_t)sample_time << (3U*(channel - 10U)));
379 ADC_SAMPT0 = sampt;
380 }else{
381 /* illegal parameters */
382 }
383 }
ADC_SAMPT0
#define ADC_SAMPT0
Definition: gd32f3x0_adc.h:24
ADC_ISQ_ISQN
#define ADC_ISQ_ISQN
Definition: gd32f3x0_adc.h:99
ADC_ISQ
#define ADC_ISQ
Definition: gd32f3x0_adc.h:35
ADC_SAMPT1
#define ADC_SAMPT1
Definition: gd32f3x0_adc.h:25
ADC_SAMPTX_SPTN
#define ADC_SAMPTX_SPTN
Definition: gd32f3x0_adc.h:83
void adc_inserted_channel_offset_config | ( | uint8_t | inserted_channel,
 |  | uint16_t | offset
 | ) |  |

configure ADC inserted channel offset

Parameters
[in] inserted_channel insert channel select only one parameter can be selected
  • ADC_INSERTED_CHANNEL_0: ADC inserted channel 0
  • ADC_INSERTED_CHANNEL_1: ADC inserted channel 1
  • ADC_INSERTED_CHANNEL_2: ADC inserted channel 2
  • ADC_INSERTED_CHANNEL_3: ADC inserted channel 3
[in] | offset | the offset data
[out] | none
Return values
none

Definition at line 397 of file gd32f3x0_adc.c.

398 {
399 uint8_t inserted_length;
400 uint32_t num = 0U;
401
402 inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U);
403 num = 3U - (inserted_length - inserted_channel);
404
405 if(num <= 3U){
406 /* calculate the offset of the register */
407 num = num * 4U;
408 /* configure the offset of the selected channels */
409 REG32((ADC) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
410 }
411 }
ADC_ISQ
#define ADC_ISQ
Definition: gd32f3x0_adc.h:35
ADC
#define ADC
Definition: gd32f3x0_adc.h:18
IOFFX_IOFF
#define IOFFX_IOFF(regval)
Definition: gd32f3x0_adc.h:168
uint16_t adc_inserted_data_read ( uint8_t inserted_channel )

read ADC inserted group data register

Parameters
[in] inserted_channel inserted channel select only one parameter can be selected
  • ADC_INSERTED_CHANNEL_0: ADC inserted channel 0
  • ADC_INSERTED_CHANNEL_1: ADC inserted channel 1
  • ADC_INSERTED_CHANNEL_2: ADC inserted channel 2
  • ADC_INSERTED_CHANNEL_3: ADC inserted channel 3
[out] none
Return values
the conversion value

Definition at line 536 of file gd32f3x0_adc.c.

537 {
538 uint32_t idata;
539 /* read the data of the selected channel */
540 switch(inserted_channel){
541 case ADC_INSERTED_CHANNEL_0:
542 idata = ADC_IDATA0;
543 break;
544 case ADC_INSERTED_CHANNEL_1:
545 idata = ADC_IDATA1;
546 break;
547 case ADC_INSERTED_CHANNEL_2:
548 idata = ADC_IDATA2;
549 break;
550 case ADC_INSERTED_CHANNEL_3:
551 idata = ADC_IDATA3;
552 break;
553 default:
554 idata = 0U;
555 break;
556 }
557 return (uint16_t)idata;
558 }
ADC_IDATA2
#define ADC_IDATA2
Definition: gd32f3x0_adc.h:38
ADC_IDATA0
#define ADC_IDATA0
Definition: gd32f3x0_adc.h:36
ADC_INSERTED_CHANNEL_1
#define ADC_INSERTED_CHANNEL_1
Definition: gd32f3x0_adc.h:224
ADC_INSERTED_CHANNEL_3
#define ADC_INSERTED_CHANNEL_3
Definition: gd32f3x0_adc.h:226
ADC_IDATA3
#define ADC_IDATA3
Definition: gd32f3x0_adc.h:39
ADC_INSERTED_CHANNEL_0
#define ADC_INSERTED_CHANNEL_0
Definition: gd32f3x0_adc.h:223
ADC_IDATA1
#define ADC_IDATA1
Definition: gd32f3x0_adc.h:37
ADC_INSERTED_CHANNEL_2
#define ADC_INSERTED_CHANNEL_2
Definition: gd32f3x0_adc.h:225
void adc_interrupt_disable ( uint32_t interrupt )

disable ADC interrupt

Parameters
[in] interrupt the adc interrupt flag one or more parameters can be selected
  • ADC_INT_WDE: analog watchdog interrupt
  • ADC_INT_EOC: end of group conversion interrupt
  • ADC_INT_EOIC: end of inserted group conversion interrupt
[out] none
Return values
none

Definition at line 693 of file gd32f3x0_adc.c.

694 {
695 /* disable analog watchdog interrupt */
696 if(RESET != (interrupt & ADC_INT_WDE)){
697 ADC_CTL0 &= ~(uint32_t)ADC_CTL0_WDEIE;
698 }
699
700 /* disable end of group conversion interrupt */
701 if(RESET != (interrupt & ADC_INT_EOC)){
702 ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOCIE;
703 }
704
705 /* disable end of inserted group conversion interrupt */
706 if(RESET != (interrupt & ADC_INT_EOIC)){
707 ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOICIE;
708 }
709 }
ADC_INT_EOC
#define ADC_INT_EOC
Definition: gd32f3x0_adc.h:251
ADC_CTL0_WDEIE
#define ADC_CTL0_WDEIE
Definition: gd32f3x0_adc.h:54
ADC_INT_WDE
#define ADC_INT_WDE
Definition: gd32f3x0_adc.h:250
ADC_CTL0_EOICIE
#define ADC_CTL0_EOICIE
Definition: gd32f3x0_adc.h:55
ADC_INT_EOIC
#define ADC_INT_EOIC
Definition: gd32f3x0_adc.h:252
ADC_CTL0_EOCIE
#define ADC_CTL0_EOCIE
Definition: gd32f3x0_adc.h:53
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_interrupt_enable ( uint32_t interrupt )

enable ADC interrupt

Parameters
[in] interrupt the adc interrupt one or more parameters can be selected
  • ADC_INT_WDE: analog watchdog interrupt
  • ADC_INT_EOC: end of group conversion interrupt
  • ADC_INT_EOIC: end of inserted group conversion interrupt
[out] none
Return values
none

Definition at line 665 of file gd32f3x0_adc.c.

666 {
667 /* enable analog watchdog interrupt */
668 if(RESET != (interrupt & ADC_INT_WDE)){
669 ADC_CTL0 |= (uint32_t)ADC_CTL0_WDEIE;
670 }
671
672 /* enable end of group conversion interrupt */
673 if(RESET != (interrupt & ADC_INT_EOC)){
674 ADC_CTL0 |= (uint32_t)ADC_CTL0_EOCIE;
675 }
676
677 /* enable end of inserted group conversion interrupt */
678 if(RESET != (interrupt & ADC_INT_EOIC)){
679 ADC_CTL0 |= (uint32_t)ADC_CTL0_EOICIE;
680 }
681 }
ADC_INT_EOC
#define ADC_INT_EOC
Definition: gd32f3x0_adc.h:251
ADC_CTL0_WDEIE
#define ADC_CTL0_WDEIE
Definition: gd32f3x0_adc.h:54
ADC_INT_WDE
#define ADC_INT_WDE
Definition: gd32f3x0_adc.h:250
ADC_CTL0_EOICIE
#define ADC_CTL0_EOICIE
Definition: gd32f3x0_adc.h:55
ADC_INT_EOIC
#define ADC_INT_EOIC
Definition: gd32f3x0_adc.h:252
ADC_CTL0_EOCIE
#define ADC_CTL0_EOCIE
Definition: gd32f3x0_adc.h:53
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_interrupt_flag_clear ( uint32_t flag )

clear ADC interrupt flag

Parameters
[in] flag the adc interrupt flag only oneparameter can be selected
  • ADC_INT_FLAG_WDE: analog watchdog interrupt flag
  • ADC_INT_FLAG_EOC: end of group conversion interrupt flag
  • ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag
[out] none
Return values
none

Definition at line 650 of file gd32f3x0_adc.c.

651 {
652 ADC_STAT &= ~((uint32_t)flag);
653 }
ADC_STAT
#define ADC_STAT
Definition: gd32f3x0_adc.h:21
FlagStatus adc_interrupt_flag_get ( uint32_t flag )

get the ADC interrupt flag

Parameters
[in] flag the adc interrupt flag only oneparameter can be selected
  • ADC_INT_FLAG_WDE: analog watchdog interrupt flag
  • ADC_INT_FLAG_EOC: end of group conversion interrupt flag
  • ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 609 of file gd32f3x0_adc.c.

610 {
611 FlagStatus interrupt_flag = RESET;
612 uint32_t state;
613
614 /* check the interrupt bits */
615 switch(flag){
616 case ADC_INT_FLAG_WDE:
617 state = ADC_STAT & ADC_STAT_WDE;
618 if((ADC_CTL0 & ADC_CTL0_WDEIE) && state){
619 interrupt_flag = SET;
620 }
621 break;
622 case ADC_INT_FLAG_EOC:
623 state = ADC_STAT & ADC_STAT_EOC;
624 if((ADC_CTL0 & ADC_CTL0_EOCIE) && state){
625 interrupt_flag = SET;
626 }
627 break;
628 case ADC_INT_FLAG_EOIC:
629 state = ADC_STAT & ADC_STAT_EOIC;
630 if((ADC_CTL0 & ADC_CTL0_EOICIE) && state){
631 interrupt_flag = SET;
632 }
633 break;
634 default:
635 break;
636 }
637 return interrupt_flag;
638 }
ADC_STAT_WDE
#define ADC_STAT_WDE
Definition: gd32f3x0_adc.h:45
ADC_INT_FLAG_EOIC
#define ADC_INT_FLAG_EOIC
Definition: gd32f3x0_adc.h:257
ADC_INT_FLAG_EOC
#define ADC_INT_FLAG_EOC
Definition: gd32f3x0_adc.h:256
ADC_INT_FLAG_WDE
#define ADC_INT_FLAG_WDE
Definition: gd32f3x0_adc.h:255
ADC_CTL0_WDEIE
#define ADC_CTL0_WDEIE
Definition: gd32f3x0_adc.h:54
ADC_STAT_EOIC
#define ADC_STAT_EOIC
Definition: gd32f3x0_adc.h:47
ADC_STAT
#define ADC_STAT
Definition: gd32f3x0_adc.h:21
ADC_CTL0_EOICIE
#define ADC_CTL0_EOICIE
Definition: gd32f3x0_adc.h:55
ADC_STAT_EOC
#define ADC_STAT_EOC
Definition: gd32f3x0_adc.h:46
ADC_CTL0_EOCIE
#define ADC_CTL0_EOCIE
Definition: gd32f3x0_adc.h:53
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_oversample_mode_config | ( | uint8_t | mode,
 |  | uint16_t | shift,
 |  | uint8_t | ratio
 | ) |  |

configure ADC oversample mode

Parameters
[in] mode ADC oversampling mode only oneparameter can be selected
  • ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger
  • ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger
[in] shift ADC oversampling shift only oneparameter can be selected
  • ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift
  • ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift
  • ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift
  • ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift
  • ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift
  • ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift
  • ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift
  • ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift
  • ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift
[in] ratio ADC oversampling ratio only oneparameter can be selected
  • ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2
  • ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4
  • ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8
  • ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16
  • ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32
  • ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64
  • ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128
  • ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256
[out] none
Return values
none

Definition at line 811 of file gd32f3x0_adc.c.

812 {
813 /* configure ADC oversampling mode */
814 if(ADC_OVERSAMPLING_ONE_CONVERT == mode){
815 ADC_OVSAMPCTL |= (uint32_t)ADC_OVSAMPCTL_TOVS;
816 }else{
817 ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_TOVS);
818 }
819
820 /* configure the shift and ratio */
821 ADC_OVSAMPCTL &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS));
822 ADC_OVSAMPCTL |= ((uint32_t)shift | (uint32_t)ratio);
823 }
ADC_OVSAMPCTL_TOVS
#define ADC_OVSAMPCTL_TOVS
Definition: gd32f3x0_adc.h:112
ADC_OVSAMPCTL_OVSR
#define ADC_OVSAMPCTL_OVSR
Definition: gd32f3x0_adc.h:110
ADC_OVSAMPCTL_OVSS
#define ADC_OVSAMPCTL_OVSS
Definition: gd32f3x0_adc.h:111
ADC_OVERSAMPLING_ONE_CONVERT
#define ADC_OVERSAMPLING_ONE_CONVERT
Definition: gd32f3x0_adc.h:214
ADC_OVSAMPCTL
#define ADC_OVSAMPCTL
Definition: gd32f3x0_adc.h:41
void adc_oversample_mode_disable ( void )

disable ADC oversample mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 842 of file gd32f3x0_adc.c.

843 {
844 ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN);
845 }
ADC_OVSAMPCTL_OVSEN
#define ADC_OVSAMPCTL_OVSEN
Definition: gd32f3x0_adc.h:109
ADC_OVSAMPCTL
#define ADC_OVSAMPCTL
Definition: gd32f3x0_adc.h:41
void adc_oversample_mode_enable ( void )

enable ADC oversample mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 831 of file gd32f3x0_adc.c.

832 {
833 ADC_OVSAMPCTL |= ADC_OVSAMPCTL_OVSEN;
834 }
ADC_OVSAMPCTL_OVSEN
#define ADC_OVSAMPCTL_OVSEN
Definition: gd32f3x0_adc.h:109
ADC_OVSAMPCTL
#define ADC_OVSAMPCTL
Definition: gd32f3x0_adc.h:41
void adc_regular_channel_config | ( | uint8_t | rank,
 |  | uint8_t | channel,
 |  | uint32_t | sample_time
 | ) |  |

configure ADC regular channel

Parameters
[in] | rank | the regular group sequence rank, this parameter must be between 0 to 15
[in] channel the selected ADC channel only one among these parameters can be selected
  • ADC_CHANNEL_x(x=0..18): ADC Channelx
[in] sample_time the sample time value only one parameter can be selected
  • ADC_SAMPLETIME_1POINT5: 1.5 cycles
  • ADC_SAMPLETIME_7POINT5: 7.5 cycles
  • ADC_SAMPLETIME_13POINT5: 13.5 cycles
  • ADC_SAMPLETIME_28POINT5: 28.5 cycles
  • ADC_SAMPLETIME_41POINT5: 41.5 cycles
  • ADC_SAMPLETIME_55POINT5: 55.5 cycles
  • ADC_SAMPLETIME_71POINT5: 71.5 cycles
  • ADC_SAMPLETIME_239POINT5: 239.5 cycles
[out] | none
Return values
none

Definition at line 299 of file gd32f3x0_adc.c.

300 {
301 uint32_t rsq,sampt;
302
303 /* configure ADC regular sequence */
304 if(rank < 6U){
305 rsq = ADC_RSQ2;
306 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank)));
307 rsq |= ((uint32_t)channel << (5U*rank));
308 ADC_RSQ2 = rsq;
309 }else if(rank < 12U){
310 rsq = ADC_RSQ1;
311 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U))));
312 rsq |= ((uint32_t)channel << (5U*(rank-6U)));
313 ADC_RSQ1 = rsq;
314 }else if(rank < 16U){
315 rsq = ADC_RSQ0;
316 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U))));
317 rsq |= ((uint32_t)channel << (5U*(rank-12U)));
318 ADC_RSQ0 = rsq;
319 }else{
320 }
321
322 /* configure ADC sampling time */
323 if(channel < 10U){
324 sampt = ADC_SAMPT1;
325 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel)));
326 sampt |= (uint32_t)(sample_time << (3U*channel));
327 ADC_SAMPT1 = sampt;
328 }else if(channel < 19U){
329 sampt = ADC_SAMPT0;
330 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel-10U))));
331 sampt |= (uint32_t)(sample_time << (3U*(channel-10U)));
332 ADC_SAMPT0 = sampt;
333 }else{
334 /* illegal parameters */
335 }
336 }
ADC_SAMPT0
#define ADC_SAMPT0
Definition: gd32f3x0_adc.h:24
ADC_RSQ2
#define ADC_RSQ2
Definition: gd32f3x0_adc.h:34
ADC_RSQ1
#define ADC_RSQ1
Definition: gd32f3x0_adc.h:33
ADC_RSQX_RSQN
#define ADC_RSQX_RSQN
Definition: gd32f3x0_adc.h:95
ADC_RSQ0
#define ADC_RSQ0
Definition: gd32f3x0_adc.h:32
ADC_SAMPT1
#define ADC_SAMPT1
Definition: gd32f3x0_adc.h:25
ADC_SAMPTX_SPTN
#define ADC_SAMPTX_SPTN
Definition: gd32f3x0_adc.h:83
uint16_t adc_regular_data_read ( void )

read ADC regular group data register

Parameters
[in] | none
[out] | none
Return values
the conversion value

Definition at line 520 of file gd32f3x0_adc.c.

521 {
522 return ((uint16_t)ADC_RDATA);
523 }
ADC_RDATA
#define ADC_RDATA
Definition: gd32f3x0_adc.h:40
void adc_resolution_config ( uint32_t resolution )

configure ADC resolution

Parameters
[in] resolution ADC resolution only one among these parameters can be selected
  • ADC_RESOLUTION_12B: 12-bit ADC resolution
  • ADC_RESOLUTION_10B: 10-bit ADC resolution
  • ADC_RESOLUTION_8B: 8-bit ADC resolution
  • ADC_RESOLUTION_6B: 6-bit ADC resolution
[out] none
Return values
none

Definition at line 152 of file gd32f3x0_adc.c.

153 {
154 ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DRES);
155 ADC_CTL0 |= (uint32_t)resolution;
156 }
ADC_CTL0_DRES
#define ADC_CTL0_DRES
Definition: gd32f3x0_adc.h:64
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_software_trigger_enable ( uint8_t channel_group )

enable ADC software trigger

Parameters
[in] channel_group select the channel group one or more parameters can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
[out] none
Return values
none

Definition at line 502 of file gd32f3x0_adc.c.

503 {
504 /* enable regular group channel software trigger */
505 if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
506 ADC_CTL1 |= ADC_CTL1_SWRCST;
507 }
508 /* enable inserted channel group software trigger */
509 if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
510 ADC_CTL1 |= ADC_CTL1_SWICST;
511 }
512 }
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f3x0_adc.h:217
ADC_CTL1_SWICST
#define ADC_CTL1_SWICST
Definition: gd32f3x0_adc.h:77
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:218
ADC_CTL1_SWRCST
#define ADC_CTL1_SWRCST
Definition: gd32f3x0_adc.h:78
void adc_special_function_config | ( | uint32_t | function,
 |  | ControlStatus | newvalue
 | ) |  |

configure ADC special function

Parameters
[in] function the function to configure one or more parameters can be selected below:
  • ADC_SCAN_MODE: scan mode select
  • ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
  • ADC_CONTINUOUS_MODE: continuous mode select
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 201 of file gd32f3x0_adc.c.

202 {
203 if(newvalue){
204 /* enable ADC scan mode */
205 if(RESET != (function & ADC_SCAN_MODE)){
206 ADC_CTL0 |= ADC_SCAN_MODE;
207 }
208 /* enable ADC inserted channel group convert automatically */
209 if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){
210 ADC_CTL0 |= ADC_INSERTED_CHANNEL_AUTO;
211 }
212 /* enable ADC continuous mode */
213 if(RESET != (function & ADC_CONTINUOUS_MODE)){
214 ADC_CTL1 |= ADC_CONTINUOUS_MODE;
215 }
216 }else{
217 /* disable ADC scan mode */
218 if(RESET != (function & ADC_SCAN_MODE)){
219 ADC_CTL0 &= ~ADC_SCAN_MODE;
220 }
221 /* disable ADC inserted channel group convert automatically */
222 if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){
223 ADC_CTL0 &= ~ADC_INSERTED_CHANNEL_AUTO;
224 }
225 /* disable ADC continuous mode */
226 if(RESET != (function & ADC_CONTINUOUS_MODE)){
227 ADC_CTL1 &= ~ADC_CONTINUOUS_MODE;
228 }
229 }
230 }
ADC_INSERTED_CHANNEL_AUTO
#define ADC_INSERTED_CHANNEL_AUTO
Definition: gd32f3x0_adc.h:127
ADC_CONTINUOUS_MODE
#define ADC_CONTINUOUS_MODE
Definition: gd32f3x0_adc.h:128
ADC_SCAN_MODE
#define ADC_SCAN_MODE
Definition: gd32f3x0_adc.h:126
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_tempsensor_vrefint_disable ( void )

disable the temperature sensor and Vrefint channel

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 111 of file gd32f3x0_adc.c.

112 {
113 /* disable the temperature sensor and Vrefint channel */
114 ADC_CTL1 &= ~ADC_CTL1_TSVREN;
115 }
ADC_CTL1_TSVREN
#define ADC_CTL1_TSVREN
Definition: gd32f3x0_adc.h:79
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_tempsensor_vrefint_enable ( void )

enable the temperature sensor and Vrefint channel

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 99 of file gd32f3x0_adc.c.

100 {
101 /* enable the temperature sensor and Vrefint channel */
102 ADC_CTL1 |= ADC_CTL1_TSVREN;
103 }
ADC_CTL1_TSVREN
#define ADC_CTL1_TSVREN
Definition: gd32f3x0_adc.h:79
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_vbat_disable ( void )

disable the vbat channel

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 135 of file gd32f3x0_adc.c.

136 {
137 /* disable the vbat channel */
138 ADC_CTL1 &= ~ADC_CTL1_VBETEN;
139 }
ADC_CTL1_VBETEN
#define ADC_CTL1_VBETEN
Definition: gd32f3x0_adc.h:80
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_vbat_enable ( void )

enable the vbat channel

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 123 of file gd32f3x0_adc.c.

124 {
125 /* enable the vbat channel */
126 ADC_CTL1 |= ADC_CTL1_VBETEN;
127 }
ADC_CTL1_VBETEN
#define ADC_CTL1_VBETEN
Definition: gd32f3x0_adc.h:80
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
void adc_watchdog_disable ( void )

disable ADC analog watchdog

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 763 of file gd32f3x0_adc.c.

764 {
765 ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
766 }
ADC_CTL0_IWDEN
#define ADC_CTL0_IWDEN
Definition: gd32f3x0_adc.h:62
ADC_CTL0_RWDEN
#define ADC_CTL0_RWDEN
Definition: gd32f3x0_adc.h:63
ADC_CTL0_WDSC
#define ADC_CTL0_WDSC
Definition: gd32f3x0_adc.h:57
ADC_CTL0_WDCHSEL
#define ADC_CTL0_WDCHSEL
Definition: gd32f3x0_adc.h:52
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_watchdog_group_channel_enable ( uint8_t channel_group )

configure ADC analog watchdog group channel

Parameters
[in] channel_group the channel group use analog watchdog only one parameter can be selected
  • ADC_REGULAR_CHANNEL: regular channel group
  • ADC_INSERTED_CHANNEL: inserted channel group
  • ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
[out] none
Return values
none

Definition at line 737 of file gd32f3x0_adc.c.

738 {
739 ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
740
741 /* select the group */
742 switch(channel_group){
743 case ADC_REGULAR_CHANNEL:
744 ADC_CTL0 |= (uint32_t)ADC_CTL0_RWDEN;
745 break;
746 case ADC_INSERTED_CHANNEL:
747 ADC_CTL0 |= (uint32_t)ADC_CTL0_IWDEN;
748 break;
749 case ADC_REGULAR_INSERTED_CHANNEL:
750 ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
751 break;
752 default:
753 break;
754 }
755 }
ADC_CTL0_IWDEN
#define ADC_CTL0_IWDEN
Definition: gd32f3x0_adc.h:62
ADC_CTL0_RWDEN
#define ADC_CTL0_RWDEN
Definition: gd32f3x0_adc.h:63
ADC_CTL0_WDSC
#define ADC_CTL0_WDSC
Definition: gd32f3x0_adc.h:57
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f3x0_adc.h:217
ADC_REGULAR_INSERTED_CHANNEL
#define ADC_REGULAR_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:219
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:218
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_watchdog_single_channel_enable ( uint8_t channel )

configure ADC analog watchdog single channel

Parameters
[in] channel the selected ADC channel only one among these parameters can be selected
  • ADC_CHANNEL_x(x=0..18): ADC Channelx
[out] none
Return values
none

Definition at line 719 of file gd32f3x0_adc.c.

720 {
721 ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
722
723 ADC_CTL0 |= (uint32_t)channel;
724 ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
725 }
ADC_CTL0_IWDEN
#define ADC_CTL0_IWDEN
Definition: gd32f3x0_adc.h:62
ADC_CTL0_RWDEN
#define ADC_CTL0_RWDEN
Definition: gd32f3x0_adc.h:63
ADC_CTL0_WDSC
#define ADC_CTL0_WDSC
Definition: gd32f3x0_adc.h:57
ADC_CTL0_WDCHSEL
#define ADC_CTL0_WDCHSEL
Definition: gd32f3x0_adc.h:52
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
void adc_watchdog_threshold_config | ( | uint16_t | low_threshold,
 |  | uint16_t | high_threshold
 | ) |  |

configure ADC analog watchdog threshold

Parameters
[in] | low_threshold | analog watchdog low threshold,0..4095
[in] | high_threshold | analog watchdog high threshold,0..4095
[out] | none
Return values
none

Definition at line 775 of file gd32f3x0_adc.c.

776 {
777 ADC_WDLT = (uint32_t)WDLT_WDLT(low_threshold);
778 ADC_WDHT = (uint32_t)WDHT_WDHT(high_threshold);
779 }
ADC_WDLT
#define ADC_WDLT
Definition: gd32f3x0_adc.h:31
WDHT_WDHT
#define WDHT_WDHT(regval)
Definition: gd32f3x0_adc.h:171
WDLT_WDLT
#define WDLT_WDLT(regval)
Definition: gd32f3x0_adc.h:174
ADC_WDHT
#define ADC_WDHT
Definition: gd32f3x0_adc.h:30
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_cec.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_cec.c File Reference

CEC driver. More...

Go to the source code of this file.

Detailed Description

CEC driver.

Definition in file gd32f3x0_cec.c.

Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_cmp.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_cmp.c File Reference

CMP driver. More...

#include "gd32f3x0_cmp.h"

Go to the source code of this file.

Functions

void | cmp_deinit (void)
deinitialize comparator More...
void | cmp_mode_init (uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis)
initialize comparator mode More...
void | cmp_output_init (uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity)
initialize comparator output More...
void | cmp_enable (uint32_t cmp_periph)
enable comparator More...
void | cmp_disable (uint32_t cmp_periph)
disable comparator More...
void | cmp_switch_enable (void)
enable comparator switch More...
void | cmp_switch_disable (void)
disable comparator switch More...
uint32_t | cmp_output_level_get (uint32_t cmp_periph)
get output level More...
void | cmp_window_enable (void)
enable the window mode More...
void | cmp_window_disable (void)
disable the window mode More...
void | cmp_lock_enable (uint32_t cmp_periph)
lock the comparator More...
void | cmp_lock_disable (uint32_t cmp_periph)
unlock the comparator More...

Detailed Description

CMP driver.

Definition in file gd32f3x0_cmp.c.

Function Documentation

void cmp_deinit ( void )

deinitialize comparator

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_cmp.c.

21 {
22 CMP_CS = ((uint32_t)0x00000000U);
23 }
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
void cmp_disable ( uint32_t cmp_periph )

disable comparator

Parameters
[in] cmp_periph
  • CMP0: comparator 0
  • CMP1: comparator 1
[out] none
Return values
none

Definition at line 129 of file gd32f3x0_cmp.c.

130 {
131 if(CMP0 == cmp_periph){
132 CMP_CS &= ~CMP_CS_CMP0EN;
133 }else{
134 CMP_CS &= ~CMP_CS_CMP1EN;
135 }
136 }
CMP_CS_CMP0EN
#define CMP_CS_CMP0EN
Definition: gd32f3x0_cmp.h:24
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CMP_CS_CMP1EN
#define CMP_CS_CMP1EN
Definition: gd32f3x0_cmp.h:33
void cmp_enable ( uint32_t cmp_periph )

enable comparator

Parameters
[in] cmp_periph
  • CMP0: comparator 0
  • CMP1: comparator 1
[out] none
Return values
none

Definition at line 112 of file gd32f3x0_cmp.c.

113 {
114 if(CMP0 == cmp_periph){
115 CMP_CS |= CMP_CS_CMP0EN;
116 }else{
117 CMP_CS |= CMP_CS_CMP1EN;
118 }
119 }
CMP_CS_CMP0EN
#define CMP_CS_CMP0EN
Definition: gd32f3x0_cmp.h:24
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CMP_CS_CMP1EN
#define CMP_CS_CMP1EN
Definition: gd32f3x0_cmp.h:33
void cmp_lock_disable ( uint32_t cmp_periph )

unlock the comparator

Parameters
[in] cmp_periph
  • CMP0: comparator 0
  • CMP1: comparator 1
[out] none
Return values
none

Definition at line 232 of file gd32f3x0_cmp.c.

233 {
234 if(CMP0 == cmp_periph){
235 CMP_CS &= ~CMP_CS_CMP0LK;
236 }else{
237 CMP_CS &= ~CMP_CS_CMP1LK;
238 }
239 }
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
CMP_CS_CMP1LK
#define CMP_CS_CMP1LK
Definition: gd32f3x0_cmp.h:41
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CMP_CS_CMP0LK
#define CMP_CS_CMP0LK
Definition: gd32f3x0_cmp.h:32
void cmp_lock_enable ( uint32_t cmp_periph )

lock the comparator

Parameters
[in] cmp_periph
  • CMP0: comparator 0
  • CMP1: comparator 1
[out] none
Return values
none

Definition at line 215 of file gd32f3x0_cmp.c.

216 {
217 if(CMP0 == cmp_periph){
218 CMP_CS |= CMP_CS_CMP0LK;
219 }else{
220 CMP_CS |= CMP_CS_CMP1LK;
221 }
222 }
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
CMP_CS_CMP1LK
#define CMP_CS_CMP1LK
Definition: gd32f3x0_cmp.h:41
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CMP_CS_CMP0LK
#define CMP_CS_CMP0LK
Definition: gd32f3x0_cmp.h:32
void cmp_mode_init | ( | uint32_t | cmp_periph,
 |  | operating_mode_enum | operating_mode,
 |  | inverting_input_enum | inverting_input,
 |  | cmp_hysteresis_enum | output_hysteresis
 | ) |  |

initialize comparator mode

Parameters
[in] cmp_periph
  • CMP0: comparator 0
  • CMP1: comparator 1
[in] operating_mode
  • CMP_HIGHSPEED: high speed mode
  • CMP_MIDDLESPEED: medium speed mode
  • CMP_LOWSPEED: low speed mode
  • CMP_VERYLOWSPEED: very-low speed mode
[in] inverting_input
  • CMP_1_4VREFINT: VREFINT *1/4 input
  • CMP_1_2VREFINT: VREFINT *1/2 input
  • CMP_3_4VREFINT: VREFINT *3/4 input
  • CMP_VREFINT: VREFINT input
  • CMP_DAC: PA4 (DAC) input
  • CMP_PA5: PA5 input
  • CMP_PA_0_2: PA0 or PA2 input
[in] hysteresis
  • CMP_HYSTERESIS_NO: output no hysteresis
  • CMP_HYSTERESIS_LOW: output low hysteresis
  • CMP_HYSTERESIS_MIDDLE: output middle hysteresis
  • CMP_HYSTERESIS_HIGH: output high hysteresis
[out] none
Return values
none

Definition at line 51 of file gd32f3x0_cmp.c.

52 {
53 if(CMP0 == cmp_periph){
54 /* initialize comparator 0 mode */
55 CMP_CS |= CS_CMP0M(operating_mode) | CS_CMP0MSEL(inverting_input) | CS_CMP0HST(output_hysteresis);
56 }else{
57 /* initialize comparator 1 mode */
58 CMP_CS |= CS_CMP1M(operating_mode) | CS_CMP1MSEL(inverting_input) | CS_CMP1HST(output_hysteresis);
59 }
60 }
CS_CMP0MSEL
#define CS_CMP0MSEL(regval)
Definition: gd32f3x0_cmp.h:91
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CS_CMP1HST
#define CS_CMP1HST(regval)
Definition: gd32f3x0_cmp.h:147
CS_CMP0M
#define CS_CMP0M(regval)
Definition: gd32f3x0_cmp.h:84
CS_CMP1M
#define CS_CMP1M(regval)
Definition: gd32f3x0_cmp.h:119
CS_CMP0HST
#define CS_CMP0HST(regval)
Definition: gd32f3x0_cmp.h:112
CS_CMP1MSEL
#define CS_CMP1MSEL(regval)
Definition: gd32f3x0_cmp.h:126
void cmp_output_init | ( | uint32_t | cmp_periph,
 |  | cmp_output_enum | output_slection,
 |  | uint32_t | output_polarity
 | ) |  |

initialize comparator output

Parameters
[in] cmp_periph
  • CMP0: comparator 0
  • CMP1: comparator 1
[in] output_slection
  • CMP_OUTPUT_NONE: output no selection
  • CMP_OUTPUT_TIMER0BKIN: TIMER 0 break input
  • CMP_OUTPUT_TIMER0IC0: TIMER 0 channel0 input capture
  • CMP_OUTPUT_TIMER0OCPRECLR: TIMER 0 OCPRE_CLR input
  • CMP_OUTPUT_TIMER1IC3: TIMER 1 channel3 input capture
  • CMP_OUTPUT_TIMER1OCPRECLR: TIMER 1 OCPRE_CLR input
  • CMP_OUTPUT_TIMER2IC0: TIMER 2 channel0 input capture
  • CMP_OUTPUT_TIMER2OCPRECLR: TIMER 2 OCPRE_CLR input
[in] output_polarity
  • CMP_OUTPUT_POLARITY_INVERTED: output is inverted
  • CMP_OUTPUT_POLARITY_NOINVERTED: output is not inverted
[out] none
Return values
none

Definition at line 82 of file gd32f3x0_cmp.c.

83 {
84 /* initialize comparator 0 output */
85 if(CMP0 == cmp_periph){
86 CMP_CS |= CS_CMP0OSEL(output_slection);
87 /* output polarity */
88 if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
89 CMP_CS |= CMP_CS_CMP0PL;
90 }else{
91 CMP_CS &= ~CMP_CS_CMP0PL;
92 }
93 }else{
94 CMP_CS |= CS_CMP1OSEL(output_slection);
95
96 if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
97 CMP_CS |= CMP_CS_CMP1PL;
98 }else{
99 CMP_CS &= ~CMP_CS_CMP1PL;
100 }
101 }
102 }
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
CMP_CS_CMP0PL
#define CMP_CS_CMP0PL
Definition: gd32f3x0_cmp.h:29
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CS_CMP0OSEL
#define CS_CMP0OSEL(regval)
Definition: gd32f3x0_cmp.h:101
CMP_OUTPUT_POLARITY_INVERTED
#define CMP_OUTPUT_POLARITY_INVERTED
Definition: gd32f3x0_cmp.h:162
CMP_CS_CMP1PL
#define CMP_CS_CMP1PL
Definition: gd32f3x0_cmp.h:38
CS_CMP1OSEL
#define CS_CMP1OSEL(regval)
Definition: gd32f3x0_cmp.h:136
uint32_t cmp_output_level_get ( uint32_t cmp_periph )

get output level

Parameters
[in] cmp_periph
  • CMP0: comparator 0
  • CMP1: comparator 1
[out] none
Return values
the output level

Definition at line 168 of file gd32f3x0_cmp.c.

169 {
170 if(CMP0 == cmp_periph){
171 if(CMP_CS & CMP_CS_CMP0O){
172 return CMP_OUTPUTLEVEL_HIGH;
173 }else{
174 return CMP_OUTPUTLEVEL_LOW;
175 }
176 }else{
177 if(CMP_CS & CMP_CS_CMP1O){
178 return CMP_OUTPUTLEVEL_HIGH;
179 }else{
180 return CMP_OUTPUTLEVEL_LOW;
181 }
182 }
183 }
CMP_CS_CMP0O
#define CMP_CS_CMP0O
Definition: gd32f3x0_cmp.h:31
CMP_OUTPUTLEVEL_LOW
#define CMP_OUTPUTLEVEL_LOW
Definition: gd32f3x0_cmp.h:159
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
CMP_OUTPUTLEVEL_HIGH
#define CMP_OUTPUTLEVEL_HIGH
Definition: gd32f3x0_cmp.h:158
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CMP_CS_CMP1O
#define CMP_CS_CMP1O
Definition: gd32f3x0_cmp.h:40
void cmp_switch_disable ( void )

disable comparator switch

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 155 of file gd32f3x0_cmp.c.

156 {
157 CMP_CS &= ~CMP_CS_CMP0SW;
158 }
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CMP_CS_CMP0SW
#define CMP_CS_CMP0SW
Definition: gd32f3x0_cmp.h:25
void cmp_switch_enable ( void )

enable comparator switch

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 144 of file gd32f3x0_cmp.c.

145 {
146 CMP_CS |= CMP_CS_CMP0SW;
147 }
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CMP_CS_CMP0SW
#define CMP_CS_CMP0SW
Definition: gd32f3x0_cmp.h:25
void cmp_window_disable ( void )

disable the window mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 202 of file gd32f3x0_cmp.c.

203 {
204 CMP_CS &= ~CMP_CS_WNDEN;
205 }
CMP_CS_WNDEN
#define CMP_CS_WNDEN
Definition: gd32f3x0_cmp.h:36
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
void cmp_window_enable ( void )

enable the window mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 191 of file gd32f3x0_cmp.c.

192 {
193 CMP_CS |= CMP_CS_WNDEN;
194 }
CMP_CS_WNDEN
#define CMP_CS_WNDEN
Definition: gd32f3x0_cmp.h:36
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_crc.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_crc.c File Reference

CRC driver. More...

#include "gd32f3x0_crc.h"

Go to the source code of this file.

Functions

void | crc_deinit (void)
deinit CRC calculation unit More...
void | crc_reverse_output_data_enable (void)
enable the reverse operation of output data More...
void | crc_reverse_output_data_disable (void)
disable the reverse operation of output data More...
void | crc_data_register_reset (void)
reset data register to the value of initializaiton data register More...
uint32_t | crc_data_register_read (void)
read the data register More...
uint8_t | crc_free_data_register_read (void)
read the free data register More...
void | crc_free_data_register_write (uint8_t free_data)
write the free data register More...
void | crc_init_data_register_write (uint32_t init_data)
write the initializaiton data register More...
void | crc_input_data_reverse_config (uint32_t data_reverse)
configure the CRC input data function More...
void | crc_polynomial_size_set (uint32_t poly_size)
configure the CRC size of polynomial function More...
void | crc_polynomial_set (uint32_t poly)
configure the CRC polynomial value function More...
uint32_t | crc_single_data_calculate (uint32_t sdata)
CRC calculate a 32-bit data. More...
uint32_t | crc_block_data_calculate (uint32_t array[], uint32_t size)
CRC calculate a 32-bit data array. More...

Detailed Description

CRC driver.

Definition in file gd32f3x0_crc.c.

Function Documentation

uint32_t crc_block_data_calculate | ( | uint32_t | array[],
 |  | uint32_t | size
 | ) |  |

CRC calculate a 32-bit data array.

Parameters
[in] | array | pointer to an array of 32 bit data words
[in] | size | size of the array
[out] | none
Return values
32-bit CRC calculate value

Definition at line 174 of file gd32f3x0_crc.c.

175 {
176 uint32_t index;
177 for(index = 0U; index < size; index++){
178 CRC_DATA = array[index];
179 }
180 return (CRC_DATA);
181 }
CRC_DATA
#define CRC_DATA
Definition: gd32f3x0_crc.h:21
uint32_t crc_data_register_read ( void )

read the data register

Parameters
[in] | none
[out] | none
Return values
32-bit value of the data register

Definition at line 69 of file gd32f3x0_crc.c.

70 {
71 uint32_t data;
72 data = CRC_DATA;
73 return (data);
74 }
CRC_DATA
#define CRC_DATA
Definition: gd32f3x0_crc.h:21
void crc_data_register_reset ( void )

reset data register to the value of initializaiton data register

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 58 of file gd32f3x0_crc.c.

59 {
60 CRC_CTL |= (uint32_t)CRC_CTL_RST;
61 }
CRC_CTL_RST
#define CRC_CTL_RST
Definition: gd32f3x0_crc.h:35
CRC_CTL
#define CRC_CTL
Definition: gd32f3x0_crc.h:23
void crc_deinit ( void )

deinit CRC calculation unit

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_crc.c.

21 {
22 CRC_IDATA = (uint32_t)0xFFFFFFFFU;
23 CRC_DATA = (uint32_t)0xFFFFFFFFU;
24 CRC_FDATA = (uint32_t)0x00000000U;
25 CRC_POLY = (uint32_t)0x04C11DB7U;
26 CRC_CTL = CRC_CTL_RST;
27 }
CRC_IDATA
#define CRC_IDATA
Definition: gd32f3x0_crc.h:24
CRC_DATA
#define CRC_DATA
Definition: gd32f3x0_crc.h:21
CRC_FDATA
#define CRC_FDATA
Definition: gd32f3x0_crc.h:22
CRC_POLY
#define CRC_POLY
Definition: gd32f3x0_crc.h:25
CRC_CTL_RST
#define CRC_CTL_RST
Definition: gd32f3x0_crc.h:35
CRC_CTL
#define CRC_CTL
Definition: gd32f3x0_crc.h:23
uint8_t crc_free_data_register_read ( void )

read the free data register

Parameters
[in] | none
[out] | none
Return values
8-bit value of the free data register

Definition at line 82 of file gd32f3x0_crc.c.

83 {
84 uint8_t fdata;
85 fdata = (uint8_t)CRC_FDATA;
86 return (fdata);
87 }
CRC_FDATA
#define CRC_FDATA
Definition: gd32f3x0_crc.h:22
void crc_free_data_register_write ( uint8_t free_data )

write the free data register

Parameters
[in] | free_data | specify 8-bit data
[out] | none
Return values
none

Definition at line 95 of file gd32f3x0_crc.c.

96 {
97 CRC_FDATA = (uint32_t)free_data;
98 }
CRC_FDATA
#define CRC_FDATA
Definition: gd32f3x0_crc.h:22
void crc_init_data_register_write ( uint32_t init_data )

write the initializaiton data register

Parameters
[in] | init_data:specify | 32-bit data
[out] | none
Return values
none

Definition at line 106 of file gd32f3x0_crc.c.

107 {
108 CRC_IDATA = (uint32_t)init_data;
109 }
CRC_IDATA
#define CRC_IDATA
Definition: gd32f3x0_crc.h:24
void crc_input_data_reverse_config ( uint32_t data_reverse )

configure the CRC input data function

Parameters
[in] data_reverse specify input data reverse function
  • CRC_INPUT_DATA_NOT: input data is not reversed
  • CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits
  • CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits
  • CRC_INPUT_DATA_WORD: input data is reversed on 32 bits
[out] none
Return values
none

Definition at line 121 of file gd32f3x0_crc.c.

122 {
123 CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I);
124 CRC_CTL |= (uint32_t)data_reverse;
125 }
CRC_CTL_REV_I
#define CRC_CTL_REV_I
Definition: gd32f3x0_crc.h:37
CRC_CTL
#define CRC_CTL
Definition: gd32f3x0_crc.h:23
void crc_polynomial_set ( uint32_t poly )

configure the CRC polynomial value function

Parameters
[in] | poly | configurable polynomial value
[out] | none
Return values
none

Definition at line 149 of file gd32f3x0_crc.c.

150 {
151 CRC_POLY &= (uint32_t)(~CRC_POLY_POLY);
152 CRC_POLY = poly;
153 }
CRC_POLY
#define CRC_POLY
Definition: gd32f3x0_crc.h:25
CRC_POLY_POLY
#define CRC_POLY_POLY
Definition: gd32f3x0_crc.h:44
void crc_polynomial_size_set ( uint32_t poly_size )

configure the CRC size of polynomial function

Parameters
[in] poly_size size of polynomial
  • CRC_CTL_PS_32: 32-bit polynomial for CRC calculation
  • CRC_CTL_PS_16: 16-bit polynomial for CRC calculation
  • CRC_CTL_PS_8: 8-bit polynomial for CRC calculation
  • CRC_CTL_PS_7: 7-bit polynomial for CRC calculation
[out] none
Return values
none

Definition at line 137 of file gd32f3x0_crc.c.

138 {
139 CRC_CTL &= (uint32_t)(~(CRC_CTL_PS));
140 CRC_CTL |= (uint32_t)poly_size;
141 }
CRC_CTL
#define CRC_CTL
Definition: gd32f3x0_crc.h:23
CRC_CTL_PS
#define CRC_CTL_PS
Definition: gd32f3x0_crc.h:36
void crc_reverse_output_data_disable ( void )

disable the reverse operation of output data

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 47 of file gd32f3x0_crc.c.

48 {
49 CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
50 }
CRC_CTL_REV_O
#define CRC_CTL_REV_O
Definition: gd32f3x0_crc.h:38
CRC_CTL
#define CRC_CTL
Definition: gd32f3x0_crc.h:23
void crc_reverse_output_data_enable ( void )

enable the reverse operation of output data

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 35 of file gd32f3x0_crc.c.

36 {
37 CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
38 CRC_CTL |= (uint32_t)CRC_CTL_REV_O;
39 }
CRC_CTL_REV_O
#define CRC_CTL_REV_O
Definition: gd32f3x0_crc.h:38
CRC_CTL
#define CRC_CTL
Definition: gd32f3x0_crc.h:23
uint32_t crc_single_data_calculate ( uint32_t sdata )

CRC calculate a 32-bit data.

Parameters
[in] | sdata | specify 32-bit data
[out] | none
Return values
32-bit CRC calculate value

Definition at line 161 of file gd32f3x0_crc.c.

162 {
163 CRC_DATA = sdata;
164 return(CRC_DATA);
165 }
CRC_DATA
#define CRC_DATA
Definition: gd32f3x0_crc.h:21
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_ctc.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Macros | Functions
gd32f3x0_ctc.c File Reference

CTC driver. More...

#include "gd32f3x0_ctc.h"

Go to the source code of this file.

Macros

#define CTC_FLAG_MASK ((uint32_t)0x00000700U)

Functions

void | ctc_deinit (void)
reset CTC clock trim controller More...
void | ctc_irc48m_trim_value_config (uint8_t trim_value)
configure the IRC48M trim value More...
void | ctc_software_refsource_pulse_generate (void)
generate software reference source sync pulse More...
void | ctc_hardware_trim_mode_config (uint32_t hardmode)
configure hardware automatically trim mode More...
void | ctc_counter_enable (void)
enable CTC trim counter More...
void | ctc_counter_disable (void)
disable CTC trim counter More...
void | ctc_refsource_polarity_config (uint32_t polarity)
configure reference signal source polarity More...
void | ctc_refsource_signal_select (uint32_t refs)
select reference signal source More...
void | ctc_refsource_prescaler_config (uint32_t prescaler)
configure reference signal source prescaler More...
void | ctc_clock_limit_value_config (uint8_t limit_value)
configure clock trim base limit value More...
void | ctc_counter_reload_value_config (uint16_t reload_value)
configure CTC counter reload value More...
uint16_t | ctc_counter_capture_value_read (void)
read CTC counter capture value when reference sync pulse occurred More...
FlagStatus | ctc_counter_direction_read (void)
read CTC trim counter direction when reference sync pulse occurred More...
uint16_t | ctc_counter_reload_value_read (void)
read CTC counter reload value More...
uint8_t | ctc_irc48m_trim_value_read (void)
read the IRC48M trim value More...
void | ctc_interrupt_enable (uint32_t interrupt)
enable the CTC interrupt More...
void | ctc_interrupt_disable (uint32_t interrupt)
disable the CTC interrupt More...
FlagStatus | ctc_interrupt_flag_get (uint32_t interrupt)
get CTC interrupt flag More...
void | ctc_interrupt_flag_clear (uint32_t interrupt)
clear CTC interrupt flag More...
FlagStatus | ctc_flag_get (uint32_t flag)
get CTC flag More...
void | ctc_flag_clear (uint32_t flag)
clear CTC flag More...

Detailed Description

CTC driver.

Definition in file gd32f3x0_ctc.c.

Macro Definition Documentation

#define CTC_FLAG_MASK ((uint32_t)0x00000700U)

Definition at line 14 of file gd32f3x0_ctc.c.

Function Documentation

void ctc_clock_limit_value_config ( uint8_t limit_value )

configure clock trim base limit value

Parameters
[in] | limit_value | 8-bit clock trim base limit value
[out] | none
Return values
none

Definition at line 145 of file gd32f3x0_ctc.c.

146 {
147 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM);
148 CTC_CTL1 |= CTL1_CKLIM(limit_value);
149 }
CTC_CTL1_CKLIM
#define CTC_CTL1_CKLIM
Definition: gd32f3x0_ctc.h:39
CTC_CTL1
#define CTC_CTL1
Definition: gd32f3x0_ctc.h:22
CTL1_CKLIM
#define CTL1_CKLIM(regval)
Definition: gd32f3x0_ctc.h:63
uint16_t ctc_counter_capture_value_read ( void )

read CTC counter capture value when reference sync pulse occurred

Parameters
[in] | none
[out] | none
Return values
the 16-bit CTC counter capture value

Definition at line 169 of file gd32f3x0_ctc.c.

170 {
171 uint16_t capture_value = 0U;
172 capture_value = (uint16_t)GET_STAT_REFCAP(CTC_STAT);
173 return (capture_value);
174 }
GET_STAT_REFCAP
#define GET_STAT_REFCAP(regval)
Definition: gd32f3x0_ctc.h:64
CTC_STAT
#define CTC_STAT
Definition: gd32f3x0_ctc.h:23
FlagStatus ctc_counter_direction_read ( void )

read CTC trim counter direction when reference sync pulse occurred

Parameters
[in] | none
[out] | none
Return values
FlagStatus SET or RESET
  • SET: CTC trim counter direction is down-counting
  • RESET: CTC trim counter direction is up-counting

Definition at line 184 of file gd32f3x0_ctc.c.

185 {
186 FlagStatus ret_status = RESET;
187 if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){
188 ret_status = SET;
189 }
190 return ret_status;
191 }
CTC_STAT
#define CTC_STAT
Definition: gd32f3x0_ctc.h:23
CTC_STAT_REFDIR
#define CTC_STAT_REFDIR
Definition: gd32f3x0_ctc.h:52
void ctc_counter_disable ( void )

disable CTC trim counter

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 85 of file gd32f3x0_ctc.c.

86 {
87 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN);
88 }
CTC_CTL0_CNTEN
#define CTC_CTL0_CNTEN
Definition: gd32f3x0_ctc.h:32
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
void ctc_counter_enable ( void )

enable CTC trim counter

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 74 of file gd32f3x0_ctc.c.

75 {
76 CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN;
77 }
CTC_CTL0_CNTEN
#define CTC_CTL0_CNTEN
Definition: gd32f3x0_ctc.h:32
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
void ctc_counter_reload_value_config ( uint16_t reload_value )

configure CTC counter reload value

Parameters
[in] | reload_value | 16-bit CTC counter reload value
[out] | none
Return values
none

Definition at line 157 of file gd32f3x0_ctc.c.

158 {
159 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE);
160 CTC_CTL1 |= (uint32_t)reload_value;
161 }
CTC_CTL1_RLVALUE
#define CTC_CTL1_RLVALUE
Definition: gd32f3x0_ctc.h:38
CTC_CTL1
#define CTC_CTL1
Definition: gd32f3x0_ctc.h:22
uint16_t ctc_counter_reload_value_read ( void )

read CTC counter reload value

Parameters
[in] | none
[out] | none
Return values
the 16-bit CTC counter reload value

Definition at line 199 of file gd32f3x0_ctc.c.

200 {
201 uint16_t reload_value = 0U;
202 reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE);
203 return (reload_value);
204 }
CTC_CTL1_RLVALUE
#define CTC_CTL1_RLVALUE
Definition: gd32f3x0_ctc.h:38
CTC_CTL1
#define CTC_CTL1
Definition: gd32f3x0_ctc.h:22
void ctc_deinit ( void )

reset CTC clock trim controller

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 22 of file gd32f3x0_ctc.c.

23 {
24 /* reset CTC */
25 rcu_periph_reset_enable(RCU_CTCRST);
26 rcu_periph_reset_disable(RCU_CTCRST);
27 }
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
RCU_CTCRST
Definition: gd32f3x0_rcu.h:362
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
void ctc_flag_clear ( uint32_t flag )

clear CTC flag

Parameters
[in] flag the CTC flag
  • CTC_FLAG_CKOK: clock trim OK flag
  • CTC_FLAG_CKWARN: clock trim warning flag
  • CTC_FLAG_ERR: error flag
  • CTC_FLAG_EREF: expect reference flag
  • CTC_FLAG_CKERR: clock trim error bit
  • CTC_FLAG_REFMISS: reference sync pulse miss
  • CTC_FLAG_TRIMERR: trim value error bit
[out] none
Return values
none

Definition at line 338 of file gd32f3x0_ctc.c.

339 {
340 if(flag & CTC_FLAG_MASK){
341 CTC_INTC |= CTC_INTC_ERRIC;
342 }else{
343 CTC_INTC |= flag;
344 }
345 }
CTC_INTC
#define CTC_INTC
Definition: gd32f3x0_ctc.h:24
CTC_INTC_ERRIC
#define CTC_INTC_ERRIC
Definition: gd32f3x0_ctc.h:58
CTC_FLAG_MASK
#define CTC_FLAG_MASK
Definition: gd32f3x0_ctc.c:14
FlagStatus ctc_flag_get ( uint32_t flag )

get CTC flag

Parameters
[in] flag the CTC flag
  • CTC_FLAG_CKOK: clock trim OK flag
  • CTC_FLAG_CKWARN: clock trim warning flag
  • CTC_FLAG_ERR: error flag
  • CTC_FLAG_EREF: expect reference flag
  • CTC_FLAG_CKERR: clock trim error bit
  • CTC_FLAG_REFMISS: reference sync pulse miss
  • CTC_FLAG_TRIMERR: trim value error bit
[out] none
Return values
FlagStatus SET or RESET

Definition at line 315 of file gd32f3x0_ctc.c.

316 {
317 FlagStatus ret_status = RESET;
318
319 if(RESET != (CTC_STAT & flag)){
320 ret_status = SET;
321 }
322 return ret_status;
323 }
CTC_STAT
#define CTC_STAT
Definition: gd32f3x0_ctc.h:23
void ctc_hardware_trim_mode_config ( uint32_t hardmode )

configure hardware automatically trim mode

Parameters
[in] hardmode
  • CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable
  • CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable
[out] none
Return values
none

Definition at line 62 of file gd32f3x0_ctc.c.

63 {
64 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM);
65 CTC_CTL0 |= (uint32_t)hardmode;
66 }
CTC_CTL0_AUTOTRIM
#define CTC_CTL0_AUTOTRIM
Definition: gd32f3x0_ctc.h:33
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
void ctc_interrupt_disable ( uint32_t interrupt )

disable the CTC interrupt

Parameters
[in] interrupt CTC interrupt enable source
  • CTC_INT_CKOK: clock trim OK interrupt enable
  • CTC_INT_CKWARN: clock trim warning interrupt enable
  • CTC_INT_ERR: error interrupt enable
  • CTC_INT_EREF: expect reference interrupt enable
[out] none
Return values
none

Definition at line 244 of file gd32f3x0_ctc.c.

245 {
246 CTC_CTL0 &= (uint32_t)(~interrupt);
247 }
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
void ctc_interrupt_enable ( uint32_t interrupt )

enable the CTC interrupt

Parameters
[in] interrupt CTC interrupt enable
  • CTC_INT_CKOK: clock trim OK interrupt enable
  • CTC_INT_CKWARN: clock trim warning interrupt enable
  • CTC_INT_ERR: error interrupt enable
  • CTC_INT_EREF: expect reference interrupt enable
[out] none
Return values
none

Definition at line 229 of file gd32f3x0_ctc.c.

230 {
231 CTC_CTL0 |= (uint32_t)interrupt;
232 }
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
void ctc_interrupt_flag_clear ( uint32_t interrupt )

clear CTC interrupt flag

Parameters
[in] interrupt the CTC interrupt flag
  • CTC_INT_FLAG_CKOK: clock trim OK interrupt
  • CTC_INT_FLAG_CKWARN: clock trim warning interrupt
  • CTC_INT_FLAG_ERR: error interrupt
  • CTC_INT_FLAG_EREF: expect reference interrupt
  • CTC_INT_FLAG_CKERR: clock trim error bit interrupt
  • CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt
  • CTC_INT_FLAG_TRIMERR: trim value error interrupt
[out] none
Return values
none

Definition at line 293 of file gd32f3x0_ctc.c.

294 {
295 if(interrupt & CTC_FLAG_MASK){
296 CTC_INTC |= CTC_INTC_ERRIC;
297 }else{
298 CTC_INTC |= interrupt;
299 }
300 }
CTC_INTC
#define CTC_INTC
Definition: gd32f3x0_ctc.h:24
CTC_INTC_ERRIC
#define CTC_INTC_ERRIC
Definition: gd32f3x0_ctc.h:58
CTC_FLAG_MASK
#define CTC_FLAG_MASK
Definition: gd32f3x0_ctc.c:14
FlagStatus ctc_interrupt_flag_get ( uint32_t interrupt )

get CTC interrupt flag

Parameters
[in] interrupt the CTC interrupt flag
  • CTC_INT_FLAG_CKOK: clock trim OK interrupt
  • CTC_INT_FLAG_CKWARN: clock trim warning interrupt
  • CTC_INT_FLAG_ERR: error interrupt
  • CTC_INT_FLAG_EREF: expect reference interrupt
  • CTC_INT_FLAG_CKERR: clock trim error bit interrupt
  • CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt
  • CTC_INT_FLAG_TRIMERR: trim value error interrupt
[out] none
Return values
FlagStatus SET or RESET

Definition at line 262 of file gd32f3x0_ctc.c.

263 {
264 uint32_t ctc_int = 0U, intenable = 0U;
265 FlagStatus ret_status = RESET;
266
267 if(interrupt & CTC_FLAG_MASK){
268 intenable = CTC_CTL0 & CTC_INT_ERR;
269 }else{
270 intenable = CTC_CTL0 & interrupt;
271 }
272 ctc_int = CTC_STAT & interrupt;
273
274 if(ctc_int && intenable){
275 ret_status = SET;
276 }
277 return ret_status;
278 }
CTC_STAT
#define CTC_STAT
Definition: gd32f3x0_ctc.h:23
CTC_FLAG_MASK
#define CTC_FLAG_MASK
Definition: gd32f3x0_ctc.c:14
CTC_INT_ERR
#define CTC_INT_ERR
Definition: gd32f3x0_ctc.h:95
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
void ctc_irc48m_trim_value_config ( uint8_t trim_value )

configure the IRC48M trim value

Parameters
[in] | trim_value | 8-bit IRC48M trim value
[out] | none
Return values
none

Definition at line 35 of file gd32f3x0_ctc.c.

36 {
37 /* clear TRIMVALUE bits */
38 CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE);
39 /* set TRIMVALUE bits */
40 CTC_CTL0 |= CTL0_TRIMVALUE(trim_value);
41 }
CTC_CTL0_TRIMVALUE
#define CTC_CTL0_TRIMVALUE
Definition: gd32f3x0_ctc.h:35
CTL0_TRIMVALUE
#define CTL0_TRIMVALUE(regval)
Definition: gd32f3x0_ctc.h:62
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
uint8_t ctc_irc48m_trim_value_read ( void )

read the IRC48M trim value

Parameters
[in] | none
[out] | none
Return values
the 8-bit IRC48M trim value

Definition at line 212 of file gd32f3x0_ctc.c.

213 {
214 uint8_t trim_value = 0U;
215 trim_value = (uint8_t)GET_CTL0_TRIMVALUE(CTC_CTL0);
216 return (trim_value);
217 }
GET_CTL0_TRIMVALUE
#define GET_CTL0_TRIMVALUE(regval)
Definition: gd32f3x0_ctc.h:65
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
void ctc_refsource_polarity_config ( uint32_t polarity )

configure reference signal source polarity

Parameters
[in] polarity
  • CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge
  • CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge
[out] none
Return values
none

Definition at line 98 of file gd32f3x0_ctc.c.

99 {
100 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL);
101 CTC_CTL1 |= (uint32_t)polarity;
102 }
CTC_CTL1
#define CTC_CTL1
Definition: gd32f3x0_ctc.h:22
CTC_CTL1_REFPOL
#define CTC_CTL1_REFPOL
Definition: gd32f3x0_ctc.h:42
void ctc_refsource_prescaler_config ( uint32_t prescaler )

configure reference signal source prescaler

Parameters
[in] prescaler
  • CTC_REFSOURCE_PSC_OFF: reference signal not divided
  • CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2
  • CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4
  • CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8
  • CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16
  • CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32
  • CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64
  • CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128
[out] none
Return values
none

Definition at line 133 of file gd32f3x0_ctc.c.

134 {
135 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC);
136 CTC_CTL1 |= (uint32_t)prescaler;
137 }
CTC_CTL1
#define CTC_CTL1
Definition: gd32f3x0_ctc.h:22
CTC_CTL1_REFPSC
#define CTC_CTL1_REFPSC
Definition: gd32f3x0_ctc.h:40
void ctc_refsource_signal_select ( uint32_t refs )

select reference signal source

Parameters
[in] refs
  • CTC_REFSOURCE_GPIO: GPIO is selected
  • CTC_REFSOURCE_LXTAL: LXTAL is clock selected
  • CTC_REFSOURCE_USBSOF: USBSOF is selected
[out] none
Return values
none

Definition at line 113 of file gd32f3x0_ctc.c.

114 {
115 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL);
116 CTC_CTL1 |= (uint32_t)refs;
117 }
CTC_CTL1_REFSEL
#define CTC_CTL1_REFSEL
Definition: gd32f3x0_ctc.h:41
CTC_CTL1
#define CTC_CTL1
Definition: gd32f3x0_ctc.h:22
void ctc_software_refsource_pulse_generate ( void )

generate software reference source sync pulse

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 49 of file gd32f3x0_ctc.c.

50 {
51 CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL;
52 }
CTC_CTL0_SWREFPUL
#define CTC_CTL0_SWREFPUL
Definition: gd32f3x0_ctc.h:34
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_dac.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_dac.c File Reference

DAC driver. More...

Go to the source code of this file.

Detailed Description

DAC driver.

Definition in file gd32f3x0_dac.c.

Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_dbg.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Macros | Functions
gd32f3x0_dbg.c File Reference

DBG driver. More...

#include "gd32f3x0_dbg.h"

Go to the source code of this file.

Macros

#define DBG_RESET_VAL 0x00000000U

Functions

void | dbg_deinit (void)
deinitialize the DBG More...
uint32_t | dbg_id_get (void)
read DBG_ID code register More...
void | dbg_low_power_enable (uint32_t dbg_low_power)
enable low power behavior when the mcu is in debug mode More...
void | dbg_low_power_disable (uint32_t dbg_low_power)
disable low power behavior when the mcu is in debug mode More...
void | dbg_periph_enable (dbg_periph_enum dbg_periph)
enable peripheral behavior when the mcu is in debug mode More...
void | dbg_periph_disable (dbg_periph_enum dbg_periph)
disable peripheral behavior when the mcu is in debug mode More...

Detailed Description

DBG driver.

Definition in file gd32f3x0_dbg.c.

Macro Definition Documentation

#define DBG_RESET_VAL 0x00000000U

Definition at line 14 of file gd32f3x0_dbg.c.

Function Documentation

void dbg_deinit ( void )

deinitialize the DBG

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 22 of file gd32f3x0_dbg.c.

23 {
24 DBG_CTL0 = DBG_RESET_VAL;
25 DBG_CTL1 = DBG_RESET_VAL;
26 }
DBG_RESET_VAL
#define DBG_RESET_VAL
Definition: gd32f3x0_dbg.c:14
DBG_CTL1
#define DBG_CTL1
Definition: gd32f3x0_dbg.h:23
DBG_CTL0
#define DBG_CTL0
Definition: gd32f3x0_dbg.h:22
uint32_t dbg_id_get ( void )

read DBG_ID code register

Parameters
[in] | none
[out] | none
Return values
DBG_ID code

Definition at line 34 of file gd32f3x0_dbg.c.

35 {
36 return DBG_ID;
37 }
DBG_ID
#define DBG_ID
Definition: gd32f3x0_dbg.h:21
void dbg_low_power_disable ( uint32_t dbg_low_power )

disable low power behavior when the mcu is in debug mode

Parameters
[in] dbg_low_power this parameter can be any combination of the following values:
  • DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
  • DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
  • DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
[out] none
Return values
none

Definition at line 64 of file gd32f3x0_dbg.c.

65 {
66 DBG_CTL0 &= ~dbg_low_power;
67 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f3x0_dbg.h:22
void dbg_low_power_enable ( uint32_t dbg_low_power )

enable low power behavior when the mcu is in debug mode

Parameters
[in] dbg_low_power this parameter can be any combination of the following values:
  • DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
  • DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
  • DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
[out] none
Return values
none

Definition at line 49 of file gd32f3x0_dbg.c.

50 {
51 DBG_CTL0 |= dbg_low_power;
52 }
DBG_CTL0
#define DBG_CTL0
Definition: gd32f3x0_dbg.h:22
void dbg_periph_disable ( dbg_periph_enum dbg_periph )

disable peripheral behavior when the mcu is in debug mode

Parameters
[in] dbg_periph DBG peripheral only one parameter can be selected which is shown as below:
  • DBG_SLEEP_HOLD: keep debugger connection during sleep mode
  • DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode
  • DBG_STANDBY_HOLD: keep debugger connection during standby mode
  • DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
  • DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
  • DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted
  • DBG_TIMER1_HOLD: TIMER1 counter kept when core is halted
  • DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted
  • DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
  • DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
  • DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted
  • DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted
  • DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted
  • DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted
  • DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted
  • DBG_I2C2_HOLD: hold I2C2 SMBUS when core is halted
  • DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
[out] none
Return values
none

Definition at line 122 of file gd32f3x0_dbg.c.

123 {
124 DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
125 }
DBG_REG_VAL
#define DBG_REG_VAL(periph)
Definition: gd32f3x0_dbg.h:59
DBG_BIT_POS
#define DBG_BIT_POS(val)
Definition: gd32f3x0_dbg.h:60
void dbg_periph_enable ( dbg_periph_enum dbg_periph )

enable peripheral behavior when the mcu is in debug mode

Parameters
[in] dbg_periph DBG peripheral only one parameter can be selected which is shown as below:
  • DBG_SLEEP_HOLD: keep debugger connection during sleep mode
  • DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode
  • DBG_STANDBY_HOLD: keep debugger connection during standby mode
  • DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
  • DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
  • DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted
  • DBG_TIMER1_HOLD: TIMER1 counter kept when core is halted
  • DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted
  • DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
  • DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
  • DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted
  • DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted
  • DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted
  • DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted
  • DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted
  • DBG_I2C2_HOLD: hold I2C2 SMBUS when core is halted
  • DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
[out] none
Return values
none

Definition at line 93 of file gd32f3x0_dbg.c.

94 {
95 DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
96 }
DBG_REG_VAL
#define DBG_REG_VAL(periph)
Definition: gd32f3x0_dbg.h:59
DBG_BIT_POS
#define DBG_BIT_POS(val)
Definition: gd32f3x0_dbg.h:60
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_dma.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_dma.c File Reference

DMA driver. More...

#include "gd32f3x0_dma.h"

Go to the source code of this file.

Functions

void | dma_deinit (dma_channel_enum channelx)
deinitialize DMA a channel registers More...
void | dma_init (dma_channel_enum channelx, dma_parameter_struct init_struct)
initialize DMA channel More...
void | dma_circulation_enable (dma_channel_enum channelx)
enable DMA circulation mode More...
void | dma_circulation_disable (dma_channel_enum channelx)
disable DMA circulation mode More...
void | dma_memory_to_memory_enable (dma_channel_enum channelx)
enable memory to memory mode More...
void | dma_memory_to_memory_disable (dma_channel_enum channelx)
disable memory to memory mode More...
void | dma_channel_enable (dma_channel_enum channelx)
enable DMA channel More...
void | dma_channel_disable (dma_channel_enum channelx)
disable DMA channel More...
void | dma_periph_address_config (dma_channel_enum channelx, uint32_t address)
set DMA peripheral base address More...
void | dma_memory_address_config (dma_channel_enum channelx, uint32_t address)
set DMA memory base address More...
void | dma_transfer_number_config (dma_channel_enum channelx, uint32_t number)
set the number of remaining data to be transferred by the DMA More...
uint32_t | dma_transfer_number_get (dma_channel_enum channelx)
get the number of remaining data to be transferred by the DMA More...
void | dma_priority_config (dma_channel_enum channelx, uint32_t priority)
configure priority level of DMA channel More...
void | dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth)
configure transfer data size of memory More...
void | dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth)
configure transfer data size of peripheral More...
void | dma_memory_increase_enable (dma_channel_enum channelx)
enable next address increasement algorithm of memory More...
void | dma_memory_increase_disable (dma_channel_enum channelx)
disable next address increasement algorithm of memory More...
void | dma_periph_increase_enable (dma_channel_enum channelx)
enable next address increasement algorithm of peripheral More...
void | dma_periph_increase_disable (dma_channel_enum channelx)
disable next address increasement algorithm of peripheral More...
void | dma_transfer_direction_config (dma_channel_enum channelx, uint32_t direction)
configure the direction of data transfer on the channel More...
FlagStatus | dma_flag_get (dma_channel_enum channelx, uint32_t flag)
check DMA flag is set or not More...
void | dma_flag_clear (uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag More...
FlagStatus | dma_interrupt_flag_get (dma_channel_enum channelx, uint32_t flag)
check DMA flag and interrupt enable bit is set or not More...
void | dma_interrupt_flag_clear (dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag More...
void | dma_interrupt_enable (dma_channel_enum channelx, uint32_t source)
enable DMA interrupt More...
void | dma_interrupt_disable (dma_channel_enum channelx, uint32_t source)
disable DMA interrupt More...

Detailed Description

DMA driver.

Definition in file gd32f3x0_dma.c.

Function Documentation

void dma_channel_disable ( dma_channel_enum channelx )

disable DMA channel

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 160 of file gd32f3x0_dma.c.

161 {
162 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
163 }
DMA_CHXCTL_CHEN
#define DMA_CHXCTL_CHEN
Definition: gd32f3x0_dma.h:66
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_channel_enable ( dma_channel_enum channelx )

enable DMA channel

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 148 of file gd32f3x0_dma.c.

149 {
150 DMA_CHCTL(channelx) |= DMA_CHXCTL_CHEN;
151 }
DMA_CHXCTL_CHEN
#define DMA_CHXCTL_CHEN
Definition: gd32f3x0_dma.h:66
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_circulation_disable ( dma_channel_enum channelx )

disable DMA circulation mode

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 112 of file gd32f3x0_dma.c.

113 {
114 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CMEN;
115 }
DMA_CHXCTL_CMEN
#define DMA_CHXCTL_CMEN
Definition: gd32f3x0_dma.h:71
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_circulation_enable ( dma_channel_enum channelx )

enable DMA circulation mode

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 100 of file gd32f3x0_dma.c.

101 {
102 DMA_CHCTL(channelx) |= DMA_CHXCTL_CMEN;
103 }
DMA_CHXCTL_CMEN
#define DMA_CHXCTL_CMEN
Definition: gd32f3x0_dma.h:71
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_deinit ( dma_channel_enum channelx )

deinitialize DMA a channel registers

Parameters
[in] channelx specify which DMA channel is deinitialized
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 21 of file gd32f3x0_dma.c.

22 {
23 /* disable DMA a channel */
24 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
25 /* reset DMA channel registers */
26 DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE;
27 DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE;
28 DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE;
29 DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE;
30 DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
31 }
DMA_CHCNT_RESET_VALUE
#define DMA_CHCNT_RESET_VALUE
Definition: gd32f3x0_dma.h:117
DMA_CHINTF_RESET_VALUE
#define DMA_CHINTF_RESET_VALUE
Definition: gd32f3x0_dma.h:120
DMA_CHCTL_RESET_VALUE
#define DMA_CHCTL_RESET_VALUE
Definition: gd32f3x0_dma.h:116
DMA_CHPADDR_RESET_VALUE
#define DMA_CHPADDR_RESET_VALUE
Definition: gd32f3x0_dma.h:118
DMA_INTC
#define DMA_INTC
Definition: gd32f3x0_dma.h:22
DMA_CHMADDR_RESET_VALUE
#define DMA_CHMADDR_RESET_VALUE
Definition: gd32f3x0_dma.h:119
DMA_CHCNT
#define DMA_CHCNT(channel)
Definition: gd32f3x0_dma.h:133
DMA_CHMADDR
#define DMA_CHMADDR(channel)
Definition: gd32f3x0_dma.h:135
DMA_CHXCTL_CHEN
#define DMA_CHXCTL_CHEN
Definition: gd32f3x0_dma.h:66
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f3x0_dma.h:123
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
DMA_CHPADDR
#define DMA_CHPADDR(channel)
Definition: gd32f3x0_dma.h:134
void dma_flag_clear | ( | uint32_t | dma_periph,
 |  | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

clear DMA a channel flag

Parameters
[in] channelx specify which DMA channel to clear flag
  • DMA_CHx(x=0..6)
[in] flag specify get which flag
  • DMA_FLAG_G: global interrupt flag of channel
  • DMA_FLAG_FTF: full transfer finish flag of channel
  • DMA_FLAG_HTF: half transfer finish flag of channel
  • DMA_FLAG_ERR: error flag of channel
[out] none
Return values
none

Definition at line 391 of file gd32f3x0_dma.c.

392 {
393 DMA_INTC |= DMA_FLAG_ADD(flag, channelx);
394 }
DMA_INTC
#define DMA_INTC
Definition: gd32f3x0_dma.h:22
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f3x0_dma.h:123
FlagStatus dma_flag_get | ( | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

check DMA flag is set or not

Parameters
[in] channelx specify which DMA channel to get flag
  • DMA_CHx(x=0..6)
[in] flag specify get which flag only one parameter can be selected which is shown as below:
  • DMA_FLAG_G: global interrupt flag of channel
  • DMA_FLAG_FTF: full transfer finish flag of channel
  • DMA_FLAG_HTF: half transfer finish flag of channel
  • DMA_FLAG_ERR: error flag of channel
[out] none
Return values
FlagStatus SET or RESET

Definition at line 366 of file gd32f3x0_dma.c.

367 {
368 FlagStatus reval;
369
370 if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))){
371 reval = SET;
372 }else{
373 reval = RESET;
374 }
375
376 return reval;
377 }
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f3x0_dma.h:123
DMA_INTF
#define DMA_INTF
Definition: gd32f3x0_dma.h:21
void dma_init | ( | dma_channel_enum | channelx,
 |  | dma_parameter_struct | init_struct
 | ) |  |

initialize DMA channel

Parameters
[in] channelx specify which DMA channel is initialized
  • DMA_CHx(x=0..6)
[in] | init_struct | the data needed to initialize DMA channel periph_addr: peripheral base address periph_width: DMA_PERIPHERAL_WIDTH_8BIT,DMA_PERIPHERAL_WIDTH_16BIT,DMA_PERIPHERAL_WIDTH_32BIT periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE memory_addr: memory base address memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE direction: DMA_PERIPHERAL_TO_MEMORY,DMA_MEMORY_TO_PERIPHERAL number: the number of remaining data to be transferred by the DMA priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH
[out] | none
Return values
none

Definition at line 50 of file gd32f3x0_dma.c.

51 {
52 uint32_t ctl;
53
54 dma_channel_disable(channelx);
55
56 /* configure peripheral base address */
57 DMA_CHPADDR(channelx) = init_struct.periph_addr;
58
59 /* configure memory base address */
60 DMA_CHMADDR(channelx) = init_struct.memory_addr;
61
62 /* configure the number of remaining data to be transferred */
63 DMA_CHCNT(channelx) = init_struct.number;
64
65 /* configure peripheral transfer width,memory transfer width,channel priotity */
66 ctl = DMA_CHCTL(channelx);
67 ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
68 ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority);
69 DMA_CHCTL(channelx) = ctl;
70
71 /* configure peripheral increasing mode */
72 if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){
73 DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
74 }else{
75 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
76 }
77
78 /* configure memory increasing mode */
79 if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){
80 DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
81 }else{
82 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
83 }
84
85 /* configure the direction of data transfer */
86 if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){
87 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
88 }else{
89 DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
90 }
91 }
DMA_CHXCTL_DIR
#define DMA_CHXCTL_DIR
Definition: gd32f3x0_dma.h:70
dma_channel_disable
void dma_channel_disable(dma_channel_enum channelx)
disable DMA channel
Definition: gd32f3x0_dma.c:160
dma_parameter_struct::priority
uint32_t priority
Definition: gd32f3x0_dma.h:112
dma_parameter_struct::memory_width
uint32_t memory_width
Definition: gd32f3x0_dma.h:108
dma_parameter_struct::periph_inc
uint8_t periph_inc
Definition: gd32f3x0_dma.h:106
DMA_CHXCTL_PWIDTH
#define DMA_CHXCTL_PWIDTH
Definition: gd32f3x0_dma.h:74
DMA_CHXCTL_MNAGA
#define DMA_CHXCTL_MNAGA
Definition: gd32f3x0_dma.h:73
DMA_PERIPH_INCREASE_ENABLE
#define DMA_PERIPH_INCREASE_ENABLE
Definition: gd32f3x0_dma.h:162
dma_parameter_struct::number
uint32_t number
Definition: gd32f3x0_dma.h:111
DMA_CHXCTL_PRIO
#define DMA_CHXCTL_PRIO
Definition: gd32f3x0_dma.h:76
DMA_MEMORY_INCREASE_ENABLE
#define DMA_MEMORY_INCREASE_ENABLE
Definition: gd32f3x0_dma.h:166
dma_parameter_struct::periph_width
uint32_t periph_width
Definition: gd32f3x0_dma.h:105
dma_parameter_struct::memory_inc
uint8_t memory_inc
Definition: gd32f3x0_dma.h:109
dma_parameter_struct::direction
uint8_t direction
Definition: gd32f3x0_dma.h:110
DMA_CHXCTL_PNAGA
#define DMA_CHXCTL_PNAGA
Definition: gd32f3x0_dma.h:72
DMA_CHCNT
#define DMA_CHCNT(channel)
Definition: gd32f3x0_dma.h:133
DMA_CHMADDR
#define DMA_CHMADDR(channel)
Definition: gd32f3x0_dma.h:135
DMA_PERIPHERAL_TO_MEMORY
#define DMA_PERIPHERAL_TO_MEMORY
Definition: gd32f3x0_dma.h:157
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
dma_parameter_struct::periph_addr
uint32_t periph_addr
Definition: gd32f3x0_dma.h:104
DMA_CHPADDR
#define DMA_CHPADDR(channel)
Definition: gd32f3x0_dma.h:134
DMA_CHXCTL_MWIDTH
#define DMA_CHXCTL_MWIDTH
Definition: gd32f3x0_dma.h:75
dma_parameter_struct::memory_addr
uint32_t memory_addr
Definition: gd32f3x0_dma.h:107
void dma_interrupt_disable | ( | dma_channel_enum | channelx,
 |  | uint32_t | source
 | ) |  |

disable DMA interrupt

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[in] source specify which interrupt to disbale
  • DMA_INT_ERR: channel error interrupt
  • DMA_INT_HTF: channel transfer half finish interrupt
  • DMA_INT_FTF: channel transfer finish interrupt
[out] none
Return values
none

Definition at line 480 of file gd32f3x0_dma.c.

481 {
482 DMA_CHCTL(channelx) &= ~source;
483 }
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_interrupt_enable | ( | dma_channel_enum | channelx,
 |  | uint32_t | source
 | ) |  |

enable DMA interrupt

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[in] source specify which interrupt to enbale
  • DMA_INT_ERR: channel error interrupt
  • DMA_INT_HTF: channel transfer half finish interrupt
  • DMA_INT_FTF: channel transfer finish interrupt
[out] none
Return values
none

Definition at line 464 of file gd32f3x0_dma.c.

465 {
466 DMA_CHCTL(channelx) |= source;
467 }
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_interrupt_flag_clear | ( | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

clear DMA a channel flag

Parameters
[in] channelx specify which DMA channel to clear flag
  • DMA_CHx(x=0..6)
[in] flag specify get which flag
  • DMA_INT_FLAG_G: global interrupt flag of channel
  • DMA_INT_FLAG_FTF: transfer finish flag of channel
  • DMA_INT_FLAG_HTF: half transfer finish flag of channel
  • DMA_INT_FLAG_ERR: error flag of channel
[out] none
Return values
none

Definition at line 448 of file gd32f3x0_dma.c.

449 {
450 DMA_INTC |= DMA_FLAG_ADD(flag,channelx);
451 }
DMA_INTC
#define DMA_INTC
Definition: gd32f3x0_dma.h:22
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f3x0_dma.h:123
FlagStatus dma_interrupt_flag_get | ( | dma_channel_enum | channelx,
 |  | uint32_t | flag
 | ) |  |

check DMA flag and interrupt enable bit is set or not

Parameters
[in] channelx specify which DMA channel to get flag
  • DMA_CHx(x=0..6)
[in] flag specify get which flag only one parameter can be selected which is shown as below:
  • DMA_INT_FLAG_FTF: transfer finish flag of channel
  • DMA_INT_FLAG_HTF: half transfer finish flag of channel
  • DMA_INT_FLAG_ERR: error flag of channel
[out] none
Return values
FlagStatus SET or RESET

Definition at line 408 of file gd32f3x0_dma.c.

409 {
410 uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
411
412 switch(flag){
413 case DMA_INT_FLAG_FTF:
414 interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
415 interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE;
416 break;
417 case DMA_INT_FLAG_HTF:
418 interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
419 interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE;
420 break;
421 case DMA_INT_FLAG_ERR:
422 interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
423 interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_ERRIE;
424 break;
425 default:
426 break;
427 }
428
429 if(interrupt_flag && interrupt_enable){
430 return SET;
431 }else{
432 return RESET;
433 }
434 }
DMA_INT_FLAG_FTF
#define DMA_INT_FLAG_FTF
Definition: gd32f3x0_dma.h:140
DMA_CHXCTL_ERRIE
#define DMA_CHXCTL_ERRIE
Definition: gd32f3x0_dma.h:69
DMA_INT_FLAG_HTF
#define DMA_INT_FLAG_HTF
Definition: gd32f3x0_dma.h:141
DMA_CHXCTL_HTFIE
#define DMA_CHXCTL_HTFIE
Definition: gd32f3x0_dma.h:68
DMA_CHXCTL_FTFIE
#define DMA_CHXCTL_FTFIE
Definition: gd32f3x0_dma.h:67
DMA_INT_FLAG_ERR
#define DMA_INT_FLAG_ERR
Definition: gd32f3x0_dma.h:142
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f3x0_dma.h:123
DMA_INTF
#define DMA_INTF
Definition: gd32f3x0_dma.h:21
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_memory_address_config | ( | dma_channel_enum | channelx,
 |  | uint32_t | address
 | ) |  |

set DMA memory base address

Parameters
[in] channelx specify which DMA channel to set memory base address
  • DMA_CHx(x=0..6)
[in] | address | memory base address
[out] | none
Return values
none

Definition at line 186 of file gd32f3x0_dma.c.

187 {
188 DMA_CHMADDR(channelx) = address;
189 }
DMA_CHMADDR
#define DMA_CHMADDR(channel)
Definition: gd32f3x0_dma.h:135
void dma_memory_increase_disable ( dma_channel_enum channelx )

disable next address increasement algorithm of memory

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 305 of file gd32f3x0_dma.c.

306 {
307 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
308 }
DMA_CHXCTL_MNAGA
#define DMA_CHXCTL_MNAGA
Definition: gd32f3x0_dma.h:73
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_memory_increase_enable ( dma_channel_enum channelx )

enable next address increasement algorithm of memory

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 293 of file gd32f3x0_dma.c.

294 {
295 DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
296 }
DMA_CHXCTL_MNAGA
#define DMA_CHXCTL_MNAGA
Definition: gd32f3x0_dma.h:73
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_memory_to_memory_disable ( dma_channel_enum channelx )

disable memory to memory mode

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 136 of file gd32f3x0_dma.c.

137 {
138 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M;
139 }
DMA_CHXCTL_M2M
#define DMA_CHXCTL_M2M
Definition: gd32f3x0_dma.h:77
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_memory_to_memory_enable ( dma_channel_enum channelx )

enable memory to memory mode

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 124 of file gd32f3x0_dma.c.

125 {
126 DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M;
127 }
DMA_CHXCTL_M2M
#define DMA_CHXCTL_M2M
Definition: gd32f3x0_dma.h:77
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_memory_width_config | ( | dma_channel_enum | channelx,
 |  | uint32_t | mwidth
 | ) |  |

configure transfer data size of memory

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[in] mwidth transfer data size of memory
  • DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit
  • DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit
  • DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit
[out] none
Return values
none

Definition at line 251 of file gd32f3x0_dma.c.

252 {
253 uint32_t ctl;
254
255 /* acquire DMA_CHxCTL register */
256 ctl = DMA_CHCTL(channelx);
257 /* assign regiser */
258 ctl &= ~DMA_CHXCTL_MWIDTH;
259 ctl |= mwidth;
260 DMA_CHCTL(channelx) = ctl;
261 }
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
DMA_CHXCTL_MWIDTH
#define DMA_CHXCTL_MWIDTH
Definition: gd32f3x0_dma.h:75
void dma_periph_address_config | ( | dma_channel_enum | channelx,
 |  | uint32_t | address
 | ) |  |

set DMA peripheral base address

Parameters
[in] channelx specify which DMA channel to set peripheral base address
  • DMA_CHx(x=0..6)
[in] | address | peripheral base address
[out] | none
Return values
none

Definition at line 173 of file gd32f3x0_dma.c.

174 {
175 DMA_CHPADDR(channelx) = address;
176 }
DMA_CHPADDR
#define DMA_CHPADDR(channel)
Definition: gd32f3x0_dma.h:134
void dma_periph_increase_disable ( dma_channel_enum channelx )

disable next address increasement algorithm of peripheral

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 329 of file gd32f3x0_dma.c.

330 {
331 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
332 }
DMA_CHXCTL_PNAGA
#define DMA_CHXCTL_PNAGA
Definition: gd32f3x0_dma.h:72
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_periph_increase_enable ( dma_channel_enum channelx )

enable next address increasement algorithm of peripheral

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[out] none
Return values
none

Definition at line 317 of file gd32f3x0_dma.c.

318 {
319 DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
320 }
DMA_CHXCTL_PNAGA
#define DMA_CHXCTL_PNAGA
Definition: gd32f3x0_dma.h:72
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_periph_width_config | ( | dma_channel_enum | channelx,
 |  | uint32_t | pwidth
 | ) |  |

configure transfer data size of peripheral

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[in] pwidth transfer data size of peripheral
  • DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit
  • DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit
  • DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit
[out] none
Return values
none

Definition at line 274 of file gd32f3x0_dma.c.

275 {
276 uint32_t ctl;
277
278 /* acquire DMA_CHxCTL register */
279 ctl = DMA_CHCTL(channelx);
280 /* assign regiser */
281 ctl &= ~DMA_CHXCTL_PWIDTH;
282 ctl |= pwidth;
283 DMA_CHCTL(channelx) = ctl;
284 }
DMA_CHXCTL_PWIDTH
#define DMA_CHXCTL_PWIDTH
Definition: gd32f3x0_dma.h:74
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_priority_config | ( | dma_channel_enum | channelx,
 |  | uint32_t | priority
 | ) |  |

configure priority level of DMA channel

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[in] priority priority level of this channel
  • DMA_PRIORITY_LOW: low priority
  • DMA_PRIORITY_MEDIUM: medium priority
  • DMA_PRIORITY_HIGH: high priority
  • DMA_PRIORITY_ULTRA_HIGH: ultra high priority
[out] none
Return values
none

Definition at line 228 of file gd32f3x0_dma.c.

229 {
230 uint32_t ctl;
231
232 /* acquire DMA_CHxCTL register */
233 ctl = DMA_CHCTL(channelx);
234 /* assign regiser */
235 ctl &= ~DMA_CHXCTL_PRIO;
236 ctl |= priority;
237 DMA_CHCTL(channelx) = ctl;
238 }
DMA_CHXCTL_PRIO
#define DMA_CHXCTL_PRIO
Definition: gd32f3x0_dma.h:76
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_transfer_direction_config | ( | dma_channel_enum | channelx,
 |  | uint32_t | direction
 | ) |  |

configure the direction of data transfer on the channel

Parameters
[in] channelx specify which DMA channel
  • DMA_CHx(x=0..6)
[in] direction specify the direction of data transfer
  • DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
  • DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
[out] none
Return values
none

Definition at line 344 of file gd32f3x0_dma.c.

345 {
346 if(DMA_PERIPHERAL_TO_MEMORY == direction){
347 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
348 } else {
349 DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
350 }
351 }
DMA_CHXCTL_DIR
#define DMA_CHXCTL_DIR
Definition: gd32f3x0_dma.h:70
DMA_PERIPHERAL_TO_MEMORY
#define DMA_PERIPHERAL_TO_MEMORY
Definition: gd32f3x0_dma.h:157
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
void dma_transfer_number_config | ( | dma_channel_enum | channelx,
 |  | uint32_t | number
 | ) |  |

set the number of remaining data to be transferred by the DMA

Parameters
[in] channelx specify which DMA channel to set number
  • DMA_CHx(x=0..6)
[in] | number | the number of remaining data to be transferred by the DMA
[out] | none
Return values
none

Definition at line 199 of file gd32f3x0_dma.c.

200 {
201 DMA_CHCNT(channelx) = (number & DMA_CHANNEL_CNT_MASK);
202 }
DMA_CHCNT
#define DMA_CHCNT(channel)
Definition: gd32f3x0_dma.h:133
DMA_CHANNEL_CNT_MASK
#define DMA_CHANNEL_CNT_MASK
Definition: gd32f3x0_dma.h:189
uint32_t dma_transfer_number_get ( dma_channel_enum channelx )

get the number of remaining data to be transferred by the DMA

Parameters
[in] channelx specify which DMA channel to set number
  • DMA_CHx(x=0..6)
[out] none
Return values
the number of remaining data to be transferred by the DMA

Definition at line 211 of file gd32f3x0_dma.c.

212 {
213 return (uint32_t)DMA_CHCNT(channelx);
214 }
DMA_CHCNT
#define DMA_CHCNT(channel)
Definition: gd32f3x0_dma.h:133
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_exti.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_exti.c File Reference

EXTI driver. More...

#include "gd32f3x0_exti.h"

Go to the source code of this file.

Functions

void | exti_deinit (void)
deinitialize the EXTI More...
void | exti_init (exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
initialize the EXTI More...
void | exti_interrupt_enable (exti_line_enum linex)
enable the interrupts from EXTI line x More...
void | exti_event_enable (exti_line_enum linex)
enable the events from EXTI line x More...
void | exti_interrupt_disable (exti_line_enum linex)
disable the interrupt from EXTI line x More...
void | exti_event_disable (exti_line_enum linex)
disable the events from EXTI line x More...
FlagStatus | exti_flag_get (exti_line_enum linex)
get EXTI lines flag More...
void | exti_flag_clear (exti_line_enum linex)
clear EXTI lines pending flag More...
FlagStatus | exti_interrupt_flag_get (exti_line_enum linex)
get EXTI lines flag when the interrupt flag is set More...
void | exti_interrupt_flag_clear (exti_line_enum linex)
clear EXTI lines pending flag More...
void | exti_software_interrupt_enable (exti_line_enum linex)
enable EXTI software interrupt event More...
void | exti_software_interrupt_disable (exti_line_enum linex)
disable EXTI software interrupt event More...

Detailed Description

EXTI driver.

Definition in file gd32f3x0_exti.c.

Function Documentation

void exti_deinit ( void )

deinitialize the EXTI

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_exti.c.

21 {
22 /* reset the value of all the EXTI registers */
23 EXTI_INTEN = (uint32_t)0x0F940000U;
24 EXTI_EVEN = (uint32_t)0x00000000U;
25 EXTI_RTEN = (uint32_t)0x00000000U;
26 EXTI_FTEN = (uint32_t)0x00000000U;
27 EXTI_SWIEV = (uint32_t)0x00000000U;
28 }
EXTI_SWIEV
#define EXTI_SWIEV
Definition: gd32f3x0_exti.h:25
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f3x0_exti.h:22
EXTI_FTEN
#define EXTI_FTEN
Definition: gd32f3x0_exti.h:24
EXTI_RTEN
#define EXTI_RTEN
Definition: gd32f3x0_exti.h:23
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f3x0_exti.h:21
void exti_event_disable ( exti_line_enum linex )

disable the events from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..27): EXTI line x
[out] none
Return values
none

Definition at line 135 of file gd32f3x0_exti.c.

136 {
137 EXTI_EVEN &= ~(uint32_t)linex;
138 }
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f3x0_exti.h:22
void exti_event_enable ( exti_line_enum linex )

enable the events from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..27): EXTI line x
[out] none
Return values
none

Definition at line 109 of file gd32f3x0_exti.c.

110 {
111 EXTI_EVEN |= (uint32_t)linex;
112 }
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f3x0_exti.h:22
void exti_flag_clear ( exti_line_enum linex )

clear EXTI lines pending flag

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19,21,22): EXTI line x
[out] none
Return values
none

Definition at line 165 of file gd32f3x0_exti.c.

166 {
167 EXTI_PD = (uint32_t)linex;
168 }
EXTI_PD
#define EXTI_PD
Definition: gd32f3x0_exti.h:26
FlagStatus exti_flag_get ( exti_line_enum linex )

get EXTI lines flag

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19,21,22): EXTI line x
[out] none
Return values
FlagStatus status of flag (RESET or SET)

Definition at line 148 of file gd32f3x0_exti.c.

149 {
150 if(RESET != (EXTI_PD & (uint32_t)linex)){
151 return SET;
152 }else{
153 return RESET;
154 }
155 }
EXTI_PD
#define EXTI_PD
Definition: gd32f3x0_exti.h:26
void exti_init | ( | exti_line_enum | linex,
 |  | exti_mode_enum | mode,
 |  | exti_trig_type_enum | trig_type
 | ) |  |

initialize the EXTI

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19,21,22): EXTI line x
[in] mode interrupt or event mode, refer to exti_mode_enum only one parameter can be selected which is shown as below:
  • EXTI_INTERRUPT: interrupt mode
  • EXTI_EVENT: event mode
[in] trig_type interrupt trigger type, refer to exti_trig_type_enum only one parameter can be selected which is shown as below:
  • EXTI_TRIG_RISING: rising edge trigger
  • EXTI_TRIG_FALLING: falling trigger
  • EXTI_TRIG_BOTH: rising and falling trigger
[out] none
Return values
none

Definition at line 47 of file gd32f3x0_exti.c.

50 {
51 /* reset the EXTI line x */
52 EXTI_INTEN &= ~(uint32_t)linex;
53 EXTI_EVEN &= ~(uint32_t)linex;
54 EXTI_RTEN &= ~(uint32_t)linex;
55 EXTI_FTEN &= ~(uint32_t)linex;
56
57 /* set the EXTI mode and enable the interrupts or events from EXTI line x */
58 switch(mode){
59 case EXTI_INTERRUPT:
60 EXTI_INTEN |= (uint32_t)linex;
61 break;
62 case EXTI_EVENT:
63 EXTI_EVEN |= (uint32_t)linex;
64 break;
65 default:
66 break;
67 }
68
69 /* set the EXTI trigger type */
70 switch(trig_type){
71 case EXTI_TRIG_RISING:
72 EXTI_RTEN |= (uint32_t)linex;
73 EXTI_FTEN &= ~(uint32_t)linex;
74 break;
75 case EXTI_TRIG_FALLING:
76 EXTI_RTEN &= ~(uint32_t)linex;
77 EXTI_FTEN |= (uint32_t)linex;
78 break;
79 case EXTI_TRIG_BOTH:
80 EXTI_RTEN |= (uint32_t)linex;
81 EXTI_FTEN |= (uint32_t)linex;
82 break;
83 default:
84 break;
85 }
86 }
EXTI_TRIG_FALLING
Definition: gd32f3x0_exti.h:230
EXTI_EVENT
Definition: gd32f3x0_exti.h:223
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f3x0_exti.h:22
EXTI_FTEN
#define EXTI_FTEN
Definition: gd32f3x0_exti.h:24
EXTI_RTEN
#define EXTI_RTEN
Definition: gd32f3x0_exti.h:23
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f3x0_exti.h:21
EXTI_INTERRUPT
Definition: gd32f3x0_exti.h:222
EXTI_TRIG_BOTH
Definition: gd32f3x0_exti.h:231
EXTI_TRIG_RISING
Definition: gd32f3x0_exti.h:229
void exti_interrupt_disable ( exti_line_enum linex )

disable the interrupt from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..27): EXTI line x
[out] none
Return values
none

Definition at line 122 of file gd32f3x0_exti.c.

123 {
124 EXTI_INTEN &= ~(uint32_t)linex;
125 }
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f3x0_exti.h:21
void exti_interrupt_enable ( exti_line_enum linex )

enable the interrupts from EXTI line x

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..27): EXTI line x
[out] none
Return values
none

Definition at line 96 of file gd32f3x0_exti.c.

97 {
98 EXTI_INTEN |= (uint32_t)linex;
99 }
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f3x0_exti.h:21
void exti_interrupt_flag_clear ( exti_line_enum linex )

clear EXTI lines pending flag

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19,21,22): EXTI line x
[out] none
Return values
none

Definition at line 200 of file gd32f3x0_exti.c.

201 {
202 EXTI_PD = (uint32_t)linex;
203 }
EXTI_PD
#define EXTI_PD
Definition: gd32f3x0_exti.h:26
FlagStatus exti_interrupt_flag_get ( exti_line_enum linex )

get EXTI lines flag when the interrupt flag is set

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19,21,22): EXTI line x
[out] none
Return values
FlagStatus status of flag (RESET or SET)

Definition at line 178 of file gd32f3x0_exti.c.

179 {
180 uint32_t flag_left, flag_right;
181
182 flag_left = EXTI_PD & (uint32_t)linex;
183 flag_right = EXTI_INTEN & (uint32_t)linex;
184
185 if((RESET != flag_left) && (RESET != flag_right)){
186 return SET;
187 }else{
188 return RESET;
189 }
190 }
EXTI_PD
#define EXTI_PD
Definition: gd32f3x0_exti.h:26
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f3x0_exti.h:21
void exti_software_interrupt_disable ( exti_line_enum linex )

disable EXTI software interrupt event

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19,21,22): EXTI line x
[out] none
Return values
none

Definition at line 226 of file gd32f3x0_exti.c.

227 {
228 EXTI_SWIEV &= ~(uint32_t)linex;
229 }
EXTI_SWIEV
#define EXTI_SWIEV
Definition: gd32f3x0_exti.h:25
void exti_software_interrupt_enable ( exti_line_enum linex )

enable EXTI software interrupt event

Parameters
[in] linex EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below:
  • EXTI_x (x=0..19,21,22): EXTI line x
[out] none
Return values
none

Definition at line 213 of file gd32f3x0_exti.c.

214 {
215 EXTI_SWIEV |= (uint32_t)linex;
216 }
EXTI_SWIEV
#define EXTI_SWIEV
Definition: gd32f3x0_exti.h:25
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_fmc.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_fmc.c File Reference

FMC driver. More...

#include "gd32f3x0_fmc.h"

Go to the source code of this file.

Functions

void | fmc_unlock (void)
unlock the main FMC operation it is better to used in pairs with fmc_lock More...
void | fmc_lock (void)
lock the main FMC operation it is better to used in pairs with fmc_unlock after an operation More...
void | fmc_wscnt_set (uint8_t wscnt)
set the wait state counter value More...
void | fmc_wait_state_enable (void)
fmc wait state enable More...
void | fmc_wait_state_disable (void)
fmc wait state disable More...
fmc_state_enum | fmc_page_erase (uint32_t page_address)
erase page More...
fmc_state_enum | fmc_mass_erase (void)
erase whole chip More...
fmc_state_enum | fmc_word_program (uint32_t address, uint32_t data)
program a word at the corresponding address More...
fmc_state_enum | fmc_halfword_program (uint32_t address, uint16_t data)
program a half word at the corresponding address More...
fmc_state_enum | fmc_word_reprogram (uint32_t address, uint32_t data)
program a word at the corresponding address without erasing More...
void | ob_unlock (void)
unlock the option byte operation it is better to used in pairs with ob_lock More...
void | ob_lock (void)
lock the option byte operation it is better to used in pairs with ob_unlock after an operation More...
void | ob_reset (void)
reload the option byte and generate a system reset More...
fmc_state_enum | ob_erase (void)
erase the option byte programmer must ensure FMC & option byte are both unlocked before calling this function More...
fmc_state_enum | ob_write_protection_enable (uint32_t ob_wp)
enable option byte write protection (OB_WP) More...
fmc_state_enum | ob_security_protection_config (uint8_t ob_spc)
configure security protection More...
fmc_state_enum | ob_user_write (uint8_t ob_user)
program the FMC user option byte More...
fmc_state_enum | ob_data_program (uint32_t address, uint8_t data)
program the FMC data option byte More...
uint8_t | ob_user_get (void)
get OB_USER in register FMC_OBSTAT More...
uint16_t | ob_data_get (void)
get OB_DATA in register FMC_OBSTAT More...
uint16_t | ob_write_protection_get (void)
get the FMC option byte write protection (OB_WP) in register FMC_WP More...
uint32_t | ob_obstat_plevel_get (void)
get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register More...
void | fmc_interrupt_enable (uint32_t interrupt)
enable FMC interrupt More...
void | fmc_interrupt_disable (uint32_t interrupt)
disable FMC interrupt More...
FlagStatus | fmc_flag_get (uint32_t flag)
get flag set or reset More...
void | fmc_flag_clear (uint32_t flag)
clear the FMC pending flag by writing 1 More...
fmc_state_enum | fmc_state_get (void)
get the FMC state More...
fmc_state_enum | fmc_ready_wait (uint32_t timeout)
check whether FMC is ready or not More...

Detailed Description

FMC driver.

Definition in file gd32f3x0_fmc.c.

Function Documentation

void fmc_flag_clear ( uint32_t flag )

clear the FMC pending flag by writing 1

Parameters
[in] flag clear FMC flag
  • FMC_FLAG_PGERR: FMC programming error flag
  • FMC_FLAG_WPERR: FMC write protection error flag
  • FMC_FLAG_END: fmc end of programming flag
[out] none
Return values
none

Definition at line 606 of file gd32f3x0_fmc.c.

607 {
608 /* clear the flags */
609 FMC_STAT = flag;
610 }
FMC_STAT
#define FMC_STAT
Definition: gd32f3x0_fmc.h:25
FlagStatus fmc_flag_get ( uint32_t flag )

get flag set or reset

Parameters
[in] flag check FMC flag
  • FMC_FLAG_BUSY: FMC busy flag
  • FMC_FLAG_PGERR: FMC programming error flag
  • FMC_FLAG_WPERR: FMC write protection error flag
  • FMC_FLAG_END: FMC end of programming flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 586 of file gd32f3x0_fmc.c.

587 {
588 FlagStatus status = RESET;
589
590 if(FMC_STAT & flag){
591 status = SET;
592 }
593 /* return the state of corresponding FMC flag */
594 return status;
595 }
FMC_STAT
#define FMC_STAT
Definition: gd32f3x0_fmc.h:25
fmc_state_enum fmc_halfword_program | ( | uint32_t | address,
 |  | uint16_t | data
 | ) |  |

program a half word at the corresponding address

Parameters
[in] | address | address to program
[in] | data | word to program
[out] | none
Return values
fmc_state

Definition at line 188 of file gd32f3x0_fmc.c.

189 {
190 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
191
192 if(FMC_READY == fmc_state){
193 /* set the PG bit to start program */
194 FMC_CTL |= FMC_CTL_PG;
195
196 REG16(address) = data;
197
198 /* wait for the FMC ready */
199 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
200
201 /* reset the PG bit */
202 FMC_CTL &= ~FMC_CTL_PG;
203 }
204
205 /* return the FMC state */
206 return fmc_state;
207 }
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL_PG
#define FMC_CTL_PG
Definition: gd32f3x0_fmc.h:55
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
void fmc_interrupt_disable ( uint32_t interrupt )

disable FMC interrupt

Parameters
[in] interrupt the FMC interrupt source
  • FMC_INTEN_END: FMC end of operation interrupt
  • FMC_INTEN_ERR: FMC error interrupt
[out] none
Return values
none

Definition at line 571 of file gd32f3x0_fmc.c.

572 {
573 FMC_CTL &= ~(uint32_t)interrupt;
574 }
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
void fmc_interrupt_enable ( uint32_t interrupt )

enable FMC interrupt

Parameters
[in] interrupt the FMC interrupt source
  • FMC_INTEN_END: FMC end of operation interrupt
  • FMC_INTEN_ERR: FMC error interrupt
[out] none
Return values
none

Definition at line 558 of file gd32f3x0_fmc.c.

559 {
560 FMC_CTL |= interrupt;
561 }
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
void fmc_lock ( void )

lock the main FMC operation it is better to used in pairs with fmc_unlock after an operation

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 39 of file gd32f3x0_fmc.c.

40 {
41 /* set the LK bit*/
42 FMC_CTL |= FMC_CTL_LK;
43 }
FMC_CTL_LK
#define FMC_CTL_LK
Definition: gd32f3x0_fmc.h:61
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum fmc_mass_erase ( void )

erase whole chip

Parameters
[in] | none
[out] | none
Return values
fmc_state

Definition at line 133 of file gd32f3x0_fmc.c.

134 {
135 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
136
137 if(FMC_READY == fmc_state){
138 /* start chip erase */
139 FMC_CTL |= FMC_CTL_MER;
140 FMC_CTL |= FMC_CTL_START;
141
142 /* wait for the FMC ready */
143 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
144
145 /* reset the MER bit */
146 FMC_CTL &= ~FMC_CTL_MER;
147 }
148
149 /* return the fmc state */
150 return fmc_state;
151 }
FMC_CTL_START
#define FMC_CTL_START
Definition: gd32f3x0_fmc.h:60
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL_MER
#define FMC_CTL_MER
Definition: gd32f3x0_fmc.h:57
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
fmc_state_enum fmc_page_erase ( uint32_t page_address )

erase page

Parameters
[in] | page_address | target page start address
[out] | none
Return values
fmc_state

Definition at line 106 of file gd32f3x0_fmc.c.

107 {
108 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
109
110 if(FMC_READY == fmc_state){
111 /* start page erase */
112 FMC_CTL |= FMC_CTL_PER;
113 FMC_ADDR = page_address;
114 FMC_CTL |= FMC_CTL_START;
115
116 /* wait for the FMC ready */
117 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
118
119 /* reset the PER bit */
120 FMC_CTL &= ~FMC_CTL_PER;
121 }
122
123 /* return the FMC state */
124 return fmc_state;
125 }
FMC_CTL_START
#define FMC_CTL_START
Definition: gd32f3x0_fmc.h:60
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_ADDR
#define FMC_ADDR
Definition: gd32f3x0_fmc.h:27
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
FMC_CTL_PER
#define FMC_CTL_PER
Definition: gd32f3x0_fmc.h:56
fmc_state_enum fmc_ready_wait ( uint32_t timeout )

check whether FMC is ready or not

Parameters
[in] | timeout | timeout count
[out] | none
Return values
fmc_state

Definition at line 643 of file gd32f3x0_fmc.c.

644 {
645 fmc_state_enum fmc_state = FMC_BUSY;
646
647 /* wait for FMC ready */
648 do{
649 /* get FMC state */
650 fmc_state = fmc_state_get();
651 timeout--;
652 }while((FMC_BUSY == fmc_state) && (0U != timeout));
653
654 if(FMC_BUSY == fmc_state){
655 fmc_state = FMC_TOERR;
656 }
657 /* return the FMC state */
658 return fmc_state;
659 }
fmc_state_get
fmc_state_enum fmc_state_get(void)
get the FMC state
Definition: gd32f3x0_fmc.c:618
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
FMC_BUSY
Definition: gd32f3x0_fmc.h:89
fmc_state_enum fmc_state_get ( void )

get the FMC state

Parameters
[in] | none
[out] | none
Return values
fmc_state

Definition at line 618 of file gd32f3x0_fmc.c.

619 {
620 fmc_state_enum fmc_state = FMC_READY;
621
622 if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)){
623 fmc_state = FMC_BUSY;
624 }else{
625 if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)){
626 fmc_state = FMC_WPERR;
627 }else{
628 if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGERR)){
629 fmc_state = FMC_PGERR;
630 }
631 }
632 }
633 /* return the FMC state */
634 return fmc_state;
635 }
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_STAT
#define FMC_STAT
Definition: gd32f3x0_fmc.h:25
FMC_STAT_PGERR
#define FMC_STAT_PGERR
Definition: gd32f3x0_fmc.h:50
FMC_PGERR
Definition: gd32f3x0_fmc.h:90
FMC_STAT_WPERR
#define FMC_STAT_WPERR
Definition: gd32f3x0_fmc.h:51
FMC_STAT_BUSY
#define FMC_STAT_BUSY
Definition: gd32f3x0_fmc.h:49
FMC_WPERR
Definition: gd32f3x0_fmc.h:91
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
FMC_BUSY
Definition: gd32f3x0_fmc.h:89
void fmc_unlock ( void )

unlock the main FMC operation it is better to used in pairs with fmc_lock

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 23 of file gd32f3x0_fmc.c.

24 {
25 if((RESET != (FMC_CTL & FMC_CTL_LK))){
26 /* write the FMC key */
27 FMC_KEY = UNLOCK_KEY0;
28 FMC_KEY = UNLOCK_KEY1;
29 }
30 }
UNLOCK_KEY1
#define UNLOCK_KEY1
Definition: gd32f3x0_fmc.h:98
UNLOCK_KEY0
#define UNLOCK_KEY0
Definition: gd32f3x0_fmc.h:97
FMC_KEY
#define FMC_KEY
Definition: gd32f3x0_fmc.h:23
FMC_CTL_LK
#define FMC_CTL_LK
Definition: gd32f3x0_fmc.h:61
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
void fmc_wait_state_disable ( void )

fmc wait state disable

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 88 of file gd32f3x0_fmc.c.

89 {
90 /* unlock the main flash */
91 fmc_unlock();
92
93 /* reset the WSEN bit in register FMC_WSEN */
94 FMC_WSEN &= ~FMC_WSEN_WSEN;
95
96 /* lock the main flash after operation */
97 fmc_lock();
98 }
fmc_lock
void fmc_lock(void)
lock the main FMC operation it is better to used in pairs with fmc_unlock after an operation ...
Definition: gd32f3x0_fmc.c:39
FMC_WSEN
#define FMC_WSEN
Definition: gd32f3x0_fmc.h:30
fmc_unlock
void fmc_unlock(void)
unlock the main FMC operation it is better to used in pairs with fmc_lock
Definition: gd32f3x0_fmc.c:23
FMC_WSEN_WSEN
#define FMC_WSEN_WSEN
Definition: gd32f3x0_fmc.h:78
void fmc_wait_state_enable ( void )

fmc wait state enable

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 70 of file gd32f3x0_fmc.c.

71 {
72 /* unlock the main flash */
73 fmc_unlock();
74
75 /* set the WSEN bit in register FMC_WSEN */
76 FMC_WSEN |= FMC_WSEN_WSEN;
77
78 /* lock the main flash after operation */
79 fmc_lock();
80 }
fmc_lock
void fmc_lock(void)
lock the main FMC operation it is better to used in pairs with fmc_unlock after an operation ...
Definition: gd32f3x0_fmc.c:39
FMC_WSEN
#define FMC_WSEN
Definition: gd32f3x0_fmc.h:30
fmc_unlock
void fmc_unlock(void)
unlock the main FMC operation it is better to used in pairs with fmc_lock
Definition: gd32f3x0_fmc.c:23
FMC_WSEN_WSEN
#define FMC_WSEN_WSEN
Definition: gd32f3x0_fmc.h:78
fmc_state_enum fmc_word_program | ( | uint32_t | address,
 |  | uint32_t | data
 | ) |  |

program a word at the corresponding address

Parameters
[in] | address | address to program
[in] | data | word to program
[out] | none
Return values
fmc_state

Definition at line 160 of file gd32f3x0_fmc.c.

161 {
162 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
163
164 if(FMC_READY == fmc_state){
165 /* set the PG bit to start program */
166 FMC_CTL |= FMC_CTL_PG;
167
168 REG32(address) = data;
169
170 /* wait for the FMC ready */
171 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
172
173 /* reset the PG bit */
174 FMC_CTL &= ~FMC_CTL_PG;
175 }
176
177 /* return the FMC state */
178 return fmc_state;
179 }
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL_PG
#define FMC_CTL_PG
Definition: gd32f3x0_fmc.h:55
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
fmc_state_enum fmc_word_reprogram | ( | uint32_t | address,
 |  | uint32_t | data
 | ) |  |

program a word at the corresponding address without erasing

Parameters
[in] | address | address to program
[in] | data | word to program
[out] | none
Return values
fmc_state

Definition at line 216 of file gd32f3x0_fmc.c.

217 {
218 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
219 FMC_WSEN |= FMC_WSEN_BPEN;
220
221 if(FMC_READY == fmc_state){
222 /* set the PG bit to start program */
223 FMC_CTL |= FMC_CTL_PG;
224
225 REG32(address) = data;
226
227 /* wait for the FMC ready */
228 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
229
230 /* reset the PG bit */
231 FMC_CTL &= ~FMC_CTL_PG;
232 }
233
234 /* return the FMC state */
235 return fmc_state;
236 }
FMC_WSEN
#define FMC_WSEN
Definition: gd32f3x0_fmc.h:30
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_WSEN_BPEN
#define FMC_WSEN_BPEN
Definition: gd32f3x0_fmc.h:79
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL_PG
#define FMC_CTL_PG
Definition: gd32f3x0_fmc.h:55
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
void fmc_wscnt_set ( uint8_t wscnt )

set the wait state counter value

Parameters
[in] wscnt wait state counter value
  • WS_WSCNT_0: 0 wait state added
  • WS_WSCNT_1: 1 wait state added
  • WS_WSCNT_2: 2 wait state added
[out] none
Return values
none

Definition at line 54 of file gd32f3x0_fmc.c.

55 {
56 uint32_t reg;
57
58 reg = FMC_WS;
59 /* set the wait state counter value */
60 reg &= ~FMC_WS_WSCNT;
61 FMC_WS = (reg | wscnt);
62 }
FMC_WS_WSCNT
#define FMC_WS_WSCNT
Definition: gd32f3x0_fmc.h:40
FMC_WS
#define FMC_WS
Definition: gd32f3x0_fmc.h:22
uint16_t ob_data_get ( void )

get OB_DATA in register FMC_OBSTAT

Parameters
[in] | none
[out] | none
Return values
ob_data

Definition at line 522 of file gd32f3x0_fmc.c.

523 {
524 return (uint16_t)(FMC_OBSTAT >> 16);
525 }
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f3x0_fmc.h:28
fmc_state_enum ob_data_program | ( | uint32_t | address,
 |  | uint8_t | data
 | ) |  |

program the FMC data option byte

Parameters
[in] address OB_DATA_ADDR0 or OB_DATA_ADDR1
  • OB_DATA_ADDR0: option byte data address 0
  • OB_DATA_ADDR1: option byte data address 1
[in] | data | the byte to be programmed
[out] | none
Return values
fmc_state

Definition at line 484 of file gd32f3x0_fmc.c.

485 {
486 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
487
488 if(FMC_READY == fmc_state){
489 /* set the OBPG bit */
490 FMC_CTL |= FMC_CTL_OBPG;
491 REG16(address) = data;
492
493 /* wait for the FMC ready */
494 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
495
496 if(FMC_TOERR != fmc_state){
497 /* reset the OBPG bit */
498 FMC_CTL &= ~FMC_CTL_OBPG;
499 }
500 }
501 /* return the FMC state */
502 return fmc_state;
503 }
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
FMC_CTL_OBPG
#define FMC_CTL_OBPG
Definition: gd32f3x0_fmc.h:58
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
fmc_state_enum ob_erase ( void )

erase the option byte programmer must ensure FMC & option byte are both unlocked before calling this function

Parameters
[in] | none
[out] | none
Return values
fmc_state

Definition at line 288 of file gd32f3x0_fmc.c.

289 {
290 uint16_t fmc_spc;
291 uint32_t fmc_plevel = ob_obstat_plevel_get();
292 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
293
294 /* get the original option byte security protection code */
295 if(OB_OBSTAT_PLEVEL_NO == fmc_plevel){
296 fmc_spc = FMC_NSPC;
297 }else if(OB_OBSTAT_PLEVEL_LOW == fmc_plevel){
298 fmc_spc = FMC_LSPC;
299 }else{
300 fmc_spc = FMC_HSPC;
301 fmc_state = FMC_OB_HSPC;
302 }
303
304 if(FMC_READY == fmc_state){
305 /* start erase the option byte */
306 FMC_CTL |= FMC_CTL_OBER;
307 FMC_CTL |= FMC_CTL_START;
308
309 /* wait for the FMC ready */
310 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
311
312 if(FMC_READY == fmc_state){
313 /* reset the OBER bit */
314 FMC_CTL &= ~FMC_CTL_OBER;
315
316 /* set the OBPG bit */
317 FMC_CTL |= FMC_CTL_OBPG;
318
319 /* restore the last get option byte security protection code */
320 OB_SPC = fmc_spc;
321
322 /* wait for the FMC ready */
323 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
324
325 if(FMC_TOERR != fmc_state){
326 /* reset the OBPG bit */
327 FMC_CTL &= ~FMC_CTL_OBPG;
328 }
329 }else{
330 if(FMC_TOERR != fmc_state){
331 /* reset the OBPG bit */
332 FMC_CTL &= ~FMC_CTL_OBPG;
333 }
334 }
335 }
336 /* return the FMC state */
337 return fmc_state;
338 }
FMC_CTL_START
#define FMC_CTL_START
Definition: gd32f3x0_fmc.h:60
OB_OBSTAT_PLEVEL_NO
#define OB_OBSTAT_PLEVEL_NO
Definition: gd32f3x0_fmc.h:145
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_LSPC
#define FMC_LSPC
Definition: gd32f3x0_fmc.h:107
OB_SPC
#define OB_SPC
Definition: gd32f3x0_fmc.h:33
FMC_OB_HSPC
Definition: gd32f3x0_fmc.h:93
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
OB_OBSTAT_PLEVEL_LOW
#define OB_OBSTAT_PLEVEL_LOW
Definition: gd32f3x0_fmc.h:146
FMC_CTL_OBPG
#define FMC_CTL_OBPG
Definition: gd32f3x0_fmc.h:58
ob_obstat_plevel_get
uint32_t ob_obstat_plevel_get(void)
get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register ...
Definition: gd32f3x0_fmc.c:544
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
FMC_HSPC
#define FMC_HSPC
Definition: gd32f3x0_fmc.h:108
FMC_NSPC
#define FMC_NSPC
Definition: gd32f3x0_fmc.h:106
FMC_CTL_OBER
#define FMC_CTL_OBER
Definition: gd32f3x0_fmc.h:59
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
void ob_lock ( void )

lock the option byte operation it is better to used in pairs with ob_unlock after an operation

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 263 of file gd32f3x0_fmc.c.

264 {
265 /* reset the OBWE bit */
266 FMC_CTL &= ~FMC_CTL_OBWEN;
267 }
FMC_CTL_OBWEN
#define FMC_CTL_OBWEN
Definition: gd32f3x0_fmc.h:62
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
uint32_t ob_obstat_plevel_get ( void )

get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register

Parameters
[in] | none
[out] | none
Return values
the value of PLEVEL

Definition at line 544 of file gd32f3x0_fmc.c.

545 {
546 return (FMC_OBSTAT & (FMC_OBSTAT_PLVL_BIT0 | FMC_OBSTAT_PLVL_BIT1));
547 }
FMC_OBSTAT_PLVL_BIT1
#define FMC_OBSTAT_PLVL_BIT1
Definition: gd32f3x0_fmc.h:73
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f3x0_fmc.h:28
FMC_OBSTAT_PLVL_BIT0
#define FMC_OBSTAT_PLVL_BIT0
Definition: gd32f3x0_fmc.h:72
void ob_reset ( void )

reload the option byte and generate a system reset

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 275 of file gd32f3x0_fmc.c.

276 {
277 /* set the OBRLD bit */
278 FMC_CTL |= FMC_CTL_OBRLD;
279 }
FMC_CTL_OBRLD
#define FMC_CTL_OBRLD
Definition: gd32f3x0_fmc.h:65
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum ob_security_protection_config ( uint8_t ob_spc )

configure security protection

Parameters
[in] ob_spc specify security protection code
  • FMC_NSPC: no security protection
  • FMC_LSPC: low security protection
  • FMC_HSPC: high security protection
[out] none
Return values
fmc_state

Definition at line 390 of file gd32f3x0_fmc.c.

391 {
392 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
393
394 /* the OB_SPC byte cannot be reprogrammed if protection level is high */
395 if(OB_OBSTAT_PLEVEL_HIGH == ob_obstat_plevel_get()){
396 fmc_state = FMC_OB_HSPC;
397 }
398
399 if(FMC_READY == fmc_state){
400 /* start erase the option byte */
401 FMC_CTL |= FMC_CTL_OBER;
402 FMC_CTL |= FMC_CTL_START;
403
404 /* wait for the FMC ready */
405 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
406
407 if(FMC_READY == fmc_state){
408
409 /* reset the OBER bit */
410 FMC_CTL &= ~FMC_CTL_OBER;
411
412 /* enable the option bytes programming */
413 FMC_CTL |= FMC_CTL_OBPG;
414
415 OB_SPC = ob_spc;
416
417 /* wait for the FMC ready */
418 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
419
420 if(FMC_TOERR != fmc_state){
421 /* reset the OBPG bit */
422 FMC_CTL &= ~FMC_CTL_OBPG;
423 }
424 }else{
425 if(FMC_TOERR != fmc_state){
426 /* reset the OBER bit */
427 FMC_CTL &= ~FMC_CTL_OBER;
428 }
429 }
430 }
431 /* return the FMC state */
432 return fmc_state;
433 }
FMC_CTL_START
#define FMC_CTL_START
Definition: gd32f3x0_fmc.h:60
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
OB_SPC
#define OB_SPC
Definition: gd32f3x0_fmc.h:33
FMC_OB_HSPC
Definition: gd32f3x0_fmc.h:93
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
OB_OBSTAT_PLEVEL_HIGH
#define OB_OBSTAT_PLEVEL_HIGH
Definition: gd32f3x0_fmc.h:147
FMC_CTL_OBPG
#define FMC_CTL_OBPG
Definition: gd32f3x0_fmc.h:58
ob_obstat_plevel_get
uint32_t ob_obstat_plevel_get(void)
get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register ...
Definition: gd32f3x0_fmc.c:544
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
FMC_CTL_OBER
#define FMC_CTL_OBER
Definition: gd32f3x0_fmc.h:59
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
void ob_unlock ( void )

unlock the option byte operation it is better to used in pairs with ob_lock

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 247 of file gd32f3x0_fmc.c.

248 {
249 if(RESET == (FMC_CTL & FMC_CTL_OBWEN)){
250 /* write the FMC key */
251 FMC_OBKEY = UNLOCK_KEY0;
252 FMC_OBKEY = UNLOCK_KEY1;
253 }
254 }
FMC_CTL_OBWEN
#define FMC_CTL_OBWEN
Definition: gd32f3x0_fmc.h:62
FMC_OBKEY
#define FMC_OBKEY
Definition: gd32f3x0_fmc.h:24
UNLOCK_KEY1
#define UNLOCK_KEY1
Definition: gd32f3x0_fmc.h:98
UNLOCK_KEY0
#define UNLOCK_KEY0
Definition: gd32f3x0_fmc.h:97
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
uint8_t ob_user_get ( void )

get OB_USER in register FMC_OBSTAT

Parameters
[in] | none
[out] | none
Return values
ob_user

Definition at line 511 of file gd32f3x0_fmc.c.

512 {
513 return (uint8_t)(FMC_OBSTAT >> 8);
514 }
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f3x0_fmc.h:28
fmc_state_enum ob_user_write ( uint8_t ob_user )

program the FMC user option byte

Parameters
[in] ob_user user option byte
  • OB_FWDGT_SW: software free watchdog timer
  • OB_FWDGT_HW: hardware free watchdog timer
  • OB_DEEPSLEEP_NRST: generate a reset instead of entering deepsleep mode
  • OB_DEEPSLEEP_RST: no reset when entering deepsleep mode
  • OB_STDBY_NRST: generate a reset instead of entering standby mode
  • OB_STDBY_RST: no reset when entering deepsleep mode
  • OB_BOOT1_SET_1: BOOT1 bit is 1
  • OB_BOOT1_SET_0: BOOT1 bit is 0
  • OB_VDDA_DISABLE: disable VDDA monitor
  • OB_VDDA_ENABLE: enable VDDA monitor
  • OB_SRAM_PARITY_DISABLE: disable sram parity check
  • OB_SRAM_PARITY_ENABLE: enable sram parity check
[out] none
Return values
fmc_state

Definition at line 453 of file gd32f3x0_fmc.c.

454 {
455 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
456
457 if(FMC_READY == fmc_state){
458 /* set the OBPG bit */
459 FMC_CTL |= FMC_CTL_OBPG;
460
461 OB_USER = (uint8_t)(ob_user | OB_USER_MASK);
462
463 /* wait for the FMC ready */
464 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
465
466 if(FMC_TOERR != fmc_state){
467 /* reset the OBPG bit */
468 FMC_CTL &= ~FMC_CTL_OBPG;
469 }
470 }
471 /* return the FMC state */
472 return fmc_state;
473 }
OB_USER_MASK
#define OB_USER_MASK
Definition: gd32f3x0_fmc.h:150
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
FMC_CTL_OBPG
#define FMC_CTL_OBPG
Definition: gd32f3x0_fmc.h:58
OB_USER
#define OB_USER
Definition: gd32f3x0_fmc.h:34
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
fmc_state_enum ob_write_protection_enable ( uint32_t ob_wp )

enable option byte write protection (OB_WP)

Parameters
[in] | ob_wp | write protection configuration data
[out] | none
Return values
fmc_state

Definition at line 346 of file gd32f3x0_fmc.c.

347 {
348 uint16_t ob_wrp0, ob_wrp1;
349
350 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
351
352 ob_wp = (uint32_t)(~ob_wp);
353 ob_wrp0 = (uint16_t)(ob_wp & OB_LWP);
354 ob_wrp1 = (uint16_t)((ob_wp & OB_HWP) >> 8);
355
356 if(FMC_READY == fmc_state){
357 /* set the OBPG bit*/
358 FMC_CTL |= FMC_CTL_OBPG;
359
360 if(0xFFU != ob_wrp0){
361 OB_WP0 = ob_wrp0;
362
363 /* wait for the FMC ready */
364 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
365 }
366 if((FMC_READY == fmc_state) && (0xFFU != ob_wrp1)){
367 OB_WP1 = ob_wrp1;
368
369 /* wait for the FMC ready */
370 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
371 }
372 if(FMC_TOERR != fmc_state){
373 /* reset the OBPG bit */
374 FMC_CTL &= ~FMC_CTL_OBPG;
375 }
376 }
377 /* return the FMC state */
378 return fmc_state;
379 }
OB_LWP
#define OB_LWP
Definition: gd32f3x0_fmc.h:111
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
OB_HWP
#define OB_HWP
Definition: gd32f3x0_fmc.h:112
OB_WP0
#define OB_WP0
Definition: gd32f3x0_fmc.h:35
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
FMC_CTL_OBPG
#define FMC_CTL_OBPG
Definition: gd32f3x0_fmc.h:58
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
OB_WP1
#define OB_WP1
Definition: gd32f3x0_fmc.h:36
uint16_t ob_write_protection_get ( void )

get the FMC option byte write protection (OB_WP) in register FMC_WP

Parameters
[in] | none
[out] | none
Return values
OB_WP

Definition at line 533 of file gd32f3x0_fmc.c.

534 {
535 return (uint16_t)(FMC_WP);
536 }
FMC_WP
#define FMC_WP
Definition: gd32f3x0_fmc.h:29
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_fwdgt.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_fwdgt.c File Reference

FWDGT driver. More...

#include "gd32f3x0_fwdgt.h"

Go to the source code of this file.

Functions

void | fwdgt_write_disable (void)
disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND More...
void | fwdgt_counter_reload (void)
reload the counter of FWDGT More...
void | fwdgt_enable (void)
start the free watchdog timer counter More...
ErrStatus | fwdgt_window_value_config (uint16_t window_value)
configure the free watchdog timer counter window value More...
ErrStatus | fwdgt_config (uint16_t reload_value, uint8_t prescaler_div)
configure counter reload value, and prescaler divider value More...
FlagStatus | fwdgt_flag_get (uint16_t flag)
get flag state of FWDGT More...

Detailed Description

FWDGT driver.

Definition in file gd32f3x0_fwdgt.c.

Function Documentation

ErrStatus fwdgt_config | ( | uint16_t | reload_value,
 |  | uint8_t | prescaler_div
 | ) |  |

configure counter reload value, and prescaler divider value

Parameters
[in] | reload_value | specify reload value(0x0000 - 0x0FFF)
[in] prescaler_div FWDGT prescaler value
  • FWDGT_PSC_DIV4: FWDGT prescaler set to 4
  • FWDGT_PSC_DIV8: FWDGT prescaler set to 8
  • FWDGT_PSC_DIV16: FWDGT prescaler set to 16
  • FWDGT_PSC_DIV32: FWDGT prescaler set to 32
  • FWDGT_PSC_DIV64: FWDGT prescaler set to 64
  • FWDGT_PSC_DIV128: FWDGT prescaler set to 128
  • FWDGT_PSC_DIV256: FWDGT prescaler set to 256
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 89 of file gd32f3x0_fwdgt.c.

90 {
91 uint32_t timeout = FWDGT_PSC_TIMEOUT;
92 uint32_t flag_status = RESET;
93
94 /* enable write access to FWDGT_PSC,and FWDGT_RLD */
95 FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
96
97 /* wait until the PUD flag to be reset */
98 do{
99 flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
100 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
101
102 if ((uint32_t)RESET != flag_status){
103 return ERROR;
104 }
105
106 /* configure FWDGT */
107 FWDGT_PSC = (uint32_t)prescaler_div;
108
109 timeout = FWDGT_RLD_TIMEOUT;
110 /* wait until the RUD flag to be reset */
111 do{
112 flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
113 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
114
115 if ((uint32_t)RESET != flag_status){
116 return ERROR;
117 }
118
119 FWDGT_RLD = RLD_RLD(reload_value);
120
121 /* reload the counter */
122 FWDGT_CTL = FWDGT_KEY_RELOAD;
123
124 return SUCCESS;
125 }
FWDGT_RLD_TIMEOUT
#define FWDGT_RLD_TIMEOUT
Definition: gd32f3x0_fwdgt.h:74
FWDGT_WRITEACCESS_ENABLE
#define FWDGT_WRITEACCESS_ENABLE
Definition: gd32f3x0_fwdgt.h:66
FWDGT_RLD
#define FWDGT_RLD
Definition: gd32f3x0_fwdgt.h:23
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f3x0_fwdgt.h:21
FWDGT_KEY_RELOAD
#define FWDGT_KEY_RELOAD
Definition: gd32f3x0_fwdgt.h:68
RLD_RLD
#define RLD_RLD(regval)
Definition: gd32f3x0_fwdgt.h:60
FWDGT_STAT_PUD
#define FWDGT_STAT_PUD
Definition: gd32f3x0_fwdgt.h:38
FWDGT_PSC_TIMEOUT
#define FWDGT_PSC_TIMEOUT
Definition: gd32f3x0_fwdgt.h:73
FWDGT_STAT
#define FWDGT_STAT
Definition: gd32f3x0_fwdgt.h:24
FWDGT_STAT_RUD
#define FWDGT_STAT_RUD
Definition: gd32f3x0_fwdgt.h:39
FWDGT_PSC
#define FWDGT_PSC
Definition: gd32f3x0_fwdgt.h:22
void fwdgt_counter_reload ( void )

reload the counter of FWDGT

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 31 of file gd32f3x0_fwdgt.c.

32 {
33 FWDGT_CTL = FWDGT_KEY_RELOAD;
34 }
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f3x0_fwdgt.h:21
FWDGT_KEY_RELOAD
#define FWDGT_KEY_RELOAD
Definition: gd32f3x0_fwdgt.h:68
void fwdgt_enable ( void )

start the free watchdog timer counter

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 42 of file gd32f3x0_fwdgt.c.

43 {
44 FWDGT_CTL = FWDGT_KEY_ENABLE;
45 }
FWDGT_KEY_ENABLE
#define FWDGT_KEY_ENABLE
Definition: gd32f3x0_fwdgt.h:69
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f3x0_fwdgt.h:21
FlagStatus fwdgt_flag_get ( uint16_t flag )

get flag state of FWDGT

Parameters
[in] flag flag to get
  • FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
  • FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
  • FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going
[out] none
Return values
FlagStatus SET or RESET

Definition at line 136 of file gd32f3x0_fwdgt.c.

137 {
138 if(FWDGT_STAT & flag){
139 return SET;
140 }
141 return RESET;
142 }
FWDGT_STAT
#define FWDGT_STAT
Definition: gd32f3x0_fwdgt.h:24
ErrStatus fwdgt_window_value_config ( uint16_t window_value )

configure the free watchdog timer counter window value

Parameters
[in] | window_value | specify window value(0x0000 - 0x0FFF)
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 53 of file gd32f3x0_fwdgt.c.

54 {
55 uint32_t time_index = FWDGT_WND_TIMEOUT;
56 uint32_t flag_status = RESET;
57
58 /* enable write access to FWDGT_WND */
59 FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
60
61 /* wait until the WUD flag to be reset */
62 do{
63 flag_status = FWDGT_STAT & FWDGT_STAT_WUD;
64 }while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
65
66 if ((uint32_t)RESET != flag_status){
67 return ERROR;
68 }
69
70 FWDGT_WND = WND_WND(window_value);
71
72 return SUCCESS;
73 }
FWDGT_WND
#define FWDGT_WND
Definition: gd32f3x0_fwdgt.h:25
FWDGT_WRITEACCESS_ENABLE
#define FWDGT_WRITEACCESS_ENABLE
Definition: gd32f3x0_fwdgt.h:66
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f3x0_fwdgt.h:21
WND_WND
#define WND_WND(regval)
Definition: gd32f3x0_fwdgt.h:63
FWDGT_STAT_WUD
#define FWDGT_STAT_WUD
Definition: gd32f3x0_fwdgt.h:40
FWDGT_STAT
#define FWDGT_STAT
Definition: gd32f3x0_fwdgt.h:24
FWDGT_WND_TIMEOUT
#define FWDGT_WND_TIMEOUT
Definition: gd32f3x0_fwdgt.h:72
void fwdgt_write_disable ( void )

disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_fwdgt.c.

21 {
22 FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
23 }
FWDGT_WRITEACCESS_DISABLE
#define FWDGT_WRITEACCESS_DISABLE
Definition: gd32f3x0_fwdgt.h:67
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f3x0_fwdgt.h:21
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_gpio.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_gpio.c File Reference

GPIO driver. More...

#include "gd32f3x0_gpio.h"

Go to the source code of this file.

Functions

void | gpio_deinit (uint32_t gpio_periph)
reset GPIO port More...
void | gpio_mode_set (uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin)
set GPIO output mode More...
void | gpio_output_options_set (uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin)
set GPIO output type and speed More...
void | gpio_bit_set (uint32_t gpio_periph, uint32_t pin)
set GPIO pin bit More...
void | gpio_bit_reset (uint32_t gpio_periph, uint32_t pin)
reset GPIO pin bit More...
void | gpio_bit_write (uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
write data to the specified GPIO pin More...
void | gpio_port_write (uint32_t gpio_periph, uint16_t data)
write data to the specified GPIO port More...
FlagStatus | gpio_input_bit_get (uint32_t gpio_periph, uint32_t pin)
get GPIO pin input status More...
uint16_t | gpio_input_port_get (uint32_t gpio_periph)
get GPIO all pins input status More...
FlagStatus | gpio_output_bit_get (uint32_t gpio_periph, uint32_t pin)
get GPIO pin output status More...
uint16_t | gpio_output_port_get (uint32_t gpio_periph)
get GPIO all pins output status More...
void | gpio_af_set (uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin)
set GPIO alternate function More...
void | gpio_pin_lock (uint32_t gpio_periph, uint32_t pin)
lock GPIO pin bit More...
void | gpio_bit_toggle (uint32_t gpio_periph, uint32_t pin)
toggle GPIO pin status More...
void | gpio_port_toggle (uint32_t gpio_periph)
toggle GPIO port status More...

Detailed Description

GPIO driver.

Definition in file gd32f3x0_gpio.c.

Function Documentation

void gpio_af_set | ( | uint32_t | gpio_periph,
 |  | uint32_t | alt_func_num,
 |  | uint32_t | pin
 | ) |  |

set GPIO alternate function

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C)
[in] alt_func_num GPIO pin af function, please refer to specific device datasheet
  • GPIO_AF_0: TIMER2, TIMER13, TIMER14, TIMER16, SPI0, SPI1, I2S0, CK_OUT, USART0, CEC, IFRP, TSI, CTC, I2C0, I2C1, SWDIO, SWCLK
  • GPIO_AF_1: USART0, USART1, TIMER2, TIMER14, I2C0, I2C1, IFRP, CEC
  • GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, I2S0
  • GPIO_AF_3: TSI, I2C0, TIMER14
  • GPIO_AF_4(port A,B only): USART1, I2C0, I2C1, TIMER13
  • GPIO_AF_5(port A,B only): TIMER15, TIMER16, USBFS, I2S0
  • GPIO_AF_6(port A,B only): CTC, SPI1
  • GPIO_AF_7(port A,B only): CMP0, CMP1
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 276 of file gd32f3x0_gpio.c.

277 {
278 uint16_t i;
279 uint32_t afrl, afrh;
280
281 afrl = GPIO_AFSEL0(gpio_periph);
282 afrh = GPIO_AFSEL1(gpio_periph);
283
284 for(i = 0U;i < 8U;i++){
285 if((1U << i) & pin){
286 /* clear the specified pin alternate function bits */
287 afrl &= ~GPIO_AFR_MASK(i);
288 afrl |= GPIO_AFR_SET(i,alt_func_num);
289 }
290 }
291
292 for(i = 8U;i < 16U;i++){
293 if((1U << i) & pin){
294 /* clear the specified pin alternate function bits */
295 afrh &= ~GPIO_AFR_MASK(i - 8U);
296 afrh |= GPIO_AFR_SET(i - 8U,alt_func_num);
297 }
298 }
299
300 GPIO_AFSEL0(gpio_periph) = afrl;
301 GPIO_AFSEL1(gpio_periph) = afrh;
302 }
GPIO_AFR_MASK
#define GPIO_AFR_MASK(n)
Definition: gd32f3x0_gpio.h:335
GPIO_AFR_SET
#define GPIO_AFR_SET(n, af)
Definition: gd32f3x0_gpio.h:334
GPIO_AFSEL0
#define GPIO_AFSEL0(gpiox)
Definition: gd32f3x0_gpio.h:33
GPIO_AFSEL1
#define GPIO_AFSEL1(gpiox)
Definition: gd32f3x0_gpio.h:34
void gpio_bit_reset | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

reset GPIO pin bit

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 169 of file gd32f3x0_gpio.c.

170 {
171 GPIO_BC(gpio_periph) = (uint32_t)pin;
172 }
GPIO_BC
#define GPIO_BC(gpiox)
Definition: gd32f3x0_gpio.h:35
void gpio_bit_set | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

set GPIO pin bit

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 157 of file gd32f3x0_gpio.c.

158 {
159 GPIO_BOP(gpio_periph) = (uint32_t)pin;
160 }
GPIO_BOP
#define GPIO_BOP(gpiox)
Definition: gd32f3x0_gpio.h:31
void gpio_bit_toggle | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

toggle GPIO pin status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 331 of file gd32f3x0_gpio.c.

332 {
333 GPIO_TG(gpio_periph) = (uint32_t)pin;
334 }
GPIO_TG
#define GPIO_TG(gpiox)
Definition: gd32f3x0_gpio.h:36
void gpio_bit_write | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin,
 |  | bit_status | bit_value
 | ) |  |

write data to the specified GPIO pin

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[in] bit_value SET or RESET
  • RESET: clear the port pin
  • SET: set the port pin
[out] | none
Return values
none

Definition at line 184 of file gd32f3x0_gpio.c.

185 {
186 if(RESET != bit_value){
187 GPIO_BOP(gpio_periph) = (uint32_t)pin;
188 }else{
189 GPIO_BC(gpio_periph) = (uint32_t)pin;
190 }
191 }
GPIO_BC
#define GPIO_BC(gpiox)
Definition: gd32f3x0_gpio.h:35
GPIO_BOP
#define GPIO_BOP(gpiox)
Definition: gd32f3x0_gpio.h:31
void gpio_deinit ( uint32_t gpio_periph )

reset GPIO port

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_gpio.c.

21 {
22 switch(gpio_periph){
23 case GPIOA:
24 /* reset GPIOA */
25 rcu_periph_reset_enable(RCU_GPIOARST);
26 rcu_periph_reset_disable(RCU_GPIOARST);
27 break;
28 case GPIOB:
29 /* reset GPIOB */
30 rcu_periph_reset_enable(RCU_GPIOBRST);
31 rcu_periph_reset_disable(RCU_GPIOBRST);
32 break;
33 case GPIOC:
34 /* reset GPIOC */
35 rcu_periph_reset_enable(RCU_GPIOCRST);
36 rcu_periph_reset_disable(RCU_GPIOCRST);
37 break;
38 case GPIOD:
39 /* reset GPIOD */
40 rcu_periph_reset_enable(RCU_GPIODRST);
41 rcu_periph_reset_disable(RCU_GPIODRST);
42 break;
43 case GPIOF:
44 /* reset GPIOF */
45 rcu_periph_reset_enable(RCU_GPIOFRST);
46 rcu_periph_reset_disable(RCU_GPIOFRST);
47 break;
48 default:
49 break;
50 }
51 }
RCU_GPIOCRST
Definition: gd32f3x0_rcu.h:328
GPIOB
#define GPIOB
Definition: gd32f3x0_gpio.h:19
RCU_GPIOBRST
Definition: gd32f3x0_rcu.h:327
GPIOF
#define GPIOF
Definition: gd32f3x0_gpio.h:22
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
GPIOA
#define GPIOA
Definition: gd32f3x0_gpio.h:18
GPIOC
#define GPIOC
Definition: gd32f3x0_gpio.h:20
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
GPIOD
#define GPIOD
Definition: gd32f3x0_gpio.h:21
RCU_GPIOARST
Definition: gd32f3x0_rcu.h:326
RCU_GPIODRST
Definition: gd32f3x0_rcu.h:329
RCU_GPIOFRST
Definition: gd32f3x0_rcu.h:330
FlagStatus gpio_input_bit_get | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

get GPIO pin input status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
SET or RESET

Definition at line 212 of file gd32f3x0_gpio.c.

213 {
214 if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){
215 return SET;
216 }else{
217 return RESET;
218 }
219 }
GPIO_ISTAT
#define GPIO_ISTAT(gpiox)
Definition: gd32f3x0_gpio.h:29
uint16_t gpio_input_port_get ( uint32_t gpio_periph )

get GPIO all pins input status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[out] | none
Return values
state of GPIO all pins

Definition at line 227 of file gd32f3x0_gpio.c.

228 {
229 return (uint16_t)GPIO_ISTAT(gpio_periph);
230 }
GPIO_ISTAT
#define GPIO_ISTAT(gpiox)
Definition: gd32f3x0_gpio.h:29
void gpio_mode_set | ( | uint32_t | gpio_periph,
 |  | uint32_t | mode,
 |  | uint32_t | pull_up_down,
 |  | uint32_t | pin
 | ) |  |

set GPIO output mode

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] mode gpio pin mode
  • GPIO_MODE_INPUT: input mode
  • GPIO_MODE_OUTPUT: output mode
  • GPIO_MODE_AF: alternate function mode
  • GPIO_MODE_ANALOG: analog mode
[in] pull_up_down gpio pin with pull-up or pull-down resistor
  • GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors
  • GPIO_PUPD_PULLUP: with pull-up resistor
  • GPIO_PUPD_PULLDOWN:with pull-down resistor
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 69 of file gd32f3x0_gpio.c.

70 {
71 uint16_t i;
72 uint32_t ctl, pupd;
73
74 ctl = GPIO_CTL(gpio_periph);
75 pupd = GPIO_PUD(gpio_periph);
76
77 for(i = 0U;i < 16U;i++){
78 if((1U << i) & pin){
79 /* clear the specified pin mode bits */
80 ctl &= ~GPIO_MODE_MASK(i);
81 /* set the specified pin mode bits */
82 ctl |= GPIO_MODE_SET(i, mode);
83
84 /* clear the specified pin pupd bits */
85 pupd &= ~GPIO_PUPD_MASK(i);
86 /* set the specified pin pupd bits */
87 pupd |= GPIO_PUPD_SET(i, pull_up_down);
88 }
89 }
90
91 GPIO_CTL(gpio_periph) = ctl;
92 GPIO_PUD(gpio_periph) = pupd;
93 }
GPIO_PUD
#define GPIO_PUD(gpiox)
Definition: gd32f3x0_gpio.h:28
GPIO_PUPD_SET
#define GPIO_PUPD_SET(n, pupd)
Definition: gd32f3x0_gpio.h:315
GPIO_PUPD_MASK
#define GPIO_PUPD_MASK(n)
Definition: gd32f3x0_gpio.h:316
GPIO_CTL
#define GPIO_CTL(gpiox)
Definition: gd32f3x0_gpio.h:25
GPIO_MODE_MASK
#define GPIO_MODE_MASK(n)
Definition: gd32f3x0_gpio.h:312
GPIO_MODE_SET
#define GPIO_MODE_SET(n, mode)
Definition: gd32f3x0_gpio.h:311
FlagStatus gpio_output_bit_get | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

get GPIO pin output status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
SET or RESET

Definition at line 239 of file gd32f3x0_gpio.c.

240 {
241 if((uint32_t)RESET != (GPIO_OCTL(gpio_periph)&(pin))){
242 return SET;
243 }else{
244 return RESET;
245 }
246 }
GPIO_OCTL
#define GPIO_OCTL(gpiox)
Definition: gd32f3x0_gpio.h:30
void gpio_output_options_set | ( | uint32_t | gpio_periph,
 |  | uint8_t | otype,
 |  | uint32_t | speed,
 |  | uint32_t | pin
 | ) |  |

set GPIO output type and speed

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] otype gpio pin output mode
  • GPIO_OTYPE_PP: push pull mode
  • GPIO_OTYPE_OD: open drain mode
[in] speed gpio pin output max speed
  • GPIO_OSPEED_2MHZ: output max speed 2MHz
  • GPIO_OSPEED_10MHZ: output max speed 10MHz
  • GPIO_OSPEED_50MHZ: output max speed 50MHz
  • GPIO_OSPEED_MAX: GPIO very high output speed, max speed more than 50MHz
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 110 of file gd32f3x0_gpio.c.

111 {
112 uint16_t i;
113 uint32_t ospeed0,ospeed1;
114
115 if(GPIO_OTYPE_OD == otype){
116 GPIO_OMODE(gpio_periph) |= (uint32_t)pin;
117 }else{
118 GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin);
119 }
120
121 /* get the specified pin output speed bits value */
122 ospeed0 = GPIO_OSPD0(gpio_periph);
123
124 if(GPIO_OSPEED_MAX == speed){
125 ospeed1 = GPIO_OSPD1(gpio_periph);
126
127 for(i = 0U;i < 16U;i++){
128 if((1U << i) & pin){
129 /* enable very high output speed function of the pin when the corresponding OSPDy(y=0..15)
130 is "11" (output max speed 50MHz) */
131 ospeed0 |= GPIO_OSPEED_SET(i,0x03);
132 ospeed1 |= (1U << i);
133 }
134 }
135 GPIO_OSPD0(gpio_periph) = ospeed0;
136 GPIO_OSPD1(gpio_periph) = ospeed1;
137 }else{
138 for(i = 0U;i < 16U;i++){
139 if((1U << i) & pin){
140 /* clear the specified pin output speed bits */
141 ospeed0 &= ~GPIO_OSPEED_MASK(i);
142 /* set the specified pin output speed bits */
143 ospeed0 |= GPIO_OSPEED_SET(i,speed);
144 }
145 }
146 GPIO_OSPD0(gpio_periph) = ospeed0;
147 }
148 }
GPIO_OSPEED_MAX
#define GPIO_OSPEED_MAX
Definition: gd32f3x0_gpio.h:331
GPIO_OSPEED_SET
#define GPIO_OSPEED_SET(n, speed)
Definition: gd32f3x0_gpio.h:319
GPIO_OSPEED_MASK
#define GPIO_OSPEED_MASK(n)
Definition: gd32f3x0_gpio.h:320
GPIO_OMODE
#define GPIO_OMODE(gpiox)
Definition: gd32f3x0_gpio.h:26
GPIO_OTYPE_OD
#define GPIO_OTYPE_OD
Definition: gd32f3x0_gpio.h:324
GPIO_OSPD0
#define GPIO_OSPD0(gpiox)
Definition: gd32f3x0_gpio.h:27
GPIO_OSPD1
#define GPIO_OSPD1(gpiox)
Definition: gd32f3x0_gpio.h:37
uint16_t gpio_output_port_get ( uint32_t gpio_periph )

get GPIO all pins output status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[out] | none
Return values
state of GPIO all pins

Definition at line 254 of file gd32f3x0_gpio.c.

255 {
256 return (uint16_t)GPIO_OCTL(gpio_periph);
257 }
GPIO_OCTL
#define GPIO_OCTL(gpiox)
Definition: gd32f3x0_gpio.h:30
void gpio_pin_lock | ( | uint32_t | gpio_periph,
 |  | uint32_t | pin
 | ) |  |

lock GPIO pin bit

Parameters
[in] | gpio_periph | GPIOx(x = A,B)
[in] | pin | GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
[out] | none
Return values
none

Definition at line 311 of file gd32f3x0_gpio.c.

312 {
313 uint32_t lock = 0x00010000U;
314 lock |= pin;
315
316 /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */
317 GPIO_LOCK(gpio_periph) = (uint32_t)lock;
318 GPIO_LOCK(gpio_periph) = (uint32_t)pin;
319 GPIO_LOCK(gpio_periph) = (uint32_t)lock;
320 lock = GPIO_LOCK(gpio_periph);
321 lock = GPIO_LOCK(gpio_periph);
322 }
GPIO_LOCK
#define GPIO_LOCK(gpiox)
Definition: gd32f3x0_gpio.h:32
void gpio_port_toggle ( uint32_t gpio_periph )

toggle GPIO port status

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[out] | none
Return values
none

Definition at line 342 of file gd32f3x0_gpio.c.

343 {
344 GPIO_TG(gpio_periph) = 0x0000FFFFU;
345 }
GPIO_TG
#define GPIO_TG(gpiox)
Definition: gd32f3x0_gpio.h:36
void gpio_port_write | ( | uint32_t | gpio_periph,
 |  | uint16_t | data
 | ) |  |

write data to the specified GPIO port

Parameters
[in] | gpio_periph | GPIOx(x = A,B,C,D,F)
[in] | data | specify the value to be written to the port output control register
[out] | none
Return values
none

Definition at line 200 of file gd32f3x0_gpio.c.

201 {
202 GPIO_OCTL(gpio_periph) = (uint32_t)data;
203 }
GPIO_OCTL
#define GPIO_OCTL(gpiox)
Definition: gd32f3x0_gpio.h:30
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_i2c.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Macros | Functions
gd32f3x0_i2c.c File Reference

I2C driver. More...

#include "gd32f3x0_i2c.h"

Go to the source code of this file.

Macros

#define | I2CCLK_MAX 0x7fU
#define | I2C_FLAG_MASK 0x0000FFFFU

Functions

void | i2c_deinit (uint32_t i2c_periph)
reset I2C More...
void | i2c_clock_config (uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
configure I2C clock More...
void | i2c_mode_addr_config (uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
configure I2C address More...
void | i2c_smbus_type_config (uint32_t i2c_periph, uint32_t type)
SMBus type selection. More...
void | i2c_ack_config (uint32_t i2c_periph, uint32_t ack)
whether or not to send an ACK More...
void | i2c_ackpos_config (uint32_t i2c_periph, uint32_t pos)
I2C POAP position configure. More...
void | i2c_master_addressing (uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
master send slave address More...
void | i2c_dualaddr_enable (uint32_t i2c_periph, uint32_t dualaddr)
dual-address mode switch More...
void | i2c_enable (uint32_t i2c_periph)
enable I2C More...
void | i2c_disable (uint32_t i2c_periph)
disable I2C More...
void | i2c_start_on_bus (uint32_t i2c_periph)
generate a START condition on I2C bus More...
void | i2c_stop_on_bus (uint32_t i2c_periph)
generate a STOP condition on I2C bus More...
void | i2c_data_transmit (uint32_t i2c_periph, uint8_t data)
I2C transmit data function. More...
uint8_t | i2c_data_receive (uint32_t i2c_periph)
I2C receive data function. More...
void | i2c_dma_enable (uint32_t i2c_periph, uint32_t dmastate)
enable I2C DMA mode More...
void | i2c_dma_last_transfer_enable (uint32_t i2c_periph, uint32_t dmalast)
flag indicating DMA last transfer More...
void | i2c_stretch_scl_low_config (uint32_t i2c_periph, uint32_t stretchpara)
whether to stretch SCL low when data is not ready in slave mode More...
void | i2c_slave_response_to_gcall_config (uint32_t i2c_periph, uint32_t gcallpara)
whether or not to response to a general call More...
void | i2c_software_reset_config (uint32_t i2c_periph, uint32_t sreset)
software reset I2C More...
FlagStatus | i2c_flag_get (uint32_t i2c_periph, uint32_t flag)
check I2C flag is set or not More...
void | i2c_flag_clear (uint32_t i2c_periph, uint32_t flag)
clear I2C flag More...
void | i2c_interrupt_enable (uint32_t i2c_periph, uint32_t inttype)
enable I2C interrupt More...
void | i2c_interrupt_disable (uint32_t i2c_periph, uint32_t inttype)
disable I2C interrupt More...
FlagStatus | i2c_interrupt_flag_get (uint32_t i2c_periph, uint32_t intflag)
check I2C interrupt flag More...
void | i2c_interrupt_flag_clear (uint32_t i2c_periph, uint32_t intflag)
clear I2C interrupt flag More...
void | i2c_pec_enable (uint32_t i2c_periph, uint32_t pecstate)
I2C PEC calculation on or off. More...
void | i2c_pec_transfer_enable (uint32_t i2c_periph, uint32_t pecpara)
I2C whether to transfer PEC value. More...
uint8_t | i2c_pec_value_get (uint32_t i2c_periph)
get packet error checking value More...
void | i2c_smbus_issue_alert (uint32_t i2c_periph, uint32_t smbuspara)
I2C issue alert through SMBA pin. More...
void | i2c_smbus_arp_enable (uint32_t i2c_periph, uint32_t arpstate)
enable or disable I2C ARP protocol in SMBus switch More...

Detailed Description

I2C driver.

Definition in file gd32f3x0_i2c.c.

Macro Definition Documentation

#define I2C_FLAG_MASK 0x0000FFFFU

i2c flag mask

Definition at line 16 of file gd32f3x0_i2c.c.

#define I2CCLK_MAX 0x7fU

i2cclk max value

Definition at line 15 of file gd32f3x0_i2c.c.

Function Documentation

void i2c_ack_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | ack
 | ) |  |

whether or not to send an ACK

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] ack
  • I2C_ACK_ENABLE: ACK will be sent
  • I2C_ACK_DISABLE: ACK will not be sent
[out] | none
Return values
none

Definition at line 180 of file gd32f3x0_i2c.c.

181 {
182 if(I2C_ACK_ENABLE == ack){
183 I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
184 }else{
185 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN);
186 }
187 }
I2C_ACK_ENABLE
#define I2C_ACK_ENABLE
Definition: gd32f3x0_i2c.h:125
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
I2C_CTL0_ACKEN
#define I2C_CTL0_ACKEN
Definition: gd32f3x0_i2c.h:46
void i2c_ackpos_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | pos
 | ) |  |

I2C POAP position configure.

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] pos
  • I2C_ACKPOS_CURRENT: whether to send ACK or not for the current
  • I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte
[out] | none
Return values
none

Definition at line 198 of file gd32f3x0_i2c.c.

199 {
200 /* configure I2C POAP position */
201 if(I2C_ACKPOS_NEXT == pos){
202 I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
203 }else{
204 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP);
205 }
206 }
I2C_CTL0_POAP
#define I2C_CTL0_POAP
Definition: gd32f3x0_i2c.h:47
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
I2C_ACKPOS_NEXT
#define I2C_ACKPOS_NEXT
Definition: gd32f3x0_i2c.h:128
void i2c_clock_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | clkspeed,
 |  | uint32_t | dutycyc
 | ) |  |

configure I2C clock

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] | clkspeed | I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) and fast mode plus (up to 1MHz)
[in] dutycyc duty cycle in fast mode or fast mode plus
  • I2C_DTCY_2: T_low/T_high=2
  • I2C_DTCY_16_9: T_low/T_high=16/9
[out] | none
Return values
none

Definition at line 58 of file gd32f3x0_i2c.c.

59 {
60 uint32_t pclk1,clkc,freq,risetime;
61 uint32_t temp;
62
63 pclk1 = rcu_clock_freq_get(CK_APB1);
64 /* I2C peripheral clock frequency */
65 freq = (uint32_t)(pclk1/1000000U);
66 if(freq >= I2CCLK_MAX){
67 freq = I2CCLK_MAX;
68 }
69 temp = I2C_CTL1(i2c_periph);
70 temp &= ~I2C_CTL1_I2CCLK;
71 temp |= freq;
72
73 I2C_CTL1(i2c_periph) = temp;
74
75 if(100000U >= clkspeed){
76 /* the maximum SCL rise time is 1000ns in standard mode */
77 risetime = (uint32_t)((pclk1/1000000U)+1U);
78 if(risetime >= I2CCLK_MAX){
79 I2C_RT(i2c_periph) = I2CCLK_MAX;
80 }else{
81 I2C_RT(i2c_periph) = risetime;
82 }
83 clkc = (uint32_t)(pclk1/(clkspeed*2U));
84 if(clkc < 0x04U){
85 /* the CLKC in standard mode minmum value is 4 */
86 clkc = 0x04U;
87 }
88 I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc);
89
90 }else if(400000U >= clkspeed){
91 /* the maximum SCL rise time is 300ns in fast mode */
92 I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U);
93 if(I2C_DTCY_2 == dutycyc){
94 /* I2C duty cycle is 2 */
95 clkc = (uint32_t)(pclk1/(clkspeed*3U));
96 I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
97 }else{
98 /* I2C duty cycle is 16/9 */
99 clkc = (uint32_t)(pclk1/(clkspeed*25U));
100 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
101 }
102 if(0U == (clkc & I2C_CKCFG_CLKC)){
103 /* the CLKC in fast mode minmum value is 1 */
104 clkc |= 0x0001U;
105 }
106 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
107 I2C_CKCFG(i2c_periph) |= clkc;
108 }else{
109 /* fast mode plus, the maximum SCL rise time is 120ns */
110 I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)120U)/(uint32_t)1000U)+(uint32_t)1U);
111 if(I2C_DTCY_2 == dutycyc){
112 /* I2C duty cycle is 2 */
113 clkc = (uint32_t)(pclk1/(clkspeed*3U));
114 I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
115 }else{
116 /* I2C duty cycle is 16/9 */
117 clkc = (uint32_t)(pclk1/(clkspeed*25U));
118 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
119 }
120 /* enable fast mode */
121 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
122 I2C_CKCFG(i2c_periph) |= clkc;
123 /* enable I2C fast mode plus */
124 I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN;
125 }
126 }
CK_APB1
Definition: gd32f3x0_rcu.h:456
I2C_FMPCFG
#define I2C_FMPCFG(i2cx)
Definition: gd32f3x0_i2c.h:33
I2C_FMPCFG_FMPEN
#define I2C_FMPCFG_FMPEN
Definition: gd32f3x0_i2c.h:108
I2C_CKCFG_CLKC
#define I2C_CKCFG_CLKC
Definition: gd32f3x0_i2c.h:100
I2C_CKCFG_FAST
#define I2C_CKCFG_FAST
Definition: gd32f3x0_i2c.h:102
I2C_CKCFG
#define I2C_CKCFG(i2cx)
Definition: gd32f3x0_i2c.h:31
I2CCLK_MAX
#define I2CCLK_MAX
Definition: gd32f3x0_i2c.c:15
I2C_CKCFG_DTCY
#define I2C_CKCFG_DTCY
Definition: gd32f3x0_i2c.h:101
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f3x0_i2c.h:25
I2C_RT
#define I2C_RT(i2cx)
Definition: gd32f3x0_i2c.h:32
I2C_DTCY_2
#define I2C_DTCY_2
Definition: gd32f3x0_i2c.h:230
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f3x0_rcu.c:964
I2C_CTL1_I2CCLK
#define I2C_CTL1_I2CCLK
Definition: gd32f3x0_i2c.h:53
uint8_t i2c_data_receive ( uint32_t i2c_periph )

I2C receive data function.

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[out] | none
Return values
data of received

Definition at line 308 of file gd32f3x0_i2c.c.

309 {
310 return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph));
311 }
DATA_RECV
#define DATA_RECV(regval)
Definition: gd32f3x0_i2c.h:182
I2C_DATA
#define I2C_DATA(i2cx)
Definition: gd32f3x0_i2c.h:28
void i2c_data_transmit | ( | uint32_t | i2c_periph,
 |  | uint8_t | data
 | ) |  |

I2C transmit data function.

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] | data | data of transmission
[out] | none
Return values
none

Definition at line 297 of file gd32f3x0_i2c.c.

298 {
299 I2C_DATA(i2c_periph) = DATA_TRANS(data);
300 }
DATA_TRANS
#define DATA_TRANS(regval)
Definition: gd32f3x0_i2c.h:179
I2C_DATA
#define I2C_DATA(i2cx)
Definition: gd32f3x0_i2c.h:28
void i2c_deinit ( uint32_t i2c_periph )

reset I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[out] | none
Return values
none

Definition at line 24 of file gd32f3x0_i2c.c.

25 {
26 switch(i2c_periph){
27 case I2C0:
28 /* reset I2C0 */
29 rcu_periph_reset_enable(RCU_I2C0RST);
30 rcu_periph_reset_disable(RCU_I2C0RST);
31 break;
32 case I2C1:
33 /* reset I2C1 */
34 rcu_periph_reset_enable(RCU_I2C1RST);
35 rcu_periph_reset_disable(RCU_I2C1RST);
36 break;
37 case I2C2:
38 /* reset I2C2 */
39 rcu_periph_reset_enable(RCU_I2C2RST);
40 rcu_periph_reset_disable(RCU_I2C2RST);
41 break;
42 default:
43 break;
44 }
45 }
RCU_I2C1RST
Definition: gd32f3x0_rcu.h:352
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
I2C1
#define I2C1
Definition: gd32f3x0_i2c.h:20
RCU_I2C0RST
Definition: gd32f3x0_rcu.h:351
I2C2
#define I2C2
Definition: gd32f3x0_i2c.h:21
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
RCU_I2C2RST
Definition: gd32f3x0_rcu.h:361
I2C0
#define I2C0
Definition: gd32f3x0_i2c.h:19
void i2c_disable ( uint32_t i2c_periph )

disable I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[out] | none
Return values
none

Definition at line 263 of file gd32f3x0_i2c.c.

264 {
265 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN);
266 }
I2C_CTL0_I2CEN
#define I2C_CTL0_I2CEN
Definition: gd32f3x0_i2c.h:37
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_dma_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | dmastate
 | ) |  |

enable I2C DMA mode

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] dmastate
  • I2C_DMA_ON: DMA mode enable
  • I2C_DMA_OFF: DMA mode disable
[out] | none
Return values
none

Definition at line 322 of file gd32f3x0_i2c.c.

323 {
324 /* configure I2C DMA function */
325 uint32_t ctl = 0U;
326 ctl = I2C_CTL1(i2c_periph);
327 ctl &= ~(I2C_CTL1_DMAON);
328 ctl |= dmastate;
329 I2C_CTL1(i2c_periph) = ctl;
330 }
I2C_CTL1_DMAON
#define I2C_CTL1_DMAON
Definition: gd32f3x0_i2c.h:57
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f3x0_i2c.h:25
void i2c_dma_last_transfer_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | dmalast
 | ) |  |

flag indicating DMA last transfer

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] dmalast
  • I2C_DMALST_ON: next DMA EOT is the last transfer
  • I2C_DMALST_OFF: next DMA EOT is not the last transfer
[out] | none
Return values
none

Definition at line 341 of file gd32f3x0_i2c.c.

342 {
343 /* configure DMA last transfer */
344 uint32_t ctl = 0U;
345 ctl = I2C_CTL1(i2c_periph);
346 ctl &= ~(I2C_CTL1_DMALST);
347 ctl |= dmalast;
348 I2C_CTL1(i2c_periph) = ctl;
349 }
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f3x0_i2c.h:25
I2C_CTL1_DMALST
#define I2C_CTL1_DMALST
Definition: gd32f3x0_i2c.h:58
void i2c_dualaddr_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | dualaddr
 | ) |  |

dual-address mode switch

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] dualaddr
  • I2C_DUADEN_DISABLE: disable dual-address mode
  • I2C_DUADEN_ENABLE: enable dual-address mode
[out] | none
Return values
none

Definition at line 237 of file gd32f3x0_i2c.c.

238 {
239 if(I2C_DUADEN_ENABLE == dualaddr){
240 I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN;
241 }else{
242 I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
243 }
244 }
I2C_SADDR1
#define I2C_SADDR1(i2cx)
Definition: gd32f3x0_i2c.h:27
I2C_DUADEN_ENABLE
#define I2C_DUADEN_ENABLE
Definition: gd32f3x0_i2c.h:133
I2C_SADDR1_DUADEN
#define I2C_SADDR1_DUADEN
Definition: gd32f3x0_i2c.h:67
void i2c_enable ( uint32_t i2c_periph )

enable I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[out] | none
Return values
none

Definition at line 252 of file gd32f3x0_i2c.c.

253 {
254 I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN;
255 }
I2C_CTL0_I2CEN
#define I2C_CTL0_I2CEN
Definition: gd32f3x0_i2c.h:37
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_flag_clear | ( | uint32_t | i2c_periph,
 |  | uint32_t | flag
 | ) |  |

clear I2C flag

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] flag flag type
  • I2C_FLAG_SMBALT: SMBus Alert status
  • I2C_FLAG_SMBTO: timeout signal in SMBus mode
  • I2C_FLAG_PECERR: PEC error when receiving data
  • I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode
  • I2C_FLAG_AERR: acknowledge error
  • I2C_FLAG_LOSTARB: arbitration lost in master mode
  • I2C_FLAG_BERR: a bus error
  • I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1
[out] | none
Return values
none

Definition at line 474 of file gd32f3x0_i2c.c.

475 {
476 if(I2C_FLAG_ADDSEND == flag){
477 /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
478 I2C_STAT0(i2c_periph);
479 I2C_STAT1(i2c_periph);
480 }else{
481 I2C_STAT0(i2c_periph) &= ~(flag);
482 }
483 }
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f3x0_i2c.h:29
I2C_FLAG_ADDSEND
#define I2C_FLAG_ADDSEND
Definition: gd32f3x0_i2c.h:186
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f3x0_i2c.h:30
FlagStatus i2c_flag_get | ( | uint32_t | i2c_periph,
 |  | uint32_t | flag
 | ) |  |

check I2C flag is set or not

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] flag
  • I2C_FLAG_SBSEND: start condition send out
  • I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode
  • I2C_FLAG_BTC: byte transmission finishes
  • I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode
  • I2C_FLAG_STPDET: stop condition detected in slave mode
  • I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving
  • I2C_FLAG_TBE: I2C_DATA is empty during transmitting
  • I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
  • I2C_FLAG_LOSTARB: arbitration lost in master mode
  • I2C_FLAG_AERR: acknowledge error
  • I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode
  • I2C_FLAG_PECERR: PEC error when receiving data
  • I2C_FLAG_SMBTO: timeout signal in SMBus mode
  • I2C_FLAG_SMBALT: SMBus alert status
  • I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode
  • I2C_FLAG_I2CBSY: busy flag
  • I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver
  • I2C_FLAG_RXGC: general call address (00h) received
  • I2C_FLAG_DEFSMB: default address of SMBus device
  • I2C_FLAG_HSTSMB: SMBus host header detected in slave mode
  • I2C_FLAG_DUMODF: dual flag in slave mode indicating which address is matched in dual-address mode
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 436 of file gd32f3x0_i2c.c.

437 {
438 uint32_t reg = 0U;
439 FlagStatus reval = RESET;
440 /* get the flag in which register */
441 reg = (BIT(31) & flag);
442 if((BIT(31) == reg)){
443 if((I2C_STAT1(i2c_periph)&(flag & I2C_FLAG_MASK))){
444 reval = SET;
445 }else{
446 reval = RESET;
447 }
448 }else{
449 if((I2C_STAT0(i2c_periph)&(flag & I2C_FLAG_MASK))){
450 reval = SET;
451 }else{
452 reval = RESET;
453 }
454 }
455 /* return the flag status */
456 return reval;
457 }
I2C_FLAG_MASK
#define I2C_FLAG_MASK
Definition: gd32f3x0_i2c.c:16
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f3x0_i2c.h:29
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f3x0_i2c.h:30
void i2c_interrupt_disable | ( | uint32_t | i2c_periph,
 |  | uint32_t | inttype
 | ) |  |

disable I2C interrupt

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] inttype interrupt type
  • I2C_INT_ERR: error interrupt enable
  • I2C_INT_EV: event interrupt enable
  • I2C_INT_BUF: buffer interrupt enable
[out] | none
Return values
none

Definition at line 510 of file gd32f3x0_i2c.c.

511 {
512 I2C_CTL1(i2c_periph) &= ~(inttype);
513 }
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f3x0_i2c.h:25
void i2c_interrupt_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | inttype
 | ) |  |

enable I2C interrupt

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] inttype interrupt type
  • I2C_INT_ERR: error interrupt enable
  • I2C_INT_EV: event interrupt enable
  • I2C_INT_BUF: buffer interrupt enable
[out] | none
Return values
none

Definition at line 495 of file gd32f3x0_i2c.c.

496 {
497 I2C_CTL1(i2c_periph) |= (inttype);
498 }
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f3x0_i2c.h:25
void i2c_interrupt_flag_clear | ( | uint32_t | i2c_periph,
 |  | uint32_t | intflag
 | ) |  |

clear I2C interrupt flag

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] intflag interrupt flag
  • I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
  • I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
  • I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
  • I2C_INT_FLAG_AERR: acknowledge error interrupt flag
  • I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
  • I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
  • I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
  • I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
[out] | none
Return values
none

Definition at line 592 of file gd32f3x0_i2c.c.

593 {
594 if(I2C_INT_FLAG_ADDSEND == intflag){
595 /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
596 I2C_STAT0(i2c_periph);
597 I2C_STAT1(i2c_periph);
598 }else{
599 I2C_STAT0(i2c_periph) &= ~(intflag);
600 }
601 }
I2C_INT_FLAG_ADDSEND
#define I2C_INT_FLAG_ADDSEND
Definition: gd32f3x0_i2c.h:209
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f3x0_i2c.h:29
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f3x0_i2c.h:30
FlagStatus i2c_interrupt_flag_get | ( | uint32_t | i2c_periph,
 |  | uint32_t | intflag
 | ) |  |

check I2C interrupt flag

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] int_flag interrupt flag
  • I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag
  • I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
  • I2C_INT_FLAG_BTC: byte transmission finishes
  • I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag
  • I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag
  • I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag
  • I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag
  • I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
  • I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
  • I2C_INT_FLAG_AERR: acknowledge error interrupt flag
  • I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
  • I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
  • I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
  • I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
[out] | none
Return values
none

Definition at line 536 of file gd32f3x0_i2c.c.

537 {
538 uint32_t evie, errie, bufie;
539
540 evie = I2C_CTL1(i2c_periph)&I2C_CTL1_EVIE;
541 errie = I2C_CTL1(i2c_periph)&I2C_CTL1_ERRIE;
542 /* check I2C event interrupt enable bit */
543 if((intflag&0x00ffU) && evie){
544 if(intflag&0x001fU){
545 /* check I2C event flags except TBE and RBNE */
546 if(intflag & I2C_STAT0(i2c_periph)){
547 return SET;
548 }else{
549 return RESET;
550 }
551 }else{
552 /* check I2C event flags TBE and RBNE */
553 bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;
554 if(bufie){
555 if(intflag & I2C_STAT0(i2c_periph)){
556 return SET;
557 }else{
558 return RESET;
559 }
560 }else{
561 return RESET;
562 }
563 }
564 /* check I2C error interrupt enable bit */
565 }else if((intflag&0xff00U) && errie){
566 /* check I2C error flags */
567 if(intflag & I2C_STAT0(i2c_periph)){
568 return SET;
569 }else{
570 return RESET;
571 }
572 }else{
573 return RESET;
574 }
575 }
I2C_CTL1_ERRIE
#define I2C_CTL1_ERRIE
Definition: gd32f3x0_i2c.h:54
I2C_CTL1_BUFIE
#define I2C_CTL1_BUFIE
Definition: gd32f3x0_i2c.h:56
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f3x0_i2c.h:25
I2C_CTL1_EVIE
#define I2C_CTL1_EVIE
Definition: gd32f3x0_i2c.h:55
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f3x0_i2c.h:29
void i2c_master_addressing | ( | uint32_t | i2c_periph,
 |  | uint32_t | addr,
 |  | uint32_t | trandirection
 | ) |  |

master send slave address

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] | addr | slave address
[in] trandirection transmitter or receiver
  • I2C_TRANSMITTER: transmitter
  • I2C_RECEIVER: receiver
[out] | none
Return values
none

Definition at line 218 of file gd32f3x0_i2c.c.

219 {
220 if(I2C_TRANSMITTER == trandirection){
221 addr = addr & I2C_TRANSMITTER;
222 }else{
223 addr = addr | I2C_RECEIVER;
224 }
225 I2C_DATA(i2c_periph) = addr;
226 }
I2C_RECEIVER
#define I2C_RECEIVER
Definition: gd32f3x0_i2c.h:120
I2C_TRANSMITTER
#define I2C_TRANSMITTER
Definition: gd32f3x0_i2c.h:121
I2C_DATA
#define I2C_DATA(i2cx)
Definition: gd32f3x0_i2c.h:28
void i2c_mode_addr_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | mode,
 |  | uint32_t | addformat,
 |  | uint32_t | addr
 | ) |  |

configure I2C address

Parameters
[in] | i2c_periph | I2Cx(x=0,1)
[in] mode
  • I2C_I2CMODE_ENABLE: I2C mode
  • I2C_SMBUSMODE_ENABLE: SMBus mode
[in] addformat 7bits or 10bits
  • I2C_ADDFORMAT_7BITS: 7bits
  • I2C_ADDFORMAT_10BITS: 10bits
[in] | addr | I2C address
[out] | none
Return values
none

Definition at line 141 of file gd32f3x0_i2c.c.

142 {
143 /* SMBus/I2C mode selected */
144 uint32_t ctl = 0U;
145 ctl = I2C_CTL0(i2c_periph);
146 ctl &= ~(I2C_CTL0_SMBEN);
147 ctl |= mode;
148 I2C_CTL0(i2c_periph) = ctl;
149 /* configure address */
150 I2C_SADDR0(i2c_periph) = (addformat | addr);
151 }
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
I2C_CTL0_SMBEN
#define I2C_CTL0_SMBEN
Definition: gd32f3x0_i2c.h:38
I2C_SADDR0
#define I2C_SADDR0(i2cx)
Definition: gd32f3x0_i2c.h:26
void i2c_pec_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | pecstate
 | ) |  |

I2C PEC calculation on or off.

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] pecpara
  • I2C_PEC_ENABLE: PEC calculation on
  • I2C_PEC_DISABLE: PEC calculation off
[out] | none
Return values
none

Definition at line 612 of file gd32f3x0_i2c.c.

613 {
614 /* on/off PEC calculation */
615 uint32_t ctl = 0U;
616 ctl = I2C_CTL0(i2c_periph);
617 ctl &= ~(I2C_CTL0_PECEN);
618 ctl |= pecstate;
619 I2C_CTL0(i2c_periph) = ctl;
620 }
I2C_CTL0_PECEN
#define I2C_CTL0_PECEN
Definition: gd32f3x0_i2c.h:41
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_pec_transfer_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | pecpara
 | ) |  |

I2C whether to transfer PEC value.

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] pecpara
  • I2C_PECTRANS_ENABLE: transfer PEC
  • I2C_PECTRANS_DISABLE: not transfer PEC
[out] | none
Return values
none

Definition at line 631 of file gd32f3x0_i2c.c.

632 {
633 /* whether to transfer PEC */
634 uint32_t ctl = 0U;
635 ctl = I2C_CTL0(i2c_periph);
636 ctl &= ~(I2C_CTL0_PECTRANS);
637 ctl |= pecpara;
638 I2C_CTL0(i2c_periph) = ctl;
639 }
I2C_CTL0_PECTRANS
#define I2C_CTL0_PECTRANS
Definition: gd32f3x0_i2c.h:48
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
uint8_t i2c_pec_value_get ( uint32_t i2c_periph )

get packet error checking value

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[out] | none
Return values
PEC value

Definition at line 647 of file gd32f3x0_i2c.c.

648 {
649 return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_ECV)>>8);
650 }
I2C_STAT1_ECV
#define I2C_STAT1_ECV
Definition: gd32f3x0_i2c.h:97
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f3x0_i2c.h:30
void i2c_slave_response_to_gcall_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | gcallpara
 | ) |  |

whether or not to response to a general call

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] gcallpara
  • I2C_GCEN_ENABLE: slave will response to a general call
  • I2C_GCEN_DISABLE: slave will not response to a general call
[out] | none
Return values
none

Definition at line 379 of file gd32f3x0_i2c.c.

380 {
381 /* configure slave response to a general call enable or disable */
382 uint32_t ctl = 0U;
383 ctl = I2C_CTL0(i2c_periph);
384 ctl &= ~(I2C_CTL0_GCEN);
385 ctl |= gcallpara;
386 I2C_CTL0(i2c_periph) = ctl;
387 }
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
I2C_CTL0_GCEN
#define I2C_CTL0_GCEN
Definition: gd32f3x0_i2c.h:42
void i2c_smbus_arp_enable | ( | uint32_t | i2c_periph,
 |  | uint32_t | arpstate
 | ) |  |

enable or disable I2C ARP protocol in SMBus switch

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] smbuspara
  • I2C_ARP_ENABLE: enable ARP
  • I2C_ARP_DISABLE: disable ARP
[out] | none
Return values
none

Definition at line 680 of file gd32f3x0_i2c.c.

681 {
682 /* enable or disable I2C ARP protocol*/
683 uint32_t ctl = 0U;
684 ctl = I2C_CTL0(i2c_periph);
685 ctl &= ~(I2C_CTL0_ARPEN);
686 ctl |= arpstate;
687 I2C_CTL0(i2c_periph) = ctl;
688 }
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
I2C_CTL0_ARPEN
#define I2C_CTL0_ARPEN
Definition: gd32f3x0_i2c.h:40
void i2c_smbus_issue_alert | ( | uint32_t | i2c_periph,
 |  | uint32_t | smbuspara
 | ) |  |

I2C issue alert through SMBA pin.

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] smbuspara
  • I2C_SALTSEND_ENABLE: issue alert through SMBA pin
  • I2C_SALTSEND_DISABLE: not issue alert through SMBA pin
[out] | none
Return values
none

Definition at line 661 of file gd32f3x0_i2c.c.

662 {
663 /* issue alert through SMBA pin configure*/
664 uint32_t ctl = 0U;
665 ctl = I2C_CTL0(i2c_periph);
666 ctl &= ~(I2C_CTL0_SALT);
667 ctl |= smbuspara;
668 I2C_CTL0(i2c_periph) = ctl;
669 }
I2C_CTL0_SALT
#define I2C_CTL0_SALT
Definition: gd32f3x0_i2c.h:49
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_smbus_type_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | type
 | ) |  |

SMBus type selection.

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] ack
  • I2C_SMBUS_DEVICE: device
  • I2C_SMBUS_HOST: host
[out] | none
Return values
none

Definition at line 162 of file gd32f3x0_i2c.c.

163 {
164 if(I2C_SMBUS_HOST == type){
165 I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
166 }else{
167 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL);
168 }
169 }
I2C_SMBUS_HOST
#define I2C_SMBUS_HOST
Definition: gd32f3x0_i2c.h:117
I2C_CTL0_SMBSEL
#define I2C_CTL0_SMBSEL
Definition: gd32f3x0_i2c.h:39
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_software_reset_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | sreset
 | ) |  |

software reset I2C

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] sreset
  • I2C_SRESET_SET: I2C is under reset
  • I2C_SRESET_RESET: I2C is not under reset
[out] | none
Return values
none

Definition at line 398 of file gd32f3x0_i2c.c.

399 {
400 /* modify CTL0 and configure software reset I2C state */
401 uint32_t ctl = 0U;
402 ctl = I2C_CTL0(i2c_periph);
403 ctl &= ~(I2C_CTL0_SRESET);
404 ctl |= sreset;
405 I2C_CTL0(i2c_periph) = ctl;
406 }
I2C_CTL0_SRESET
#define I2C_CTL0_SRESET
Definition: gd32f3x0_i2c.h:50
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_start_on_bus ( uint32_t i2c_periph )

generate a START condition on I2C bus

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[out] | none
Return values
none

Definition at line 274 of file gd32f3x0_i2c.c.

275 {
276 I2C_CTL0(i2c_periph) |= I2C_CTL0_START;
277 }
I2C_CTL0_START
#define I2C_CTL0_START
Definition: gd32f3x0_i2c.h:44
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_stop_on_bus ( uint32_t i2c_periph )

generate a STOP condition on I2C bus

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[out] | none
Return values
none

Definition at line 285 of file gd32f3x0_i2c.c.

286 {
287 I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP;
288 }
I2C_CTL0_STOP
#define I2C_CTL0_STOP
Definition: gd32f3x0_i2c.h:45
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
void i2c_stretch_scl_low_config | ( | uint32_t | i2c_periph,
 |  | uint32_t | stretchpara
 | ) |  |

whether to stretch SCL low when data is not ready in slave mode

Parameters
[in] | i2c_periph | I2Cx(x=0,1,2)
[in] stretchpara
  • I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled
  • I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled
[out] | none
Return values
none

Definition at line 360 of file gd32f3x0_i2c.c.

361 {
362 /* configure I2C SCL strerching enable or disable */
363 uint32_t ctl = 0U;
364 ctl = I2C_CTL0(i2c_periph);
365 ctl &= ~(I2C_CTL0_DISSTRC);
366 ctl |= stretchpara;
367 I2C_CTL0(i2c_periph) = ctl;
368 }
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
I2C_CTL0_DISSTRC
#define I2C_CTL0_DISSTRC
Definition: gd32f3x0_i2c.h:43
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_misc.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_misc.c File Reference

MISC driver. More...

#include "gd32f3x0_misc.h"

Go to the source code of this file.

Functions

void | nvic_priority_group_set (uint32_t nvic_prigroup)
set the priority group More...
void | nvic_irq_enable (uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority)
enable NVIC request More...
void | nvic_irq_disable (uint8_t nvic_irq)
disable NVIC request More...
void | nvic_vector_table_set (uint32_t nvic_vict_tab, uint32_t offset)
set the NVIC vector table base address More...
void | system_lowpower_set (uint8_t lowpower_mode)
set the state of the low power mode More...
void | system_lowpower_reset (uint8_t lowpower_mode)
reset the state of the low power mode More...
void | systick_clksource_set (uint32_t systick_clksource)
set the systick clock source More...

Detailed Description

MISC driver.

Definition in file gd32f3x0_misc.c.

Function Documentation

void nvic_irq_disable ( uint8_t nvic_irq )

disable NVIC request

Parameters
[in] | nvic_irq | the NVIC interrupt request, detailed in IRQn_Type
[out] | none
Return values
none

Definition at line 87 of file gd32f3x0_misc.c.

88 {
89 /* disable the selected IRQ.*/
90 NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F);
91 }
void nvic_irq_enable | ( | uint8_t | nvic_irq,
 |  | uint8_t | nvic_irq_pre_priority,
 |  | uint8_t | nvic_irq_sub_priority
 | ) |  |

enable NVIC request

Parameters
[in] | nvic_irq | the NVIC interrupt request, detailed in IRQn_Type
[in] | nvic_irq_pre_priority | the pre-emption priority needed to set
[in] | nvic_irq_sub_priority | the subpriority needed to set
[out] | none
Return values
none

Definition at line 39 of file gd32f3x0_misc.c.

42 {
43 uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
44
45 /* use the priority group value to get the temp_pre and the temp_sub */
46 switch ((SCB->AIRCR) & (uint32_t)0x700U) {
47 case NVIC_PRIGROUP_PRE0_SUB4:
48 temp_pre = 0U;
49 temp_sub = 0x4U;
50 break;
51 case NVIC_PRIGROUP_PRE1_SUB3:
52 temp_pre = 1U;
53 temp_sub = 0x3U;
54 break;
55 case NVIC_PRIGROUP_PRE2_SUB2:
56 temp_pre = 2U;
57 temp_sub = 0x2U;
58 break;
59 case NVIC_PRIGROUP_PRE3_SUB1:
60 temp_pre = 3U;
61 temp_sub = 0x1U;
62 break;
63 case NVIC_PRIGROUP_PRE4_SUB0:
64 temp_pre = 4U;
65 temp_sub = 0x0U;
66 break;
67 default:
68 break;
69 }
70
71 /* get the temp_priority to fill the NVIC->IP register */
72 temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
73 temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
74 temp_priority = temp_priority << 0x04U;
75 NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
76
77 /* enable the selected IRQ */
78 NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
79 }
NVIC_PRIGROUP_PRE2_SUB2
#define NVIC_PRIGROUP_PRE2_SUB2
Definition: gd32f3x0_misc.h:31
NVIC_PRIGROUP_PRE0_SUB4
#define NVIC_PRIGROUP_PRE0_SUB4
Definition: gd32f3x0_misc.h:29
NVIC_PRIGROUP_PRE4_SUB0
#define NVIC_PRIGROUP_PRE4_SUB0
Definition: gd32f3x0_misc.h:33
NVIC_PRIGROUP_PRE1_SUB3
#define NVIC_PRIGROUP_PRE1_SUB3
Definition: gd32f3x0_misc.h:30
NVIC_PRIGROUP_PRE3_SUB1
#define NVIC_PRIGROUP_PRE3_SUB1
Definition: gd32f3x0_misc.h:32
void nvic_priority_group_set ( uint32_t nvic_prigroup )

set the priority group

Parameters
[in] nvic_prigroup the NVIC priority group
  • NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
  • NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
  • NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
  • NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
  • NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
[out] none
Return values
none

Definition at line 25 of file gd32f3x0_misc.c.

26 {
27 /* set the priority group value */
28 SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
29 }
NVIC_AIRCR_VECTKEY_MASK
#define NVIC_AIRCR_VECTKEY_MASK
Definition: gd32f3x0_misc.h:26
void nvic_vector_table_set | ( | uint32_t | nvic_vict_tab,
 |  | uint32_t | offset
 | ) |  |

set the NVIC vector table base address

Parameters
[in] nvic_vict_tab the RAM or FLASH base address
  • NVIC_VECTTAB_RAM: RAM base address NVIC_VECTTAB_FLASH: Flash base address
[in] | offset | Vector Table offset
[out] | none
Return values
none

Definition at line 102 of file gd32f3x0_misc.c.

103 {
104 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
105 }
NVIC_VECTTAB_OFFSET_MASK
#define NVIC_VECTTAB_OFFSET_MASK
Definition: gd32f3x0_misc.h:23
void system_lowpower_reset ( uint8_t lowpower_mode )

reset the state of the low power mode

Parameters
[in] lowpower_mode the low power mode state
  • SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power mode by exiting from ISR
  • SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
  • SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be woke up by the enable interrupts
[out] none
Return values
none

Definition at line 134 of file gd32f3x0_misc.c.

135 {
136 SCB->SCR &= (~(uint32_t)lowpower_mode);
137 }
void system_lowpower_set ( uint8_t lowpower_mode )

set the state of the low power mode

Parameters
[in] lowpower_mode the low power mode state
  • SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power mode by exiting from ISR
  • SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
  • SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up by all the enable and disable interrupts
[out] none
Return values
none

Definition at line 118 of file gd32f3x0_misc.c.

119 {
120 SCB->SCR |= (uint32_t)lowpower_mode;
121 }
void systick_clksource_set ( uint32_t systick_clksource )

set the systick clock source

Parameters
[in] systick_clksource the systick clock source needed to choose
  • SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
  • SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
[out] none
Return values
none

Definition at line 148 of file gd32f3x0_misc.c.

149 {
150 if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
151 /* set the systick clock source from HCLK */
152 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
153 }else{
154 /* set the systick clock source from HCLK/8 */
155 SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
156 }
157 }
SYSTICK_CLKSOURCE_HCLK_DIV8
#define SYSTICK_CLKSOURCE_HCLK_DIV8
Definition: gd32f3x0_misc.h:45
SYSTICK_CLKSOURCE_HCLK
#define SYSTICK_CLKSOURCE_HCLK
Definition: gd32f3x0_misc.h:46
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_pmu.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_pmu.c File Reference

PMU driver. More...

#include "gd32f3x0_pmu.h"
#include "core_cm4.h"

Go to the source code of this file.

Functions

void | pmu_deinit (void)
reset PMU register More...
void | pmu_lvd_select (uint32_t lvdt_n)
select low voltage detector threshold More...
void | pmu_ldo_output_select (uint32_t ldo_output)
select LDO output voltage these bits set by software when the main PLL closed More...
void | pmu_lvd_disable (void)
disable PMU lvd More...
void | pmu_lowdriver_mode_enable (void)
enable low-driver mode in deep-sleep mode More...
void | pmu_lowdriver_mode_disable (void)
enable low-driver mode in deep-sleep mode More...
void | pmu_highdriver_mode_enable (void)
enable high-driver mode this bit set by software only when IRC8M or HXTAL used as system clock More...
void | pmu_highdriver_mode_disable (void)
disable high-driver mode More...
void | pmu_highdriver_switch_select (uint32_t highdr_switch)
switch high-driver mode this bit set by software only when IRC8M or HXTAL used as system clock More...
void | pmu_lowpower_driver_config (uint32_t mode)
low-driver mode when use low power LDO More...
void | pmu_normalpower_driver_config (uint32_t mode)
low-driver mode when use normal power LDO More...
void | pmu_to_sleepmode (uint8_t sleepmodecmd)
PMU work at sleep mode. More...
void | pmu_to_deepsleepmode (uint32_t ldo, uint8_t deepsleepmodecmd)
PMU work at deepsleep mode. More...
void | pmu_to_standbymode (uint8_t standbymodecmd)
pmu work at standby mode More...
void | pmu_wakeup_pin_enable (uint32_t wakeup_pin)
enable wakeup pin More...
void | pmu_wakeup_pin_disable (uint32_t wakeup_pin)
disable wakeup pin More...
void | pmu_backup_write_enable (void)
enable backup domain write More...
void | pmu_backup_write_disable (void)
disable backup domain write More...
void | pmu_flag_clear (uint32_t flag_clear)
clear flag bit More...
FlagStatus | pmu_flag_get (uint32_t flag)
get flag state More...

Detailed Description

PMU driver.

Definition in file gd32f3x0_pmu.c.

Function Documentation

void pmu_backup_write_disable ( void )

disable backup domain write

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 317 of file gd32f3x0_pmu.c.

318 {
319 PMU_CTL &= ~PMU_CTL_BKPWEN;
320 }
PMU_CTL_BKPWEN
#define PMU_CTL_BKPWEN
Definition: gd32f3x0_pmu.h:32
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_backup_write_enable ( void )

enable backup domain write

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 306 of file gd32f3x0_pmu.c.

307 {
308 PMU_CTL |= PMU_CTL_BKPWEN;
309 }
PMU_CTL_BKPWEN
#define PMU_CTL_BKPWEN
Definition: gd32f3x0_pmu.h:32
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_deinit ( void )

reset PMU register

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 21 of file gd32f3x0_pmu.c.

22 {
23 /* reset PMU */
24 rcu_periph_reset_enable(RCU_PMURST);
25 rcu_periph_reset_disable(RCU_PMURST);
26 }
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
RCU_PMURST
Definition: gd32f3x0_rcu.h:353
void pmu_flag_clear ( uint32_t flag_clear )

clear flag bit

Parameters
[in] flag_clear one or more parameters can be selected below
  • PMU_FLAG_RESET_WAKEUP: reset wakeup flag
  • PMU_FLAG_RESET_STANDBY: reset standby flag
[out] none
Return values
none

Definition at line 331 of file gd32f3x0_pmu.c.

332 {
333 if(RESET != (flag_clear & PMU_FLAG_RESET_WAKEUP)){
334 /* reset wakeup flag */
335 PMU_CTL |= PMU_CTL_WURST;
336 }
337 if(RESET != (flag_clear & PMU_FLAG_RESET_STANDBY)){
338 /* reset standby flag */
339 PMU_CTL |= PMU_CTL_STBRST;
340 }
341 }
PMU_FLAG_RESET_STANDBY
#define PMU_FLAG_RESET_STANDBY
Definition: gd32f3x0_pmu.h:116
PMU_FLAG_RESET_WAKEUP
#define PMU_FLAG_RESET_WAKEUP
Definition: gd32f3x0_pmu.h:115
PMU_CTL_WURST
#define PMU_CTL_WURST
Definition: gd32f3x0_pmu.h:28
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_CTL_STBRST
#define PMU_CTL_STBRST
Definition: gd32f3x0_pmu.h:29
FlagStatus pmu_flag_get ( uint32_t flag )

get flag state

Parameters
[in] flag only one among these parameters can be selected
  • PMU_FLAG_WAKEUP: wakeup flag
  • PMU_FLAG_STANDBY: standby flag
  • PMU_FLAG_LVD: lvd flag
  • PMU_FLAG_LDOVSR: LDO voltage select ready flag
  • PMU_FLAG_HDR: high-driver ready flag
  • PMU_FLAG_HDSR: high-driver switch ready flag
  • PMU_FLAG_LDR: low-driver mode ready flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 357 of file gd32f3x0_pmu.c.

358 {
359 FlagStatus ret_status = RESET;
360
361 if(PMU_CS & flag){
362 ret_status = SET;
363 }
364
365 return ret_status;
366 }
PMU_CS
#define PMU_CS
Definition: gd32f3x0_pmu.h:22
void pmu_highdriver_mode_disable ( void )

disable high-driver mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 126 of file gd32f3x0_pmu.c.

127 {
128 PMU_CTL &= ~PMU_CTL_HDEN;
129 }
PMU_CTL_HDEN
#define PMU_CTL_HDEN
Definition: gd32f3x0_pmu.h:36
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_highdriver_mode_enable ( void )

enable high-driver mode this bit set by software only when IRC8M or HXTAL used as system clock

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 115 of file gd32f3x0_pmu.c.

116 {
117 PMU_CTL |= PMU_CTL_HDEN;
118 }
PMU_CTL_HDEN
#define PMU_CTL_HDEN
Definition: gd32f3x0_pmu.h:36
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_highdriver_switch_select ( uint32_t highdr_switch )

switch high-driver mode this bit set by software only when IRC8M or HXTAL used as system clock

Parameters
[in] highdr_switch only one among these parameters can be selected
  • PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch
  • PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch
[out] none
Return values
none

Definition at line 141 of file gd32f3x0_pmu.c.

142 {
143 /* wait for HDRF flag to be set */
144 while(SET != pmu_flag_get(PMU_FLAG_HDR)){
145 }
146 PMU_CTL &= ~PMU_CTL_HDS;
147 PMU_CTL |= highdr_switch;
148 }
pmu_flag_get
FlagStatus pmu_flag_get(uint32_t flag)
get flag state
Definition: gd32f3x0_pmu.c:357
PMU_CTL_HDS
#define PMU_CTL_HDS
Definition: gd32f3x0_pmu.h:37
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_FLAG_HDR
#define PMU_FLAG_HDR
Definition: gd32f3x0_pmu.h:103
void pmu_ldo_output_select ( uint32_t ldo_output )

select LDO output voltage these bits set by software when the main PLL closed

Parameters
[in] ldo_output only one among these parameters can be selected
  • PMU_LDOVS_LOW: LDO output voltage low mode
  • PMU_LDOVS_MID: LDO output voltage mid mode
  • PMU_LDOVS_HIGH: LDO output voltage high mode
[out] none
Return values
none

Definition at line 66 of file gd32f3x0_pmu.c.

67 {
68 PMU_CTL &= ~PMU_CTL_LDOVS;
69 PMU_CTL |= ldo_output;
70 }
PMU_CTL_LDOVS
#define PMU_CTL_LDOVS
Definition: gd32f3x0_pmu.h:35
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_lowdriver_mode_disable ( void )

enable low-driver mode in deep-sleep mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 102 of file gd32f3x0_pmu.c.

103 {
104 PMU_CTL &= ~PMU_CTL_LDEN;
105 PMU_CTL |= PMU_LOWDRIVER_DISABLE;
106 }
PMU_LOWDRIVER_DISABLE
#define PMU_LOWDRIVER_DISABLE
Definition: gd32f3x0_pmu.h:74
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_CTL_LDEN
#define PMU_CTL_LDEN
Definition: gd32f3x0_pmu.h:38
void pmu_lowdriver_mode_enable ( void )

enable low-driver mode in deep-sleep mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 90 of file gd32f3x0_pmu.c.

91 {
92 PMU_CTL &= ~PMU_CTL_LDEN;
93 PMU_CTL |= PMU_LOWDRIVER_ENABLE;
94 }
PMU_LOWDRIVER_ENABLE
#define PMU_LOWDRIVER_ENABLE
Definition: gd32f3x0_pmu.h:75
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_CTL_LDEN
#define PMU_CTL_LDEN
Definition: gd32f3x0_pmu.h:38
void pmu_lowpower_driver_config ( uint32_t mode )

low-driver mode when use low power LDO

Parameters
[in] mode only one among these parameters can be selected
  • PMU_NORMALDR_LOWPWR: normal-driver when use low power LDO
  • PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO
[out] none
Return values
none

Definition at line 159 of file gd32f3x0_pmu.c.

160 {
161 PMU_CTL &= ~PMU_CTL_LDLP;
162 PMU_CTL |= mode;
163 }
PMU_CTL_LDLP
#define PMU_CTL_LDLP
Definition: gd32f3x0_pmu.h:33
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_lvd_disable ( void )

disable PMU lvd

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 78 of file gd32f3x0_pmu.c.

79 {
80 /* disable LVD */
81 PMU_CTL &= ~PMU_CTL_LVDEN;
82 }
PMU_CTL_LVDEN
#define PMU_CTL_LVDEN
Definition: gd32f3x0_pmu.h:30
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_lvd_select ( uint32_t lvdt_n )

select low voltage detector threshold

Parameters
[in] lvdt_n only one among these parameters can be selected
  • PMU_LVDT_0: voltage threshold is 2.1V
  • PMU_LVDT_1: voltage threshold is 2.3V
  • PMU_LVDT_2: voltage threshold is 2.4V
  • PMU_LVDT_3: voltage threshold is 2.6V
  • PMU_LVDT_4: voltage threshold is 2.7V
  • PMU_LVDT_5: voltage threshold is 2.9V
  • PMU_LVDT_6: voltage threshold is 3.0V
  • PMU_LVDT_7: voltage threshold is 3.1V
[out] none
Return values
none

Definition at line 43 of file gd32f3x0_pmu.c.

44 {
45 /* disable LVD */
46 PMU_CTL &= ~PMU_CTL_LVDEN;
47 /* clear LVDT bits */
48 PMU_CTL &= ~PMU_CTL_LVDT;
49 /* set LVDT bits according to lvdt_n */
50 PMU_CTL |= lvdt_n;
51 /* enable LVD */
52 PMU_CTL |= PMU_CTL_LVDEN;
53 }
PMU_CTL_LVDT
#define PMU_CTL_LVDT
Definition: gd32f3x0_pmu.h:31
PMU_CTL_LVDEN
#define PMU_CTL_LVDEN
Definition: gd32f3x0_pmu.h:30
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
void pmu_normalpower_driver_config ( uint32_t mode )

low-driver mode when use normal power LDO

Parameters
[in] mode only one among these parameters can be selected
  • PMU_NORMALDR_NORMALPWR: normal-driver when use low power LDO
  • PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use low power LDO
[out] none
Return values
none

Definition at line 174 of file gd32f3x0_pmu.c.

175 {
176 PMU_CTL &= ~PMU_CTL_LDNP;
177 PMU_CTL |= mode;
178 }
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_CTL_LDNP
#define PMU_CTL_LDNP
Definition: gd32f3x0_pmu.h:34
void pmu_to_deepsleepmode | ( | uint32_t | ldo,
 |  | uint8_t | deepsleepmodecmd
 | ) |  |

PMU work at deepsleep mode.

Parameters
[in] ldo only one among these parameters can be selected
  • PMU_LDO_NORMAL: LDO operates normally when pmu enter deepsleep mode
  • PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
[in] deepsleepmodecmd only one among these parameters can be selected
  • WFI_CMD: use WFI command
  • WFE_CMD: use WFE command
[out] none
Return values
none

Definition at line 215 of file gd32f3x0_pmu.c.

216 {
217 /* clear stbmod and ldolp bits */
218 PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
219
220 /* set ldolp bit according to pmu_ldo */
221 PMU_CTL |= ldo;
222
223 /* set sleepdeep bit of Cortex-M4 system control register */
224 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
225
226 /* select WFI or WFE command to enter deepsleep mode */
227 if(WFI_CMD == deepsleepmodecmd){
228 __WFI();
229 }else{
230 __SEV();
231 __WFE();
232 __WFE();
233 }
234 /* reset sleepdeep bit of Cortex-M4 system control register */
235 SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
236 }
WFI_CMD
#define WFI_CMD
Definition: gd32f3x0_pmu.h:119
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_CTL_STBMOD
#define PMU_CTL_STBMOD
Definition: gd32f3x0_pmu.h:27
PMU_CTL_LDOLP
#define PMU_CTL_LDOLP
Definition: gd32f3x0_pmu.h:26
void pmu_to_sleepmode ( uint8_t sleepmodecmd )

PMU work at sleep mode.

Parameters
[in] sleepmodecmd only one among these parameters can be selected
  • WFI_CMD: use WFI command
  • WFE_CMD: use WFE command
[out] none
Return values
none

Definition at line 189 of file gd32f3x0_pmu.c.

190 {
191 /* clear sleepdeep bit of Cortex-M4 system control register */
192 SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
193
194 /* select WFI or WFE command to enter sleep mode */
195 if(WFI_CMD == sleepmodecmd){
196 __WFI();
197 }else{
198 __WFE();
199 }
200 }
WFI_CMD
#define WFI_CMD
Definition: gd32f3x0_pmu.h:119
void pmu_to_standbymode ( uint8_t standbymodecmd )

pmu work at standby mode

Parameters
[in] standbymodecmd only one among these parameters can be selected
  • WFI_CMD: use WFI command
  • WFE_CMD: use WFE command
[out] none
Return values
none

Definition at line 247 of file gd32f3x0_pmu.c.

248 {
249 /* set sleepdeep bit of Cortex-M4 system control register */
250 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
251
252 /* set stbmod bit */
253 PMU_CTL |= PMU_CTL_STBMOD;
254
255 /* reset wakeup flag */
256 PMU_CTL |= PMU_CTL_WURST;
257
258 /* select WFI or WFE command to enter standby mode */
259 if(WFI_CMD == standbymodecmd){
260 __WFI();
261 }else{
262 __WFE();
263 }
264 }
PMU_CTL_WURST
#define PMU_CTL_WURST
Definition: gd32f3x0_pmu.h:28
WFI_CMD
#define WFI_CMD
Definition: gd32f3x0_pmu.h:119
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_CTL_STBMOD
#define PMU_CTL_STBMOD
Definition: gd32f3x0_pmu.h:27
void pmu_wakeup_pin_disable ( uint32_t wakeup_pin )

disable wakeup pin

Parameters
[in] wakeup_pin one or more parameters can be selected below
  • PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
  • PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
  • PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5)
  • PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
  • PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
[out] none
Return values
none

Definition at line 295 of file gd32f3x0_pmu.c.

296 {
297 PMU_CS &= ~(wakeup_pin);
298 }
PMU_CS
#define PMU_CS
Definition: gd32f3x0_pmu.h:22
void pmu_wakeup_pin_enable ( uint32_t wakeup_pin )

enable wakeup pin

Parameters
[in] wakeup_pin one or more parameters can be selected below
  • PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
  • PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
  • PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5)
  • PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
  • PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
[out] none
Return values
none

Definition at line 278 of file gd32f3x0_pmu.c.

279 {
280 PMU_CS |= wakeup_pin;
281 }
PMU_CS
#define PMU_CS
Definition: gd32f3x0_pmu.h:22
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_rcu.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Macros | Functions
gd32f3x0_rcu.c File Reference

RCU driver. More...

#include "gd32f3x0_rcu.h"

Go to the source code of this file.

Macros

#define | SEL_IRC8M 0x00U
#define | SEL_HXTAL 0x01U
#define | SEL_PLL 0x02U
#define | OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU)
#define | LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU)

Functions

void | rcu_deinit (void)
deinitialize the RCU More...
void | rcu_periph_clock_enable (rcu_periph_enum periph)
enable the peripherals clock More...
void | rcu_periph_clock_disable (rcu_periph_enum periph)
disable the peripherals clock More...
void | rcu_periph_clock_sleep_enable (rcu_periph_sleep_enum periph)
enable the peripherals clock when sleep mode More...
void | rcu_periph_clock_sleep_disable (rcu_periph_sleep_enum periph)
disable the peripherals clock when sleep mode More...
void | rcu_periph_reset_enable (rcu_periph_reset_enum periph_reset)
reset the peripherals More...
void | rcu_periph_reset_disable (rcu_periph_reset_enum periph_reset)
disable reset the peripheral More...
void | rcu_bkp_reset_enable (void)
reset the BKP More...
void | rcu_bkp_reset_disable (void)
disable the BKP reset More...
void | rcu_system_clock_source_config (uint32_t ck_sys)
configure the system clock source More...
uint32_t | rcu_system_clock_source_get (void)
get the system clock source More...
void | rcu_ahb_clock_config (uint32_t ck_ahb)
configure the AHB clock prescaler selection More...
void | rcu_apb1_clock_config (uint32_t ck_apb1)
configure the APB1 clock prescaler selection More...
void | rcu_apb2_clock_config (uint32_t ck_apb2)
configure the APB2 clock prescaler selection More...
void | rcu_adc_clock_config (rcu_adc_clock_enum ck_adc)
configure the ADC clock prescaler selection More...
void | rcu_usbfs_clock_config (uint32_t ck_usbfs)
configure the USBFS clock prescaler selection More...
void | rcu_ckout_config (uint32_t ckout_src, uint32_t ckout_div)
configure the CK_OUT clock source and divider More...
void | rcu_pll_preselection_config (uint32_t pll_presel)
configure the PLL clock source preselection More...
void | rcu_pll_config (uint32_t pll_src, uint32_t pll_mul)
configure the PLL clock source selection and PLL multiply factor More...
void | rcu_usart_clock_config (uint32_t ck_usart)
configure the USART clock source selection More...
void | rcu_cec_clock_config (uint32_t ck_cec)
configure the CEC clock source selection More...
void | rcu_rtc_clock_config (uint32_t rtc_clock_source)
configure the RTC clock source selection More...
void | rcu_hxtal_prediv_config (uint32_t hxtal_prediv)
configure the HXTAL divider used as input of PLL More...
void | rcu_lxtal_drive_capability_config (uint32_t lxtal_dricap)
configure the LXTAL drive capability More...
FlagStatus | rcu_flag_get (rcu_flag_enum flag)
get the clock stabilization and periphral reset flags More...
void | rcu_all_reset_flag_clear (void)
clear the reset flag More...
FlagStatus | rcu_interrupt_flag_get (rcu_int_flag_enum int_flag)
get the clock stabilization interrupt and ckm flags More...
void | rcu_interrupt_flag_clear (rcu_int_flag_clear_enum int_flag_clear)
clear the interrupt flags More...
void | rcu_interrupt_enable (rcu_int_enum stab_int)
enable the stabilization interrupt More...
void | rcu_interrupt_disable (rcu_int_enum stab_int)
disable the stabilization interrupt More...
ErrStatus | rcu_osci_stab_wait (rcu_osci_type_enum osci)
wait until oscillator stabilization flags is SET More...
void | rcu_osci_on (rcu_osci_type_enum osci)
turn on the oscillator More...
void | rcu_osci_off (rcu_osci_type_enum osci)
turn off the oscillator More...
void | rcu_osci_bypass_mode_enable (rcu_osci_type_enum osci)
enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it More...
void | rcu_osci_bypass_mode_disable (rcu_osci_type_enum osci)
disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it More...
void | rcu_hxtal_clock_monitor_enable (void)
enable the HXTAL clock monitor More...
void | rcu_hxtal_clock_monitor_disable (void)
disable the HXTAL clock monitor More...
void | rcu_irc8m_adjust_value_set (uint8_t irc8m_adjval)
set the IRC8M adjust value More...
void | rcu_irc28m_adjust_value_set (uint8_t irc28m_adjval)
set the IRC28M adjust value More...
void | rcu_voltage_key_unlock (void)
unlock the voltage key More...
void | rcu_deepsleep_voltage_set (uint32_t dsvol)
set voltage in deep sleep mode More...
uint32_t | rcu_clock_freq_get (rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency More...

Detailed Description

RCU driver.

Definition in file gd32f3x0_rcu.c.

Macro Definition Documentation

#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU)

Definition at line 21 of file gd32f3x0_rcu.c.

#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU)

Definition at line 20 of file gd32f3x0_rcu.c.

#define SEL_HXTAL 0x01U

Definition at line 16 of file gd32f3x0_rcu.c.

#define SEL_IRC8M 0x00U

Definition at line 15 of file gd32f3x0_rcu.c.

#define SEL_PLL 0x02U

Definition at line 17 of file gd32f3x0_rcu.c.

Function Documentation

void rcu_adc_clock_config ( rcu_adc_clock_enum ck_adc )

configure the ADC clock prescaler selection

Parameters
[in] ck_adc ADC clock prescaler selection, refer to rcu_adc_clock_enum
  • RCU_ADCCK_IRC28M_DIV2: select CK_IRC28M/2 as CK_ADC
  • RCU_ADCCK_IRC28M: select CK_IRC28M as CK_ADC
  • RCU_ADCCK_APB2_DIV2: select CK_APB2/2 as CK_ADC
  • RCU_ADCCK_APB2_DIV3: select CK_APB2/3 as CK_ADC
  • RCU_ADCCK_APB2_DIV4: select CK_APB2/4 as CK_ADC
  • RCU_ADCCK_APB2_DIV5: select CK_APB2/5 as CK_ADC
  • RCU_ADCCK_APB2_DIV6: select CK_APB2/6 as CK_ADC
  • RCU_ADCCK_APB2_DIV7: select CK_APB2/7 as CK_ADC
  • RCU_ADCCK_APB2_DIV8: select CK_APB2/8 as CK_ADC
  • RCU_ADCCK_APB2_DIV9: select CK_APB2/9 as CK_ADC
[out] none
Return values
none

Definition at line 318 of file gd32f3x0_rcu.c.

319 {
320 /* reset the ADCPSC, ADCSEL, IRC28MDIV bits */
321 RCU_CFG0 &= ~RCU_CFG0_ADCPSC;
322 RCU_CFG2 &= ~(RCU_CFG2_ADCSEL | RCU_CFG2_IRC28MDIV | RCU_CFG2_ADCPSC2);
323
324 /* set the ADC clock according to ck_adc */
325 switch(ck_adc){
326 case RCU_ADCCK_IRC28M_DIV2:
327 RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
328 RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
329 break;
330 case RCU_ADCCK_IRC28M:
331 RCU_CFG2 |= RCU_CFG2_IRC28MDIV;
332 RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
333 break;
334 case RCU_ADCCK_APB2_DIV2:
335 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2;
336 RCU_CFG2 |= RCU_CFG2_ADCSEL;
337 break;
338 case RCU_ADCCK_APB2_DIV3:
339 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2;
340 RCU_CFG2 |= RCU_CFG2_ADCPSC2;
341 RCU_CFG2 |= RCU_CFG2_ADCSEL;
342 break;
343 case RCU_ADCCK_APB2_DIV4:
344 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4;
345 RCU_CFG2 |= RCU_CFG2_ADCSEL;
346 break;
347 case RCU_ADCCK_APB2_DIV5:
348 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4;
349 RCU_CFG2 |= RCU_CFG2_ADCPSC2;
350 RCU_CFG2 |= RCU_CFG2_ADCSEL;
351 break;
352 case RCU_ADCCK_APB2_DIV6:
353 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6;
354 RCU_CFG2 |= RCU_CFG2_ADCSEL;
355 break;
356 case RCU_ADCCK_APB2_DIV7:
357 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6;
358 RCU_CFG2 |= RCU_CFG2_ADCPSC2;
359 RCU_CFG2 |= RCU_CFG2_ADCSEL;
360 break;
361 case RCU_ADCCK_APB2_DIV8:
362 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8;
363 RCU_CFG2 |= RCU_CFG2_ADCSEL;
364 break;
365 case RCU_ADCCK_APB2_DIV9:
366 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8;
367 RCU_CFG2 |= RCU_CFG2_ADCPSC2;
368 RCU_CFG2 |= RCU_CFG2_ADCSEL;
369 break;
370 default:
371 break;
372 }
373 }
RCU_ADCCK_APB2_DIV3
Definition: gd32f3x0_rcu.h:430
RCU_CFG2_ADCPSC2
#define RCU_CFG2_ADCPSC2
Definition: gd32f3x0_rcu.h:198
RCU_ADCCK_APB2_DIV6
Definition: gd32f3x0_rcu.h:433
RCU_ADC_CKAPB2_DIV8
#define RCU_ADC_CKAPB2_DIV8
Definition: gd32f3x0_rcu.h:508
RCU_ADCCK_IRC28M
Definition: gd32f3x0_rcu.h:428
RCU_ADCCK_APB2_DIV5
Definition: gd32f3x0_rcu.h:432
RCU_CFG0_ADCPSC
#define RCU_CFG0_ADCPSC
Definition: gd32f3x0_rcu.h:61
RCU_ADCCK_APB2_DIV9
Definition: gd32f3x0_rcu.h:436
RCU_CFG2_IRC28MDIV
#define RCU_CFG2_IRC28MDIV
Definition: gd32f3x0_rcu.h:196
RCU_ADCCK_APB2_DIV7
Definition: gd32f3x0_rcu.h:434
RCU_CFG2_ADCSEL
#define RCU_CFG2_ADCSEL
Definition: gd32f3x0_rcu.h:195
RCU_ADC_CKAPB2_DIV4
#define RCU_ADC_CKAPB2_DIV4
Definition: gd32f3x0_rcu.h:506
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_ADC_CKAPB2_DIV6
#define RCU_ADC_CKAPB2_DIV6
Definition: gd32f3x0_rcu.h:507
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
RCU_ADCCK_APB2_DIV8
Definition: gd32f3x0_rcu.h:435
RCU_ADC_CKAPB2_DIV2
#define RCU_ADC_CKAPB2_DIV2
Definition: gd32f3x0_rcu.h:505
RCU_ADCCK_IRC28M_DIV2
Definition: gd32f3x0_rcu.h:427
RCU_ADCCK_APB2_DIV4
Definition: gd32f3x0_rcu.h:431
RCU_ADCCK_APB2_DIV2
Definition: gd32f3x0_rcu.h:429
void rcu_ahb_clock_config ( uint32_t ck_ahb )

configure the AHB clock prescaler selection

Parameters
[in] ck_ahb AHB clock prescaler selection
  • RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512
[out] none
Return values
none

Definition at line 253 of file gd32f3x0_rcu.c.

254 {
255 uint32_t ahbpsc = 0U;
256 ahbpsc = RCU_CFG0;
257 /* reset the AHBPSC bits and set according to ck_ahb */
258 ahbpsc &= ~RCU_CFG0_AHBPSC;
259 RCU_CFG0 = (ck_ahb | ahbpsc);
260 }
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG0_AHBPSC
#define RCU_CFG0_AHBPSC
Definition: gd32f3x0_rcu.h:58
void rcu_all_reset_flag_clear ( void )

clear the reset flag

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 574 of file gd32f3x0_rcu.c.

575 {
576 RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
577 }
RCU_RSTSCK
#define RCU_RSTSCK
Definition: gd32f3x0_rcu.h:30
RCU_RSTSCK_RSTFC
#define RCU_RSTSCK_RSTFC
Definition: gd32f3x0_rcu.h:169
void rcu_apb1_clock_config ( uint32_t ck_apb1 )

configure the APB1 clock prescaler selection

Parameters
[in] ck_apb1 APB1 clock prescaler selection
  • RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1
  • RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1
  • RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1
  • RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1
  • RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1
[out] none
Return values
none

Definition at line 273 of file gd32f3x0_rcu.c.

274 {
275 uint32_t apb1psc = 0U;
276 apb1psc = RCU_CFG0;
277 /* reset the APB1PSC and set according to ck_apb1 */
278 apb1psc &= ~RCU_CFG0_APB1PSC;
279 RCU_CFG0 = (ck_apb1 | apb1psc);
280 }
RCU_CFG0_APB1PSC
#define RCU_CFG0_APB1PSC
Definition: gd32f3x0_rcu.h:59
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
void rcu_apb2_clock_config ( uint32_t ck_apb2 )

configure the APB2 clock prescaler selection

Parameters
[in] ck_apb2 APB2 clock prescaler selection
  • RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2
  • RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2
  • RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2
  • RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2
  • RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2
[out] none
Return values
none

Definition at line 293 of file gd32f3x0_rcu.c.

294 {
295 uint32_t apb2psc = 0U;
296 apb2psc = RCU_CFG0;
297 /* reset the APB2PSC and set according to ck_apb2 */
298 apb2psc &= ~RCU_CFG0_APB2PSC;
299 RCU_CFG0 = (ck_apb2 | apb2psc);
300 }
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG0_APB2PSC
#define RCU_CFG0_APB2PSC
Definition: gd32f3x0_rcu.h:60
void rcu_bkp_reset_disable ( void )

disable the BKP reset

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 208 of file gd32f3x0_rcu.c.

209 {
210 RCU_BDCTL &= ~RCU_BDCTL_BKPRST;
211 }
RCU_BDCTL_BKPRST
#define RCU_BDCTL_BKPRST
Definition: gd32f3x0_rcu.h:163
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f3x0_rcu.h:29
void rcu_bkp_reset_enable ( void )

reset the BKP

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 197 of file gd32f3x0_rcu.c.

198 {
199 RCU_BDCTL |= RCU_BDCTL_BKPRST;
200 }
RCU_BDCTL_BKPRST
#define RCU_BDCTL_BKPRST
Definition: gd32f3x0_rcu.h:163
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f3x0_rcu.h:29
void rcu_cec_clock_config ( uint32_t ck_cec )

configure the CEC clock source selection

Parameters
[in] ck_cec CEC clock source selection
  • RCU_CECSRC_IRC8M_DIV244: CK_CEC select CK_IRC8M/244
  • RCU_CECSRC_LXTAL: CK_CEC select CK_LXTAL
[out] none
Return values
none

Definition at line 480 of file gd32f3x0_rcu.c.

481 {
482 /* reset the CECSEL bit and set according to ck_cec */
483 RCU_CFG2 &= ~RCU_CFG2_CECSEL;
484 RCU_CFG2 |= ck_cec;
485 }
RCU_CFG2_CECSEL
#define RCU_CFG2_CECSEL
Definition: gd32f3x0_rcu.h:194
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
void rcu_ckout_config | ( | uint32_t | ckout_src,
 |  | uint32_t | ckout_div
 | ) |  |

configure the CK_OUT clock source and divider

Parameters
[in] ckout_src CK_OUT clock source selection
  • RCU_CKOUTSRC_NONE: no clock selected
  • RCU_CKOUTSRC_IRC28M: IRC28M selected
  • RCU_CKOUTSRC_IRC40K: IRC40K selected
  • RCU_CKOUTSRC_LXTAL: LXTAL selected
  • RCU_CKOUTSRC_CKSYS: CKSYS selected
  • RCU_CKOUTSRC_IRC8M: IRC8M selected
  • RCU_CKOUTSRC_HXTAL: HXTAL selected
  • RCU_CKOUTSRC_CKPLL_DIV1: CK_PLL selected
  • RCU_CKOUTSRC_CKPLL_DIV2: CK_PLL/2 selected
[in] ckout_div CK_OUT divider
  • RCU_CKOUT_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT is divided by x
[out] none
Return values
none

Definition at line 414 of file gd32f3x0_rcu.c.

415 {
416 uint32_t ckout = 0U;
417 ckout = RCU_CFG0;
418 /* reset the CKOUTSEL, CKOUTDIV and PLLDV bits and set according to ckout_src and ckout_div */
419 ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
420 RCU_CFG0 = (ckout | ckout_src | ckout_div);
421 }
RCU_CFG0_CKOUTSEL
#define RCU_CFG0_CKOUTSEL
Definition: gd32f3x0_rcu.h:66
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG0_PLLDV
#define RCU_CFG0_PLLDV
Definition: gd32f3x0_rcu.h:69
RCU_CFG0_CKOUTDIV
#define RCU_CFG0_CKOUTDIV
Definition: gd32f3x0_rcu.h:68
uint32_t rcu_clock_freq_get ( rcu_clock_freq_enum clock )

get the system clock, bus and peripheral clock frequency

Parameters
[in] clock the clock frequency which to get
  • CK_SYS: system clock frequency
  • CK_AHB: AHB clock frequency
  • CK_APB1: APB1 clock frequency
  • CK_APB2: APB2 clock frequency
  • CK_ADC: ADC clock frequency
  • CK_CEC: CEC clock frequency
  • CK_USART: USART clock frequency
[out] none
Return values
clock frequency of system, AHB, APB1, APB2, ADC, CEC or USRAT

Definition at line 964 of file gd32f3x0_rcu.c.

965 {
966 uint32_t sws = 0U, adcps = 0U, adcps2 = 0U, ck_freq = 0U;
967 uint32_t cksys_freq = 0U, ahb_freq = 0U, apb1_freq = 0U, apb2_freq = 0U;
968 uint32_t adc_freq = 0U, cec_freq = 0U, usart_freq = 0U;
969 uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
970 /* exponent of AHB, APB1 and APB2 clock divider */
971 const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
972 const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
973 const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
974
975 sws = GET_BITS(RCU_CFG0, 2, 3);
976 switch(sws){
977 /* IRC8M is selected as CK_SYS */
978 case SEL_IRC8M:
979 cksys_freq = IRC8M_VALUE;
980 break;
981 /* HXTAL is selected as CK_SYS */
982 case SEL_HXTAL:
983 cksys_freq = HXTAL_VALUE;
984 break;
985 /* PLL is selected as CK_SYS */
986 case SEL_PLL:
987 /* get the value of PLLMF[3:0] */
988 pllmf = GET_BITS(RCU_CFG0, 18, 21);
989 pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
990 pllmf5 = GET_BITS(RCU_CFG1, 31, 31);
991 /* high 16 bits */
992 if(1U == pllmf4){
993 pllmf += 17U;
994 }else{
995 pllmf += 2U;
996 }
997 if(1U == pllmf5){
998 pllmf += 31U;
999 }
1000
1001 /* PLL clock source selection, HXTAL or IRC8M/2 */
1002 pllsel = GET_BITS(RCU_CFG0, 16, 16);
1003 pllpresel = GET_BITS(RCU_CFG1, 30, 30);
1004 if(0U != pllsel){
1005 prediv = (GET_BITS(RCU_CFG1,0, 3) + 1U);
1006 if(0U == pllpresel){
1007 cksys_freq = (HXTAL_VALUE / prediv) * pllmf;
1008 }else{
1009 cksys_freq = (IRC48M_VALUE / prediv) * pllmf;
1010 }
1011 }else{
1012 cksys_freq = (IRC8M_VALUE >> 1) * pllmf;
1013 }
1014 break;
1015 /* IRC8M is selected as CK_SYS */
1016 default:
1017 cksys_freq = IRC8M_VALUE;
1018 break;
1019 }
1020 /* calculate AHB clock frequency */
1021 idx = GET_BITS(RCU_CFG0, 4, 7);
1022 clk_exp = ahb_exp[idx];
1023 ahb_freq = cksys_freq >> clk_exp;
1024
1025 /* calculate APB1 clock frequency */
1026 idx = GET_BITS(RCU_CFG0, 8, 10);
1027 clk_exp = apb1_exp[idx];
1028 apb1_freq = ahb_freq >> clk_exp;
1029
1030 /* calculate APB2 clock frequency */
1031 idx = GET_BITS(RCU_CFG0, 11, 13);
1032 clk_exp = apb2_exp[idx];
1033 apb2_freq = ahb_freq >> clk_exp;
1034
1035 /* return the clocks frequency */
1036 switch(clock){
1037 case CK_SYS:
1038 ck_freq = cksys_freq;
1039 break;
1040 case CK_AHB:
1041 ck_freq = ahb_freq;
1042 break;
1043 case CK_APB1:
1044 ck_freq = apb1_freq;
1045 break;
1046 case CK_APB2:
1047 ck_freq = apb2_freq;
1048 break;
1049 case CK_ADC:
1050 /* calculate ADC clock frequency */
1051 if(RCU_ADCSRC_APB2DIV != (RCU_CFG2 & RCU_CFG2_ADCSEL)){
1052 if(RCU_ADC_IRC28M_DIV1 != (RCU_CFG2 & RCU_CFG2_IRC28MDIV)){
1053 adc_freq = IRC28M_VALUE >> 1;
1054 }else{
1055 adc_freq = IRC28M_VALUE;
1056 }
1057 }else{
1058 /* ADC clock select CK_APB2 divided by 2/3/4/5/6/7/8/9 */
1059 adcps = GET_BITS(RCU_CFG0, 14, 15);
1060 adcps2 = GET_BITS(RCU_CFG2, 31, 31);
1061 switch(adcps){
1062 case 0:
1063 if(0U == adcps2){
1064 adc_freq = apb2_freq / 2U;
1065 }else{
1066 adc_freq = apb2_freq / 3U;
1067 }
1068 break;
1069 case 1:
1070 if(0U == adcps2){
1071 adc_freq = apb2_freq / 4U;
1072 }else{
1073 adc_freq = apb2_freq / 5U;
1074 }
1075 break;
1076 case 2:
1077 if(0U == adcps2){
1078 adc_freq = apb2_freq / 6U;
1079 }else{
1080 adc_freq = apb2_freq / 7U;
1081 }
1082 break;
1083 case 3:
1084 if(0U == adcps2){
1085 adc_freq = apb2_freq / 8U;
1086 }else{
1087 adc_freq = apb2_freq / 9U;
1088 }
1089 break;
1090 default:
1091 break;
1092 }
1093 }
1094 ck_freq = adc_freq;
1095 break;
1096 case CK_CEC:
1097 /* calculate CEC clock frequency */
1098 if(RCU_CECSRC_LXTAL != (RCU_CFG2 & RCU_CFG2_CECSEL)){
1099 cec_freq = IRC8M_VALUE / 244U;
1100 }else{
1101 cec_freq = LXTAL_VALUE;
1102 }
1103 ck_freq = cec_freq;
1104 break;
1105 case CK_USART:
1106 /* calculate USART clock frequency */
1107 if(RCU_USART0SRC_CKAPB2 == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
1108 usart_freq = apb2_freq;
1109 }else if(RCU_USART0SRC_CKSYS == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
1110 usart_freq = cksys_freq;
1111 }else if(RCU_USART0SRC_LXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
1112 usart_freq = LXTAL_VALUE;
1113 }else if(RCU_USART0SRC_IRC8M == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
1114 usart_freq = IRC8M_VALUE;
1115 }else{
1116 }
1117 ck_freq = usart_freq;
1118 break;
1119 default:
1120 break;
1121 }
1122 return ck_freq;
1123 }
CK_APB1
Definition: gd32f3x0_rcu.h:456
SEL_HXTAL
#define SEL_HXTAL
Definition: gd32f3x0_rcu.c:16
RCU_USART0SRC_LXTAL
#define RCU_USART0SRC_LXTAL
Definition: gd32f3x0_rcu.h:661
CK_ADC
Definition: gd32f3x0_rcu.h:458
RCU_CFG2_USART0SEL
#define RCU_CFG2_USART0SEL
Definition: gd32f3x0_rcu.h:193
RCU_USART0SRC_CKSYS
#define RCU_USART0SRC_CKSYS
Definition: gd32f3x0_rcu.h:660
RCU_CFG2_IRC28MDIV
#define RCU_CFG2_IRC28MDIV
Definition: gd32f3x0_rcu.h:196
RCU_CECSRC_LXTAL
#define RCU_CECSRC_LXTAL
Definition: gd32f3x0_rcu.h:666
CK_USART
Definition: gd32f3x0_rcu.h:460
CK_SYS
Definition: gd32f3x0_rcu.h:454
CK_AHB
Definition: gd32f3x0_rcu.h:455
RCU_CFG2_ADCSEL
#define RCU_CFG2_ADCSEL
Definition: gd32f3x0_rcu.h:195
RCU_USART0SRC_CKAPB2
#define RCU_USART0SRC_CKAPB2
Definition: gd32f3x0_rcu.h:659
RCU_ADCSRC_APB2DIV
#define RCU_ADCSRC_APB2DIV
Definition: gd32f3x0_rcu.h:670
RCU_CFG1
#define RCU_CFG1
Definition: gd32f3x0_rcu.h:32
CK_APB2
Definition: gd32f3x0_rcu.h:457
CK_CEC
Definition: gd32f3x0_rcu.h:459
RCU_ADC_IRC28M_DIV1
#define RCU_ADC_IRC28M_DIV1
Definition: gd32f3x0_rcu.h:674
SEL_IRC8M
#define SEL_IRC8M
Definition: gd32f3x0_rcu.c:15
RCU_CFG2_CECSEL
#define RCU_CFG2_CECSEL
Definition: gd32f3x0_rcu.h:194
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
RCU_USART0SRC_IRC8M
#define RCU_USART0SRC_IRC8M
Definition: gd32f3x0_rcu.h:662
SEL_PLL
#define SEL_PLL
Definition: gd32f3x0_rcu.c:17
void rcu_deepsleep_voltage_set ( uint32_t dsvol )

set voltage in deep sleep mode

Parameters
[in] dsvol deep sleep mode voltage
  • RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V
  • RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V
  • RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V
  • RCU_DEEPSLEEP_V_0_7: the core voltage is 0.7V
[out] none
Return values
none

Definition at line 944 of file gd32f3x0_rcu.c.

945 {
946 /* reset the DSLPVS bits and set according to dsvol */
947 RCU_DSV &= ~RCU_DSV_DSLPVS;
948 RCU_DSV |= dsvol;
949 }
RCU_DSV_DSLPVS
#define RCU_DSV_DSLPVS
Definition: gd32f3x0_rcu.h:229
RCU_DSV
#define RCU_DSV
Definition: gd32f3x0_rcu.h:40
void rcu_deinit ( void )

deinitialize the RCU

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 29 of file gd32f3x0_rcu.c.

30 {
31 /* enable IRC8M */
32 RCU_CTL0 |= RCU_CTL0_IRC8MEN;
33 while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
34 }
35 /* reset RCU */
36 RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
37 RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
38 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
39 #if (defined(GD32F350))
40 RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC);
41 RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2);
42 #endif /* GD32F350 */
43 RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
44 RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL);
45 RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
46 RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
47 RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
48 RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
49 RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN;
50 RCU_INT = 0x00000000U;
51 RCU_ADDINT = 0x00000000U;
52 }
RCU_CFG1_PLLMF5
#define RCU_CFG1_PLLMF5
Definition: gd32f3x0_rcu.h:190
RCU_CFG2_ADCPSC2
#define RCU_CFG2_ADCPSC2
Definition: gd32f3x0_rcu.h:198
RCU_INT
#define RCU_INT
Definition: gd32f3x0_rcu.h:23
RCU_CFG1_PLLPRESEL
#define RCU_CFG1_PLLPRESEL
Definition: gd32f3x0_rcu.h:189
RCU_CFG2_USBFSPSC2
#define RCU_CFG2_USBFSPSC2
Definition: gd32f3x0_rcu.h:197
RCU_CTL1_IRC28MEN
#define RCU_CTL1_IRC28MEN
Definition: gd32f3x0_rcu.h:201
RCU_CFG2_USART0SEL
#define RCU_CFG2_USART0SEL
Definition: gd32f3x0_rcu.h:193
RCU_CFG0_ADCPSC
#define RCU_CFG0_ADCPSC
Definition: gd32f3x0_rcu.h:61
RCU_CFG2_IRC28MDIV
#define RCU_CFG2_IRC28MDIV
Definition: gd32f3x0_rcu.h:196
RCU_CFG0_APB1PSC
#define RCU_CFG0_APB1PSC
Definition: gd32f3x0_rcu.h:59
RCU_CFG0_PLLMF4
#define RCU_CFG0_PLLMF4
Definition: gd32f3x0_rcu.h:67
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
RCU_CFG2_ADCSEL
#define RCU_CFG2_ADCSEL
Definition: gd32f3x0_rcu.h:195
RCU_CTL1
#define RCU_CTL1
Definition: gd32f3x0_rcu.h:34
RCU_CFG1
#define RCU_CFG1
Definition: gd32f3x0_rcu.h:32
RCU_CTL0_PLLEN
#define RCU_CTL0_PLLEN
Definition: gd32f3x0_rcu.h:52
RCU_CFG0_PLLMF
#define RCU_CFG0_PLLMF
Definition: gd32f3x0_rcu.h:64
RCU_CFG0_SCS
#define RCU_CFG0_SCS
Definition: gd32f3x0_rcu.h:56
RCU_CTL0_IRC8MSTB
#define RCU_CTL0_IRC8MSTB
Definition: gd32f3x0_rcu.h:45
RCU_CTL0_IRC8MEN
#define RCU_CTL0_IRC8MEN
Definition: gd32f3x0_rcu.h:44
RCU_ADDCTL
#define RCU_ADDCTL
Definition: gd32f3x0_rcu.h:35
RCU_CFG0_CKOUTSEL
#define RCU_CFG0_CKOUTSEL
Definition: gd32f3x0_rcu.h:66
RCU_CFG2_CECSEL
#define RCU_CFG2_CECSEL
Definition: gd32f3x0_rcu.h:194
RCU_CFG1_PREDV
#define RCU_CFG1_PREDV
Definition: gd32f3x0_rcu.h:188
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
RCU_CFG0_USBFSPSC
#define RCU_CFG0_USBFSPSC
Definition: gd32f3x0_rcu.h:65
RCU_CTL0_CKMEN
#define RCU_CTL0_CKMEN
Definition: gd32f3x0_rcu.h:51
RCU_CFG0_APB2PSC
#define RCU_CFG0_APB2PSC
Definition: gd32f3x0_rcu.h:60
RCU_CTL0_HXTALEN
#define RCU_CTL0_HXTALEN
Definition: gd32f3x0_rcu.h:48
RCU_CFG0_PLLDV
#define RCU_CFG0_PLLDV
Definition: gd32f3x0_rcu.h:69
RCU_ADDCTL_IRC48MEN
#define RCU_ADDCTL_IRC48MEN
Definition: gd32f3x0_rcu.h:208
RCU_ADDINT
#define RCU_ADDINT
Definition: gd32f3x0_rcu.h:36
RCU_CTL0_HXTALBPS
#define RCU_CTL0_HXTALBPS
Definition: gd32f3x0_rcu.h:50
RCU_CFG0_CKOUTDIV
#define RCU_CFG0_CKOUTDIV
Definition: gd32f3x0_rcu.h:68
RCU_CFG0_PLLSEL
#define RCU_CFG0_PLLSEL
Definition: gd32f3x0_rcu.h:62
RCU_CFG0_AHBPSC
#define RCU_CFG0_AHBPSC
Definition: gd32f3x0_rcu.h:58
FlagStatus rcu_flag_get ( rcu_flag_enum flag )

get the clock stabilization and periphral reset flags

Parameters
[in] flag the clock stabilization and periphral reset flags, refer to rcu_flag_enum only one parameter can be selected which is shown as below:
  • RCU_FLAG_IRC40KSTB: IRC40K stabilization flag
  • RCU_FLAG_LXTALSTB: LXTAL stabilization flag
  • RCU_FLAG_IRC8MSTB: IRC8M stabilization flag
  • RCU_FLAG_HXTALSTB: HXTAL stabilization flag
  • RCU_FLAG_PLLSTB: PLL stabilization flag
  • RCU_FLAG_IRC28MSTB: IRC28M stabilization flag
  • RCU_FLAG_IRC48MSTB: IRC48M stabilization flag
  • RCU_FLAG_V12RST: V12 domain power reset flag
  • RCU_FLAG_OBLRST: option byte loader reset flag
  • RCU_FLAG_EPRST: external pin reset flag
  • RCU_FLAG_PORRST: power reset flag
  • RCU_FLAG_SWRST: software reset flag
  • RCU_FLAG_FWDGTRST: free watchdog timer reset flag
  • RCU_FLAG_WWDGTRST: window watchdog timer reset flag
  • RCU_FLAG_LPRST: low-power reset flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 559 of file gd32f3x0_rcu.c.

560 {
561 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){
562 return SET;
563 }else{
564 return RESET;
565 }
566 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_hxtal_clock_monitor_disable ( void )

disable the HXTAL clock monitor

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 886 of file gd32f3x0_rcu.c.

887 {
888 RCU_CTL0 &= ~RCU_CTL0_CKMEN;
889 }
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
RCU_CTL0_CKMEN
#define RCU_CTL0_CKMEN
Definition: gd32f3x0_rcu.h:51
void rcu_hxtal_clock_monitor_enable ( void )

enable the HXTAL clock monitor

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 875 of file gd32f3x0_rcu.c.

876 {
877 RCU_CTL0 |= RCU_CTL0_CKMEN;
878 }
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
RCU_CTL0_CKMEN
#define RCU_CTL0_CKMEN
Definition: gd32f3x0_rcu.h:51
void rcu_hxtal_prediv_config ( uint32_t hxtal_prediv )

configure the HXTAL divider used as input of PLL

Parameters
[in] hxtal_prediv HXTAL divider used as input of PLL
  • RCU_PLL_PREDVx(x=1..16): HXTAL or IRC48M divided x used as input of PLL
[out] none
Return values
none

Definition at line 511 of file gd32f3x0_rcu.c.

512 {
513 uint32_t prediv = 0U;
514 prediv = RCU_CFG1;
515 /* reset the HXTALPREDV bits and set according to hxtal_prediv */
516 prediv &= ~RCU_CFG1_PREDV;
517 RCU_CFG1 = (prediv | hxtal_prediv);
518 }
RCU_CFG1
#define RCU_CFG1
Definition: gd32f3x0_rcu.h:32
RCU_CFG1_PREDV
#define RCU_CFG1_PREDV
Definition: gd32f3x0_rcu.h:188
void rcu_interrupt_disable ( rcu_int_enum stab_int )

disable the stabilization interrupt

Parameters
[in] stab_int clock stabilization interrupt, refer to rcu_int_enum only one parameter can be selected which is shown as below:
  • RCU_INT_IRC40KSTB: IRC40K stabilization interrupt disable
  • RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable
  • RCU_INT_IRC8MSTB: IRC8M stabilization interrupt disable
  • RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable
  • RCU_INT_PLLSTB: PLL stabilization interrupt disable
  • RCU_INT_IRC28MSTB: IRC28M stabilization interrupt disable
  • RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable
[out] none
Return values
none

Definition at line 657 of file gd32f3x0_rcu.c.

658 {
659 RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int));
660 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_interrupt_enable ( rcu_int_enum stab_int )

enable the stabilization interrupt

Parameters
[in] stab_int clock stabilization interrupt, refer to rcu_int_enum only one parameter can be selected which is shown as below:
  • RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
  • RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
  • RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
  • RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
  • RCU_INT_PLLSTB: PLL stabilization interrupt enable
  • RCU_INT_IRC28MSTB: IRC28M stabilization interrupt enable
  • RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable
[out] none
Return values
none

Definition at line 637 of file gd32f3x0_rcu.c.

638 {
639 RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int));
640 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_interrupt_flag_clear ( rcu_int_flag_clear_enum int_flag_clear )

clear the interrupt flags

Parameters
[in] int_flag_clear clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum only one parameter can be selected which is shown as below:
  • RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear
  • RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear
  • RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear
  • RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear
  • RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear
  • RCU_INT_FLAG_IRC28MSTB_CLR: IRC28M stabilization interrupt flag clear
  • RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear
  • RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear
[out] none
Return values
none

Definition at line 618 of file gd32f3x0_rcu.c.

619 {
620 RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear));
621 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
FlagStatus rcu_interrupt_flag_get ( rcu_int_flag_enum int_flag )

get the clock stabilization interrupt and ckm flags

Parameters
[in] int_flag interrupt and ckm flags, refer to rcu_int_flag_enum only one parameter can be selected which is shown as below:
  • RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag
  • RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag
  • RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag
  • RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag
  • RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag
  • RCU_INT_FLAG_IRC28MSTB: IRC28M stabilization interrupt flag
  • RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag
  • RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 594 of file gd32f3x0_rcu.c.

595 {
596 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){
597 return SET;
598 }else{
599 return RESET;
600 }
601 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_irc28m_adjust_value_set ( uint8_t irc28m_adjval )

set the IRC28M adjust value

Parameters
[in] | irc28m_adjval | IRC28M adjust value, must be between 0 and 0x1F
[out] | none
Return values
none

Definition at line 912 of file gd32f3x0_rcu.c.

913 {
914 uint32_t adjust = 0U;
915 adjust = RCU_CTL1;
916 /* reset the IRC28MADJ bits and set according to irc28m_adjval */
917 adjust &= ~RCU_CTL1_IRC28MADJ;
918 RCU_CTL1 = (adjust | (((uint32_t)irc28m_adjval)<<3));
919 }
RCU_CTL1_IRC28MADJ
#define RCU_CTL1_IRC28MADJ
Definition: gd32f3x0_rcu.h:203
RCU_CTL1
#define RCU_CTL1
Definition: gd32f3x0_rcu.h:34
void rcu_irc8m_adjust_value_set ( uint8_t irc8m_adjval )

set the IRC8M adjust value

Parameters
[in] | irc8m_adjval | IRC8M adjust value, must be between 0 and 0x1F
[out] | none
Return values
none

Definition at line 897 of file gd32f3x0_rcu.c.

898 {
899 uint32_t adjust = 0U;
900 adjust = RCU_CTL0;
901 /* reset the IRC8MADJ bits and set according to irc8m_adjval */
902 adjust &= ~RCU_CTL0_IRC8MADJ;
903 RCU_CTL0 = (adjust | (((uint32_t)irc8m_adjval)<<3));
904 }
RCU_CTL0_IRC8MADJ
#define RCU_CTL0_IRC8MADJ
Definition: gd32f3x0_rcu.h:46
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
void rcu_lxtal_drive_capability_config ( uint32_t lxtal_dricap )

configure the LXTAL drive capability

Parameters
[in] lxtal_dricap drive capability of LXTAL
  • RCU_LXTAL_LOWDRI: lower driving capability
  • RCU_LXTAL_MED_LOWDRI: medium low driving capability
  • RCU_LXTAL_MED_HIGHDRI: medium high driving capability
  • RCU_LXTAL_HIGHDRI: higher driving capability
[out] none
Return values
none

Definition at line 530 of file gd32f3x0_rcu.c.

531 {
532 /* reset the LXTALDRI bits and set according to lxtal_dricap */
533 RCU_BDCTL &= ~RCU_BDCTL_LXTALDRI;
534 RCU_BDCTL |= lxtal_dricap;
535 }
RCU_BDCTL_LXTALDRI
#define RCU_BDCTL_LXTALDRI
Definition: gd32f3x0_rcu.h:160
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f3x0_rcu.h:29
void rcu_osci_bypass_mode_disable ( rcu_osci_type_enum osci )

disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum
  • RCU_HXTAL: HXTAL
  • RCU_LXTAL: LXTAL
[out] none
Return values
none

Definition at line 842 of file gd32f3x0_rcu.c.

843 {
844 uint32_t reg;
845 switch(osci){
846 case RCU_HXTAL:
847 /* HXTALEN must be reset before disable the oscillator bypass mode */
848 reg = RCU_CTL0;
849 RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
850 RCU_CTL0 = (reg & (~RCU_CTL0_HXTALBPS));
851 break;
852 case RCU_LXTAL:
853 /* LXTALEN must be reset before disable the oscillator bypass mode */
854 reg = RCU_BDCTL;
855 RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
856 RCU_BDCTL = (reg & (~RCU_BDCTL_LXTALBPS));
857 break;
858 case RCU_IRC8M:
859 case RCU_IRC28M:
860 case RCU_IRC48M:
861 case RCU_IRC40K:
862 case RCU_PLL_CK:
863 break;
864 default:
865 break;
866 }
867 }
RCU_IRC48M
Definition: gd32f3x0_rcu.h:446
RCU_BDCTL_LXTALEN
#define RCU_BDCTL_LXTALEN
Definition: gd32f3x0_rcu.h:157
RCU_HXTAL
Definition: gd32f3x0_rcu.h:442
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
RCU_IRC28M
Definition: gd32f3x0_rcu.h:445
RCU_BDCTL_LXTALBPS
#define RCU_BDCTL_LXTALBPS
Definition: gd32f3x0_rcu.h:159
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f3x0_rcu.h:29
RCU_IRC8M
Definition: gd32f3x0_rcu.h:444
RCU_PLL_CK
Definition: gd32f3x0_rcu.h:448
RCU_CTL0_HXTALEN
#define RCU_CTL0_HXTALEN
Definition: gd32f3x0_rcu.h:48
RCU_CTL0_HXTALBPS
#define RCU_CTL0_HXTALBPS
Definition: gd32f3x0_rcu.h:50
RCU_LXTAL
Definition: gd32f3x0_rcu.h:443
RCU_IRC40K
Definition: gd32f3x0_rcu.h:447
void rcu_osci_bypass_mode_enable ( rcu_osci_type_enum osci )

enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum
  • RCU_HXTAL: HXTAL
  • RCU_LXTAL: LXTAL
[out] none
Return values
none

Definition at line 807 of file gd32f3x0_rcu.c.

808 {
809 uint32_t reg;
810 switch(osci){
811 case RCU_HXTAL:
812 /* HXTALEN must be reset before enable the oscillator bypass mode */
813 reg = RCU_CTL0;
814 RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
815 RCU_CTL0 = (reg | RCU_CTL0_HXTALBPS);
816 break;
817 case RCU_LXTAL:
818 /* LXTALEN must be reset before enable the oscillator bypass mode */
819 reg = RCU_BDCTL;
820 RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
821 RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
822 break;
823 case RCU_IRC8M:
824 case RCU_IRC28M:
825 case RCU_IRC48M:
826 case RCU_IRC40K:
827 case RCU_PLL_CK:
828 break;
829 default:
830 break;
831 }
832 }
RCU_IRC48M
Definition: gd32f3x0_rcu.h:446
RCU_BDCTL_LXTALEN
#define RCU_BDCTL_LXTALEN
Definition: gd32f3x0_rcu.h:157
RCU_HXTAL
Definition: gd32f3x0_rcu.h:442
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
RCU_IRC28M
Definition: gd32f3x0_rcu.h:445
RCU_BDCTL_LXTALBPS
#define RCU_BDCTL_LXTALBPS
Definition: gd32f3x0_rcu.h:159
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f3x0_rcu.h:29
RCU_IRC8M
Definition: gd32f3x0_rcu.h:444
RCU_PLL_CK
Definition: gd32f3x0_rcu.h:448
RCU_CTL0_HXTALEN
#define RCU_CTL0_HXTALEN
Definition: gd32f3x0_rcu.h:48
RCU_CTL0_HXTALBPS
#define RCU_CTL0_HXTALBPS
Definition: gd32f3x0_rcu.h:50
RCU_LXTAL
Definition: gd32f3x0_rcu.h:443
RCU_IRC40K
Definition: gd32f3x0_rcu.h:447
void rcu_osci_off ( rcu_osci_type_enum osci )

turn off the oscillator

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum
  • RCU_HXTAL: HXTAL
  • RCU_LXTAL: LXTAL
  • RCU_IRC8M: IRC8M
  • RCU_IRC28M: IRC28M
  • RCU_IRC48M: IRC48M
  • RCU_IRC40K: IRC40K
  • RCU_PLL_CK: PLL
[out] none
Return values
none

Definition at line 794 of file gd32f3x0_rcu.c.

795 {
796 RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci));
797 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_osci_on ( rcu_osci_type_enum osci )

turn on the oscillator

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum
  • RCU_HXTAL: HXTAL
  • RCU_LXTAL: LXTAL
  • RCU_IRC8M: IRC8M
  • RCU_IRC28M: IRC28M
  • RCU_IRC48M: IRC48M
  • RCU_IRC40K: IRC40K
  • RCU_PLL_CK: PLL
[out] none
Return values
none

Definition at line 776 of file gd32f3x0_rcu.c.

777 {
778 RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));
779 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
ErrStatus rcu_osci_stab_wait ( rcu_osci_type_enum osci )

wait until oscillator stabilization flags is SET

Parameters
[in] osci oscillator types, refer to rcu_osci_type_enum
  • RCU_HXTAL: HXTAL
  • RCU_LXTAL: LXTAL
  • RCU_IRC8M: IRC8M
  • RCU_IRC28M: IRC28M
  • RCU_IRC48M: IRC48M
  • RCU_IRC40K: IRC40K
  • RCU_PLL_CK: PLL
[out] none
Return values
ErrStatus SUCCESS or ERROR

Definition at line 675 of file gd32f3x0_rcu.c.

676 {
677 uint32_t stb_cnt = 0U;
678 ErrStatus reval = ERROR;
679 FlagStatus osci_stat = RESET;
680 switch(osci){
681 case RCU_HXTAL:
682 /* wait until HXTAL is stabilization and osci_stat is not more than timeout */
683 while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){
684 osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
685 stb_cnt++;
686 }
687 if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){
688 reval = SUCCESS;
689 }
690 break;
691 /* wait LXTAL stable */
692 case RCU_LXTAL:
693 while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){
694 osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
695 stb_cnt++;
696 }
697
698 /* check whether flag is set or not */
699 if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){
700 reval = SUCCESS;
701 }
702 break;
703
704 /* wait IRC8M stable */
705 case RCU_IRC8M:
706 while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){
707 osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
708 stb_cnt++;
709 }
710
711 /* check whether flag is set or not */
712 if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){
713 reval = SUCCESS;
714 }
715 break;
716
717 /* wait IRC48M stable */
718 case RCU_IRC48M:
719 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
720 osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB);
721 stb_cnt++;
722 }
723
724 /* check whether flag is set or not */
725 if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)){
726 reval = SUCCESS;
727 }
728 break;
729
730 /* wait IRC40K stable */
731 case RCU_IRC40K:
732 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
733 osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
734 stb_cnt++;
735 }
736
737 /* check whether flag is set or not */
738 if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){
739 reval = SUCCESS;
740 }
741 break;
742
743 /* wait PLL stable */
744 case RCU_PLL_CK:
745 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
746 osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
747 stb_cnt++;
748 }
749
750 /* check whether flag is set or not */
751 if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){
752 reval = SUCCESS;
753 }
754 break;
755
756 default:
757 break;
758 }
759 /* return value */
760 return reval;
761 }
RCU_FLAG_HXTALSTB
Definition: gd32f3x0_rcu.h:371
RCU_FLAG_IRC40KSTB
Definition: gd32f3x0_rcu.h:368
RCU_IRC48M
Definition: gd32f3x0_rcu.h:446
RCU_HXTAL
Definition: gd32f3x0_rcu.h:442
RCU_FLAG_LXTALSTB
Definition: gd32f3x0_rcu.h:369
RCU_FLAG_PLLSTB
Definition: gd32f3x0_rcu.h:372
OSC_STARTUP_TIMEOUT
#define OSC_STARTUP_TIMEOUT
Definition: gd32f3x0_rcu.c:20
RCU_IRC8M
Definition: gd32f3x0_rcu.h:444
rcu_flag_get
FlagStatus rcu_flag_get(rcu_flag_enum flag)
get the clock stabilization and periphral reset flags
Definition: gd32f3x0_rcu.c:559
RCU_PLL_CK
Definition: gd32f3x0_rcu.h:448
RCU_FLAG_IRC8MSTB
Definition: gd32f3x0_rcu.h:370
LXTAL_STARTUP_TIMEOUT
#define LXTAL_STARTUP_TIMEOUT
Definition: gd32f3x0_rcu.c:21
RCU_LXTAL
Definition: gd32f3x0_rcu.h:443
RCU_IRC40K
Definition: gd32f3x0_rcu.h:447
RCU_FLAG_IRC48MSTB
Definition: gd32f3x0_rcu.h:374
void rcu_periph_clock_disable ( rcu_periph_enum periph )

disable the peripherals clock

Parameters
[in] periph RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOx (x=A,B,C,D,F): GPIO ports clock
  • RCU_DMA: DMA clock
  • RCU_CRC: CRC clock
  • RCU_TSI: TSI clock
  • RCU_CFGCMP: CFGCMP clock
  • RCU_ADC: ADC clock
  • RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock (RCU_TIMER5 only for GD32F350)
  • RCU_SPIx (x=0,1,2): SPI clock
  • RCU_USARTx (x=0,1): USART clock
  • RCU_WWDGT: WWDGT clock
  • RCU_I2Cx (x=0,1,2): I2C clock
  • RCU_USBFS: USBFS clock (only for GD32F350)
  • RCU_PMU: PMU clock
  • RCU_DAC: DAC clock (only for GD32F350)
  • RCU_CEC: CEC clock (only for GD32F350)
  • RCU_CTC: CTC clock
  • RCU_RTC: RTC clock
[out] none
Return values
none

Definition at line 107 of file gd32f3x0_rcu.c.

108 {
109 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
110 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_periph_clock_enable ( rcu_periph_enum periph )

enable the peripherals clock

Parameters
[in] periph RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOx (x=A,B,C,D,F): GPIO ports clock
  • RCU_DMA: DMA clock
  • RCU_CRC: CRC clock
  • RCU_TSI: TSI clock
  • RCU_CFGCMP: CFGCMP clock
  • RCU_ADC: ADC clock
  • RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock (RCU_TIMER5 only for GD32F350)
  • RCU_SPIx (x=0,1,2): SPI clock
  • RCU_USARTx (x=0,1): USART clock
  • RCU_WWDGT: WWDGT clock
  • RCU_I2Cx (x=0,1,2): I2C clock
  • RCU_USBFS: USBFS clock (only for GD32F350)
  • RCU_PMU: PMU clock
  • RCU_DAC: DAC clock (only for GD32F350)
  • RCU_CEC: CEC clock (only for GD32F350)
  • RCU_CTC: CTC clock
  • RCU_RTC: RTC clock
[out] none
Return values
none

Definition at line 78 of file gd32f3x0_rcu.c.

79 {
80 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
81 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_periph_clock_sleep_disable ( rcu_periph_sleep_enum periph )

disable the peripherals clock when sleep mode

Parameters
[in] periph RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below:
  • RCU_FMC_SLP: FMC clock
  • RCU_SRAM_SLP: SRAM clock
[out] none
Return values
none

Definition at line 135 of file gd32f3x0_rcu.c.

136 {
137 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
138 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_periph_clock_sleep_enable ( rcu_periph_sleep_enum periph )

enable the peripherals clock when sleep mode

Parameters
[in] periph RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below:
  • RCU_FMC_SLP: FMC clock
  • RCU_SRAM_SLP: SRAM clock
[out] none
Return values
none

Definition at line 121 of file gd32f3x0_rcu.c.

122 {
123 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
124 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_periph_reset_disable ( rcu_periph_reset_enum periph_reset )

disable reset the peripheral

Parameters
[in] periph_reset RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOxRST (x=A,B,C,D,F): reset GPIO ports
  • RCU_TSIRST: reset TSI
  • RCU_CFGCMPRST: reset CFGCMP
  • RCU_ADCRST: reset ADC
  • RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER (RCU_TIMER5 only for GD32F350)
  • RCU_SPIxRST (x=0,1,2): reset SPI
  • RCU_USARTxRST (x=0,1): reset USART
  • RCU_WWDGTRST: reset WWDGT
  • RCU_I2CxRST (x=0,1,2): reset I2C
  • RCU_USBFSRST: reset USBFS (only for GD32F350)
  • RCU_PMURST: reset PMU
  • RCU_DACRST: reset DAC (only for GD32F350)
  • RCU_CECRST: reset CEC (only for GD32F350)
  • RCU_CTCRST: reset CTC
[out] none
Return values
none

Definition at line 186 of file gd32f3x0_rcu.c.

187 {
188 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset));
189 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_periph_reset_enable ( rcu_periph_reset_enum periph_reset )

reset the peripherals

Parameters
[in] periph_reset RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below:
  • RCU_GPIOxRST (x=A,B,C,D,F): reset GPIO ports
  • RCU_TSIRST: reset TSI
  • RCU_CFGCMPRST: reset CFGCMP
  • RCU_ADCRST: reset ADC
  • RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER (RCU_TIMER5 only for GD32F350)
  • RCU_SPIxRST (x=0,1,2): reset SPI
  • RCU_USARTxRST (x=0,1): reset USART
  • RCU_WWDGTRST: reset WWDGT
  • RCU_I2CxRST (x=0,1,2): reset I2C
  • RCU_USBFSRST: reset USBFS (only for GD32F350)
  • RCU_PMURST: reset PMU
  • RCU_DACRST: reset DAC (only for GD32F350)
  • RCU_CECRST: reset CEC (only for GD32F350)
  • RCU_CTCRST: reset CTC
[out] none
Return values
none

Definition at line 160 of file gd32f3x0_rcu.c.

161 {
162 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
163 }
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
void rcu_pll_config | ( | uint32_t | pll_src,
 |  | uint32_t | pll_mul
 | ) |  |

configure the PLL clock source selection and PLL multiply factor

Parameters
[in] pll_src PLL clock source selection
  • RCU_PLLSRC_IRC8M_DIV2: select CK_IRC8M/2 as PLL source clock
  • RCU_PLLSRC_HXTAL_IRC48M: select HXTAL or IRC48M as PLL source clock
[in] pll_mul PLL multiply factor
  • RCU_PLL_MULx(x=2..64): PLL source clock * x
[out] none
Return values
none

Definition at line 447 of file gd32f3x0_rcu.c.

448 {
449 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
450 RCU_CFG1 &= ~(RCU_CFG1_PLLMF5);
451 RCU_CFG0 |= (pll_src | (pll_mul & (~RCU_CFG1_PLLMF5)));
452 RCU_CFG1 |= (pll_mul & RCU_CFG1_PLLMF5);
453 }
RCU_CFG1_PLLMF5
#define RCU_CFG1_PLLMF5
Definition: gd32f3x0_rcu.h:190
RCU_CFG1
#define RCU_CFG1
Definition: gd32f3x0_rcu.h:32
RCU_CFG0_PLLMF
#define RCU_CFG0_PLLMF
Definition: gd32f3x0_rcu.h:64
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG0_PLLSEL
#define RCU_CFG0_PLLSEL
Definition: gd32f3x0_rcu.h:62
void rcu_pll_preselection_config ( uint32_t pll_presel )

configure the PLL clock source preselection

Parameters
[in] pll_presel PLL clock source preselection
  • RCU_PLLPRESEL_IRC48M: select IRC48M as PLL preselection clock
  • RCU_PLLPRESEL_HXTAL: select HXTAL as PLL preselection clock
[out] none
Return values
none

Definition at line 431 of file gd32f3x0_rcu.c.

432 {
433 RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL);
434 RCU_CFG1 |= pll_presel;
435 }
RCU_CFG1_PLLPRESEL
#define RCU_CFG1_PLLPRESEL
Definition: gd32f3x0_rcu.h:189
RCU_CFG1
#define RCU_CFG1
Definition: gd32f3x0_rcu.h:32
void rcu_rtc_clock_config ( uint32_t rtc_clock_source )

configure the RTC clock source selection

Parameters
[in] rtc_clock_source RTC clock source selection
  • RCU_RTCSRC_NONE: no clock selected
  • RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock
  • RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock
  • RCU_RTCSRC_HXTAL_DIV32: CK_HXTAL/32 selected as RTC source clock
[out] none
Return values
none

Definition at line 497 of file gd32f3x0_rcu.c.

498 {
499 /* reset the RTCSRC bits and set according to rtc_clock_source */
500 RCU_BDCTL &= ~RCU_BDCTL_RTCSRC;
501 RCU_BDCTL |= rtc_clock_source;
502 }
RCU_BDCTL_RTCSRC
#define RCU_BDCTL_RTCSRC
Definition: gd32f3x0_rcu.h:161
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f3x0_rcu.h:29
void rcu_system_clock_source_config ( uint32_t ck_sys )

configure the system clock source

Parameters
[in] ck_sys system clock source select only one parameter can be selected which is shown as below:
  • RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source
  • RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source
  • RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source
[out] none
Return values
none

Definition at line 223 of file gd32f3x0_rcu.c.

224 {
225 uint32_t cksys_source = 0U;
226 cksys_source = RCU_CFG0;
227 /* reset the SCS bits and set according to ck_sys */
228 cksys_source &= ~RCU_CFG0_SCS;
229 RCU_CFG0 = (ck_sys | cksys_source);
230 }
RCU_CFG0_SCS
#define RCU_CFG0_SCS
Definition: gd32f3x0_rcu.h:56
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
uint32_t rcu_system_clock_source_get ( void )

get the system clock source

Parameters
[in] | none
[out] | none
Return values
which clock is selected as CK_SYS source
  • RCU_SCSS_IRC8M: select CK_IRC8M as the CK_SYS source
  • RCU_SCSS_HXTAL: select CK_HXTAL as the CK_SYS source
  • RCU_SCSS_PLL: select CK_PLL as the CK_SYS source

Definition at line 241 of file gd32f3x0_rcu.c.

242 {
243 return (RCU_CFG0 & RCU_CFG0_SCSS);
244 }
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG0_SCSS
#define RCU_CFG0_SCSS
Definition: gd32f3x0_rcu.h:57
void rcu_usart_clock_config ( uint32_t ck_usart )

configure the USART clock source selection

Parameters
[in] ck_usart USART clock source selection
  • RCU_USART0SRC_CKAPB2: CK_USART0 select CK_APB2
  • RCU_USART0SRC_CKSYS: CK_USART0 select CK_SYS
  • RCU_USART0SRC_LXTAL: CK_USART0 select CK_LXTAL
  • RCU_USART0SRC_IRC8M: CK_USART0 select CK_IRC8M
[out] none
Return values
none

Definition at line 465 of file gd32f3x0_rcu.c.

466 {
467 /* reset the USART0SEL bits and set according to ck_usart */
468 RCU_CFG2 &= ~RCU_CFG2_USART0SEL;
469 RCU_CFG2 |= ck_usart;
470 }
RCU_CFG2_USART0SEL
#define RCU_CFG2_USART0SEL
Definition: gd32f3x0_rcu.h:193
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
void rcu_usbfs_clock_config ( uint32_t ck_usbfs )

configure the USBFS clock prescaler selection

Parameters
[in] ck_usbfs USBFS clock prescaler selection
  • RCU_USBFS_CKPLL_DIV1_5: select CK_PLL/1.5 as CK_USBFS
  • RCU_USBFS_CKPLL_DIV1: select CK_PLL as CK_USBFS
  • RCU_USBFS_CKPLL_DIV2_5: select CK_PLL/2.5 as CK_USBFS
  • RCU_USBFS_CKPLL_DIV2: select CK_PLL/2 as CK_USBFS
  • RCU_USBFS_CKPLL_DIV3: select CK_PLL/3 as CK_USBFS
  • RCU_USBFS_CKPLL_DIV3_5: select CK_PLL/3.5 as CK_USBFS
[out] none
Return values
none

Definition at line 387 of file gd32f3x0_rcu.c.

388 {
389 /* reset the USBFSPSC bits and set according to ck_usbfs */
390 RCU_CFG0 &= ~RCU_CFG0_USBFSPSC;
391 RCU_CFG2 &= ~RCU_CFG2_USBFSPSC2;
392
393 RCU_CFG0 |= (ck_usbfs & (~RCU_CFG2_USBFSPSC2));
394 RCU_CFG2 |= (ck_usbfs & RCU_CFG2_USBFSPSC2);
395 }
RCU_CFG2_USBFSPSC2
#define RCU_CFG2_USBFSPSC2
Definition: gd32f3x0_rcu.h:197
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
RCU_CFG0_USBFSPSC
#define RCU_CFG0_USBFSPSC
Definition: gd32f3x0_rcu.h:65
void rcu_voltage_key_unlock ( void )

unlock the voltage key

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 927 of file gd32f3x0_rcu.c.

928 {
929 /* reset the KEY bits and set 0x1A2B3C4D */
930 RCU_VKEY &= ~RCU_VKEY_KEY;
931 RCU_VKEY |= RCU_VKEY_UNLOCK;
932 }
RCU_VKEY
#define RCU_VKEY
Definition: gd32f3x0_rcu.h:39
RCU_VKEY_UNLOCK
#define RCU_VKEY_UNLOCK
Definition: gd32f3x0_rcu.h:237
RCU_VKEY_KEY
#define RCU_VKEY_KEY
Definition: gd32f3x0_rcu.h:226
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_rtc.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_rtc.c File Reference

RTC driver. More...

#include "gd32f3x0_rtc.h"

Go to the source code of this file.

Functions

ErrStatus | rtc_deinit (void)
reset most of the RTC registers More...
ErrStatus | rtc_init (rtc_parameter_struct *rtc_initpara_struct)
initialize RTC registers More...
ErrStatus | rtc_init_mode_enter (void)
enter RTC init mode More...
void | rtc_init_mode_exit (void)
exit RTC init mode More...
ErrStatus | rtc_register_sync_wait (void)
wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated More...
void | rtc_current_time_get (rtc_parameter_struct *rtc_initpara_struct)
get current time and date More...
uint32_t | rtc_subsecond_get (void)
get current subsecond value More...
void | rtc_alarm_config (rtc_alarm_struct *rtc_alarm_time)
configure RTC alarm More...
void | rtc_alarm_subsecond_config (uint32_t mask_subsecond, uint32_t subsecond)
configure subsecond of RTC alarm More...
void | rtc_alarm_enable (void)
enable RTC alarm More...
ErrStatus | rtc_alarm_disable (void)
disable RTC alarm More...
void | rtc_alarm_get (rtc_alarm_struct *rtc_alarm_time)
get RTC alarm More...
uint32_t | rtc_alarm_subsecond_get (void)
get RTC alarm subsecond More...
void | rtc_timestamp_enable (uint32_t edge)
enable RTC time-stamp More...
void | rtc_timestamp_disable (void)
disable RTC time-stamp More...
void | rtc_timestamp_get (rtc_timestamp_struct *rtc_timestamp)
get RTC timestamp time and date More...
uint32_t | rtc_timestamp_subsecond_get (void)
get RTC time-stamp subsecond More...
void | rtc_tamper_enable (rtc_tamper_struct *rtc_tamper)
enable RTC tamper More...
void | rtc_tamper_disable (uint32_t source)
disable RTC tamper More...
void | rtc_interrupt_enable (uint32_t interrupt)
enable specified RTC interrupt More...
void | rtc_interrupt_disable (uint32_t interrupt)
disble specified RTC interrupt More...
FlagStatus | rtc_flag_get (uint32_t flag)
check specified flag More...
void | rtc_flag_clear (uint32_t flag)
clear specified flag More...
void | rtc_alter_output_config (uint32_t source, uint32_t mode)
configure rtc alternate output source More...
void | rtc_hour_adjust (uint32_t operation)
ajust the daylight saving time by adding or substracting one hour from the current time More...
void | rtc_bypass_shadow_enable (void)
enable RTC bypass shadow registers function More...
void | rtc_bypass_shadow_disable (void)
disable RTC bypass shadow registers function More...
ErrStatus | rtc_refclock_detection_enable (void)
enable RTC reference clock detection function More...
ErrStatus | rtc_refclock_detection_disable (void)
disable RTC reference clock detection function More...
ErrStatus | rtc_second_ajust (uint32_t add, uint32_t minus)
ajust RTC second or subsecond value of current time More...
ErrStatus | rtc_calibration_config (uint32_t window, uint32_t plus, uint32_t minus)
configure RTC calibration register More...

Detailed Description

RTC driver.

Definition in file gd32f3x0_rtc.c.

Function Documentation

void rtc_alarm_config ( rtc_alarm_struct * rtc_alarm_time )

configure RTC alarm

Parameters
[in] | rtc_alarm_time | pointer to a rtc_alarm_struct structure which contains parameters for RTC alarm configuration members of the structure and the member values are shown as below: rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format rtc_alarm_minute: 0x0 - 0x59(BCD format) rtc_alarm_second: 0x0 - 0x59(BCD format) rtc_am_pm: RTC_AM, RTC_PM
[out] | none
Return values
none

Definition at line 291 of file gd32f3x0_rtc.c.

292 {
293 uint32_t reg_alrm0td = 0x00U;
294
295 reg_alrm0td = (rtc_alarm_time->rtc_alarm_mask | \
296 rtc_alarm_time->rtc_weekday_or_date | \
297 rtc_alarm_time->rtc_am_pm | \
298 ALRM0TD_DAY(rtc_alarm_time->rtc_alarm_day) | \
299 ALRM0TD_HR(rtc_alarm_time->rtc_alarm_hour) | \
300 ALRM0TD_MN(rtc_alarm_time->rtc_alarm_minute) | \
301 ALRM0TD_SC(rtc_alarm_time->rtc_alarm_second));
302
303 /* disable the write protection */
304 RTC_WPK = RTC_UNLOCK_KEY1;
305 RTC_WPK = RTC_UNLOCK_KEY2;
306
307 RTC_ALRM0TD = (uint32_t)reg_alrm0td;
308
309 /* enable the write protection */
310 RTC_WPK = RTC_LOCK_KEY;
311 }
rtc_alarm_struct::rtc_alarm_hour
uint8_t rtc_alarm_hour
Definition: gd32f3x0_rtc.h:207
ALRM0TD_HR
#define ALRM0TD_HR(regval)
Definition: gd32f3x0_rtc.h:312
rtc_alarm_struct::rtc_alarm_mask
uint32_t rtc_alarm_mask
Definition: gd32f3x0_rtc.h:204
ALRM0TD_MN
#define ALRM0TD_MN(regval)
Definition: gd32f3x0_rtc.h:309
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
rtc_alarm_struct::rtc_alarm_day
uint8_t rtc_alarm_day
Definition: gd32f3x0_rtc.h:206
RTC_ALRM0TD
#define RTC_ALRM0TD
Definition: gd32f3x0_rtc.h:26
ALRM0TD_DAY
#define ALRM0TD_DAY(regval)
Definition: gd32f3x0_rtc.h:315
ALRM0TD_SC
#define ALRM0TD_SC(regval)
Definition: gd32f3x0_rtc.h:306
rtc_alarm_struct::rtc_alarm_minute
uint8_t rtc_alarm_minute
Definition: gd32f3x0_rtc.h:208
rtc_alarm_struct::rtc_alarm_second
uint8_t rtc_alarm_second
Definition: gd32f3x0_rtc.h:209
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
ErrStatus rtc_alarm_disable ( void )

disable RTC alarm

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 372 of file gd32f3x0_rtc.c.

373 {
374 volatile uint32_t time_index = RTC_ALRM0WF_TIMEOUT;
375 ErrStatus error_status = ERROR;
376 uint32_t flag_status = RESET;
377
378 /* disable the write protection */
379 RTC_WPK = RTC_UNLOCK_KEY1;
380 RTC_WPK = RTC_UNLOCK_KEY2;
381
382 /* clear the state of alarm */
383 RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN);
384
385 /* wait until ALRM0WF flag to be set after the alarm is disabled */
386 do{
387 flag_status = RTC_STAT & RTC_STAT_ALRM0WF;
388 }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status));
389
390 if((uint32_t)RESET != flag_status){
391 error_status = SUCCESS;
392 }
393
394 /* enable the write protection */
395 RTC_WPK = RTC_LOCK_KEY;
396
397 return error_status;
398 }
RTC_CTL_ALRM0EN
#define RTC_CTL_ALRM0EN
Definition: gd32f3x0_rtc.h:66
RTC_STAT_ALRM0WF
#define RTC_STAT_ALRM0WF
Definition: gd32f3x0_rtc.h:79
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
RTC_ALRM0WF_TIMEOUT
#define RTC_ALRM0WF_TIMEOUT
Definition: gd32f3x0_rtc.h:451
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_alarm_enable ( void )

enable RTC alarm

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 354 of file gd32f3x0_rtc.c.

355 {
356 /* disable the write protection */
357 RTC_WPK = RTC_UNLOCK_KEY1;
358 RTC_WPK = RTC_UNLOCK_KEY2;
359
360 RTC_CTL |= RTC_CTL_ALRM0EN;
361
362 /* enable the write protection */
363 RTC_WPK = RTC_LOCK_KEY;
364 }
RTC_CTL_ALRM0EN
#define RTC_CTL_ALRM0EN
Definition: gd32f3x0_rtc.h:66
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_alarm_get ( rtc_alarm_struct * rtc_alarm_time )

get RTC alarm

Parameters
[in] | none
[out] | rtc_alarm_time | pointer to a rtc_alarm_struct structure which contains parameters for RTC alarm configuration members of the structure and the member values are shown as below: rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format rtc_alarm_minute: 0x0 - 0x59(BCD format) rtc_alarm_second: 0x0 - 0x59(BCD format) rtc_am_pm: RTC_AM, RTC_PM
Return values
none

Definition at line 418 of file gd32f3x0_rtc.c.

419 {
420 uint32_t reg_alrm0td = 0x00U;
421
422 /* get the value of RTC_ALRM0TD register */
423 reg_alrm0td = RTC_ALRM0TD;
424
425 /* get alarm parameters and construct the rtc_alarm_struct structure */
426 rtc_alarm_time->rtc_alarm_mask = reg_alrm0td & RTC_ALARM_ALL_MASK;
427 rtc_alarm_time->rtc_am_pm = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_PM);
428 rtc_alarm_time->rtc_weekday_or_date = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_DOWS);
429 rtc_alarm_time->rtc_alarm_day = (uint8_t)GET_ALRM0TD_DAY(reg_alrm0td);
430 rtc_alarm_time->rtc_alarm_hour = (uint8_t)GET_ALRM0TD_HR(reg_alrm0td);
431 rtc_alarm_time->rtc_alarm_minute = (uint8_t)GET_ALRM0TD_MN(reg_alrm0td);
432 rtc_alarm_time->rtc_alarm_second = (uint8_t)GET_ALRM0TD_SC(reg_alrm0td);
433 }
GET_ALRM0TD_SC
#define GET_ALRM0TD_SC(regval)
Definition: gd32f3x0_rtc.h:307
rtc_alarm_struct::rtc_alarm_hour
uint8_t rtc_alarm_hour
Definition: gd32f3x0_rtc.h:207
RTC_ALRM0TD_PM
#define RTC_ALRM0TD_PM
Definition: gd32f3x0_rtc.h:105
GET_ALRM0TD_MN
#define GET_ALRM0TD_MN(regval)
Definition: gd32f3x0_rtc.h:310
rtc_alarm_struct::rtc_alarm_mask
uint32_t rtc_alarm_mask
Definition: gd32f3x0_rtc.h:204
RTC_ALRM0TD_DOWS
#define RTC_ALRM0TD_DOWS
Definition: gd32f3x0_rtc.h:109
rtc_alarm_struct::rtc_alarm_day
uint8_t rtc_alarm_day
Definition: gd32f3x0_rtc.h:206
RTC_ALRM0TD
#define RTC_ALRM0TD
Definition: gd32f3x0_rtc.h:26
rtc_alarm_struct::rtc_alarm_minute
uint8_t rtc_alarm_minute
Definition: gd32f3x0_rtc.h:208
rtc_alarm_struct::rtc_weekday_or_date
uint32_t rtc_weekday_or_date
Definition: gd32f3x0_rtc.h:205
GET_ALRM0TD_DAY
#define GET_ALRM0TD_DAY(regval)
Definition: gd32f3x0_rtc.h:316
RTC_ALARM_ALL_MASK
#define RTC_ALARM_ALL_MASK
Definition: gd32f3x0_rtc.h:323
rtc_alarm_struct::rtc_alarm_second
uint8_t rtc_alarm_second
Definition: gd32f3x0_rtc.h:209
rtc_alarm_struct::rtc_am_pm
uint32_t rtc_am_pm
Definition: gd32f3x0_rtc.h:210
GET_ALRM0TD_HR
#define GET_ALRM0TD_HR(regval)
Definition: gd32f3x0_rtc.h:313
void rtc_alarm_subsecond_config | ( | uint32_t | mask_subsecond,
 |  | uint32_t | subsecond
 | ) |  |

configure subsecond of RTC alarm

Parameters
[in] mask_subsecond alarm subsecond mask
  • RTC_MASKSSC_0_14: mask alarm subsecond configuration
  • RTC_MASKSSC_1_14: mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared
  • RTC_MASKSSC_2_14: mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared
  • RTC_MASKSSC_3_14: mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared
  • RTC_MASKSSC_4_14: mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared
  • RTC_MASKSSC_5_14: mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared
  • RTC_MASKSSC_6_14: mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared
  • RTC_MASKSSC_7_14: mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared
  • RTC_MASKSSC_8_14: mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared
  • RTC_MASKSSC_9_14: mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared
  • RTC_MASKSSC_10_14: mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared
  • RTC_MASKSSC_11_14: mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared
  • RTC_MASKSSC_12_14: mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared
  • RTC_MASKSSC_13_14: mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared
  • RTC_MASKSSC_14: mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared
  • RTC_MASKSSC_NONE: mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared
[in] | subsecond | alarm subsecond value(0x000 - 0x7FFF)
[out] | none
Return values
none

Definition at line 336 of file gd32f3x0_rtc.c.

337 {
338 /* disable the write protection */
339 RTC_WPK = RTC_UNLOCK_KEY1;
340 RTC_WPK = RTC_UNLOCK_KEY2;
341
342 RTC_ALRM0SS = mask_subsecond | subsecond;
343
344 /* enable the write protection */
345 RTC_WPK = RTC_LOCK_KEY;
346 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_ALRM0SS
#define RTC_ALRM0SS
Definition: gd32f3x0_rtc.h:35
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
uint32_t rtc_alarm_subsecond_get ( void )

get RTC alarm subsecond

Parameters
[in] | none
[out] | none
Return values
RTC alarm subsecond value

Definition at line 441 of file gd32f3x0_rtc.c.

442 {
443 return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC));
444 }
RTC_ALRM0SS
#define RTC_ALRM0SS
Definition: gd32f3x0_rtc.h:35
RTC_ALRM0SS_SSC
#define RTC_ALRM0SS_SSC
Definition: gd32f3x0_rtc.h:166
void rtc_alter_output_config | ( | uint32_t | source,
 |  | uint32_t | mode
 | ) |  |

configure rtc alternate output source

Parameters
[in] source specify signal to output
  • RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC is the default value, output 512Hz signal
  • RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC is the default value, output 512Hz signal
  • RTC_ALARM_HIGH: when the alarm flag is set, the output pin is high
  • RTC_ALARM_LOW: when the Alarm flag is set, the output pin is low
[in] mode specify the output pin (PC13) mode when output alarm signal
  • RTC_ALARM_OUTPUT_OD: open drain mode
  • RTC_ALARM_OUTPUT_PP: push pull mode
[out] none
Return values
none

Definition at line 718 of file gd32f3x0_rtc.c.

719 {
720 /* disable the write protection */
721 RTC_WPK = RTC_UNLOCK_KEY1;
722 RTC_WPK = RTC_UNLOCK_KEY2;
723
724 RTC_CTL &= (uint32_t)~(RTC_CTL_COEN | RTC_CTL_OS | RTC_CTL_OPOL | RTC_CTL_COS);
725
726 RTC_CTL |= (uint32_t)(source);
727
728 /* alarm output */
729 if((uint32_t)RESET != (source & RTC_OS_ENABLE)){
730 RTC_TAMP &= (uint32_t)~(RTC_TAMP_PC13VAL);
731 RTC_TAMP |= (uint32_t)(mode);
732 }
733
734 /* enable the write protection */
735 RTC_WPK = RTC_LOCK_KEY;
736 }
RTC_CTL_COEN
#define RTC_CTL_COEN
Definition: gd32f3x0_rtc.h:76
RTC_CTL_OPOL
#define RTC_CTL_OPOL
Definition: gd32f3x0_rtc.h:74
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_TAMP
#define RTC_TAMP
Definition: gd32f3x0_rtc.h:34
RTC_CTL_OS
#define RTC_CTL_OS
Definition: gd32f3x0_rtc.h:75
RTC_TAMP_PC13VAL
#define RTC_TAMP_PC13VAL
Definition: gd32f3x0_rtc.h:158
RTC_OS_ENABLE
#define RTC_OS_ENABLE
Definition: gd32f3x0_rtc.h:285
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_CTL_COS
#define RTC_CTL_COS
Definition: gd32f3x0_rtc.h:73
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_bypass_shadow_disable ( void )

disable RTC bypass shadow registers function

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 782 of file gd32f3x0_rtc.c.

783 {
784 /* disable the write protection */
785 RTC_WPK = RTC_UNLOCK_KEY1;
786 RTC_WPK = RTC_UNLOCK_KEY2;
787
788 RTC_CTL &= (uint8_t)~RTC_CTL_BPSHAD;
789
790 /* enable the write protection */
791 RTC_WPK = RTC_LOCK_KEY;
792 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL_BPSHAD
#define RTC_CTL_BPSHAD
Definition: gd32f3x0_rtc.h:64
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_bypass_shadow_enable ( void )

enable RTC bypass shadow registers function

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 764 of file gd32f3x0_rtc.c.

765 {
766 /* disable the write protection */
767 RTC_WPK = RTC_UNLOCK_KEY1;
768 RTC_WPK = RTC_UNLOCK_KEY2;
769
770 RTC_CTL |= (uint8_t)RTC_CTL_BPSHAD;
771
772 /* enable the write protection */
773 RTC_WPK = RTC_LOCK_KEY;
774 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL_BPSHAD
#define RTC_CTL_BPSHAD
Definition: gd32f3x0_rtc.h:64
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
ErrStatus rtc_calibration_config | ( | uint32_t | window,
 |  | uint32_t | plus,
 |  | uint32_t | minus
 | ) |  |

configure RTC calibration register

Parameters
[in] window select calibration window
  • RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz
  • RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz
  • RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz
[in] plus add RTC clock or not
  • RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock
  • RTC_CALIBRATION_PLUS_RESET: no effect
[in] | minus | the RTC clock to minus during the calibration window(0x0 - 0x1FF)
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 903 of file gd32f3x0_rtc.c.

904 {
905 uint32_t time_index = RTC_HRFC_TIMEOUT;
906 ErrStatus error_status = ERROR;
907 uint32_t flag_status = RESET;
908
909 /* disable the write protection */
910 RTC_WPK = RTC_UNLOCK_KEY1;
911 RTC_WPK = RTC_UNLOCK_KEY2;
912
913 /* check if a calibration operation is ongoing */
914 do{
915 flag_status = RTC_STAT & RTC_STAT_SCPF;
916 }while((--time_index > 0x00U) && ((uint32_t)RESET != flag_status));
917
918 if((uint32_t)RESET == flag_status){
919 RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus));
920 error_status = SUCCESS;
921 }
922
923 /* enable the write protection */
924 RTC_WPK = RTC_LOCK_KEY;
925
926 return error_status;
927 }
RTC_HRFC_TIMEOUT
#define RTC_HRFC_TIMEOUT
Definition: gd32f3x0_rtc.h:449
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_HRFC
#define RTC_HRFC
Definition: gd32f3x0_rtc.h:33
RTC_STAT_SCPF
#define RTC_STAT_SCPF
Definition: gd32f3x0_rtc.h:90
HRFC_CMSK
#define HRFC_CMSK(regval)
Definition: gd32f3x0_rtc.h:364
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_current_time_get ( rtc_parameter_struct * rtc_initpara_struct )

get current time and date

Parameters
[in] | none
[out] | rtc_initpara_struct | pointer to a rtc_parameter_struct structure which contains parameters for initialization of the rtc peripheral members of the structure and the member values are shown as below: rtc_year: 0x0 - 0x99(BCD format) rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC rtc_date: 0x1 - 0x31(BCD format) rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose rtc_minute: 0x0 - 0x59(BCD format) rtc_second: 0x0 - 0x59(BCD format) rtc_factor_asyn: 0x0 - 0x7F rtc_factor_syn: 0x0 - 0x7FFF rtc_am_pm: RTC_AM, RTC_PM rtc_display_format: RTC_24HOUR, RTC_12HOUR
Return values
none

Definition at line 233 of file gd32f3x0_rtc.c.

234 {
235 uint32_t temp_tr = 0x00U, temp_dr = 0x00U, temp_pscr = 0x00U, temp_ctlr = 0x00U;
236
237 temp_tr = (uint32_t)RTC_TIME;
238 temp_dr = (uint32_t)RTC_DATE;
239 temp_pscr = (uint32_t)RTC_PSC;
240 temp_ctlr = (uint32_t)RTC_CTL;
241
242 /* get current time and construct rtc_parameter_struct structure */
243 rtc_initpara_struct->rtc_year = (uint8_t)GET_DATE_YR(temp_dr);
244 rtc_initpara_struct->rtc_month = (uint8_t)GET_DATE_MON(temp_dr);
245 rtc_initpara_struct->rtc_date = (uint8_t)GET_DATE_DAY(temp_dr);
246 rtc_initpara_struct->rtc_day_of_week = (uint8_t)GET_DATE_DOW(temp_dr);
247 rtc_initpara_struct->rtc_hour = (uint8_t)GET_TIME_HR(temp_tr);
248 rtc_initpara_struct->rtc_minute = (uint8_t)GET_TIME_MN(temp_tr);
249 rtc_initpara_struct->rtc_second = (uint8_t)GET_TIME_SC(temp_tr);
250 rtc_initpara_struct->rtc_factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr);
251 rtc_initpara_struct->rtc_factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr);
252 rtc_initpara_struct->rtc_am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM);
253 rtc_initpara_struct->rtc_display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS);
254 }
RTC_TIME
#define RTC_TIME
Definition: gd32f3x0_rtc.h:21
rtc_parameter_struct::rtc_minute
uint8_t rtc_minute
Definition: gd32f3x0_rtc.h:193
RTC_TIME_PM
#define RTC_TIME_PM
Definition: gd32f3x0_rtc.h:50
RTC_CTL_CS
#define RTC_CTL_CS
Definition: gd32f3x0_rtc.h:65
rtc_parameter_struct::rtc_year
uint8_t rtc_year
Definition: gd32f3x0_rtc.h:188
rtc_parameter_struct::rtc_am_pm
uint32_t rtc_am_pm
Definition: gd32f3x0_rtc.h:197
rtc_parameter_struct::rtc_display_format
uint32_t rtc_display_format
Definition: gd32f3x0_rtc.h:198
RTC_PSC
#define RTC_PSC
Definition: gd32f3x0_rtc.h:25
rtc_parameter_struct::rtc_date
uint8_t rtc_date
Definition: gd32f3x0_rtc.h:190
GET_TIME_HR
#define GET_TIME_HR(regval)
Definition: gd32f3x0_rtc.h:245
GET_DATE_DOW
#define GET_DATE_DOW(regval)
Definition: gd32f3x0_rtc.h:270
rtc_parameter_struct::rtc_hour
uint8_t rtc_hour
Definition: gd32f3x0_rtc.h:192
GET_PSC_FACTOR_S
#define GET_PSC_FACTOR_S(regval)
Definition: gd32f3x0_rtc.h:300
rtc_parameter_struct::rtc_second
uint8_t rtc_second
Definition: gd32f3x0_rtc.h:194
GET_DATE_YR
#define GET_DATE_YR(regval)
Definition: gd32f3x0_rtc.h:280
rtc_parameter_struct::rtc_day_of_week
uint8_t rtc_day_of_week
Definition: gd32f3x0_rtc.h:191
rtc_parameter_struct::rtc_factor_asyn
uint16_t rtc_factor_asyn
Definition: gd32f3x0_rtc.h:195
RTC_DATE
#define RTC_DATE
Definition: gd32f3x0_rtc.h:22
GET_PSC_FACTOR_A
#define GET_PSC_FACTOR_A(regval)
Definition: gd32f3x0_rtc.h:303
GET_TIME_MN
#define GET_TIME_MN(regval)
Definition: gd32f3x0_rtc.h:242
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
GET_DATE_MON
#define GET_DATE_MON(regval)
Definition: gd32f3x0_rtc.h:255
rtc_parameter_struct::rtc_factor_syn
uint16_t rtc_factor_syn
Definition: gd32f3x0_rtc.h:196
GET_TIME_SC
#define GET_TIME_SC(regval)
Definition: gd32f3x0_rtc.h:239
rtc_parameter_struct::rtc_month
uint8_t rtc_month
Definition: gd32f3x0_rtc.h:189
GET_DATE_DAY
#define GET_DATE_DAY(regval)
Definition: gd32f3x0_rtc.h:252
ErrStatus rtc_deinit ( void )

reset most of the RTC registers

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 20 of file gd32f3x0_rtc.c.

21 {
22 ErrStatus error_status = ERROR;
23
24 /* RTC_TAMP register is not under write protection */
25 RTC_TAMP = RTC_REGISTER_RESET;
26
27 /* disable the write protection */
28 RTC_WPK = RTC_UNLOCK_KEY1;
29 RTC_WPK = RTC_UNLOCK_KEY2;
30
31 /* reset RTC_CTL register, this can be done without the init mode */
32 RTC_CTL &= RTC_REGISTER_RESET;
33
34 /* enter init mode */
35 error_status = rtc_init_mode_enter();
36
37 if(ERROR != error_status){
38 /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition.
39 in order to read calendar from shadow register, not the real registers being reset */
40 RTC_TIME = RTC_REGISTER_RESET;
41 RTC_DATE = RTC_DATE_RESET;
42
43 RTC_PSC = RTC_PSC_RESET;
44
45 /* reset RTC_STAT register, also exit init mode.
46 at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */
47 RTC_STAT = RTC_STAT_RESET;
48
49 /* to write RTC_ALRM0SS register, ALRM0EN bit in RTC_CTL register should be reset as the condition */
50 RTC_ALRM0TD = RTC_REGISTER_RESET;
51 RTC_ALRM0SS = RTC_REGISTER_RESET;
52
53 /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */
54 RTC_SHIFTCTL = RTC_REGISTER_RESET;
55 RTC_HRFC = RTC_REGISTER_RESET;
56
57 error_status = rtc_register_sync_wait();
58 }
59
60 /* enable the write protection */
61 RTC_WPK = RTC_LOCK_KEY;
62
63 return error_status;
64 }
RTC_TIME
#define RTC_TIME
Definition: gd32f3x0_rtc.h:21
RTC_SHIFTCTL
#define RTC_SHIFTCTL
Definition: gd32f3x0_rtc.h:29
RTC_REGISTER_RESET
#define RTC_REGISTER_RESET
Definition: gd32f3x0_rtc.h:441
RTC_PSC_RESET
#define RTC_PSC_RESET
Definition: gd32f3x0_rtc.h:444
RTC_STAT_RESET
#define RTC_STAT_RESET
Definition: gd32f3x0_rtc.h:443
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_TAMP
#define RTC_TAMP
Definition: gd32f3x0_rtc.h:34
RTC_PSC
#define RTC_PSC
Definition: gd32f3x0_rtc.h:25
RTC_ALRM0SS
#define RTC_ALRM0SS
Definition: gd32f3x0_rtc.h:35
RTC_ALRM0TD
#define RTC_ALRM0TD
Definition: gd32f3x0_rtc.h:26
RTC_HRFC
#define RTC_HRFC
Definition: gd32f3x0_rtc.h:33
RTC_DATE_RESET
#define RTC_DATE_RESET
Definition: gd32f3x0_rtc.h:442
RTC_DATE
#define RTC_DATE
Definition: gd32f3x0_rtc.h:22
rtc_init_mode_enter
ErrStatus rtc_init_mode_enter(void)
enter RTC init mode
Definition: gd32f3x0_rtc.c:138
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
rtc_register_sync_wait
ErrStatus rtc_register_sync_wait(void)
wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers ...
Definition: gd32f3x0_rtc.c:180
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_flag_clear ( uint32_t flag )

clear specified flag

Parameters
[in] flag specify which flag to clear
  • RTC_FLAG_TAMP1: tamper 1 event flag
  • RTC_FLAG_TAMP0: tamper 0 event flag
  • RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag
  • RTC_FLAG_TIMESTAMP: time-stamp event flag
  • RTC_FLAG_ALARM0: alarm event flag
  • RTC_FLAG_RSYN: time and date registers synchronized event flag
[out] none
Return values
none

Definition at line 698 of file gd32f3x0_rtc.c.

699 {
700 RTC_STAT &= (uint32_t)(~flag);
701 }
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
FlagStatus rtc_flag_get ( uint32_t flag )

check specified flag

Parameters
[in] flag specify which flag to check
  • RTC_FLAG_RECALIBRATION: recalibration pending flag
  • RTC_FLAG_TAMP1: tamper 1 event flag
  • RTC_FLAG_TAMP0: tamper 0 event flag
  • RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag
  • RTC_FLAG_TIMESTAMP: time-stamp event flag
  • RTC_FLAG_ALARM0: alarm event flag
  • RTC_FLAG_INIT: init mode event flag
  • RTC_FLAG_RSYN: time and date registers synchronized event flag
  • RTC_FLAG_YCM: year parameter configured event flag
  • RTC_FLAG_SHIFT: shift operation pending flag
  • RTC_FLAG_ALARM0_WRITTEN: alarm writen available flag
[out] none
Return values
FlagStatus SET or RESET

Definition at line 676 of file gd32f3x0_rtc.c.

677 {
678 FlagStatus flag_state = RESET;
679
680 if((uint32_t)RESET != (RTC_STAT & flag)){
681 flag_state = SET;
682 }
683 return flag_state;
684 }
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
void rtc_hour_adjust ( uint32_t operation )

ajust the daylight saving time by adding or substracting one hour from the current time

Parameters
[in] operation hour ajustment operation
  • RTC_CTL_A1H: add one hour
  • RTC_CTL_S1H: substract one hour
[out] none
Return values
none

Definition at line 746 of file gd32f3x0_rtc.c.

747 {
748 /* disable the write protection */
749 RTC_WPK = RTC_UNLOCK_KEY1;
750 RTC_WPK = RTC_UNLOCK_KEY2;
751
752 RTC_CTL |= (uint32_t)(operation);
753
754 /* enable the write protection */
755 RTC_WPK = RTC_LOCK_KEY;
756 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
ErrStatus rtc_init ( rtc_parameter_struct * rtc_initpara_struct )

initialize RTC registers

Parameters
[in] | rtc_initpara_struct | pointer to a rtc_parameter_struct structure which contains parameters for initialization of the rtc peripheral members of the structure and the member values are shown as below: rtc_year: 0x0 - 0x99(BCD format) rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC rtc_date: 0x1 - 0x31(BCD format) rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose rtc_minute: 0x0 - 0x59(BCD format) rtc_second: 0x0 - 0x59(BCD format) rtc_factor_asyn: 0x0 - 0x7F rtc_factor_syn: 0x0 - 0x7FFF rtc_am_pm: RTC_AM, RTC_PM rtc_display_format: RTC_24HOUR, RTC_12HOUR
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 87 of file gd32f3x0_rtc.c.

88 {
89 ErrStatus error_status = ERROR;
90 uint32_t reg_time = 0x00U, reg_date = 0x00U;
91
92 reg_date = (DATE_YR(rtc_initpara_struct->rtc_year) | \
93 DATE_DOW(rtc_initpara_struct->rtc_day_of_week) | \
94 DATE_MON(rtc_initpara_struct->rtc_month) | \
95 DATE_DAY(rtc_initpara_struct->rtc_date));
96
97 reg_time = (rtc_initpara_struct->rtc_am_pm| \
98 TIME_HR(rtc_initpara_struct->rtc_hour) | \
99 TIME_MN(rtc_initpara_struct->rtc_minute) | \
100 TIME_SC(rtc_initpara_struct->rtc_second));
101
102 /* 1st: disable the write protection */
103 RTC_WPK = RTC_UNLOCK_KEY1;
104 RTC_WPK = RTC_UNLOCK_KEY2;
105
106 /* 2nd: enter init mode */
107 error_status = rtc_init_mode_enter();
108
109 if(ERROR != error_status){
110 RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->rtc_factor_asyn)| \
111 PSC_FACTOR_S(rtc_initpara_struct->rtc_factor_syn));
112
113 RTC_TIME = (uint32_t)reg_time;
114 RTC_DATE = (uint32_t)reg_date;
115
116 RTC_CTL &= (uint32_t)(~RTC_CTL_CS);
117 RTC_CTL |= rtc_initpara_struct->rtc_display_format;
118
119 /* 3rd: exit init mode */
120 rtc_init_mode_exit();
121
122 /* 4th: wait the RSYNF flag to set */
123 error_status = rtc_register_sync_wait();
124 }
125
126 /* 5th: enable the write protection */
127 RTC_WPK = RTC_LOCK_KEY;
128
129 return error_status;
130 }
RTC_TIME
#define RTC_TIME
Definition: gd32f3x0_rtc.h:21
PSC_FACTOR_S
#define PSC_FACTOR_S(regval)
Definition: gd32f3x0_rtc.h:299
rtc_parameter_struct::rtc_minute
uint8_t rtc_minute
Definition: gd32f3x0_rtc.h:193
RTC_CTL_CS
#define RTC_CTL_CS
Definition: gd32f3x0_rtc.h:65
rtc_parameter_struct::rtc_year
uint8_t rtc_year
Definition: gd32f3x0_rtc.h:188
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
rtc_parameter_struct::rtc_am_pm
uint32_t rtc_am_pm
Definition: gd32f3x0_rtc.h:197
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
TIME_HR
#define TIME_HR(regval)
Definition: gd32f3x0_rtc.h:244
DATE_DOW
#define DATE_DOW(regval)
Definition: gd32f3x0_rtc.h:269
rtc_parameter_struct::rtc_display_format
uint32_t rtc_display_format
Definition: gd32f3x0_rtc.h:198
RTC_PSC
#define RTC_PSC
Definition: gd32f3x0_rtc.h:25
rtc_parameter_struct::rtc_date
uint8_t rtc_date
Definition: gd32f3x0_rtc.h:190
PSC_FACTOR_A
#define PSC_FACTOR_A(regval)
Definition: gd32f3x0_rtc.h:302
rtc_parameter_struct::rtc_hour
uint8_t rtc_hour
Definition: gd32f3x0_rtc.h:192
rtc_parameter_struct::rtc_second
uint8_t rtc_second
Definition: gd32f3x0_rtc.h:194
rtc_parameter_struct::rtc_day_of_week
uint8_t rtc_day_of_week
Definition: gd32f3x0_rtc.h:191
DATE_DAY
#define DATE_DAY(regval)
Definition: gd32f3x0_rtc.h:251
TIME_SC
#define TIME_SC(regval)
Definition: gd32f3x0_rtc.h:238
DATE_MON
#define DATE_MON(regval)
Definition: gd32f3x0_rtc.h:254
rtc_init_mode_exit
void rtc_init_mode_exit(void)
exit RTC init mode
Definition: gd32f3x0_rtc.c:168
rtc_parameter_struct::rtc_factor_asyn
uint16_t rtc_factor_asyn
Definition: gd32f3x0_rtc.h:195
RTC_DATE
#define RTC_DATE
Definition: gd32f3x0_rtc.h:22
DATE_YR
#define DATE_YR(regval)
Definition: gd32f3x0_rtc.h:279
rtc_init_mode_enter
ErrStatus rtc_init_mode_enter(void)
enter RTC init mode
Definition: gd32f3x0_rtc.c:138
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
rtc_register_sync_wait
ErrStatus rtc_register_sync_wait(void)
wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers ...
Definition: gd32f3x0_rtc.c:180
rtc_parameter_struct::rtc_factor_syn
uint16_t rtc_factor_syn
Definition: gd32f3x0_rtc.h:196
rtc_parameter_struct::rtc_month
uint8_t rtc_month
Definition: gd32f3x0_rtc.h:189
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
TIME_MN
#define TIME_MN(regval)
Definition: gd32f3x0_rtc.h:241
ErrStatus rtc_init_mode_enter ( void )

enter RTC init mode

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 138 of file gd32f3x0_rtc.c.

139 {
140 uint32_t time_index = RTC_INITM_TIMEOUT;
141 uint32_t flag_status = RESET;
142 ErrStatus error_status = ERROR;
143
144 /* check whether it has been in init mode */
145 if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)){
146 RTC_STAT |= RTC_STAT_INITM;
147
148 /* wait until the INITF flag to be set */
149 do{
150 flag_status = RTC_STAT & RTC_STAT_INITF;
151 }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status));
152
153 if((uint32_t)RESET != flag_status){
154 error_status = SUCCESS;
155 }
156 }else{
157 error_status = SUCCESS;
158 }
159 return error_status;
160 }
RTC_INITM_TIMEOUT
#define RTC_INITM_TIMEOUT
Definition: gd32f3x0_rtc.h:447
RTC_STAT_INITM
#define RTC_STAT_INITM
Definition: gd32f3x0_rtc.h:84
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
RTC_STAT_INITF
#define RTC_STAT_INITF
Definition: gd32f3x0_rtc.h:83
void rtc_init_mode_exit ( void )

exit RTC init mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 168 of file gd32f3x0_rtc.c.

169 {
170 RTC_STAT &= (uint32_t)(~RTC_STAT_INITM);
171 }
RTC_STAT_INITM
#define RTC_STAT_INITM
Definition: gd32f3x0_rtc.h:84
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
void rtc_interrupt_disable ( uint32_t interrupt )

disble specified RTC interrupt

Parameters
[in] interrupt specify which interrupt source to be disabled
  • RTC_INT_TIMESTAMP: timestamp interrupt
  • RTC_INT_ALARM: alarm interrupt
  • RTC_INT_TAMP: tamp interrupt
[out] none
Return values
none

Definition at line 644 of file gd32f3x0_rtc.c.

645 {
646 /* disable the write protection */
647 RTC_WPK = RTC_UNLOCK_KEY1;
648 RTC_WPK = RTC_UNLOCK_KEY2;
649
650 /* disable the interrupts in RTC_CTL register */
651 RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE);
652 /* disable the interrupts in RTC_TAMP register */
653 RTC_TAMP &= (uint32_t)~(interrupt & RTC_TAMP_TPIE);
654
655 /* enable the write protection */
656 RTC_WPK = RTC_LOCK_KEY;
657 }
RTC_TAMP_TPIE
#define RTC_TAMP_TPIE
Definition: gd32f3x0_rtc.h:150
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_TAMP
#define RTC_TAMP
Definition: gd32f3x0_rtc.h:34
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_interrupt_enable ( uint32_t interrupt )

enable specified RTC interrupt

Parameters
[in] interrupt specify which interrupt source to be enabled
  • RTC_INT_TIMESTAMP: timestamp interrupt
  • RTC_INT_ALARM: alarm interrupt
  • RTC_INT_TAMP: tamp interrupt
[out] none
Return values
none

Definition at line 620 of file gd32f3x0_rtc.c.

621 {
622 /* disable the write protection */
623 RTC_WPK = RTC_UNLOCK_KEY1;
624 RTC_WPK = RTC_UNLOCK_KEY2;
625
626 /* enable the interrupts in RTC_CTL register */
627 RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE);
628 /* enable the interrupts in RTC_TAMP register */
629 RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE);
630
631 /* enable the write protection */
632 RTC_WPK = RTC_LOCK_KEY;
633 }
RTC_TAMP_TPIE
#define RTC_TAMP_TPIE
Definition: gd32f3x0_rtc.h:150
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_TAMP
#define RTC_TAMP
Definition: gd32f3x0_rtc.h:34
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
ErrStatus rtc_refclock_detection_disable ( void )

disable RTC reference clock detection function

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 829 of file gd32f3x0_rtc.c.

830 {
831 ErrStatus error_status = ERROR;
832
833 /* disable the write protection */
834 RTC_WPK = RTC_UNLOCK_KEY1;
835 RTC_WPK = RTC_UNLOCK_KEY2;
836
837 /* enter init mode */
838 error_status = rtc_init_mode_enter();
839
840 if(ERROR != error_status){
841 RTC_CTL &= (uint32_t)~RTC_CTL_REFEN;
842 /* exit init mode */
843 rtc_init_mode_exit();
844 }
845
846 /* enable the write protection */
847 RTC_WPK = RTC_LOCK_KEY;
848
849 return error_status;
850 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
rtc_init_mode_exit
void rtc_init_mode_exit(void)
exit RTC init mode
Definition: gd32f3x0_rtc.c:168
RTC_CTL_REFEN
#define RTC_CTL_REFEN
Definition: gd32f3x0_rtc.h:63
rtc_init_mode_enter
ErrStatus rtc_init_mode_enter(void)
enter RTC init mode
Definition: gd32f3x0_rtc.c:138
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
ErrStatus rtc_refclock_detection_enable ( void )

enable RTC reference clock detection function

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 800 of file gd32f3x0_rtc.c.

801 {
802 ErrStatus error_status = ERROR;
803
804 /* disable the write protection */
805 RTC_WPK = RTC_UNLOCK_KEY1;
806 RTC_WPK = RTC_UNLOCK_KEY2;
807
808 /* enter init mode */
809 error_status = rtc_init_mode_enter();
810
811 if(ERROR != error_status){
812 RTC_CTL |= (uint32_t)RTC_CTL_REFEN;
813 /* exit init mode */
814 rtc_init_mode_exit();
815 }
816
817 /* enable the write protection */
818 RTC_WPK = RTC_LOCK_KEY;
819
820 return error_status;
821 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
rtc_init_mode_exit
void rtc_init_mode_exit(void)
exit RTC init mode
Definition: gd32f3x0_rtc.c:168
RTC_CTL_REFEN
#define RTC_CTL_REFEN
Definition: gd32f3x0_rtc.h:63
rtc_init_mode_enter
ErrStatus rtc_init_mode_enter(void)
enter RTC init mode
Definition: gd32f3x0_rtc.c:138
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
ErrStatus rtc_register_sync_wait ( void )

wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated

Parameters
[in] | none
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 180 of file gd32f3x0_rtc.c.

181 {
182 volatile uint32_t time_index = RTC_RSYNF_TIMEOUT;
183 uint32_t flag_status = RESET;
184 ErrStatus error_status = ERROR;
185
186 if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)){
187 /* disable the write protection */
188 RTC_WPK = RTC_UNLOCK_KEY1;
189 RTC_WPK = RTC_UNLOCK_KEY2;
190
191 /* firstly clear RSYNF flag */
192 RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF);
193
194 /* wait until RSYNF flag to be set */
195 do{
196 flag_status = RTC_STAT & RTC_STAT_RSYNF;
197 }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status));
198
199 if((uint32_t)RESET != flag_status){
200 error_status = SUCCESS;
201 }
202
203 /* enable the write protection */
204 RTC_WPK = RTC_LOCK_KEY;
205 }else{
206 error_status = SUCCESS;
207 }
208
209 return error_status;
210 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL_BPSHAD
#define RTC_CTL_BPSHAD
Definition: gd32f3x0_rtc.h:64
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_RSYNF_TIMEOUT
#define RTC_RSYNF_TIMEOUT
Definition: gd32f3x0_rtc.h:448
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
RTC_STAT_RSYNF
#define RTC_STAT_RSYNF
Definition: gd32f3x0_rtc.h:82
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
ErrStatus rtc_second_ajust | ( | uint32_t | add,
 |  | uint32_t | minus
 | ) |  |

ajust RTC second or subsecond value of current time

Parameters
[in] add add 1s to current time or not
  • RTC_SHIFT_ADD1S_RESET: no effect
  • RTC_SHIFT_ADD1S_SET: add 1s to current time
[in] | minus | number of subsecond to minus from current time(0x0 - 0x7FFF)
[out] | none
Return values
ErrStatus ERROR or SUCCESS

Definition at line 861 of file gd32f3x0_rtc.c.

862 {
863 uint32_t time_index = RTC_SHIFTCTL_TIMEOUT;
864 ErrStatus error_status = ERROR;
865 uint32_t flag_status = RESET;
866 uint32_t temp=0U;
867
868 /* disable the write protection */
869 RTC_WPK = RTC_UNLOCK_KEY1;
870 RTC_WPK = RTC_UNLOCK_KEY2;
871
872 /* check if a shift operation is ongoing */
873 do{
874 flag_status = RTC_STAT & RTC_STAT_SOPF;
875 }while((--time_index > 0x00U) && ((uint32_t)RESET != flag_status));
876
877 temp = RTC_CTL & RTC_CTL_REFEN;
878 /* check if the function of reference clock detection is disabled */
879 if(((uint32_t)RESET == flag_status) && (RESET == temp)){
880 RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus));
881 error_status = rtc_register_sync_wait();
882 }
883
884 /* enable the write protection */
885 RTC_WPK = RTC_LOCK_KEY;
886
887 return error_status;
888 }
SHIFTCTL_SFS
#define SHIFTCTL_SFS(regval)
Definition: gd32f3x0_rtc.h:335
RTC_SHIFTCTL
#define RTC_SHIFTCTL
Definition: gd32f3x0_rtc.h:29
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_SHIFTCTL_TIMEOUT
#define RTC_SHIFTCTL_TIMEOUT
Definition: gd32f3x0_rtc.h:450
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_STAT_SOPF
#define RTC_STAT_SOPF
Definition: gd32f3x0_rtc.h:80
RTC_CTL_REFEN
#define RTC_CTL_REFEN
Definition: gd32f3x0_rtc.h:63
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
rtc_register_sync_wait
ErrStatus rtc_register_sync_wait(void)
wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers ...
Definition: gd32f3x0_rtc.c:180
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
uint32_t rtc_subsecond_get ( void )

get current subsecond value

Parameters
[in] | none
[out] | none
Return values
current subsecond value

Definition at line 262 of file gd32f3x0_rtc.c.

263 {
264 uint32_t reg = 0x00U;
265 /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */
266 reg = (uint32_t)RTC_SS;
267 /* read RTC_DATE to unlock the 3 shadow registers */
268 (void) (RTC_DATE);
269
270 return reg;
271 }
RTC_SS
#define RTC_SS
Definition: gd32f3x0_rtc.h:28
RTC_DATE
#define RTC_DATE
Definition: gd32f3x0_rtc.h:22
void rtc_tamper_disable ( uint32_t source )

disable RTC tamper

Parameters
[in] source specify which tamper source to be disabled
  • RTC_TAMPER0
  • RTC_TAMPER1
[out] none
Return values
none

Definition at line 604 of file gd32f3x0_rtc.c.

605 {
606 /* disable tamper */
607 RTC_TAMP &= (uint32_t)~source;
608
609 }
RTC_TAMP
#define RTC_TAMP
Definition: gd32f3x0_rtc.h:34
void rtc_tamper_enable ( rtc_tamper_struct * rtc_tamper )

enable RTC tamper

Parameters
[in] | rtc_tamper | pointer to a rtc_tamper_struct structure which contains parameters for RTC tamper configuration members of the structure and the member values are shown as below: rtc_tamper_source: RTC_TAMPER0, RTC_TAMPER1 rtc_tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH rtc_tamper_filter: RTC_FLT_EDGE, RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S rtc_tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192, RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024, RTC_FREQ_DIV512, RTC_FREQ_DIV256 rtc_tamper_precharge_enable: DISABLE, ENABLE rtc_tamper_precharge_time: RTC_PRCH_1C, RTC_PRCH_2C, RTC_PRCH_4C, RTC_PRCH_8C rtc_tamper_with_timestamp: DISABLE, ENABLE
[out] | none
Return values
none

Definition at line 557 of file gd32f3x0_rtc.c.

558 {
559 /* disable tamper */
560 RTC_TAMP &= (uint32_t)~(rtc_tamper->rtc_tamper_source);
561
562 /* tamper filter must be used when the tamper source is voltage level detection */
563 RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT;
564
565 /* the tamper source is voltage level detection */
566 if(rtc_tamper->rtc_tamper_filter != RTC_FLT_EDGE ){
567 RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT);
568
569 /* check if the tamper pin need precharge, if need, then configure the precharge time */
570 if(DISABLE == rtc_tamper->rtc_tamper_precharge_enable){
571 RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU;
572 }else{
573 RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_precharge_time);
574 }
575
576 RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_sample_frequency);
577 RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_filter);
578 }
579
580 RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS;
581
582 if(DISABLE != rtc_tamper->rtc_tamper_with_timestamp){
583 /* the tamper event also cause a time-stamp event */
584 RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS;
585 }
586
587 /* configure the tamper trigger */
588 RTC_TAMP &= ((uint32_t)~((rtc_tamper->rtc_tamper_source) << RTC_TAMPER_TRIGGER_POS));
589 if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->rtc_tamper_trigger){
590 RTC_TAMP |= (uint32_t)((rtc_tamper->rtc_tamper_source)<< RTC_TAMPER_TRIGGER_POS);
591 }
592 /* enable tamper */
593 RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_source);
594 }
rtc_tamper_struct::rtc_tamper_sample_frequency
uint32_t rtc_tamper_sample_frequency
Definition: gd32f3x0_rtc.h:231
rtc_tamper_struct::rtc_tamper_with_timestamp
ControlStatus rtc_tamper_with_timestamp
Definition: gd32f3x0_rtc.h:234
RTC_TAMP
#define RTC_TAMP
Definition: gd32f3x0_rtc.h:34
RTC_TAMPER_TRIGGER_POS
#define RTC_TAMPER_TRIGGER_POS
Definition: gd32f3x0_rtc.h:404
RTC_TAMP_TPTS
#define RTC_TAMP_TPTS
Definition: gd32f3x0_rtc.h:153
RTC_TAMP_FLT
#define RTC_TAMP_FLT
Definition: gd32f3x0_rtc.h:155
RTC_TAMP_DISPU
#define RTC_TAMP_DISPU
Definition: gd32f3x0_rtc.h:157
rtc_tamper_struct::rtc_tamper_trigger
uint32_t rtc_tamper_trigger
Definition: gd32f3x0_rtc.h:229
rtc_tamper_struct::rtc_tamper_source
uint32_t rtc_tamper_source
Definition: gd32f3x0_rtc.h:228
RTC_TAMP_FREQ
#define RTC_TAMP_FREQ
Definition: gd32f3x0_rtc.h:154
rtc_tamper_struct::rtc_tamper_precharge_enable
ControlStatus rtc_tamper_precharge_enable
Definition: gd32f3x0_rtc.h:232
rtc_tamper_struct::rtc_tamper_precharge_time
uint32_t rtc_tamper_precharge_time
Definition: gd32f3x0_rtc.h:233
RTC_TAMPER_TRIGGER_EDGE_RISING
#define RTC_TAMPER_TRIGGER_EDGE_RISING
Definition: gd32f3x0_rtc.h:399
RTC_FLT_EDGE
#define RTC_FLT_EDGE
Definition: gd32f3x0_rtc.h:385
rtc_tamper_struct::rtc_tamper_filter
uint32_t rtc_tamper_filter
Definition: gd32f3x0_rtc.h:230
RTC_TAMP_PRCH
#define RTC_TAMP_PRCH
Definition: gd32f3x0_rtc.h:156
void rtc_timestamp_disable ( void )

disable RTC time-stamp

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 480 of file gd32f3x0_rtc.c.

481 {
482 /* disable the write protection */
483 RTC_WPK = RTC_UNLOCK_KEY1;
484 RTC_WPK = RTC_UNLOCK_KEY2;
485
486 /* clear the TSEN bit */
487 RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN);
488
489 /* enable the write protection */
490 RTC_WPK = RTC_LOCK_KEY;
491 }
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL_TSEN
#define RTC_CTL_TSEN
Definition: gd32f3x0_rtc.h:67
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_timestamp_enable ( uint32_t edge )

enable RTC time-stamp

Parameters
[in] edge specify which edge to detect of time-stamp
  • RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event
  • RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event
[out] none
Return values
none

Definition at line 454 of file gd32f3x0_rtc.c.

455 {
456 uint32_t reg_ctl = 0x00U;
457
458 /* clear the bits to be configured in RTC_CTL */
459 reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN)));
460
461 /* new configuration */
462 reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN);
463
464 /* disable the write protection */
465 RTC_WPK = RTC_UNLOCK_KEY1;
466 RTC_WPK = RTC_UNLOCK_KEY2;
467
468 RTC_CTL = (uint32_t)reg_ctl;
469
470 /* enable the write protection */
471 RTC_WPK = RTC_LOCK_KEY;
472 }
RTC_CTL_TSEG
#define RTC_CTL_TSEG
Definition: gd32f3x0_rtc.h:62
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
RTC_CTL_TSEN
#define RTC_CTL_TSEN
Definition: gd32f3x0_rtc.h:67
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
void rtc_timestamp_get ( rtc_timestamp_struct * rtc_timestamp )

get RTC timestamp time and date

Parameters
[in] | none
[out] | rtc_timestamp | pointer to a rtc_timestamp_struct structure which contains parameters for RTC time-stamp configuration members of the structure and the member values are shown as below: rtc_timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC rtc_timestamp_date: 0x1 - 0x31(BCD format) rtc_timestamp_day: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set rtc_timestamp_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format rtc_timestamp_minute: 0x0 - 0x59(BCD format) rtc_timestamp_second: 0x0 - 0x59(BCD format) rtc_am_pm: RTC_AM, RTC_PM
Return values
none

Definition at line 510 of file gd32f3x0_rtc.c.

511 {
512 uint32_t temp_tts = 0x00U, temp_dts = 0x00U;
513
514 /* get the value of time_stamp registers */
515 temp_tts = (uint32_t)RTC_TTS;
516 temp_dts = (uint32_t)RTC_DTS;
517
518 /* get timestamp time and construct the rtc_timestamp_struct structure */
519 rtc_timestamp->rtc_am_pm = (uint32_t)(temp_tts & RTC_TTS_PM);
520 rtc_timestamp->rtc_timestamp_month = (uint8_t)GET_DTS_MON(temp_dts);
521 rtc_timestamp->rtc_timestamp_date = (uint8_t)GET_DTS_DAY(temp_dts);
522 rtc_timestamp->rtc_timestamp_day = (uint8_t)GET_DTS_DOW(temp_dts);
523 rtc_timestamp->rtc_timestamp_hour = (uint8_t)GET_TTS_HR(temp_tts);
524 rtc_timestamp->rtc_timestamp_minute = (uint8_t)GET_TTS_MN(temp_tts);
525 rtc_timestamp->rtc_timestamp_second = (uint8_t)GET_TTS_SC(temp_tts);
526 }
GET_DTS_DAY
#define GET_DTS_DAY(regval)
Definition: gd32f3x0_rtc.h:352
GET_TTS_SC
#define GET_TTS_SC(regval)
Definition: gd32f3x0_rtc.h:342
rtc_timestamp_struct::rtc_timestamp_second
uint8_t rtc_timestamp_second
Definition: gd32f3x0_rtc.h:221
rtc_timestamp_struct::rtc_timestamp_date
uint8_t rtc_timestamp_date
Definition: gd32f3x0_rtc.h:217
RTC_TTS_PM
#define RTC_TTS_PM
Definition: gd32f3x0_rtc.h:129
GET_TTS_MN
#define GET_TTS_MN(regval)
Definition: gd32f3x0_rtc.h:345
rtc_timestamp_struct::rtc_am_pm
uint32_t rtc_am_pm
Definition: gd32f3x0_rtc.h:222
rtc_timestamp_struct::rtc_timestamp_day
uint8_t rtc_timestamp_day
Definition: gd32f3x0_rtc.h:218
RTC_DTS
#define RTC_DTS
Definition: gd32f3x0_rtc.h:31
GET_TTS_HR
#define GET_TTS_HR(regval)
Definition: gd32f3x0_rtc.h:348
rtc_timestamp_struct::rtc_timestamp_minute
uint8_t rtc_timestamp_minute
Definition: gd32f3x0_rtc.h:220
RTC_TTS
#define RTC_TTS
Definition: gd32f3x0_rtc.h:30
GET_DTS_MON
#define GET_DTS_MON(regval)
Definition: gd32f3x0_rtc.h:355
rtc_timestamp_struct::rtc_timestamp_month
uint8_t rtc_timestamp_month
Definition: gd32f3x0_rtc.h:216
rtc_timestamp_struct::rtc_timestamp_hour
uint8_t rtc_timestamp_hour
Definition: gd32f3x0_rtc.h:219
GET_DTS_DOW
#define GET_DTS_DOW(regval)
Definition: gd32f3x0_rtc.h:358
uint32_t rtc_timestamp_subsecond_get ( void )

get RTC time-stamp subsecond

Parameters
[in] | none
[out] | none
Return values
RTC time-stamp subsecond value

Definition at line 534 of file gd32f3x0_rtc.c.

535 {
536 return ((uint32_t)RTC_SSTS);
537 }
RTC_SSTS
#define RTC_SSTS
Definition: gd32f3x0_rtc.h:32
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_spi.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Macros | Functions
gd32f3x0_spi.c File Reference

SPI driver. More...

#include "gd32f3x0_spi.h"

Go to the source code of this file.

Macros

#define | SPI_INIT_MASK ((uint32_t)0x00003040U)
#define | I2S_INIT_MASK ((uint32_t)0x0000F047U)
#define | SPI_I2SPSC_RESET ((uint32_t)0x00000002U)

Functions

void | spi_i2s_deinit (uint32_t spi_periph)
reset SPI and I2S More...
void | spi_init (uint32_t spi_periph, spi_parameter_struct *spi_struct)
initialize SPI parameter More...
void | spi_enable (uint32_t spi_periph)
enable SPI More...
void | spi_disable (uint32_t spi_periph)
disable SPI More...
void | spi_nss_output_enable (uint32_t spi_periph)
enable SPI NSS output More...
void | spi_nss_output_disable (uint32_t spi_periph)
disable SPI NSS output More...
void | spi_nss_internal_high (uint32_t spi_periph)
SPI NSS pin high level in software mode. More...
void | spi_nss_internal_low (uint32_t spi_periph)
SPI NSS pin low level in software mode. More...
void | spi_dma_enable (uint32_t spi_periph, uint8_t dma)
enable SPI DMA send or receive More...
void | spi_dma_disable (uint32_t spi_periph, uint8_t dma)
disable SPI DMA send or receive More...
void | spi_i2s_data_frame_format_config (uint32_t spi_periph, uint16_t frame_format)
configure SPI/I2S data frame format More...
void | spi_i2s_data_transmit (uint32_t spi_periph, uint16_t data)
SPI transmit data. More...
uint16_t | spi_i2s_data_receive (uint32_t spi_periph)
SPI receive data. More...
void | spi_bidirectional_transfer_config (uint32_t spi_periph, uint32_t transfer_direction)
configure SPI bidirectional transfer direction More...
void | spi_i2s_interrupt_enable (uint32_t spi_periph, uint8_t interrupt)
enable SPI and I2S interrupt More...
void | spi_i2s_interrupt_disable (uint32_t spi_periph, uint8_t interrupt)
disable SPI and I2S interrupt More...
FlagStatus | spi_i2s_interrupt_flag_get (uint32_t spi_periph, uint8_t interrupt)
get SPI and I2S interrupt flag status More...
FlagStatus | spi_i2s_flag_get (uint32_t spi_periph, uint32_t flag)
get SPI and I2S flag status More...
void | spi_crc_error_clear (uint32_t spi_periph)
clear SPI CRC error flag status More...
void | spi_crc_on (uint32_t spi_periph)
turn on CRC function More...
void | spi_crc_off (uint32_t spi_periph)
turn off CRC function More...
void | spi_crc_polynomial_set (uint32_t spi_periph, uint16_t crc_poly)
set CRC polynomial More...
uint16_t | spi_crc_polynomial_get (uint32_t spi_periph)
get SPI CRC polynomial More...
void | spi_crc_next (uint32_t spi_periph)
SPI next data is CRC value. More...
uint16_t | spi_crc_get (uint32_t spi_periph, uint8_t crc)
get SPI CRC send value or receive value More...
void | spi_ti_mode_enable (uint32_t spi_periph)
enable SPI TI mode More...
void | spi_ti_mode_disable (uint32_t spi_periph)
disable SPI TI mode More...
void | spi_nssp_mode_enable (uint32_t spi_periph)
enable SPI NSS pulse mode More...
void | spi_nssp_mode_disable (uint32_t spi_periph)
disable SPI NSS pulse mode More...
void | qspi_enable (uint32_t spi_periph)
enable quad wire SPI More...
void | qspi_disable (uint32_t spi_periph)
disable quad wire SPI More...
void | qspi_write_enable (uint32_t spi_periph)
enable quad wire SPI write More...
void | qspi_read_enable (uint32_t spi_periph)
enable quad wire SPI read More...
void | qspi_io23_output_enable (uint32_t spi_periph)
enable SPI_IO2 and SPI_IO3 pin output More...
void | qspi_io23_output_disable (uint32_t spi_periph)
disable SPI_IO2 and SPI_IO3 pin output More...

Detailed Description

SPI driver.

Definition in file gd32f3x0_spi.c.

Macro Definition Documentation

#define I2S_INIT_MASK ((uint32_t)0x0000F047U)

I2S parameter initialization mask

Definition at line 15 of file gd32f3x0_spi.c.

#define SPI_I2SPSC_RESET ((uint32_t)0x00000002U)

I2S clock prescaler register reset value

Definition at line 17 of file gd32f3x0_spi.c.

#define SPI_INIT_MASK ((uint32_t)0x00003040U)

SPI parameter initialization mask

Definition at line 14 of file gd32f3x0_spi.c.

Function Documentation

void qspi_disable ( uint32_t spi_periph )

disable quad wire SPI

Parameters
[in] | spi_periph | SPI1
[out] | none
Return values
none

Definition at line 692 of file gd32f3x0_spi.c.

693 {
694 SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD);
695 }
SPI_QCTL
#define SPI_QCTL(spix)
Definition: gd32f3x0_spi.h:32
SPI_QCTL_QMOD
#define SPI_QCTL_QMOD
Definition: gd32f3x0_spi.h:100
void qspi_enable ( uint32_t spi_periph )

enable quad wire SPI

Parameters
[in] | spi_periph | SPI1
[out] | none
Return values
none

Definition at line 681 of file gd32f3x0_spi.c.

682 {
683 SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD;
684 }
SPI_QCTL
#define SPI_QCTL(spix)
Definition: gd32f3x0_spi.h:32
SPI_QCTL_QMOD
#define SPI_QCTL_QMOD
Definition: gd32f3x0_spi.h:100
void qspi_io23_output_disable ( uint32_t spi_periph )

disable SPI_IO2 and SPI_IO3 pin output

Parameters
[in] | spi_periph | SPI1
[out] | none
Return values
none

Definition at line 736 of file gd32f3x0_spi.c.

737 {
738 SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV);
739 }
SPI_QCTL
#define SPI_QCTL(spix)
Definition: gd32f3x0_spi.h:32
SPI_QCTL_IO23_DRV
#define SPI_QCTL_IO23_DRV
Definition: gd32f3x0_spi.h:102
void qspi_io23_output_enable ( uint32_t spi_periph )

enable SPI_IO2 and SPI_IO3 pin output

Parameters
[in] | spi_periph | SPI1
[out] | none
Return values
none

Definition at line 725 of file gd32f3x0_spi.c.

726 {
727 SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV;
728 }
SPI_QCTL
#define SPI_QCTL(spix)
Definition: gd32f3x0_spi.h:32
SPI_QCTL_IO23_DRV
#define SPI_QCTL_IO23_DRV
Definition: gd32f3x0_spi.h:102
void qspi_read_enable ( uint32_t spi_periph )

enable quad wire SPI read

Parameters
[in] | spi_periph | SPI1
[out] | none
Return values
none

Definition at line 714 of file gd32f3x0_spi.c.

715 {
716 SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD;
717 }
SPI_QCTL
#define SPI_QCTL(spix)
Definition: gd32f3x0_spi.h:32
SPI_QCTL_QRD
#define SPI_QCTL_QRD
Definition: gd32f3x0_spi.h:101
void qspi_write_enable ( uint32_t spi_periph )

enable quad wire SPI write

Parameters
[in] | spi_periph | SPI1
[out] | none
Return values
none

Definition at line 703 of file gd32f3x0_spi.c.

704 {
705 SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD);
706 }
SPI_QCTL
#define SPI_QCTL(spix)
Definition: gd32f3x0_spi.h:32
SPI_QCTL_QRD
#define SPI_QCTL_QRD
Definition: gd32f3x0_spi.h:101
void spi_bidirectional_transfer_config | ( | uint32_t | spi_periph,
 |  | uint32_t | transfer_direction
 | ) |  |

configure SPI bidirectional transfer direction

Parameters
[in] spi_periph SPIx(x=0,1,2)
[in] transfer_direction SPI transfer direction
  • SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode
  • SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode
Return values
none

Definition at line 376 of file gd32f3x0_spi.c.

377 {
378 if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){
379 /* set the transmit only mode */
380 SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
381 }else{
382 /* set the receive only mode */
383 SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
384 }
385 }
SPI_BIDIRECTIONAL_RECEIVE
#define SPI_BIDIRECTIONAL_RECEIVE
Definition: gd32f3x0_spi.h:158
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
SPI_BIDIRECTIONAL_TRANSMIT
#define SPI_BIDIRECTIONAL_TRANSMIT
Definition: gd32f3x0_spi.h:157
void spi_crc_error_clear ( uint32_t spi_periph )

clear SPI CRC error flag status

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 551 of file gd32f3x0_spi.c.

552 {
553 SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR);
554 }
SPI_FLAG_CRCERR
#define SPI_FLAG_CRCERR
Definition: gd32f3x0_spi.h:228
SPI_STAT
#define SPI_STAT(spix)
Definition: gd32f3x0_spi.h:25
uint16_t spi_crc_get | ( | uint32_t | spi_periph,
 |  | uint8_t | crc
 | ) |  |

get SPI CRC send value or receive value

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] crc SPI crc value
  • SPI_CRC_TX: get transmit crc value
  • SPI_CRC_RX: get receive crc value
[out] | none
Return values
16-bit CRC value

Definition at line 622 of file gd32f3x0_spi.c.

623 {
624 if(SPI_CRC_TX == crc){
625 return ((uint16_t)(SPI_TCRC(spi_periph)));
626 }else{
627 return ((uint16_t)(SPI_RCRC(spi_periph)));
628 }
629 }
SPI_RCRC
#define SPI_RCRC(spix)
Definition: gd32f3x0_spi.h:28
SPI_CRC_TX
#define SPI_CRC_TX
Definition: gd32f3x0_spi.h:208
SPI_TCRC
#define SPI_TCRC(spix)
Definition: gd32f3x0_spi.h:29
void spi_crc_next ( uint32_t spi_periph )

SPI next data is CRC value.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 608 of file gd32f3x0_spi.c.

609 {
610 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
611 }
SPI_CTL0_CRCNT
#define SPI_CTL0_CRCNT
Definition: gd32f3x0_spi.h:46
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
void spi_crc_off ( uint32_t spi_periph )

turn off CRC function

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 573 of file gd32f3x0_spi.c.

574 {
575 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
576 }
SPI_CTL0_CRCEN
#define SPI_CTL0_CRCEN
Definition: gd32f3x0_spi.h:47
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
void spi_crc_on ( uint32_t spi_periph )

turn on CRC function

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 562 of file gd32f3x0_spi.c.

563 {
564 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
565 }
SPI_CTL0_CRCEN
#define SPI_CTL0_CRCEN
Definition: gd32f3x0_spi.h:47
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
uint16_t spi_crc_polynomial_get ( uint32_t spi_periph )

get SPI CRC polynomial

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
16-bit CRC polynomial

Definition at line 597 of file gd32f3x0_spi.c.

598 {
599 return ((uint16_t)SPI_CRCPOLY(spi_periph));
600 }
SPI_CRCPOLY
#define SPI_CRCPOLY(spix)
Definition: gd32f3x0_spi.h:27
void spi_crc_polynomial_set | ( | uint32_t | spi_periph,
 |  | uint16_t | crc_poly
 | ) |  |

set CRC polynomial

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] | crc_poly | CRC polynomial value
[out] | none
Return values
none

Definition at line 585 of file gd32f3x0_spi.c.

586 {
587 /* set SPI CRC polynomial */
588 SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
589 }
SPI_CRCPOLY
#define SPI_CRCPOLY(spix)
Definition: gd32f3x0_spi.h:27
void spi_disable ( uint32_t spi_periph )

disable SPI

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 110 of file gd32f3x0_spi.c.

111 {
112 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN);
113 }
SPI_CTL0_SPIEN
#define SPI_CTL0_SPIEN
Definition: gd32f3x0_spi.h:40
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
void spi_dma_disable | ( | uint32_t | spi_periph,
 |  | uint8_t | dma
 | ) |  |

disable SPI DMA send or receive

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] dma SPI DMA mode
  • SPI_DMA_TRANSMIT: SPI transmit data use DMA
  • SPI_DMA_RECEIVE: SPI receive data use DMA
[out] | none
Return values
none

Definition at line 319 of file gd32f3x0_spi.c.

320 {
321 if(SPI_DMA_TRANSMIT == dma){
322 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
323 }else{
324 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
325 }
326 }
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_CTL1_DMATEN
#define SPI_CTL1_DMATEN
Definition: gd32f3x0_spi.h:53
SPI_DMA_TRANSMIT
#define SPI_DMA_TRANSMIT
Definition: gd32f3x0_spi.h:204
SPI_CTL1_DMAREN
#define SPI_CTL1_DMAREN
Definition: gd32f3x0_spi.h:52
void spi_dma_enable | ( | uint32_t | spi_periph,
 |  | uint8_t | dma
 | ) |  |

enable SPI DMA send or receive

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] dma SPI DMA mode
  • SPI_DMA_TRANSMIT: SPI transmit data use DMA
  • SPI_DMA_RECEIVE: SPI receive data use DMA
[out] | none
Return values
none

Definition at line 301 of file gd32f3x0_spi.c.

302 {
303 if(SPI_DMA_TRANSMIT == dma){
304 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
305 }else{
306 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
307 }
308 }
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_CTL1_DMATEN
#define SPI_CTL1_DMATEN
Definition: gd32f3x0_spi.h:53
SPI_DMA_TRANSMIT
#define SPI_DMA_TRANSMIT
Definition: gd32f3x0_spi.h:204
SPI_CTL1_DMAREN
#define SPI_CTL1_DMAREN
Definition: gd32f3x0_spi.h:52
void spi_enable ( uint32_t spi_periph )

enable SPI

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 99 of file gd32f3x0_spi.c.

100 {
101 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN;
102 }
SPI_CTL0_SPIEN
#define SPI_CTL0_SPIEN
Definition: gd32f3x0_spi.h:40
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
void spi_i2s_data_frame_format_config | ( | uint32_t | spi_periph,
 |  | uint16_t | frame_format
 | ) |  |

configure SPI/I2S data frame format

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] frame_format SPI frame size
  • SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits
  • SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits
[out] | none
Return values
none

Definition at line 337 of file gd32f3x0_spi.c.

338 {
339 /* clear SPI_CTL0_FF16 bit */
340 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
341 /* confige SPI_CTL0_FF16 bit */
342 SPI_CTL0(spi_periph) |= (uint32_t)frame_format;
343 }
SPI_CTL0_FF16
#define SPI_CTL0_FF16
Definition: gd32f3x0_spi.h:45
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
uint16_t spi_i2s_data_receive ( uint32_t spi_periph )

SPI receive data.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
16-bit data

Definition at line 363 of file gd32f3x0_spi.c.

364 {
365 return ((uint16_t)SPI_DATA(spi_periph));
366 }
SPI_DATA
#define SPI_DATA(spix)
Definition: gd32f3x0_spi.h:26
void spi_i2s_data_transmit | ( | uint32_t | spi_periph,
 |  | uint16_t | data
 | ) |  |

SPI transmit data.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] | data | 16-bit data
[out] | none
Return values
none

Definition at line 352 of file gd32f3x0_spi.c.

353 {
354 SPI_DATA(spi_periph) = (uint32_t)data;
355 }
SPI_DATA
#define SPI_DATA(spix)
Definition: gd32f3x0_spi.h:26
void spi_i2s_deinit ( uint32_t spi_periph )

reset SPI and I2S

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 25 of file gd32f3x0_spi.c.

26 {
27 switch(spi_periph){
28 case SPI0:
29 /* reset SPI0 and I2S0 */
30 rcu_periph_reset_enable(RCU_SPI0RST);
31 rcu_periph_reset_disable(RCU_SPI0RST);
32 break;
33 case SPI1:
34 /* reset SPI1 */
35 rcu_periph_reset_enable(RCU_SPI1RST);
36 rcu_periph_reset_disable(RCU_SPI1RST);
37 break;
38 case SPI2:
39 /* reset SPI2 and I2S2 */
40 rcu_periph_reset_enable(RCU_SPI2RST);
41 rcu_periph_reset_disable(RCU_SPI2RST);
42 break;
43 default :
44 break;
45 }
46 }
SPI1
#define SPI1
Definition: gd32f3x0_spi.h:19
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
RCU_SPI0RST
Definition: gd32f3x0_rcu.h:337
SPI0
#define SPI0
Definition: gd32f3x0_spi.h:18
SPI2
#define SPI2
Definition: gd32f3x0_spi.h:20
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
RCU_SPI1RST
Definition: gd32f3x0_rcu.h:348
RCU_SPI2RST
Definition: gd32f3x0_rcu.h:349
FlagStatus spi_i2s_flag_get | ( | uint32_t | spi_periph,
 |  | uint32_t | flag
 | ) |  |

get SPI and I2S flag status

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] flag SPI/I2S flag status
  • SPI_FLAG_TBE: transmit buffer empty flag
  • SPI_FLAG_RBNE: receive buffer not empty flag
  • SPI_FLAG_TRANS: transmit on-going flag
  • SPI_FLAG_RXORERR: receive overrun error flag
  • SPI_FLAG_CONFERR: mode config error flag
  • SPI_FLAG_CRCERR: CRC error flag
  • SPI_FLAG_FERR: format error interrupt flag
  • I2S_FLAG_TBE: transmit buffer empty flag
  • I2S_FLAG_RBNE: receive buffer not empty flag
  • I2S_FLAG_TRANS: transmit on-going flag
  • I2S_FLAG_RXORERR: overrun error flag
  • I2S_FLAG_TXURERR: underrun error flag
  • I2S_FLAG_CH: channel side flag
  • I2S_FLAG_FERR: format error interrupt flag
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 536 of file gd32f3x0_spi.c.

537 {
538 if(SPI_STAT(spi_periph) & flag){
539 return SET;
540 }else{
541 return RESET;
542 }
543 }
SPI_STAT
#define SPI_STAT(spix)
Definition: gd32f3x0_spi.h:25
void spi_i2s_interrupt_disable | ( | uint32_t | spi_periph,
 |  | uint8_t | interrupt
 | ) |  |

disable SPI and I2S interrupt

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] interrupt SPI/I2S interrupt
  • SPI_I2S_INT_TBE: transmit buffer empty interrupt
  • SPI_I2S_INT_RBNE: receive buffer not empty interrupt
  • SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, transmission underrun error and format error interrupt
[out] | none
Return values
none

Definition at line 429 of file gd32f3x0_spi.c.

430 {
431 switch(interrupt){
432 /* SPI/I2S transmit buffer empty interrupt */
433 case SPI_I2S_INT_TBE:
434 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
435 break;
436 /* SPI/I2S receive buffer not empty interrupt */
437 case SPI_I2S_INT_RBNE:
438 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
439 break;
440 /* SPI/I2S error */
441 case SPI_I2S_INT_ERR:
442 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
443 break;
444 default :
445 break;
446 }
447 }
SPI_I2S_INT_ERR
#define SPI_I2S_INT_ERR
Definition: gd32f3x0_spi.h:214
SPI_CTL1_ERRIE
#define SPI_CTL1_ERRIE
Definition: gd32f3x0_spi.h:57
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_I2S_INT_RBNE
#define SPI_I2S_INT_RBNE
Definition: gd32f3x0_spi.h:213
SPI_CTL1_TBEIE
#define SPI_CTL1_TBEIE
Definition: gd32f3x0_spi.h:59
SPI_I2S_INT_TBE
#define SPI_I2S_INT_TBE
Definition: gd32f3x0_spi.h:212
SPI_CTL1_RBNEIE
#define SPI_CTL1_RBNEIE
Definition: gd32f3x0_spi.h:58
void spi_i2s_interrupt_enable | ( | uint32_t | spi_periph,
 |  | uint8_t | interrupt
 | ) |  |

enable SPI and I2S interrupt

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] interrupt SPI/I2S interrupt
  • SPI_I2S_INT_TBE: transmit buffer empty interrupt
  • SPI_I2S_INT_RBNE: receive buffer not empty interrupt
  • SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, transmission underrun error and format error interrupt
[out] | none
Return values
none

Definition at line 398 of file gd32f3x0_spi.c.

399 {
400 switch(interrupt){
401 /* SPI/I2S transmit buffer empty interrupt */
402 case SPI_I2S_INT_TBE:
403 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
404 break;
405 /* SPI/I2S receive buffer not empty interrupt */
406 case SPI_I2S_INT_RBNE:
407 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE;
408 break;
409 /* SPI/I2S error */
410 case SPI_I2S_INT_ERR:
411 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE;
412 break;
413 default:
414 break;
415 }
416 }
SPI_I2S_INT_ERR
#define SPI_I2S_INT_ERR
Definition: gd32f3x0_spi.h:214
SPI_CTL1_ERRIE
#define SPI_CTL1_ERRIE
Definition: gd32f3x0_spi.h:57
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_I2S_INT_RBNE
#define SPI_I2S_INT_RBNE
Definition: gd32f3x0_spi.h:213
SPI_CTL1_TBEIE
#define SPI_CTL1_TBEIE
Definition: gd32f3x0_spi.h:59
SPI_I2S_INT_TBE
#define SPI_I2S_INT_TBE
Definition: gd32f3x0_spi.h:212
SPI_CTL1_RBNEIE
#define SPI_CTL1_RBNEIE
Definition: gd32f3x0_spi.h:58
FlagStatus spi_i2s_interrupt_flag_get | ( | uint32_t | spi_periph,
 |  | uint8_t | interrupt
 | ) |  |

get SPI and I2S interrupt flag status

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] interrupt SPI/I2S interrupt flag status
  • SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag
  • SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag
  • SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag
  • SPI_INT_FLAG_CONFERR: config error interrupt flag
  • SPI_INT_FLAG_CRCERR: CRC error interrupt flag
  • I2S_INT_FLAG_TXURERR: underrun error interrupt flag
  • SPI_I2S_INT_FLAG_FERR: format error interrupt flag
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 463 of file gd32f3x0_spi.c.

464 {
465 uint32_t reg1 = SPI_STAT(spi_periph);
466 uint32_t reg2 = SPI_CTL1(spi_periph);
467
468 switch(interrupt){
469 /* SPI/I2S transmit buffer empty interrupt */
470 case SPI_I2S_INT_FLAG_TBE:
471 reg1 = reg1 & SPI_STAT_TBE;
472 reg2 = reg2 & SPI_CTL1_TBEIE;
473 break;
474 /* SPI/I2S receive buffer not empty interrupt */
475 case SPI_I2S_INT_FLAG_RBNE:
476 reg1 = reg1 & SPI_STAT_RBNE;
477 reg2 = reg2 & SPI_CTL1_RBNEIE;
478 break;
479 /* SPI/I2S overrun interrupt */
480 case SPI_I2S_INT_FLAG_RXORERR:
481 reg1 = reg1 & SPI_STAT_RXORERR;
482 reg2 = reg2 & SPI_CTL1_ERRIE;
483 break;
484 /* SPI config error interrupt */
485 case SPI_INT_FLAG_CONFERR:
486 reg1 = reg1 & SPI_STAT_CONFERR;
487 reg2 = reg2 & SPI_CTL1_ERRIE;
488 break;
489 /* SPI CRC error interrupt */
490 case SPI_INT_FLAG_CRCERR:
491 reg1 = reg1 & SPI_STAT_CRCERR;
492 reg2 = reg2 & SPI_CTL1_ERRIE;
493 break;
494 /* I2S underrun error interrupt */
495 case I2S_INT_FLAG_TXURERR:
496 reg1 = reg1 & SPI_STAT_TXURERR;
497 reg2 = reg2 & SPI_CTL1_ERRIE;
498 break;
499 /* SPI/I2S format error interrupt */
500 case SPI_I2S_INT_FLAG_FERR:
501 reg1 = reg1 & SPI_STAT_FERR;
502 reg2 = reg2 & SPI_CTL1_ERRIE;
503 break;
504 default :
505 break;
506 }
507 /*get SPI/I2S interrupt flag status */
508 if(reg1 && reg2){
509 return SET;
510 }else{
511 return RESET;
512 }
513 }
SPI_STAT_CONFERR
#define SPI_STAT_CONFERR
Definition: gd32f3x0_spi.h:67
SPI_CTL1_ERRIE
#define SPI_CTL1_ERRIE
Definition: gd32f3x0_spi.h:57
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_STAT_TBE
#define SPI_STAT_TBE
Definition: gd32f3x0_spi.h:63
SPI_STAT
#define SPI_STAT(spix)
Definition: gd32f3x0_spi.h:25
SPI_I2S_INT_FLAG_RBNE
#define SPI_I2S_INT_FLAG_RBNE
Definition: gd32f3x0_spi.h:218
SPI_INT_FLAG_CONFERR
#define SPI_INT_FLAG_CONFERR
Definition: gd32f3x0_spi.h:220
SPI_I2S_INT_FLAG_TBE
#define SPI_I2S_INT_FLAG_TBE
Definition: gd32f3x0_spi.h:217
SPI_STAT_CRCERR
#define SPI_STAT_CRCERR
Definition: gd32f3x0_spi.h:66
SPI_CTL1_TBEIE
#define SPI_CTL1_TBEIE
Definition: gd32f3x0_spi.h:59
SPI_STAT_RBNE
#define SPI_STAT_RBNE
Definition: gd32f3x0_spi.h:62
SPI_I2S_INT_FLAG_FERR
#define SPI_I2S_INT_FLAG_FERR
Definition: gd32f3x0_spi.h:223
SPI_I2S_INT_FLAG_RXORERR
#define SPI_I2S_INT_FLAG_RXORERR
Definition: gd32f3x0_spi.h:219
SPI_INT_FLAG_CRCERR
#define SPI_INT_FLAG_CRCERR
Definition: gd32f3x0_spi.h:221
I2S_INT_FLAG_TXURERR
#define I2S_INT_FLAG_TXURERR
Definition: gd32f3x0_spi.h:222
SPI_STAT_TXURERR
#define SPI_STAT_TXURERR
Definition: gd32f3x0_spi.h:65
SPI_STAT_FERR
#define SPI_STAT_FERR
Definition: gd32f3x0_spi.h:70
SPI_CTL1_RBNEIE
#define SPI_CTL1_RBNEIE
Definition: gd32f3x0_spi.h:58
SPI_STAT_RXORERR
#define SPI_STAT_RXORERR
Definition: gd32f3x0_spi.h:68
void spi_init | ( | uint32_t | spi_periph,
 |  | spi_parameter_struct * | spi_struct
 | ) |  |

initialize SPI parameter

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[in] | spi_struct | SPI parameter initialization stuct members of the structure and the member values are shown as below: device_mode: SPI_MASTER, SPI_SLAVE trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT nss: SPI_NSS_SOFT, SPI_NSS_HARD endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256)
[out] | none
Return values
none

Definition at line 65 of file gd32f3x0_spi.c.

66 {
67 uint32_t reg = 0U;
68 reg = SPI_CTL0(spi_periph);
69 reg &= SPI_INIT_MASK;
70
71 /* select SPI as master or slave */
72 reg |= spi_struct->device_mode;
73 /* select SPI transfer mode */
74 reg |= spi_struct->trans_mode;
75 /* select SPI frame size */
76 reg |= spi_struct->frame_size;
77 /* select SPI NSS use hardware or software */
78 reg |= spi_struct->nss;
79 /* select SPI LSB or MSB */
80 reg |= spi_struct->endian;
81 /* select SPI polarity and phase */
82 reg |= spi_struct->clock_polarity_phase;
83 /* select SPI prescale to adjust transmit speed */
84 reg |= spi_struct->prescale;
85
86 /* write to SPI_CTL0 register */
87 SPI_CTL0(spi_periph) = (uint32_t)reg;
88
89 /* select SPI mode */
90 SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL);
91 }
spi_parameter_struct::nss
uint32_t nss
Definition: gd32f3x0_spi.h:111
spi_parameter_struct::device_mode
uint32_t device_mode
Definition: gd32f3x0_spi.h:108
spi_parameter_struct::frame_size
uint32_t frame_size
Definition: gd32f3x0_spi.h:110
spi_parameter_struct::trans_mode
uint32_t trans_mode
Definition: gd32f3x0_spi.h:109
SPI_INIT_MASK
#define SPI_INIT_MASK
Definition: gd32f3x0_spi.c:14
SPI_I2SCTL_I2SSEL
#define SPI_I2SCTL_I2SSEL
Definition: gd32f3x0_spi.h:92
spi_parameter_struct::endian
uint32_t endian
Definition: gd32f3x0_spi.h:112
spi_parameter_struct::clock_polarity_phase
uint32_t clock_polarity_phase
Definition: gd32f3x0_spi.h:113
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
SPI_I2SCTL
#define SPI_I2SCTL(spix)
Definition: gd32f3x0_spi.h:30
spi_parameter_struct::prescale
uint32_t prescale
Definition: gd32f3x0_spi.h:114
void spi_nss_internal_high ( uint32_t spi_periph )

SPI NSS pin high level in software mode.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 276 of file gd32f3x0_spi.c.

277 {
278 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS;
279 }
SPI_CTL0_SWNSS
#define SPI_CTL0_SWNSS
Definition: gd32f3x0_spi.h:42
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
void spi_nss_internal_low ( uint32_t spi_periph )

SPI NSS pin low level in software mode.

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 287 of file gd32f3x0_spi.c.

288 {
289 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS);
290 }
SPI_CTL0_SWNSS
#define SPI_CTL0_SWNSS
Definition: gd32f3x0_spi.h:42
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
void spi_nss_output_disable ( uint32_t spi_periph )

disable SPI NSS output

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 265 of file gd32f3x0_spi.c.

266 {
267 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
268 }
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_CTL1_NSSDRV
#define SPI_CTL1_NSSDRV
Definition: gd32f3x0_spi.h:54
void spi_nss_output_enable ( uint32_t spi_periph )

enable SPI NSS output

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 254 of file gd32f3x0_spi.c.

255 {
256 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
257 }
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_CTL1_NSSDRV
#define SPI_CTL1_NSSDRV
Definition: gd32f3x0_spi.h:54
void spi_nssp_mode_disable ( uint32_t spi_periph )

disable SPI NSS pulse mode

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 670 of file gd32f3x0_spi.c.

671 {
672 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP);
673 }
SPI_CTL1_NSSP
#define SPI_CTL1_NSSP
Definition: gd32f3x0_spi.h:55
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
void spi_nssp_mode_enable ( uint32_t spi_periph )

enable SPI NSS pulse mode

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 659 of file gd32f3x0_spi.c.

660 {
661 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP;
662 }
SPI_CTL1_NSSP
#define SPI_CTL1_NSSP
Definition: gd32f3x0_spi.h:55
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
void spi_ti_mode_disable ( uint32_t spi_periph )

disable SPI TI mode

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 648 of file gd32f3x0_spi.c.

649 {
650 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD);
651 }
SPI_CTL1_TMOD
#define SPI_CTL1_TMOD
Definition: gd32f3x0_spi.h:56
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
void spi_ti_mode_enable ( uint32_t spi_periph )

enable SPI TI mode

Parameters
[in] | spi_periph | SPIx(x=0,1,2)
[out] | none
Return values
none

Definition at line 637 of file gd32f3x0_spi.c.

638 {
639 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD;
640 }
SPI_CTL1_TMOD
#define SPI_CTL1_TMOD
Definition: gd32f3x0_spi.h:56
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_syscfg.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_syscfg.c File Reference

SYSCFG driver. More...

#include "gd32f3x0_syscfg.h"

Go to the source code of this file.

Functions

void | syscfg_deinit (void)
reset the SYSCFG registers More...
void | syscfg_dma_remap_enable (uint32_t syscfg_dma_remap)
enable the DMA channels remapping More...
void | syscfg_dma_remap_disable (uint32_t syscfg_dma_remap)
disable the DMA channels remapping More...
void | syscfg_high_current_enable (void)
enable PB9 high current capability More...
void | syscfg_high_current_disable (void)
disable PB9 high current capability More...
void | syscfg_exti_line_config (uint8_t exti_port, uint8_t exti_pin)
configure the GPIO pin as EXTI Line More...
void | syscfg_lock_config (uint32_t syscfg_lock)
connect TIMER0/14/15/16 break input to the selected parameter More...
FlagStatus | syscfg_flag_get (uint32_t syscfg_flag)
check if the specified flag in SYSCFG_CFG2 is set or not. More...
void | syscfg_flag_clear (uint32_t syscfg_flag)
clear the flag in SYSCFG_CFG2 by writing 1. More...
void | syscfg_compensation_config (uint32_t syscfg_compensation)
configure the I/O compensation cell More...
FlagStatus | syscfg_cps_rdy_flag_get (void)
check if the I/O compensation cell ready flag is set or not More...

Detailed Description

SYSCFG driver.

Definition in file gd32f3x0_syscfg.c.

Function Documentation

void syscfg_compensation_config ( uint32_t syscfg_compensation )

configure the I/O compensation cell

Parameters
[in] syscfg_compensation specifies the I/O compensation cell mode
  • SYSCFG_COMPENSATION_ENABLE: I/O compensation cell is enabled
  • SYSCFG_COMPENSATION_DISABLE: I/O compensation cell is disabled
[out] none
Return values
none

Definition at line 174 of file gd32f3x0_syscfg.c.

175 {
176 uint32_t reg;
177
178 reg = SYSCFG_CPSCTL;
179 /* reset the SYSCFG_CPSCTL_CPS_EN bit and set according to syscfg_compensation */
180 reg &= ~SYSCFG_CPSCTL_CPS_EN;
181 SYSCFG_CPSCTL = (reg | syscfg_compensation);
182 }
SYSCFG_CPSCTL_CPS_EN
#define SYSCFG_CPSCTL_CPS_EN
Definition: gd32f3x0_syscfg.h:69
SYSCFG_CPSCTL
#define SYSCFG_CPSCTL
Definition: gd32f3x0_syscfg.h:27
FlagStatus syscfg_cps_rdy_flag_get ( void )

check if the I/O compensation cell ready flag is set or not

Parameters
[in] | none
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 190 of file gd32f3x0_syscfg.c.

191 {
192 if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)){
193 return SET;
194 }else{
195 return RESET;
196 }
197 }
SYSCFG_CPSCTL_CPS_RDY
#define SYSCFG_CPSCTL_CPS_RDY
Definition: gd32f3x0_syscfg.h:70
SYSCFG_CPSCTL
#define SYSCFG_CPSCTL
Definition: gd32f3x0_syscfg.h:27
void syscfg_deinit ( void )

reset the SYSCFG registers

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_syscfg.c.

21 {
22 rcu_periph_reset_enable(RCU_CFGCMPRST);
23 rcu_periph_reset_disable(RCU_CFGCMPRST);
24 }
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
RCU_CFGCMPRST
Definition: gd32f3x0_rcu.h:334
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
void syscfg_dma_remap_disable ( uint32_t syscfg_dma_remap )

disable the DMA channels remapping

Parameters
[in] syscfg_dma_remap specify the DMA channels to remap
  • SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
  • SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
  • SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
  • SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1)
  • SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1
[out] none
Return values
none

Definition at line 53 of file gd32f3x0_syscfg.c.

54 {
55 SYSCFG_CFG0 &= ~syscfg_dma_remap;
56 }
SYSCFG_CFG0
#define SYSCFG_CFG0
Definition: gd32f3x0_syscfg.h:21
void syscfg_dma_remap_enable ( uint32_t syscfg_dma_remap )

enable the DMA channels remapping

Parameters
[in] syscfg_dma_remap specify the DMA channels to remap
  • SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
  • SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
  • SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
  • SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1)
  • SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1
[out] none
Return values
none

Definition at line 37 of file gd32f3x0_syscfg.c.

38 {
39 SYSCFG_CFG0 |= syscfg_dma_remap;
40 }
SYSCFG_CFG0
#define SYSCFG_CFG0
Definition: gd32f3x0_syscfg.h:21
void syscfg_exti_line_config | ( | uint8_t | exti_port,
 |  | uint8_t | exti_pin
 | ) |  |

configure the GPIO pin as EXTI Line

Parameters
[in] exti_port specify the GPIO port used in EXTI
  • EXTI_SOURCE_GPIOx(x = A,B,C,D,F): EXTI GPIO port
[in] exti_pin specify the EXTI line
  • EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin
[out] none
Return values
none

Definition at line 89 of file gd32f3x0_syscfg.c.

90 {
91 uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin)));
92 uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin));
93
94 switch(exti_pin / EXTI_SS_JSTEP){
95 case EXTISS0:
96 /* clear EXTI source line(0..3) */
97 SYSCFG_EXTISS0 &= clear_exti_mask;
98 /* configure EXTI soure line(0..3) */
99 SYSCFG_EXTISS0 |= config_exti_mask;
100 break;
101 case EXTISS1:
102 /* clear EXTI soure line(4..7) */
103 SYSCFG_EXTISS1 &= clear_exti_mask;
104 /* configure EXTI soure line(4..7) */
105 SYSCFG_EXTISS1 |= config_exti_mask;
106 break;
107 case EXTISS2:
108 /* clear EXTI soure line(8..11) */
109 SYSCFG_EXTISS2 &= clear_exti_mask;
110 /* configure EXTI soure line(8..11) */
111 SYSCFG_EXTISS2 |= config_exti_mask;
112 break;
113 case EXTISS3:
114 /* clear EXTI soure line(12..15) */
115 SYSCFG_EXTISS3 &= clear_exti_mask;
116 /* configure EXTI soure line(12..15) */
117 SYSCFG_EXTISS3 |= config_exti_mask;
118 break;
119 default:
120 break;
121 }
122 }
SYSCFG_EXTISS1
#define SYSCFG_EXTISS1
Definition: gd32f3x0_syscfg.h:23
SYSCFG_EXTISS0
#define SYSCFG_EXTISS0
Definition: gd32f3x0_syscfg.h:22
EXTI_SS_MASK
#define EXTI_SS_MASK
Definition: gd32f3x0_syscfg.h:91
EXTISS2
#define EXTISS2
Definition: gd32f3x0_syscfg.h:87
EXTI_SS_JSTEP
#define EXTI_SS_JSTEP
Definition: gd32f3x0_syscfg.h:94
EXTI_SS_MSTEP
#define EXTI_SS_MSTEP(pin)
Definition: gd32f3x0_syscfg.h:97
EXTISS1
#define EXTISS1
Definition: gd32f3x0_syscfg.h:86
SYSCFG_EXTISS3
#define SYSCFG_EXTISS3
Definition: gd32f3x0_syscfg.h:25
EXTISS0
#define EXTISS0
Definition: gd32f3x0_syscfg.h:85
SYSCFG_EXTISS2
#define SYSCFG_EXTISS2
Definition: gd32f3x0_syscfg.h:24
EXTISS3
#define EXTISS3
Definition: gd32f3x0_syscfg.h:88
void syscfg_flag_clear ( uint32_t syscfg_flag )

clear the flag in SYSCFG_CFG2 by writing 1.

Parameters
[in] syscfg_flag Specify the flag in SYSCFG_CFG2 to clear.
  • SYSCFG_SRAM_PCEF: SRAM parity check error flag.
[out] none
Return values
none

Definition at line 161 of file gd32f3x0_syscfg.c.

162 {
163 SYSCFG_CFG2 |= (uint32_t) syscfg_flag;
164 }
SYSCFG_CFG2
#define SYSCFG_CFG2
Definition: gd32f3x0_syscfg.h:26
FlagStatus syscfg_flag_get ( uint32_t syscfg_flag )

check if the specified flag in SYSCFG_CFG2 is set or not.

Parameters
[in] syscfg_flag specify the flag in SYSCFG_CFG2 to check.
  • SYSCFG_SRAM_PCEF: SRAM parity check error flag.
[out] none
Return values
the syscfg_flag state returned (SET or RESET).

Definition at line 145 of file gd32f3x0_syscfg.c.

146 {
147 if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET){
148 return SET;
149 }else{
150 return RESET;
151 }
152 }
SYSCFG_CFG2
#define SYSCFG_CFG2
Definition: gd32f3x0_syscfg.h:26
void syscfg_high_current_disable ( void )

disable PB9 high current capability

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 75 of file gd32f3x0_syscfg.c.

76 {
77 SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE;
78 }
SYSCFG_CFG0
#define SYSCFG_CFG0
Definition: gd32f3x0_syscfg.h:21
SYSCFG_HIGH_CURRENT_DISABLE
#define SYSCFG_HIGH_CURRENT_DISABLE
Definition: gd32f3x0_syscfg.h:82
void syscfg_high_current_enable ( void )

enable PB9 high current capability

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 64 of file gd32f3x0_syscfg.c.

65 {
66 SYSCFG_CFG0 |= SYSCFG_HIGH_CURRENT_ENABLE;
67 }
SYSCFG_CFG0
#define SYSCFG_CFG0
Definition: gd32f3x0_syscfg.h:21
SYSCFG_HIGH_CURRENT_ENABLE
#define SYSCFG_HIGH_CURRENT_ENABLE
Definition: gd32f3x0_syscfg.h:81
void syscfg_lock_config ( uint32_t syscfg_lock )

connect TIMER0/14/15/16 break input to the selected parameter

Parameters
[in] syscfg_lock Specify the parameter to be connected
  • SYSCFG_LOCK_LOCKUP: Cortex-M4 lockup output connected to the break input
  • SYSCFG_LOCK_SRAM_PARITY_ERROR: SRAM_PARITY check error connected to the break input
  • SYSCFG_LOCK_LVD: LVD interrupt connected to the break input
[out] none
Return values
none

Definition at line 133 of file gd32f3x0_syscfg.c.

134 {
135 SYSCFG_CFG2 |= syscfg_lock;
136 }
SYSCFG_CFG2
#define SYSCFG_CFG2
Definition: gd32f3x0_syscfg.h:26
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_timer.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_timer.c File Reference

TIMER driver. More...

#include "gd32f3x0_timer.h"

Go to the source code of this file.

Functions

void | timer_deinit (uint32_t timer_periph)
deinit a TIMER More...
void | timer_init (uint32_t timer_periph, timer_parameter_struct *initpara)
initialize TIMER counter More...
void | timer_enable (uint32_t timer_periph)
enable a TIMER More...
void | timer_disable (uint32_t timer_periph)
disable a TIMER More...
void | timer_auto_reload_shadow_enable (uint32_t timer_periph)
enable the auto reload shadow function More...
void | timer_auto_reload_shadow_disable (uint32_t timer_periph)
disable the auto reload shadow function More...
void | timer_update_event_enable (uint32_t timer_periph)
enable the update event More...
void | timer_update_event_disable (uint32_t timer_periph)
disable the update event More...
void | timer_counter_alignment (uint32_t timer_periph, uint16_t aligned)
set TIMER counter alignment mode More...
void | timer_counter_up_direction (uint32_t timer_periph)
set TIMER counter up direction More...
void | timer_counter_down_direction (uint32_t timer_periph)
set TIMER counter down direction More...
void | timer_prescaler_config (uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
configure TIMER prescaler More...
void | timer_repetition_value_config (uint32_t timer_periph, uint16_t repetition)
configure TIMER repetition register value More...
void | timer_autoreload_value_config (uint32_t timer_periph, uint32_t autoreload)
configure TIMER autoreload register value More...
void | timer_counter_value_config (uint32_t timer_periph, uint32_t counter)
configure TIMER counter register value More...
uint32_t | timer_counter_read (uint32_t timer_periph)
read TIMER counter value More...
uint16_t | timer_prescaler_read (uint32_t timer_periph)
read TIMER prescaler value More...
void | timer_single_pulse_mode_config (uint32_t timer_periph, uint8_t spmode)
configure TIMER single pulse mode More...
void | timer_update_source_config (uint32_t timer_periph, uint8_t update)
configure TIMER update source More...
void | timer_ocpre_clear_source_config (uint32_t timer_periph, uint8_t ocpreclear)
configure TIMER OCPRE clear source selection More...
void | timer_interrupt_enable (uint32_t timer_periph, uint32_t interrupt)
enable the TIMER interrupt More...
void | timer_interrupt_disable (uint32_t timer_periph, uint32_t interrupt)
disable the TIMER interrupt More...
FlagStatus | timer_interrupt_flag_get (uint32_t timer_periph, uint32_t interrupt)
get timer interrupt flag More...
void | timer_interrupt_flag_clear (uint32_t timer_periph, uint32_t interrupt)
clear TIMER interrupt flag More...
FlagStatus | timer_flag_get (uint32_t timer_periph, uint32_t flag)
get TIMER flags More...
void | timer_flag_clear (uint32_t timer_periph, uint32_t flag)
clear TIMER flags More...
void | timer_dma_enable (uint32_t timer_periph, uint16_t dma)
enable the TIMER DMA More...
void | timer_dma_disable (uint32_t timer_periph, uint16_t dma)
disable the TIMER DMA More...
void | timer_channel_dma_request_source_select (uint32_t timer_periph, uint8_t dma_request)
channel DMA request source selection More...
void | timer_dma_transfer_config (uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
configure the TIMER DMA transfer More...
void | timer_event_software_generate (uint32_t timer_periph, uint16_t event)
software generate events More...
void | timer_break_config (uint32_t timer_periph, timer_break_parameter_struct *breakpara)
configure TIMER break function More...
void | timer_break_enable (uint32_t timer_periph)
enable TIMER break function More...
void | timer_break_disable (uint32_t timer_periph)
disable TIMER break function More...
void | timer_automatic_output_enable (uint32_t timer_periph)
enable TIMER output automatic function More...
void | timer_automatic_output_disable (uint32_t timer_periph)
disable TIMER output automatic function More...
void | timer_primary_output_config (uint32_t timer_periph, ControlStatus newvalue)
configure TIMER primary output function More...
void | timer_channel_control_shadow_config (uint32_t timer_periph, ControlStatus newvalue)
channel capture/compare control shadow register enable More...
void | timer_channel_control_shadow_update_config (uint32_t timer_periph, uint8_t ccuctl)
configure TIMER channel control shadow register update control More...
void | timer_channel_output_config (uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara)
configure TIMER channel output function More...
void | timer_channel_output_mode_config (uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
configure TIMER channel output compare mode More...
void | timer_channel_output_pulse_value_config (uint32_t timer_periph, uint16_t channel, uint32_t pulse)
configure TIMER channel output pulse value More...
void | timer_channel_output_shadow_config (uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
configure TIMER channel output shadow function More...
void | timer_channel_output_fast_config (uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
configure TIMER channel output fast function More...
void | timer_channel_output_clear_config (uint32_t timer_periph, uint16_t channel, uint16_t occlear)
configure TIMER channel output clear function More...
void | timer_channel_output_polarity_config (uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
configure TIMER channel output polarity More...
void | timer_channel_complementary_output_polarity_config (uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
configure TIMER channel complementary output polarity More...
void | timer_channel_output_state_config (uint32_t timer_periph, uint16_t channel, uint32_t state)
configure TIMER channel enable state More...
void | timer_channel_complementary_output_state_config (uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
configure TIMER channel complementary output enable state More...
void | timer_input_capture_config (uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara)
configure TIMER input capture parameter More...
void | timer_channel_input_capture_prescaler_config (uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value More...
uint32_t | timer_channel_capture_value_register_read (uint32_t timer_periph, uint16_t channel)
read TIMER channel capture compare register value More...
void | timer_input_pwm_capture_config (uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm)
configure TIMER input pwm capture function More...
void | timer_hall_mode_config (uint32_t timer_periph, uint8_t hallmode)
configure TIMER hall sensor mode More...
void | timer_input_trigger_source_select (uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source More...
void | timer_master_output_trigger_source_select (uint32_t timer_periph, uint32_t outrigger)
select TIMER master mode output trigger source More...
void | timer_slave_mode_select (uint32_t timer_periph, uint32_t slavemode)
select TIMER slave mode More...
void | timer_master_slave_mode_config (uint32_t timer_periph, uint8_t masterslave)
configure TIMER master slave mode More...
void | timer_external_trigger_config (uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input More...
void | timer_quadrature_decoder_mode_config (uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
configure TIMER quadrature decoder mode More...
void | timer_internal_clock_config (uint32_t timer_periph)
configure TIMER internal clock mode More...
void | timer_internal_trigger_as_external_clock_config (uint32_t timer_periph, uint32_t intrigger)
configure TIMER the internal trigger as external clock input More...
void | timer_external_trigger_as_external_clock_config (uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter)
configure TIMER the external trigger as external clock input More...
void | timer_external_clock_mode0_config (uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode0 More...
void | timer_external_clock_mode1_config (uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode1 More...
void | timer_external_clock_mode1_disable (uint32_t timer_periph)
disable TIMER the external clock mode1 More...
void | timer_channel_remap_config (uint32_t timer_periph, uint32_t remap)
configure TIMER channel remap function More...
void | timer_write_cc_register_config (uint32_t timer_periph, uint16_t ccsel)
configure TIMER write CHxVAL register selection More...
void | timer_output_value_selection_config (uint32_t timer_periph, uint16_t outsel)
configure TIMER output value selection More...

Detailed Description

TIMER driver.

Definition in file gd32f3x0_timer.c.

Function Documentation

void timer_auto_reload_shadow_disable ( uint32_t timer_periph )

disable the auto reload shadow function

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
none

Definition at line 153 of file gd32f3x0_timer.c.

154 {
155 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
156 }
TIMER_CTL0_ARSE
#define TIMER_CTL0_ARSE
Definition: gd32f3x0_timer.h:61
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
void timer_auto_reload_shadow_enable ( uint32_t timer_periph )

enable the auto reload shadow function

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
none

Definition at line 142 of file gd32f3x0_timer.c.

143 {
144 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
145 }
TIMER_CTL0_ARSE
#define TIMER_CTL0_ARSE
Definition: gd32f3x0_timer.h:61
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
void timer_automatic_output_disable ( uint32_t timer_periph )

disable TIMER output automatic function

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 671 of file gd32f3x0_timer.c.

672 {
673 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
674 }
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f3x0_timer.h:47
TIMER_CCHP_OAEN
#define TIMER_CCHP_OAEN
Definition: gd32f3x0_timer.h:219
void timer_automatic_output_enable ( uint32_t timer_periph )

enable TIMER output automatic function

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 660 of file gd32f3x0_timer.c.

661 {
662 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
663 }
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f3x0_timer.h:47
TIMER_CCHP_OAEN
#define TIMER_CCHP_OAEN
Definition: gd32f3x0_timer.h:219
void timer_autoreload_value_config | ( | uint32_t | timer_periph,
 |  | uint32_t | autoreload
 | ) |  |

configure TIMER autoreload register value

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[in] | autoreload | the counter auto-reload value
[out] | none
Return values
none

Definition at line 257 of file gd32f3x0_timer.c.

258 {
259 TIMER_CAR(timer_periph) = (uint32_t)autoreload;
260 }
TIMER_CAR
#define TIMER_CAR(timerx)
Definition: gd32f3x0_timer.h:41
void timer_break_config | ( | uint32_t | timer_periph,
 |  | timer_break_parameter_struct * | breakpara
 | ) |  |

configure TIMER break function

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[in] | breakpara | TIMER break parameter struct runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE deadtime: 0~255 breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE
[out] | none
Return values
none

Definition at line 621 of file gd32f3x0_timer.c.

622 {
623 TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))|
624 ((uint32_t)(breakpara->ideloffstate))|
625 ((uint32_t)(breakpara->deadtime))|
626 ((uint32_t)(breakpara->breakpolarity))|
627 ((uint32_t)(breakpara->outputautostate)) |
628 ((uint32_t)(breakpara->protectmode))|
629 ((uint32_t)(breakpara->breakstate))) ;
630 }
timer_break_parameter_struct::deadtime
uint16_t deadtime
Definition: gd32f3x0_timer.h:253
timer_break_parameter_struct::ideloffstate
uint32_t ideloffstate
Definition: gd32f3x0_timer.h:252
timer_break_parameter_struct::outputautostate
uint16_t outputautostate
Definition: gd32f3x0_timer.h:255
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f3x0_timer.h:47
timer_break_parameter_struct::runoffstate
uint16_t runoffstate
Definition: gd32f3x0_timer.h:251
timer_break_parameter_struct::breakpolarity
uint16_t breakpolarity
Definition: gd32f3x0_timer.h:254
timer_break_parameter_struct::breakstate
uint16_t breakstate
Definition: gd32f3x0_timer.h:257
timer_break_parameter_struct::protectmode
uint16_t protectmode
Definition: gd32f3x0_timer.h:256
void timer_break_disable ( uint32_t timer_periph )

disable TIMER break function

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 649 of file gd32f3x0_timer.c.

650 {
651 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
652 }
TIMER_CCHP_BRKEN
#define TIMER_CCHP_BRKEN
Definition: gd32f3x0_timer.h:217
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f3x0_timer.h:47
void timer_break_enable ( uint32_t timer_periph )

enable TIMER break function

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 638 of file gd32f3x0_timer.c.

639 {
640 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
641 }
TIMER_CCHP_BRKEN
#define TIMER_CCHP_BRKEN
Definition: gd32f3x0_timer.h:217
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f3x0_timer.h:47
uint32_t timer_channel_capture_value_register_read | ( | uint32_t | timer_periph,
 |  | uint16_t | channel
 | ) |  |

read TIMER channel capture compare register value

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[out] | none
Return values
channel capture compare register value

Definition at line 1399 of file gd32f3x0_timer.c.

1400 {
1401 uint32_t count_value = 0U;
1402
1403 switch(channel){
1404 case TIMER_CH_0:
1405 count_value = TIMER_CH0CV(timer_periph);
1406 break;
1407 case TIMER_CH_1:
1408 count_value = TIMER_CH1CV(timer_periph);
1409 break;
1410 case TIMER_CH_2:
1411 count_value = TIMER_CH2CV(timer_periph);
1412 break;
1413 case TIMER_CH_3:
1414 count_value = TIMER_CH3CV(timer_periph);
1415 break;
1416 default:
1417 break;
1418 }
1419 return (count_value);
1420 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CH0CV
#define TIMER_CH0CV(timerx)
Definition: gd32f3x0_timer.h:43
TIMER_CH3CV
#define TIMER_CH3CV(timerx)
Definition: gd32f3x0_timer.h:46
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CH1CV
#define TIMER_CH1CV(timerx)
Definition: gd32f3x0_timer.h:44
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CH2CV
#define TIMER_CH2CV(timerx)
Definition: gd32f3x0_timer.h:45
void timer_channel_complementary_output_polarity_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocnpolarity
 | ) |  |

configure TIMER channel complementary output polarity

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel2(TIMERx(x=1,2))
[in] ocnpolarity channel complementary output polarity
  • TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
  • TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
[out] | none
Return values
none

Definition at line 1135 of file gd32f3x0_timer.c.

1136 {
1137 switch(channel){
1138 /* configure TIMER_CH_0 */
1139 case TIMER_CH_0:
1140 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
1141 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
1142 break;
1143 /* configure TIMER_CH_1 */
1144 case TIMER_CH_1:
1145 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
1146 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
1147 break;
1148 /* configure TIMER_CH_2 */
1149 case TIMER_CH_2:
1150 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
1151 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
1152 break;
1153 /* configure TIMER_CH_3 */
1154 case TIMER_CH_3:
1155 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3NP);
1156 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 12U);
1157 break;
1158 default:
1159 break;
1160 }
1161 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL2_CH3NP
#define TIMER_CHCTL2_CH3NP
Definition: gd32f3x0_timer.h:180
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f3x0_timer.h:173
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f3x0_timer.h:169
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
TIMER_CHCTL2_CH2NP
#define TIMER_CHCTL2_CH2NP
Definition: gd32f3x0_timer.h:177
void timer_channel_complementary_output_state_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocnstate
 | ) |  |

configure TIMER channel complementary output enable state

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0,14..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0))
[in] ocnstate TIMER channel complementary output enable state
  • TIMER_CCXN_ENABLE: channel complementary enable
  • TIMER_CCXN_DISABLE: channel complementary disable
[out] | none
Return values
none

Definition at line 1218 of file gd32f3x0_timer.c.

1219 {
1220 switch(channel){
1221 /* configure TIMER_CH_0 */
1222 case TIMER_CH_0:
1223 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
1224 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
1225 break;
1226 /* configure TIMER_CH_1 */
1227 case TIMER_CH_1:
1228 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
1229 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
1230 break;
1231 /* configure TIMER_CH_2 */
1232 case TIMER_CH_2:
1233 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
1234 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
1235 break;
1236 default:
1237 break;
1238 }
1239 }
TIMER_CHCTL2_CH1NEN
#define TIMER_CHCTL2_CH1NEN
Definition: gd32f3x0_timer.h:172
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL2_CH2NEN
#define TIMER_CHCTL2_CH2NEN
Definition: gd32f3x0_timer.h:176
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
TIMER_CHCTL2_CH0NEN
#define TIMER_CHCTL2_CH0NEN
Definition: gd32f3x0_timer.h:168
void timer_channel_control_shadow_config | ( | uint32_t | timer_periph,
 |  | ControlStatus | newvalue
 | ) |  |

channel capture/compare control shadow register enable

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 699 of file gd32f3x0_timer.c.

700 {
701 if(ENABLE == newvalue){
702 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
703 }else{
704 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
705 }
706 }
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f3x0_timer.h:31
TIMER_CTL1_CCSE
#define TIMER_CTL1_CCSE
Definition: gd32f3x0_timer.h:65
void timer_channel_control_shadow_update_config | ( | uint32_t | timer_periph,
 |  | uint8_t | ccuctl
 | ) |  |

configure TIMER channel control shadow register update control

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[in] ccuctl channel control shadow register update control
  • TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
  • TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs
[out] | none
Return values
none

Definition at line 717 of file gd32f3x0_timer.c.

718 {
719 if(TIMER_UPDATECTL_CCU == ccuctl){
720 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
721 }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
722 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
723 }else{
724 }
725 }
TIMER_UPDATECTL_CCU
#define TIMER_UPDATECTL_CCU
Definition: gd32f3x0_timer.h:490
TIMER_CTL1_CCUC
#define TIMER_CTL1_CCUC
Definition: gd32f3x0_timer.h:66
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f3x0_timer.h:31
TIMER_UPDATECTL_CCUTRI
#define TIMER_UPDATECTL_CCUTRI
Definition: gd32f3x0_timer.h:491
void timer_channel_dma_request_source_select | ( | uint32_t | timer_periph,
 |  | uint8_t | dma_request
 | ) |  |

channel DMA request source selection

Parameters
[in] | timer_periph | TIMERx(x=0..2,14..16)
[in] dma_request channel DMA request source selection
  • TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs
  • TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs
[out] | none
Return values
none

Definition at line 542 of file gd32f3x0_timer.c.

543 {
544 if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
545 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
546 }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
547 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
548 }else{
549 }
550 }
TIMER_CTL1_DMAS
#define TIMER_CTL1_DMAS
Definition: gd32f3x0_timer.h:67
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f3x0_timer.h:31
TIMER_DMAREQUEST_CHANNELEVENT
#define TIMER_DMAREQUEST_CHANNELEVENT
Definition: gd32f3x0_timer.h:325
TIMER_DMAREQUEST_UPDATEEVENT
#define TIMER_DMAREQUEST_UPDATEEVENT
Definition: gd32f3x0_timer.h:324
void timer_channel_input_capture_prescaler_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | prescaler
 | ) |  |

configure TIMER channel input capture prescaler value

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] prescaler channel input capture prescaler value
  • TIMER_IC_PSC_DIV1: no prescaler
  • TIMER_IC_PSC_DIV2: divided by 2
  • TIMER_IC_PSC_DIV4: divided by 4
  • TIMER_IC_PSC_DIV8: divided by 8
[out] | none
Return values
none

Definition at line 1360 of file gd32f3x0_timer.c.

1361 {
1362 switch(channel){
1363 /* configure TIMER_CH_0 */
1364 case TIMER_CH_0:
1365 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
1366 TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
1367 break;
1368 /* configure TIMER_CH_1 */
1369 case TIMER_CH_1:
1370 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
1371 TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
1372 break;
1373 /* configure TIMER_CH_2 */
1374 case TIMER_CH_2:
1375 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
1376 TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
1377 break;
1378 /* configure TIMER_CH_3 */
1379 case TIMER_CH_3:
1380 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
1381 TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
1382 break;
1383 default:
1384 break;
1385 }
1386 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CHCTL0_CH1CAPPSC
#define TIMER_CHCTL0_CH1CAPPSC
Definition: gd32f3x0_timer.h:144
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL1_CH2CAPPSC
#define TIMER_CHCTL1_CH2CAPPSC
Definition: gd32f3x0_timer.h:160
TIMER_CHCTL0_CH0CAPPSC
#define TIMER_CHCTL0_CH0CAPPSC
Definition: gd32f3x0_timer.h:142
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL1_CH3CAPPSC
#define TIMER_CHCTL1_CH3CAPPSC
Definition: gd32f3x0_timer.h:162
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
void timer_channel_output_clear_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | occlear
 | ) |  |

configure TIMER channel output clear function

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] occlear channel output clear function
  • TIMER_OC_CLEAR_ENABLE: channel output clear function enable
  • TIMER_OC_CLEAR_DISABLE: channel output clear function disable
[out] | none
Return values
none

Definition at line 1051 of file gd32f3x0_timer.c.

1052 {
1053 switch(channel){
1054 /* configure TIMER_CH_0 */
1055 case TIMER_CH_0:
1056 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
1057 TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
1058 break;
1059 /* configure TIMER_CH_1 */
1060 case TIMER_CH_1:
1061 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
1062 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1063 break;
1064 /* configure TIMER_CH_2 */
1065 case TIMER_CH_2:
1066 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
1067 TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
1068 break;
1069 /* configure TIMER_CH_3 */
1070 case TIMER_CH_3:
1071 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
1072 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1073 break;
1074 default:
1075 break;
1076 }
1077 }
TIMER_CHCTL0_CH0COMCEN
#define TIMER_CHCTL0_CH0COMCEN
Definition: gd32f3x0_timer.h:135
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL1_CH3COMCEN
#define TIMER_CHCTL1_CH3COMCEN
Definition: gd32f3x0_timer.h:158
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL0_CH1COMCEN
#define TIMER_CHCTL0_CH1COMCEN
Definition: gd32f3x0_timer.h:140
TIMER_CHCTL1_CH2COMCEN
#define TIMER_CHCTL1_CH2COMCEN
Definition: gd32f3x0_timer.h:153
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
void timer_channel_output_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | timer_oc_parameter_struct * | ocpara
 | ) |  |

configure TIMER channel output function

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel 0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel 1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel 2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel 3(TIMERx(x=0..2))
[in] | ocpara | TIMER channeln output parameter struct outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH
[out] | none
Return values
none

Definition at line 745 of file gd32f3x0_timer.c.

746 {
747 switch(channel){
748 /* configure TIMER_CH_0 */
749 case TIMER_CH_0:
750 /* reset the CH0EN bit */
751 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
752 /* set the CH0EN bit */
753 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
754 /* reset the CH0P bit */
755 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
756 /* set the CH0P bit */
757 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
758
759 if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){
760 /* reset the CH0NEN bit */
761 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
762 /* set the CH0NEN bit */
763 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
764 /* reset the CH0NP bit */
765 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
766 /* set the CH0NP bit */
767 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
768 /* reset the ISO0 bit */
769 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
770 /* set the ISO0 bit */
771 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
772 /* reset the ISO0N bit */
773 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
774 /* set the ISO0N bit */
775 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
776 }
777 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
778 break;
779 /* configure TIMER_CH_1 */
780 case TIMER_CH_1:
781 /* reset the CH1EN bit */
782 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
783 /* set the CH1EN bit */
784 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 4U);
785 /* reset the CH1P bit */
786 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
787 /* set the CH1P bit */
788 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U);
789
790 if(TIMER0 == timer_periph){
791 /* reset the CH1NEN bit */
792 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
793 /* set the CH1NEN bit */
794 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U);
795 /* reset the CH1NP bit */
796 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
797 /* set the CH1NP bit */
798 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U);
799 /* reset the ISO1 bit */
800 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
801 /* set the ISO1 bit */
802 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
803 /* reset the ISO1N bit */
804 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
805 /* set the ISO1N bit */
806 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U);
807 }
808
809 if(TIMER14 == timer_periph){
810 /* reset the ISO1 bit */
811 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
812 /* set the ISO1 bit */
813 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
814 }
815
816 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
817 break;
818 /* configure TIMER_CH_2 */
819 case TIMER_CH_2:
820 /* reset the CH2EN bit */
821 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
822 /* set the CH2EN bit */
823 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 8U);
824 /* reset the CH2P bit */
825 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
826 /* set the CH2P bit */
827 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U);
828
829 if(TIMER0 == timer_periph){
830 /* reset the CH2NEN bit */
831 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
832 /* set the CH2NEN bit */
833 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U);
834 /* reset the CH2NP bit */
835 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
836 /* set the CH2NP bit */
837 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U);
838 /* reset the ISO2 bit */
839 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
840 /* set the ISO2 bit */
841 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U);
842 /* reset the ISO2N bit */
843 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
844 /* set the ISO2N bit */
845 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U);
846 }
847 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
848 break;
849 /* configure TIMER_CH_3 */
850 case TIMER_CH_3:
851 /* reset the CH3EN bit */
852 TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN);
853 /* set the CH3EN bit */
854 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 12U);
855 /* reset the CH3P bit */
856 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
857 /* set the CH3P bit */
858 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U);
859
860 if(TIMER0 == timer_periph){
861 /* reset the ISO3 bit */
862 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
863 /* set the ISO3 bit */
864 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U);
865 }
866 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
867 break;
868 default:
869 break;
870 }
871 }
TIMER0
#define TIMER0
Definition: gd32f3x0_timer.h:18
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f3x0_timer.h:171
TIMER_CHCTL2_CH1NEN
#define TIMER_CHCTL2_CH1NEN
Definition: gd32f3x0_timer.h:172
timer_oc_parameter_struct::ocnidlestate
uint16_t ocnidlestate
Definition: gd32f3x0_timer.h:268
TIMER_CTL1_ISO1
#define TIMER_CTL1_ISO1
Definition: gd32f3x0_timer.h:72
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CHCTL1_CH3MS
#define TIMER_CHCTL1_CH3MS
Definition: gd32f3x0_timer.h:154
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER16
#define TIMER16
Definition: gd32f3x0_timer.h:27
TIMER_CHCTL2_CH2NEN
#define TIMER_CHCTL2_CH2NEN
Definition: gd32f3x0_timer.h:176
TIMER_CTL1_ISO3
#define TIMER_CTL1_ISO3
Definition: gd32f3x0_timer.h:76
TIMER14
#define TIMER14
Definition: gd32f3x0_timer.h:25
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f3x0_timer.h:31
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
timer_oc_parameter_struct::ocpolarity
uint16_t ocpolarity
Definition: gd32f3x0_timer.h:265
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f3x0_timer.h:173
TIMER_CTL1_ISO1N
#define TIMER_CTL1_ISO1N
Definition: gd32f3x0_timer.h:73
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f3x0_timer.h:169
TIMER_CHCTL1_CH2MS
#define TIMER_CHCTL1_CH2MS
Definition: gd32f3x0_timer.h:149
TIMER_CHCTL2_CH2EN
#define TIMER_CHCTL2_CH2EN
Definition: gd32f3x0_timer.h:174
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f3x0_timer.h:166
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f3x0_timer.h:167
TIMER_CHCTL2_CH3EN
#define TIMER_CHCTL2_CH3EN
Definition: gd32f3x0_timer.h:178
TIMER_CHCTL2_CH2P
#define TIMER_CHCTL2_CH2P
Definition: gd32f3x0_timer.h:175
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
TIMER15
#define TIMER15
Definition: gd32f3x0_timer.h:26
timer_oc_parameter_struct::outputstate
uint32_t outputstate
Definition: gd32f3x0_timer.h:263
timer_oc_parameter_struct::ocidlestate
uint16_t ocidlestate
Definition: gd32f3x0_timer.h:267
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f3x0_timer.h:131
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f3x0_timer.h:170
TIMER_CHCTL2_CH3P
#define TIMER_CHCTL2_CH3P
Definition: gd32f3x0_timer.h:179
TIMER_CTL1_ISO0
#define TIMER_CTL1_ISO0
Definition: gd32f3x0_timer.h:70
TIMER_CHCTL2_CH0NEN
#define TIMER_CHCTL2_CH0NEN
Definition: gd32f3x0_timer.h:168
TIMER_CTL1_ISO2N
#define TIMER_CTL1_ISO2N
Definition: gd32f3x0_timer.h:75
TIMER_CTL1_ISO0N
#define TIMER_CTL1_ISO0N
Definition: gd32f3x0_timer.h:71
TIMER_CHCTL2_CH2NP
#define TIMER_CHCTL2_CH2NP
Definition: gd32f3x0_timer.h:177
timer_oc_parameter_struct::ocnpolarity
uint16_t ocnpolarity
Definition: gd32f3x0_timer.h:266
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f3x0_timer.h:136
TIMER_CTL1_ISO2
#define TIMER_CTL1_ISO2
Definition: gd32f3x0_timer.h:74
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
timer_oc_parameter_struct::outputnstate
uint16_t outputnstate
Definition: gd32f3x0_timer.h:264
void timer_channel_output_fast_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocfast
 | ) |  |

configure TIMER channel output fast function

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] ocfast channel output fast function
  • TIMER_OC_FAST_ENABLE: channel output fast function enable
  • TIMER_OC_FAST_DISABLE: channel output fast function disable
[out] | none
Return values
none

Definition at line 1009 of file gd32f3x0_timer.c.

1010 {
1011 switch(channel){
1012 /* configure TIMER_CH_0 */
1013 case TIMER_CH_0:
1014 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
1015 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
1016 break;
1017 /* configure TIMER_CH_1 */
1018 case TIMER_CH_1:
1019 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN);
1020 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1021 break;
1022 /* configure TIMER_CH_2 */
1023 case TIMER_CH_2:
1024 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN);
1025 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
1026 break;
1027 /* configure TIMER_CH_3 */
1028 case TIMER_CH_3:
1029 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN);
1030 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1031 break;
1032 default:
1033 break;
1034 }
1035 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL1_CH3COMFEN
#define TIMER_CHCTL1_CH3COMFEN
Definition: gd32f3x0_timer.h:155
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL1_CH2COMFEN
#define TIMER_CHCTL1_CH2COMFEN
Definition: gd32f3x0_timer.h:150
TIMER_CHCTL0_CH0COMFEN
#define TIMER_CHCTL0_CH0COMFEN
Definition: gd32f3x0_timer.h:132
TIMER_CHCTL0_CH1COMFEN
#define TIMER_CHCTL0_CH1COMFEN
Definition: gd32f3x0_timer.h:137
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
void timer_channel_output_mode_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocmode
 | ) |  |

configure TIMER channel output compare mode

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] ocmode channel output compare mode
  • TIMER_OC_MODE_TIMING: timing mode
  • TIMER_OC_MODE_ACTIVE: active mode
  • TIMER_OC_MODE_INACTIVE: inactive mode
  • TIMER_OC_MODE_TOGGLE: toggle mode
  • TIMER_OC_MODE_LOW: force low mode
  • TIMER_OC_MODE_HIGH: force high mode
  • TIMER_OC_MODE_PWM0: PWM0 mode
  • TIMER_OC_MODE_PWM1: PWM1 mode
[out] | none
Return values
none

Definition at line 893 of file gd32f3x0_timer.c.

894 {
895 switch(channel){
896 /* configure TIMER_CH_0 */
897 case TIMER_CH_0:
898 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
899 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
900 break;
901 /* configure TIMER_CH_1 */
902 case TIMER_CH_1:
903 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
904 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
905 break;
906 /* configure TIMER_CH_2 */
907 case TIMER_CH_2:
908 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
909 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
910 break;
911 /* configure TIMER_CH_3 */
912 case TIMER_CH_3:
913 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
914 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
915 break;
916 default:
917 break;
918 }
919 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL1_CH3COMCTL
#define TIMER_CHCTL1_CH3COMCTL
Definition: gd32f3x0_timer.h:157
TIMER_CHCTL0_CH1COMCTL
#define TIMER_CHCTL0_CH1COMCTL
Definition: gd32f3x0_timer.h:139
TIMER_CHCTL0_CH0COMCTL
#define TIMER_CHCTL0_CH0COMCTL
Definition: gd32f3x0_timer.h:134
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
TIMER_CHCTL1_CH2COMCTL
#define TIMER_CHCTL1_CH2COMCTL
Definition: gd32f3x0_timer.h:152
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
void timer_channel_output_polarity_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocpolarity
 | ) |  |

configure TIMER channel output polarity

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] ocpolarity channel output polarity
  • TIMER_OC_POLARITY_HIGH: channel output polarity is high
  • TIMER_OC_POLARITY_LOW: channel output polarity is low
[out] | none
Return values
none

Definition at line 1093 of file gd32f3x0_timer.c.

1094 {
1095 switch(channel){
1096 /* configure TIMER_CH_0 */
1097 case TIMER_CH_0:
1098 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
1099 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
1100 break;
1101 /* configure TIMER_CH_1 */
1102 case TIMER_CH_1:
1103 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
1104 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
1105 break;
1106 /* configure TIMER_CH_2 */
1107 case TIMER_CH_2:
1108 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
1109 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
1110 break;
1111 /* configure TIMER_CH_3 */
1112 case TIMER_CH_3:
1113 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
1114 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
1115 break;
1116 default:
1117 break;
1118 }
1119 }
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f3x0_timer.h:171
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f3x0_timer.h:167
TIMER_CHCTL2_CH2P
#define TIMER_CHCTL2_CH2P
Definition: gd32f3x0_timer.h:175
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
TIMER_CHCTL2_CH3P
#define TIMER_CHCTL2_CH3P
Definition: gd32f3x0_timer.h:179
void timer_channel_output_pulse_value_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint32_t | pulse
 | ) |  |

configure TIMER channel output pulse value

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] | pulse | channel output pulse value
[out] | none
Return values
none

Definition at line 933 of file gd32f3x0_timer.c.

934 {
935 switch(channel){
936 case TIMER_CH_0:
937 TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
938 break;
939 case TIMER_CH_1:
940 TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
941 break;
942 case TIMER_CH_2:
943 TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
944 break;
945 case TIMER_CH_3:
946 TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
947 break;
948 default:
949 break;
950 }
951 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CH0CV
#define TIMER_CH0CV(timerx)
Definition: gd32f3x0_timer.h:43
TIMER_CH3CV
#define TIMER_CH3CV(timerx)
Definition: gd32f3x0_timer.h:46
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CH1CV
#define TIMER_CH1CV(timerx)
Definition: gd32f3x0_timer.h:44
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CH2CV
#define TIMER_CH2CV(timerx)
Definition: gd32f3x0_timer.h:45
void timer_channel_output_shadow_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint16_t | ocshadow
 | ) |  |

configure TIMER channel output shadow function

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] ocshadow channel output shadow state
  • TIMER_OC_SHADOW_ENABLE: channel output shadow state enable
  • TIMER_OC_SHADOW_DISABLE: channel output shadow state disable
[out] | none
Return values
none

Definition at line 967 of file gd32f3x0_timer.c.

968 {
969 switch(channel){
970 /* configure TIMER_CH_0 */
971 case TIMER_CH_0:
972 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
973 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
974 break;
975 /* configure TIMER_CH_1 */
976 case TIMER_CH_1:
977 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
978 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
979 break;
980 /* configure TIMER_CH_2 */
981 case TIMER_CH_2:
982 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
983 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
984 break;
985 /* configure TIMER_CH_3 */
986 case TIMER_CH_3:
987 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
988 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
989 break;
990 default:
991 break;
992 }
993 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
TIMER_CHCTL1_CH2COMSEN
#define TIMER_CHCTL1_CH2COMSEN
Definition: gd32f3x0_timer.h:151
TIMER_CHCTL0_CH0COMSEN
#define TIMER_CHCTL0_CH0COMSEN
Definition: gd32f3x0_timer.h:133
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL1_CH3COMSEN
#define TIMER_CHCTL1_CH3COMSEN
Definition: gd32f3x0_timer.h:156
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL0_CH1COMSEN
#define TIMER_CHCTL0_CH1COMSEN
Definition: gd32f3x0_timer.h:138
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
void timer_channel_output_state_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | uint32_t | state
 | ) |  |

configure TIMER channel enable state

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] state TIMER channel enable state
  • TIMER_CCX_ENABLE: channel enable
  • TIMER_CCX_DISABLE: channel disable
[out] | none
Return values
none

Definition at line 1177 of file gd32f3x0_timer.c.

1178 {
1179 switch(channel){
1180 /* configure TIMER_CH_0 */
1181 case TIMER_CH_0:
1182 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1183 TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
1184 break;
1185 /* configure TIMER_CH_1 */
1186 case TIMER_CH_1:
1187 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1188 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
1189 break;
1190 /* configure TIMER_CH_2 */
1191 case TIMER_CH_2:
1192 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1193 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
1194 break;
1195 /* configure TIMER_CH_3 */
1196 case TIMER_CH_3:
1197 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1198 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
1199 break;
1200 default:
1201 break;
1202 }
1203 }
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL2_CH2EN
#define TIMER_CHCTL2_CH2EN
Definition: gd32f3x0_timer.h:174
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f3x0_timer.h:166
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL2_CH3EN
#define TIMER_CHCTL2_CH3EN
Definition: gd32f3x0_timer.h:178
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f3x0_timer.h:170
void timer_channel_remap_config | ( | uint32_t | timer_periph,
 |  | uint32_t | remap
 | ) |  |

configure TIMER channel remap function

Parameters
[in] | timer_periph | TIMERx(x=13)
[in] remap
  • TIMER13_CI0_RMP_GPIO: timer13 channel 0 input is connected to GPIO(TIMER13_CH0)
  • TIMER13_CI0_RMP_RTCCLK: timer13 channel 0 input is connected to the RTCCLK
  • TIMER13_CI0_RMP_HXTAL_DIV32: timer13 channel 0 input is connected to HXTAL/32 clock
  • TIMER13_CI0_RMP_CKOUTSEL: timer13 channel 0 input is connected to CKOUTSEL
[out] | none
Return values
none

Definition at line 1848 of file gd32f3x0_timer.c.

1849 {
1850 TIMER_IRMP(timer_periph) = (uint32_t)remap;
1851 }
TIMER_IRMP
#define TIMER_IRMP(timerx)
Definition: gd32f3x0_timer.h:50
void timer_counter_alignment | ( | uint32_t | timer_periph,
 |  | uint16_t | aligned
 | ) |  |

set TIMER counter alignment mode

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[in] aligned
  • TIMER_COUNTER_EDGE: edge-aligned mode
  • TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
  • TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
  • TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
[out] | none
Return values
none

Definition at line 191 of file gd32f3x0_timer.c.

192 {
193 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM;
194 TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
195 }
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
TIMER_CTL0_CAM
#define TIMER_CTL0_CAM
Definition: gd32f3x0_timer.h:60
void timer_counter_down_direction ( uint32_t timer_periph )

set TIMER counter down direction

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[out] | none
Return values
none

Definition at line 214 of file gd32f3x0_timer.c.

215 {
216 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
217 }
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
TIMER_CTL0_DIR
#define TIMER_CTL0_DIR
Definition: gd32f3x0_timer.h:59
uint32_t timer_counter_read ( uint32_t timer_periph )

read TIMER counter value

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
counter value

Definition at line 280 of file gd32f3x0_timer.c.

281 {
282 uint32_t count_value = 0U;
283 count_value = TIMER_CNT(timer_periph);
284 return (count_value);
285 }
TIMER_CNT
#define TIMER_CNT(timerx)
Definition: gd32f3x0_timer.h:39
void timer_counter_up_direction ( uint32_t timer_periph )

set TIMER counter up direction

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[out] | none
Return values
none

Definition at line 203 of file gd32f3x0_timer.c.

204 {
205 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
206 }
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
TIMER_CTL0_DIR
#define TIMER_CTL0_DIR
Definition: gd32f3x0_timer.h:59
void timer_counter_value_config | ( | uint32_t | timer_periph,
 |  | uint32_t | counter
 | ) |  |

configure TIMER counter register value

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[in] | counter | the counter value
[out] | none
Return values
none

Definition at line 269 of file gd32f3x0_timer.c.

270 {
271 TIMER_CNT(timer_periph) = (uint32_t)counter;
272 }
TIMER_CNT
#define TIMER_CNT(timerx)
Definition: gd32f3x0_timer.h:39
void timer_deinit ( uint32_t timer_periph )

deinit a TIMER

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_timer.c.

21 {
22 switch(timer_periph){
23 case TIMER0:
24 /* reset TIMER0 */
25 rcu_periph_reset_enable(RCU_TIMER0RST);
26 rcu_periph_reset_disable(RCU_TIMER0RST);
27 break;
28 case TIMER1:
29 /* reset TIMER1 */
30 rcu_periph_reset_enable(RCU_TIMER1RST);
31 rcu_periph_reset_disable(RCU_TIMER1RST);
32 break;
33 case TIMER2:
34 /* reset TIMER2 */
35 rcu_periph_reset_enable(RCU_TIMER2RST);
36 rcu_periph_reset_disable(RCU_TIMER2RST);
37 break;
38 #ifdef GD32F350
39 case TIMER5:
40 /* reset TIMER5 */
41 rcu_periph_reset_enable(RCU_TIMER5RST);
42 rcu_periph_reset_disable(RCU_TIMER5RST);
43 break;
44 #endif
45 case TIMER13:
46 /* reset TIMER13 */
47 rcu_periph_reset_enable(RCU_TIMER13RST);
48 rcu_periph_reset_disable(RCU_TIMER13RST);
49 break;
50 case TIMER14:
51 /* reset TIMER14 */
52 rcu_periph_reset_enable(RCU_TIMER14RST);
53 rcu_periph_reset_disable(RCU_TIMER14RST);
54 break;
55 case TIMER15:
56 /* reset TIMER15 */
57 rcu_periph_reset_enable(RCU_TIMER15RST);
58 rcu_periph_reset_disable(RCU_TIMER15RST);
59 break;
60 case TIMER16:
61 /* reset TIMER16 */
62 rcu_periph_reset_enable(RCU_TIMER16RST);
63 rcu_periph_reset_disable(RCU_TIMER16RST);
64 break;
65 default:
66 break;
67 }
68 }
TIMER0
#define TIMER0
Definition: gd32f3x0_timer.h:18
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
TIMER16
#define TIMER16
Definition: gd32f3x0_timer.h:27
TIMER14
#define TIMER14
Definition: gd32f3x0_timer.h:25
TIMER2
#define TIMER2
Definition: gd32f3x0_timer.h:20
RCU_TIMER1RST
Definition: gd32f3x0_rcu.h:344
RCU_TIMER13RST
Definition: gd32f3x0_rcu.h:346
RCU_TIMER14RST
Definition: gd32f3x0_rcu.h:339
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
TIMER15
#define TIMER15
Definition: gd32f3x0_timer.h:26
TIMER1
#define TIMER1
Definition: gd32f3x0_timer.h:19
TIMER13
#define TIMER13
Definition: gd32f3x0_timer.h:24
RCU_TIMER0RST
Definition: gd32f3x0_rcu.h:336
RCU_TIMER15RST
Definition: gd32f3x0_rcu.h:340
RCU_TIMER16RST
Definition: gd32f3x0_rcu.h:341
RCU_TIMER2RST
Definition: gd32f3x0_rcu.h:345
void timer_disable ( uint32_t timer_periph )

disable a TIMER

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
none

Definition at line 131 of file gd32f3x0_timer.c.

132 {
133 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
134 }
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
TIMER_CTL0_CEN
#define TIMER_CTL0_CEN
Definition: gd32f3x0_timer.h:55
void timer_dma_disable | ( | uint32_t | timer_periph,
 |  | uint16_t | dma
 | ) |  |

disable the TIMER DMA

Parameters
[in] | timer_periph | please refer to the following parameters
[in] dma timer DMA source enable
  • TIMER_DMA_UPD: update DMA, TIMERx(x=0..2,14..16),TIMER5 just for GD32F350
  • TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0..2,14..16)
  • TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0..2,14)
  • TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0..2)
  • TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0..2)
  • TIMER_DMA_CMTD: commutation DMA request , TIMERx(x=0,14)
  • TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0..2,14)
[out] | none
Return values
none

Definition at line 528 of file gd32f3x0_timer.c.

529 {
530 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma));
531 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f3x0_timer.h:33
void timer_dma_enable | ( | uint32_t | timer_periph,
 |  | uint16_t | dma
 | ) |  |

enable the TIMER DMA

Parameters
[in] | timer_periph | please refer to the following parameters
[in] dma timer DMA source enable
  • TIMER_DMA_UPD: update DMA, TIMERx(x=0..2,14..16),TIMER5 just for GD32F350
  • TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0..2,14..16)
  • TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0..2,14)
  • TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0..2)
  • TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0..2)
  • TIMER_DMA_CMTD: commutation DMA request, TIMERx(x=0,14)
  • TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0..2,14)
[out] | none
Return values
none

Definition at line 509 of file gd32f3x0_timer.c.

510 {
511 TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
512 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f3x0_timer.h:33
void timer_dma_transfer_config | ( | uint32_t | timer_periph,
 |  | uint32_t | dma_baseaddr,
 |  | uint32_t | dma_lenth
 | ) |  |

configure the TIMER DMA transfer

Parameters
[in] | timer_periph | TIMERx(x=0..2,14..16)
[in] dma_baseaddr
  • TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0..2,14)
  • TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0..2)
  • TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0,14..16)
  • TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0..2,14)
  • TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0..2)
  • TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0..2)
  • TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0,14..16)
  • TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0..2,14..16)
  • TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB, TIMERx(x=0..2,14..16)
[in] dma_lenth
  • TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time
[out] | none
Return values
none

Definition at line 581 of file gd32f3x0_timer.c.

582 {
583 TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
584 TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
585 }
TIMER_DMACFG
#define TIMER_DMACFG(timerx)
Definition: gd32f3x0_timer.h:48
TIMER_DMACFG_DMATC
#define TIMER_DMACFG_DMATC
Definition: gd32f3x0_timer.h:224
TIMER_DMACFG_DMATA
#define TIMER_DMACFG_DMATA
Definition: gd32f3x0_timer.h:223
void timer_enable ( uint32_t timer_periph )

enable a TIMER

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
none

Definition at line 120 of file gd32f3x0_timer.c.

121 {
122 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
123 }
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
TIMER_CTL0_CEN
#define TIMER_CTL0_CEN
Definition: gd32f3x0_timer.h:55
void timer_event_software_generate | ( | uint32_t | timer_periph,
 |  | uint16_t | event
 | ) |  |

software generate events

Parameters
[in] | timer_periph | please refer to the following parameters
[in] event the timer software event generation sources
  • TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..2,13..16), TIMER5 just for GD32F350
  • TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..2,13..16)
  • TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..2,14)
  • TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..2)
  • TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..2)
  • TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,14..16)
  • TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..2,14)
  • TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 602 of file gd32f3x0_timer.c.

603 {
604 TIMER_SWEVG(timer_periph) |= (uint32_t)event;
605 }
TIMER_SWEVG
#define TIMER_SWEVG(timerx)
Definition: gd32f3x0_timer.h:35
void timer_external_clock_mode0_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extprescaler,
 |  | uint32_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER the external clock mode0

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[in] extprescaler
  • TIMER_EXT_TRI_PSC_OFF: no divided
  • TIMER_EXT_TRI_PSC_DIV2: divided by 2
  • TIMER_EXT_TRI_PSC_DIV4: divided by 4
  • TIMER_EXT_TRI_PSC_DIV8: divided by 8
[in] expolarity
  • TIMER_ETP_FALLING: active low or falling edge active
  • TIMER_ETP_RISING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1790 of file gd32f3x0_timer.c.

1792 {
1793 /* configure TIMER external trigger input */
1794 timer_external_trigger_config(timer_periph, extprescaler, expolarity, extfilter);
1795
1796 /* reset the SMC bit,TRGS bit */
1797 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
1798 /* set the SMC bit,TRGS bit */
1799 TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
1800 }
TIMER_SMCFG_TRGS
#define TIMER_SMCFG_TRGS
Definition: gd32f3x0_timer.h:81
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_TRGSEL_ETIFP
#define TIMER_SMCFG_TRGSEL_ETIFP
Definition: gd32f3x0_timer.h:518
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f3x0_timer.h:79
timer_external_trigger_config
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input
Definition: gd32f3x0_timer.c:1649
TIMER_SLAVE_MODE_EXTERNAL0
#define TIMER_SLAVE_MODE_EXTERNAL0
Definition: gd32f3x0_timer.h:540
void timer_external_clock_mode1_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extprescaler,
 |  | uint32_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER the external clock mode1

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[in] extprescaler
  • TIMER_EXT_TRI_PSC_OFF: no divided
  • TIMER_EXT_TRI_PSC_DIV2: divided by 2
  • TIMER_EXT_TRI_PSC_DIV4: divided by 4
  • TIMER_EXT_TRI_PSC_DIV8: divided by 8
[in] expolarity
  • TIMER_ETP_FALLING: active low or falling edge active
  • TIMER_ETP_RISING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1817 of file gd32f3x0_timer.c.

1819 {
1820 /* configure TIMER external trigger input */
1821 timer_external_trigger_config(timer_periph, extprescaler, expolarity, extfilter);
1822
1823 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
1824 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_SMC1
#define TIMER_SMCFG_SMC1
Definition: gd32f3x0_timer.h:85
timer_external_trigger_config
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input
Definition: gd32f3x0_timer.c:1649
void timer_external_clock_mode1_disable ( uint32_t timer_periph )

disable TIMER the external clock mode1

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[out] | none
Return values
none

Definition at line 1832 of file gd32f3x0_timer.c.

1833 {
1834 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
1835 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_SMC1
#define TIMER_SMCFG_SMC1
Definition: gd32f3x0_timer.h:85
void timer_external_trigger_as_external_clock_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extrigger,
 |  | uint16_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER the external trigger as external clock input

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[in] extrigger
  • TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 Edge Detector
  • TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
  • TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
[in] expolarity
  • TIMER_IC_POLARITY_RISING: active low or falling edge active
  • TIMER_IC_POLARITY_FALLING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1729 of file gd32f3x0_timer.c.

1731 {
1732 if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
1733 /* reset the CH1EN bit */
1734 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1735 /* reset the CH1NP bit */
1736 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1737 /* set the CH1NP bit */
1738 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)expolarity << 4U);
1739 /* reset the CH1MS bit */
1740 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1741 /* set the CH1MS bit */
1742 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U);
1743 /* reset the CH1CAPFLT bit */
1744 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1745 /* set the CH1CAPFLT bit */
1746 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U);
1747 /* set the CH1EN bit */
1748 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1749 }else{
1750 /* reset the CH0EN bit */
1751 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1752 /* reset the CH0P and CH0NP bits */
1753 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1754 /* set the CH0P and CH0NP bits */
1755 TIMER_CHCTL2(timer_periph) |= (uint32_t)expolarity;
1756 /* reset the CH0MS bit */
1757 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1758 /* set the CH0MS bit */
1759 TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
1760 /* reset the CH0CAPFLT bit */
1761 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1762 /* reset the CH0CAPFLT bit */
1763 TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter;
1764 /* set the CH0EN bit */
1765 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1766 }
1767 /* select TIMER input trigger source */
1768 timer_input_trigger_source_select(timer_periph,extrigger);
1769 /* reset the SMC bit */
1770 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1771 /* set the SMC bit */
1772 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1773 }
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f3x0_timer.h:171
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f3x0_timer.h:173
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f3x0_timer.h:169
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f3x0_timer.h:166
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f3x0_timer.h:167
TIMER_CHCTL0_CH0CAPFLT
#define TIMER_CHCTL0_CH0CAPFLT
Definition: gd32f3x0_timer.h:143
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f3x0_timer.h:79
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
timer_input_trigger_source_select
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source
Definition: gd32f3x0_timer.c:1565
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f3x0_timer.h:131
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f3x0_timer.h:170
TIMER_CHCTL0_CH1CAPFLT
#define TIMER_CHCTL0_CH1CAPFLT
Definition: gd32f3x0_timer.h:145
TIMER_SMCFG_TRGSEL_CI1FE1
#define TIMER_SMCFG_TRGSEL_CI1FE1
Definition: gd32f3x0_timer.h:517
TIMER_IC_SELECTION_DIRECTTI
#define TIMER_IC_SELECTION_DIRECTTI
Definition: gd32f3x0_timer.h:499
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f3x0_timer.h:136
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
TIMER_SLAVE_MODE_EXTERNAL0
#define TIMER_SLAVE_MODE_EXTERNAL0
Definition: gd32f3x0_timer.h:540
void timer_external_trigger_config | ( | uint32_t | timer_periph,
 |  | uint32_t | extprescaler,
 |  | uint32_t | expolarity,
 |  | uint32_t | extfilter
 | ) |  |

configure TIMER external trigger input

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[in] extprescaler
  • TIMER_EXT_TRI_PSC_OFF: no divided
  • TIMER_EXT_TRI_PSC_DIV2: divided by 2
  • TIMER_EXT_TRI_PSC_DIV4: divided by 4
  • TIMER_EXT_TRI_PSC_DIV8: divided by 8
[in] expolarity
  • TIMER_ETP_FALLING: active low or falling edge active
  • TIMER_ETP_RISING: active high or rising edge active
[in] | extfilter | a value between 0 and 15
[out] | none
Return values
none

Definition at line 1649 of file gd32f3x0_timer.c.

1651 {
1652 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC));
1653 TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | expolarity);
1654 TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U);
1655 }
TIMER_SMCFG_ETPSC
#define TIMER_SMCFG_ETPSC
Definition: gd32f3x0_timer.h:84
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_ETP
#define TIMER_SMCFG_ETP
Definition: gd32f3x0_timer.h:86
TIMER_SMCFG_ETFC
#define TIMER_SMCFG_ETFC
Definition: gd32f3x0_timer.h:83
void timer_flag_clear | ( | uint32_t | timer_periph,
 |  | uint32_t | flag
 | ) |  |

clear TIMER flags

Parameters
[in] | timer_periph | please refer to the following parameters
[in] flag the timer interrupt flags
  • TIMER_FLAG_UP: update flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
  • TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..2,13..16)
  • TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..2,14)
  • TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..2)
  • TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..2)
  • TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16)
  • TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..2,14)
  • TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16)
  • TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..2,13..16)
  • TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..2,14)
  • TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..2)
  • TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..2)
[out] | none
Return values
none

Definition at line 490 of file gd32f3x0_timer.c.

491 {
492 TIMER_INTF(timer_periph) &= (~(uint32_t)flag);
493 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f3x0_timer.h:34
FlagStatus timer_flag_get | ( | uint32_t | timer_periph,
 |  | uint32_t | flag
 | ) |  |

get TIMER flags

Parameters
[in] | timer_periph | please refer to the following parameters
[in] flag the timer interrupt flags
  • TIMER_FLAG_UP: update flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
  • TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..2,13..16)
  • TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..2,14)
  • TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..2)
  • TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..2)
  • TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16)
  • TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..2,14)
  • TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16)
  • TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..2,13..16)
  • TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..2,14)
  • TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..2)
  • TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..2)
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 462 of file gd32f3x0_timer.c.

463 {
464 if(RESET != (TIMER_INTF(timer_periph) & flag)){
465 return SET;
466 }else{
467 return RESET;
468 }
469 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f3x0_timer.h:34
void timer_hall_mode_config | ( | uint32_t | timer_periph,
 |  | uint8_t | hallmode
 | ) |  |

configure TIMER hall sensor mode

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[in] hallmode
  • TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
  • TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
[out] | none
Return values
none

Definition at line 1541 of file gd32f3x0_timer.c.

1542 {
1543 if(TIMER_HALLINTERFACE_ENABLE == hallmode){
1544 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
1545 }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
1546 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
1547 }else{
1548 }
1549 }
TIMER_CTL1_TI0S
#define TIMER_CTL1_TI0S
Definition: gd32f3x0_timer.h:69
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f3x0_timer.h:31
TIMER_HALLINTERFACE_ENABLE
#define TIMER_HALLINTERFACE_ENABLE
Definition: gd32f3x0_timer.h:562
TIMER_HALLINTERFACE_DISABLE
#define TIMER_HALLINTERFACE_DISABLE
Definition: gd32f3x0_timer.h:563
void timer_init | ( | uint32_t | timer_periph,
 |  | timer_parameter_struct * | initpara
 | ) |  |

initialize TIMER counter

Parameters
[in] | periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[in] | timer_initpara | init parameter struct prescaler: prescaler value of the counter clock,0~65535 alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN period: counter auto reload value,(TIMER1 32 bit) clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 repetitioncounter: counter repetition value,0~255
[out] | none
Return values
none

Definition at line 83 of file gd32f3x0_timer.c.

84 {
85 /* configure the counter prescaler value */
86 TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
87
88 /* configure the counter direction and aligned mode */
89 if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph)){
90 TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM);
91 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode;
92 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection;
93 }
94
95 /* configure the autoreload value */
96 TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
97
98 if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER13 == timer_periph)
99 || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){
100 /* reset the CKDIV bit */
101 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV;
102 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision;
103 }
104
105 if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){
106 /* configure the repetition counter value */
107 TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
108 }
109
110 /* generate an update event */
111 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
112 }
TIMER0
#define TIMER0
Definition: gd32f3x0_timer.h:18
TIMER16
#define TIMER16
Definition: gd32f3x0_timer.h:27
TIMER_CAR
#define TIMER_CAR(timerx)
Definition: gd32f3x0_timer.h:41
TIMER_SWEVG_UPG
#define TIMER_SWEVG_UPG
Definition: gd32f3x0_timer.h:120
TIMER14
#define TIMER14
Definition: gd32f3x0_timer.h:25
TIMER_CTL0_CKDIV
#define TIMER_CTL0_CKDIV
Definition: gd32f3x0_timer.h:62
TIMER2
#define TIMER2
Definition: gd32f3x0_timer.h:20
TIMER_PSC
#define TIMER_PSC(timerx)
Definition: gd32f3x0_timer.h:40
TIMER_CREP
#define TIMER_CREP(timerx)
Definition: gd32f3x0_timer.h:42
timer_parameter_struct::clockdivision
uint16_t clockdivision
Definition: gd32f3x0_timer.h:244
TIMER15
#define TIMER15
Definition: gd32f3x0_timer.h:26
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
TIMER1
#define TIMER1
Definition: gd32f3x0_timer.h:19
TIMER_SWEVG
#define TIMER_SWEVG(timerx)
Definition: gd32f3x0_timer.h:35
TIMER13
#define TIMER13
Definition: gd32f3x0_timer.h:24
TIMER_CTL0_CAM
#define TIMER_CTL0_CAM
Definition: gd32f3x0_timer.h:60
timer_parameter_struct::repetitioncounter
uint8_t repetitioncounter
Definition: gd32f3x0_timer.h:245
TIMER_CTL0_DIR
#define TIMER_CTL0_DIR
Definition: gd32f3x0_timer.h:59
timer_parameter_struct::prescaler
uint16_t prescaler
Definition: gd32f3x0_timer.h:240
timer_parameter_struct::period
uint32_t period
Definition: gd32f3x0_timer.h:243
timer_parameter_struct::alignedmode
uint16_t alignedmode
Definition: gd32f3x0_timer.h:241
timer_parameter_struct::counterdirection
uint16_t counterdirection
Definition: gd32f3x0_timer.h:242
void timer_input_capture_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | timer_ic_parameter_struct * | icpara
 | ) |  |

configure TIMER input capture parameter

Parameters
[in] | timer_periph | please refer to the following parameters
[in] channel
  • TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16))
  • TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14))
  • TIMER_CH_2: TIMER channel2(TIMERx(x=0..2))
  • TIMER_CH_3: TIMER channel3(TIMERx(x=0..2))
[in] | icpara | TIMER channel intput parameter struct icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 icfilter: 0~15
[out] | none
Return values
none

Definition at line 1257 of file gd32f3x0_timer.c.

1258 {
1259 switch(channel){
1260 /* configure TIMER_CH_0 */
1261 case TIMER_CH_0:
1262 /* reset the CH0EN bit */
1263 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1264
1265 /* reset the CH0P and CH0NP bits */
1266 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1267 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
1268 /* reset the CH0MS bit */
1269 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1270 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
1271 /* reset the CH0CAPFLT bit */
1272 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1273 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1274
1275 /* set the CH0EN bit */
1276 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1277 break;
1278
1279 /* configure TIMER_CH_1 */
1280 case TIMER_CH_1:
1281 /* reset the CH1EN bit */
1282 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1283
1284 /* reset the CH1P and CH1NP bits */
1285 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1286 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U);
1287 /* reset the CH1MS bit */
1288 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1289 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1290 /* reset the CH1CAPFLT bit */
1291 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1292 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1293
1294 /* set the CH1EN bit */
1295 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1296 break;
1297 /* configure TIMER_CH_2 */
1298 case TIMER_CH_2:
1299 /* reset the CH2EN bit */
1300 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1301
1302 /* reset the CH2P and CH2NP bits */
1303 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP));
1304 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U);
1305
1306 /* reset the CH2MS bit */
1307 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
1308 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection));
1309
1310 /* reset the CH2CAPFLT bit */
1311 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
1312 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1313
1314 /* set the CH2EN bit */
1315 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
1316 break;
1317 /* configure TIMER_CH_3 */
1318 case TIMER_CH_3:
1319 /* reset the CH3EN bit */
1320 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1321
1322 /* reset the CH3P and CH3NP bits */
1323 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P|TIMER_CHCTL2_CH3NP));
1324 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U);
1325
1326 /* reset the CH3MS bit */
1327 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
1328 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1329
1330 /* reset the CH3CAPFLT bit */
1331 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
1332 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1333
1334 /* set the CH3EN bit */
1335 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
1336 break;
1337 default:
1338 break;
1339 }
1340 /* configure TIMER channel input capture prescaler value */
1341 timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler));
1342 }
timer_channel_input_capture_prescaler_config
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value
Definition: gd32f3x0_timer.c:1360
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f3x0_timer.h:171
timer_ic_parameter_struct::icselection
uint16_t icselection
Definition: gd32f3x0_timer.h:275
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CHCTL1_CH3MS
#define TIMER_CHCTL1_CH3MS
Definition: gd32f3x0_timer.h:154
TIMER_CH_2
#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
TIMER_CHCTL2_CH3NP
#define TIMER_CHCTL2_CH3NP
Definition: gd32f3x0_timer.h:180
TIMER_CHCTL1_CH3CAPFLT
#define TIMER_CHCTL1_CH3CAPFLT
Definition: gd32f3x0_timer.h:163
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f3x0_timer.h:173
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f3x0_timer.h:169
TIMER_CHCTL1_CH2MS
#define TIMER_CHCTL1_CH2MS
Definition: gd32f3x0_timer.h:149
TIMER_CHCTL2_CH2EN
#define TIMER_CHCTL2_CH2EN
Definition: gd32f3x0_timer.h:174
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f3x0_timer.h:166
timer_ic_parameter_struct::icprescaler
uint16_t icprescaler
Definition: gd32f3x0_timer.h:276
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f3x0_timer.h:167
TIMER_CHCTL0_CH0CAPFLT
#define TIMER_CHCTL0_CH0CAPFLT
Definition: gd32f3x0_timer.h:143
TIMER_CHCTL2_CH3EN
#define TIMER_CHCTL2_CH3EN
Definition: gd32f3x0_timer.h:178
TIMER_CHCTL2_CH2P
#define TIMER_CHCTL2_CH2P
Definition: gd32f3x0_timer.h:175
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
timer_ic_parameter_struct::icpolarity
uint16_t icpolarity
Definition: gd32f3x0_timer.h:274
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f3x0_timer.h:131
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f3x0_timer.h:170
TIMER_CHCTL2_CH3P
#define TIMER_CHCTL2_CH3P
Definition: gd32f3x0_timer.h:179
TIMER_CHCTL0_CH1CAPFLT
#define TIMER_CHCTL0_CH1CAPFLT
Definition: gd32f3x0_timer.h:145
TIMER_CHCTL2_CH2NP
#define TIMER_CHCTL2_CH2NP
Definition: gd32f3x0_timer.h:177
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f3x0_timer.h:136
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
TIMER_CHCTL1_CH2CAPFLT
#define TIMER_CHCTL1_CH2CAPFLT
Definition: gd32f3x0_timer.h:161
timer_ic_parameter_struct::icfilter
uint16_t icfilter
Definition: gd32f3x0_timer.h:277
void timer_input_pwm_capture_config | ( | uint32_t | timer_periph,
 |  | uint16_t | channel,
 |  | timer_ic_parameter_struct * | icpwm
 | ) |  |

configure TIMER input pwm capture function

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[in] channel
  • TIMER_CH_0: TIMER channel0
  • TIMER_CH_1: TIMER channel1
[in] | icpwm:TIMER | channel intput pwm parameter struct icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 icfilter: 0~15
[out] | none
Return values
none

Definition at line 1436 of file gd32f3x0_timer.c.

1437 {
1438 uint16_t icpolarity = 0x0U;
1439 uint16_t icselection = 0x0U;
1440
1441 if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
1442 icpolarity = TIMER_IC_POLARITY_FALLING;
1443 }else{
1444 icpolarity = TIMER_IC_POLARITY_RISING;
1445 }
1446
1447 if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
1448 icselection = TIMER_IC_SELECTION_INDIRECTTI;
1449 }else{
1450 icselection = TIMER_IC_SELECTION_DIRECTTI;
1451 }
1452
1453 if(TIMER_CH_0 == channel){
1454 /* reset the CH0EN bit */
1455 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1456 /* reset the CH0P and CH0NP bits */
1457 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1458 /* set the CH0P and CH0NP bits */
1459 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
1460 /* reset the CH0MS bit */
1461 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1462 /* set the CH0MS bit */
1463 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
1464 /* reset the CH0CAPFLT bit */
1465 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1466 /* set the CH0CAPFLT bit */
1467 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1468 /* set the CH0EN bit */
1469 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1470 /* configure TIMER channel input capture prescaler value */
1471 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler));
1472
1473 /* reset the CH1EN bit */
1474 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1475 /* reset the CH1P and CH1NP bits */
1476 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1477 /* set the CH1P and CH1NP bits */
1478 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U);
1479 /* reset the CH1MS bit */
1480 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1481 /* set the CH1MS bit */
1482 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U);
1483 /* reset the CH1CAPFLT bit */
1484 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1485 /* set the CH1CAPFLT bit */
1486 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1487 /* set the CH1EN bit */
1488 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1489 /* configure TIMER channel input capture prescaler value */
1490 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler));
1491 }else{
1492 /* reset the CH1EN bit */
1493 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1494 /* reset the CH1P and CH1NP bits */
1495 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1496 /* set the CH1P and CH1NP bits */
1497 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U);
1498 /* reset the CH1MS bit */
1499 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1500 /* set the CH1MS bit */
1501 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U);
1502 /* reset the CH1CAPFLT bit */
1503 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1504 /* set the CH1CAPFLT bit */
1505 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1506 /* set the CH1EN bit */
1507 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1508 /* configure TIMER channel input capture prescaler value */
1509 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
1510
1511 /* reset the CH0EN bit */
1512 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1513 /* reset the CH0P and CH0NP bits */
1514 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1515 /* set the CH0P and CH0NP bits */
1516 TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
1517 /* reset the CH0MS bit */
1518 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1519 /* set the CH0MS bit */
1520 TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
1521 /* reset the CH0CAPFLT bit */
1522 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1523 /* set the CH0CAPFLT bit */
1524 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1525 /* set the CH0EN bit */
1526 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1527 /* configure TIMER channel input capture prescaler value */
1528 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
1529 }
1530 }
TIMER_IC_POLARITY_RISING
#define TIMER_IC_POLARITY_RISING
Definition: gd32f3x0_timer.h:494
timer_channel_input_capture_prescaler_config
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value
Definition: gd32f3x0_timer.c:1360
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f3x0_timer.h:171
timer_ic_parameter_struct::icselection
uint16_t icselection
Definition: gd32f3x0_timer.h:275
TIMER_CH_1
#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f3x0_timer.h:173
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f3x0_timer.h:169
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f3x0_timer.h:166
timer_ic_parameter_struct::icprescaler
uint16_t icprescaler
Definition: gd32f3x0_timer.h:276
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f3x0_timer.h:167
TIMER_CHCTL0_CH0CAPFLT
#define TIMER_CHCTL0_CH0CAPFLT
Definition: gd32f3x0_timer.h:143
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
TIMER_IC_SELECTION_INDIRECTTI
#define TIMER_IC_SELECTION_INDIRECTTI
Definition: gd32f3x0_timer.h:500
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
timer_ic_parameter_struct::icpolarity
uint16_t icpolarity
Definition: gd32f3x0_timer.h:274
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f3x0_timer.h:131
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f3x0_timer.h:170
TIMER_CHCTL0_CH1CAPFLT
#define TIMER_CHCTL0_CH1CAPFLT
Definition: gd32f3x0_timer.h:145
TIMER_IC_SELECTION_DIRECTTI
#define TIMER_IC_SELECTION_DIRECTTI
Definition: gd32f3x0_timer.h:499
TIMER_IC_POLARITY_FALLING
#define TIMER_IC_POLARITY_FALLING
Definition: gd32f3x0_timer.h:495
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f3x0_timer.h:136
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
timer_ic_parameter_struct::icfilter
uint16_t icfilter
Definition: gd32f3x0_timer.h:277
void timer_input_trigger_source_select | ( | uint32_t | timer_periph,
 |  | uint32_t | intrigger
 | ) |  |

select TIMER input trigger source

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[in] intrigger
  • TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..2,14))
  • TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..2,14))
  • TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..2))
  • TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 Edge Detector(TIMERx(x=0..2,14))
  • TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..2,14))
  • TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..2,14))
  • TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0..2))
[out] | none
Return values
none

Definition at line 1565 of file gd32f3x0_timer.c.

1566 {
1567 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
1568 TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
1569 }
TIMER_SMCFG_TRGS
#define TIMER_SMCFG_TRGS
Definition: gd32f3x0_timer.h:81
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
void timer_internal_clock_config ( uint32_t timer_periph )

configure TIMER internal clock mode

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[out] | none
Return values
none

Definition at line 1693 of file gd32f3x0_timer.c.

1694 {
1695 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1696 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f3x0_timer.h:79
void timer_internal_trigger_as_external_clock_config | ( | uint32_t | timer_periph,
 |  | uint32_t | intrigger
 | ) |  |

configure TIMER the internal trigger as external clock input

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[in] intrigger
  • TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..2,14))
  • TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..2,14))
  • TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..2))
[out] | none
Return values
none

Definition at line 1708 of file gd32f3x0_timer.c.

1709 {
1710 timer_input_trigger_source_select(timer_periph, intrigger);
1711 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1712 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1713 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f3x0_timer.h:79
timer_input_trigger_source_select
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source
Definition: gd32f3x0_timer.c:1565
TIMER_SLAVE_MODE_EXTERNAL0
#define TIMER_SLAVE_MODE_EXTERNAL0
Definition: gd32f3x0_timer.h:540
void timer_interrupt_disable | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

disable the TIMER interrupt

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt timer interrupt source enable
  • TIMER_INT_UP: update interrupt enable, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
  • TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..2,13..16)
  • TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..2,14)
  • TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..2)
  • TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..2)
  • TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,14..16)
  • TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..2,14)
  • TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 392 of file gd32f3x0_timer.c.

393 {
394 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
395 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f3x0_timer.h:33
void timer_interrupt_enable | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

enable the TIMER interrupt

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt timer interrupt enable source
  • TIMER_INT_UP: update interrupt enable, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
  • TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..2,13..16)
  • TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..2,14)
  • TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..2)
  • TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..2)
  • TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,14..16)
  • TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..2,14)
  • TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 372 of file gd32f3x0_timer.c.

373 {
374 TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
375 }
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f3x0_timer.h:33
void timer_interrupt_flag_clear | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

clear TIMER interrupt flag

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt the timer interrupt bits
  • TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
  • TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..2,13..16)
  • TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..2,14)
  • TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..2)
  • TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..2)
  • TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,14..16)
  • TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0..2,14)
  • TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0,14..16)
[out] | none
Return values
none

Definition at line 438 of file gd32f3x0_timer.c.

439 {
440 TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt);
441 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f3x0_timer.h:34
FlagStatus timer_interrupt_flag_get | ( | uint32_t | timer_periph,
 |  | uint32_t | interrupt
 | ) |  |

get timer interrupt flag

Parameters
[in] | timer_periph | please refer to the following parameters
[in] interrupt the timer interrupt bits
  • TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
  • TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..2,13..16)
  • TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..2,14)
  • TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..2)
  • TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..2)
  • TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,14..16)
  • TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0..2,14)
  • TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,14..16)
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 412 of file gd32f3x0_timer.c.

413 {
414 uint32_t val;
415 val = (TIMER_DMAINTEN(timer_periph) & interrupt);
416 if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){
417 return SET;
418 }else{
419 return RESET;
420 }
421 }
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f3x0_timer.h:34
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f3x0_timer.h:33
void timer_master_output_trigger_source_select | ( | uint32_t | timer_periph,
 |  | uint32_t | outrigger
 | ) |  |

select TIMER master mode output trigger source

Parameters
[in] | timer_periph | TIMERx(x=0..2,14),TIMER5 just for GD32F350
[in] outrigger
  • TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350)
  • TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350)
  • TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350)
  • TIMER_TRI_OUT_SRC_CC0: a capture or a compare match occurred in channal0 as trigger output TRGO
  • TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..2,14))
  • TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..2,14))
  • TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..2,14))
  • TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..2,14))
[out] | none
Return values
none

Definition at line 1586 of file gd32f3x0_timer.c.

1587 {
1588 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
1589 TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
1590 }
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f3x0_timer.h:31
TIMER_CTL1_MMC
#define TIMER_CTL1_MMC
Definition: gd32f3x0_timer.h:68
void timer_master_slave_mode_config | ( | uint32_t | timer_periph,
 |  | uint8_t | masterslave
 | ) |  |

configure TIMER master slave mode

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[in] masterslave
  • TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
  • TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
[out] | none
Return values
none

Definition at line 1624 of file gd32f3x0_timer.c.

1625 {
1626 if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
1627 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
1628 }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
1629 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
1630 }else{
1631 }
1632 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_MASTER_SLAVE_MODE_ENABLE
#define TIMER_MASTER_SLAVE_MODE_ENABLE
Definition: gd32f3x0_timer.h:547
TIMER_MASTER_SLAVE_MODE_DISABLE
#define TIMER_MASTER_SLAVE_MODE_DISABLE
Definition: gd32f3x0_timer.h:548
TIMER_SMCFG_MSM
#define TIMER_SMCFG_MSM
Definition: gd32f3x0_timer.h:82
void timer_ocpre_clear_source_config | ( | uint32_t | timer_periph,
 |  | uint8_t | ocpreclear
 | ) |  |

configure TIMER OCPRE clear source selection

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[in] ocpreclear
  • TIMER_OCPRE_CLEAR_SOURCE_CLR: OCPRE_CLR_INT is connected to the OCPRE_CLR input
  • TIMER_OCPRE_CLEAR_SOURCE_ETIF: OCPRE_CLR_INT is connected to ETIF
[out] | none
Return values
none

Definition at line 347 of file gd32f3x0_timer.c.

348 {
349 if(TIMER_OCPRE_CLEAR_SOURCE_ETIF == ocpreclear){
350 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_OCRC;
351 }else if(TIMER_OCPRE_CLEAR_SOURCE_CLR == ocpreclear){
352 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_OCRC;
353 }else{
354 }
355 }
TIMER_SMCFG_OCRC
#define TIMER_SMCFG_OCRC
Definition: gd32f3x0_timer.h:80
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_OCPRE_CLEAR_SOURCE_ETIF
#define TIMER_OCPRE_CLEAR_SOURCE_ETIF
Definition: gd32f3x0_timer.h:544
TIMER_OCPRE_CLEAR_SOURCE_CLR
#define TIMER_OCPRE_CLEAR_SOURCE_CLR
Definition: gd32f3x0_timer.h:543
void timer_output_value_selection_config | ( | uint32_t | timer_periph,
 |  | uint16_t | outsel
 | ) |  |

configure TIMER output value selection

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[in] outsel
  • TIMER_OUTSEL_DISABLE: no effect
  • TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled
[out] | none
Return values
none

Definition at line 1881 of file gd32f3x0_timer.c.

1882 {
1883 if(TIMER_OUTSEL_ENABLE == outsel){
1884 TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL;
1885 }else if(TIMER_OUTSEL_DISABLE == outsel){
1886 TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL;
1887 }else{
1888 }
1889 }
TIMER_OUTSEL_ENABLE
#define TIMER_OUTSEL_ENABLE
Definition: gd32f3x0_timer.h:571
TIMER_CFG
#define TIMER_CFG(timerx)
Definition: gd32f3x0_timer.h:51
TIMER_OUTSEL_DISABLE
#define TIMER_OUTSEL_DISABLE
Definition: gd32f3x0_timer.h:570
TIMER_CFG_OUTSEL
#define TIMER_CFG_OUTSEL
Definition: gd32f3x0_timer.h:233
void timer_prescaler_config | ( | uint32_t | timer_periph,
 |  | uint16_t | prescaler,
 |  | uint8_t | pscreload
 | ) |  |

configure TIMER prescaler

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[in] | prescaler | prescaler value
[in] pscreload prescaler reload mode
  • TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
  • TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
[out] | none
Return values
none

Definition at line 229 of file gd32f3x0_timer.c.

230 {
231 TIMER_PSC(timer_periph) = (uint32_t)prescaler;
232
233 if(TIMER_PSC_RELOAD_NOW == pscreload){
234 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
235 }
236 }
TIMER_SWEVG_UPG
#define TIMER_SWEVG_UPG
Definition: gd32f3x0_timer.h:120
TIMER_PSC_RELOAD_NOW
#define TIMER_PSC_RELOAD_NOW
Definition: gd32f3x0_timer.h:389
TIMER_PSC
#define TIMER_PSC(timerx)
Definition: gd32f3x0_timer.h:40
TIMER_SWEVG
#define TIMER_SWEVG(timerx)
Definition: gd32f3x0_timer.h:35
uint16_t timer_prescaler_read ( uint32_t timer_periph )

read TIMER prescaler value

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
prescaler register value

Definition at line 293 of file gd32f3x0_timer.c.

294 {
295 uint16_t prescaler_value = 0U;
296 prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
297 return (prescaler_value);
298 }
TIMER_PSC
#define TIMER_PSC(timerx)
Definition: gd32f3x0_timer.h:40
void timer_primary_output_config | ( | uint32_t | timer_periph,
 |  | ControlStatus | newvalue
 | ) |  |

configure TIMER primary output function

Parameters
[in] | timer_periph | TIMERx(x=0,14..16)
[in] | newvalue | ENABLE or DISABLE
[out] | none
Return values
none

Definition at line 683 of file gd32f3x0_timer.c.

684 {
685 if(ENABLE == newvalue){
686 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
687 }else{
688 TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
689 }
690 }
TIMER_CCHP_POEN
#define TIMER_CCHP_POEN
Definition: gd32f3x0_timer.h:220
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f3x0_timer.h:47
void timer_quadrature_decoder_mode_config | ( | uint32_t | timer_periph,
 |  | uint32_t | decomode,
 |  | uint16_t | ic0polarity,
 |  | uint16_t | ic1polarity
 | ) |  |

configure TIMER quadrature decoder mode

Parameters
[in] | timer_periph | TIMERx(x=0..2)
[in] decomode
  • TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
  • TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
  • TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
[in] ic0polarity
  • TIMER_IC_POLARITY_RISING: capture rising edge
  • TIMER_IC_POLARITY_FALLING: capture falling edge
[in] ic1polarity
  • TIMER_IC_POLARITY_RISING: capture rising edge
  • TIMER_IC_POLARITY_FALLING: capture falling edge
[out] | none
Return values
none

Definition at line 1673 of file gd32f3x0_timer.c.

1675 {
1676 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1677 TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
1678
1679 TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS)));
1680 TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U));
1681
1682 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1683 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1684 TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity << 4U));
1685 }
TIMER_CHCTL2_CH1P
#define TIMER_CHCTL2_CH1P
Definition: gd32f3x0_timer.h:171
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f3x0_timer.h:173
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f3x0_timer.h:169
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f3x0_timer.h:167
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f3x0_timer.h:79
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f3x0_timer.h:131
TIMER_IC_SELECTION_DIRECTTI
#define TIMER_IC_SELECTION_DIRECTTI
Definition: gd32f3x0_timer.h:499
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f3x0_timer.h:136
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
void timer_repetition_value_config | ( | uint32_t | timer_periph,
 |  | uint16_t | repetition
 | ) |  |

configure TIMER repetition register value

Parameters
[in] | timer_periph | TIMERx(x=0,15,16)
[in] | repetition | the counter repetition value,0~255
[out] | none
Return values
none

Definition at line 245 of file gd32f3x0_timer.c.

246 {
247 TIMER_CREP(timer_periph) = (uint32_t)repetition;
248 }
TIMER_CREP
#define TIMER_CREP(timerx)
Definition: gd32f3x0_timer.h:42
void timer_single_pulse_mode_config | ( | uint32_t | timer_periph,
 |  | uint8_t | spmode
 | ) |  |

configure TIMER single pulse mode

Parameters
[in] | timer_periph | TIMERx(x=0..2,14..16),TIMER5 just for GD32F350
[in] spmode
  • TIMER_SP_MODE_SINGLE: single pulse mode
  • TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
[out] | none
Return values
none

Definition at line 309 of file gd32f3x0_timer.c.

310 {
311 if(TIMER_SP_MODE_SINGLE == spmode){
312 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
313 }else if(TIMER_SP_MODE_REPETITIVE == spmode){
314 TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
315 }else{
316 }
317 }
TIMER_SP_MODE_REPETITIVE
#define TIMER_SP_MODE_REPETITIVE
Definition: gd32f3x0_timer.h:404
TIMER_SP_MODE_SINGLE
#define TIMER_SP_MODE_SINGLE
Definition: gd32f3x0_timer.h:403
TIMER_CTL0_SPM
#define TIMER_CTL0_SPM
Definition: gd32f3x0_timer.h:58
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
void timer_slave_mode_select | ( | uint32_t | timer_periph,
 |  | uint32_t | slavemode
 | ) |  |

select TIMER slave mode

Parameters
[in] | timer_periph | TIMERx(x=0..2,14)
[in] slavemode
  • TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..2,14))
  • TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..2))
  • TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..2))
  • TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..2))
  • TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..2,14))
  • TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..2,14))
  • TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..2,14))
  • TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0(TIMERx(x=0..2,14))
[out] | none
Return values
none

Definition at line 1608 of file gd32f3x0_timer.c.

1609 {
1610 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1611
1612 TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
1613 }
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f3x0_timer.h:79
void timer_update_event_disable ( uint32_t timer_periph )

disable the update event

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
none

Definition at line 175 of file gd32f3x0_timer.c.

176 {
177 TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
178 }
TIMER_CTL0_UPDIS
#define TIMER_CTL0_UPDIS
Definition: gd32f3x0_timer.h:56
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
void timer_update_event_enable ( uint32_t timer_periph )

enable the update event

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[out] | none
Return values
none

Definition at line 164 of file gd32f3x0_timer.c.

165 {
166 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
167 }
TIMER_CTL0_UPDIS
#define TIMER_CTL0_UPDIS
Definition: gd32f3x0_timer.h:56
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
void timer_update_source_config | ( | uint32_t | timer_periph,
 |  | uint8_t | update
 | ) |  |

configure TIMER update source

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16),TIMER5 just for GD32F350
[in] update
  • TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger
  • TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
[out] | none
Return values
none

Definition at line 328 of file gd32f3x0_timer.c.

329 {
330 if(TIMER_UPDATE_SRC_REGULAR == update){
331 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
332 }else if(TIMER_UPDATE_SRC_GLOBAL == update){
333 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
334 }else{
335 }
336 }
TIMER_UPDATE_SRC_REGULAR
#define TIMER_UPDATE_SRC_REGULAR
Definition: gd32f3x0_timer.h:407
TIMER_CTL0_UPS
#define TIMER_CTL0_UPS
Definition: gd32f3x0_timer.h:57
TIMER_UPDATE_SRC_GLOBAL
#define TIMER_UPDATE_SRC_GLOBAL
Definition: gd32f3x0_timer.h:408
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
void timer_write_cc_register_config | ( | uint32_t | timer_periph,
 |  | uint16_t | ccsel
 | ) |  |

configure TIMER write CHxVAL register selection

Parameters
[in] | timer_periph | TIMERx(x=0..2,13..16)
[in] ccsel
  • TIMER_CCSEL_DISABLE: no effect
  • TIMER_CCSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored
[out] | none
Return values
none

Definition at line 1862 of file gd32f3x0_timer.c.

1863 {
1864 if(TIMER_CCSEL_ENABLE == ccsel){
1865 TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL;
1866 }else if(TIMER_CCSEL_DISABLE == ccsel){
1867 TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL;
1868 }else{
1869 }
1870 }
TIMER_CFG_CHVSEL
#define TIMER_CFG_CHVSEL
Definition: gd32f3x0_timer.h:234
TIMER_CCSEL_ENABLE
#define TIMER_CCSEL_ENABLE
Definition: gd32f3x0_timer.h:567
TIMER_CFG
#define TIMER_CFG(timerx)
Definition: gd32f3x0_timer.h:51
TIMER_CCSEL_DISABLE
#define TIMER_CCSEL_DISABLE
Definition: gd32f3x0_timer.h:566
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_tsi.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_tsi.c File Reference

tsi driver More...

#include "gd32f3x0_tsi.h"

Go to the source code of this file.

Functions

void | tsi_deinit (void)
reset TSI peripheral More...
void | tsi_init (uint32_t prescaler, uint32_t charge_duration, uint32_t transfer_duration, uint32_t max_number)
initialize TSI plus prescaler,charge plus,transfer plus,max cycle number More...
void | tsi_sample_pin_enable (uint32_t sample)
enable sample pin More...
void | tsi_sample_pin_disable (uint32_t sample)
disable sample pin More...
void | tsi_channel_pin_enable (uint32_t channel)
enable channel pin More...
void | tsi_channel_pin_disable (uint32_t channel)
disable channel pin More...
void | tsi_plus_config (uint32_t prescaler, uint32_t charge_duration, uint32_t transfer_duration)
configure charge plus and transfer plus More...
void | tsi_sofeware_mode_config (void)
configure TSI triggering by software More...
void | tsi_hardware_mode_config (uint8_t trigger_edge)
configure TSI triggering by hardware More...
void | tsi_pin_mode_config (uint8_t pin_mode)
configure TSI pin mode when charge-transfer sequence is IDLE More...
void | tsi_max_number_config (uint32_t max_number)
configure the max cycle number of a charge-transfer sequence More...
void | tsi_software_start (void)
start a charge-transfer sequence when TSI is in software trigger mode More...
void | tsi_software_stop (void)
stop a charge-transfer sequence when TSI is in software trigger mode More...
void | tsi_enable (void)
enable TSI module More...
void | tsi_disable (void)
disable TSI module More...
void | tsi_extend_charge_config (ControlStatus extend, uint8_t prescaler, uint32_t max_duration)
configure extend charge state More...
void | tsi_interrupt_enable (uint32_t source)
enable TSI interrupt More...
void | tsi_interrupt_disable (uint32_t source)
disable TSI interrupt More...
void | tsi_interrupt_flag_clear (uint32_t flag)
clear TSI interrupt flag More...
FlagStatus | tsi_interrupt_flag_get (uint32_t flag)
get TSI interrupt flag More...
void | tsi_flag_clear (uint32_t flag)
clear flag More...
FlagStatus | tsi_flag_get (uint32_t flag)
get flag More...
void | tsi_hysteresis_on (uint32_t group_pin)
switch on hysteresis pin More...
void | tsi_hysteresis_off (uint32_t group_pin)
switch off hysteresis pin More...
void | tsi_analog_on (uint32_t group_pin)
switch on analog pin More...
void | tsi_analog_off (uint32_t group_pin)
switch off analog pin More...
void | tsi_group_enable (uint32_t group)
enbale group More...
void | tsi_group_disable (uint32_t group)
disbale group More...
FlagStatus | tsi_group_status_get (uint32_t group)
get group complete status More...
uint16_t | tsi_group0_cycle_get (void)
get the cycle number for group0 as soon as a charge-transfer sequence completes More...
uint16_t | tsi_group1_cycle_get (void)
get the cycle number for group1 as soon as a charge-transfer sequence completes More...
uint16_t | tsi_group2_cycle_get (void)
get the cycle number for group2 as soon as a charge-transfer sequence completes More...
uint16_t | tsi_group3_cycle_get (void)
get the cycle number for group3 as soon as a charge-transfer sequence completes More...
uint16_t | tsi_group4_cycle_get (void)
get the cycle number for group4 as soon as a charge-transfer sequence completes More...
uint16_t | tsi_group5_cycle_get (void)
get the cycle number for group5 as soon as a charge-transfer sequence completes More...

Detailed Description

tsi driver

Definition in file gd32f3x0_tsi.c.

Function Documentation

void tsi_analog_off ( uint32_t group_pin )

switch off analog pin

Parameters
[in] group_pin select pin which will be switched off analog
  • TSI_ASW_GxPy(x=0..5,y=0..3):pin y of group x switch off analog
[out] none
Return values
none

Definition at line 541 of file gd32f3x0_tsi.c.

542 {
543 TSI_ASW &= ~group_pin;
544 }
TSI_ASW
#define TSI_ASW
Definition: gd32f3x0_tsi.h:26
void tsi_analog_on ( uint32_t group_pin )

switch on analog pin

Parameters
[in] group_pin select pin which will be switched on analog
  • TSI_ASW_GxPy(x=0..5,y=0..3):pin y of group x switch on analog
[out] none
Return values
none

Definition at line 529 of file gd32f3x0_tsi.c.

530 {
531 TSI_ASW |= group_pin;
532 }
TSI_ASW
#define TSI_ASW
Definition: gd32f3x0_tsi.h:26
void tsi_channel_pin_disable ( uint32_t channel )

disable channel pin

Parameters
[in] channel channel pin
  • TSI_CHCFG_GxPy( x=0..5,y=0..3): pin y of group x
[out] none
Return values
none

Definition at line 140 of file gd32f3x0_tsi.c.

141 {
142 TSI_CHCFG &= ~channel;
143 }
TSI_CHCFG
#define TSI_CHCFG
Definition: gd32f3x0_tsi.h:28
void tsi_channel_pin_enable ( uint32_t channel )

enable channel pin

Parameters
[in] channel channel pin
  • TSI_CHCFG_GxPy( x=0..5,y=0..3): pin y of group x
[out] none
Return values
none

Definition at line 128 of file gd32f3x0_tsi.c.

129 {
130 TSI_CHCFG |= channel;
131 }
TSI_CHCFG
#define TSI_CHCFG
Definition: gd32f3x0_tsi.h:28
void tsi_deinit ( void )

reset TSI peripheral

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_tsi.c.

21 {
22 rcu_periph_reset_enable(RCU_TSIRST);
23 rcu_periph_reset_disable(RCU_TSIRST);
24 }
RCU_TSIRST
Definition: gd32f3x0_rcu.h:331
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
void tsi_disable ( void )

disable TSI module

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 322 of file gd32f3x0_tsi.c.

323 {
324 TSI_CTL0 &= ~TSI_CTL0_TSIEN;
325 }
TSI_CTL0_TSIEN
#define TSI_CTL0_TSIEN
Definition: gd32f3x0_tsi.h:40
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
void tsi_enable ( void )

enable TSI module

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 311 of file gd32f3x0_tsi.c.

312 {
313 TSI_CTL0 |= TSI_CTL0_TSIEN;
314 }
TSI_CTL0_TSIEN
#define TSI_CTL0_TSIEN
Definition: gd32f3x0_tsi.h:40
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
void tsi_extend_charge_config | ( | ControlStatus | extend,
 |  | uint8_t | prescaler,
 |  | uint32_t | max_duration
 | ) |  |

configure extend charge state

Parameters
[in] extend enable or disable extend charge state
  • ENABLE: enable extend charge state
  • DISABLE: disable extend charge state
[in] prescaler ECCLK clock division factor
  • TSI_EXTEND_DIV1: fECCLK = fHCLK
  • TSI_EXTEND_DIV2: fECCLK = fHCLK/2
  • TSI_EXTEND_DIV3: fECCLK = fHCLK/3
  • TSI_EXTEND_DIV4: fECCLK = fHCLK/4
  • TSI_EXTEND_DIV5: fECCLK = fHCLK/5
  • TSI_EXTEND_DIV6: fECCLK = fHCLK/6
  • TSI_EXTEND_DIV7: fECCLK = fHCLK/7
  • TSI_EXTEND_DIV8: fECCLK = fHCLK/8
[in] | max_duration | value range 1...128,extend charge state maximum duration time is 1*tECCLK~128*tECCLK
[out] | none
Return values
none

Definition at line 345 of file gd32f3x0_tsi.c.

346 {
347 uint32_t ctl0,ctl1;
348 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
349 if(DISABLE == extend){
350 /*disable extend charge state*/
351 TSI_CTL0 &= ~TSI_CTL0_ECEN;
352 }else{
353 if(TSI_EXTEND_DIV3 > prescaler){
354 /*configure extend charge state maximum duration time*/
355 ctl0 = TSI_CTL0;
356 ctl0 &= ~TSI_CTL0_ECDT;
357 ctl0 |= TSI_EXTENDMAX((max_duration-1U));
358 TSI_CTL0 = ctl0;
359 /*configure ECCLK clock division factor*/
360 ctl0 = TSI_CTL0;
361 ctl0 &= ~TSI_CTL0_ECDIV;
362 ctl0 |= (uint32_t)prescaler<<15U;
363 TSI_CTL0 = ctl0;
364 /*enable extend charge state*/
365 TSI_CTL0 |= TSI_CTL0_ECEN;
366 }else{
367 /*configure extend charge state maximum duration time*/
368 ctl0 = TSI_CTL0;
369 ctl0 &= ~TSI_CTL0_ECDT;
370 ctl0 |= TSI_EXTENDMAX((max_duration-1U));
371 TSI_CTL0 = ctl0;
372 /*configure ECCLK clock division factor*/
373 ctl0 = TSI_CTL0;
374 ctl0 &= ~TSI_CTL0_ECDIV;
375 ctl0 |= (prescaler & 0x01U)<<15U;
376 TSI_CTL0 = ctl0;
377 ctl1 = TSI_CTL1;
378 ctl1 &= ~TSI_CTL1_ECDIV;
379 ctl1 |= (prescaler & 0x06U)<<28U;
380 TSI_CTL1 = ctl1;
381 /*enable extend charge state*/
382 TSI_CTL0 |= TSI_CTL0_ECEN;
383 }
384 }
385 }
386 }
TSI_CTL0_ECDIV
#define TSI_CTL0_ECDIV
Definition: gd32f3x0_tsi.h:47
TSI_CTL0_ECDT
#define TSI_CTL0_ECDT
Definition: gd32f3x0_tsi.h:49
TSI_CTL0_ECEN
#define TSI_CTL0_ECEN
Definition: gd32f3x0_tsi.h:48
TSI_CTL1_ECDIV
#define TSI_CTL1_ECDIV
Definition: gd32f3x0_tsi.h:205
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
TSI_CTL1
#define TSI_CTL1
Definition: gd32f3x0_tsi.h:36
TSI_EXTENDMAX
#define TSI_EXTENDMAX(regval)
Definition: gd32f3x0_tsi.h:285
TSI_EXTEND_DIV3
#define TSI_EXTEND_DIV3
Definition: gd32f3x0_tsi.h:277
void tsi_flag_clear ( uint32_t flag )

clear flag

Parameters
[in] source select flag which will be cleared
  • TSI_FLAG_CTCF_CLR: clear charge-transfer complete flag
  • TSI_FLAG_MNERR_CLR: clear max cycle number error
[out] none
Return values
none

Definition at line 474 of file gd32f3x0_tsi.c.

475 {
476 TSI_INTC |= flag;
477 }
TSI_INTC
#define TSI_INTC
Definition: gd32f3x0_tsi.h:23
FlagStatus tsi_flag_get ( uint32_t flag )

get flag

Parameters
[in] status
  • TSI_FLAG_CTCF: charge-transfer complete flag
  • TSI_FLAG_MNERR: max Cycle Number Error
[out] none
Return values
FlagStatus:SET or RESET

Definition at line 487 of file gd32f3x0_tsi.c.

488 {
489 FlagStatus flag_status;
490 if(TSI_INTF & flag){
491 flag_status = SET;
492 }else{
493 flag_status = RESET;
494 }
495 return flag_status;
496 }
TSI_INTF
#define TSI_INTF
Definition: gd32f3x0_tsi.h:24
uint16_t tsi_group0_cycle_get ( void )

get the cycle number for group0 as soon as a charge-transfer sequence completes

Parameters
[in] | none
[out] | none
Return values
group0 cycle number

Definition at line 594 of file gd32f3x0_tsi.c.

595 {
596 return (uint16_t)TSI_G0CYCN;
597 }
TSI_G0CYCN
#define TSI_G0CYCN
Definition: gd32f3x0_tsi.h:30
uint16_t tsi_group1_cycle_get ( void )

get the cycle number for group1 as soon as a charge-transfer sequence completes

Parameters
[in] | none
[out] | none
Return values
group1 cycle number

Definition at line 605 of file gd32f3x0_tsi.c.

606 {
607 return (uint16_t)TSI_G1CYCN;
608 }
TSI_G1CYCN
#define TSI_G1CYCN
Definition: gd32f3x0_tsi.h:31
uint16_t tsi_group2_cycle_get ( void )

get the cycle number for group2 as soon as a charge-transfer sequence completes

Parameters
[in] | none
[out] | none
Return values
group2 cycle number

Definition at line 616 of file gd32f3x0_tsi.c.

617 {
618 return (uint16_t)TSI_G2CYCN;
619 }
TSI_G2CYCN
#define TSI_G2CYCN
Definition: gd32f3x0_tsi.h:32
uint16_t tsi_group3_cycle_get ( void )

get the cycle number for group3 as soon as a charge-transfer sequence completes

Parameters
[in] | none
[out] | none
Return values
group3 cycle number

Definition at line 627 of file gd32f3x0_tsi.c.

628 {
629 return (uint16_t)TSI_G3CYCN;
630 }
TSI_G3CYCN
#define TSI_G3CYCN
Definition: gd32f3x0_tsi.h:33
uint16_t tsi_group4_cycle_get ( void )

get the cycle number for group4 as soon as a charge-transfer sequence completes

Parameters
[in] | none
[out] | none
Return values
group4 cycle number

Definition at line 638 of file gd32f3x0_tsi.c.

639 {
640 return (uint16_t)TSI_G4CYCN;
641 }
TSI_G4CYCN
#define TSI_G4CYCN
Definition: gd32f3x0_tsi.h:34
uint16_t tsi_group5_cycle_get ( void )

get the cycle number for group5 as soon as a charge-transfer sequence completes

Parameters
[in] | none
[out] | none
Return values
group5 cycle number

Definition at line 649 of file gd32f3x0_tsi.c.

650 {
651 return (uint16_t)TSI_G5CYCN;
652 }
TSI_G5CYCN
#define TSI_G5CYCN
Definition: gd32f3x0_tsi.h:35
void tsi_group_disable ( uint32_t group )

disbale group

Parameters
[in] group select group to be disabled
  • TSI_GCTL_GEx(x=0..5):the x group will be disabled
[out] none
Return values
none

Definition at line 565 of file gd32f3x0_tsi.c.

566 {
567 TSI_GCTL &= ~group;
568 }
TSI_GCTL
#define TSI_GCTL
Definition: gd32f3x0_tsi.h:29
void tsi_group_enable ( uint32_t group )

enbale group

Parameters
[in] group select group to be enabled
  • TSI_GCTL_GEx(x=0..5): the x group will be enabled
[out] none
Return values
none

Definition at line 553 of file gd32f3x0_tsi.c.

554 {
555 TSI_GCTL |= group;
556 }
TSI_GCTL
#define TSI_GCTL
Definition: gd32f3x0_tsi.h:29
FlagStatus tsi_group_status_get ( uint32_t group )

get group complete status

Parameters
[in] group select group
  • TSI_GCTL_GCx(x=0..5): get the complete status of group x
[out] none
Return values
FlagStatus group complete status,SET or RESET

Definition at line 577 of file gd32f3x0_tsi.c.

578 {
579 FlagStatus flag_status;
580 if(TSI_GCTL & group){
581 flag_status = SET;
582 }else{
583 flag_status = RESET;
584 }
585 return flag_status;
586 }
TSI_GCTL
#define TSI_GCTL
Definition: gd32f3x0_tsi.h:29
void tsi_hardware_mode_config ( uint8_t trigger_edge )

configure TSI triggering by hardware

Parameters
[in] trigger_edge the edge type in hardware trigger mode
  • TSI_FALLING_TRIGGER: falling edge trigger TSI charge transfer sequence
  • TSI_RISING_TRIGGER: rising edge trigger TSI charge transfer sequence
[out] none
Return values
none

Definition at line 225 of file gd32f3x0_tsi.c.

226 {
227 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
228 /*enable hardware mode*/
229 TSI_CTL0 |= TSI_CTL0_TRGMOD;
230 /*configure the edge type in hardware trigger mode*/
231 if(TSI_FALLING_TRIGGER == trigger_edge){
232 TSI_CTL0 &= ~TSI_CTL0_EGSEL;
233 }else{
234 TSI_CTL0 |= TSI_CTL0_EGSEL;
235 }
236 }
237 }
TSI_CTL0_EGSEL
#define TSI_CTL0_EGSEL
Definition: gd32f3x0_tsi.h:43
TSI_CTL0_TRGMOD
#define TSI_CTL0_TRGMOD
Definition: gd32f3x0_tsi.h:42
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
TSI_FALLING_TRIGGER
#define TSI_FALLING_TRIGGER
Definition: gd32f3x0_tsi.h:288
void tsi_hysteresis_off ( uint32_t group_pin )

switch off hysteresis pin

Parameters
[in] group_pin select pin which will be switched off hysteresis
  • TSI_PHM_GxPy(x=0..5,y=0..3): pin y of group x switch off hysteresis
[out] none
Return values
none

Definition at line 517 of file gd32f3x0_tsi.c.

518 {
519 TSI_PHM &= ~group_pin;
520 }
TSI_PHM
#define TSI_PHM
Definition: gd32f3x0_tsi.h:25
void tsi_hysteresis_on ( uint32_t group_pin )

switch on hysteresis pin

Parameters
[in] group_pin select pin which will be switched on hysteresis
  • TSI_PHM_GxPy(x=0..5,y=0..3): pin y of group x switch on hysteresis
[out] none
Return values
none

Definition at line 505 of file gd32f3x0_tsi.c.

506 {
507 TSI_PHM |= group_pin;
508 }
TSI_PHM
#define TSI_PHM
Definition: gd32f3x0_tsi.h:25
void tsi_init | ( | uint32_t | prescaler,
 |  | uint32_t | charge_duration,
 |  | uint32_t | transfer_duration,
 |  | uint32_t | max_number
 | ) |  |

initialize TSI plus prescaler,charge plus,transfer plus,max cycle number

Parameters
[in] prescaler CTCLK clock division factor
  • TSI_CTCDIV_DIV1: fCTCLK = fHCLK
  • TSI_CTCDIV_DIV2: fCTCLK = fHCLK/2
  • TSI_CTCDIV_DIV4: fCTCLK = fHCLK/4
  • TSI_CTCDIV_DIV8: fCTCLK = fHCLK/8
  • TSI_CTCDIV_DIV16: fCTCLK = fHCLK/16
  • TSI_CTCDIV_DIV32: fCTCLK = fHCLK/32
  • TSI_CTCDIV_DIV64: fCTCLK = fHCLK/64
  • TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128
  • TSI_CTCDIV_DIV256: fCTCLK = fHCLK/256
  • TSI_CTCDIV_DIV512: fCTCLK = fHCLK/512
  • TSI_CTCDIV_DIV1024: fCTCLK = fHCLK/1024
  • TSI_CTCDIV_DIV2048: fCTCLK = fHCLK/2048
  • TSI_CTCDIV_DIV4096: fCTCLK = fHCLK/4096
  • TSI_CTCDIV_DIV8192: fCTCLK = fHCLK/8192
  • TSI_CTCDIV_DIV16384: fCTCLK = fHCLK/16384
  • TSI_CTCDIV_DIV32768: fCTCLK = fHCLK/32768
[in] charge_duration charge state duration time
  • TSI_CHARGE_1CTCLK(x=1..16): the duration time of charge state is x CTCLK
[in] transfer_duration charge transfer state duration time
  • TSI_TRANSFER_xCTCLK(x=1..16): the duration time of transfer state is x CTCLK
[in] max_number max cycle number
  • TSI_MAXNUM255: the max cycle number of a sequence is 255
  • TSI_MAXNUM511: the max cycle number of a sequence is 511
  • TSI_MAXNUM1023: the max cycle number of a sequence is 1023
  • TSI_MAXNUM2047: the max cycle number of a sequence is 2047
  • TSI_MAXNUM4095: the max cycle number of a sequence is 4095
  • TSI_MAXNUM8191: the max cycle number of a sequence is 8191
  • TSI_MAXNUM16383: the max cycle number of a sequence is 16383
[out] none
Return values
none

Definition at line 60 of file gd32f3x0_tsi.c.

61 {
62 uint32_t ctl0,ctl1;
63 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
64 if(TSI_CTCDIV_DIV256 > prescaler){
65 /* config TSI_CTL0 */
66 ctl0 = TSI_CTL0;
67 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
68 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT|TSI_CTL0_MCN);
69 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration|max_number);
70 TSI_CTL0 = ctl0;
71
72 /* config TSI_CTL1 */
73 ctl1 = TSI_CTL1;
74 ctl1 &= ~TSI_CTL1_CTCDIV;
75 TSI_CTL1 = ctl1;
76 }else{
77 /* config TSI_CTL0 */
78 ctl0 = TSI_CTL0;
79 prescaler &= ~0x08U;
80 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
81 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT|TSI_CTL0_MCN);
82 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration|max_number);
83 TSI_CTL0 = ctl0;
84
85 /* config TSI_CTL1 */
86 ctl1 = TSI_CTL1;
87 ctl1 |= TSI_CTL1_CTCDIV;
88 TSI_CTL1 = ctl1;
89 }
90 }
91 }
TSI_CTL0_CTCDIV
#define TSI_CTL0_CTCDIV
Definition: gd32f3x0_tsi.h:46
TSI_CTL0_MCN
#define TSI_CTL0_MCN
Definition: gd32f3x0_tsi.h:45
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_CDT
#define TSI_CTL0_CDT
Definition: gd32f3x0_tsi.h:51
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
TSI_CTCDIV_DIV256
#define TSI_CTCDIV_DIV256
Definition: gd32f3x0_tsi.h:217
TSI_CTL1_CTCDIV
#define TSI_CTL1_CTCDIV
Definition: gd32f3x0_tsi.h:204
TSI_CTL0_CTDT
#define TSI_CTL0_CTDT
Definition: gd32f3x0_tsi.h:50
TSI_CTL1
#define TSI_CTL1
Definition: gd32f3x0_tsi.h:36
void tsi_interrupt_disable ( uint32_t source )

disable TSI interrupt

Parameters
[in] source select interrupt which will be disabled
  • TSI_INT_CCTCF: charge-transfer complete flag interrupt disable
  • TSI_INT_MNERR: max cycle number error interrupt disable
[out] none
Return values
none

Definition at line 409 of file gd32f3x0_tsi.c.

410 {
411 TSI_INTEN &= ~source;
412 }
TSI_INTEN
#define TSI_INTEN
Definition: gd32f3x0_tsi.h:22
void tsi_interrupt_enable ( uint32_t source )

enable TSI interrupt

Parameters
[in] source select interrupt which will be enabled
  • TSI_INT_CCTCF: charge-transfer complete flag interrupt enable
  • TSI_INT_MNERR: max cycle number error interrupt enable
[out] none
Return values
none

Definition at line 396 of file gd32f3x0_tsi.c.

397 {
398 TSI_INTEN |= source;
399 }
TSI_INTEN
#define TSI_INTEN
Definition: gd32f3x0_tsi.h:22
void tsi_interrupt_flag_clear ( uint32_t flag )

clear TSI interrupt flag

Parameters
[in] source select flag which will be cleared
  • TSI_INT_FLAG_CTCF_CLR: clear charge-transfer complete flag
  • TSI_INT_FLAG_MNERR_CLR: clear max cycle number error
[out] none
Return values
none

Definition at line 422 of file gd32f3x0_tsi.c.

423 {
424 TSI_INTC |= flag;
425 }
TSI_INTC
#define TSI_INTC
Definition: gd32f3x0_tsi.h:23
FlagStatus tsi_interrupt_flag_get ( uint32_t flag )

get TSI interrupt flag

Parameters
[in] status
  • TSI_INT_FLAG_CTCF: charge-transfer complete flag
  • TSI_INT_FLAG_MNERR: max Cycle Number Error
[out] none
Return values
FlagStatus:SET or RESET

Definition at line 435 of file gd32f3x0_tsi.c.

436 {
437 FlagStatus flag_status;
438 uint32_t tsi_inten;
439 tsi_inten = TSI_INTEN;
440 if(TSI_INT_FLAG_CTCF == flag){
441 if(TSI_INT_CCTCF & tsi_inten){
442 if(TSI_INTF & flag){
443 flag_status = SET;
444 }else{
445 flag_status = RESET;
446 }
447 }else{
448 flag_status = RESET;
449 }
450 }else if(TSI_INT_FLAG_MNERR == flag){
451 if(TSI_INT_MNERR & tsi_inten){
452 if(TSI_INTF & flag){
453 flag_status = SET;
454 }else{
455 flag_status = RESET;
456 }
457 }else{
458 flag_status = RESET;
459 }
460 }else{
461 flag_status = RESET;
462 }
463 return flag_status;
464 }
TSI_INTEN
#define TSI_INTEN
Definition: gd32f3x0_tsi.h:22
TSI_INT_MNERR
#define TSI_INT_MNERR
Definition: gd32f3x0_tsi.h:67
TSI_INTF
#define TSI_INTF
Definition: gd32f3x0_tsi.h:24
TSI_INT_CCTCF
#define TSI_INT_CCTCF
Definition: gd32f3x0_tsi.h:66
TSI_INT_FLAG_MNERR
#define TSI_INT_FLAG_MNERR
Definition: gd32f3x0_tsi.h:71
TSI_INT_FLAG_CTCF
#define TSI_INT_FLAG_CTCF
Definition: gd32f3x0_tsi.h:70
void tsi_max_number_config ( uint32_t max_number )

configure the max cycle number of a charge-transfer sequence

Parameters
[in] max_number max cycle number
  • TSI_MAXNUM255: the max cycle number of a sequence is 255
  • TSI_MAXNUM511: the max cycle number of a sequence is 511
  • TSI_MAXNUM1023: the max cycle number of a sequence is 1023
  • TSI_MAXNUM2047: the max cycle number of a sequence is 2047
  • TSI_MAXNUM4095: the max cycle number of a sequence is 4095
  • TSI_MAXNUM8191: the max cycle number of a sequence is 8191
  • TSI_MAXNUM16383: the max cycle number of a sequence is 16383
[out] none
Return values
none

Definition at line 271 of file gd32f3x0_tsi.c.

272 {
273 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
274 uint32_t maxnum;
275 maxnum = TSI_CTL0;
276 /*configure the max cycle number of a charge-transfer sequence*/
277 maxnum &= ~TSI_CTL0_MCN;
278 maxnum |= max_number;
279 TSI_CTL0 = maxnum;
280 }
281 }
TSI_CTL0_MCN
#define TSI_CTL0_MCN
Definition: gd32f3x0_tsi.h:45
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
void tsi_pin_mode_config ( uint8_t pin_mode )

configure TSI pin mode when charge-transfer sequence is IDLE

Parameters
[in] pin_mode pin mode when charge-transfer sequence is IDLE
  • TSI_OUTPUT_LOW: TSI pin will output low when IDLE
  • TSI_INPUT_FLOATING: TSI pin will keep input_floating when IDLE
[out] none
Return values
none

Definition at line 247 of file gd32f3x0_tsi.c.

248 {
249 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
250 if(TSI_OUTPUT_LOW == pin_mode){
251 TSI_CTL0 &= ~TSI_CTL0_PINMOD;
252 }else{
253 TSI_CTL0 |= TSI_CTL0_PINMOD;
254 }
255 }
256 }
TSI_OUTPUT_LOW
#define TSI_OUTPUT_LOW
Definition: gd32f3x0_tsi.h:292
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_PINMOD
#define TSI_CTL0_PINMOD
Definition: gd32f3x0_tsi.h:44
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
void tsi_plus_config | ( | uint32_t | prescaler,
 |  | uint32_t | charge_duration,
 |  | uint32_t | transfer_duration
 | ) |  |

configure charge plus and transfer plus

Parameters
[in] prescaler CTCLK clock division factor
  • TSI_CTCDIV_DIV1: fCTCLK = fHCLK
  • TSI_CTCDIV_DIV2: fCTCLK = fHCLK/2
  • TSI_CTCDIV_DIV4: fCTCLK = fHCLK/4
  • TSI_CTCDIV_DIV8: fCTCLK = fHCLK/8
  • TSI_CTCDIV_DIV16: fCTCLK = fHCLK/16
  • TSI_CTCDIV_DIV32: fCTCLK = fHCLK/32
  • TSI_CTCDIV_DIV64: fCTCLK = fHCLK/64
  • TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128
  • TSI_CTCDIV_DIV256: fCTCLK = fHCLK/256
  • TSI_CTCDIV_DIV512: fCTCLK = fHCLK/512
  • TSI_CTCDIV_DIV1024: fCTCLK = fHCLK/1024
  • TSI_CTCDIV_DIV2048: fCTCLK = fHCLK/2048
  • TSI_CTCDIV_DIV4096: fCTCLK = fHCLK/4096
  • TSI_CTCDIV_DIV8192: fCTCLK = fHCLK/8192
  • TSI_CTCDIV_DIV16384: fCTCLK = fHCLK/16384
  • TSI_CTCDIV_DIV32768: fCTCLK = fHCLK/32768
[in] charge_duration charge state duration time
  • TSI_CHARGE_xCTCLK(x=1..16): the duration time of charge state is x CTCLK
[in] transfer_duration charge transfer state duration time
  • TSI_TRANSFER_xCTCLK(x=1..16): the duration time of transfer state is x CTCLK
[out] none
Return values
none

Definition at line 171 of file gd32f3x0_tsi.c.

172 {
173 uint32_t ctl0,ctl1;
174 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
175 if(TSI_CTCDIV_DIV256 > prescaler){
176 /* config TSI_CTL0 */
177 ctl0 = TSI_CTL0;
178 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
179 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT);
180 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration);
181 TSI_CTL0 = ctl0;
182
183 /* config TSI_CTL1 */
184 ctl1 = TSI_CTL1;
185 ctl1 &= ~TSI_CTL1_CTCDIV;
186 TSI_CTL1 = ctl1;
187 }else{
188 /* config TSI_CTL */
189 ctl0 = TSI_CTL0;
190 prescaler &= ~0x08U;
191 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
192 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT);
193 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration);
194 TSI_CTL0 = ctl0;
195
196 /* config TSI_CTL2 */
197 ctl1 = TSI_CTL1;
198 ctl1 |= TSI_CTL1_CTCDIV;
199 TSI_CTL1 = ctl1;
200 }
201 }
202 }
TSI_CTL0_CTCDIV
#define TSI_CTL0_CTCDIV
Definition: gd32f3x0_tsi.h:46
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_CDT
#define TSI_CTL0_CDT
Definition: gd32f3x0_tsi.h:51
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
TSI_CTCDIV_DIV256
#define TSI_CTCDIV_DIV256
Definition: gd32f3x0_tsi.h:217
TSI_CTL1_CTCDIV
#define TSI_CTL1_CTCDIV
Definition: gd32f3x0_tsi.h:204
TSI_CTL0_CTDT
#define TSI_CTL0_CTDT
Definition: gd32f3x0_tsi.h:50
TSI_CTL1
#define TSI_CTL1
Definition: gd32f3x0_tsi.h:36
void tsi_sample_pin_disable ( uint32_t sample )

disable sample pin

Parameters
[in] sample sample pin
  • TSI_SAMPCFG_GxPy( x=0..5,y=0..3): pin y of group x is sample pin
[out] none
Return values
none

Definition at line 114 of file gd32f3x0_tsi.c.

115 {
116 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
117 TSI_SAMPCFG &= ~sample;
118 }
119 }
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_SAMPCFG
#define TSI_SAMPCFG
Definition: gd32f3x0_tsi.h:27
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
void tsi_sample_pin_enable ( uint32_t sample )

enable sample pin

Parameters
[in] sample sample pin
  • TSI_SAMPCFG_GxPy( x=0..5,y=0..3):pin y of group x is sample pin
[out] none
Return values
none

Definition at line 100 of file gd32f3x0_tsi.c.

101 {
102 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
103 TSI_SAMPCFG |= sample;
104 }
105 }
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_SAMPCFG
#define TSI_SAMPCFG
Definition: gd32f3x0_tsi.h:27
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
void tsi_sofeware_mode_config ( void )

configure TSI triggering by software

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 210 of file gd32f3x0_tsi.c.

211 {
212 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
213 TSI_CTL0 &= ~TSI_CTL0_TRGMOD;
214 }
215 }
TSI_CTL0_TRGMOD
#define TSI_CTL0_TRGMOD
Definition: gd32f3x0_tsi.h:42
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
void tsi_software_start ( void )

start a charge-transfer sequence when TSI is in software trigger mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 289 of file gd32f3x0_tsi.c.

290 {
291 TSI_CTL0 |= TSI_CTL0_TSIS;
292 }
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
void tsi_software_stop ( void )

stop a charge-transfer sequence when TSI is in software trigger mode

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 300 of file gd32f3x0_tsi.c.

301 {
302 TSI_CTL0 &= ~TSI_CTL0_TSIS;
303 }
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_usart.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_usart.c File Reference

USART driver. More...

#include "gd32f3x0_usart.h"

Go to the source code of this file.

Functions

void | usart_deinit (uint32_t usart_periph)
reset USART More...
void | usart_baudrate_set (uint32_t usart_periph, uint32_t baudval)
configure USART baud rate value More...
void | usart_parity_config (uint32_t usart_periph, uint32_t paritycfg)
configure USART parity More...
void | usart_word_length_set (uint32_t usart_periph, uint32_t wlen)
configure USART word length More...
void | usart_stop_bit_set (uint32_t usart_periph, uint32_t stblen)
configure USART stop bit length More...
void | usart_enable (uint32_t usart_periph)
enable USART More...
void | usart_disable (uint32_t usart_periph)
disable USART More...
void | usart_transmit_config (uint32_t usart_periph, uint32_t txconfig)
configure USART transmitter More...
void | usart_receive_config (uint32_t usart_periph, uint32_t rxconfig)
configure USART receiver More...
void | usart_data_transmit (uint32_t usart_periph, uint32_t data)
USART transmit data function. More...
uint16_t | usart_data_receive (uint32_t usart_periph)
USART receive data function. More...
void | usart_data_first_config (uint32_t usart_periph, uint32_t msbf)
data is transmitted/received with the LSB/MSB first More...
void | usart_invert_config (uint32_t usart_periph, usart_invert_enum invertpara)
USART inverted configure. More...
void | usart_overrun_enable (uint32_t usart_periph)
overrun function is enabled More...
void | usart_overrun_disable (uint32_t usart_periph)
overrun function is disabled More...
void | usart_oversample_config (uint32_t usart_periph, uint32_t oversamp)
configure the USART oversample mode More...
void | usart_sample_bit_config (uint32_t usart_periph, uint32_t osb)
sample bit method configure More...
void | usart_autobaud_detection_enable (uint32_t usart_periph)
auto baud rate detection enable More...
void | usart_autobaud_detection_disable (uint32_t usart_periph)
auto baud rate detection disable More...
void | usart_autobaud_detection_mode_config (uint32_t usart_periph, uint32_t abdmod)
auto baud rate detection mode configure More...
void | usart_mute_mode_enable (uint32_t usart_periph)
mute mode enable More...
void | usart_mute_mode_disable (uint32_t usart_periph)
mute mode disable More...
void | usart_mute_mode_wakeup_config (uint32_t usart_periph, uint32_t wmethod)
wakeup method in mute mode configure More...
void | usart_address_detection_mode_config (uint32_t usart_periph, uint32_t addmod)
address detection mode configure More...
void | usart_address_config (uint32_t usart_periph, uint8_t addr)
address of the USART terminal More...
void | usart_receiver_timeout_enable (uint32_t usart_periph)
receiver timeout enable More...
void | usart_receiver_timeout_disable (uint32_t usart_periph)
receiver timeout disable More...
void | usart_receiver_timeout_config (uint32_t usart_periph, uint32_t rtimeout)
receiver timeout threshold configure More...
void | usart_lin_mode_enable (uint32_t usart_periph)
LIN mode enable. More...
void | usart_lin_mode_disable (uint32_t usart_periph)
LIN mode disable. More...
void | usart_lin_break_dection_length_config (uint32_t usart_periph, uint32_t lblen)
LIN break detection length. More...
void | usart_halfduplex_enable (uint32_t usart_periph)
half-duplex enable More...
void | usart_halfduplex_disable (uint32_t usart_periph)
half-duplex disable More...
void | usart_clock_enable (uint32_t usart_periph)
clock enable More...
void | usart_clock_disable (uint32_t usart_periph)
clock disable More...
void | usart_synchronous_clock_config (uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
configure USART synchronous mode parameters More...
void | usart_smartcard_mode_enable (uint32_t usart_periph)
smartcard mode enable More...
void | usart_smartcard_mode_disable (uint32_t usart_periph)
smartcard mode disable More...
void | usart_smartcard_mode_nack_enable (uint32_t usart_periph)
NACK enable in smartcard mode. More...
void | usart_smartcard_mode_nack_disable (uint32_t usart_periph)
NACK disable in smartcard mode. More...
void | usart_guard_time_config (uint32_t usart_periph, uint32_t guat)
guard time value configure in smartcard mode More...
void | usart_block_length_config (uint32_t usart_periph, uint32_t bl)
block length configure More...
void | usart_smartcard_autoretry_config (uint32_t usart_periph, uint32_t scrtnum)
smartcard auto-retry number configure More...
void | usart_smartcard_mode_early_nack_enable (uint32_t usart_periph)
early NACK enable in smartcard mode More...
void | usart_smartcard_mode_early_nack_disable (uint32_t usart_periph)
early NACK disable in smartcard mode More...
void | usart_irda_mode_enable (uint32_t usart_periph)
IrDA mode enable. More...
void | usart_irda_mode_disable (uint32_t usart_periph)
IrDA mode disable. More...
void | usart_irda_lowpower_config (uint32_t usart_periph, uint32_t irlp)
IrDA low-power configure. More...
void | usart_prescaler_config (uint32_t usart_periph, uint32_t psc)
configure the peripheral clock prescaler in USART IrDA low-power mode More...
void | usart_hardware_flow_rts_config (uint32_t usart_periph, uint32_t rtsconfig)
configure hardware flow control RTS More...
void | usart_hardware_flow_cts_config (uint32_t usart_periph, uint32_t ctsconfig)
configure hardware flow control CTS More...
void | usart_rs485_driver_enable (uint32_t usart_periph)
RS485 driver enable. More...
void | usart_rs485_driver_disable (uint32_t usart_periph)
RS485 driver disable. More...
void | usart_driver_assertime_config (uint32_t usart_periph, uint32_t deatime)
driver enable assertion time configure More...
void | usart_driver_deassertime_config (uint32_t usart_periph, uint32_t dedtime)
driver enable de-assertion time configure More...
void | usart_depolarity_config (uint32_t usart_periph, uint32_t dep)
configure driver enable polarity mode More...
void | usart_dma_receive_config (uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA reception More...
void | usart_dma_transmit_config (uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA transmission More...
void | usart_reception_error_dma_disable (uint32_t usart_periph)
disable DMA on reception error More...
void | usart_reception_error_dma_enable (uint32_t usart_periph)
enable DMA on reception error More...
void | usart_wakeup_enable (uint32_t usart_periph)
USART be able to wake up the MCU from deep-sleep mode. More...
void | usart_wakeup_disable (uint32_t usart_periph)
USART be not able to wake up the MCU from deep-sleep mode. More...
void | usart_wakeup_mode_config (uint32_t usart_periph, uint32_t wum)
wakeup mode from deep-sleep mode More...
void | usart_receive_fifo_enable (uint32_t usart_periph)
receive FIFO enable More...
void | usart_receive_fifo_disable (uint32_t usart_periph)
receive FIFO disable More...
uint8_t | usart_receive_fifo_counter_number (uint32_t usart_periph)
read receive FIFO counter number More...
FlagStatus | usart_flag_get (uint32_t usart_periph, usart_flag_enum flag)
get flag in STAT/RFCS register More...
void | usart_flag_clear (uint32_t usart_periph, usart_flag_enum flag)
clear USART status More...
void | usart_interrupt_enable (uint32_t usart_periph, uint32_t inttype)
enable USART interrupt More...
void | usart_interrupt_disable (uint32_t usart_periph, uint32_t inttype)
disable USART interrupt More...
void | usart_command_enable (uint32_t usart_periph, uint32_t cmdtype)
enable USART command More...
FlagStatus | usart_interrupt_flag_get (uint32_t usart_periph, uint32_t int_flag)
get USART interrupt and flag status More...
void | usart_interrupt_flag_clear (uint32_t usart_periph, uint32_t flag)
clear USART interrupt flag More...

Detailed Description

USART driver.

Definition in file gd32f3x0_usart.c.

Function Documentation

void usart_address_config | ( | uint32_t | usart_periph,
 |  | uint8_t | addr
 | ) |  |

address of the USART terminal

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] | addr | 0x00-0xFF, address of USART terminal
[out] | none
Return values
none

Definition at line 430 of file gd32f3x0_usart.c.

431 {
432 /* disable USART */
433 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
434
435 USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR);
436 USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (((uint32_t)addr) << 24));
437 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_ADDR
#define USART_CTL1_ADDR
Definition: gd32f3x0_usart.h:76
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_address_detection_mode_config | ( | uint32_t | usart_periph,
 |  | uint32_t | addmod
 | ) |  |

address detection mode configure

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] addmod address detection mode
  • USART_ADDM_4BIT: 4 bits
  • USART_ADDM_FULLBIT: full bits
[out] | none
Return values
none

Definition at line 414 of file gd32f3x0_usart.c.

415 {
416 /* disable USART */
417 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
418
419 USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDM);
420 USART_CTL1(usart_periph) |= USART_CTL1_ADDM & (addmod);
421 }
USART_CTL1_ADDM
#define USART_CTL1_ADDM
Definition: gd32f3x0_usart.h:59
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_autobaud_detection_disable ( uint32_t usart_periph )

auto baud rate detection disable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 344 of file gd32f3x0_usart.c.

345 {
346 USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDEN);
347 }
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_ABDEN
#define USART_CTL1_ABDEN
Definition: gd32f3x0_usart.h:73
void usart_autobaud_detection_enable ( uint32_t usart_periph )

auto baud rate detection enable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 333 of file gd32f3x0_usart.c.

334 {
335 USART_CTL1(usart_periph) |= USART_CTL1_ABDEN;
336 }
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_ABDEN
#define USART_CTL1_ABDEN
Definition: gd32f3x0_usart.h:73
void usart_autobaud_detection_mode_config | ( | uint32_t | usart_periph,
 |  | uint32_t | abdmod
 | ) |  |

auto baud rate detection mode configure

Parameters
[in] | usart_periph | USARTx(x=0)
[in] abdmod auto baud rate detection mode
  • USART_ABDM_FTOR: falling edge to rising edge measurement
  • USART_ABDM_FTOF: falling edge to falling edge measurement
[out] | none
Return values
none

Definition at line 358 of file gd32f3x0_usart.c.

359 {
360 /* reset ABDM bits */
361 USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDM);
362 USART_CTL1(usart_periph) |= abdmod;
363 }
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_ABDM
#define USART_CTL1_ABDM
Definition: gd32f3x0_usart.h:74
void usart_baudrate_set | ( | uint32_t | usart_periph,
 |  | uint32_t | baudval
 | ) |  |

configure USART baud rate value

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] | baudval | baud rate value
[out] | none
Return values
none

Definition at line 43 of file gd32f3x0_usart.c.

44 {
45 uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U;
46 switch(usart_periph){
47 case USART0:
48 uclk = rcu_clock_freq_get(CK_USART);
49 break;
50 case USART1:
51 uclk = rcu_clock_freq_get(CK_APB1);
52 break;
53 default:
54 break;
55 }
56 if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){
57 /* when oversampling by 8,configure the value of USART_BAUD */
58 udiv = ((2U*uclk)+baudval/2U)/baudval;
59 intdiv = udiv & 0xfff0U;
60 fradiv = udiv & 0x7U;
61 USART_BAUD(usart_periph) |= ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
62 }else{
63 /* when oversampling by 16,configure the value of USART_BAUD */
64 udiv = (uclk+baudval/2U)/baudval;
65 intdiv = udiv & 0xfff0U;
66 fradiv = udiv & 0xfU;
67 USART_BAUD(usart_periph) |= ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
68 }
69 }
CK_APB1
Definition: gd32f3x0_rcu.h:456
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
CK_USART
Definition: gd32f3x0_rcu.h:460
USART_CTL0_OVSMOD
#define USART_CTL0_OVSMOD
Definition: gd32f3x0_usart.h:52
USART1
#define USART1
Definition: gd32f3x0_usart.h:19
USART0
#define USART0
Definition: gd32f3x0_usart.h:18
USART_BAUD
#define USART_BAUD(usartx)
Definition: gd32f3x0_usart.h:25
USART_BAUD_INTDIV
#define USART_BAUD_INTDIV
Definition: gd32f3x0_usart.h:101
USART_BAUD_FRADIV
#define USART_BAUD_FRADIV
Definition: gd32f3x0_usart.h:100
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f3x0_rcu.c:964
void usart_block_length_config | ( | uint32_t | usart_periph,
 |  | uint32_t | bl
 | ) |  |

block length configure

Parameters
[in] | usart_periph | USARTx(x=0)
[in] | bl | 0x00-0xFF
[out] | none
Return values
none

Definition at line 681 of file gd32f3x0_usart.c.

682 {
683 USART_RT(usart_periph) &= ~(USART_RT_BL);
684 USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << 24));
685 }
USART_RT
#define USART_RT(usartx)
Definition: gd32f3x0_usart.h:27
USART_RT_BL
#define USART_RT_BL
Definition: gd32f3x0_usart.h:109
void usart_clock_disable ( uint32_t usart_periph )

clock disable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 567 of file gd32f3x0_usart.c.

568 {
569 /* disable USART */
570 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
571
572 USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN);
573 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_CKEN
#define USART_CTL1_CKEN
Definition: gd32f3x0_usart.h:65
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_clock_enable ( uint32_t usart_periph )

clock enable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 553 of file gd32f3x0_usart.c.

554 {
555 /* disable USART */
556 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
557
558 USART_CTL1(usart_periph) |= USART_CTL1_CKEN;
559 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_CKEN
#define USART_CTL1_CKEN
Definition: gd32f3x0_usart.h:65
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_command_enable | ( | uint32_t | usart_periph,
 |  | uint32_t | cmdtype
 | ) |  |

enable USART command

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] cmdtype command type
  • USART_CMD_ABDCMD: auto baudrate detection command
  • USART_CMD_SBKCMD: send break command
  • USART_CMD_MMCMD: mute mode command
  • USART_CMD_RXFCMD: receive data flush command
  • USART_CMD_TXFCMD: transmit data flush request
[out] | none
Return values
none

Definition at line 1161 of file gd32f3x0_usart.c.

1162 {
1163 USART_CMD(usart_periph) |= (cmdtype);
1164 }
USART_CMD
#define USART_CMD(usartx)
Definition: gd32f3x0_usart.h:28
void usart_data_first_config | ( | uint32_t | usart_periph,
 |  | uint32_t | msbf
 | ) |  |

data is transmitted/received with the LSB/MSB first

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] msbf LSB/MSB
  • USART_MSBF_LSB: LSB first
  • USART_MSBF_MSB: MSB first
[out] | none
Return values
none

Definition at line 216 of file gd32f3x0_usart.c.

217 {
218 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
219 /* configure LSB or MSB first */
220 USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF);
221 USART_CTL1(usart_periph) |= (USART_CTL1_MSBF & msbf);
222 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_MSBF
#define USART_CTL1_MSBF
Definition: gd32f3x0_usart.h:72
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
uint16_t usart_data_receive ( uint32_t usart_periph )

USART receive data function.

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
data of received

Definition at line 202 of file gd32f3x0_usart.c.

203 {
204 return (uint16_t)(GET_BITS(USART_RDATA(usart_periph), 0U, 8U));
205 }
USART_RDATA
#define USART_RDATA(usartx)
Definition: gd32f3x0_usart.h:31
void usart_data_transmit | ( | uint32_t | usart_periph,
 |  | uint32_t | data
 | ) |  |

USART transmit data function.

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] | data | data of transmission
[out] | none
Return values
none

Definition at line 191 of file gd32f3x0_usart.c.

192 {
193 USART_TDATA(usart_periph) = (USART_TDATA_TDATA & data);
194 }
USART_TDATA_TDATA
#define USART_TDATA_TDATA
Definition: gd32f3x0_usart.h:160
USART_TDATA
#define USART_TDATA(usartx)
Definition: gd32f3x0_usart.h:32
void usart_deinit ( uint32_t usart_periph )

reset USART

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 20 of file gd32f3x0_usart.c.

21 {
22 switch(usart_periph){
23 case USART0:
24 rcu_periph_reset_enable(RCU_USART0RST);
25 rcu_periph_reset_disable(RCU_USART0RST);
26 break;
27 case USART1:
28 rcu_periph_reset_enable(RCU_USART1RST);
29 rcu_periph_reset_disable(RCU_USART1RST);
30 break;
31 default:
32 break;
33 }
34 }
RCU_USART0RST
Definition: gd32f3x0_rcu.h:338
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
RCU_USART1RST
Definition: gd32f3x0_rcu.h:350
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
USART1
#define USART1
Definition: gd32f3x0_usart.h:19
USART0
#define USART0
Definition: gd32f3x0_usart.h:18
void usart_depolarity_config | ( | uint32_t | usart_periph,
 |  | uint32_t | dep
 | ) |  |

configure driver enable polarity mode

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] dep DE signal
  • USART_DEP_HIGH: DE signal is active high
  • USART_DEP_LOW: DE signal is active low
[out] | none
Return values
none

Definition at line 889 of file gd32f3x0_usart.c.

890 {
891 /* disable USART */
892 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
893 /* reset DEP bit */
894 USART_CTL2(usart_periph) &= ~(USART_CTL2_DEP);
895 USART_CTL2(usart_periph) |= (USART_CTL2_DEP & dep);
896 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_DEP
#define USART_CTL2_DEP
Definition: gd32f3x0_usart.h:94
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_disable ( uint32_t usart_periph )

disable USART

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 147 of file gd32f3x0_usart.c.

148 {
149 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
150 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_dma_receive_config | ( | uint32_t | usart_periph,
 |  | uint32_t | dmacmd
 | ) |  |

configure USART DMA reception

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] dmacmd enable or disable DMA for reception
  • USART_DENR_ENABLE: DMA enable for reception
  • USART_DENR_DISABLE: DMA disable for reception
[out] | none
Return values
none

Definition at line 907 of file gd32f3x0_usart.c.

908 {
909 USART_CTL2(usart_periph) &= ~USART_CTL2_DENR;
910 /* configure DMA reception */
911 USART_CTL2(usart_periph) |= dmacmd;
912 }
USART_CTL2_DENR
#define USART_CTL2_DENR
Definition: gd32f3x0_usart.h:85
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_dma_transmit_config | ( | uint32_t | usart_periph,
 |  | uint32_t | dmacmd
 | ) |  |

configure USART DMA transmission

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] dmacmd enable or disable DMA for transmission
  • USART_DENT_ENABLE: DMA enable for transmission
  • USART_DENT_DISABLE: DMA disable for transmission
[out] | none
Return values
none

Definition at line 923 of file gd32f3x0_usart.c.

924 {
925 USART_CTL2(usart_periph) &= ~USART_CTL2_DENT;
926 /* configure DMA transmission */
927 USART_CTL2(usart_periph) |= dmacmd;
928 }
USART_CTL2_DENT
#define USART_CTL2_DENT
Definition: gd32f3x0_usart.h:86
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_driver_assertime_config | ( | uint32_t | usart_periph,
 |  | uint32_t | deatime
 | ) |  |

driver enable assertion time configure

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] | deatime | 0x00-0x1F
[out] | none
Return values
none

Definition at line 855 of file gd32f3x0_usart.c.

856 {
857 /* disable USART */
858 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
859
860 USART_CTL0(usart_periph) &= ~(USART_CTL0_DEA);
861 USART_CTL0(usart_periph) |= (USART_CTL0_DEA & ((deatime) << 21));
862 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_DEA
#define USART_CTL0_DEA
Definition: gd32f3x0_usart.h:54
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_driver_deassertime_config | ( | uint32_t | usart_periph,
 |  | uint32_t | dedtime
 | ) |  |

driver enable de-assertion time configure

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] | dedtime | 0x00-0x1F
[out] | none
Return values
none

Definition at line 871 of file gd32f3x0_usart.c.

872 {
873 /* disable USART */
874 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
875
876 USART_CTL0(usart_periph) &= ~(USART_CTL0_DED);
877 USART_CTL0(usart_periph) |= (USART_CTL0_DED & ((dedtime) << 16));
878 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL0_DED
#define USART_CTL0_DED
Definition: gd32f3x0_usart.h:53
void usart_enable ( uint32_t usart_periph )

enable USART

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 136 of file gd32f3x0_usart.c.

137 {
138 USART_CTL0(usart_periph) |= USART_CTL0_UEN;
139 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_flag_clear | ( | uint32_t | usart_periph,
 |  | usart_flag_enum | flag
 | ) |  |

clear USART status

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] flag flag type
  • USART_FLAG_PERR: parity error flag
  • USART_FLAG_FERR: frame error flag
  • USART_FLAG_NERR: noise detected flag
  • USART_FLAG_ORERR:overrun error flag
  • USART_FLAG_IDLE: idle line detected flag
  • USART_FLAG_TC: transmission complete flag
  • USART_FLAG_LBD: LIN break detected flag
  • USART_FLAG_CTSF: CTS change flag
  • USART_FLAG_RT: receiver timeout flag
  • USART_FLAG_EB: end of block flag
  • USART_FLAG_AM: address match flag
  • USART_FLAG_WU: wakeup from deep-sleep mode flag
[out] | none
Return values
none

Definition at line 1092 of file gd32f3x0_usart.c.

1093 {
1094 USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag));
1095 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f3x0_usart.h:176
USART_INTC
#define USART_INTC(usartx)
Definition: gd32f3x0_usart.h:30
FlagStatus usart_flag_get | ( | uint32_t | usart_periph,
 |  | usart_flag_enum | flag
 | ) |  |

get flag in STAT/RFCS register

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] flag flag type
  • USART_FLAG_PERR: parity error flag
  • USART_FLAG_FERR: frame error flag
  • USART_FLAG_NERR: noise error flag
  • USART_FLAG_ORERR: overrun error
  • USART_FLAG_IDLE: idle line detected flag
  • USART_FLAG_RBNE: read data buffer not empty
  • USART_FLAG_TC: transmission completed
  • USART_FLAG_TBE: transmit data register empty
  • USART_FLAG_LBD: LIN break detected flag
  • USART_FLAG_CTSF: CTS change flag
  • USART_FLAG_CTS: CTS level
  • USART_FLAG_RT: receiver timeout flag
  • USART_FLAG_EB: end of block flag
  • USART_FLAG_ABDE: auto baudrate detection error
  • USART_FLAG_ABD: auto baudrate detection flag
  • USART_FLAG_BSY: busy flag
  • USART_FLAG_AM: address match flag
  • USART_FLAG_SB: send break flag
  • USART_FLAG_RWU: receiver wakeup from mute mode.
  • USART_FLAG_WU: wakeup from deep-sleep mode flag
  • USART_FLAG_TEA: transmit enable acknowledge flag
  • USART_FLAG_REA: receive enable acknowledge flag
  • USART_FLAG_RFFINT:receive FIFO full interrupt flag
  • USART_FLAG_RFE: receive FIFO empty flag
  • USART_FLAG_RFF: receive FIFO full flag
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 1064 of file gd32f3x0_usart.c.

1065 {
1066 if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){
1067 return SET;
1068 }else{
1069 return RESET;
1070 }
1071 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f3x0_usart.h:176
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f3x0_usart.h:175
void usart_guard_time_config | ( | uint32_t | usart_periph,
 |  | uint32_t | guat
 | ) |  |

guard time value configure in smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0)
[in] | guat | 0x00-0xFF
[out] | none
Return values
none

Definition at line 665 of file gd32f3x0_usart.c.

666 {
667 /* disable USART */
668 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
669
670 USART_GP(usart_periph) &= ~(USART_GP_GUAT);
671 USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << 8));
672 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_GP
#define USART_GP(usartx)
Definition: gd32f3x0_usart.h:26
USART_GP_GUAT
#define USART_GP_GUAT
Definition: gd32f3x0_usart.h:105
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_halfduplex_disable ( uint32_t usart_periph )

half-duplex disable

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 539 of file gd32f3x0_usart.c.

540 {
541 /* disable USART */
542 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
543
544 USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN);
545 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2_HDEN
#define USART_CTL2_HDEN
Definition: gd32f3x0_usart.h:82
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_halfduplex_enable ( uint32_t usart_periph )

half-duplex enable

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 525 of file gd32f3x0_usart.c.

526 {
527 /* disable USART */
528 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
529
530 USART_CTL2(usart_periph) |= USART_CTL2_HDEN;
531 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2_HDEN
#define USART_CTL2_HDEN
Definition: gd32f3x0_usart.h:82
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_hardware_flow_cts_config | ( | uint32_t | usart_periph,
 |  | uint32_t | ctsconfig
 | ) |  |

configure hardware flow control CTS

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] ctsconfig enable or disable CTS
  • USART_CTS_ENABLE: enable CTS
  • USART_CTS_DISABLE: disable CTS
[out] | none
Return values
none

Definition at line 811 of file gd32f3x0_usart.c.

812 {
813 /* disable USART */
814 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
815
816 USART_CTL2(usart_periph) &= ~USART_CTL2_CTSEN;
817 USART_CTL2(usart_periph) |= ctsconfig;
818 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_CTSEN
#define USART_CTL2_CTSEN
Definition: gd32f3x0_usart.h:88
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_hardware_flow_rts_config | ( | uint32_t | usart_periph,
 |  | uint32_t | rtsconfig
 | ) |  |

configure hardware flow control RTS

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] rtsconfig enable or disable RTS
  • USART_RTS_ENABLE: enable RTS
  • USART_RTS_DISABLE: disable RTS
[out] | none
Return values
none

Definition at line 793 of file gd32f3x0_usart.c.

794 {
795 /* disable USART */
796 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
797
798 USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN);
799 USART_CTL2(usart_periph) |= rtsconfig;
800 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_RTSEN
#define USART_CTL2_RTSEN
Definition: gd32f3x0_usart.h:87
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_interrupt_disable | ( | uint32_t | usart_periph,
 |  | uint32_t | inttype
 | ) |  |

disable USART interrupt

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] inttype interrupt type
  • USART_INT_IDLE: idle interrupt
  • USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt
  • USART_INT_TC: transmission complete interrupt
  • USART_INT_TBE: transmit data register empty interrupt
  • USART_INT_PERR: parity error interrupt
  • USART_INT_AM: address match interrupt
  • USART_INT_RT: receiver timeout interrupt
  • USART_INT_EB: end of block interrupt
  • USART_INT_LBD: LIN break detection interrupt
  • USART_INT_ERR: error interrupt enable in multibuffer communication
  • USART_INT_CTS: CTS interrupt
  • USART_INT_WU: wakeup from deep-sleep mode interrupt
  • USART_INT_RFF: receive FIFO full interrupt enable
[out] | none
Return values
none

Definition at line 1144 of file gd32f3x0_usart.c.

1145 {
1146 USART_REG_VAL(usart_periph, inttype) &= ~BIT(USART_BIT_POS(inttype));
1147 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f3x0_usart.h:176
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f3x0_usart.h:175
void usart_interrupt_enable | ( | uint32_t | usart_periph,
 |  | uint32_t | inttype
 | ) |  |

enable USART interrupt

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] inttype interrupt type
  • USART_INT_IDLE: idle interrupt
  • USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt enable interrupt
  • USART_INT_TC: transmission complete interrupt
  • USART_INT_TBE: transmit data register empty interrupt
  • USART_INT_PERR: parity error interrupt
  • USART_INT_AM: address match interrupt
  • USART_INT_RT: receiver timeout interrupt
  • USART_INT_EB: end of block interrupt
  • USART_INT_LBD: LIN break detection interrupt
  • USART_INT_ERR: error interrupt enable in multibuffer communication
  • USART_INT_CTS: CTS interrupt
  • USART_INT_WU: wakeup from deep-sleep mode interrupt
  • USART_INT_RFF: receive FIFO full interrupt enable
[out] | none
Return values
none

Definition at line 1118 of file gd32f3x0_usart.c.

1119 {
1120 USART_REG_VAL(usart_periph, inttype) |= BIT(USART_BIT_POS(inttype));
1121 }
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f3x0_usart.h:176
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f3x0_usart.h:175
void usart_interrupt_flag_clear | ( | uint32_t | usart_periph,
 |  | uint32_t | flag
 | ) |  |

clear USART interrupt flag

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] flag USART interrupt flag
  • USART_INT_FLAG_PERR: parity error flag
  • USART_INT_FLAG_FERR: frame error flag
  • USART_INT_FLAG_NERR: noise detected flag
  • USART_INT_FLAG_ORERR:overrun error flag
  • USART_INT_FLAG_IDLE: idle line detected flag
  • USART_INT_FLAG_TC: transmission complete flag
  • USART_INT_FLAG_LBD: LIN break detected flag
  • USART_INT_FLAG_CTS: CTS change flag
  • USART_INT_FLAG_RT: receiver timeout flag
  • USART_INT_FLAG_EB: end of block flag
  • USART_INT_FLAG_AM: address match flag
  • USART_INT_FLAG_WU: wakeup from deep-sleep mode flag
[out] | none
Return values
none

Definition at line 1223 of file gd32f3x0_usart.c.

1224 {
1225 USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(flag));
1226 }
USART_BIT_POS2
#define USART_BIT_POS2(val)
Definition: gd32f3x0_usart.h:180
USART_INTC
#define USART_INTC(usartx)
Definition: gd32f3x0_usart.h:30
FlagStatus usart_interrupt_flag_get | ( | uint32_t | usart_periph,
 |  | uint32_t | int_flag
 | ) |  |

get USART interrupt and flag status

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] int_flag interrupt and flag type, refer to usart_interrupt_flag_enum
  • USART_INT_FLAG_EB: end of block interrupt and flag
  • USART_INT_FLAG_RT: receiver timeout interrupt and flag
  • USART_INT_FLAG_AM: address match interrupt and flag
  • USART_INT_FLAG_PERR: parity error interrupt and flag
  • USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag
  • USART_INT_FLAG_TC: transmission complete interrupt and flag
  • USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag
  • USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag
  • USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag
  • USART_INT_FLAG_LBD: LIN break detected interrupt and flag
  • USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt and flag
  • USART_INT_FLAG_CTS: CTS interrupt and flag
  • USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag
  • USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error
  • USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag
  • USART_INT_FLAG_RFF: receive FIFO full interrupt and flag
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 1189 of file gd32f3x0_usart.c.

1190 {
1191 uint32_t intenable = 0U, flagstatus = 0U;
1192 /* get the interrupt enable bit status */
1193 intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)));
1194 /* get the corresponding flag bit status */
1195 flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
1196
1197 if(flagstatus && intenable){
1198 return SET;
1199 }else{
1200 return RESET;
1201 }
1202 }
USART_BIT_POS2
#define USART_BIT_POS2(val)
Definition: gd32f3x0_usart.h:180
USART_REG_VAL2
#define USART_REG_VAL2(usartx, offset)
Definition: gd32f3x0_usart.h:179
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f3x0_usart.h:176
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f3x0_usart.h:175
void usart_invert_config | ( | uint32_t | usart_periph,
 |  | usart_invert_enum | invertpara
 | ) |  |

USART inverted configure.

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] | invertpara | refer to usart_invert_enum
[out] | none
Return values
none

Definition at line 231 of file gd32f3x0_usart.c.

232 {
233 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
234 /* inverted or not the specified signal */
235 switch(invertpara){
236 case USART_DINV_ENABLE:
237 USART_CTL1(usart_periph) |= USART_CTL1_DINV;
238 break;
239 case USART_DINV_DISABLE:
240 USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV);
241 break;
242 case USART_TXPIN_DISABLE:
243 USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV);
244 break;
245 case USART_RXPIN_DISABLE:
246 USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV);
247 break;
248 case USART_SWAP_DISABLE:
249 USART_CTL1(usart_periph) &= ~(USART_CTL1_STRP);
250 break;
251 case USART_TXPIN_ENABLE:
252 USART_CTL1(usart_periph) |= USART_CTL1_TINV;
253 break;
254 case USART_RXPIN_ENABLE:
255 USART_CTL1(usart_periph) |= USART_CTL1_RINV;
256 break;
257 case USART_SWAP_ENABLE:
258 USART_CTL1(usart_periph) |= USART_CTL1_STRP;
259 break;
260 default:
261 break;
262 }
263 }
USART_DINV_DISABLE
Definition: gd32f3x0_usart.h:271
USART_CTL1_TINV
#define USART_CTL1_TINV
Definition: gd32f3x0_usart.h:70
USART_CTL1_RINV
#define USART_CTL1_RINV
Definition: gd32f3x0_usart.h:69
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_TXPIN_ENABLE
Definition: gd32f3x0_usart.h:273
USART_CTL1_STRP
#define USART_CTL1_STRP
Definition: gd32f3x0_usart.h:68
USART_CTL1_DINV
#define USART_CTL1_DINV
Definition: gd32f3x0_usart.h:71
USART_TXPIN_DISABLE
Definition: gd32f3x0_usart.h:274
USART_RXPIN_ENABLE
Definition: gd32f3x0_usart.h:276
USART_SWAP_DISABLE
Definition: gd32f3x0_usart.h:280
USART_DINV_ENABLE
Definition: gd32f3x0_usart.h:270
USART_SWAP_ENABLE
Definition: gd32f3x0_usart.h:279
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_RXPIN_DISABLE
Definition: gd32f3x0_usart.h:277
void usart_irda_lowpower_config | ( | uint32_t | usart_periph,
 |  | uint32_t | irlp
 | ) |  |

IrDA low-power configure.

Parameters
[in] | usart_periph | USARTx(x=0)
[in] irlp IrDA low-power or normal
  • USART_IRLP_LOW: low-power
  • USART_IRLP_NORMAL: normal
[out] | none
Return values
none

Definition at line 761 of file gd32f3x0_usart.c.

762 {
763 /* disable USART */
764 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
765
766 USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp);
767 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_IRLP
#define USART_CTL2_IRLP
Definition: gd32f3x0_usart.h:81
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_irda_mode_disable ( uint32_t usart_periph )

IrDA mode disable.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 744 of file gd32f3x0_usart.c.

745 {
746 /* disable USART */
747 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
748
749 USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN);
750 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_IREN
#define USART_CTL2_IREN
Definition: gd32f3x0_usart.h:80
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_irda_mode_enable ( uint32_t usart_periph )

IrDA mode enable.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 730 of file gd32f3x0_usart.c.

731 {
732 /* disable USART */
733 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
734
735 USART_CTL2(usart_periph) |= USART_CTL2_IREN;
736 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_IREN
#define USART_CTL2_IREN
Definition: gd32f3x0_usart.h:80
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_lin_break_dection_length_config | ( | uint32_t | usart_periph,
 |  | uint32_t | lblen
 | ) |  |

LIN break detection length.

Parameters
[in] | usart_periph | USARTx(x=0)
[in] lblen LIN break detection length
  • USART_LBLEN_10B: 10 bits break detection
  • USART_LBLEN_11B: 11 bits break detection
[out] | none
Return values
none

Definition at line 511 of file gd32f3x0_usart.c.

512 {
513 /* disable USART */
514 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
515
516 USART_CTL1(usart_periph) |= USART_CTL1_LBLEN & (lblen);
517 }
USART_CTL1_LBLEN
#define USART_CTL1_LBLEN
Definition: gd32f3x0_usart.h:60
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_lin_mode_disable ( uint32_t usart_periph )

LIN mode disable.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 494 of file gd32f3x0_usart.c.

495 {
496 /* disable USART */
497 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
498
499 USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN);
500 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_LMEN
#define USART_CTL1_LMEN
Definition: gd32f3x0_usart.h:67
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_lin_mode_enable ( uint32_t usart_periph )

LIN mode enable.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 480 of file gd32f3x0_usart.c.

481 {
482 /* disable USART */
483 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
484
485 USART_CTL1(usart_periph) |= USART_CTL1_LMEN;
486 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_LMEN
#define USART_CTL1_LMEN
Definition: gd32f3x0_usart.h:67
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_mute_mode_disable ( uint32_t usart_periph )

mute mode disable

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 382 of file gd32f3x0_usart.c.

383 {
384 USART_CTL0(usart_periph) &= ~(USART_CTL0_MEN);
385 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_MEN
#define USART_CTL0_MEN
Definition: gd32f3x0_usart.h:50
void usart_mute_mode_enable ( uint32_t usart_periph )

mute mode enable

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 371 of file gd32f3x0_usart.c.

372 {
373 USART_CTL0(usart_periph) |= USART_CTL0_MEN;
374 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_MEN
#define USART_CTL0_MEN
Definition: gd32f3x0_usart.h:50
void usart_mute_mode_wakeup_config | ( | uint32_t | usart_periph,
 |  | uint32_t | wmethod
 | ) |  |

wakeup method in mute mode configure

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] wmethod two methods be used to enter or exit the mute mode
  • USART_WM_IDLE: idle line
  • USART_WM_ADDR: address mark
[out] | none
Return values
none

Definition at line 396 of file gd32f3x0_usart.c.

397 {
398 /* disable USART */
399 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
400
401 USART_CTL0(usart_periph) &= ~(USART_CTL0_WM);
402 USART_CTL0(usart_periph) |= wmethod;
403 }
USART_CTL0_WM
#define USART_CTL0_WM
Definition: gd32f3x0_usart.h:48
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_overrun_disable ( uint32_t usart_periph )

overrun function is disabled

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 284 of file gd32f3x0_usart.c.

285 {
286 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
287 /* disable overrun function */
288 USART_CTL2(usart_periph) |= USART_CTL2_OVRD;
289 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_OVRD
#define USART_CTL2_OVRD
Definition: gd32f3x0_usart.h:91
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_overrun_enable ( uint32_t usart_periph )

overrun function is enabled

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 271 of file gd32f3x0_usart.c.

272 {
273 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
274 /* enable overrun function */
275 USART_CTL2(usart_periph) &= ~(USART_CTL2_OVRD);
276 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_OVRD
#define USART_CTL2_OVRD
Definition: gd32f3x0_usart.h:91
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_oversample_config | ( | uint32_t | usart_periph,
 |  | uint32_t | oversamp
 | ) |  |

configure the USART oversample mode

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] oversamp oversample value
  • USART_OVSMOD_8: oversampling by 8
  • USART_OVSMOD_16: oversampling by 16
[out] | none
Return values
none

Definition at line 300 of file gd32f3x0_usart.c.

301 {
302 /* disable USART */
303 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
304 /* clear OVSMOD bit */
305 USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD);
306 USART_CTL0(usart_periph) |= oversamp;
307 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_OVSMOD
#define USART_CTL0_OVSMOD
Definition: gd32f3x0_usart.h:52
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_parity_config | ( | uint32_t | usart_periph,
 |  | uint32_t | paritycfg
 | ) |  |

configure USART parity

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] paritycfg USART parity configure
  • USART_PM_NONE: no parity
  • USART_PM_ODD: odd parity
  • USART_PM_EVEN: even parity
[out] | none
Return values
none

Definition at line 81 of file gd32f3x0_usart.c.

82 {
83 /* disable USART */
84 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
85 /* clear USART_CTL0 PM,PCEN bits */
86 USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN);
87 /* configure USART parity mode */
88 USART_CTL0(usart_periph) |= paritycfg;
89 }
USART_CTL0_PM
#define USART_CTL0_PM
Definition: gd32f3x0_usart.h:46
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_PCEN
#define USART_CTL0_PCEN
Definition: gd32f3x0_usart.h:47
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_prescaler_config | ( | uint32_t | usart_periph,
 |  | uint32_t | psc
 | ) |  |

configure the peripheral clock prescaler in USART IrDA low-power mode

Parameters
[in] | usart_periph | USARTx(x=0)
[in] | psc | 0x00-0xFF
[out] | none
Return values
none

Definition at line 776 of file gd32f3x0_usart.c.

777 {
778 /* disable USART */
779 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
780 USART_GP(usart_periph) &= ~(USART_GP_PSC);
781 USART_GP(usart_periph) |= psc;
782 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_GP
#define USART_GP(usartx)
Definition: gd32f3x0_usart.h:26
USART_GP_PSC
#define USART_GP_PSC
Definition: gd32f3x0_usart.h:104
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_receive_config | ( | uint32_t | usart_periph,
 |  | uint32_t | rxconfig
 | ) |  |

configure USART receiver

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] rxconfig enable or disable USART receiver
  • USART_RECEIVE_ENABLE: enable USART reception
  • USART_RECEIVE_DISABLE: disable USART reception
[out] | none
Return values
none

Definition at line 177 of file gd32f3x0_usart.c.

178 {
179 USART_CTL0(usart_periph) &= ~USART_CTL0_REN;
180 /* configure receiver mode */
181 USART_CTL0(usart_periph) |= rxconfig;
182 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_REN
#define USART_CTL0_REN
Definition: gd32f3x0_usart.h:39
uint8_t usart_receive_fifo_counter_number ( uint32_t usart_periph )

read receive FIFO counter number

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
receive FIFO counter number

Definition at line 1027 of file gd32f3x0_usart.c.

1028 {
1029 return (uint8_t)(GET_BITS(USART_RFCS(usart_periph), 12U, 14U));
1030 }
USART_RFCS
#define USART_RFCS(usartx)
Definition: gd32f3x0_usart.h:33
void usart_receive_fifo_disable ( uint32_t usart_periph )

receive FIFO disable

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 1016 of file gd32f3x0_usart.c.

1017 {
1018 USART_RFCS(usart_periph) &= ~(USART_RFCS_RFEN);
1019 }
USART_RFCS
#define USART_RFCS(usartx)
Definition: gd32f3x0_usart.h:33
USART_RFCS_RFEN
#define USART_RFCS_RFEN
Definition: gd32f3x0_usart.h:164
void usart_receive_fifo_enable ( uint32_t usart_periph )

receive FIFO enable

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 1005 of file gd32f3x0_usart.c.

1006 {
1007 USART_RFCS(usart_periph) |= USART_RFCS_RFEN;
1008 }
USART_RFCS
#define USART_RFCS(usartx)
Definition: gd32f3x0_usart.h:33
USART_RFCS_RFEN
#define USART_RFCS_RFEN
Definition: gd32f3x0_usart.h:164
void usart_receiver_timeout_config | ( | uint32_t | usart_periph,
 |  | uint32_t | rtimeout
 | ) |  |

receiver timeout threshold configure

Parameters
[in] | usart_periph | USARTx(x=0)
[in] | rtimeout | 0x000000-0xFFFFFF, receiver timeout value in terms of number of baud clocks
[out] | none
Return values
none

Definition at line 468 of file gd32f3x0_usart.c.

469 {
470 USART_RT(usart_periph) &= ~(USART_RT_RT);
471 USART_RT(usart_periph) |= rtimeout;
472 }
USART_RT_RT
#define USART_RT_RT
Definition: gd32f3x0_usart.h:108
USART_RT
#define USART_RT(usartx)
Definition: gd32f3x0_usart.h:27
void usart_receiver_timeout_disable ( uint32_t usart_periph )

receiver timeout disable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 456 of file gd32f3x0_usart.c.

457 {
458 USART_CTL1(usart_periph) &= ~(USART_CTL1_RTEN);
459 }
USART_CTL1_RTEN
#define USART_CTL1_RTEN
Definition: gd32f3x0_usart.h:75
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
void usart_receiver_timeout_enable ( uint32_t usart_periph )

receiver timeout enable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 445 of file gd32f3x0_usart.c.

446 {
447 USART_CTL1(usart_periph) |= USART_CTL1_RTEN;
448 }
USART_CTL1_RTEN
#define USART_CTL1_RTEN
Definition: gd32f3x0_usart.h:75
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
void usart_reception_error_dma_disable ( uint32_t usart_periph )

disable DMA on reception error

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 936 of file gd32f3x0_usart.c.

937 {
938 /* disable USART */
939 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
940
941 USART_CTL2(usart_periph) |= USART_CTL2_DDRE;
942 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2_DDRE
#define USART_CTL2_DDRE
Definition: gd32f3x0_usart.h:92
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_reception_error_dma_enable ( uint32_t usart_periph )

enable DMA on reception error

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 950 of file gd32f3x0_usart.c.

951 {
952 /* disable USART */
953 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
954
955 USART_CTL2(usart_periph) &= ~(USART_CTL2_DDRE);
956 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2_DDRE
#define USART_CTL2_DDRE
Definition: gd32f3x0_usart.h:92
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_rs485_driver_disable ( uint32_t usart_periph )

RS485 driver disable.

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 840 of file gd32f3x0_usart.c.

841 {
842 /* disable USART */
843 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
844
845 USART_CTL2(usart_periph) &= ~(USART_CTL2_DEM);
846 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_DEM
#define USART_CTL2_DEM
Definition: gd32f3x0_usart.h:93
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_rs485_driver_enable ( uint32_t usart_periph )

RS485 driver enable.

Parameters
[in] | usart_periph | USARTx(x=0,1)
[out] | none
Return values
none

Definition at line 826 of file gd32f3x0_usart.c.

827 {
828 /* disable USART */
829 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
830
831 USART_CTL2(usart_periph) |= USART_CTL2_DEM;
832 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_DEM
#define USART_CTL2_DEM
Definition: gd32f3x0_usart.h:93
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_sample_bit_config | ( | uint32_t | usart_periph,
 |  | uint32_t | osb
 | ) |  |

sample bit method configure

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] osb sample bit
  • USART_OSB_1BIT: 1 bit
  • USART_OSB_3BIT: 3 bits
[out] | none
Return values
none

Definition at line 318 of file gd32f3x0_usart.c.

319 {
320 /* disable USART */
321 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
322
323 USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB);
324 USART_CTL2(usart_periph) |= osb;
325 }
USART_CTL2_OSB
#define USART_CTL2_OSB
Definition: gd32f3x0_usart.h:90
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_smartcard_autoretry_config | ( | uint32_t | usart_periph,
 |  | uint32_t | scrtnum
 | ) |  |

smartcard auto-retry number configure

Parameters
[in] | usart_periph | USARTx(x=0)
[in] | scrtnum | 0x0-0x7, smartcard auto-retry number
[out] | none
Return values
none

Definition at line 694 of file gd32f3x0_usart.c.

695 {
696 /* disable USART */
697 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
698 USART_CTL2(usart_periph) &= ~(USART_CTL2_SCRTNUM);
699 USART_CTL2(usart_periph) |= (USART_CTL2_SCRTNUM & (scrtnum << 17));
700 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_SCRTNUM
#define USART_CTL2_SCRTNUM
Definition: gd32f3x0_usart.h:95
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_smartcard_mode_disable ( uint32_t usart_periph )

smartcard mode disable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 622 of file gd32f3x0_usart.c.

623 {
624 /* disable USART */
625 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
626
627 USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN);
628 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_SCEN
#define USART_CTL2_SCEN
Definition: gd32f3x0_usart.h:84
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_smartcard_mode_early_nack_disable ( uint32_t usart_periph )

early NACK disable in smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 719 of file gd32f3x0_usart.c.

720 {
721 USART_RFCS(usart_periph) &= ~USART_RFCS_ELNACK;
722 }
USART_RFCS
#define USART_RFCS(usartx)
Definition: gd32f3x0_usart.h:33
USART_RFCS_ELNACK
#define USART_RFCS_ELNACK
Definition: gd32f3x0_usart.h:163
void usart_smartcard_mode_early_nack_enable ( uint32_t usart_periph )

early NACK enable in smartcard mode

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 708 of file gd32f3x0_usart.c.

709 {
710 USART_RFCS(usart_periph) |= USART_RFCS_ELNACK;
711 }
USART_RFCS
#define USART_RFCS(usartx)
Definition: gd32f3x0_usart.h:33
USART_RFCS_ELNACK
#define USART_RFCS_ELNACK
Definition: gd32f3x0_usart.h:163
void usart_smartcard_mode_enable ( uint32_t usart_periph )

smartcard mode enable

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 608 of file gd32f3x0_usart.c.

609 {
610 /* disable USART */
611 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
612
613 USART_CTL2(usart_periph) |= USART_CTL2_SCEN;
614 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_SCEN
#define USART_CTL2_SCEN
Definition: gd32f3x0_usart.h:84
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_smartcard_mode_nack_disable ( uint32_t usart_periph )

NACK disable in smartcard mode.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 650 of file gd32f3x0_usart.c.

651 {
652 /* disable USART */
653 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
654
655 USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN);
656 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_NKEN
#define USART_CTL2_NKEN
Definition: gd32f3x0_usart.h:83
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_smartcard_mode_nack_enable ( uint32_t usart_periph )

NACK enable in smartcard mode.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 636 of file gd32f3x0_usart.c.

637 {
638 /* disable USART */
639 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
640
641 USART_CTL2(usart_periph) |= USART_CTL2_NKEN;
642 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_NKEN
#define USART_CTL2_NKEN
Definition: gd32f3x0_usart.h:83
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_stop_bit_set | ( | uint32_t | usart_periph,
 |  | uint32_t | stblen
 | ) |  |

configure USART stop bit length

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] stblen USART stop bit configure
  • USART_STB_1BIT: 1 bit
  • USART_STB_0_5BIT: 0.5bit
  • USART_STB_2BIT: 2 bits
  • USART_STB_1_5BIT: 1.5bit
[out] | none
Return values
none

Definition at line 121 of file gd32f3x0_usart.c.

122 {
123 /* disable USART */
124 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
125 /* clear USART_CTL1 STB bits */
126 USART_CTL1(usart_periph) &= ~USART_CTL1_STB;
127 USART_CTL1(usart_periph) |= stblen;
128 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_STB
#define USART_CTL1_STB
Definition: gd32f3x0_usart.h:66
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
void usart_synchronous_clock_config | ( | uint32_t | usart_periph,
 |  | uint32_t | clen,
 |  | uint32_t | cph,
 |  | uint32_t | cpl
 | ) |  |

configure USART synchronous mode parameters

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] clen last bit clock pulse
  • USART_CLEN_NONE: clock pulse of the last data bit (MSB) is not output to the CK pin
  • USART_CLEN_EN: clock pulse of the last data bit (MSB) is output to the CK pin
[in] cph clock phase
  • USART_CPH_1CK: first clock transition is the first data capture edge
  • USART_CPH_2CK: second clock transition is the first data capture edge
[in] cpl clock polarity
  • USART_CPL_LOW: steady low value on CK pin
  • USART_CPL_HIGH: steady high value on CK pin
[out] | none
Return values
none

Definition at line 590 of file gd32f3x0_usart.c.

591 {
592 /* disable USART */
593 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
594 /* reset USART_CTL1 CLEN,CPH,CPL bits */
595 USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL);
596
597 USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen);
598 USART_CTL1(usart_periph) |= (USART_CTL1_CPH & cph);
599 USART_CTL1(usart_periph) |= (USART_CTL1_CPL & cpl);
600 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_CTL1_CLEN
#define USART_CTL1_CLEN
Definition: gd32f3x0_usart.h:62
USART_CTL1_CPH
#define USART_CTL1_CPH
Definition: gd32f3x0_usart.h:63
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL1_CPL
#define USART_CTL1_CPL
Definition: gd32f3x0_usart.h:64
void usart_transmit_config | ( | uint32_t | usart_periph,
 |  | uint32_t | txconfig
 | ) |  |

configure USART transmitter

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] txconfig enable or disable USART transmitter
  • USART_TRANSMIT_ENABLE: enable USART transmission
  • USART_TRANSMIT_DISABLE: enable USART transmission
[out] | none
Return values
none

Definition at line 161 of file gd32f3x0_usart.c.

162 {
163 USART_CTL0(usart_periph) &= ~USART_CTL0_TEN;
164 /* configure transfer mode */
165 USART_CTL0(usart_periph) |= txconfig;
166 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_TEN
#define USART_CTL0_TEN
Definition: gd32f3x0_usart.h:40
void usart_wakeup_disable ( uint32_t usart_periph )

USART be not able to wake up the MCU from deep-sleep mode.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 975 of file gd32f3x0_usart.c.

976 {
977 USART_CTL0(usart_periph) &= ~(USART_CTL0_UESM);
978 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UESM
#define USART_CTL0_UESM
Definition: gd32f3x0_usart.h:38
void usart_wakeup_enable ( uint32_t usart_periph )

USART be able to wake up the MCU from deep-sleep mode.

Parameters
[in] | usart_periph | USARTx(x=0)
[out] | none
Return values
none

Definition at line 964 of file gd32f3x0_usart.c.

965 {
966 USART_CTL0(usart_periph) |= USART_CTL0_UESM;
967 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_UESM
#define USART_CTL0_UESM
Definition: gd32f3x0_usart.h:38
void usart_wakeup_mode_config | ( | uint32_t | usart_periph,
 |  | uint32_t | wum
 | ) |  |

wakeup mode from deep-sleep mode

Parameters
[in] | usart_periph | USARTx(x=0)
[in] wum wakeup mode
  • USART_WUM_ADDR: WUF active on address match
  • USART_WUM_STARTB: WUF active on start bit
  • USART_WUM_RBNE: WUF active on RBNE
[out] | none
Return values
none

Definition at line 990 of file gd32f3x0_usart.c.

991 {
992 /* disable USART */
993 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
994 /* reset WUM bit */
995 USART_CTL2(usart_periph) &= ~(USART_CTL2_WUM);
996 USART_CTL2(usart_periph) |= USART_CTL2_WUM & (wum);
997 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL2_WUM
#define USART_CTL2_WUM
Definition: gd32f3x0_usart.h:96
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
void usart_word_length_set | ( | uint32_t | usart_periph,
 |  | uint32_t | wlen
 | ) |  |

configure USART word length

Parameters
[in] | usart_periph | USARTx(x=0,1)
[in] wlen USART word length configure
  • USART_WL_8BIT: 8 bits
  • USART_WL_9BIT: 9 bits
[out] | none
Return values
none

Definition at line 100 of file gd32f3x0_usart.c.

101 {
102 /* disable USART */
103 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
104 /* clear USART_CTL0 WL bit */
105 USART_CTL0(usart_periph) &= ~USART_CTL0_WL;
106 /* configure USART word length */
107 USART_CTL0(usart_periph) |= wlen;
108 }
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
USART_CTL0_WL
#define USART_CTL0_WL
Definition: gd32f3x0_usart.h:49
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_wwdgt.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
Functions
gd32f3x0_wwdgt.c File Reference

WWDGT driver. More...

#include "gd32f3x0_wwdgt.h"
#include "gd32f3x0_rcu.h"

Go to the source code of this file.

Functions

void | wwdgt_deinit (void)
reset the window watchdog timer configuration More...
void | wwdgt_counter_update (uint16_t counter_value)
configure the window watchdog timer counter value More...
void | wwdgt_enable (void)
start the window watchdog timer counter More...
void | wwdgt_config (uint16_t counter, uint16_t window, uint32_t prescaler)
configure counter value, window value, and prescaler divider value More...
void | wwdgt_interrupt_enable (void)
enable early wakeup interrupt of WWDGT More...
FlagStatus | wwdgt_flag_get (void)
check early wakeup interrupt state of WWDGT More...
void | wwdgt_flag_clear (void)
clear early wakeup interrupt state of WWDGT More...

Detailed Description

WWDGT driver.

Definition in file gd32f3x0_wwdgt.c.

Function Documentation

void wwdgt_config | ( | uint16_t | counter,
 |  | uint16_t | window,
 |  | uint32_t | prescaler
 | ) |  |

configure counter value, window value, and prescaler divider value

Parameters
[in] | counter | 0x00 - 0x7F
[in] | window | 0x00 - 0x7F
[in] prescaler wwdgt prescaler value
  • WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
  • WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
  • WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
  • WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
[out] | none
Return values
none

Definition at line 66 of file gd32f3x0_wwdgt.c.

67 {
68 uint32_t reg_cfg = 0x0U, reg_ctl = 0x0U;
69
70 /* clear WIN and PSC bits, clear CNT bit */
71 reg_cfg = WWDGT_CFG &(~((uint32_t)WWDGT_CFG_WIN|(uint32_t)WWDGT_CFG_PSC));
72 reg_ctl = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT);
73
74 /* configure WIN and PSC bits, configure CNT bit */
75 reg_cfg |= (uint32_t)(CFG_WIN(window));
76 reg_cfg |= (uint32_t)(prescaler);
77 reg_ctl |= (uint32_t)(CTL_CNT(counter));
78
79 WWDGT_CFG = (uint32_t)reg_cfg;
80 WWDGT_CTL = (uint32_t)reg_ctl;
81 }
CTL_CNT
#define CTL_CNT(regval)
Definition: gd32f3x0_wwdgt.h:40
WWDGT_CFG_WIN
#define WWDGT_CFG_WIN
Definition: gd32f3x0_wwdgt.h:31
WWDGT_CFG
#define WWDGT_CFG
Definition: gd32f3x0_wwdgt.h:22
WWDGT_CTL
#define WWDGT_CTL
Definition: gd32f3x0_wwdgt.h:21
CFG_WIN
#define CFG_WIN(regval)
Definition: gd32f3x0_wwdgt.h:43
WWDGT_CTL_CNT
#define WWDGT_CTL_CNT
Definition: gd32f3x0_wwdgt.h:27
WWDGT_CFG_PSC
#define WWDGT_CFG_PSC
Definition: gd32f3x0_wwdgt.h:32
void wwdgt_counter_update ( uint16_t counter_value )

configure the window watchdog timer counter value

Parameters
[in] | counter_value | 0x00 - 0x7F
[out] | none
Return values
none

Definition at line 33 of file gd32f3x0_wwdgt.c.

34 {
35 uint32_t reg = 0x0U;
36
37 reg = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT);
38 reg |= (uint32_t)(CTL_CNT(counter_value));
39
40 WWDGT_CTL = (uint32_t)reg;
41 }
CTL_CNT
#define CTL_CNT(regval)
Definition: gd32f3x0_wwdgt.h:40
WWDGT_CTL
#define WWDGT_CTL
Definition: gd32f3x0_wwdgt.h:21
WWDGT_CTL_CNT
#define WWDGT_CTL_CNT
Definition: gd32f3x0_wwdgt.h:27
void wwdgt_deinit ( void )

reset the window watchdog timer configuration

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 21 of file gd32f3x0_wwdgt.c.

22 {
23 rcu_periph_reset_enable(RCU_WWDGTRST);
24 rcu_periph_reset_disable(RCU_WWDGTRST);
25 }
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
RCU_WWDGTRST
Definition: gd32f3x0_rcu.h:347
void wwdgt_enable ( void )

start the window watchdog timer counter

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 49 of file gd32f3x0_wwdgt.c.

50 {
51 WWDGT_CTL |= WWDGT_CTL_WDGTEN;
52 }
WWDGT_CTL_WDGTEN
#define WWDGT_CTL_WDGTEN
Definition: gd32f3x0_wwdgt.h:28
WWDGT_CTL
#define WWDGT_CTL
Definition: gd32f3x0_wwdgt.h:21
void wwdgt_flag_clear ( void )

clear early wakeup interrupt state of WWDGT

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 114 of file gd32f3x0_wwdgt.c.

115 {
116 WWDGT_STAT &= (uint32_t)(~(uint32_t)WWDGT_STAT_EWIF);
117 }
WWDGT_STAT_EWIF
#define WWDGT_STAT_EWIF
Definition: gd32f3x0_wwdgt.h:36
WWDGT_STAT
#define WWDGT_STAT
Definition: gd32f3x0_wwdgt.h:23
FlagStatus wwdgt_flag_get ( void )

check early wakeup interrupt state of WWDGT

Parameters
[in] | none
[out] | none
Return values
FlagStatus SET or RESET

Definition at line 100 of file gd32f3x0_wwdgt.c.

101 {
102 if(WWDGT_STAT & WWDGT_STAT_EWIF){
103 return SET;
104 }
105 return RESET;
106 }
WWDGT_STAT_EWIF
#define WWDGT_STAT_EWIF
Definition: gd32f3x0_wwdgt.h:36
WWDGT_STAT
#define WWDGT_STAT
Definition: gd32f3x0_wwdgt.h:23
void wwdgt_interrupt_enable ( void )

enable early wakeup interrupt of WWDGT

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 89 of file gd32f3x0_wwdgt.c.

90 {
91 WWDGT_CFG |= WWDGT_CFG_EWIE;
92 }
WWDGT_CFG
#define WWDGT_CFG
Definition: gd32f3x0_wwdgt.h:22
WWDGT_CFG_EWIE
#define WWDGT_CFG_EWIE
Definition: gd32f3x0_wwdgt.h:33
Generated on Tue Jun 27 2017 14:36:13 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver Directory Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
GD32F3x0_usbfs_driver Directory Reference

Directories

directory | Include
directory | Source


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include Directory Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
Include Directory Reference

Files

file | usb_core.h [code]
USB core driver header file.
file | usb_defines.h [code]
USB core defines.
file | usb_regs.h [code]
USB FS cell registers definition and handle macros.
file | usb_std.h [code]
USB 2.0 standard defines.
file | usbd_core.h [code]
USB device mode core driver header file.
file | usbd_int.h [code]
USB device mode interrupt handler header file.
file | usbd_std.h [code]
USB 2.0 standard defines.
file | usbh_core.h [code]
header file for usbh_core.c
file | usbh_ctrl.h [code]
header file for usbh_ctrl.c
file | usbh_hcs.h [code]
header file for usbh_hcs.c
file | usbh_int.h [code]
USB host mode interrupt handler header file.
file | usbh_std.h [code]
header file for usbh_std.c


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_core.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
Data Structures | Macros | Enumerations | Functions
usb_core.h File Reference

USB core driver header file. More...

#include "usb_conf.h"
#include "usb_regs.h"
#include "usb_defines.h"

Go to the source code of this file.

Data Structures

struct | usb_core_cfgs_struct
struct | usb_ep_struct
struct | usb_device_req_struct
struct | dcd_dev_struct
struct | usb_hostchannel_struct
struct | hcd_dev_struct
struct | usb_core_handle_struct

Macros

#define | USB_MAX_EP0_SIZE 64U /* endpoint 0 max packet size */
#define | RX_MAX_DATA_LENGTH 512U /* host rx buffer max data length */
#define | HC_MAX_PACKET_COUNT 140U /* host channel max packet count */
#define | USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT
#define | USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U)

Enumerations

enum | usb_status_enum { USB_OK = 0, USB_FAIL }
enum hc_status_enum {
HC_IDLE = 0, HC_XF, HC_HALTED, HC_NAK,
HC_NYET, HC_STALL, HC_TRACERR, HC_BBERR,
HC_DTGERR
}
enum urb_state_enum {
URB_IDLE = 0, URB_DONE, URB_NOTREADY, URB_ERROR,
URB_STALL, URB_PING
}
enum | usbd_status_enum { USBD_OK = 0, USBD_BUSY, USBD_FAIL }
enum usbd_control_state_enum {
USB_CTRL_IDLE = 0, USB_CTRL_SETUP, USB_CTRL_DATA_IN, USB_CTRL_DATA_OUT,
USB_CTRL_STATUS_IN, USB_CTRL_STATUS_OUT, USB_CTRL_STALL
}
enum | usb_dir_enum { USB_RX = 0, USB_TX }

Functions

usb_status_enum | usb_core_init (usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation More...
usb_status_enum | usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters More...
void * | usb_fifo_read (uint8_t *dest, uint16_t len)
read a packet from the Rx FIFO associated with the endpoint More...
usb_status_enum | usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint More...
usb_status_enum | usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs More...
usb_status_enum | usb_rxfifo_flush (usb_core_handle_struct *pudev)
flush the entire Rx FIFO More...
usb_status_enum | usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device) More...

Detailed Description

USB core driver header file.

Definition in file usb_core.h.

Macro Definition Documentation

#define HC_MAX_PACKET_COUNT 140U /* host channel max packet count */

Definition at line 21 of file usb_core.h.

#define RX_MAX_DATA_LENGTH 512U /* host rx buffer max data length */

Definition at line 20 of file usb_core.h.

#define USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT

Definition at line 23 of file usb_core.h.

#define USB_MAX_EP0_SIZE 64U /* endpoint 0 max packet size */

Definition at line 19 of file usb_core.h.

#define USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U)

Definition at line 24 of file usb_core.h.

Enumeration Type Documentation

enum hc_status_enum
Enumerator
HC_IDLE
HC_XF
HC_HALTED
HC_NAK
HC_NYET
HC_STALL
HC_TRACERR
HC_BBERR
HC_DTGERR

Definition at line 34 of file usb_core.h.

35 {
36 HC_IDLE = 0, /* USB host channel idle status */
37 HC_XF, /* USB host channel transfer status */
38 HC_HALTED, /* USB host channel halted status */
39 HC_NAK, /* USB host channel nak status */
40 HC_NYET, /* USB host channel nyet status */
41 HC_STALL, /* USB host channel stall status */
42 HC_TRACERR, /* USB host channel tracerr status */
43 HC_BBERR, /* USB host channel bberr status */
44 HC_DTGERR, /* USB host channel dtgerr status */
45 }hc_status_enum;
HC_NYET
Definition: usb_core.h:40
HC_XF
Definition: usb_core.h:37
hc_status_enum
hc_status_enum
Definition: usb_core.h:34
HC_BBERR
Definition: usb_core.h:43
HC_IDLE
Definition: usb_core.h:36
HC_TRACERR
Definition: usb_core.h:42
HC_NAK
Definition: usb_core.h:39
HC_STALL
Definition: usb_core.h:41
HC_HALTED
Definition: usb_core.h:38
HC_DTGERR
Definition: usb_core.h:44
enum urb_state_enum
Enumerator
URB_IDLE
URB_DONE
URB_NOTREADY
URB_ERROR
URB_STALL
URB_PING

Definition at line 48 of file usb_core.h.

49 {
50 URB_IDLE = 0, /* USB URB idle status */
51 URB_DONE, /* USB URB done status */
52 URB_NOTREADY, /* USB URB notready status */
53 URB_ERROR, /* USB URB error status */
54 URB_STALL, /* USB URB stall status */
55 URB_PING /* USB URB ping status */
56 }urb_state_enum;
URB_STALL
Definition: usb_core.h:54
urb_state_enum
urb_state_enum
Definition: usb_core.h:48
URB_PING
Definition: usb_core.h:55
URB_IDLE
Definition: usb_core.h:50
URB_NOTREADY
Definition: usb_core.h:52
URB_ERROR
Definition: usb_core.h:53
URB_DONE
Definition: usb_core.h:51
enum usb_dir_enum
Enumerator
USB_RX
USB_TX

Definition at line 92 of file usb_core.h.

93 {
94 USB_RX = 0, /* receive direction type value */
95 USB_TX /* transmit direction type value */
96 }usb_dir_enum;
USB_TX
Definition: usb_core.h:95
USB_RX
Definition: usb_core.h:94
usb_dir_enum
usb_dir_enum
Definition: usb_core.h:92
enum usb_status_enum
Enumerator
USB_OK
USB_FAIL

Definition at line 27 of file usb_core.h.

28 {
29 USB_OK = 0, /* USB core OK status */
30 USB_FAIL /* USB core fail status */
31 }usb_status_enum;
USB_OK
Definition: usb_core.h:29
usb_status_enum
usb_status_enum
Definition: usb_core.h:27
USB_FAIL
Definition: usb_core.h:30
enum usbd_control_state_enum
Enumerator
USB_CTRL_IDLE
USB_CTRL_SETUP
USB_CTRL_DATA_IN
USB_CTRL_DATA_OUT
USB_CTRL_STATUS_IN
USB_CTRL_STATUS_OUT
USB_CTRL_STALL

Definition at line 80 of file usb_core.h.

81 {
82 USB_CTRL_IDLE = 0, /* USB control transfer idle state */
83 USB_CTRL_SETUP, /* USB control transfer setup state */
84 USB_CTRL_DATA_IN, /* USB control transfer data in state */
85 USB_CTRL_DATA_OUT, /* USB control transfer data out state */
86 USB_CTRL_STATUS_IN, /* USB control transfer status in state*/
87 USB_CTRL_STATUS_OUT, /* USB control transfer status out state */
88 USB_CTRL_STALL /* USB control transfer stall state */
89 }usbd_control_state_enum;
USB_CTRL_STATUS_OUT
Definition: usb_core.h:87
USB_CTRL_STATUS_IN
Definition: usb_core.h:86
USB_CTRL_DATA_IN
Definition: usb_core.h:84
USB_CTRL_STALL
Definition: usb_core.h:88
USB_CTRL_DATA_OUT
Definition: usb_core.h:85
USB_CTRL_SETUP
Definition: usb_core.h:83
USB_CTRL_IDLE
Definition: usb_core.h:82
usbd_control_state_enum
usbd_control_state_enum
Definition: usb_core.h:80
enum usbd_status_enum
Enumerator
USBD_OK
USBD_BUSY
USBD_FAIL

Definition at line 72 of file usb_core.h.

73 {
74 USBD_OK = 0, /* USB device ok status */
75 USBD_BUSY, /* USB device busy status */
76 USBD_FAIL, /* USB device fail stauts */
77 }usbd_status_enum;
USBD_OK
Definition: usb_core.h:74
usbd_status_enum
usbd_status_enum
Definition: usb_core.h:72
USBD_FAIL
Definition: usb_core.h:76
USBD_BUSY
Definition: usb_core.h:75

Function Documentation

usb_status_enum usb_core_init ( usb_core_handle_struct * pudev )

initializes the USB controller registers and prepares the core device mode or host mode operation

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
operation status

Definition at line 167 of file usb_core.c.

168 {
169 /* soft reset the core */
170 usb_core_reset(pudev);
171
172 /* active the transceiver and enable vbus sensing */
173 USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN;
174
175 /* set Tx FIFO empty level to half empty mode */
176 USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF;
177
178 #ifndef VBUS_SENSING_ENABLED
179 USB_GCCFG |= GCCFG_VBUSIG;
180 #endif /* VBUS_SENSING_ENABLED */
181
182 if(pudev->cfg.sof_output){
183 USB_GCCFG |= GCCFG_SOFOEN;
184 }
185
186 if (NULL != pudev->mdelay) {
187 pudev->mdelay(20U);
188 }
189
190
191 #ifdef USE_OTG_MODE
192 /* enable OTG features */
193 USB_GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP;
194 USB_OTG_EnableCommonInt(pudev);
195
196 #endif /* USE_OTG_MODE */
197
198 return USB_OK;
199 }
USB_GCCFG
#define USB_GCCFG
Definition: usb_regs.h:48
GAHBCS_TXFTH
#define GAHBCS_TXFTH
Definition: usb_regs.h:117
GCCFG_VBUSBCEN
#define GCCFG_VBUSBCEN
Definition: usb_regs.h:228
USB_GUSBCS
#define USB_GUSBCS
Definition: usb_regs.h:38
GCCFG_PWRON
#define GCCFG_PWRON
Definition: usb_regs.h:230
USB_OK
Definition: usb_core.h:29
TXFIFO_EMPTY_HALF
#define TXFIFO_EMPTY_HALF
Definition: usb_regs.h:504
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:217
GCCFG_SOFOEN
#define GCCFG_SOFOEN
Definition: usb_regs.h:227
usb_core_cfgs_struct::sof_output
uint8_t sof_output
Definition: usb_core.h:66
GCCFG_VBUSACEN
#define GCCFG_VBUSACEN
Definition: usb_regs.h:229
GCCFG_VBUSIG
#define GCCFG_VBUSIG
Definition: usb_regs.h:226
NULL
#define NULL
Definition: usb_defines.h:18
USB_GAHBCS
#define USB_GAHBCS
Definition: usb_regs.h:37
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:202
usb_status_enum usb_core_select | ( | usb_core_handle_struct * | pudev,
 |  | usb_core_id_enum | core_id
 | ) |  |

initialize core parameters

Parameters
[in] | pudev | pointer to usb device
[in] | core_id | USB core id
[out] | none
Return values
operation status

Definition at line 125 of file usb_core.c.

126 {
127 /* at startup the core is in FS mode */
128 pudev->cfg.core_speed = USB_CORE_SPEED_FULL;
129 pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE;
130
131 /* initialize the core parameters */
132 if (USB_FS_CORE_ID == core_id) {
133
134 pudev->cfg.core_id = USB_FS_CORE_ID;
135
136 /* set the host channel numbers */
137 pudev->cfg.host_channel_num = USBFS_MAX_HOST_CHANNELCOUNT;
138
139 /* set the device endpoint numbers */
140 pudev->cfg.dev_endp_num = USBFS_MAX_DEV_EPCOUNT;
141
142 /* fifo size is in terms of DWORD */
143 pudev->cfg.max_fifo_size = USBFS_MAX_FIFO_WORDLEN;
144
145 /* OTG_FS core use embedded physical layer */
146 pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY;
147
148 #ifdef USBFS_SOF_OUTPUT_ENABLED
149 pudev->cfg.sof_output = 1U;
150 #endif /* USBFS_SOF_OUTPUT_ENABLED */
151
152 #ifdef USBFS_LOW_PWR_MGMT_SUPPORT
153 pudev->cfg.low_power = 1U;
154 #endif /* USBFS_LOW_PWR_MGMT_SUPPORT */
155 }
156
157 return USB_OK;
158 }
USBFS_MAX_PACKET_SIZE
#define USBFS_MAX_PACKET_SIZE
Definition: usb_defines.h:24
usb_core_cfgs_struct::dev_endp_num
uint8_t dev_endp_num
Definition: usb_core.h:65
usb_core_cfgs_struct::max_packet_size
uint16_t max_packet_size
Definition: usb_core.h:68
USBFS_MAX_HOST_CHANNELCOUNT
#define USBFS_MAX_HOST_CHANNELCOUNT
Definition: usb_defines.h:25
USB_OK
Definition: usb_core.h:29
usb_core_cfgs_struct::phy_interface
uint8_t phy_interface
Definition: usb_core.h:63
USB_CORE_SPEED_FULL
#define USB_CORE_SPEED_FULL
Definition: usb_defines.h:22
usb_core_cfgs_struct::sof_output
uint8_t sof_output
Definition: usb_core.h:66
USB_CORE_EMBEDDED_PHY
#define USB_CORE_EMBEDDED_PHY
Definition: usb_defines.h:35
usb_core_cfgs_struct::core_speed
uint8_t core_speed
Definition: usb_core.h:62
usb_core_cfgs_struct::low_power
uint8_t low_power
Definition: usb_core.h:67
USB_FS_CORE_ID
Definition: usb_defines.h:89
USBFS_MAX_FIFO_WORDLEN
#define USBFS_MAX_FIFO_WORDLEN
Definition: usb_defines.h:27
USBFS_MAX_DEV_EPCOUNT
#define USBFS_MAX_DEV_EPCOUNT
Definition: usb_defines.h:26
usb_core_cfgs_struct::max_fifo_size
uint16_t max_fifo_size
Definition: usb_core.h:69
usb_core_cfgs_struct::core_id
uint8_t core_id
Definition: usb_core.h:61
usb_core_cfgs_struct::host_channel_num
uint8_t host_channel_num
Definition: usb_core.h:64
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:202
void* usb_fifo_read | ( | uint8_t * | dest,
 |  | uint16_t | len
 | ) |  |

read a packet from the Rx FIFO associated with the endpoint

Parameters
[in] | dest | pointer to destination buffer
[in] | len | packet length
[out] | none
Return values
void type pointer

Definition at line 102 of file usb_core.c.

103 {
104 uint32_t i = 0U;
105 uint32_t count32b = (len + 3U) / 4U;
106
107 __IO uint32_t *fifo = USB_FIFO(0U);
108
109 for (i = 0U; i < count32b; i++) {
110 *(__packed uint32_t *)dest = *fifo;
111
112 dest += 4U;
113 }
114
115 return ((void *)dest);
116 }
USB_FIFO
#define USB_FIFO(x)
Definition: usb_regs.h:93
usb_status_enum usb_fifo_write | ( | uint8_t * | src,
 |  | uint8_t | chep_num,
 |  | uint16_t | len
 | ) |  |

write a packet into the Tx FIFO associated with the endpoint

Parameters
[in] | src | pointer to source buffer
[in] | chep_num | channel or endpoint identifier which is in (0..3)
[in] | len | packet length
[out] | none
Return values
operation status

Definition at line 79 of file usb_core.c.

80 {
81 uint32_t count32b = 0U, i = 0U;
82 __IO uint32_t *fifo = USB_FIFO(chep_num);
83
84 count32b = (len + 3U) / 4U;
85
86 for (i = 0U; i < count32b; i++) {
87 *fifo = *((__packed uint32_t *)src);
88
89 src += 4U;
90 }
91
92 return USB_OK;
93 }
USB_OK
Definition: usb_core.h:29
USB_FIFO
#define USB_FIFO(x)
Definition: usb_regs.h:93
usb_status_enum usb_mode_set | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | mode
 | ) |  |

set operation mode (host or device)

Parameters
[in] | pudev | pointer to usb device
[in] mode operation mode which need to set
  • HOST_MODE
  • DEVICE_MODE
[out] | none
Return values
operation status

Definition at line 266 of file usb_core.c.

267 {
268 if (HOST_MODE == mode) {
269 USB_GUSBCS &= ~GUSBCS_FDM;
270 USB_GUSBCS |= GUSBCS_FHM;
271 } else if (DEVICE_MODE == mode) {
272 USB_GUSBCS &= ~GUSBCS_FHM;
273 USB_GUSBCS |= GUSBCS_FDM;
274 } else {
275 /* no operation */
276 }
277
278 if (NULL != pudev->mdelay) {
279 pudev->mdelay(50U);
280 }
281
282 return USB_OK;
283 }
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:48
USB_GUSBCS
#define USB_GUSBCS
Definition: usb_regs.h:38
GUSBCS_FDM
#define GUSBCS_FDM
Definition: usb_regs.h:123
USB_OK
Definition: usb_core.h:29
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:217
GUSBCS_FHM
#define GUSBCS_FHM
Definition: usb_regs.h:124
NULL
#define NULL
Definition: usb_defines.h:18
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:47
usb_status_enum usb_rxfifo_flush ( usb_core_handle_struct * pudev )

flush the entire Rx FIFO

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
operation status

Definition at line 236 of file usb_core.c.

237 {
238 uint32_t count = 0U;
239
240 USB_GRSTCTL = GRSTCTL_RXFF;
241
242 /* wait for Rx FIFO flush bit is set */
243 do {
244 if (++count > 200000U) {
245 break;
246 }
247 } while (USB_GRSTCTL & GRSTCTL_RXFF);
248
249 /* wait for 3 PHY clocks */
250 if (NULL != pudev->udelay) {
251 pudev->udelay(3U);
252 }
253
254 return USB_OK;
255 }
usb_core_handle_struct::udelay
void(* udelay)(const uint32_t usec)
Definition: usb_core.h:216
USB_OK
Definition: usb_core.h:29
GRSTCTL_RXFF
#define GRSTCTL_RXFF
Definition: usb_regs.h:138
NULL
#define NULL
Definition: usb_defines.h:18
USB_GRSTCTL
#define USB_GRSTCTL
Definition: usb_regs.h:39
usb_status_enum usb_txfifo_flush | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | fifo_num
 | ) |  |

flush a Tx FIFO or all Tx FIFOs

Parameters
[in] | pudev | pointer to usb device
[in] | fifo_num | FIFO number which is in (0..3)
[out] | none
Return values
operation status

Definition at line 208 of file usb_core.c.

209 {
210 uint32_t count = 0U;
211
212 USB_GRSTCTL &= ~GRSTCTL_TXFNUM;
213 USB_GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF;
214
215 /* wait for Tx FIFO flush bit is set */
216 do {
217 if (++count > 200000U) {
218 break;
219 }
220 } while (USB_GRSTCTL & GRSTCTL_TXFF);
221
222 /* wait for 3 PHY clocks */
223 if (NULL != pudev->udelay) {
224 pudev->udelay(3U);
225 }
226
227 return USB_OK;
228 }
GRSTCTL_TXFNUM
#define GRSTCTL_TXFNUM
Definition: usb_regs.h:136
usb_core_handle_struct::udelay
void(* udelay)(const uint32_t usec)
Definition: usb_core.h:216
USB_OK
Definition: usb_core.h:29
GRSTCTL_TXFF
#define GRSTCTL_TXFF
Definition: usb_regs.h:137
NULL
#define NULL
Definition: usb_defines.h:18
USB_GRSTCTL
#define USB_GRSTCTL
Definition: usb_regs.h:39
Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_defines.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
Macros | Enumerations
usb_defines.h File Reference

USB core defines. More...

#include "usb_conf.h"

Go to the source code of this file.

Macros

#define | NULL (void *)0
#define | USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */
#define | USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */
#define | USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */
#define | USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */
#define | USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */
#define | USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */
#define | USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */
#define | USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */
#define | USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */
#define | USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */
#define | USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */
#define | USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */
#define | DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */
#define | DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */
#define | DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */
#define | DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */
#define | GRSTATR_RPCKST_IN 2U /* IN data packet received */
#define | GRSTATR_RPCKST_IN_XFER_COMP 3U /* IN transfer completed (generates an interrupt if poped) */
#define | GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* data toggle error (generates an interrupt if poped) */
#define | GRSTATR_RPCKST_CH_HALTED 7U /* channel halted (generates an interrupt if poped) */
#define | DEVICE_MODE 0U /* USB core in device mode */
#define | HOST_MODE 1U /* USB core in host mode */
#define | OTG_MODE 2U /* USB core in OTG mode */
#define | USB_EPTYPE_CTRL 0U /* USB control endpoint type */
#define | USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */
#define | USB_EPTYPE_BULK 2U /* USB bulk endpoint type */
#define | USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */
#define | USB_EPTYPE_MASK 3U /* USB endpoint type mask */
#define | RXSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */
#define | RXSTAT_DATA_UPDT 2U /* OUT data packet received */
#define | RXSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */
#define | RXSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */
#define | RXSTAT_SETUP_UPDT 6U /* SETUP data packet received */
#define | DPID_DATA0 0U /* device endpoint data PID is DATA0 */
#define | DPID_DATA1 2U /* device endpoint data PID is DATA1 */
#define | DPID_DATA2 1U /* device endpoint data PID is DATA2 */
#define | DPID_MDATA 3U /* device endpoint data PID is MDATA */
#define | HC_PID_DATA0 0U /* host channel data PID is DATA0 */
#define | HC_PID_DATA2 1U /* host channel data PID is DATA2 */
#define | HC_PID_DATA1 2U /* host channel data PID is DATA1 */
#define | HC_PID_SETUP 3U /* host channel data PID is SETUP */
#define | HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */
#define | HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */
#define | HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */
#define | HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */
#define | HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */
#define | HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */
#define | HCCHAR_CTRL 0U /* control channel type */
#define | HCCHAR_ISOC 1U /* synchronous channel type */
#define | HCCHAR_BULK 2U /* bulk channel type */
#define | HCCHAR_INTR 3U /* interrupt channel type */

Enumerations

enum | usb_core_id_enum { USB_HS_CORE_ID = 0, USB_FS_CORE_ID = 1 }
enum | usb_speed_enum { USB_SPEED_UNKNOWN = 0, USB_SPEED_LOW, USB_SPEED_FULL, USB_SPEED_HIGH }

Detailed Description

USB core defines.

Definition in file usb_defines.h.

Macro Definition Documentation

#define DEVICE_MODE 0U /* USB core in device mode */

Definition at line 47 of file usb_defines.h.

#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */

Definition at line 63 of file usb_defines.h.

#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */

Definition at line 64 of file usb_defines.h.

#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */

Definition at line 65 of file usb_defines.h.

#define DPID_MDATA 3U /* device endpoint data PID is MDATA */

Definition at line 66 of file usb_defines.h.

#define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */

Definition at line 38 of file usb_defines.h.

#define DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */

Definition at line 40 of file usb_defines.h.

#define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */

Definition at line 37 of file usb_defines.h.

#define DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */

Definition at line 39 of file usb_defines.h.

#define GRSTATR_RPCKST_CH_HALTED 7U /* channel halted (generates an interrupt if poped) */

Definition at line 45 of file usb_defines.h.

#define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* data toggle error (generates an interrupt if poped) */

Definition at line 44 of file usb_defines.h.

#define GRSTATR_RPCKST_IN 2U /* IN data packet received */

Definition at line 42 of file usb_defines.h.

#define GRSTATR_RPCKST_IN_XFER_COMP 3U /* IN transfer completed (generates an interrupt if poped) */

Definition at line 43 of file usb_defines.h.

#define HC_PID_DATA0 0U /* host channel data PID is DATA0 */

Definition at line 68 of file usb_defines.h.

#define HC_PID_DATA1 2U /* host channel data PID is DATA1 */

Definition at line 70 of file usb_defines.h.

#define HC_PID_DATA2 1U /* host channel data PID is DATA2 */

Definition at line 69 of file usb_defines.h.

#define HC_PID_SETUP 3U /* host channel data PID is SETUP */

Definition at line 71 of file usb_defines.h.

#define HCCHAR_BULK 2U /* bulk channel type */

Definition at line 83 of file usb_defines.h.

#define HCCHAR_CTRL 0U /* control channel type */

Definition at line 81 of file usb_defines.h.

#define HCCHAR_INTR 3U /* interrupt channel type */

Definition at line 84 of file usb_defines.h.

#define HCCHAR_ISOC 1U /* synchronous channel type */

Definition at line 82 of file usb_defines.h.

#define HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */

Definition at line 77 of file usb_defines.h.

#define HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */

Definition at line 78 of file usb_defines.h.

#define HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */

Definition at line 79 of file usb_defines.h.

#define HOST_MODE 1U /* USB core in host mode */

Definition at line 48 of file usb_defines.h.

#define HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */

Definition at line 74 of file usb_defines.h.

#define HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */

Definition at line 73 of file usb_defines.h.

#define HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */

Definition at line 75 of file usb_defines.h.

#define NULL (void *)0

USB null marco value

Definition at line 18 of file usb_defines.h.

#define OTG_MODE 2U /* USB core in OTG mode */

Definition at line 49 of file usb_defines.h.

#define RXSTAT_DATA_UPDT 2U /* OUT data packet received */

Definition at line 58 of file usb_defines.h.

#define RXSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */

Definition at line 57 of file usb_defines.h.

#define RXSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */

Definition at line 60 of file usb_defines.h.

#define RXSTAT_SETUP_UPDT 6U /* SETUP data packet received */

Definition at line 61 of file usb_defines.h.

#define RXSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */

Definition at line 59 of file usb_defines.h.

#define USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */

Definition at line 35 of file usb_defines.h.

#define USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */

Definition at line 22 of file usb_defines.h.

#define USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */

Definition at line 21 of file usb_defines.h.

#define USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */

Definition at line 34 of file usb_defines.h.

#define USB_EPTYPE_BULK 2U /* USB bulk endpoint type */

Definition at line 53 of file usb_defines.h.

#define USB_EPTYPE_CTRL 0U /* USB control endpoint type */

Definition at line 51 of file usb_defines.h.

#define USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */

Definition at line 54 of file usb_defines.h.

#define USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */

Definition at line 52 of file usb_defines.h.

#define USB_EPTYPE_MASK 3U /* USB endpoint type mask */

Definition at line 55 of file usb_defines.h.

#define USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */

Definition at line 26 of file usb_defines.h.

#define USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */

Definition at line 27 of file usb_defines.h.

#define USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */

Definition at line 25 of file usb_defines.h.

#define USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */

Definition at line 24 of file usb_defines.h.

#define USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */

Definition at line 31 of file usb_defines.h.

#define USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */

Definition at line 32 of file usb_defines.h.

#define USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */

Definition at line 30 of file usb_defines.h.

#define USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */

Definition at line 29 of file usb_defines.h.

Enumeration Type Documentation

enum usb_core_id_enum
Enumerator
USB_HS_CORE_ID
USB_FS_CORE_ID

Definition at line 86 of file usb_defines.h.

87 {
88 USB_HS_CORE_ID = 0,
89 USB_FS_CORE_ID = 1
90 }usb_core_id_enum;
USB_HS_CORE_ID
Definition: usb_defines.h:88
USB_FS_CORE_ID
Definition: usb_defines.h:89
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:86
enum usb_speed_enum
Enumerator
USB_SPEED_UNKNOWN
USB_SPEED_LOW
USB_SPEED_FULL
USB_SPEED_HIGH

Definition at line 92 of file usb_defines.h.

93 {
94 USB_SPEED_UNKNOWN = 0,
95 USB_SPEED_LOW,
96 USB_SPEED_FULL,
97 USB_SPEED_HIGH
98 }usb_speed_enum;
USB_SPEED_FULL
Definition: usb_defines.h:96
usb_speed_enum
usb_speed_enum
Definition: usb_defines.h:92
USB_SPEED_UNKNOWN
Definition: usb_defines.h:94
USB_SPEED_HIGH
Definition: usb_defines.h:97
USB_SPEED_LOW
Definition: usb_defines.h:95
Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_regs.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
Macros
usb_regs.h File Reference

USB FS cell registers definition and handle macros. More...

#include "usb_conf.h"

Go to the source code of this file.

Macros

#define | USBFS USBFS_BASE
#define | LOCATE_DIEPTFLEN(x) (0x104U + 4U * ((x) - 1U))
#define | LOCATE_HCHCTL(x) (0x500U + 0x20U * (x))
#define | LOCATE_HCHINTF(x) (0x508U + 0x20U * (x))
#define | LOCATE_HCHINTEN(x) (0x50CU + 0x20U * (x))
#define | LOCATE_HCHLEN(x) (0x510U + 0x20U * (x))
#define | LOCATE_DIEPCTL(x) (0x900U + 0x20U * (x))
#define | LOCATE_DOEPCTL(x) (0xB00U + 0x20U * (x))
#define | LOCATE_DIEPINTF(x) (0x908U + 0x20U * (x))
#define | LOCATE_DOEPINTF(x) (0xB08U + 0x20U * (x))
#define | LOCATE_DIEPLEN(x) (0x910U + 0x20U * (x))
#define | LOCATE_DOEPLEN(x) (0xB10U + 0x20U * (x))
#define | LOCATE_DIEPxTFSTAT(x) (0x918U + 0x20U * (x))
#define | LOCATE_FIFO(x) (((x) + 1U) << 12U)
#define | USB_GOTGCS REG32(((USBFS) + 0x0000U))
#define | USB_GOTGINTF REG32(((USBFS) + 0x0004U))
#define | USB_GAHBCS REG32(((USBFS) + 0x0008U))
#define | USB_GUSBCS REG32(((USBFS) + 0x000CU))
#define | USB_GRSTCTL REG32(((USBFS) + 0x0010U))
#define | USB_GINTF REG32(((USBFS) + 0x0014U))
#define | USB_GINTEN REG32(((USBFS) + 0x0018U))
#define | USB_GRSTATR REG32(((USBFS) + 0x001CU))
#define | USB_GRSTATP REG32(((USBFS) + 0x0020U))
#define | USB_GRFLEN REG32(((USBFS) + 0x0024U))
#define | USB_HNPTFLEN REG32(((USBFS) + 0x0028U))
#define | USB_DIEP0TFLEN REG32(((USBFS) + 0x0028U))
#define | USB_HNPTFQSTAT REG32(((USBFS) + 0x002CU))
#define | USB_GCCFG REG32(((USBFS) + 0x0038U))
#define | USB_CID REG32(((USBFS) + 0x003CU))
#define | USB_HPTFLEN REG32(((USBFS) + 0x0100U))
#define | USB_DIEPxTFLEN(x) REG32(((USBFS) + LOCATE_DIEPTFLEN(x)))
#define | USB_HCTL REG32(((USBFS) + 0x0400U))
#define | USB_HFT REG32(((USBFS) + 0x0404U))
#define | USB_HFINFR REG32(((USBFS) + 0x0408U))
#define | USB_HPTFQSTAT REG32(((USBFS) + 0x0410U))
#define | USB_HACHINT REG32(((USBFS) + 0x0414U))
#define | USB_HACHINTEN REG32(((USBFS) + 0x0418U))
#define | USB_HPCS REG32(((USBFS) + 0x0440U))
#define | USB_HCHxCTL(x) REG32(((USBFS) + LOCATE_HCHCTL(x)))
#define | USB_HCHxINTF(x) REG32(((USBFS) + LOCATE_HCHINTF(x)))
#define | USB_HCHxINTEN(x) REG32(((USBFS) + LOCATE_HCHINTEN(x)))
#define | USB_HCHxLEN(x) REG32(((USBFS) + LOCATE_HCHLEN(x)))
#define | USB_DCFG REG32(((USBFS) + 0x0800U))
#define | USB_DCTL REG32(((USBFS) + 0x0804U))
#define | USB_DSTAT REG32(((USBFS) + 0x0808U))
#define | USB_DIEPINTEN REG32(((USBFS) + 0x0810U))
#define | USB_DOEPINTEN REG32(((USBFS) + 0x0814U))
#define | USB_DAEPINT REG32(((USBFS) + 0x0818U))
#define | USB_DAEPINTEN REG32(((USBFS) + 0x081CU))
#define | USB_DVBUSDT REG32(((USBFS) + 0x0828U))
#define | USB_DVBUSPT REG32(((USBFS) + 0x082CU))
#define | USB_DIEPFEINTEN REG32(((USBFS) + 0x0834U))
#define | USB_DEP1INT REG32(((USBFS) + 0x0838U))
#define | USB_DEP1INTEN REG32(((USBFS) + 0x083CU))
#define | USB_DIEP1INTEN REG32(((USBFS) + 0x0844U))
#define | USB_DOEP1INTEN REG32(((USBFS) + 0x0884U))
#define | USB_DIEP0CTL REG32(((USBFS) + 0x0900U))
#define | USB_DIEP0LEN REG32(((USBFS) + 0x0910U))
#define | USB_DOEP0CTL REG32(((USBFS) + 0x0B00U))
#define | USB_DOEP0LEN REG32(((USBFS) + 0x0B10U))
#define | USB_DIEPxCTL(x) REG32(((USBFS) + LOCATE_DIEPCTL(x)))
#define | USB_DOEPxCTL(x) REG32(((USBFS) + LOCATE_DOEPCTL(x)))
#define | USB_DIEPxINTF(x) REG32(((USBFS) + LOCATE_DIEPINTF(x)))
#define | USB_DOEPxINTF(x) REG32(((USBFS) + LOCATE_DOEPINTF(x)))
#define | USB_DIEPxLEN(x) REG32(((USBFS) + LOCATE_DIEPLEN(x)))
#define | USB_DOEPxLEN(x) REG32(((USBFS) + LOCATE_DOEPLEN(x)))
#define | USB_DIEPxTFSTAT(x) REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x)))
#define | USB_PWRCLKCTL REG32(((USBFS) + 0x0E00U))
#define | USB_FIFO(x) (&REG32(((USBFS) + LOCATE_FIFO(x))))
#define | GOTGCS_BSV BIT(19)
#define | GOTGCS_ASV BIT(18)
#define | GOTGCS_DI BIT(17)
#define | GOTGCS_IDPS BIT(16)
#define | GOTGCS_DHNPEN BIT(11)
#define | GOTGCS_HHNPEN BIT(10)
#define | GOTGCS_HNPREQ BIT(9)
#define | GOTGCS_HNPS BIT(8)
#define | GOTGCS_SRPREQ BIT(1)
#define | GOTGCS_SRPS BIT(0)
#define | GOTGINTF_DF BIT(19)
#define | GOTGINTF_ADTO BIT(18)
#define | GOTGINTF_HNPDET BIT(17)
#define | GOTGINTF_HNPEND BIT(9)
#define | GOTGINTF_SRPEND BIT(8)
#define | GOTGINTF_SESEND BIT(2)
#define | GAHBCS_PTXFTH BIT(8)
#define | GAHBCS_TXFTH BIT(7)
#define | GAHBCS_GINTEN BIT(0)
#define | GUSBCS_FDM BIT(30)
#define | GUSBCS_FHM BIT(29)
#define | GUSBCS_UTT BITS(10, 13)
#define | GUSBCS_HNPCEN BIT(9)
#define | GUSBCS_SRPCEN BIT(8)
#define | GUSBCS_TOC BITS(0, 2)
#define | GRSTCTL_TXFNUM BITS(6, 10)
#define | GRSTCTL_TXFF BIT(5)
#define | GRSTCTL_RXFF BIT(4)
#define | GRSTCTL_HFCRST BIT(2)
#define | GRSTCTL_HCSRST BIT(1)
#define | GRSTCTL_CSRST BIT(0)
#define | GINTF_WKUPIF BIT(31)
#define | GINTF_SESIF BIT(30)
#define | GINTF_DISCIF BIT(29)
#define | GINTF_IDPSC BIT(28)
#define | GINTF_PTXFEIF BIT(26)
#define | GINTF_HCIF BIT(25)
#define | GINTF_HPIF BIT(24)
#define | GINTF_PXNCIF BIT(21)
#define | GINTF_ISOONCIF BIT(21)
#define | GINTF_ISOINCIF BIT(20)
#define | GINTF_OEPIF BIT(19)
#define | GINTF_IEPIF BIT(18)
#define | GINTF_EOPFIF BIT(15)
#define | GINTF_ISOOPDIF BIT(14)
#define | GINTF_ENUMF BIT(13)
#define | GINTF_RST BIT(12)
#define | GINTF_SP BIT(11)
#define | GINTF_ESP BIT(10)
#define | GINTF_GONAK BIT(7)
#define | GINTF_GNPINAK BIT(6)
#define | GINTF_NPTXFEIF BIT(5)
#define | GINTF_RXFNEIF BIT(4)
#define | GINTF_SOF BIT(3)
#define | GINTF_OTGIF BIT(2)
#define | GINTF_MFIF BIT(1)
#define | GINTF_COPM BIT(0)
#define | GINTEN_WKUPIE BIT(31)
#define | GINTEN_SESIE BIT(30)
#define | GINTEN_DISCIE BIT(29)
#define | GINTEN_IDPSCIE BIT(28)
#define | GINTEN_PTXFEIE BIT(26)
#define | GINTEN_HCIE BIT(25)
#define | GINTEN_HPIE BIT(24)
#define | GINTEN_PXNCIE BIT(21)
#define | GINTEN_ISOONCIE BIT(21)
#define | GINTEN_ISOINCIE BIT(20)
#define | GINTEN_OEPIE BIT(19)
#define | GINTEN_IEPIE BIT(18)
#define | GINTEN_EOPFIE BIT(15)
#define | GINTEN_ISOOPDIE BIT(14)
#define | GINTEN_ENUMFIE BIT(13)
#define | GINTEN_RSTIE BIT(12)
#define | GINTEN_SPIE BIT(11)
#define | GINTEN_ESPIE BIT(10)
#define | GINTEN_GONAKIE BIT(7)
#define | GINTEN_GNPINAKIE BIT(6)
#define | GINTEN_NPTXFEIE BIT(5)
#define | GINTEN_RXFNEIE BIT(4)
#define | GINTEN_SOFIE BIT(3)
#define | GINTEN_OTGIE BIT(2)
#define | GINTEN_MFIE BIT(1)
#define | GRSTATRP_RPCKST BITS(17, 20)
#define | GRSTATRP_DPID BITS(15, 16)
#define | GRSTATRP_BCOUNT BITS(4, 14)
#define | GRSTATRP_CNUM BITS(0, 3)
#define | GRSTATRP_EPNUM BITS(0, 3)
#define | GRFLEN_RXFD BITS(0, 15)
#define | HNPTFLEN_HNPTXFD BITS(16, 31)
#define | HNPTFLEN_HNPTXRSAR BITS(0, 15)
#define | DIEP0TFLEN_IEP0TXFD BITS(16, 31)
#define | DIEP0TFLEN_IEP0TXRSAR BITS(0, 15)
#define | HNPTFQSTAT_NPTXRQTOP BITS(24, 30)
#define | HNPTFQSTAT_NPTXRQS BITS(16, 23)
#define | HNPTFQSTAT_NPTXFS BITS(0, 15)
#define | HNPTFQSTAT_CNUM BITS(27, 30)
#define | HNPTFQSTAT_EPNUM BITS(27, 30)
#define | HNPTFQSTAT_TYPE BITS(25, 26)
#define | HNPTFQSTAT_TMF BIT(24)
#define | GCCFG_VBUSIG BIT(21)
#define | GCCFG_SOFOEN BIT(20)
#define | GCCFG_VBUSBCEN BIT(19)
#define | GCCFG_VBUSACEN BIT(18)
#define | GCCFG_PWRON BIT(16)
#define | CID_CID BITS(0, 31)
#define | HPTFLEN_HPTXFD BITS(16, 31)
#define | HPTFLEN_HPTXFSAR BITS(0, 15)
#define | DIEPTFLEN_IEPTXFD BITS(16, 31)
#define | DIEPTFLEN_IEPTXRSAR BITS(0, 15)
#define | HCTL_CLKSEL BITS(0, 1)
#define | HFT_FRI BITS(0, 15)
#define | HFINFR_FRT BITS(16, 31)
#define | HFINFR_FRNUM BITS(0, 15)
#define | HPTFQSTAT_PTXREQT BITS(24, 31)
#define | HPTFQSTAT_PTXREQS BITS(16, 23)
#define | HPTFQSTAT_PTXFS BITS(0, 15)
#define | HPTFQSTAT_OEFRM BIT(31)
#define | HPTFQSTAT_CNUM BITS(27, 30)
#define | HPTFQSTAT_EPNUM BITS(27, 30)
#define | HPTFQSTAT_TYPE BITS(25, 26)
#define | HPTFQSTAT_TMF BIT(24)
#define | HACHINT_HACHINT BITS(0, 7)
#define | HACHINTEN_CINTEN BITS(0, 7)
#define | HPCS_PS BITS(17, 18)
#define | HPCS_PP BIT(12)
#define | HPCS_PLST BITS(10, 11)
#define | HPCS_PRST BIT(8)
#define | HPCS_PSP BIT(7)
#define | HPCS_PREM BIT(6)
#define | HPCS_PEDC BIT(3)
#define | HPCS_PE BIT(2)
#define | HPCS_PCD BIT(1)
#define | HPCS_PCST BIT(0)
#define | HCHCTL_CEN BIT(31)
#define | HCHCTL_CDIS BIT(30)
#define | HCHCTL_ODDFRM BIT(29)
#define | HCHCTL_DAR BITS(22, 28)
#define | HCHCTL_MPC BITS(20, 21)
#define | HCHCTL_EPTYPE BITS(18, 19)
#define | HCHCTL_LSD BIT(17)
#define | HCHCTL_EPDIR BIT(15)
#define | HCHCTL_EPNUM BITS(11, 14)
#define | HCHCTL_MPL BITS(0, 10)
#define | HCHINTF_DTER BIT(10)
#define | HCHINTF_REQOVR BIT(9)
#define | HCHINTF_BBER BIT(8)
#define | HCHINTF_USBER BIT(7)
#define | HCHINTF_NYET BIT(6)
#define | HCHINTF_ACK BIT(5)
#define | HCHINTF_NAK BIT(4)
#define | HCHINTF_STALL BIT(3)
#define | HCHINTF_CH BIT(1)
#define | HCHINTF_TF BIT(0)
#define | HCHINTEN_DTERIE BIT(10)
#define | HCHINTEN_REQOVRIE BIT(9)
#define | HCHINTEN_BBERIE BIT(8)
#define | HCHINTEN_USBERIE BIT(7)
#define | HCHINTEN_NYETIE BIT(6)
#define | HCHINTEN_ACKIE BIT(5)
#define | HCHINTEN_NAKIE BIT(4)
#define | HCHINTEN_STALLIE BIT(3)
#define | HCHINTEN_CHIE BIT(1)
#define | HCHINTEN_TFIE BIT(0)
#define | HCHLEN_DPID BITS(29, 30)
#define | HCHLEN_PCNT BITS(19, 28)
#define | HCHLEN_TLEN BITS(0, 18)
#define | DCFG_EOPFT BITS(11, 12)
#define | DCFG_DAR BITS(4, 10)
#define | DCFG_NZLSOH BIT(2)
#define | DCFG_DS BITS(0, 1)
#define | DCTL_POIF BIT(11)
#define | DCTL_CGONAK BIT(10)
#define | DCTL_SGONAK BIT(9)
#define | DCTL_CGINAK BIT(8)
#define | DCTL_SGINAK BIT(7)
#define | DCTL_GONS BIT(3)
#define | DCTL_GINS BIT(2)
#define | DCTL_SD BIT(1)
#define | DCTL_RWKUP BIT(0)
#define | DSTAT_FNRSOF BITS(8, 21)
#define | DSTAT_ES BITS(1, 2)
#define | DSTAT_SPST BIT(0)
#define | DIEPINTEN_TXFEEN BIT(7)
#define | DIEPINTEN_IEPNEEN BIT(6)
#define | DIEPINTEN_EPTXFUDEN BIT(4)
#define | DIEPINTEN_CITOEN BIT(3)
#define | DIEPINTEN_EPDISEN BIT(1)
#define | DIEPINTEN_TFEN BIT(0)
#define | DOEPINTEN_BTBSTPEN BIT(6)
#define | DOEPINTEN_EPRXFOVREN BIT(4)
#define | DOEPINTEN_STPFEN BIT(3)
#define | DOEPINTEN_EPDISEN BIT(1)
#define | DOEPINTEN_TFEN BIT(0)
#define | DAEPINT_OEPITB BITS(16, 21)
#define | DAEPINT_IEPITB BITS(0, 5)
#define | DAEPINTEN_OEPIE BITS(16, 21)
#define | DAEPINTEN_IEPIE BITS(0, 3)
#define | DVBUSDT_DVBUSDT BITS(0, 15)
#define | DVBUSPT_DVBUSPT BITS(0, 11)
#define | DIEPFEINTEN_IEPTXFEIE BITS(0, 3)
#define | DEP0CTL_EPEN BIT(31)
#define | DEP0CTL_EPD BIT(30)
#define | DEP0CTL_SNAK BIT(27)
#define | DEP0CTL_CNAK BIT(26)
#define | DIEP0CTL_TXFNUM BITS(22, 25)
#define | DEP0CTL_STALL BIT(21)
#define | DEP0CTL_EPTYPE BITS(18, 19)
#define | DEP0CTL_NAKS BIT(17)
#define | DEP0CTL_EPACT BIT(15)
#define | DEP0CTL_MPL BITS(0, 1)
#define | DEPCTL_EPEN BIT(31)
#define | DEPCTL_EPD BIT(30)
#define | DEPCTL_SODDFRM BIT(29)
#define | DEPCTL_SD1PID BIT(29)
#define | DEPCTL_SEVNFRM BIT(28)
#define | DEPCTL_SD0PID BIT(28)
#define | DEPCTL_SNAK BIT(27)
#define | DEPCTL_CNAK BIT(26)
#define | DIEPCTL_TXFNUM BITS(22, 25)
#define | DEPCTL_STALL BIT(21)
#define | DEPCTL_EPTYPE BITS(18, 19)
#define | DEPCTL_NAKS BIT(17)
#define | DEPCTL_EOFRM BIT(16)
#define | DEPCTL_DPID BIT(16)
#define | DEPCTL_EPACT BIT(15)
#define | DEPCTL_MPL BITS(0, 10)
#define | DIEPINTF_TXFE BIT(7)
#define | DIEPINTF_IEPNE BIT(6)
#define | DIEPINTF_EPTXFUD BIT(4)
#define | DIEPINTF_CITO BIT(3)
#define | DIEPINTF_EPDIS BIT(1)
#define | DIEPINTF_TF BIT(0)
#define | DOEPINTF_BTBSTP BIT(6)
#define | DOEPINTF_EPRXFOVR BIT(4)
#define | DOEPINTF_STPF BIT(3)
#define | DOEPINTF_EPDIS BIT(1)
#define | DOEPINTF_TF BIT(0)
#define | DIEP0LEN_PCNT BITS(19, 20)
#define | DIEP0LEN_TLEN BITS(0, 6)
#define | DOEP0LEN_STPCNT BITS(29, 30)
#define | DOEP0LEN_PCNT BIT(19)
#define | DOEP0LEN_TLEN BITS(0, 6)
#define | DOEPLEN_RXDPID BITS(29, 30)
#define | DOEPLEN_STPCNT BITS(29, 30)
#define | DIEPLEN_MCNT BITS(29, 30)
#define | DEPLEN_PCNT BITS(19, 28)
#define | DEPLEN_TLEN BITS(0, 18)
#define | DIEPTFSTAT_IEPTFS BITS(0, 15)
#define | PWRCLKCTL_SHCLK BIT(1)
#define | PWRCLKCTL_SUCLK BIT(0)
#define | DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U))
#define | USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U)
#define | USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U)
#define | USB_SPEED_INP_FULL DCFG_DEVSPEED(3U)
#define | GAHBCS_TFEL(regval) (GAHBCS_TXFTH & ((regval) << 7U))
#define | TXFIFO_EMPTY_HALF GAHBCS_TFEL(0U)
#define | TXFIFO_EMPTY GAHBCS_TFEL(1U)
#define | GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U))
#define | DMA_INCR0 GAHBCS_DMAINCR(0U)
#define | DMA_INCR1 GAHBCS_DMAINCR(1U)
#define | DMA_INCR4 GAHBCS_DMAINCR(3U)
#define | DMA_INCR8 GAHBCS_DMAINCR(5U)
#define | DMA_INCR16 GAHBCS_DMAINCR(7U)
#define | DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U))
#define | FRAME_INTERVAL_80 DCFG_PFRI(0U)
#define | FRAME_INTERVAL_85 DCFG_PFRI(1U)
#define | FRAME_INTERVAL_90 DCFG_PFRI(2U)
#define | FRAME_INTERVAL_95 DCFG_PFRI(3U)
#define | DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U))
#define | EP0MPL_64 DEP0_MPL(0U)
#define | EP0MPL_32 DEP0_MPL(1U)
#define | EP0MPL_16 DEP0_MPL(2U)
#define | EP0MPL_8 DEP0_MPL(3U)
#define | EP0_OUT ((uint8_t)0x00U)
#define | EP0_IN ((uint8_t)0x80U)
#define | EP1_OUT ((uint8_t)0x01U)
#define | EP1_IN ((uint8_t)0x81U)
#define | EP2_OUT ((uint8_t)0x02U)
#define | EP2_IN ((uint8_t)0x82U)
#define | EP3_OUT ((uint8_t)0x03U)
#define | EP3_IN ((uint8_t)0x83U)
#define | USB_GLOBAL_INT_ENABLE() (USB_GAHBCS |= GAHBCS_GINTEN)
#define | USB_GLOBAL_INT_DISABLE() (USB_GAHBCS &= ~GAHBCS_GINTEN)
#define | USB_CURRENT_MODE_GET() (USB_GINTF & GINTF_COPM)
#define | USB_CORE_INTR_READ(x)
#define | USB_DAOEP_INTR_READ(x)
#define | USB_DOEP_INTR_READ(x, EpID)
#define | USB_DAIEP_INTR_READ(x)
#define | USB_DIEP_INTR_READ(x, EpID)
#define | USB_REMOTE_WAKEUP_SET() (USB_DCTL |= DCTL_RWKUP)
#define | USB_REMOTE_WAKEUP_RESET() (USB_DCTL &= ~DCTL_RWKUP)
#define | USB_SOFT_DISCONNECT_ENABLE() (USB_DCTL |= DCTL_SD)
#define | USB_SOFT_DISCONNECT_DISABLE() (USB_DCTL &= ~DCTL_SD)
#define | USB_SET_DEVADDR(DevAddr) (USB_DCFG |= (DevAddr) << 4U)
#define | USB_EVEN_FRAME() (!(USB_HFINFR & 0x01U))
#define | USB_PORT_READ() (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC))
#define | USB_FSLSCLOCK_INIT(ClockFreq) (USB_HCTL &= ~HCTL_CLKSEL | (ClockFreq))
#define | USB_CURRENT_SPEED_GET() ((USB_HPCS & HPCS_PS) >> 17)
#define | USB_CURRENT_FRAME_GET() (USB_HFINFR & 0xFFFFU)

Detailed Description

USB FS cell registers definition and handle macros.

Definition in file usb_regs.h.

Macro Definition Documentation

#define CID_CID BITS(0, 31)

core ID

Definition at line 233 of file usb_regs.h.

#define DAEPINT_IEPITB BITS(0, 5)

device all IN endpoint interrupt bits

Definition at line 378 of file usb_regs.h.

#define DAEPINT_OEPITB BITS(16, 21)

device all OUT endpoint interrupt bits

Definition at line 377 of file usb_regs.h.

#define DAEPINTEN_IEPIE BITS(0, 3)

IN endpoint interrupt enable

Definition at line 382 of file usb_regs.h.

#define DAEPINTEN_OEPIE BITS(16, 21)

OUT endpoint interrupt enable

Definition at line 381 of file usb_regs.h.

#define DCFG_DAR BITS(4, 10)

device address

Definition at line 339 of file usb_regs.h.

#define DCFG_DEVSPEED ( regval ) (DCFG_DS & ((regval) << 0U))

device speed configuration

Definition at line 496 of file usb_regs.h.

#define DCFG_DS BITS(0, 1)

device speed

Definition at line 341 of file usb_regs.h.

#define DCFG_EOPFT BITS(11, 12)

end of periodic frame time

Definition at line 338 of file usb_regs.h.

#define DCFG_NZLSOH BIT(2)

non-zero-length status OUT handshake

Definition at line 340 of file usb_regs.h.

#define DCFG_PFRI ( regval ) (DCFG_EOPFT & ((regval) << 11U))

end of periodic frame time configuration

Definition at line 515 of file usb_regs.h.

#define DCTL_CGINAK BIT(8)

clear global IN NAK

Definition at line 347 of file usb_regs.h.

#define DCTL_CGONAK BIT(10)

clear global OUT NAK

Definition at line 345 of file usb_regs.h.

#define DCTL_GINS BIT(2)

global IN NAK status

Definition at line 350 of file usb_regs.h.

#define DCTL_GONS BIT(3)

global OUT NAK status

Definition at line 349 of file usb_regs.h.

#define DCTL_POIF BIT(11)

power-on initialization finished

Definition at line 344 of file usb_regs.h.

#define DCTL_RWKUP BIT(0)

remote wakeup

Definition at line 352 of file usb_regs.h.

#define DCTL_SD BIT(1)

soft disconnect

Definition at line 351 of file usb_regs.h.

#define DCTL_SGINAK BIT(7)

set global IN NAK

Definition at line 348 of file usb_regs.h.

#define DCTL_SGONAK BIT(9)

set global OUT NAK

Definition at line 346 of file usb_regs.h.

#define DEP0_MPL ( regval ) (DEP0CTL_MPL & ((regval) << 0U))

maximum packet length configuration

Definition at line 522 of file usb_regs.h.

#define DEP0CTL_CNAK BIT(26)

clear NAK

Definition at line 421 of file usb_regs.h.

#define DEP0CTL_EPACT BIT(15)

endpoint active

Definition at line 427 of file usb_regs.h.

#define DEP0CTL_EPD BIT(30)

endpoint disable

Definition at line 419 of file usb_regs.h.

#define DEP0CTL_EPEN BIT(31)
  • device endpoint 1 interrupt register bits definitions */* device endpoint 1 interrupt register enable bits definitions */* device IN endpoint 1 interrupt enable register bits definitions */* device OUT endpoint 1 interrupt enable register bits definitions */ endpoint enable

Definition at line 418 of file usb_regs.h.

#define DEP0CTL_EPTYPE BITS(18, 19)

endpoint type

Definition at line 425 of file usb_regs.h.

#define DEP0CTL_MPL BITS(0, 1)

maximum packet length

Definition at line 428 of file usb_regs.h.

#define DEP0CTL_NAKS BIT(17)

NAK status

Definition at line 426 of file usb_regs.h.

#define DEP0CTL_SNAK BIT(27)

set NAK

Definition at line 420 of file usb_regs.h.

#define DEP0CTL_STALL BIT(21)

STALL handshake

Definition at line 423 of file usb_regs.h.

#define DEPCTL_CNAK BIT(26)

clear NAK

Definition at line 438 of file usb_regs.h.

#define DEPCTL_DPID BIT(16)

endpoint data PID

Definition at line 445 of file usb_regs.h.

#define DEPCTL_EOFRM BIT(16)

even/odd frame

Definition at line 444 of file usb_regs.h.

#define DEPCTL_EPACT BIT(15)

endpoint active

Definition at line 446 of file usb_regs.h.

#define DEPCTL_EPD BIT(30)

endpoint disable

Definition at line 432 of file usb_regs.h.

#define DEPCTL_EPEN BIT(31)

endpoint enable

Definition at line 431 of file usb_regs.h.

#define DEPCTL_EPTYPE BITS(18, 19)

endpoint type

Definition at line 442 of file usb_regs.h.

#define DEPCTL_MPL BITS(0, 10)

maximum packet length

Definition at line 447 of file usb_regs.h.

#define DEPCTL_NAKS BIT(17)

NAK status

Definition at line 443 of file usb_regs.h.

#define DEPCTL_SD0PID BIT(28)

set DATA0 PID

Definition at line 436 of file usb_regs.h.

#define DEPCTL_SD1PID BIT(29)

set DATA1 PID

Definition at line 434 of file usb_regs.h.

#define DEPCTL_SEVNFRM BIT(28)

set even frame

Definition at line 435 of file usb_regs.h.

#define DEPCTL_SNAK BIT(27)

set NAK

Definition at line 437 of file usb_regs.h.

#define DEPCTL_SODDFRM BIT(29)

set odd frame

Definition at line 433 of file usb_regs.h.

#define DEPCTL_STALL BIT(21)

STALL handshake

Definition at line 440 of file usb_regs.h.

#define DEPLEN_PCNT BITS(19, 28)

packet count

Definition at line 479 of file usb_regs.h.

#define DEPLEN_TLEN BITS(0, 18)

transfer length

Definition at line 480 of file usb_regs.h.

#define DIEP0CTL_TXFNUM BITS(22, 25)

tx FIFO number

Definition at line 422 of file usb_regs.h.

#define DIEP0LEN_PCNT BITS(19, 20)

packet count

Definition at line 467 of file usb_regs.h.

#define DIEP0LEN_TLEN BITS(0, 6)

transfer length

Definition at line 468 of file usb_regs.h.

#define DIEP0TFLEN_IEP0TXFD BITS(16, 31)

IN Endpoint 0 Tx FIFO depth

Definition at line 213 of file usb_regs.h.

#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15)

IN Endpoint 0 TX RAM start address

Definition at line 214 of file usb_regs.h.

#define DIEPCTL_TXFNUM BITS(22, 25)

tx FIFO number

Definition at line 439 of file usb_regs.h.

#define DIEPFEINTEN_IEPTXFEIE BITS(0, 3)

IN endpoint Tx FIFO empty interrupt enable bits

Definition at line 391 of file usb_regs.h.

#define DIEPINTEN_CITOEN BIT(3)

control In Timeout interrupt enable bit

Definition at line 364 of file usb_regs.h.

#define DIEPINTEN_EPDISEN BIT(1)

endpoint disabled interrupt enable bit

Definition at line 365 of file usb_regs.h.

#define DIEPINTEN_EPTXFUDEN BIT(4)

endpoint Tx FIFO underrun interrupt enable bit

Definition at line 363 of file usb_regs.h.

#define DIEPINTEN_IEPNEEN BIT(6)

IN endpoint NAK effective interrupt enable bit

Definition at line 362 of file usb_regs.h.

#define DIEPINTEN_TFEN BIT(0)

transfer finished interrupt enable bit

Definition at line 366 of file usb_regs.h.

#define DIEPINTEN_TXFEEN BIT(7)

transmit FIFO empty interrupt enable bit

Definition at line 361 of file usb_regs.h.

#define DIEPINTF_CITO BIT(3)

control In Timeout interrupt

Definition at line 454 of file usb_regs.h.

#define DIEPINTF_EPDIS BIT(1)

endpoint disabled

Definition at line 455 of file usb_regs.h.

#define DIEPINTF_EPTXFUD BIT(4)

endpoint Tx FIFO underrun

Definition at line 453 of file usb_regs.h.

#define DIEPINTF_IEPNE BIT(6)

IN endpoint NAK effective

Definition at line 452 of file usb_regs.h.

#define DIEPINTF_TF BIT(0)

transfer finished

Definition at line 456 of file usb_regs.h.

#define DIEPINTF_TXFE BIT(7)

transmit FIFO empty

Definition at line 451 of file usb_regs.h.

#define DIEPLEN_MCNT BITS(29, 30)

multi count

Definition at line 478 of file usb_regs.h.

#define DIEPTFLEN_IEPTXFD BITS(16, 31)

IN endpoint Tx FIFO x depth

Definition at line 240 of file usb_regs.h.

#define DIEPTFLEN_IEPTXRSAR BITS(0, 15)

IN endpoint FIFOx Tx x RAM start address

Definition at line 241 of file usb_regs.h.

#define DIEPTFSTAT_IEPTFS BITS(0, 15)

IN endpoint¡¯s Tx FIFO space remaining

Definition at line 489 of file usb_regs.h.

#define DMA_INCR0 GAHBCS_DMAINCR(0U)

single burst type used by DMA

Definition at line 509 of file usb_regs.h.

#define DMA_INCR1 GAHBCS_DMAINCR(1U)

4-beat incrementing burst type used by DMA

Definition at line 510 of file usb_regs.h.

#define DMA_INCR16 GAHBCS_DMAINCR(7U)

32-beat incrementing burst type used by DMA

Definition at line 513 of file usb_regs.h.

#define DMA_INCR4 GAHBCS_DMAINCR(3U)

8-beat incrementing burst type used by DMA

Definition at line 511 of file usb_regs.h.

#define DMA_INCR8 GAHBCS_DMAINCR(5U)

16-beat incrementing burst type used by DMA

Definition at line 512 of file usb_regs.h.

#define DOEP0LEN_PCNT BIT(19)

packet count

Definition at line 472 of file usb_regs.h.

#define DOEP0LEN_STPCNT BITS(29, 30)

SETUP packet count

Definition at line 471 of file usb_regs.h.

#define DOEP0LEN_TLEN BITS(0, 6)

transfer length

Definition at line 473 of file usb_regs.h.

#define DOEPINTEN_BTBSTPEN BIT(6)

back-to-back SETUP packets interrupt enable bit

Definition at line 370 of file usb_regs.h.

#define DOEPINTEN_EPDISEN BIT(1)

endpoint disabled interrupt enable bit

Definition at line 373 of file usb_regs.h.

#define DOEPINTEN_EPRXFOVREN BIT(4)

endpoint Rx FIFO overrun interrupt enable bit

Definition at line 371 of file usb_regs.h.

#define DOEPINTEN_STPFEN BIT(3)

SETUP phase finished interrupt enable bit

Definition at line 372 of file usb_regs.h.

#define DOEPINTEN_TFEN BIT(0)

transfer finished interrupt enable bit

Definition at line 374 of file usb_regs.h.

#define DOEPINTF_BTBSTP BIT(6)

back-to-back SETUP packets

Definition at line 460 of file usb_regs.h.

#define DOEPINTF_EPDIS BIT(1)

endpoint disabled

Definition at line 463 of file usb_regs.h.

#define DOEPINTF_EPRXFOVR BIT(4)

endpoint Rx FIFO overrun

Definition at line 461 of file usb_regs.h.

#define DOEPINTF_STPF BIT(3)

SETUP phase finished

Definition at line 462 of file usb_regs.h.

#define DOEPINTF_TF BIT(0)

transfer finished

Definition at line 464 of file usb_regs.h.

#define DOEPLEN_RXDPID BITS(29, 30)

received data PID

Definition at line 476 of file usb_regs.h.

#define DOEPLEN_STPCNT BITS(29, 30)

SETUP packet count

Definition at line 477 of file usb_regs.h.

#define DSTAT_ES BITS(1, 2)

enumerated speed

Definition at line 356 of file usb_regs.h.

#define DSTAT_FNRSOF BITS(8, 21)

the frame number of the received SOF.

Definition at line 355 of file usb_regs.h.

#define DSTAT_SPST BIT(0)

suspend status

Definition at line 357 of file usb_regs.h.

#define DVBUSDT_DVBUSDT BITS(0, 15)

device VBUS discharge time

Definition at line 385 of file usb_regs.h.

#define DVBUSPT_DVBUSPT BITS(0, 11)

device VBUS pulsing time

Definition at line 388 of file usb_regs.h.

#define EP0_IN ((uint8_t)0x80U)

endpoint in 0

Definition at line 533 of file usb_regs.h.

#define EP0_OUT ((uint8_t)0x00U)

endpoint out 0

Definition at line 532 of file usb_regs.h.

#define EP0MPL_16 DEP0_MPL(2U)

maximum packet length 16 bytes

Definition at line 526 of file usb_regs.h.

#define EP0MPL_32 DEP0_MPL(1U)

maximum packet length 32 bytes

Definition at line 525 of file usb_regs.h.

#define EP0MPL_64 DEP0_MPL(0U)

maximum packet length 64 bytes

Definition at line 524 of file usb_regs.h.

#define EP0MPL_8 DEP0_MPL(3U)

maximum packet length 8 bytes

Definition at line 527 of file usb_regs.h.

#define EP1_IN ((uint8_t)0x81U)

endpoint in 1

Definition at line 535 of file usb_regs.h.

#define EP1_OUT ((uint8_t)0x01U)

endpoint out 1

Definition at line 534 of file usb_regs.h.

#define EP2_IN ((uint8_t)0x82U)

endpoint in 2

Definition at line 537 of file usb_regs.h.

#define EP2_OUT ((uint8_t)0x02U)

endpoint out 2

Definition at line 536 of file usb_regs.h.

#define EP3_IN ((uint8_t)0x83U)

endpoint in 3

Definition at line 539 of file usb_regs.h.

#define EP3_OUT ((uint8_t)0x03U)

endpoint out 3

Definition at line 538 of file usb_regs.h.

#define FRAME_INTERVAL_80 DCFG_PFRI(0U)

80% of the frame time

Definition at line 517 of file usb_regs.h.

#define FRAME_INTERVAL_85 DCFG_PFRI(1U)

85% of the frame time

Definition at line 518 of file usb_regs.h.

#define FRAME_INTERVAL_90 DCFG_PFRI(2U)

90% of the frame time

Definition at line 519 of file usb_regs.h.

#define FRAME_INTERVAL_95 DCFG_PFRI(3U)

95% of the frame time

Definition at line 520 of file usb_regs.h.

#define GAHBCS_DMAINCR ( regval ) (GAHBCS_BURST & ((regval) << 1U))

AHB burst type used by DMA

Definition at line 507 of file usb_regs.h.

#define GAHBCS_GINTEN BIT(0)

global interrupt enable

Definition at line 120 of file usb_regs.h.

#define GAHBCS_PTXFTH BIT(8)

periodic Tx FIFO threshold

Definition at line 116 of file usb_regs.h.

#define GAHBCS_TFEL ( regval ) (GAHBCS_TXFTH & ((regval) << 7U))

device speed configuration

Definition at line 502 of file usb_regs.h.

#define GAHBCS_TXFTH BIT(7)

tx FIFO threshold

Definition at line 117 of file usb_regs.h.

#define GCCFG_PWRON BIT(16)

power on

Definition at line 230 of file usb_regs.h.

#define GCCFG_SOFOEN BIT(20)

SOF output enable

Definition at line 227 of file usb_regs.h.

#define GCCFG_VBUSACEN BIT(18)

the VBUS A-device comparer enable

Definition at line 229 of file usb_regs.h.

#define GCCFG_VBUSBCEN BIT(19)

the VBUS B-device comparer enable

Definition at line 228 of file usb_regs.h.

#define GCCFG_VBUSIG BIT(21)

vbus ignored

Definition at line 226 of file usb_regs.h.

#define GINTEN_DISCIE BIT(29)

disconnect interrupt enable

Definition at line 174 of file usb_regs.h.

#define GINTEN_ENUMFIE BIT(13)

enumeration finish enable

Definition at line 186 of file usb_regs.h.

#define GINTEN_EOPFIE BIT(15)

end of periodic frame interrupt enable

Definition at line 184 of file usb_regs.h.

#define GINTEN_ESPIE BIT(10)

early suspend interrupt enable

Definition at line 189 of file usb_regs.h.

#define GINTEN_GNPINAKIE BIT(6)

global non-periodic IN NAK effective interrupt enable

Definition at line 191 of file usb_regs.h.

#define GINTEN_GONAKIE BIT(7)

global OUT NAK effective interrupt enable

Definition at line 190 of file usb_regs.h.

#define GINTEN_HCIE BIT(25)

host channels interrupt enable

Definition at line 177 of file usb_regs.h.

#define GINTEN_HPIE BIT(24)

host port interrupt enable

Definition at line 178 of file usb_regs.h.

#define GINTEN_IDPSCIE BIT(28)

id pin status change interrupt enable

Definition at line 175 of file usb_regs.h.

#define GINTEN_IEPIE BIT(18)

IN endpoints interrupt enable

Definition at line 183 of file usb_regs.h.

#define GINTEN_ISOINCIE BIT(20)

isochronous IN transfer not complete interrupt enable

Definition at line 181 of file usb_regs.h.

#define GINTEN_ISOONCIE BIT(21)

isochronous OUT transfer not complete interrupt enable

Definition at line 180 of file usb_regs.h.

#define GINTEN_ISOOPDIE BIT(14)

isochronous OUT packet dropped interrupt enable

Definition at line 185 of file usb_regs.h.

#define GINTEN_MFIE BIT(1)

mode fault interrupt enable

Definition at line 196 of file usb_regs.h.

#define GINTEN_NPTXFEIE BIT(5)

non-periodic Tx FIFO empty interrupt enable

Definition at line 192 of file usb_regs.h.

#define GINTEN_OEPIE BIT(19)

OUT endpoints interrupt enable

Definition at line 182 of file usb_regs.h.

#define GINTEN_OTGIE BIT(2)

OTG interrupt enable

Definition at line 195 of file usb_regs.h.

#define GINTEN_PTXFEIE BIT(26)

periodic tx FIFO empty interrupt enable

Definition at line 176 of file usb_regs.h.

#define GINTEN_PXNCIE BIT(21)

periodic transfer not complete interrupt enable

Definition at line 179 of file usb_regs.h.

#define GINTEN_RSTIE BIT(12)

USB reset interrupt enable

Definition at line 187 of file usb_regs.h.

#define GINTEN_RXFNEIE BIT(4)

receive FIFO non-empty interrupt enable

Definition at line 193 of file usb_regs.h.

#define GINTEN_SESIE BIT(30)

session interrupt enable

Definition at line 173 of file usb_regs.h.

#define GINTEN_SOFIE BIT(3)

start of frame interrupt enable

Definition at line 194 of file usb_regs.h.

#define GINTEN_SPIE BIT(11)

USB suspend interrupt enable

Definition at line 188 of file usb_regs.h.

#define GINTEN_WKUPIE BIT(31)

wakeup interrupt enable

Definition at line 172 of file usb_regs.h.

#define GINTF_COPM BIT(0)

current operation mode

Definition at line 169 of file usb_regs.h.

#define GINTF_DISCIF BIT(29)

disconnect interrupt flag

Definition at line 146 of file usb_regs.h.

#define GINTF_ENUMF BIT(13)

enumeration finished

Definition at line 158 of file usb_regs.h.

#define GINTF_EOPFIF BIT(15)

end of periodic frame interrupt flag

Definition at line 156 of file usb_regs.h.

#define GINTF_ESP BIT(10)

early suspend

Definition at line 161 of file usb_regs.h.

#define GINTF_GNPINAK BIT(6)

global IN non-periodic NAK effective

Definition at line 163 of file usb_regs.h.

#define GINTF_GONAK BIT(7)

global OUT NAK effective

Definition at line 162 of file usb_regs.h.

#define GINTF_HCIF BIT(25)

host channels interrupt flag

Definition at line 149 of file usb_regs.h.

#define GINTF_HPIF BIT(24)

host port interrupt flag

Definition at line 150 of file usb_regs.h.

#define GINTF_IDPSC BIT(28)

id pin status change

Definition at line 147 of file usb_regs.h.

#define GINTF_IEPIF BIT(18)

IN endpoint interrupt flag

Definition at line 155 of file usb_regs.h.

#define GINTF_ISOINCIF BIT(20)

isochronous IN transfer not complete interrupt flag

Definition at line 153 of file usb_regs.h.

#define GINTF_ISOONCIF BIT(21)

isochronous OUT transfer not complete interrupt flag

Definition at line 152 of file usb_regs.h.

#define GINTF_ISOOPDIF BIT(14)

isochronous OUT packet dropped interrupt flag

Definition at line 157 of file usb_regs.h.

#define GINTF_MFIF BIT(1)

mode fault interrupt flag

Definition at line 168 of file usb_regs.h.

#define GINTF_NPTXFEIF BIT(5)

non-periodic tx FIFO empty interrupt flag

Definition at line 164 of file usb_regs.h.

#define GINTF_OEPIF BIT(19)

OUT endpoint interrupt flag

Definition at line 154 of file usb_regs.h.

#define GINTF_OTGIF BIT(2)

OTG interrupt flag

Definition at line 167 of file usb_regs.h.

#define GINTF_PTXFEIF BIT(26)

periodic tx FIFO empty interrupt flag

Definition at line 148 of file usb_regs.h.

#define GINTF_PXNCIF BIT(21)

periodic transfer not complete interrupt flag

Definition at line 151 of file usb_regs.h.

#define GINTF_RST BIT(12)

USB reset

Definition at line 159 of file usb_regs.h.

#define GINTF_RXFNEIF BIT(4)

rx FIFO non-empty interrupt flag

Definition at line 165 of file usb_regs.h.

#define GINTF_SESIF BIT(30)

session interrupt flag

Definition at line 145 of file usb_regs.h.

#define GINTF_SOF BIT(3)

start of frame

Definition at line 166 of file usb_regs.h.

#define GINTF_SP BIT(11)

USB suspend

Definition at line 160 of file usb_regs.h.

#define GINTF_WKUPIF BIT(31)

wakeup interrupt flag

Definition at line 144 of file usb_regs.h.

#define GOTGCS_ASV BIT(18)

A-session valid

Definition at line 97 of file usb_regs.h.

#define GOTGCS_BSV BIT(19)

B-Session Valid

Definition at line 96 of file usb_regs.h.

#define GOTGCS_DHNPEN BIT(11)

device HNP enable

Definition at line 100 of file usb_regs.h.

#define GOTGCS_DI BIT(17)

debounce interval

Definition at line 98 of file usb_regs.h.

#define GOTGCS_HHNPEN BIT(10)

host HNP enable

Definition at line 101 of file usb_regs.h.

#define GOTGCS_HNPREQ BIT(9)

HNP request

Definition at line 102 of file usb_regs.h.

#define GOTGCS_HNPS BIT(8)

HNP successes

Definition at line 103 of file usb_regs.h.

#define GOTGCS_IDPS BIT(16)

id pin status

Definition at line 99 of file usb_regs.h.

#define GOTGCS_SRPREQ BIT(1)

SRP request

Definition at line 104 of file usb_regs.h.

#define GOTGCS_SRPS BIT(0)

SRP successes

Definition at line 105 of file usb_regs.h.

#define GOTGINTF_ADTO BIT(18)

A-device timeout

Definition at line 109 of file usb_regs.h.

#define GOTGINTF_DF BIT(19)

debounce finish

Definition at line 108 of file usb_regs.h.

#define GOTGINTF_HNPDET BIT(17)

host negotiation request detected

Definition at line 110 of file usb_regs.h.

#define GOTGINTF_HNPEND BIT(9)

HNP end

Definition at line 111 of file usb_regs.h.

#define GOTGINTF_SESEND BIT(2)

session end

Definition at line 113 of file usb_regs.h.

#define GOTGINTF_SRPEND BIT(8)

SRP end

Definition at line 112 of file usb_regs.h.

#define GRFLEN_RXFD BITS(0, 15)

rx FIFO depth

Definition at line 206 of file usb_regs.h.

#define GRSTATRP_BCOUNT BITS(4, 14)

byte count

Definition at line 201 of file usb_regs.h.

#define GRSTATRP_CNUM BITS(0, 3)

channel number

Definition at line 202 of file usb_regs.h.

#define GRSTATRP_DPID BITS(15, 16)

data PID

Definition at line 200 of file usb_regs.h.

#define GRSTATRP_EPNUM BITS(0, 3)

endpoint number

Definition at line 203 of file usb_regs.h.

#define GRSTATRP_RPCKST BITS(17, 20)

received packet status

Definition at line 199 of file usb_regs.h.

#define GRSTCTL_CSRST BIT(0)

core soft reset

Definition at line 141 of file usb_regs.h.

#define GRSTCTL_HCSRST BIT(1)

HCLK soft reset

Definition at line 140 of file usb_regs.h.

#define GRSTCTL_HFCRST BIT(2)

host frame counter reset

Definition at line 139 of file usb_regs.h.

#define GRSTCTL_RXFF BIT(4)

rx FIFO flush

Definition at line 138 of file usb_regs.h.

#define GRSTCTL_TXFF BIT(5)

tx FIFO flush

Definition at line 137 of file usb_regs.h.

#define GRSTCTL_TXFNUM BITS(6, 10)

tx FIFO number

Definition at line 136 of file usb_regs.h.

#define GUSBCS_FDM BIT(30)

force device mode

Definition at line 123 of file usb_regs.h.

#define GUSBCS_FHM BIT(29)

force host mode

Definition at line 124 of file usb_regs.h.

#define GUSBCS_HNPCEN BIT(9)

HNP capability enable

Definition at line 128 of file usb_regs.h.

#define GUSBCS_SRPCEN BIT(8)

SRP capability enable

Definition at line 129 of file usb_regs.h.

#define GUSBCS_TOC BITS(0, 2)

timeout calibration

Definition at line 131 of file usb_regs.h.

#define GUSBCS_UTT BITS(10, 13)

USB turnaround time

Definition at line 127 of file usb_regs.h.

#define HACHINT_HACHINT BITS(0, 7)

host all channel interrupts

Definition at line 265 of file usb_regs.h.

#define HACHINTEN_CINTEN BITS(0, 7)

channel interrupt enable

Definition at line 268 of file usb_regs.h.

#define HCHCTL_CDIS BIT(30)

channel disable

Definition at line 284 of file usb_regs.h.

#define HCHCTL_CEN BIT(31)

channel enable

Definition at line 283 of file usb_regs.h.

#define HCHCTL_DAR BITS(22, 28)

device address

Definition at line 286 of file usb_regs.h.

#define HCHCTL_EPDIR BIT(15)

endpoint direction

Definition at line 290 of file usb_regs.h.

#define HCHCTL_EPNUM BITS(11, 14)

endpoint number

Definition at line 291 of file usb_regs.h.

#define HCHCTL_EPTYPE BITS(18, 19)

endpoint type

Definition at line 288 of file usb_regs.h.

#define HCHCTL_LSD BIT(17)

low-speed device

Definition at line 289 of file usb_regs.h.

#define HCHCTL_MPC BITS(20, 21)

multiple packet count

Definition at line 287 of file usb_regs.h.

#define HCHCTL_MPL BITS(0, 10)

maximum packet length

Definition at line 292 of file usb_regs.h.

#define HCHCTL_ODDFRM BIT(29)

odd frame

Definition at line 285 of file usb_regs.h.

#define HCHINTEN_ACKIE BIT(5)

ACK interrupt enable

Definition at line 320 of file usb_regs.h.

#define HCHINTEN_BBERIE BIT(8)

babble error interrupt enable

Definition at line 317 of file usb_regs.h.

#define HCHINTEN_CHIE BIT(1)

channel halted interrupt enable

Definition at line 324 of file usb_regs.h.

#define HCHINTEN_DTERIE BIT(10)

data toggle error interrupt enable

Definition at line 315 of file usb_regs.h.

#define HCHINTEN_NAKIE BIT(4)

NAK interrupt enable

Definition at line 321 of file usb_regs.h.

#define HCHINTEN_NYETIE BIT(6)

NYET interrupt enable

Definition at line 319 of file usb_regs.h.

#define HCHINTEN_REQOVRIE BIT(9)

request queue overrun interrupt enable

Definition at line 316 of file usb_regs.h.

#define HCHINTEN_STALLIE BIT(3)

STALL interrupt enable

Definition at line 322 of file usb_regs.h.

#define HCHINTEN_TFIE BIT(0)

transfer finished interrupt enable

Definition at line 325 of file usb_regs.h.

#define HCHINTEN_USBERIE BIT(7)

USB bus error interrupt enable

Definition at line 318 of file usb_regs.h.

#define HCHINTF_ACK BIT(5)

ACK

Definition at line 307 of file usb_regs.h.

#define HCHINTF_BBER BIT(8)

babble error

Definition at line 304 of file usb_regs.h.

#define HCHINTF_CH BIT(1)

channel halted

Definition at line 311 of file usb_regs.h.

#define HCHINTF_DTER BIT(10)

data toggle error

Definition at line 302 of file usb_regs.h.

#define HCHINTF_NAK BIT(4)

NAK

Definition at line 308 of file usb_regs.h.

#define HCHINTF_NYET BIT(6)

NYET

Definition at line 306 of file usb_regs.h.

#define HCHINTF_REQOVR BIT(9)

request queue overrun

Definition at line 303 of file usb_regs.h.

#define HCHINTF_STALL BIT(3)

STALL

Definition at line 309 of file usb_regs.h.

#define HCHINTF_TF BIT(0)

transfer finished

Definition at line 312 of file usb_regs.h.

#define HCHINTF_USBER BIT(7)

USB bus Error

Definition at line 305 of file usb_regs.h.

#define HCHLEN_DPID BITS(29, 30)

data PID

Definition at line 329 of file usb_regs.h.

#define HCHLEN_PCNT BITS(19, 28)

packet count

Definition at line 330 of file usb_regs.h.

#define HCHLEN_TLEN BITS(0, 18)

transfer length

Definition at line 331 of file usb_regs.h.

#define HCTL_CLKSEL BITS(0, 1)

clock select for USB clock

Definition at line 245 of file usb_regs.h.

#define HFINFR_FRNUM BITS(0, 15)

frame number

Definition at line 252 of file usb_regs.h.

#define HFINFR_FRT BITS(16, 31)

frame remaining time

Definition at line 251 of file usb_regs.h.

#define HFT_FRI BITS(0, 15)

frame interval

Definition at line 248 of file usb_regs.h.

#define HNPTFLEN_HNPTXFD BITS(16, 31)

non-periodic Tx FIFO depth

Definition at line 209 of file usb_regs.h.

#define HNPTFLEN_HNPTXRSAR BITS(0, 15)

non-periodic Tx RAM start address

Definition at line 210 of file usb_regs.h.

#define HNPTFQSTAT_CNUM BITS(27, 30)

channel number

Definition at line 220 of file usb_regs.h.

#define HNPTFQSTAT_EPNUM BITS(27, 30)

endpoint number

Definition at line 221 of file usb_regs.h.

#define HNPTFQSTAT_NPTXFS BITS(0, 15)

non-periodic Tx FIFO space

Definition at line 219 of file usb_regs.h.

#define HNPTFQSTAT_NPTXRQS BITS(16, 23)

non-periodic Tx request queue space

Definition at line 218 of file usb_regs.h.

#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30)

top entry of the non-periodic Tx request queue

Definition at line 217 of file usb_regs.h.

#define HNPTFQSTAT_TMF BIT(24)

terminate flag

Definition at line 223 of file usb_regs.h.

#define HNPTFQSTAT_TYPE BITS(25, 26)

token type

Definition at line 222 of file usb_regs.h.

#define HPCS_PCD BIT(1)

port connect detected

Definition at line 279 of file usb_regs.h.

#define HPCS_PCST BIT(0)

port connect status

Definition at line 280 of file usb_regs.h.

#define HPCS_PE BIT(2)

port enable

Definition at line 278 of file usb_regs.h.

#define HPCS_PEDC BIT(3)

port enable/disable change

Definition at line 277 of file usb_regs.h.

#define HPCS_PLST BITS(10, 11)

port line status

Definition at line 273 of file usb_regs.h.

#define HPCS_PP BIT(12)

port power

Definition at line 272 of file usb_regs.h.

#define HPCS_PREM BIT(6)

port resume

Definition at line 276 of file usb_regs.h.

#define HPCS_PRST BIT(8)

port reset

Definition at line 274 of file usb_regs.h.

#define HPCS_PS BITS(17, 18)

port speed

Definition at line 271 of file usb_regs.h.

#define HPCS_PSP BIT(7)

port suspend

Definition at line 275 of file usb_regs.h.

#define HPTFLEN_HPTXFD BITS(16, 31)

host periodic Tx FIFO depth

Definition at line 236 of file usb_regs.h.

#define HPTFLEN_HPTXFSAR BITS(0, 15)

host periodic Tx RAM start address

Definition at line 237 of file usb_regs.h.

#define HPTFQSTAT_CNUM BITS(27, 30)

channel number

Definition at line 259 of file usb_regs.h.

#define HPTFQSTAT_EPNUM BITS(27, 30)

endpoint number

Definition at line 260 of file usb_regs.h.

#define HPTFQSTAT_OEFRM BIT(31)

odd/eveb frame

Definition at line 258 of file usb_regs.h.

#define HPTFQSTAT_PTXFS BITS(0, 15)

periodic Tx FIFO space

Definition at line 257 of file usb_regs.h.

#define HPTFQSTAT_PTXREQS BITS(16, 23)

periodic Tx request queue space

Definition at line 256 of file usb_regs.h.

#define HPTFQSTAT_PTXREQT BITS(24, 31)

top entry of the periodic Tx request queue

Definition at line 255 of file usb_regs.h.

#define HPTFQSTAT_TMF BIT(24)

terminate flag

Definition at line 262 of file usb_regs.h.

#define HPTFQSTAT_TYPE BITS(25, 26)

token type

Definition at line 261 of file usb_regs.h.

#define LOCATE_DIEPCTL ( x ) (0x900U + 0x20U * (x))

locate device IN endpoint-x control registers

Definition at line 25 of file usb_regs.h.

#define LOCATE_DIEPINTF ( x ) (0x908U + 0x20U * (x))

locate device IN endpoint-x interrupt flag registers

Definition at line 27 of file usb_regs.h.

#define LOCATE_DIEPLEN ( x ) (0x910U + 0x20U * (x))

locate device IN endpoint-x transfer length registers

Definition at line 29 of file usb_regs.h.

#define LOCATE_DIEPTFLEN ( x ) (0x104U + 4U * ((x) - 1U))

locate device IN endpoint-x (x = 1..3) transfer length registers

Definition at line 20 of file usb_regs.h.

#define LOCATE_DIEPxTFSTAT ( x ) (0x918U + 0x20U * (x))

locate Device IN endpoint-x transmit FIFO status register

Definition at line 31 of file usb_regs.h.

#define LOCATE_DOEPCTL ( x ) (0xB00U + 0x20U * (x))

locate device OUT endpoint-x control registers

Definition at line 26 of file usb_regs.h.

#define LOCATE_DOEPINTF ( x ) (0xB08U + 0x20U * (x))

locate device OUT endpoint-x interrupt flag registers

Definition at line 28 of file usb_regs.h.

#define LOCATE_DOEPLEN ( x ) (0xB10U + 0x20U * (x))

locate device OUT endpoint-x transfer length registers

Definition at line 30 of file usb_regs.h.

#define LOCATE_FIFO ( x ) (((x) + 1U) << 12U)

locate FIFO-x memory

Definition at line 32 of file usb_regs.h.

#define LOCATE_HCHCTL ( x ) (0x500U + 0x20U * (x))

locate host channel-x control registers

Definition at line 21 of file usb_regs.h.

#define LOCATE_HCHINTEN ( x ) (0x50CU + 0x20U * (x))

locate host channel-x interrupt enable registers

Definition at line 23 of file usb_regs.h.

#define LOCATE_HCHINTF ( x ) (0x508U + 0x20U * (x))

locate host channel-x interrupt flag registers

Definition at line 22 of file usb_regs.h.

#define LOCATE_HCHLEN ( x ) (0x510U + 0x20U * (x))

locate host channel-x transfer length registers

Definition at line 24 of file usb_regs.h.

#define PWRCLKCTL_SHCLK BIT(1)

stop HCLK

Definition at line 492 of file usb_regs.h.

#define PWRCLKCTL_SUCLK BIT(0)

stop the USB clock

Definition at line 493 of file usb_regs.h.

#define TXFIFO_EMPTY GAHBCS_TFEL(1U)

Tx FIFO completely empty

Definition at line 505 of file usb_regs.h.

#define TXFIFO_EMPTY_HALF GAHBCS_TFEL(0U)

Tx FIFO half empty

Definition at line 504 of file usb_regs.h.

#define USB_CID REG32(((USBFS) + 0x003CU))

core id register

Definition at line 49 of file usb_regs.h.

#define USB_CORE_INTR_READ ( x )
Value:
do { \
uint32_t global_intf = USB_GINTF; \
(x) = global_intf & USB_GINTEN; \
} while(0)
USB_GINTEN
#define USB_GINTEN
Definition: usb_regs.h:41
USB_GINTF
#define USB_GINTF
Definition: usb_regs.h:40

Definition at line 551 of file usb_regs.h.

#define USB_CURRENT_FRAME_GET ( ) (USB_HFINFR & 0xFFFFU)

Definition at line 620 of file usb_regs.h.

#define USB_CURRENT_MODE_GET ( ) (USB_GINTF & GINTF_COPM)

Definition at line 548 of file usb_regs.h.

#define USB_CURRENT_SPEED_GET ( ) ((USB_HPCS & HPCS_PS) >> 17)

Definition at line 617 of file usb_regs.h.

#define USB_DAEPINT REG32(((USBFS) + 0x0818U))

device all endpoints interrupt register

Definition at line 70 of file usb_regs.h.

#define USB_DAEPINTEN REG32(((USBFS) + 0x081CU))

device all endpoints interrupt enable register

Definition at line 71 of file usb_regs.h.

#define USB_DAIEP_INTR_READ ( x )
Value:
do { \
uint32_t dev_all_ep_inten = USB_DAEPINTEN; \
uint32_t dev_all_ep_int = USB_DAEPINT; \
uint32_t in_ep_intb = DAEPINT_IEPITB; \
(x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \
} while(0)
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:71
USB_DAEPINT
#define USB_DAEPINT
Definition: usb_regs.h:70
DAEPINT_IEPITB
#define DAEPINT_IEPITB
Definition: usb_regs.h:378

Definition at line 574 of file usb_regs.h.

#define USB_DAOEP_INTR_READ ( x )
Value:
do { \
uint32_t dev_all_ep_inten = USB_DAEPINTEN; \
uint32_t dev_all_ep_int = USB_DAEPINT; \
uint32_t out_ep_intb = DAEPINT_OEPITB; \
(x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \
} while(0)
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:71
USB_DAEPINT
#define USB_DAEPINT
Definition: usb_regs.h:70
DAEPINT_OEPITB
#define DAEPINT_OEPITB
Definition: usb_regs.h:377

Definition at line 558 of file usb_regs.h.

#define USB_DCFG REG32(((USBFS) + 0x0800U))

device configuration register

Definition at line 65 of file usb_regs.h.

#define USB_DCTL REG32(((USBFS) + 0x0804U))

device control register

Definition at line 66 of file usb_regs.h.

#define USB_DEP1INT REG32(((USBFS) + 0x0838U))

device endpoint 1 interrupt register

Definition at line 75 of file usb_regs.h.

#define USB_DEP1INTEN REG32(((USBFS) + 0x083CU))

device endpoint 1 interrupt enable register

Definition at line 76 of file usb_regs.h.

#define USB_DIEP0CTL REG32(((USBFS) + 0x0900U))

device IN endpoint 0 control register

Definition at line 79 of file usb_regs.h.

#define USB_DIEP0LEN REG32(((USBFS) + 0x0910U))

device IN endpoint 0 transfer length register

Definition at line 80 of file usb_regs.h.

#define USB_DIEP0TFLEN REG32(((USBFS) + 0x0028U))

device IN endpoint 0 transmit FIFO length register

Definition at line 46 of file usb_regs.h.

#define USB_DIEP1INTEN REG32(((USBFS) + 0x0844U))

device IN endpoint 1 interrupt enable register

Definition at line 77 of file usb_regs.h.

#define USB_DIEP_INTR_READ | ( | x,
 |  | EpID
 | ) |
Value:
do { \
uint32_t dev_ep_intf = USB_DIEPxINTF(EpID); \
uint32_t dev_ep_fifoempty_intf = (((USB_DIEPFEINTEN >> (EpID)) & 0x1U) << 7U); \
uint32_t dev_inep_inten = USB_DIEPINTEN; \
(x) = dev_ep_intf & (dev_ep_fifoempty_intf | dev_inep_inten); \
} while(0)
USB_DIEPxINTF
#define USB_DIEPxINTF(x)
Definition: usb_regs.h:85
USB_DIEPINTEN
#define USB_DIEPINTEN
Definition: usb_regs.h:68
USB_DIEPFEINTEN
#define USB_DIEPFEINTEN
Definition: usb_regs.h:74

Definition at line 584 of file usb_regs.h.

#define USB_DIEPFEINTEN REG32(((USBFS) + 0x0834U))

device IN endpoint FIFO empty interrupt enable register

Definition at line 74 of file usb_regs.h.

#define USB_DIEPINTEN REG32(((USBFS) + 0x0810U))

device IN endpoint common interrupt enable register

Definition at line 68 of file usb_regs.h.

#define USB_DIEPxCTL ( x ) REG32(((USBFS) + LOCATE_DIEPCTL(x)))

device IN endpoint-x control register

Definition at line 83 of file usb_regs.h.

#define USB_DIEPxINTF ( x ) REG32(((USBFS) + LOCATE_DIEPINTF(x)))

device IN endpoint-x interrupt flag register

Definition at line 85 of file usb_regs.h.

#define USB_DIEPxLEN ( x ) REG32(((USBFS) + LOCATE_DIEPLEN(x)))

device IN endpoint-x transfer length register

Definition at line 87 of file usb_regs.h.

#define USB_DIEPxTFLEN ( x ) REG32(((USBFS) + LOCATE_DIEPTFLEN(x)))

device IN endpoint transmit FIFO length register

Definition at line 51 of file usb_regs.h.

#define USB_DIEPxTFSTAT ( x ) REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x)))

device IN endpoint-x transmit FIFO status register

Definition at line 89 of file usb_regs.h.

#define USB_DOEP0CTL REG32(((USBFS) + 0x0B00U))

device OUT endpoint 0 control register

Definition at line 81 of file usb_regs.h.

#define USB_DOEP0LEN REG32(((USBFS) + 0x0B10U))

device OUT endpoint 0 transfer length register

Definition at line 82 of file usb_regs.h.

#define USB_DOEP1INTEN REG32(((USBFS) + 0x0884U))

device OUT endpoint 1 interrupt enable register

Definition at line 78 of file usb_regs.h.

#define USB_DOEP_INTR_READ | ( | x,
 |  | EpID
 | ) |
Value:
do { \
uint32_t out_epintf = USB_DOEPxINTF(EpID); \
(x) = out_epintf & USB_DOEPINTEN; \
} while(0)
USB_DOEPINTEN
#define USB_DOEPINTEN
Definition: usb_regs.h:69
USB_DOEPxINTF
#define USB_DOEPxINTF(x)
Definition: usb_regs.h:86

Definition at line 567 of file usb_regs.h.

#define USB_DOEPINTEN REG32(((USBFS) + 0x0814U))

device OUT endpoint common interrupt enable register

Definition at line 69 of file usb_regs.h.

#define USB_DOEPxCTL ( x ) REG32(((USBFS) + LOCATE_DOEPCTL(x)))

device OUT endpoint-x control register

Definition at line 84 of file usb_regs.h.

#define USB_DOEPxINTF ( x ) REG32(((USBFS) + LOCATE_DOEPINTF(x)))

device OUT endpoint-x interrupt flag register

Definition at line 86 of file usb_regs.h.

#define USB_DOEPxLEN ( x ) REG32(((USBFS) + LOCATE_DOEPLEN(x)))

device OUT endpoint-x transfer length register

Definition at line 88 of file usb_regs.h.

#define USB_DSTAT REG32(((USBFS) + 0x0808U))

device status register

Definition at line 67 of file usb_regs.h.

#define USB_DVBUSDT REG32(((USBFS) + 0x0828U))

device vbus discharge time register

Definition at line 72 of file usb_regs.h.

#define USB_DVBUSPT REG32(((USBFS) + 0x082CU))

device vbus pulsing time register

Definition at line 73 of file usb_regs.h.

#define USB_EVEN_FRAME ( ) (!(USB_HFINFR & 0x01U))

Definition at line 608 of file usb_regs.h.

#define USB_FIFO ( x ) (&REG32(((USBFS) + LOCATE_FIFO(x))))

FIFO memory

Definition at line 93 of file usb_regs.h.

#define USB_FSLSCLOCK_INIT ( ClockFreq ) (USB_HCTL &= ~HCTL_CLKSEL | (ClockFreq))

Definition at line 614 of file usb_regs.h.

#define USB_GAHBCS REG32(((USBFS) + 0x0008U))

global AHB control and status register

Definition at line 37 of file usb_regs.h.

#define USB_GCCFG REG32(((USBFS) + 0x0038U))

global core configuration register

Definition at line 48 of file usb_regs.h.

#define USB_GINTEN REG32(((USBFS) + 0x0018U))

global interrupt enable register

Definition at line 41 of file usb_regs.h.

#define USB_GINTF REG32(((USBFS) + 0x0014U))

global interrupt flag register

Definition at line 40 of file usb_regs.h.

#define USB_GLOBAL_INT_DISABLE ( ) (USB_GAHBCS &= ~GAHBCS_GINTEN)

Definition at line 545 of file usb_regs.h.

#define USB_GLOBAL_INT_ENABLE ( ) (USB_GAHBCS |= GAHBCS_GINTEN)

Definition at line 542 of file usb_regs.h.

#define USB_GOTGCS REG32(((USBFS) + 0x0000U))

global OTG control and status register

Definition at line 35 of file usb_regs.h.

#define USB_GOTGINTF REG32(((USBFS) + 0x0004U))

global OTG interrupt flag register

Definition at line 36 of file usb_regs.h.

#define USB_GRFLEN REG32(((USBFS) + 0x0024U))

global receive FIFO length register

Definition at line 44 of file usb_regs.h.

#define USB_GRSTATP REG32(((USBFS) + 0x0020U))

global receive status read and pop register

Definition at line 43 of file usb_regs.h.

#define USB_GRSTATR REG32(((USBFS) + 0x001CU))

global receive status read register

Definition at line 42 of file usb_regs.h.

#define USB_GRSTCTL REG32(((USBFS) + 0x0010U))

global reset control register

Definition at line 39 of file usb_regs.h.

#define USB_GUSBCS REG32(((USBFS) + 0x000CU))

global USB control and status register

Definition at line 38 of file usb_regs.h.

#define USB_HACHINT REG32(((USBFS) + 0x0414U))

host all channels interrupt register

Definition at line 57 of file usb_regs.h.

#define USB_HACHINTEN REG32(((USBFS) + 0x0418U))

host all channels interrupt enable register

Definition at line 58 of file usb_regs.h.

#define USB_HCHxCTL ( x ) REG32(((USBFS) + LOCATE_HCHCTL(x)))

host channel-x control register

Definition at line 60 of file usb_regs.h.

#define USB_HCHxINTEN ( x ) REG32(((USBFS) + LOCATE_HCHINTEN(x)))

host channel-x interrupt enable register

Definition at line 62 of file usb_regs.h.

#define USB_HCHxINTF ( x ) REG32(((USBFS) + LOCATE_HCHINTF(x)))

host channel-x interrupt flag register

Definition at line 61 of file usb_regs.h.

#define USB_HCHxLEN ( x ) REG32(((USBFS) + LOCATE_HCHLEN(x)))

host channel-x tranfer length register

Definition at line 63 of file usb_regs.h.

#define USB_HCTL REG32(((USBFS) + 0x0400U))

host control register

Definition at line 53 of file usb_regs.h.

#define USB_HFINFR REG32(((USBFS) + 0x0408U))

host frame information remaining register

Definition at line 55 of file usb_regs.h.

#define USB_HFT REG32(((USBFS) + 0x0404U))

host frame interval register

Definition at line 54 of file usb_regs.h.

#define USB_HNPTFLEN REG32(((USBFS) + 0x0028U))

host non-periodic transmit FIFO length register

Definition at line 45 of file usb_regs.h.

#define USB_HNPTFQSTAT REG32(((USBFS) + 0x002CU))

host non-periodic transmint FIFO/queue status register

Definition at line 47 of file usb_regs.h.

#define USB_HPCS REG32(((USBFS) + 0x0440U))

host port control and status register

Definition at line 59 of file usb_regs.h.

#define USB_HPTFLEN REG32(((USBFS) + 0x0100U))

host periodic transmit FIFO length register

Definition at line 50 of file usb_regs.h.

#define USB_HPTFQSTAT REG32(((USBFS) + 0x0410U))

host periodic transmit FIFO/queue status register

Definition at line 56 of file usb_regs.h.

#define USB_PORT_READ ( ) (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC))

Definition at line 611 of file usb_regs.h.

#define USB_PWRCLKCTL REG32(((USBFS) + 0x0E00U))

power and clock register

Definition at line 91 of file usb_regs.h.

#define USB_REMOTE_WAKEUP_RESET ( ) (USB_DCTL &= ~DCTL_RWKUP)

Definition at line 596 of file usb_regs.h.

#define USB_REMOTE_WAKEUP_SET ( ) (USB_DCTL |= DCTL_RWKUP)

Definition at line 593 of file usb_regs.h.

#define USB_SET_DEVADDR ( DevAddr ) (USB_DCFG |= (DevAddr) << 4U)

Definition at line 605 of file usb_regs.h.

#define USB_SOFT_DISCONNECT_DISABLE ( ) (USB_DCTL &= ~DCTL_SD)

Definition at line 602 of file usb_regs.h.

#define USB_SOFT_DISCONNECT_ENABLE ( ) (USB_DCTL |= DCTL_SD)

Definition at line 599 of file usb_regs.h.

#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U)

device external PHY full speed

Definition at line 499 of file usb_regs.h.

#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U)

device external PHY high speed

Definition at line 498 of file usb_regs.h.

#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U)

device internal PHY full speed

Definition at line 500 of file usb_regs.h.

#define USBFS USBFS_BASE

base address of USBFS registers

Definition at line 17 of file usb_regs.h.

Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_std.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
Data Structures | Macros
usb_std.h File Reference

USB 2.0 standard defines. More...

#include "usb_conf.h"

Go to the source code of this file.

Data Structures

union | usb_setup_union
struct | usb_setup_union::_setup_packet_struct
struct | usb_descriptor_header_struct
struct | usb_descriptor_device_struct
struct | usb_descriptor_configuration_struct
struct | usb_descriptor_interface_struct
struct | usb_descriptor_endpoint_struct
struct | usb_descriptor_language_id_struct

Macros

#define | USB_DEV_QUALIFIER_DESC_LEN 0x0AU
#define | USB_DEV_DESC_LEN 0x12U
#define | USB_CFG_DESC_LEN 0x09U
#define | USB_IF_DESC_LEN 0x09U
#define | USB_EP_DESC_LEN 0x07U
#define | USB_OTG_DESC_LEN 0x03U
#define | USB_DIR_MASK 0x80U
#define | USB_DIR_OUT 0x00U
#define | USB_DIR_IN 0x80U
#define | USB_STANDARD_REQ 0x00U
#define | USB_CLASS_REQ 0x20U
#define | USB_VENDOR_REQ 0x40U
#define | USB_REQ_MASK 0x60U
#define | USB_REQTYPE_DEVICE 0x00U
#define | USB_REQTYPE_INTERFACE 0x01U
#define | USB_REQTYPE_ENDPOINT 0x02U
#define | USB_REQTYPE_MASK 0x03U
#define | USBREQ_GET_STATUS 0x00U
#define | USBREQ_CLEAR_FEATURE 0x01U
#define | USBREQ_SET_FEATURE 0x03U
#define | USBREQ_SET_ADDRESS 0x05U
#define | USBREQ_GET_DESCRIPTOR 0x06U
#define | USBREQ_SET_DESCRIPTOR 0x07U
#define | USBREQ_GET_CONFIGURATION 0x08U
#define | USBREQ_SET_CONFIGURATION 0x09U
#define | USBREQ_GET_INTERFACE 0x0AU
#define | USBREQ_SET_INTERFACE 0x0BU
#define | USBREQ_SYNCH_FRAME 0x0CU
#define | USB_DESCTYPE_DEVICE 0x01U
#define | USB_DESCTYPE_CONFIGURATION 0x02U
#define | USB_DESCTYPE_STRING 0x03U
#define | USB_DESCTYPE_INTERFACE 0x04U
#define | USB_DESCTYPE_ENDPOINT 0x05U
#define | USB_DESCTYPE_DEVICE_QUALIFIER 0x06U
#define | USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U
#define | USB_DESCTYPE_INTERFACE_POWER 0x08U
#define | USB_DESCTYPE_HID 0x21U
#define | USB_DESCTYPE_HID_REPORT 0x22U
#define | USB_DEVDESC_SIZE 18U
#define | USB_CFGDESC_SIZE 9U
#define | USB_INTDESC_SIZE 9U
#define | USB_EPDESC_SIZE 7U
#define | USB_DEVDESC ((USB_DESCTYPE_DEVICE << 8U) & 0xFF00U)
#define | USB_CFGDESC ((USB_DESCTYPE_CONFIGURATION << 8U) & 0xFF00U)
#define | USB_STRDESC ((USB_DESCTYPE_STRING << 8U) & 0xFF00U)
#define | USB_INTDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U)
#define | USB_EPDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U)
#define | USB_DEVQUADESC ((USB_DESCTYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U)
#define | USB_OSPCFGDESC ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U)
#define | USB_INTPWRDESC ((USB_DESCTYPE_INTERFACE_POWER << 8U) & 0xFF00U)
#define | USB_HIDREPDESC ((USB_DESCTYPE_HID_REPORT << 8U) & 0xFF00U)
#define | USB_HIDDESC ((USB_DESCTYPE_HID << 8U) & 0xFF00U)
#define | SWAPBYTE(addr)
#define | USB_MSC_CLASS 0x08U
#define | USB_HID_CLASS 0x03U
#define | HID_BOOT_CODE 0x01U
#define | HID_KEYBRD_BOOT_CODE 0x01U
#define | HID_MOUSE_BOOT_CODE 0x02U
#define | DATA_STAGE_TIMEOUT 5000U
#define | NODATA_STAGE_TIMEOUT 50U
#define | USBH_CFG_DESC_SET_SIZE

Detailed Description

USB 2.0 standard defines.

Definition in file usb_std.h.

Macro Definition Documentation

#define DATA_STAGE_TIMEOUT 5000U

USB data stage timeout

Definition at line 99 of file usb_std.h.

#define HID_BOOT_CODE 0x01U

USB HID boot code

Definition at line 93 of file usb_std.h.

#define HID_KEYBRD_BOOT_CODE 0x01U

USB HID keyboard boot code

Definition at line 94 of file usb_std.h.

#define HID_MOUSE_BOOT_CODE 0x02U

USB HID mouse boot code

Definition at line 95 of file usb_std.h.

#define NODATA_STAGE_TIMEOUT 50U

USB no data stage timeout

Definition at line 100 of file usb_std.h.

#define SWAPBYTE ( addr )
Value:
(((uint16_t)(*((uint8_t *)(addr)))) + \
(uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))

Definition at line 85 of file usb_std.h.

#define USB_CFG_DESC_LEN 0x09U

USB device configuration descriptor length

Definition at line 19 of file usb_std.h.

#define USB_CFGDESC ((USB_DESCTYPE_CONFIGURATION << 8U) & 0xFF00U)

USB configuration operation marco

Definition at line 75 of file usb_std.h.

#define USB_CFGDESC_SIZE 9U

USB configure descriptor size

Definition at line 68 of file usb_std.h.

#define USB_CLASS_REQ 0x20U

USB class request

Definition at line 31 of file usb_std.h.

#define USB_DESCTYPE_CONFIGURATION 0x02U

USB configuration descriptor type

Definition at line 56 of file usb_std.h.

#define USB_DESCTYPE_DEVICE 0x01U

USB device descriptor type

Definition at line 55 of file usb_std.h.

#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U

USB device qualtfier descriptor type

Definition at line 60 of file usb_std.h.

#define USB_DESCTYPE_ENDPOINT 0x05U

USB endpoint descriptor type

Definition at line 59 of file usb_std.h.

#define USB_DESCTYPE_HID 0x21U

USB HID descriptor type

Definition at line 64 of file usb_std.h.

#define USB_DESCTYPE_HID_REPORT 0x22U

USB HID report descriptor type

Definition at line 65 of file usb_std.h.

#define USB_DESCTYPE_INTERFACE 0x04U

USB interface descriptor type

Definition at line 58 of file usb_std.h.

#define USB_DESCTYPE_INTERFACE_POWER 0x08U

USB interface power descriptor type

Definition at line 62 of file usb_std.h.

#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U

USB other speed configuration descriptor type

Definition at line 61 of file usb_std.h.

#define USB_DESCTYPE_STRING 0x03U

USB string descriptor type

Definition at line 57 of file usb_std.h.

#define USB_DEV_DESC_LEN 0x12U

USB device descriptor length

Definition at line 18 of file usb_std.h.

#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU

USB device qualifier descriptor length

Definition at line 17 of file usb_std.h.

#define USB_DEVDESC ((USB_DESCTYPE_DEVICE << 8U) & 0xFF00U)

USB device operation marco

Definition at line 74 of file usb_std.h.

#define USB_DEVDESC_SIZE 18U

USB device descriptor size

Definition at line 67 of file usb_std.h.

#define USB_DEVQUADESC ((USB_DESCTYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U)

USB device qualifier operation marco

Definition at line 79 of file usb_std.h.

#define USB_DIR_IN 0x80U

USB transfer IN direction

Definition at line 27 of file usb_std.h.

#define USB_DIR_MASK 0x80U

USB transfer direction mask

Definition at line 25 of file usb_std.h.

#define USB_DIR_OUT 0x00U

USB transfer OUT direction

Definition at line 26 of file usb_std.h.

#define USB_EP_DESC_LEN 0x07U

USB device endpoint descriptor length

Definition at line 21 of file usb_std.h.

#define USB_EPDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U)

USB endpoint operation marco

Definition at line 78 of file usb_std.h.

#define USB_EPDESC_SIZE 7U

USB endpoint descriptor size

Definition at line 70 of file usb_std.h.

#define USB_HID_CLASS 0x03U

USB HID class

Definition at line 90 of file usb_std.h.

#define USB_HIDDESC ((USB_DESCTYPE_HID << 8U) & 0xFF00U)

USB HID operation marco

Definition at line 83 of file usb_std.h.

#define USB_HIDREPDESC ((USB_DESCTYPE_HID_REPORT << 8U) & 0xFF00U)

USB HID report operation marco

Definition at line 82 of file usb_std.h.

#define USB_IF_DESC_LEN 0x09U

USB device interface descriptor length

Definition at line 20 of file usb_std.h.

#define USB_INTDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U)

USB interface operation marco

Definition at line 77 of file usb_std.h.

#define USB_INTDESC_SIZE 9U

USB interface descriptor size

Definition at line 69 of file usb_std.h.

#define USB_INTPWRDESC ((USB_DESCTYPE_INTERFACE_POWER << 8U) & 0xFF00U)

USB interface power operation marco

Definition at line 81 of file usb_std.h.

#define USB_MSC_CLASS 0x08U

USB MSC class

Definition at line 89 of file usb_std.h.

#define USB_OSPCFGDESC ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U)

USB other speed configuration operation marco

Definition at line 80 of file usb_std.h.

#define USB_OTG_DESC_LEN 0x03U

USB device OTG descriptor length

Definition at line 22 of file usb_std.h.

#define USB_REQ_MASK 0x60U

USB request mask

Definition at line 33 of file usb_std.h.

#define USB_REQTYPE_DEVICE 0x00U

USB device request type

Definition at line 36 of file usb_std.h.

#define USB_REQTYPE_ENDPOINT 0x02U

USB endpoint request type

Definition at line 38 of file usb_std.h.

#define USB_REQTYPE_INTERFACE 0x01U

USB interface request type

Definition at line 37 of file usb_std.h.

#define USB_REQTYPE_MASK 0x03U

USB request type mask

Definition at line 39 of file usb_std.h.

#define USB_STANDARD_REQ 0x00U

USB standard request

Definition at line 30 of file usb_std.h.

#define USB_STRDESC ((USB_DESCTYPE_STRING << 8U) & 0xFF00U)

USB string operation marco

Definition at line 76 of file usb_std.h.

#define USB_VENDOR_REQ 0x40U

USB vebdor request

Definition at line 32 of file usb_std.h.

#define USBH_CFG_DESC_SET_SIZE
Value:
(USB_CFGDESC_SIZE + USB_INTDESC_SIZE \
+ (USBH_MAX_EP_NUM * USB_EPDESC_SIZE))
USB_EPDESC_SIZE
#define USB_EPDESC_SIZE
Definition: usb_std.h:70
USB_INTDESC_SIZE
#define USB_INTDESC_SIZE
Definition: usb_std.h:69
USB_CFGDESC_SIZE
#define USB_CFGDESC_SIZE
Definition: usb_std.h:68

USB host set configuration descriptor size

Definition at line 102 of file usb_std.h.

#define USBREQ_CLEAR_FEATURE 0x01U

USB clear feature request

Definition at line 43 of file usb_std.h.

#define USBREQ_GET_CONFIGURATION 0x08U

USB get configuration request

Definition at line 48 of file usb_std.h.

#define USBREQ_GET_DESCRIPTOR 0x06U

USB get descriptor request

Definition at line 46 of file usb_std.h.

#define USBREQ_GET_INTERFACE 0x0AU

USB get interface request

Definition at line 50 of file usb_std.h.

#define USBREQ_GET_STATUS 0x00U

USB get status request

Definition at line 42 of file usb_std.h.

#define USBREQ_SET_ADDRESS 0x05U

USB set address request

Definition at line 45 of file usb_std.h.

#define USBREQ_SET_CONFIGURATION 0x09U

USB set configuration request

Definition at line 49 of file usb_std.h.

#define USBREQ_SET_DESCRIPTOR 0x07U

USB set descriptor request

Definition at line 47 of file usb_std.h.

#define USBREQ_SET_FEATURE 0x03U

USB set feature request

Definition at line 44 of file usb_std.h.

#define USBREQ_SET_INTERFACE 0x0BU

USB set interface request

Definition at line 51 of file usb_std.h.

#define USBREQ_SYNCH_FRAME 0x0CU

USB synchronize frame request

Definition at line 52 of file usb_std.h.

Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbd_core.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
Macros | Functions
usbd_core.h File Reference

USB device mode core driver header file. More...

#include "usbd_conf.h"
#include "usb_core.h"
#include "usbd_std.h"

Go to the source code of this file.

Macros

#define | USB_STATUS_DEFAULT 1U /* default status */
#define | USB_STATUS_ADDRESSED 2U /* addressed status */
#define | USB_STATUS_CONFIGURED 3U /* configured status */
#define | USB_STATUS_SUSPENDED 4U /* suspended status */

Functions

void | usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initailizes the USB device-mode handler stack More...
void | usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc)
endpoint initialization More...
void | usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr)
endpoint deinitialize More...
void | usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data More...
void | usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
endpoint prepare to transmit data More...
usbd_status_enum | usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
transmit data on the control channel More...
usbd_status_enum | usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
receive data on the control channel More...
usbd_status_enum | usbd_ctlstatus_tx (usb_core_handle_struct *pudev)
transmit status on the control channel More...
usbd_status_enum | usbd_ctlstatus_rx (usb_core_handle_struct *pudev)
receive status on the control channel More...
void | usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status More...
void | usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status More...
void | usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr)
flushes the FIFOs More...
uint16_t | usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num)
get the received data length More...

Detailed Description

USB device mode core driver header file.

Definition in file usbd_core.h.

Macro Definition Documentation

#define USB_STATUS_ADDRESSED 2U /* addressed status */

Definition at line 21 of file usbd_core.h.

#define USB_STATUS_CONFIGURED 3U /* configured status */

Definition at line 22 of file usbd_core.h.

#define USB_STATUS_DEFAULT 1U /* default status */

Definition at line 20 of file usbd_core.h.

#define USB_STATUS_SUSPENDED 4U /* suspended status */

Definition at line 23 of file usbd_core.h.

Function Documentation

usbd_status_enum usbd_ctlrx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | pbuf,
 |  | uint16_t | len
 | ) |  |

receive data on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[in] | pbuf | pointer to buffer
[in] | len | buffer length
[out] | none
Return values
usb device operation status

Definition at line 333 of file usbd_core.c.

334 {
335 pudev->dev.sum_len = len;
336 pudev->dev.remain_len = len;
337 pudev->dev.ctl_status = USB_CTRL_DATA_OUT;
338
339 usbd_ep_rx (pudev, 0U, pbuf, len);
340
341 return USBD_OK;
342 }
USBD_OK
Definition: usb_core.h:74
USB_CTRL_DATA_OUT
Definition: usb_core.h:85
usbd_ep_rx
void usbd_ep_rx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:161
usbd_status_enum usbd_ctlstatus_rx ( usb_core_handle_struct * pudev )

receive status on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
usb device operation status

Definition at line 367 of file usbd_core.c.

368 {
369 pudev->dev.ctl_status = USB_CTRL_STATUS_OUT;
370
371 usbd_ep_rx (pudev, 0U, NULL, 0U);
372
373 usb_ep0_startout(pudev);
374
375 return USBD_OK;
376 }
USB_CTRL_STATUS_OUT
Definition: usb_core.h:87
USBD_OK
Definition: usb_core.h:74
NULL
#define NULL
Definition: usb_defines.h:18
usbd_ep_rx
void usbd_ep_rx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:161
usbd_status_enum usbd_ctlstatus_tx ( usb_core_handle_struct * pudev )

transmit status on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
usb device operation status

Definition at line 350 of file usbd_core.c.

351 {
352 pudev->dev.ctl_status = USB_CTRL_STATUS_IN;
353
354 usbd_ep_tx (pudev, 0U, NULL, 0U);
355
356 usb_ep0_startout(pudev);
357
358 return USBD_OK;
359 }
USBD_OK
Definition: usb_core.h:74
USB_CTRL_STATUS_IN
Definition: usb_core.h:86
NULL
#define NULL
Definition: usb_defines.h:18
usbd_ep_tx
void usbd_ep_tx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:230
usbd_status_enum usbd_ctltx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | pbuf,
 |  | uint16_t | len
 | ) |  |

transmit data on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[in] | pbuf | pointer to buffer
[in] | len | buffer length
[out] | none
Return values
usb device operation status

Definition at line 312 of file usbd_core.c.

313 {
314 usbd_status_enum ret = USBD_OK;
315
316 pudev->dev.sum_len = len;
317 pudev->dev.remain_len = len;
318 pudev->dev.ctl_status = USB_CTRL_DATA_IN;
319
320 usbd_ep_tx (pudev, 0U, pbuf, (uint32_t)len);
321
322 return ret;
323 }
USBD_OK
Definition: usb_core.h:74
USB_CTRL_DATA_IN
Definition: usb_core.h:84
usbd_status_enum
usbd_status_enum
Definition: usb_core.h:72
usbd_ep_tx
void usbd_ep_tx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:230
void usbd_ep_clear_stall | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

clear endpoint stalled status

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 415 of file usbd_core.c.

416 {
417 usb_ep_struct *ep;
418 uint8_t ep_num = ep_addr & 0x7FU;
419 __IO uint32_t devepctl = 0U;
420
421 if(ep_addr >> 7){
422 ep = &pudev->dev.in_ep[ep_num];
423
424 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
425
426 /* clear the IN endpoint stall bits */
427 devepctl &= ~DEPCTL_STALL;
428
429 if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) {
430 devepctl |= DEPCTL_SEVNFRM;
431 }
432
433 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
434 } else {
435 ep = &pudev->dev.out_ep[ep_num];
436
437 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
438
439 /* clear the OUT endpoint stall bits */
440 devepctl &= ~DEPCTL_STALL;
441
442 if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) {
443 devepctl |= DEPCTL_SEVNFRM;
444 }
445
446 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
447 }
448 }
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:54
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:101
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:83
usb_ep_struct
Definition: usb_core.h:99
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:84
DEPCTL_STALL
#define DEPCTL_STALL
Definition: usb_regs.h:440
DEPCTL_SEVNFRM
#define DEPCTL_SEVNFRM
Definition: usb_regs.h:435
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:53
void usbd_ep_deinit | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

endpoint deinitialize

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 133 of file usbd_core.c.

134 {
135 uint32_t devepinten = 0U;
136 uint8_t ep_num = ep_addr & 0x7FU;
137
138 if (ep_addr >> 7) {
139 devepinten |= 1U << ep_num;
140
141 USB_DIEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT;
142 } else {
143 devepinten |= (1U << ep_num) << 16U;
144
145 USB_DOEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT;
146 }
147
148 /* disable the interrupts for this endpoint */
149 USB_DAEPINTEN &= ~devepinten;
150 }
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:71
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:83
DEPCTL_EPACT
#define DEPCTL_EPACT
Definition: usb_regs.h:446
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:84
void usbd_ep_fifo_flush | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

flushes the FIFOs

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 457 of file usbd_core.c.

458 {
459 if (ep_addr >> 7) {
460 usb_txfifo_flush(pudev, ep_addr & 0x7FU);
461 } else {
462 usb_rxfifo_flush(pudev);
463 }
464 }
usb_txfifo_flush
usb_status_enum usb_txfifo_flush(usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs
Definition: usb_core.c:208
usb_rxfifo_flush
usb_status_enum usb_rxfifo_flush(usb_core_handle_struct *pudev)
flush the entire Rx FIFO
Definition: usb_core.c:236
void usbd_ep_init | ( | usb_core_handle_struct * | pudev,
 |  | const usb_descriptor_endpoint_struct * | ep_desc
 | ) |  |

endpoint initialization

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_desc | pointer to usb endpoint descriptor
[out] | none
Return values
none

Definition at line 66 of file usbd_core.c.

67 {
68 usb_ep_struct *ep;
69 usb_dir_enum ep_dir;
70
71 uint32_t devepinten = 0U;
72 uint32_t devepctl = 0U;
73
74 uint8_t ep_num = ep_desc->bEndpointAddress & 0x7FU;
75 uint8_t ep_type = ep_desc->bmAttributes & USB_EPTYPE_MASK;
76 uint16_t ep_mps = ep_desc->wMaxPacketSize;
77
78 if (ep_desc->bEndpointAddress >> 7) {
79 ep = &pudev->dev.in_ep[ep_num];
80
81 devepinten |= 1U << ep_num;
82 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
83
84 ep_dir = USB_TX;
85 } else {
86 ep = &pudev->dev.out_ep[ep_num];
87
88 devepinten |= (1U << ep_num) << 16;
89 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
90
91 ep_dir = USB_RX;
92 }
93
94 /* if the endpoint is not active, need change the endpoint control register */
95 if (!(devepctl & DEPCTL_EPACT)) {
96 devepctl &= ~DEPCTL_MPL;
97 devepctl |= ep_mps;
98
99 devepctl &= ~DEPCTL_EPTYPE;
100 devepctl |= (uint32_t)ep_type << 18;
101
102 if (USB_TX == ep_dir) {
103 devepctl &= ~DIEPCTL_TXFNUM;
104 devepctl |= (uint32_t)ep_num << 22;
105 }
106
107 devepctl |= DEPCTL_SD0PID;
108 devepctl |= DEPCTL_EPACT;
109 }
110
111 if (USB_TX == ep_dir) {
112 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
113 } else if (USB_RX == ep_dir) {
114 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
115 } else {
116 /* no operation */
117 }
118
119 ep->endp_mps = ep_mps;
120 ep->endp_type = ep_type;
121
122 /* enable the interrupts for this endpoint */
123 USB_DAEPINTEN |= devepinten;
124 }
usb_descriptor_endpoint_struct::bmAttributes
uint8_t bmAttributes
Definition: usb_std.h:175
USB_TX
Definition: usb_core.h:95
DEPCTL_EPTYPE
#define DEPCTL_EPTYPE
Definition: usb_regs.h:442
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:71
usb_descriptor_endpoint_struct::bEndpointAddress
uint8_t bEndpointAddress
Definition: usb_std.h:174
USB_EPTYPE_MASK
#define USB_EPTYPE_MASK
Definition: usb_defines.h:55
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:101
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:103
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:83
DEPCTL_EPACT
#define DEPCTL_EPACT
Definition: usb_regs.h:446
USB_RX
Definition: usb_core.h:94
usb_ep_struct
Definition: usb_core.h:99
usb_dir_enum
usb_dir_enum
Definition: usb_core.h:92
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:84
DEPCTL_MPL
#define DEPCTL_MPL
Definition: usb_regs.h:447
usb_descriptor_endpoint_struct::wMaxPacketSize
uint16_t wMaxPacketSize
Definition: usb_std.h:176
DIEPCTL_TXFNUM
#define DIEPCTL_TXFNUM
Definition: usb_regs.h:439
DEPCTL_SD0PID
#define DEPCTL_SD0PID
Definition: usb_regs.h:436
void usbd_ep_rx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pbuf,
 |  | uint16_t | buf_len
 | ) |  |

endpoint prepare to receive data

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[in] | pbuf | pointer to buffer
[in] | buf_len | buffer length
[out] | none
Return values
none

Definition at line 161 of file usbd_core.c.

162 {
163 usb_ep_struct *ep;
164 uint8_t ep_num = ep_addr & 0x7FU;
165 uint32_t devepctl = 0U, devepxlen = 0U;
166
167 ep = &pudev->dev.out_ep[ep_num];
168
169 /* setup and start the Xfer */
170 ep->xfer_buff = pbuf;
171 ep->xfer_len = buf_len;
172 ep->xfer_count = 0U;
173
174 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
175 devepxlen = USB_DOEPxLEN((uint16_t)ep_num);
176
177 devepxlen &= ~DEPLEN_TLEN;
178 devepxlen &= ~DEPLEN_PCNT;
179
180 /* zero length packet */
181 if (0U == ep->xfer_len) {
182 /* set the transfer length to max packet size */
183 devepxlen |= ep->endp_mps;
184
185 /* set the transfer packet count to 1 */
186 devepxlen |= 1U << 19U;
187 } else {
188
189 if (0U == ep_num) {
190 /* set the transfer length to max packet size */
191 devepxlen |= ep->endp_mps;
192
193 /* set the transfer packet count to 1 */
194 devepxlen |= 1U << 19U;
195 } else {
196 /* configure the transfer size and packet count as follows:
197 * pktcnt = N
198 * xfersize = N * maxpacket
199 */
200 devepxlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U;
201 devepxlen |= ((devepxlen & DEPLEN_PCNT) >> 19U) * ep->endp_mps;
202 }
203 }
204
205 USB_DOEPxLEN((uint16_t)ep_num) = devepxlen;
206
207 if (USB_EPTYPE_ISOC == ep->endp_type) {
208 if (ep->endp_frame) {
209 devepctl |= DEPCTL_SODDFRM;
210 } else {
211 devepctl |= DEPCTL_SEVNFRM;
212 }
213 }
214
215 /* enable the endpoint and clear the NAK */
216 devepctl |= DEPCTL_EPEN | DEPCTL_CNAK;
217
218 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
219 }
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:52
usb_ep_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:108
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:431
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:101
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:103
usb_ep_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:107
usb_ep_struct::endp_frame
uint8_t endp_frame
Definition: usb_core.h:102
DEPLEN_TLEN
#define DEPLEN_TLEN
Definition: usb_regs.h:480
DEPLEN_PCNT
#define DEPLEN_PCNT
Definition: usb_regs.h:479
usb_ep_struct
Definition: usb_core.h:99
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:84
USB_DOEPxLEN
#define USB_DOEPxLEN(x)
Definition: usb_regs.h:88
DEPCTL_CNAK
#define DEPCTL_CNAK
Definition: usb_regs.h:438
DEPCTL_SEVNFRM
#define DEPCTL_SEVNFRM
Definition: usb_regs.h:435
DEPCTL_SODDFRM
#define DEPCTL_SODDFRM
Definition: usb_regs.h:433
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:106
void usbd_ep_stall | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

set an endpoint to STALL status

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 385 of file usbd_core.c.

386 {
387 uint8_t ep_num = ep_addr & 0x7FU;
388 __IO uint32_t devepctl = 0U;
389
390 if (ep_addr >> 7U) {
391 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
392
393 /* set the endpoint disable bit */
394 if (devepctl & DEPCTL_EPEN) {
395 devepctl |= DEPCTL_EPD;
396 }
397
398 /* set the endpoint stall bit */
399 devepctl |= DEPCTL_STALL;
400
401 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
402 } else {
403 /* set the endpoint stall bit */
404 USB_DOEPxCTL((uint16_t)ep_num) |= DEPCTL_STALL;
405 }
406 }
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:431
DEPCTL_EPD
#define DEPCTL_EPD
Definition: usb_regs.h:432
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:83
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:84
DEPCTL_STALL
#define DEPCTL_STALL
Definition: usb_regs.h:440
void usbd_ep_tx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pbuf,
 |  | uint32_t | buf_len
 | ) |  |

endpoint prepare to transmit data

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[in] | pbuf | pointer to buffer
[in] | len | buffer length
[out] | none
Return values
none

Definition at line 230 of file usbd_core.c.

231 {
232 usb_ep_struct *ep;
233 uint8_t ep_num = ep_addr & 0x7FU;
234 __IO uint32_t devepctl = 0U;
235 __IO uint32_t deveplen = 0U;
236
237 ep = &pudev->dev.in_ep[ep_num];
238
239 /* setup and start the transfer */
240 ep->xfer_buff = pbuf;
241 ep->xfer_len = buf_len;
242 ep->xfer_count = 0U;
243
244 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
245 deveplen = USB_DIEPxLEN((uint16_t)ep_num);
246
247 /* clear transfer length to 0 */
248 deveplen &= ~DEPLEN_TLEN;
249
250 /* clear transfer packet to 0 */
251 deveplen &= ~DEPLEN_PCNT;
252
253 /* zero length packet */
254 if (0U == ep->xfer_len) {
255 /* set transfer packet count to 1 */
256 deveplen |= 1U << 19U;
257 } else {
258 if (0U == ep_num) {
259 if (ep->xfer_len > ep->endp_mps) {
260 ep->xfer_len = ep->endp_mps;
261 }
262
263 deveplen |= 1U << 19U;
264 } else {
265 deveplen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U;
266 }
267
268 /* configure the transfer size and packet count as follows:
269 * xfersize = N * maxpacket + short_packet
270 * pktcnt = N + (short_packet exist ? 1 : 0)
271 */
272 deveplen |= ep->xfer_len;
273
274 if (USB_EPTYPE_ISOC == ep->endp_type) {
275 deveplen |= DIEPLEN_MCNT & (1U << 29U);
276 }
277 }
278
279 USB_DIEPxLEN((uint16_t)ep_num) = deveplen;
280
281 if (USB_EPTYPE_ISOC == ep->endp_type) {
282 if (0U == (((USB_DSTAT & DSTAT_FNRSOF) >> 8U) & 0x1U)) {
283 devepctl |= DEPCTL_SODDFRM;
284 } else {
285 devepctl |= DEPCTL_SEVNFRM;
286 }
287 }
288
289 /* enable the endpoint and clear the NAK */
290 devepctl |= DEPCTL_EPEN | DEPCTL_CNAK;
291
292 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
293
294 if (USB_EPTYPE_ISOC != ep->endp_type) {
295 /* enable the Tx FIFO empty interrupt for this endpoint */
296 if (ep->xfer_len > 0U) {
297 USB_DIEPFEINTEN |= 1U << ep_num;
298 }
299 } else {
300 usb_fifo_write(ep->xfer_buff, ep_num, (uint16_t)ep->xfer_len);
301 }
302 }
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:52
usb_ep_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:108
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:431
usb_fifo_write
usb_status_enum usb_fifo_write(uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint
Definition: usb_core.c:79
DIEPLEN_MCNT
#define DIEPLEN_MCNT
Definition: usb_regs.h:478
USB_DIEPxLEN
#define USB_DIEPxLEN(x)
Definition: usb_regs.h:87
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:101
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:103
usb_ep_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:107
DEPLEN_TLEN
#define DEPLEN_TLEN
Definition: usb_regs.h:480
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:83
DEPLEN_PCNT
#define DEPLEN_PCNT
Definition: usb_regs.h:479
usb_ep_struct
Definition: usb_core.h:99
USB_DSTAT
#define USB_DSTAT
Definition: usb_regs.h:67
DSTAT_FNRSOF
#define DSTAT_FNRSOF
Definition: usb_regs.h:355
USB_DIEPFEINTEN
#define USB_DIEPFEINTEN
Definition: usb_regs.h:74
DEPCTL_CNAK
#define DEPCTL_CNAK
Definition: usb_regs.h:438
DEPCTL_SEVNFRM
#define DEPCTL_SEVNFRM
Definition: usb_regs.h:435
DEPCTL_SODDFRM
#define DEPCTL_SODDFRM
Definition: usb_regs.h:433
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:106
void usbd_init | ( | usb_core_handle_struct * | pudev,
 |  | usb_core_id_enum | core_id
 | ) |  |

initailizes the USB device-mode handler stack

Parameters
[in] | pudev | pointer to usb device instance
[in] | core_id | USB core ID
[out] | none
Return values
none

Definition at line 22 of file usbd_core.c.

23 {
24 /* select USB core */
25 usb_core_select (pudev, core_id);
26
27 pudev->dev.status = USB_STATUS_DEFAULT;
28
29 /* disable USB global interrupt */
30 USB_GLOBAL_INT_DISABLE();
31
32 /* init the core (common init.) */
33 usb_core_init(pudev);
34
35 /* force device mode*/
36 usb_mode_set(pudev, DEVICE_MODE);
37
38 /* set device disconnect */
39 USB_SOFT_DISCONNECT_ENABLE();
40
41 if ((void *)0 != pudev->mdelay) {
42 pudev->mdelay(3U);
43 }
44
45 /* init device */
46 usb_devcore_init(pudev);
47
48 /* set device Connect */
49 USB_SOFT_DISCONNECT_DISABLE();
50
51 if ((void *)0 != pudev->mdelay) {
52 pudev->mdelay(3U);
53 }
54
55 /* enable USB global interrupt */
56 USB_GLOBAL_INT_ENABLE();
57 }
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:125
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:266
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:217
USB_SOFT_DISCONNECT_DISABLE
#define USB_SOFT_DISCONNECT_DISABLE()
Definition: usb_regs.h:602
USB_GLOBAL_INT_DISABLE
#define USB_GLOBAL_INT_DISABLE()
Definition: usb_regs.h:545
USB_GLOBAL_INT_ENABLE
#define USB_GLOBAL_INT_ENABLE()
Definition: usb_regs.h:542
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:167
USB_SOFT_DISCONNECT_ENABLE
#define USB_SOFT_DISCONNECT_ENABLE()
Definition: usb_regs.h:599
USB_STATUS_DEFAULT
#define USB_STATUS_DEFAULT
Definition: usbd_core.h:20
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:47
uint16_t usbd_rxcount_get | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_num
 | ) |  |

get the received data length

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_num | endpoint identifier which is in (0..3)
[out] | none
Return values
received data length

Definition at line 473 of file usbd_core.c.

474 {
475 return (uint16_t)pudev->dev.out_ep[ep_num].xfer_count;
476 }
Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbd_int.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
Data Structures | Functions | Variables
usbd_int.h File Reference

USB device mode interrupt handler header file. More...

#include "usbd_core.h"

Go to the source code of this file.

Data Structures

struct usbd_int_cb_struct

Functions

uint32_t usbd_isr (usb_core_handle_struct *pudev)
USB device-mode interrupts global service routine handler. More...

Variables

usbd_int_cb_struct * usbd_int_fops

Detailed Description

USB device mode interrupt handler header file.

Definition in file usbd_int.h.

Function Documentation

uint32_t usbd_isr ( usb_core_handle_struct * pudev )

USB device-mode interrupts global service routine handler.

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
operation status

Definition at line 57 of file usbd_int.c.

58 {
59 uint32_t retval = 0U;
60 uint32_t int_status = 0U, gintf = USB_GINTF, ginten = USB_GINTEN;
61
62 /* ensure the core is in device mode */
63 if (DEVICE_MODE == USB_CURRENT_MODE_GET()) {
64 int_status = gintf & ginten;
65
66 /* there are no interrupts, avoid spurious interrupt */
67 if (!int_status) {
68 return 0U;
69 }
70
71 /* OUT endpoints interrupts */
72 if (int_status & GINTF_OEPIF) {
73 retval |= usbd_intf_outep(pudev);
74 }
75
76 /* IN endpoints interrupts */
77 if (int_status & GINTF_IEPIF) {
78 retval |= usbd_intf_inep(pudev);
79 }
80
81 /* mode mismatch interrupt */
82 if (int_status & GINTF_MFIF) {
83 /* clear interrupt */
84 USB_GINTF = GINTF_MFIF;
85 }
86
87 /* early suspend interrupt */
88 if (int_status & GINTF_ESP) {
89 retval |= usbd_intf_earlysuspend(pudev);
90 }
91
92 /* suspend interrupt */
93 if (int_status & GINTF_SP) {
94 retval |= usbd_intf_suspend(pudev);
95 }
96
97 /* wakeup interrupt */
98 if (int_status & GINTF_WKUPIF) {
99 retval |= usbd_intf_resume(pudev);
100 }
101
102 /* start of frame interrupt */
103 if (int_status & GINTF_SOF) {
104 retval |= usbd_intf_sof(pudev);
105 }
106
107 /* reveive fifo not empty interrupt */
108 if (int_status & GINTF_RXFNEIF) {
109 retval |= usbd_intf_rxfifo(pudev);
110 }
111
112 /* USB reset interrupt */
113 if (int_status & GINTF_RST) {
114 retval |= usbd_intf_reset(pudev);
115 }
116
117 /* enumeration has been finished interrupt */
118 if (int_status & GINTF_ENUMF) {
119 retval |= usbd_intf_enumfinish(pudev);
120 }
121
122 /* incomplete synchronization in transfer interrupt*/
123 if (int_status & GINTF_ISOINCIF) {
124 retval |= usbd_intf_isoinincomplete(pudev);
125 }
126
127 /* incomplete synchronization out transfer interrupt*/
128 if (int_status & GINTF_ISOONCIF) {
129 retval |= usbd_intf_isooutincomplete(pudev);
130 }
131
132 #ifdef VBUS_SENSING_ENABLED
133
134 /* session request interrupt */
135 if (int_status & GINTF_SESIF) {
136 retval |= usbd_intf_sessionrequest(pudev);
137 }
138
139 /* OTG mode interrupt */
140 if (int_status & GINTF_OTGIF) {
141 retval |= usbd_intf_otg(pudev);
142 }
143 #endif /* VBUS_SENSING_ENABLED */
144 }
145
146 return retval;
147 }
GINTF_IEPIF
#define GINTF_IEPIF
Definition: usb_regs.h:155
GINTF_RXFNEIF
#define GINTF_RXFNEIF
Definition: usb_regs.h:165
GINTF_ISOINCIF
#define GINTF_ISOINCIF
Definition: usb_regs.h:153
USB_GINTEN
#define USB_GINTEN
Definition: usb_regs.h:41
GINTF_SESIF
#define GINTF_SESIF
Definition: usb_regs.h:145
USB_GINTF
#define USB_GINTF
Definition: usb_regs.h:40
USB_CURRENT_MODE_GET
#define USB_CURRENT_MODE_GET()
Definition: usb_regs.h:548
GINTF_OEPIF
#define GINTF_OEPIF
Definition: usb_regs.h:154
GINTF_ESP
#define GINTF_ESP
Definition: usb_regs.h:161
GINTF_OTGIF
#define GINTF_OTGIF
Definition: usb_regs.h:167
GINTF_SP
#define GINTF_SP
Definition: usb_regs.h:160
GINTF_WKUPIF
#define GINTF_WKUPIF
Definition: usb_regs.h:144
GINTF_RST
#define GINTF_RST
Definition: usb_regs.h:159
GINTF_ISOONCIF
#define GINTF_ISOONCIF
Definition: usb_regs.h:152
GINTF_ENUMF
#define GINTF_ENUMF
Definition: usb_regs.h:158
GINTF_SOF
#define GINTF_SOF
Definition: usb_regs.h:166
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:47
GINTF_MFIF
#define GINTF_MFIF
Definition: usb_regs.h:168

Variable Documentation

usbd_int_cb_struct* usbd_int_fops
Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbd_std.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
Macros | Functions
usbd_std.h File Reference

USB 2.0 standard defines. More...

#include "usb_std.h"
#include "usbd_core.h"
#include "usbd_conf.h"
#include <wchar.h>

Go to the source code of this file.

Macros

#define | USBD_LANGID_STR_IDX 0x00U
#define | USBD_MFC_STR_IDX 0x01U
#define | USBD_PRODUCT_STR_IDX 0x02U
#define | USBD_SERIAL_STR_IDX 0x03U
#define | USBD_CONFIG_STR_IDX 0x04U
#define | USBD_INTERFACE_STR_IDX 0x05U
#define | USB_STATUS_REMOTE_WAKEUP 0x02U
#define | USB_STATUS_SELF_POWERED 0x01U
#define | USB_FEATURE_ENDP_HALT 0x00U
#define | USB_FEATURE_REMOTE_WAKEUP 0x01U
#define | USB_FEATURE_TEST_MODE 0x02U
#define | ENG_LANGID 0x0409U
#define | CHN_LANGID 0x0804U
#define | USB_DEVICE_DESC_SIZE 0x12U
#define | LOWBYTE(x) ((uint8_t)((x) & 0x00FFU))
#define | HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U))
#define | USB_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | WIDE_STRING(string) _WIDE_STRING(string)
#define | _WIDE_STRING(string) L##string
#define | USBD_STRING_DESC(string)
#define | IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U))

Functions

usbd_status_enum | usbd_setup_transaction (usb_core_handle_struct *pudev)
USB setup stage processing. More...
usbd_status_enum | usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num)
data out stage processing More...
usbd_status_enum | usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num)
data in stage processing More...
void | usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB low level error event More...

Detailed Description

USB 2.0 standard defines.

Definition in file usbd_std.h.

Macro Definition Documentation

#define _WIDE_STRING ( string ) L##string

Definition at line 45 of file usbd_std.h.

#define CHN_LANGID 0x0804U

USB chinese language id

Definition at line 35 of file usbd_std.h.

#define ENG_LANGID 0x0409U

USB english language id

Definition at line 34 of file usbd_std.h.

#define HIGHBYTE ( x ) ((uint8_t)(((x) & 0xFF00U) >> 8U))

USB highbyte operation marco

Definition at line 40 of file usbd_std.h.

#define IS_NOT_EP0 ( ep_addr ) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U))

Definition at line 58 of file usbd_std.h.

#define LOWBYTE ( x ) ((uint8_t)((x) & 0x00FFU))

USB lowbyte operation marco

Definition at line 39 of file usbd_std.h.

#define USB_DEVICE_DESC_SIZE 0x12U

USB device descriptor size

Definition at line 37 of file usbd_std.h.

#define USB_FEATURE_ENDP_HALT 0x00U

USB halt endpoint feature

Definition at line 30 of file usbd_std.h.

#define USB_FEATURE_REMOTE_WAKEUP 0x01U

USB remote wakeup feature

Definition at line 31 of file usbd_std.h.

#define USB_FEATURE_TEST_MODE 0x02U

USB test mode feature

Definition at line 32 of file usbd_std.h.

#define USB_MIN | ( | a,
 |  | b
 | ) | (((a) < (b)) ? (a) : (b))

USB minimum operation marco

Definition at line 42 of file usbd_std.h.

#define USB_STATUS_REMOTE_WAKEUP 0x02U

USB remote wakeup status

Definition at line 27 of file usbd_std.h.

#define USB_STATUS_SELF_POWERED 0x01U

USB self power status

Definition at line 28 of file usbd_std.h.

#define USBD_CONFIG_STR_IDX 0x04U

USB configuration string index

Definition at line 24 of file usbd_std.h.

#define USBD_INTERFACE_STR_IDX 0x05U

USB interface string index

Definition at line 25 of file usbd_std.h.

#define USBD_LANGID_STR_IDX 0x00U

USB language ID string index

Definition at line 20 of file usbd_std.h.

#define USBD_MFC_STR_IDX 0x01U

USB manufacturer string index

Definition at line 21 of file usbd_std.h.

#define USBD_PRODUCT_STR_IDX 0x02U

USB product string index

Definition at line 22 of file usbd_std.h.

#define USBD_SERIAL_STR_IDX 0x03U

USB serial string index

Definition at line 23 of file usbd_std.h.

#define USBD_STRING_DESC ( string )
Value:
(uint8_t *)&(struct { \
uint8_t _len; \
uint8_t _type; \
wchar_t _data[sizeof(string)]; \
}) { \
sizeof(WIDE_STRING(string)) + 2U - 2U, \
USB_DESCTYPE_STRING, \
WIDE_STRING(string) \
}
WIDE_STRING
#define WIDE_STRING(string)
Definition: usbd_std.h:44
USB_DESCTYPE_STRING
#define USB_DESCTYPE_STRING
Definition: usb_std.h:57

Definition at line 47 of file usbd_std.h.

#define WIDE_STRING ( string ) _WIDE_STRING(string)

Definition at line 44 of file usbd_std.h.

Function Documentation

void usbd_enum_error | ( | usb_core_handle_struct * | pudev,
 |  | usb_device_req_struct * | req
 | ) |  |

handle USB low level error event

Parameters
[in] | pudev | pointer to USB device instance
[in] | req | pointer to USB device request
[out] | none
Return values
none

Definition at line 688 of file usbd_std.c.

689 {
690 usbd_ep_stall(pudev, 0x80U);
691 usbd_ep_stall(pudev, 0x00U);
692 usb_ep0_startout(pudev);
693 }
usbd_ep_stall
void usbd_ep_stall(usb_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:385
usbd_status_enum usbd_in_transaction | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | endp_num
 | ) |  |

data in stage processing

Parameters
[in] | pudev | pointer to USB device instance
[in] | ep_id | endpoint identifier(0..7)
[out] | none
Return values
USB device operation status

Definition at line 142 of file usbd_std.c.

143 {
144 usb_ep_struct *ep;
145
146 if (0U == endp_num) {
147 ep = &pudev->dev.in_ep[0];
148
149 if (USB_CTRL_DATA_IN == pudev->dev.ctl_status) {
150 if (pudev->dev.remain_len > ep->endp_mps) {
151 pudev->dev.remain_len -= ep->endp_mps;
152
153 usbd_ep_tx (pudev, 0U, ep->xfer_buff, pudev->dev.remain_len);
154
155 usbd_ep_rx (pudev, 0U, NULL, 0U);
156 } else {
157 /* last packet is MPS multiple, so send ZLP packet */
158 if ((pudev->dev.sum_len % ep->endp_mps == 0U) &&
159 (pudev->dev.sum_len >= ep->endp_mps) &&
160 (pudev->dev.sum_len < pudev->dev.ctl_len)) {
161 usbd_ep_tx (pudev, 0U, NULL, 0U);
162 pudev->dev.ctl_len = 0U;
163
164 usbd_ep_rx (pudev, 0U, NULL, 0U);
165 } else {
166 if (USB_STATUS_CONFIGURED == pudev->dev.status) {
167 pudev->dev.class_data_handler(pudev, USB_TX, 0U);
168 }
169
170 usbd_ctlstatus_rx(pudev);
171 }
172 }
173 }
174 } else if (USB_STATUS_CONFIGURED == pudev->dev.status) {
175 pudev->dev.class_data_handler(pudev, USB_TX, endp_num);
176 } else {
177 /* no operation */
178 }
179
180 return USBD_OK;
181 }
USB_TX
Definition: usb_core.h:95
USBD_OK
Definition: usb_core.h:74
USB_STATUS_CONFIGURED
#define USB_STATUS_CONFIGURED
Definition: usbd_core.h:22
usbd_ctlstatus_rx
usbd_status_enum usbd_ctlstatus_rx(usb_core_handle_struct *pudev)
receive status on the control channel
Definition: usbd_core.c:367
USB_CTRL_DATA_IN
Definition: usb_core.h:84
usbd_ep_tx
void usbd_ep_tx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:230
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:103
usbd_ep_rx
void usbd_ep_rx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:161
usb_ep_struct
Definition: usb_core.h:99
NULL
#define NULL
Definition: usb_defines.h:18
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:106
usbd_status_enum usbd_out_transaction | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | endp_num
 | ) |  |

data out stage processing

Parameters
[in] | pudev | pointer to USB device instance
[in] | ep_id | endpoint identifier(0..7)
[out] | none
Return values
USB device operation status

Definition at line 103 of file usbd_std.c.

104 {
105 usb_ep_struct *ep;
106
107 if (0U == endp_num) {
108 ep = &pudev->dev.out_ep[0];
109
110 if (USB_CTRL_DATA_OUT == pudev->dev.ctl_status) {
111 if (pudev->dev.remain_len > ep->endp_mps) {
112 pudev->dev.remain_len -= ep->endp_mps;
113
114 usbd_ep_rx (pudev,
115 0U,
116 ep->xfer_buff,
117 (uint16_t)USB_MIN(pudev->dev.remain_len, ep->endp_mps));
118 } else {
119 if (USB_STATUS_CONFIGURED == pudev->dev.status) {
120 pudev->dev.class_data_handler(pudev, USB_RX, 0U);
121 }
122
123 usbd_ctlstatus_tx(pudev);
124 }
125 }
126 } else if (USB_STATUS_CONFIGURED == pudev->dev.status) {
127 pudev->dev.class_data_handler(pudev, USB_RX, endp_num);
128 } else {
129 /* no operation */
130 }
131
132 return USBD_OK;
133 }
USBD_OK
Definition: usb_core.h:74
USB_STATUS_CONFIGURED
#define USB_STATUS_CONFIGURED
Definition: usbd_core.h:22
USB_CTRL_DATA_OUT
Definition: usb_core.h:85
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:103
USB_RX
Definition: usb_core.h:94
usbd_ep_rx
void usbd_ep_rx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:161
usb_ep_struct
Definition: usb_core.h:99
usbd_ctlstatus_tx
usbd_status_enum usbd_ctlstatus_tx(usb_core_handle_struct *pudev)
transmit status on the control channel
Definition: usbd_core.c:350
USB_MIN
#define USB_MIN(a, b)
Definition: usbd_std.h:42
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:106
usbd_status_enum usbd_setup_transaction ( usb_core_handle_struct * pudev )

USB setup stage processing.

Parameters
[in] | pudev | pointer to USB device instance
[out] | none
Return values
USB device operation status

Definition at line 69 of file usbd_std.c.

70 {
71 usb_device_req_struct req;
72
73 usbd_setup_request_parse(pudev, &req);
74
75 switch (req.bmRequestType & USB_REQ_MASK) {
76 /* standard device request */
77 case USB_STANDARD_REQ:
78 usbd_standard_request(pudev, &req);
79 break;
80 /* device class request */
81 case USB_CLASS_REQ:
82 usbd_device_class_request(pudev, &req);
83 break;
84 /* vendor defined request */
85 case USB_VENDOR_REQ:
86 usbd_vendor_request(pudev, &req);
87 break;
88 default:
89 usbd_ep_stall(pudev, req.bmRequestType & 0x80U);
90 break;
91 }
92
93 return USBD_OK;
94 }
USB_CLASS_REQ
#define USB_CLASS_REQ
Definition: usb_std.h:31
USBD_OK
Definition: usb_core.h:74
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usb_std.h:30
usb_device_req_struct
Definition: usb_core.h:114
usb_device_req_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_core.h:116
usbd_ep_stall
void usbd_ep_stall(usb_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:385
USB_REQ_MASK
#define USB_REQ_MASK
Definition: usb_std.h:33
USB_VENDOR_REQ
#define USB_VENDOR_REQ
Definition: usb_std.h:32
Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_core.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
Data Structures | Macros | Typedefs | Enumerations | Functions
usbh_core.h File Reference

header file for usbh_core.c More...

#include "usbh_conf.h"
#include "usb_std.h"
#include "usb_core.h"

Go to the source code of this file.

Data Structures

struct | usbh_ctrl_struct
struct | usbh_device_struct
struct | usbh_user_callback_struct
struct | backup_state_struct
struct | usbh_host_struct
struct | state_table_struct
struct | usbh_state_stack_struct
struct | usbh_state_regist_table_struct
struct | usbh_state_handle_struct

Macros

#define | MSC_CLASS 0x08
#define | HID_CLASS 0x03
#define | MSC_PROTOCOL 0x50
#define | CBI_PROTOCOL 0x01
#define | USBH_DEVICE_ADDRESS_DEFAULT 0U
#define | USBH_DEVICE_ADDRESS 1U
#define | USBH_MAX_ERROR_COUNT 2U
#define | HOST_USER_SELECT_CONFIGURATION 1U
#define | HOST_USER_CLASS_ACTIVE 2U
#define | HOST_USER_CLASS_SELECTED 3U
#define | HOST_USER_CONNECTION 4U
#define | HOST_USER_DISCONNECTION 5U
#define | HOST_USER_UNRECOVERED_ERROR 6U
#define | MAX_USBH_STATE_STACK_DEEP 4
#define | MAX_USBH_STATE_TABLE_NUM 10U
#define | HOST_FSM_ID 0U
#define | ENUM_FSM_ID 1U
#define | CMD_FSM_ID 2U
#define | CTRL_FSM_ID 3U
#define | CLASS_REQ_FSM_ID 4U
#define | CLASS_FSM_ID 5U
#define | UP_STATE 100U
#define | GO_TO_UP_STATE_EVENT 100U
#define | HOST_HANDLE_TABLE_SIZE 9U

Typedefs

typedef usbh_status_enum(* ACT_FUN) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)

Enumerations

enum host_state_enum {
HOST_IDLE = 0, HOST_DEV_ATTACHED, HOST_DEV_DETACHED, HOST_DETECT_DEV_SPEED,
HOST_ENUMERATION, HOST_CLASS_REQUEST, HOST_CLASS, HOST_USER_INPUT,
HOST_SUSPENDED, HOST_ERROR
}
enum host_event_enum {
HOST_EVENT_ATTACHED = 0, HOST_EVENT_ENUM, HOST_EVENT_USER_INPUT, HOST_EVENT_CLASS_REQ,
HOST_EVENT_CLASS, HOST_EVENT_ERROR, HOST_EVENT_DEV_DETACHED, HOST_EVENT_IDLE
}
enum enum_state_enum {
ENUM_IDLE = 0, ENUM_SET_ADDR, ENUM_GET_FULL_DEV_DESC, ENUM_GET_CFG_DESC,
ENUM_GET_FULL_CFG_DESC, ENUM_GET_MFC_STRING_DESC, ENUM_GET_PRODUCT_STRING_DESC, ENUM_GET_SERIALNUM_STRING_DESC,
ENUM_SET_CONFIGURATION, ENUM_DEV_CONFIGURED
}
enum ctrl_state_enum {
CTRL_IDLE = 0, CTRL_SETUP, CTRL_DATA, CTRL_STATUS,
CTRL_ERROR, CTRL_STALLED, CTRL_COMPLETE
}
enum usbh_status_enum {
USBH_OK = 0, USBH_BUSY, USBH_FAIL, USBH_NOT_SUPPORTED,
USBH_UNRECOVERED_ERROR, USBH_SPEED_UNKNOWN_ERROR, USBH_APPLY_DEINIT
}
enum usbh_user_status_enum { USBH_USER_NO_RESP = 0, USBH_USER_RESP_OK = 1 }

Functions

usbh_status_enum | host_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of HOST state More...
uint32_t | hcd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize the host portion of the driver. More...
uint32_t | hcd_is_device_connected (usb_core_handle_struct *pudev)
check if the device is connected. More...
urb_state_enum | hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate More...
uint32_t | hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate More...
usbh_status_enum | usbh_deinit (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
de-initialize host More...
void | scd_init (usbh_state_handle_struct *pustate)
state core driver init More...
void | scd_table_regist (usbh_state_handle_struct *pustate, state_table_struct *pstate_table, uint8_t table_id, uint8_t current_table_size)
state core driver table regist More...
void | scd_begin (usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin More...
void | scd_state_move (usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state More...
usbh_status_enum | scd_event_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate, uint8_t event, uint8_t state)
state core driver event handle More...
void | scd_table_push (usbh_state_handle_struct *pustate)
state core driver table push More...
void | scd_table_pop (usbh_state_handle_struct *pustate)
state core driver table pop More...
usbh_status_enum | only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move More...
usbh_status_enum | goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state More...

Detailed Description

header file for usbh_core.c

Definition in file usbh_core.h.

Macro Definition Documentation

#define CBI_PROTOCOL 0x01

the CBI protocal define

Definition at line 22 of file usbh_core.h.

#define CLASS_FSM_ID 5U

the class state table id

Definition at line 43 of file usbh_core.h.

#define CLASS_REQ_FSM_ID 4U

the class req state table id

Definition at line 42 of file usbh_core.h.

#define CMD_FSM_ID 2U

the cmd state table id

Definition at line 40 of file usbh_core.h.

#define CTRL_FSM_ID 3U

the ctrl state table id

Definition at line 41 of file usbh_core.h.

#define ENUM_FSM_ID 1U

the enum state table id

Definition at line 39 of file usbh_core.h.

#define GO_TO_UP_STATE_EVENT 100U

go to up state event define

Definition at line 46 of file usbh_core.h.

#define HID_CLASS 0x03

the HID class define

Definition at line 20 of file usbh_core.h.

#define HOST_FSM_ID 0U

the host state table id

Definition at line 38 of file usbh_core.h.

#define HOST_HANDLE_TABLE_SIZE 9U

the host handle table size define

Definition at line 48 of file usbh_core.h.

#define HOST_USER_CLASS_ACTIVE 2U

the user class active define

Definition at line 29 of file usbh_core.h.

#define HOST_USER_CLASS_SELECTED 3U

the user class selected define

Definition at line 30 of file usbh_core.h.

#define HOST_USER_CONNECTION 4U

the user connecttion define

Definition at line 31 of file usbh_core.h.

#define HOST_USER_DISCONNECTION 5U

the user disconnection define

Definition at line 32 of file usbh_core.h.

#define HOST_USER_SELECT_CONFIGURATION 1U

the user select configuration define

Definition at line 28 of file usbh_core.h.

#define HOST_USER_UNRECOVERED_ERROR 6U

the user unrecovered error define

Definition at line 33 of file usbh_core.h.

#define MAX_USBH_STATE_STACK_DEEP 4

the max state stack deep define

Definition at line 35 of file usbh_core.h.

#define MAX_USBH_STATE_TABLE_NUM 10U

the max state table number

Definition at line 36 of file usbh_core.h.

#define MSC_CLASS 0x08

the MSC class define

Definition at line 19 of file usbh_core.h.

#define MSC_PROTOCOL 0x50

the MSC protocal define

Definition at line 21 of file usbh_core.h.

#define UP_STATE 100U

up state define

Definition at line 45 of file usbh_core.h.

#define USBH_DEVICE_ADDRESS 1U

the device address define

Definition at line 25 of file usbh_core.h.

#define USBH_DEVICE_ADDRESS_DEFAULT 0U

the default device address define

Definition at line 24 of file usbh_core.h.

#define USBH_MAX_ERROR_COUNT 2U

the max error count define

Definition at line 26 of file usbh_core.h.

Typedef Documentation

typedef usbh_status_enum(* ACT_FUN) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)

Definition at line 199 of file usbh_core.h.

Enumeration Type Documentation

enum ctrl_state_enum
Enumerator
CTRL_IDLE
CTRL_SETUP
CTRL_DATA
CTRL_STATUS
CTRL_ERROR
CTRL_STALLED
CTRL_COMPLETE

Definition at line 94 of file usbh_core.h.

95 {
96 CTRL_IDLE = 0, /* the ctrl idle state definition */
97 CTRL_SETUP, /* the ctrl setup state definition */
98 CTRL_DATA, /* the ctrl data state definition */
99 CTRL_STATUS, /* the ctrl status state definition */
100 CTRL_ERROR, /* the ctrl error state definition */
101 CTRL_STALLED, /* the ctrl stalled state definition */
102 CTRL_COMPLETE /* the ctrl complete state definition */
103 }ctrl_state_enum;
CTRL_IDLE
Definition: usbh_core.h:96
CTRL_ERROR
Definition: usbh_core.h:100
ctrl_state_enum
ctrl_state_enum
Definition: usbh_core.h:94
CTRL_STATUS
Definition: usbh_core.h:99
CTRL_STALLED
Definition: usbh_core.h:101
CTRL_SETUP
Definition: usbh_core.h:97
CTRL_COMPLETE
Definition: usbh_core.h:102
CTRL_DATA
Definition: usbh_core.h:98
enum enum_state_enum
Enumerator
ENUM_IDLE
ENUM_SET_ADDR
ENUM_GET_FULL_DEV_DESC
ENUM_GET_CFG_DESC
ENUM_GET_FULL_CFG_DESC
ENUM_GET_MFC_STRING_DESC
ENUM_GET_PRODUCT_STRING_DESC
ENUM_GET_SERIALNUM_STRING_DESC
ENUM_SET_CONFIGURATION
ENUM_DEV_CONFIGURED

Definition at line 79 of file usbh_core.h.

80 {
81 ENUM_IDLE = 0, /* the enum idle state definition */
82 ENUM_SET_ADDR, /* the enum set address state definition */
83 ENUM_GET_FULL_DEV_DESC, /* the enum get full device descripter state definition */
84 ENUM_GET_CFG_DESC, /* the enum get configuration descripter state definition */
85 ENUM_GET_FULL_CFG_DESC, /* the enum get full configuration descripter state definition */
86 ENUM_GET_MFC_STRING_DESC, /* the enum get MFC string descripter state definition */
87 ENUM_GET_PRODUCT_STRING_DESC, /* the enum get product string descripter state definition */
88 ENUM_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string descripter state definition */
89 ENUM_SET_CONFIGURATION, /* the enum set congiguration state definition */
90 ENUM_DEV_CONFIGURED /* the enum device configuration state definition */
91 }enum_state_enum;
ENUM_DEV_CONFIGURED
Definition: usbh_core.h:90
ENUM_IDLE
Definition: usbh_core.h:81
ENUM_GET_PRODUCT_STRING_DESC
Definition: usbh_core.h:87
ENUM_GET_CFG_DESC
Definition: usbh_core.h:84
ENUM_SET_ADDR
Definition: usbh_core.h:82
enum_state_enum
enum_state_enum
Definition: usbh_core.h:79
ENUM_SET_CONFIGURATION
Definition: usbh_core.h:89
ENUM_GET_FULL_CFG_DESC
Definition: usbh_core.h:85
ENUM_GET_FULL_DEV_DESC
Definition: usbh_core.h:83
ENUM_GET_MFC_STRING_DESC
Definition: usbh_core.h:86
ENUM_GET_SERIALNUM_STRING_DESC
Definition: usbh_core.h:88
enum host_event_enum
Enumerator
HOST_EVENT_ATTACHED
HOST_EVENT_ENUM
HOST_EVENT_USER_INPUT
HOST_EVENT_CLASS_REQ
HOST_EVENT_CLASS
HOST_EVENT_ERROR
HOST_EVENT_DEV_DETACHED
HOST_EVENT_IDLE

Definition at line 66 of file usbh_core.h.

67 {
68 HOST_EVENT_ATTACHED = 0, /* the host attached event */
69 HOST_EVENT_ENUM, /* the host enum event */
70 HOST_EVENT_USER_INPUT, /* the host user input event */
71 HOST_EVENT_CLASS_REQ, /* the host class request event */
72 HOST_EVENT_CLASS, /* the host class event */
73 HOST_EVENT_ERROR, /* the host error event */
74 HOST_EVENT_DEV_DETACHED, /* the host device detached event */
75 HOST_EVENT_IDLE /* the host idle event */
76 }host_event_enum;
HOST_EVENT_IDLE
Definition: usbh_core.h:75
HOST_EVENT_CLASS_REQ
Definition: usbh_core.h:71
HOST_EVENT_CLASS
Definition: usbh_core.h:72
HOST_EVENT_ENUM
Definition: usbh_core.h:69
HOST_EVENT_ERROR
Definition: usbh_core.h:73
host_event_enum
host_event_enum
Definition: usbh_core.h:66
HOST_EVENT_DEV_DETACHED
Definition: usbh_core.h:74
HOST_EVENT_ATTACHED
Definition: usbh_core.h:68
HOST_EVENT_USER_INPUT
Definition: usbh_core.h:70
enum host_state_enum
Enumerator
HOST_IDLE
HOST_DEV_ATTACHED
HOST_DEV_DETACHED
HOST_DETECT_DEV_SPEED
HOST_ENUMERATION
HOST_CLASS_REQUEST
HOST_CLASS
HOST_USER_INPUT
HOST_SUSPENDED
HOST_ERROR

Definition at line 51 of file usbh_core.h.

52 {
53 HOST_IDLE = 0, /* the host idle state definition */
54 HOST_DEV_ATTACHED, /* the host device attached state definition */
55 HOST_DEV_DETACHED, /* the host device detached state definition */
56 HOST_DETECT_DEV_SPEED, /* the host detect device speed state definition */
57 HOST_ENUMERATION, /* the host enumeration state definition */
58 HOST_CLASS_REQUEST, /* the host class request state definition */
59 HOST_CLASS, /* the host class state definition */
60 HOST_USER_INPUT, /* the host user input state definition */
61 HOST_SUSPENDED, /* the host suspended state definition */
62 HOST_ERROR /* the host error state definition */
63 }host_state_enum;
HOST_SUSPENDED
Definition: usbh_core.h:61
HOST_CLASS
Definition: usbh_core.h:59
HOST_ERROR
Definition: usbh_core.h:62
HOST_DEV_DETACHED
Definition: usbh_core.h:55
HOST_DEV_ATTACHED
Definition: usbh_core.h:54
HOST_ENUMERATION
Definition: usbh_core.h:57
host_state_enum
host_state_enum
Definition: usbh_core.h:51
HOST_DETECT_DEV_SPEED
Definition: usbh_core.h:56
HOST_CLASS_REQUEST
Definition: usbh_core.h:58
HOST_USER_INPUT
Definition: usbh_core.h:60
HOST_IDLE
Definition: usbh_core.h:53
enum usbh_status_enum
Enumerator
USBH_OK
USBH_BUSY
USBH_FAIL
USBH_NOT_SUPPORTED
USBH_UNRECOVERED_ERROR
USBH_SPEED_UNKNOWN_ERROR
USBH_APPLY_DEINIT

Definition at line 106 of file usbh_core.h.

107 {
108 USBH_OK = 0, /* the usbh ok status definition */
109 USBH_BUSY, /* the usbh busy status definition */
110 USBH_FAIL, /* the usbh fail status definition */
111 USBH_NOT_SUPPORTED, /* the usbh not supported status definition */
112 USBH_UNRECOVERED_ERROR, /* the usbh unrecovered error status definition */
113 USBH_SPEED_UNKNOWN_ERROR, /* the usbh speed unknown error status definition */
114 USBH_APPLY_DEINIT /* the usbh apply deinit status definition */
115 }usbh_status_enum;
USBH_NOT_SUPPORTED
Definition: usbh_core.h:111
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:106
USBH_APPLY_DEINIT
Definition: usbh_core.h:114
USBH_UNRECOVERED_ERROR
Definition: usbh_core.h:112
USBH_SPEED_UNKNOWN_ERROR
Definition: usbh_core.h:113
USBH_OK
Definition: usbh_core.h:108
USBH_FAIL
Definition: usbh_core.h:110
USBH_BUSY
Definition: usbh_core.h:109
enum usbh_user_status_enum
Enumerator
USBH_USER_NO_RESP
USBH_USER_RESP_OK

Definition at line 118 of file usbh_core.h.

119 {
120 USBH_USER_NO_RESP = 0, /* the user no response */
121 USBH_USER_RESP_OK = 1, /* the user response ok */
122 }usbh_user_status_enum;
usbh_user_status_enum
usbh_user_status_enum
Definition: usbh_core.h:118
USBH_USER_RESP_OK
Definition: usbh_core.h:121
USBH_USER_NO_RESP
Definition: usbh_core.h:120

Function Documentation

usbh_status_enum goto_up_state_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the function to the up state

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 705 of file usbh_core.c.

706 {
707 scd_table_pop((usbh_state_handle_struct *)pustate);
708
709 return USBH_OK;
710 }
usbh_state_handle_struct
Definition: usbh_core.h:227
scd_table_pop
void scd_table_pop(usbh_state_handle_struct *pustate)
state core driver table pop
Definition: usbh_core.c:644
USBH_OK
Definition: usbh_core.h:108
uint32_t hcd_init | ( | usb_core_handle_struct * | pudev,
 |  | usb_core_id_enum | core_id
 | ) |  |

initialize the host portion of the driver.

Parameters
[in] | pudev | pointer to usb device
[in] | core_id | usb otg core identifier(high-speed or full-speed)
[out] | none
Return values
operation status

Definition at line 385 of file usbh_core.c.

386 {
387 pudev->host.connect_status = 0U;
388
389 pudev->host.host_channel[0].endp_mps = 8U;
390
391 usb_core_select(pudev, core_id);
392
393 #ifndef DUAL_ROLE_MODE_ENABLED
394
395 USB_GLOBAL_INT_DISABLE();
396
397 usb_core_init(pudev);
398
399 /* force host mode*/
400 usb_mode_set(pudev, HOST_MODE);
401
402 usb_hostcore_init(pudev);
403
404 USB_GLOBAL_INT_ENABLE();
405
406 #endif
407
408 return 0U;
409 }
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:125
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:48
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:266
USB_GLOBAL_INT_DISABLE
#define USB_GLOBAL_INT_DISABLE()
Definition: usb_regs.h:545
USB_GLOBAL_INT_ENABLE
#define USB_GLOBAL_INT_ENABLE()
Definition: usb_regs.h:542
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:167
uint32_t hcd_is_device_connected ( usb_core_handle_struct * pudev )

check if the device is connected.

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
device connection status. 1 -> connected and 0 -> disconnected

Definition at line 417 of file usbh_core.c.

418 {
419 return (uint32_t)(pudev->host.connect_status);
420 }
urb_state_enum hcd_urb_state_get | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num
 | ) |  |

this function returns the last URBstate

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[out] | none
Return values
urb_state_enum

Definition at line 429 of file usbh_core.c.

430 {
431 return pudev->host.host_channel[channel_num].urb_state;
432 }
uint32_t hcd_xfer_count_get | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num
 | ) |  |

this function returns the last URBstate

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[out] | none
Return values
No. of data bytes transferred

Definition at line 441 of file usbh_core.c.

442 {
443 return pudev->host.host_channel[channel_num].xfer_count;
444 }
usbh_status_enum host_state_polling_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the polling function of HOST state

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 88 of file usbh_core.c.

91 {
92 usbh_state_handle_struct *p_state = (usbh_state_handle_struct *)pustate;
93
94 scd_begin(p_state, HOST_FSM_ID);
95
96 if (-1 == p_state->usbh_current_state_stack_top) {
97 uint8_t cur_state = p_state->usbh_current_state;
98
99 if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != cur_state)) {
100 if (HOST_DEV_DETACHED != cur_state) {
101 p_state->usbh_current_state = HOST_DEV_DETACHED;
102 cur_state = HOST_DEV_DETACHED;
103 }
104 }
105
106 host_state_handle[cur_state](pudev, puhost, p_state);
107 } else {
108 uint8_t stack0_state = p_state->stack[0].state;
109
110 if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != stack0_state)) {
111 if (HOST_DEV_DETACHED != stack0_state) {
112 p_state->stack[0].state = HOST_DEV_DETACHED;
113 stack0_state = HOST_DEV_DETACHED;
114 p_state->usbh_current_state = HOST_DEV_DETACHED;
115 }
116 }
117
118 host_state_handle[stack0_state](pudev, puhost, p_state);
119 }
120
121 return USBH_OK;
122 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
usbh_state_handle_struct
Definition: usbh_core.h:227
hcd_is_device_connected
uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev)
check if the device is connected.
Definition: usbh_core.c:417
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:213
HOST_DEV_DETACHED
Definition: usbh_core.h:55
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:538
HOST_FSM_ID
#define HOST_FSM_ID
Definition: usbh_core.h:38
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:233
host_state_handle
void(* host_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_core.c:51
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:234
USBH_OK
Definition: usbh_core.h:108
HOST_IDLE
Definition: usbh_core.h:53
usbh_status_enum only_state_move | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the function is only used to state move

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 692 of file usbh_core.c.

693 {
694 return USBH_OK;
695 }
USBH_OK
Definition: usbh_core.h:108
void scd_begin | ( | usbh_state_handle_struct * | pustate,
 |  | uint8_t | table_id
 | ) |  |

state core driver begin

Parameters
[in] | pustate | pointer to usb state driver
[in] | table_id | the id of the table to begin
[out] | none
Return values
none

Definition at line 538 of file usbh_core.c.

539 {
540 uint8_t i = 0U, table_num = pustate->usbh_regist_state_table_num;
541 usbh_state_regist_table_struct *cur_state_reg_table;
542
543 for (i = 0U; i < table_num; i++) {
544 cur_state_reg_table = &pustate->usbh_regist_state_table[i];
545
546 if (table_id == cur_state_reg_table->id) {
547 pustate->usbh_current_state_table = cur_state_reg_table->table;
548 pustate->usbh_current_state_table_size = cur_state_reg_table->table_size;
549 break;
550 }
551 }
552 }
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:231
usbh_state_handle_struct::usbh_regist_state_table
usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]
Definition: usbh_core.h:236
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:237
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:223
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:221
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:222
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:230
usbh_state_regist_table_struct
Definition: usbh_core.h:219
usbh_status_enum scd_event_handle | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | usbh_state_handle_struct * | pustate,
 |  | uint8_t | event,
 |  | uint8_t | state
 | ) |  |

state core driver event handle

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[in] | event | the current event
[in] | state | the current state
[out] | none
Return values
host status

Definition at line 576 of file usbh_core.c.

581 {
582 uint8_t i = 0U;
583 ACT_FUN event_act_fun = NULL;
584 state_table_struct *backup_state_t = pustate->usbh_current_state_table;
585 state_table_struct *executive_state_table = pustate->usbh_current_state_table;
586
587 /* look up the table to find the action function */
588 for (i = 0U; i < pustate->usbh_current_state_table_size; i++) {
589 if (state == executive_state_table->cur_state) {
590 if (event == executive_state_table->cur_event) {
591 state = executive_state_table->next_state;
592 event_act_fun = executive_state_table->event_action_fun;
593 break;
594 } else {
595 executive_state_table++;
596 }
597 } else {
598 executive_state_table++;
599 }
600 }
601
602 pustate->usbh_current_state_table = backup_state_t;
603
604 /* if the action function is not NULL, execute the action function */
605 if (event_act_fun) {
606 if (event_act_fun == &only_state_move) {
607 pustate->usbh_current_state = state;
608 } else {
609 return event_act_fun(pudev, puhost, pustate);
610 }
611 }
612
613 return USBH_BUSY;
614 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
state_table_struct::event_action_fun
ACT_FUN event_action_fun
Definition: usbh_core.h:207
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:231
state_table_struct::next_state
uint8_t next_state
Definition: usbh_core.h:206
state_table_struct
Definition: usbh_core.h:202
state_table_struct::cur_state
uint8_t cur_state
Definition: usbh_core.h:204
ACT_FUN
usbh_status_enum(* ACT_FUN)(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
Definition: usbh_core.h:199
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:230
NULL
#define NULL
Definition: usb_defines.h:18
USBH_BUSY
Definition: usbh_core.h:109
state_table_struct::cur_event
uint8_t cur_event
Definition: usbh_core.h:205
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:692
void scd_init ( usbh_state_handle_struct * pustate )

state core driver init

Parameters
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 484 of file usbh_core.c.

485 {
486 /* init the state core */
487 pustate->usbh_current_state = 0U;
488 pustate->usbh_current_state_table = NULL;
489 pustate->usbh_current_state_table_size = 0U;
490
491 pustate->usbh_current_state_stack_top = -1;
492 pustate->stack->state = 0U;
493 pustate->stack->table_size = 0U;
494 pustate->stack->table = NULL;
495
496 pustate->usbh_regist_state_table_num = 0U;
497 pustate->usbh_regist_state_table->table = NULL;
498 pustate->usbh_regist_state_table->table_size = 0U;
499 pustate->usbh_regist_state_table->id = 0U;
500
501 /* init the control and the enumeration polling handle flag */
502 ctrl_polling_handle_flag = 0U;
503 enum_polling_handle_flag = 0U;
504 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
enum_polling_handle_flag
uint8_t enum_polling_handle_flag
Definition: usbh_std.c:19
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:213
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:231
usbh_state_handle_struct::usbh_regist_state_table
usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]
Definition: usbh_core.h:236
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:237
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:223
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:221
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:233
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:214
ctrl_polling_handle_flag
uint8_t ctrl_polling_handle_flag
Definition: usbh_ctrl.c:16
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:222
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:234
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:230
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:215
NULL
#define NULL
Definition: usb_defines.h:18
void scd_state_move | ( | usbh_state_handle_struct * | pustate,
 |  | uint8_t | state
 | ) |  |

state core driver move state

Parameters
[in] | pustate | pointer to usb state driver
[in] | state | the state to move
[out] | none
Return values
none

Definition at line 561 of file usbh_core.c.

562 {
563 pustate->usbh_current_state = state;
564 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
void scd_table_pop ( usbh_state_handle_struct * pustate )

state core driver table pop

Parameters
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 644 of file usbh_core.c.

645 {
646 usbh_state_stack_struct *top_state_element;
647
648 top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top];
649
650 if (pustate->usbh_current_state_stack_top > -1) {
651 /* get the current state table from the state stack */
652 pustate->usbh_current_state = top_state_element->state;
653 pustate->usbh_current_state_table = top_state_element->table;
654 pustate->usbh_current_state_table_size = top_state_element->table_size;
655 pustate->usbh_current_state_stack_top--;
656 }
657 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:213
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:231
usbh_state_stack_struct
Definition: usbh_core.h:211
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:233
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:214
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:234
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:230
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:215
void scd_table_push ( usbh_state_handle_struct * pustate )

state core driver table push

Parameters
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 622 of file usbh_core.c.

623 {
624 usbh_state_stack_struct *top_state_element;
625
626 if (pustate->usbh_current_state_stack_top < MAX_USBH_STATE_STACK_DEEP) {
627 pustate->usbh_current_state_stack_top++;
628
629 top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top];
630
631 /* put the current state table into the state stack */
632 top_state_element->state = pustate->usbh_current_state;
633 top_state_element->table = pustate->usbh_current_state_table;
634 top_state_element->table_size = pustate->usbh_current_state_table_size;
635 }
636 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:213
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:231
usbh_state_stack_struct
Definition: usbh_core.h:211
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:233
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:214
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:234
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:230
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:215
MAX_USBH_STATE_STACK_DEEP
#define MAX_USBH_STATE_STACK_DEEP
Definition: usbh_core.h:35
void scd_table_regist | ( | usbh_state_handle_struct * | pustate,
 |  | state_table_struct * | pstate_table,
 |  | uint8_t | table_id,
 |  | uint8_t | current_table_size
 | ) |  |

state core driver table regist

Parameters
[in] | pustate | pointer to usb state driver
[in] | pstate_table | pointer to the table to regist
[in] | table_id | the id of the table to regist
[in] | current_table_size | the size of the current table to regist
[out] | none
Return values
none

Definition at line 515 of file usbh_core.c.

519 {
520 usbh_state_regist_table_struct *cur_state_reg_table;
521
522 cur_state_reg_table = &pustate->usbh_regist_state_table[pustate->usbh_regist_state_table_num];
523
524 cur_state_reg_table->id = table_id;
525 cur_state_reg_table->table = pstate_table;
526 cur_state_reg_table->table_size = current_table_size;
527
528 pustate->usbh_regist_state_table_num++;
529 }
usbh_state_handle_struct::usbh_regist_state_table
usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]
Definition: usbh_core.h:236
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:237
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:223
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:221
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:222
usbh_state_regist_table_struct
Definition: usbh_core.h:219
usbh_status_enum usbh_deinit | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | usbh_state_handle_struct * | pustate
 | ) |  |

de-initialize host

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[out] | none
Return values
host status

Definition at line 453 of file usbh_core.c.

456 {
457 /* software init */
458
459 puhost->control.ep0_size = USB_MAX_EP0_SIZE;
460
461 puhost->device.address = USBH_DEVICE_ADDRESS_DEFAULT;
462 puhost->device.speed = HPRT_PRTSPD_FULL_SPEED;
463
464 usbh_channel_free(pudev, puhost->control.hc_in_num);
465 usbh_channel_free(pudev, puhost->control.hc_out_num);
466
467 scd_init(pustate);
468 scd_table_regist(pustate, host_handle_table, HOST_FSM_ID, HOST_HANDLE_TABLE_SIZE);
469 scd_table_regist(pustate, enum_handle_table, ENUM_FSM_ID, ENUM_HANDLE_TABLE_SIZE);
470 scd_table_regist(pustate, ctrl_handle_table, CTRL_FSM_ID, CTRL_HANDLE_TABLE_SIZE);
471
472 scd_begin(pustate,HOST_FSM_ID);
473 scd_state_move(pustate, HOST_IDLE);
474
475 return USBH_OK;
476 }
ENUM_FSM_ID
#define ENUM_FSM_ID
Definition: usbh_core.h:39
usbh_channel_free
uint8_t usbh_channel_free(usb_core_handle_struct *pudev, uint8_t index)
free the usb host channel
Definition: usbh_hcs.c:114
host_handle_table
state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE]
Definition: usbh_core.c:66
CTRL_FSM_ID
#define CTRL_FSM_ID
Definition: usbh_core.h:41
usbh_ctrl_struct::hc_in_num
uint8_t hc_in_num
Definition: usbh_core.h:127
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:561
scd_table_regist
void scd_table_regist(usbh_state_handle_struct *pustate, state_table_struct *pstate_table, uint8_t table_id, uint8_t current_table_size)
state core driver table regist
Definition: usbh_core.c:515
usbh_ctrl_struct::ep0_size
uint8_t ep0_size
Definition: usbh_core.h:129
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:538
scd_init
void scd_init(usbh_state_handle_struct *pustate)
state core driver init
Definition: usbh_core.c:484
CTRL_HANDLE_TABLE_SIZE
#define CTRL_HANDLE_TABLE_SIZE
Definition: usbh_ctrl.h:18
usbh_device_struct::speed
uint8_t speed
Definition: usbh_core.h:141
HOST_FSM_ID
#define HOST_FSM_ID
Definition: usbh_core.h:38
usbh_device_struct::address
uint8_t address
Definition: usbh_core.h:140
ctrl_handle_table
state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]
Definition: usbh_ctrl.c:46
HPRT_PRTSPD_FULL_SPEED
#define HPRT_PRTSPD_FULL_SPEED
Definition: usb_defines.h:74
USB_MAX_EP0_SIZE
#define USB_MAX_EP0_SIZE
Definition: usb_core.h:19
usbh_host_struct::device
usbh_device_struct device
Definition: usbh_core.h:192
USBH_OK
Definition: usbh_core.h:108
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:191
ENUM_HANDLE_TABLE_SIZE
#define ENUM_HANDLE_TABLE_SIZE
Definition: usbh_std.h:23
enum_handle_table
state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]
Definition: usbh_std.c:48
HOST_IDLE
Definition: usbh_core.h:53
USBH_DEVICE_ADDRESS_DEFAULT
#define USBH_DEVICE_ADDRESS_DEFAULT
Definition: usbh_core.h:24
usbh_ctrl_struct::hc_out_num
uint8_t hc_out_num
Definition: usbh_core.h:128
HOST_HANDLE_TABLE_SIZE
#define HOST_HANDLE_TABLE_SIZE
Definition: usbh_core.h:48
Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_ctrl.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
Macros | Enumerations | Functions | Variables
usbh_ctrl.h File Reference

header file for usbh_ctrl.c More...

#include "usbh_core.h"
#include "usbh_usr.h"

Go to the source code of this file.

Macros

#define CTRL_HANDLE_TABLE_SIZE 13U

Enumerations

enum ctrl_event_enum {
CTRL_EVENT_IDLE = 0, CTRL_EVENT_SETUP, CTRL_EVENT_DATA, CTRL_EVENT_STATUS,
CTRL_EVENT_COMPLETE, CTRL_EVENT_ERROR, CTRL_EVENT_STALLED
}

Functions

usbh_status_enum | ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of CTRL state More...
usbh_status_enum | usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len)
send datas from the host channel More...
usbh_status_enum | usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num)
send the setup packet to the device More...
uint32_t | hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer More...

Variables

state_table_struct ctrl_handle_table [CTRL_HANDLE_TABLE_SIZE]
uint8_t ctrl_polling_handle_flag

Detailed Description

header file for usbh_ctrl.c

Definition in file usbh_ctrl.h.

Macro Definition Documentation

#define CTRL_HANDLE_TABLE_SIZE 13U

the ctrl handle table size define

Definition at line 18 of file usbh_ctrl.h.

Enumeration Type Documentation

enum ctrl_event_enum
Enumerator
CTRL_EVENT_IDLE
CTRL_EVENT_SETUP
CTRL_EVENT_DATA
CTRL_EVENT_STATUS
CTRL_EVENT_COMPLETE
CTRL_EVENT_ERROR
CTRL_EVENT_STALLED

Definition at line 24 of file usbh_ctrl.h.

25 {
26 CTRL_EVENT_IDLE = 0, /* the ctrl idle event */
27 CTRL_EVENT_SETUP, /* the ctrl setup event */
28 CTRL_EVENT_DATA, /* the ctrl data event */
29 CTRL_EVENT_STATUS, /* the ctrl status event */
30 CTRL_EVENT_COMPLETE, /* the ctrl complete event */
31 CTRL_EVENT_ERROR, /* the ctrl error event */
32 CTRL_EVENT_STALLED, /* the ctrl stalled event */
33 }ctrl_event_enum;
CTRL_EVENT_ERROR
Definition: usbh_ctrl.h:31
CTRL_EVENT_SETUP
Definition: usbh_ctrl.h:27
CTRL_EVENT_DATA
Definition: usbh_ctrl.h:28
ctrl_event_enum
ctrl_event_enum
Definition: usbh_ctrl.h:24
CTRL_EVENT_STALLED
Definition: usbh_ctrl.h:32
CTRL_EVENT_COMPLETE
Definition: usbh_ctrl.h:30
CTRL_EVENT_IDLE
Definition: usbh_ctrl.h:26
CTRL_EVENT_STATUS
Definition: usbh_ctrl.h:29

Function Documentation

usbh_status_enum ctrl_state_polling_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the polling function of CTRL state

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 72 of file usbh_ctrl.c.

75 {
76 usbh_status_enum exe_state = USBH_BUSY;
77 usbh_state_handle_struct *p_state;
78
79 p_state = (usbh_state_handle_struct *)pustate;
80
81 /* if first enter this function, begin the ctrl state */
82 if (0U == ctrl_polling_handle_flag) {
83 ctrl_polling_handle_flag = 1U;
84 scd_table_push(p_state);
85 scd_state_move(p_state, CTRL_IDLE);
86 }
87
88 /* base on the current state to handle the ctrl state */
89 scd_begin(p_state, CTRL_FSM_ID);
90 ctrl_state_handle[p_state->usbh_current_state](pudev, puhost, p_state);
91
92 /* determine the control transfer whether to complete */
93 switch (puhost->usbh_backup_state.ctrl_backup_state) {
94 case CTRL_COMPLETE:
95 ctrl_polling_handle_flag = 0U;
96 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
97 exe_state = USBH_OK;
98 break;
99 case CTRL_STALLED:
100 ctrl_polling_handle_flag = 0U;
101 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
102 exe_state = USBH_NOT_SUPPORTED;
103 break;
104 case CTRL_ERROR:
105 ctrl_polling_handle_flag = 0U;
106 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
107 exe_state = USBH_FAIL;
108 break;
109 default:
110 exe_state = USBH_BUSY;
111 break;
112 }
113
114 return exe_state;
115 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
usbh_state_handle_struct
Definition: usbh_core.h:227
ctrl_state_handle
void(* ctrl_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_ctrl.c:32
CTRL_IDLE
Definition: usbh_core.h:96
CTRL_ERROR
Definition: usbh_core.h:100
CTRL_FSM_ID
#define CTRL_FSM_ID
Definition: usbh_core.h:41
ctrl_polling_handle_flag
uint8_t ctrl_polling_handle_flag
Definition: usbh_ctrl.c:16
USBH_NOT_SUPPORTED
Definition: usbh_core.h:111
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:106
CTRL_STALLED
Definition: usbh_core.h:101
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:561
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:538
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:622
USBH_OK
Definition: usbh_core.h:108
USBH_FAIL
Definition: usbh_core.h:110
CTRL_COMPLETE
Definition: usbh_core.h:102
USBH_BUSY
Definition: usbh_core.h:109
uint32_t hcd_submit_request | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num
 | ) |  |

this function prepare a hc and start a transfer

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[out] | none
Return values
host operation status

Definition at line 604 of file usbh_ctrl.c.

605 {
606 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
607
608 puhc->urb_state = URB_IDLE;
609 puhc->xfer_count = 0U;
610
611 return (uint32_t)usb_hostchannel_startxfer(pudev, channel_num);
612 }
usb_hostchannel_struct::urb_state
urb_state_enum urb_state
Definition: usb_core.h:172
URB_IDLE
Definition: usb_core.h:50
usb_hostchannel_struct
Definition: usb_core.h:154
usb_hostchannel_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:167
usbh_status_enum usbh_ctltx_setup | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | buf,
 |  | uint8_t | hc_num
 | ) |  |

send the setup packet to the device

Parameters
[in] | pudev | pointer to usb device
[in] | buf | buffer pointer from which the data will be send to device
[in] | hc_num | host channel number
[out] | none
Return values
host operation status

Definition at line 586 of file usbh_ctrl.c.

587 {
588 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
589
590 puhc->DPID = HC_PID_SETUP;
591 puhc->xfer_buff = buf;
592 puhc->xfer_len = USBH_SETUP_PACKET_SIZE;
593
594 return (usbh_status_enum)hcd_submit_request (pudev, hc_num);
595 }
hcd_submit_request
uint32_t hcd_submit_request(usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer
Definition: usbh_ctrl.c:604
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:165
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:106
usb_hostchannel_struct
Definition: usb_core.h:154
USBH_SETUP_PACKET_SIZE
#define USBH_SETUP_PACKET_SIZE
Definition: usbh_std.h:22
usb_hostchannel_struct::DPID
uint8_t DPID
Definition: usb_core.h:158
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:166
HC_PID_SETUP
#define HC_PID_SETUP
Definition: usb_defines.h:71
usbh_status_enum usbh_xfer | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | buf,
 |  | uint8_t | hc_num,
 |  | uint16_t | len
 | ) |  |

send datas from the host channel

Parameters
[in] | pudev | pointer to usb device
[in] | buf | data buffer address to send datas
[in] | hc_num | the number of the host channel
[in] | len | length of the send data
[out] | none
Return values
host operation status

Definition at line 493 of file usbh_ctrl.c.

497 {
498 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
499
500 puhc->xfer_buff = buf;
501 puhc->xfer_len = len;
502
503 switch (puhc->endp_type) {
504 case USB_EPTYPE_CTRL:
505 if (0U == puhc->endp_in) {
506 if (0U == len) {
507 /* for status out stage, length = 0, status out pid = 1 */
508 puhc->data_tg_out = 1U;
509 }
510
511 /* set the data toggle bit as per the flag */
512 if (0U == puhc->data_tg_out) {
513 /* put the pid 0 */
514 puhc->DPID = HC_PID_DATA0;
515 } else {
516 /* put the pid 1 */
517 puhc->DPID = HC_PID_DATA1;
518 }
519 } else {
520 puhc->DPID = HC_PID_DATA1;
521 }
522 break;
523
524 case USB_EPTYPE_ISOC:
525 puhc->DPID = HC_PID_DATA0;
526 break;
527
528 case USB_EPTYPE_BULK:
529 if (0U == puhc->endp_in) {
530 /* set the data toggle bit as per the flag */
531 if (0U == puhc->data_tg_out) {
532 /* put the pid 0 */
533 puhc->DPID = HC_PID_DATA0;
534 } else {
535 /* put the pid 1 */
536 puhc->DPID = HC_PID_DATA1;
537 }
538 } else {
539 if (0U == puhc->data_tg_in) {
540 puhc->DPID = HC_PID_DATA0;
541 } else {
542 puhc->DPID = HC_PID_DATA1;
543 }
544 }
545 break;
546
547 case USB_EPTYPE_INTR:
548 if (0U == puhc->endp_in) {
549 if (0U == puhc->data_tg_out) {
550 puhc->DPID = HC_PID_DATA0;
551 } else {
552 puhc->DPID = HC_PID_DATA1;
553 }
554
555 /* toggle data pid */
556 puhc->data_tg_out ^= 1U;
557 } else {
558 if (0U == puhc->data_tg_in) {
559 puhc->DPID = HC_PID_DATA0;
560 } else {
561 puhc->DPID = HC_PID_DATA1;
562 }
563
564 /* toggle data pid */
565 puhc->data_tg_in ^= 1U;
566 }
567 break;
568
569 default:
570 break;
571 }
572
573 hcd_submit_request (pudev, hc_num);
574
575 return USBH_OK;
576 }
hcd_submit_request
uint32_t hcd_submit_request(usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer
Definition: usbh_ctrl.c:604
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:52
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:165
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:175
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:54
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:160
USB_EPTYPE_CTRL
#define USB_EPTYPE_CTRL
Definition: usb_defines.h:51
HC_PID_DATA1
#define HC_PID_DATA1
Definition: usb_defines.h:70
usb_hostchannel_struct
Definition: usb_core.h:154
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:174
HC_PID_DATA0
#define HC_PID_DATA0
Definition: usb_defines.h:68
usb_hostchannel_struct::DPID
uint8_t DPID
Definition: usb_core.h:158
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:166
USBH_OK
Definition: usbh_core.h:108
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:161
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:53

Variable Documentation

state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]

Definition at line 46 of file usbh_ctrl.c.

uint8_t ctrl_polling_handle_flag

Definition at line 16 of file usbh_ctrl.c.

Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_hcs.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
Macros | Functions
usbh_hcs.h File Reference

header file for usbh_hcs.c More...

#include "usbh_core.h"

Go to the source code of this file.

Macros

#define | HC_MAX 8U
#define | HC_OK 0x0000U
#define | HC_USED 0x8000U
#define | HC_ERROR 0xFFFFU
#define | HC_USED_MASK 0x7FFFU

Functions

uint8_t | usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr)
allocate a new channel for the pipe More...
uint8_t | usbh_allchannel_dealloc (usb_core_handle_struct *pudev)
free all usb host channel More...
uint8_t | usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index)
free the usb host channel More...
uint8_t | usbh_channel_open (usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
open a channel More...
uint8_t | usbh_channel_modify (usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
modify a channel More...

Detailed Description

header file for usbh_hcs.c

Definition in file usbh_hcs.h.

Macro Definition Documentation

#define HC_ERROR 0xFFFFU

Definition at line 21 of file usbh_hcs.h.

#define HC_MAX 8U

Definition at line 17 of file usbh_hcs.h.

#define HC_OK 0x0000U

Definition at line 19 of file usbh_hcs.h.

#define HC_USED 0x8000U

Definition at line 20 of file usbh_hcs.h.

#define HC_USED_MASK 0x7FFFU

Definition at line 22 of file usbh_hcs.h.

Function Documentation

uint8_t usbh_allchannel_dealloc ( usb_core_handle_struct * pudev )

free all usb host channel

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
host operation status

Definition at line 129 of file usbh_hcs.c.

130 {
131 uint8_t index;
132
133 for (index = 2U; index < HC_MAX; index ++) {
134 pudev->host.host_channel[index].info = 0U;
135 }
136
137 return USBH_OK;
138 }
HC_MAX
#define HC_MAX
Definition: usbh_hcs.h:17
USBH_OK
Definition: usbh_core.h:108
uint8_t usbh_channel_alloc | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

allocate a new channel for the pipe

Parameters
[in] | pudev | pointer to usb device
[in] | ep_addr | endpoint for which the channel to be allocated
[out] | none
Return values
host channel number

Definition at line 96 of file usbh_hcs.c.

97 {
98 uint16_t hc_num = usbh_freechannel_get(pudev);
99
100 if ((uint16_t)HC_ERROR != hc_num) {
101 pudev->host.host_channel[hc_num].info = HC_USED | ep_addr;
102 }
103
104 return (uint8_t)hc_num;
105 }
HC_USED
#define HC_USED
Definition: usbh_hcs.h:20
HC_ERROR
#define HC_ERROR
Definition: usbh_hcs.h:21
uint8_t usbh_channel_free | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | index
 | ) |  |

free the usb host channel

Parameters
[in] | pudev | pointer to usb device
[in] | index | channel number to be freed which is in (0..7)
[out] | none
Return values
host operation status

Definition at line 114 of file usbh_hcs.c.

115 {
116 if (index < HC_MAX) {
117 pudev->host.host_channel[index].info &= HC_USED_MASK;
118 }
119
120 return USBH_OK;
121 }
HC_MAX
#define HC_MAX
Definition: usbh_hcs.h:17
HC_USED_MASK
#define HC_USED_MASK
Definition: usbh_hcs.h:22
USBH_OK
Definition: usbh_core.h:108
uint8_t usbh_channel_modify | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num,
 |  | uint8_t | dev_addr,
 |  | uint8_t | dev_speed,
 |  | uint8_t | ep_type,
 |  | uint16_t | ep_mps
 | ) |  |

modify a channel

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[in] | dev_addr | USB Device address allocated to attached device
[in] | dev_speed | USB device speed (Full speed/Low speed)
[in] | ep_type | endpoint type (bulk/int/ctl)
[in] | ep_mps | max packet size
[out] | none
Return values
operation status

Definition at line 63 of file usbh_hcs.c.

69 {
70 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
71
72 if (0U != dev_addr) {
73 puhc->dev_addr = dev_addr;
74 }
75
76 if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) {
77 puhc->endp_mps = ep_mps;
78 }
79
80 if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) {
81 puhc->dev_speed = dev_speed;
82 }
83
84 usb_hostchannel_init(pudev, channel_num);
85
86 return (uint8_t)HC_OK;
87 }
usb_hostchannel_struct
Definition: usb_core.h:154
usb_hostchannel_struct::endp_mps
uint16_t endp_mps
Definition: usb_core.h:162
usb_hostchannel_struct::dev_addr
uint8_t dev_addr
Definition: usb_core.h:156
usb_hostchannel_struct::dev_speed
uint8_t dev_speed
Definition: usb_core.h:157
HC_OK
#define HC_OK
Definition: usbh_hcs.h:19
uint8_t usbh_channel_open | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num,
 |  | uint8_t | dev_addr,
 |  | uint8_t | dev_speed,
 |  | uint8_t | ep_type,
 |  | uint16_t | ep_mps
 | ) |  |

open a channel

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[in] | dev_addr | USB device address allocated to attached device
[in] | dev_speed | USB device speed (Full speed/Low speed)
[in] | ep_type | endpoint type (bulk/int/ctl)
[in] | ep_mps | max packet size
[out] | none
Return values
operation status

Definition at line 27 of file usbh_hcs.c.

33 {
34 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
35 uint16_t channel_info = puhc->info;
36
37 puhc->endp_id = (uint8_t)channel_info & 0x7FU;
38 puhc->endp_in = (uint8_t)(channel_info & 0x80U) >> 7;
39 puhc->endp_type = ep_type;
40 puhc->endp_mps = ep_mps;
41 puhc->dev_addr = dev_addr;
42 puhc->dev_speed = dev_speed;
43
44 puhc->data_tg_in = 0U;
45 puhc->data_tg_out = 0U;
46
47 usb_hostchannel_init(pudev, channel_num);
48
49 return (uint8_t)HC_OK;
50 }
usb_hostchannel_struct::info
uint16_t info
Definition: usb_core.h:163
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:175
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:160
usb_hostchannel_struct
Definition: usb_core.h:154
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:174
usb_hostchannel_struct::endp_mps
uint16_t endp_mps
Definition: usb_core.h:162
usb_hostchannel_struct::dev_addr
uint8_t dev_addr
Definition: usb_core.h:156
usb_hostchannel_struct::dev_speed
uint8_t dev_speed
Definition: usb_core.h:157
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:161
HC_OK
#define HC_OK
Definition: usbh_hcs.h:19
usb_hostchannel_struct::endp_id
uint8_t endp_id
Definition: usb_core.h:159
Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_int.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
Data Structures | Functions | Variables
usbh_int.h File Reference

USB host mode interrupt handler header file. More...

#include "usb_core.h"

Go to the source code of this file.

Data Structures

struct usbh_hcd_int_cb_struct

Functions

uint32_t usbh_isr (usb_core_handle_struct *pudev)
handle global host interrupt More...

Variables

usbh_hcd_int_cb_struct * usbh_hcd_int_fops

Detailed Description

USB host mode interrupt handler header file.

Definition in file usbh_int.h.

Function Documentation

uint32_t usbh_isr ( usb_core_handle_struct * pudev )

handle global host interrupt

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
operation status

Definition at line 33 of file usbh_int.c.

34 {
35 uint32_t retval = 0U;
36 uint32_t int_flag = 0U;
37
38 /* check if host mode */
39 if (USB_CURRENT_MODE_GET() == HOST_MODE) {
40 USB_CORE_INTR_READ(int_flag);
41
42 if (!int_flag) {
43 return 0U;
44 }
45
46 /* start of frame interrupt handle */
47 if (int_flag & GINTF_SOF) {
48 retval |= usbh_intf_sof (pudev);
49 }
50
51 /* Rx FIFO non-empty interrupt handle */
52 if (int_flag & GINTF_RXFNEIF) {
53 retval |= usbh_intf_rxfifo_noempty (pudev);
54 }
55
56 /* Non-Periodic Tx FIFO empty interrupt hanlde */
57 if (int_flag & GINTF_NPTXFEIF) {
58 retval |= usbh_intf_nptxfifo_empty (pudev);
59 }
60
61 /* periodic Tx FIFO empty interrupt handle */
62 if (int_flag & GINTF_PTXFEIF) {
63 retval |= usbh_intf_ptxfifo_empty (pudev);
64 }
65
66 /* host channels interrupt handle */
67 if (int_flag & GINTF_HCIF) {
68 retval |= usbh_intf_hc (pudev);
69 }
70
71 /* host port interrupt handle */
72 if (int_flag & GINTF_HPIF) {
73 retval |= usbh_intf_port (pudev);
74 }
75
76 /* disconnect interrupt handle */
77 if (int_flag & GINTF_DISCIF) {
78 retval |= usbh_intf_disconnect (pudev);
79 }
80
81 /* isochronous IN transfer not complete interrupt handle */
82 if (int_flag & GINTF_ISOONCIF) {
83 retval |= usbh_intf_iso_incomplete_xfer (pudev);
84 }
85 }
86
87 return retval;
88 }
USB_CORE_INTR_READ
#define USB_CORE_INTR_READ(x)
Definition: usb_regs.h:551
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:48
GINTF_RXFNEIF
#define GINTF_RXFNEIF
Definition: usb_regs.h:165
USB_CURRENT_MODE_GET
#define USB_CURRENT_MODE_GET()
Definition: usb_regs.h:548
GINTF_HCIF
#define GINTF_HCIF
Definition: usb_regs.h:149
GINTF_HPIF
#define GINTF_HPIF
Definition: usb_regs.h:150
GINTF_NPTXFEIF
#define GINTF_NPTXFEIF
Definition: usb_regs.h:164
GINTF_ISOONCIF
#define GINTF_ISOONCIF
Definition: usb_regs.h:152
GINTF_PTXFEIF
#define GINTF_PTXFEIF
Definition: usb_regs.h:148
GINTF_SOF
#define GINTF_SOF
Definition: usb_regs.h:166
GINTF_DISCIF
#define GINTF_DISCIF
Definition: usb_regs.h:146

Variable Documentation

usbh_hcd_int_cb_struct* usbh_hcd_int_fops

Definition at line 33 of file usbh_core.c.

Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_std.h File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
Macros | Enumerations | Functions | Variables
usbh_std.h File Reference

header file for usbh_std.c More...

#include "usbh_core.h"
#include "usbh_usr.h"

Go to the source code of this file.

Macros

#define | FEATURE_SELECTOR_ENDPOINT 0x00U
#define | FEATURE_SELECTOR_DEVICE 0x01U
#define | USBH_SETUP_PACKET_SIZE 8U /* setup packet size */
#define | ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */

Enumerations

enum enum_event_enum {
ENUN_EVENT_IDLE = 0, ENUM_EVENT_SET_ADDR, ENUN_EVENT_GET_FULL_DEV_DESC, ENUN_EVENT_GET_CFG_DESC,
ENUN_EVENT_GET_FULL_CFG_DESC, ENUN_EVENT_GET_MFC_STRING_DESC, ENUN_EVENT_GET_PRODUCT_STRING_DESC, ENUN_EVENT_GET_SERIALNUM_STRING_DESC,
ENUN_EVENT_SET_CONFIGURATION, ENUN_EVENT_DEV_CONFIGURED
}

Functions

usbh_status_enum | enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of enumeration state More...
void | usbh_enum_desc_get (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t *buf, uint8_t req_type, uint16_t value_idx, uint16_t len)
get descriptor in usb host enumeration stage More...
void | usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address)
set address in usb host enumeration stage More...
void | usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx)
set configuration in usb host enumeration stage More...
void | usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len)
parse the device descriptor More...
void | usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, usb_descriptor_interface_struct *itf_desc, usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], uint8_t *buf, uint16_t len)
parse the configuration descriptor More...
void | usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf)
parse the interface descriptor More...
void | usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf)
parse the endpoint descriptor More...
void | usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len)
parse the string descriptor More...
usb_descriptor_header_struct * | usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr)
get the next descriptor header More...

Variables

uint8_t | usbh_cfg_desc [512]
uint8_t | enum_polling_handle_flag
state_table_struct enum_handle_table [ENUM_HANDLE_TABLE_SIZE]

Detailed Description

header file for usbh_std.c

Definition in file usbh_std.h.

Macro Definition Documentation

#define ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */

Definition at line 23 of file usbh_std.h.

#define FEATURE_SELECTOR_DEVICE 0x01U

Definition at line 20 of file usbh_std.h.

#define FEATURE_SELECTOR_ENDPOINT 0x00U

Definition at line 19 of file usbh_std.h.

#define USBH_SETUP_PACKET_SIZE 8U /* setup packet size */

Definition at line 22 of file usbh_std.h.

Enumeration Type Documentation

enum enum_event_enum
Enumerator
ENUN_EVENT_IDLE
ENUM_EVENT_SET_ADDR
ENUN_EVENT_GET_FULL_DEV_DESC
ENUN_EVENT_GET_CFG_DESC
ENUN_EVENT_GET_FULL_CFG_DESC
ENUN_EVENT_GET_MFC_STRING_DESC
ENUN_EVENT_GET_PRODUCT_STRING_DESC
ENUN_EVENT_GET_SERIALNUM_STRING_DESC
ENUN_EVENT_SET_CONFIGURATION
ENUN_EVENT_DEV_CONFIGURED

Definition at line 29 of file usbh_std.h.

30 {
31 ENUN_EVENT_IDLE = 0, /* the enum idle event */
32 ENUM_EVENT_SET_ADDR, /* the enum set address event */
33 ENUN_EVENT_GET_FULL_DEV_DESC, /* the enum get full device descripter event */
34 ENUN_EVENT_GET_CFG_DESC, /* the enum get congiguration descripter event */
35 ENUN_EVENT_GET_FULL_CFG_DESC, /* the enum get full configuration descripter event */
36 ENUN_EVENT_GET_MFC_STRING_DESC, /* the enum get MFC string descripter event */
37 ENUN_EVENT_GET_PRODUCT_STRING_DESC, /* the enum get product string event */
38 ENUN_EVENT_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string event */
39 ENUN_EVENT_SET_CONFIGURATION, /* the enum set configuration event */
40 ENUN_EVENT_DEV_CONFIGURED /* the enum device configured event */
41 }enum_event_enum;
ENUN_EVENT_GET_SERIALNUM_STRING_DESC
Definition: usbh_std.h:38
enum_event_enum
enum_event_enum
Definition: usbh_std.h:29
ENUN_EVENT_DEV_CONFIGURED
Definition: usbh_std.h:40
ENUN_EVENT_SET_CONFIGURATION
Definition: usbh_std.h:39
ENUN_EVENT_GET_PRODUCT_STRING_DESC
Definition: usbh_std.h:37
ENUN_EVENT_GET_CFG_DESC
Definition: usbh_std.h:34
ENUN_EVENT_GET_FULL_CFG_DESC
Definition: usbh_std.h:35
ENUN_EVENT_GET_MFC_STRING_DESC
Definition: usbh_std.h:36
ENUN_EVENT_GET_FULL_DEV_DESC
Definition: usbh_std.h:33
ENUN_EVENT_IDLE
Definition: usbh_std.h:31
ENUM_EVENT_SET_ADDR
Definition: usbh_std.h:32

Function Documentation

usbh_status_enum enum_state_polling_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the polling function of enumeration state

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | pustate | pointer to USB state driver
[out] | none
Return values
usb host status

Definition at line 71 of file usbh_std.c.

72 {
73 usbh_status_enum exe_state = USBH_BUSY;
74 usbh_state_handle_struct *p_state;
75 p_state = (usbh_state_handle_struct *)pustate;
76
77 if (0U == enum_polling_handle_flag) {
78 enum_polling_handle_flag = 1U;
79 scd_table_push(p_state);
80 scd_state_move(p_state, ENUM_IDLE);
81 }
82
83 /* start the enumeration state handle */
84 scd_begin(p_state,ENUM_FSM_ID);
85
86 if (0 == p_state->usbh_current_state_stack_top) {
87 enum_state_handle[p_state->usbh_current_state](pudev, puhost, p_state);
88 } else {
89 enum_state_handle[p_state->stack[1].state](pudev, puhost, p_state);
90 }
91
92 /* determine the enumeration whether to complete */
93 if (ENUM_DEV_CONFIGURED == puhost->usbh_backup_state.enum_backup_state) {
94 puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE;
95 enum_polling_handle_flag = 0U;
96 exe_state = USBH_OK;
97 }
98
99 return exe_state;
100 }
ENUM_DEV_CONFIGURED
Definition: usbh_core.h:90
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
enum_polling_handle_flag
uint8_t enum_polling_handle_flag
Definition: usbh_std.c:19
usbh_state_handle_struct
Definition: usbh_core.h:227
ENUM_FSM_ID
#define ENUM_FSM_ID
Definition: usbh_core.h:39
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:213
ENUM_IDLE
Definition: usbh_core.h:81
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:106
backup_state_struct::enum_backup_state
enum_state_enum enum_backup_state
Definition: usbh_core.h:181
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:561
enum_state_handle
void(* enum_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_std.c:33
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:538
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:233
usbh_host_struct::usbh_backup_state
backup_state_struct usbh_backup_state
Definition: usbh_core.h:190
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:622
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:234
USBH_OK
Definition: usbh_core.h:108
USBH_BUSY
Definition: usbh_core.h:109
void usbh_cfg_desc_parse | ( | usb_descriptor_configuration_struct * | cfg_desc,
 |  | usb_descriptor_interface_struct * | itf_desc,
 |  | usb_descriptor_endpoint_struct | ep_desc[][USBH_MAX_EP_NUM],
 |  | uint8_t * | buf,
 |  | uint16_t | len
 | ) |  |

parse the configuration descriptor

Parameters
[in] | cfg_desc | configuration descriptor address
[in] | itf_desc | interface descriptor address
[in] | ep_desc | endpoint descriptor address
[in] | buf | buffer where the source descriptor is available
[in] | len | length of the descriptor
[out] | none
Return values
none

Definition at line 637 of file usbh_std.c.

642 {
643 usb_descriptor_interface_struct *pitf = NULL;
644 usb_descriptor_interface_struct temp_pitf;
645 usb_descriptor_endpoint_struct *pep = NULL;
646 usb_descriptor_header_struct *pdesc = (usb_descriptor_header_struct *)buf;
647
648 uint8_t itf_ix = 0U;
649 uint8_t ep_ix = 0U;
650 uint16_t ptr = 0U;
651 static uint8_t prev_itf = 0U;
652 static uint16_t prev_ep_size = 0U;
653
654 /* parse configuration descriptor */
655 cfg_desc->Header.bLength = *(uint8_t *)(buf + 0);
656 cfg_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
657 cfg_desc->wTotalLength = SWAPBYTE(buf + 2);
658 cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4);
659 cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5);
660 cfg_desc->iConfiguration = *(uint8_t *)(buf + 6);
661 cfg_desc->bmAttributes = *(uint8_t *)(buf + 7);
662 cfg_desc->bMaxPower = *(uint8_t *)(buf + 8);
663
664 if (len > USB_CFGDESC_SIZE) {
665 ptr = USB_CFG_DESC_LEN;
666
667 if (cfg_desc->bNumInterfaces <= USBH_MAX_INTERFACES_NUM) {
668 pitf = (usb_descriptor_interface_struct *)0;
669
670 for (; ptr < cfg_desc->wTotalLength; ) {
671 pdesc = usbh_next_desc_get((uint8_t *)pdesc, &ptr);
672
673 if (USB_DESCTYPE_INTERFACE == pdesc->bDescriptorType) {
674 itf_ix = *((uint8_t *)pdesc + 2U);
675 pitf = &itf_desc[itf_ix];
676
677 if (*((uint8_t *)pdesc + 3U) < 3U) {
678 usbh_interface_desc_parse (&temp_pitf, (uint8_t *)pdesc);
679
680 /* parse endpoint descriptors relative to the current interface */
681 if (temp_pitf.bNumEndpoints <= USBH_MAX_EP_NUM) {
682 for (ep_ix = 0U; ep_ix < temp_pitf.bNumEndpoints;) {
683 pdesc = usbh_next_desc_get((void* )pdesc, &ptr);
684
685 if (USB_DESCTYPE_ENDPOINT == pdesc->bDescriptorType) {
686 pep = &ep_desc[itf_ix][ep_ix];
687
688 if (prev_itf != itf_ix) {
689 prev_itf = itf_ix;
690 usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf);
691 } else {
692 if (prev_ep_size > SWAPBYTE((uint8_t *)pdesc + 4)) {
693 break;
694 } else {
695 usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf);
696 }
697 }
698
699 usbh_endpoint_desc_parse (pep, (uint8_t *)pdesc);
700 prev_ep_size = SWAPBYTE((uint8_t *)pdesc + 4);
701 ep_ix++;
702 }
703 }
704 }
705 }
706 }
707 }
708 }
709
710 prev_ep_size = 0U;
711 prev_itf = 0U;
712 }
713 }
usb_descriptor_configuration_struct::bmAttributes
uint8_t bmAttributes
Definition: usb_std.h:153
usb_descriptor_configuration_struct::wTotalLength
uint16_t wTotalLength
Definition: usb_std.h:149
usb_descriptor_configuration_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:147
usbh_endpoint_desc_parse
void usbh_endpoint_desc_parse(usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf)
parse the endpoint descriptor
Definition: usbh_std.c:742
usb_descriptor_interface_struct::bNumEndpoints
uint8_t bNumEndpoints
Definition: usb_std.h:163
USB_CFG_DESC_LEN
#define USB_CFG_DESC_LEN
Definition: usb_std.h:19
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usb_std.h:123
usb_descriptor_interface_struct
Definition: usb_std.h:157
usb_descriptor_header_struct
Definition: usb_std.h:121
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usb_std.h:85
usbh_interface_desc_parse
void usbh_interface_desc_parse(usb_descriptor_interface_struct *itf_desc, uint8_t *buf)
parse the interface descriptor
Definition: usbh_std.c:722
usb_descriptor_configuration_struct::bConfigurationValue
uint8_t bConfigurationValue
Definition: usb_std.h:151
usb_descriptor_endpoint_struct
Definition: usb_std.h:170
USB_DESCTYPE_INTERFACE
#define USB_DESCTYPE_INTERFACE
Definition: usb_std.h:58
usbh_next_desc_get
usb_descriptor_header_struct * usbh_next_desc_get(uint8_t *pbuf, uint16_t *ptr)
get the next descriptor header
Definition: usbh_std.c:795
usb_descriptor_configuration_struct::bNumInterfaces
uint8_t bNumInterfaces
Definition: usb_std.h:150
USB_CFGDESC_SIZE
#define USB_CFGDESC_SIZE
Definition: usb_std.h:68
NULL
#define NULL
Definition: usb_defines.h:18
usb_descriptor_configuration_struct::iConfiguration
uint8_t iConfiguration
Definition: usb_std.h:152
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usb_std.h:124
usb_descriptor_configuration_struct::bMaxPower
uint8_t bMaxPower
Definition: usb_std.h:154
USB_DESCTYPE_ENDPOINT
#define USB_DESCTYPE_ENDPOINT
Definition: usb_std.h:59
void usbh_device_desc_parse | ( | usb_descriptor_device_struct * | dev_desc,
 |  | uint8_t * | buf,
 |  | uint16_t | len
 | ) |  |

parse the device descriptor

Parameters
[in] | dev_desc | device_descriptor destinaton address
[in] | buf | buffer where the source descriptor is available
[in] | len | length of the descriptor
[out] | none
Return values
none

Definition at line 605 of file usbh_std.c.

606 {
607 dev_desc->Header.bLength = *(uint8_t *)(buf + 0);
608 dev_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
609 dev_desc->bcdUSB = SWAPBYTE(buf + 2);
610 dev_desc->bDeviceClass = *(uint8_t *)(buf + 4);
611 dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5);
612 dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6);
613 dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7);
614
615 if (len > 8U){
616 /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */
617 dev_desc->idVendor = SWAPBYTE(buf + 8);
618 dev_desc->idProduct = SWAPBYTE(buf + 10);
619 dev_desc->bcdDevice = SWAPBYTE(buf + 12);
620 dev_desc->iManufacturer = *(uint8_t *)(buf + 14);
621 dev_desc->iProduct = *(uint8_t *)(buf + 15);
622 dev_desc->iSerialNumber = *(uint8_t *)(buf + 16);
623 dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17);
624 }
625 }
usb_descriptor_device_struct::idProduct
uint16_t idProduct
Definition: usb_std.h:137
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usb_std.h:123
usb_descriptor_device_struct::bcdUSB
uint16_t bcdUSB
Definition: usb_std.h:131
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usb_std.h:85
usb_descriptor_device_struct::bDeviceProtocol
uint8_t bDeviceProtocol
Definition: usb_std.h:134
usb_descriptor_device_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:129
usb_descriptor_device_struct::bcdDevice
uint16_t bcdDevice
Definition: usb_std.h:138
usb_descriptor_device_struct::bDeviceSubClass
uint8_t bDeviceSubClass
Definition: usb_std.h:133
usb_descriptor_device_struct::bNumberConfigurations
uint8_t bNumberConfigurations
Definition: usb_std.h:142
usb_descriptor_device_struct::idVendor
uint16_t idVendor
Definition: usb_std.h:136
usb_descriptor_device_struct::iProduct
uint8_t iProduct
Definition: usb_std.h:140
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usb_std.h:124
usb_descriptor_device_struct::bDeviceClass
uint8_t bDeviceClass
Definition: usb_std.h:132
usb_descriptor_device_struct::bMaxPacketSize0
uint8_t bMaxPacketSize0
Definition: usb_std.h:135
usb_descriptor_device_struct::iManufacturer
uint8_t iManufacturer
Definition: usb_std.h:139
usb_descriptor_device_struct::iSerialNumber
uint8_t iSerialNumber
Definition: usb_std.h:141
void usbh_endpoint_desc_parse | ( | usb_descriptor_endpoint_struct * | ep_desc,
 |  | uint8_t * | buf
 | ) |  |

parse the endpoint descriptor

Parameters
[in] | ep_desc | endpoint descriptor destination address
[in] | buf | buffer where the parsed descriptor stored
[out] | none
Return values
none

Definition at line 742 of file usbh_std.c.

743 {
744 ep_desc->Header.bLength = *(uint8_t *)(buf + 0);
745 ep_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
746 ep_desc->bEndpointAddress = *(uint8_t *)(buf + 2);
747 ep_desc->bmAttributes = *(uint8_t *)(buf + 3);
748 ep_desc->wMaxPacketSize = SWAPBYTE(buf + 4);
749 ep_desc->bInterval = *(uint8_t *)(buf + 6);
750 }
usb_descriptor_endpoint_struct::bmAttributes
uint8_t bmAttributes
Definition: usb_std.h:175
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usb_std.h:123
usb_descriptor_endpoint_struct::bEndpointAddress
uint8_t bEndpointAddress
Definition: usb_std.h:174
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usb_std.h:85
usb_descriptor_endpoint_struct::wMaxPacketSize
uint16_t wMaxPacketSize
Definition: usb_std.h:176
usb_descriptor_endpoint_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:172
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usb_std.h:124
usb_descriptor_endpoint_struct::bInterval
uint8_t bInterval
Definition: usb_std.h:177
void usbh_enum_addr_set | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | uint8_t | device_address
 | ) |  |

set address in usb host enumeration stage

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | device_address | the device address
[out] | none
Return values
none

Definition at line 559 of file usbh_std.c.

562 {
563 usb_setup_union *p_setup = &(puhost->control.setup);
564
565 p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ;
566 p_setup->b.bRequest = USBREQ_SET_ADDRESS;
567 p_setup->b.wValue = (uint16_t)device_address;
568 p_setup->b.wIndex = 0U;
569 p_setup->b.wLength = 0U;
570 puhost->control.buff = 0U;
571 puhost->control.length = 0U;
572 }
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:116
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usb_std.h:30
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:113
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:133
usb_setup_union
Definition: usb_std.h:107
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:117
USB_DIR_OUT
#define USB_DIR_OUT
Definition: usb_std.h:26
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:115
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:131
USB_REQTYPE_DEVICE
#define USB_REQTYPE_DEVICE
Definition: usb_std.h:36
USBREQ_SET_ADDRESS
#define USBREQ_SET_ADDRESS
Definition: usb_std.h:45
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:114
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:191
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:134
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
void usbh_enum_cfg_set | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | uint16_t | cfg_idx
 | ) |  |

set configuration in usb host enumeration stage

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | cfg_idx | the index of the configuration
[out] | none
Return values
none

Definition at line 582 of file usbh_std.c.

585 {
586 usb_setup_union *p_setup = &(puhost->control.setup);
587
588 p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ;
589 p_setup->b.bRequest = USBREQ_SET_CONFIGURATION;
590 p_setup->b.wValue = cfg_idx;
591 p_setup->b.wIndex = 0U;
592 p_setup->b.wLength = 0U;
593 puhost->control.buff = 0;
594 puhost->control.length = 0U;
595 }
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:116
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usb_std.h:30
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:113
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:133
usb_setup_union
Definition: usb_std.h:107
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:117
USB_DIR_OUT
#define USB_DIR_OUT
Definition: usb_std.h:26
USBREQ_SET_CONFIGURATION
#define USBREQ_SET_CONFIGURATION
Definition: usb_std.h:49
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:115
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:131
USB_REQTYPE_DEVICE
#define USB_REQTYPE_DEVICE
Definition: usb_std.h:36
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:114
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:191
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:134
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
void usbh_enum_desc_get | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | uint8_t * | buf,
 |  | uint8_t | req_type,
 |  | uint16_t | value_idx,
 |  | uint16_t | len
 | ) |  |

get descriptor in usb host enumeration stage

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | buf | buffer to store the descriptor
[in] | ReqType | descriptor type
[in] | ValueIdx | wValue for the GetDescriptr request
[in] | Len | length of the descriptor
[out] | none
Return values
none

Definition at line 525 of file usbh_std.c.

531 {
532 usb_setup_union *pSetup = &(puhost->control.setup);
533
534 pSetup->b.bmRequestType = USB_DIR_IN | req_type;
535 pSetup->b.bRequest = USBREQ_GET_DESCRIPTOR;
536 pSetup->b.wValue = value_idx;
537
538 if (USB_STRDESC == (value_idx & 0xff00U)){
539 pSetup->b.wIndex = 0x0409U;
540 } else {
541 pSetup->b.wIndex = 0U;
542 }
543
544 pSetup->b.wLength = len;
545
546 puhost->control.buff = buf;
547 puhost->control.length = len;
548
549 }
USB_STRDESC
#define USB_STRDESC
Definition: usb_std.h:76
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:116
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:113
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:133
USBREQ_GET_DESCRIPTOR
#define USBREQ_GET_DESCRIPTOR
Definition: usb_std.h:46
usb_setup_union
Definition: usb_std.h:107
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:117
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:115
USB_DIR_IN
#define USB_DIR_IN
Definition: usb_std.h:27
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:131
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:114
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:191
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:134
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
void usbh_interface_desc_parse | ( | usb_descriptor_interface_struct * | itf_desc,
 |  | uint8_t * | buf
 | ) |  |

parse the interface descriptor

Parameters
[in] | itf_desc | interface descriptor destination
[in] | buf | buffer where the descriptor data is available
[out] | none
Return values
none

Definition at line 722 of file usbh_std.c.

723 {
724 itf_desc->Header.bLength = *(uint8_t *)(buf + 0);
725 itf_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
726 itf_desc->bInterfaceNumber = *(uint8_t *)(buf + 2);
727 itf_desc->bAlternateSetting = *(uint8_t *)(buf + 3);
728 itf_desc->bNumEndpoints = *(uint8_t *)(buf + 4);
729 itf_desc->bInterfaceClass = *(uint8_t *)(buf + 5);
730 itf_desc->bInterfaceSubClass = *(uint8_t *)(buf + 6);
731 itf_desc->bInterfaceProtocol = *(uint8_t *)(buf + 7);
732 itf_desc->iInterface = *(uint8_t *)(buf + 8);
733 }
usb_descriptor_interface_struct::bInterfaceProtocol
uint8_t bInterfaceProtocol
Definition: usb_std.h:166
usb_descriptor_interface_struct::iInterface
uint8_t iInterface
Definition: usb_std.h:167
usb_descriptor_interface_struct::bNumEndpoints
uint8_t bNumEndpoints
Definition: usb_std.h:163
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usb_std.h:123
usb_descriptor_interface_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:159
usb_descriptor_interface_struct::bInterfaceClass
uint8_t bInterfaceClass
Definition: usb_std.h:164
usb_descriptor_interface_struct::bInterfaceSubClass
uint8_t bInterfaceSubClass
Definition: usb_std.h:165
usb_descriptor_interface_struct::bAlternateSetting
uint8_t bAlternateSetting
Definition: usb_std.h:162
usb_descriptor_interface_struct::bInterfaceNumber
uint8_t bInterfaceNumber
Definition: usb_std.h:161
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usb_std.h:124
usb_descriptor_header_struct* usbh_next_desc_get | ( | uint8_t * | pbuf,
 |  | uint16_t * | ptr
 | ) |  |

get the next descriptor header

Parameters
[in] | pbuf | pointer to buffer where the cfg descriptor is available
[in] | ptr | data popinter inside the configuration descriptor
[out] | none
Return values
next descriptor header

Definition at line 795 of file usbh_std.c.

796 {
797 uint8_t len = ((usb_descriptor_header_struct *)pbuf)->bLength;
798
799 usb_descriptor_header_struct *pnext;
800
801 *ptr += len;
802
803 pnext = (usb_descriptor_header_struct *)((uint8_t *)pbuf + len);
804
805 return(pnext);
806 }
usb_descriptor_header_struct
Definition: usb_std.h:121
void usbh_string_desc_parse | ( | uint8_t * | psrc,
 |  | uint8_t * | pdest,
 |  | uint16_t | len
 | ) |  |

parse the string descriptor

Parameters
[in] | psrc | source pointer containing the descriptor data
[in] | pdest | destination address pointer
[in] | len | length of the descriptor
[out] | none
Return values
none

Definition at line 760 of file usbh_std.c.

761 {
762 uint16_t strlength;
763 uint16_t idx;
764
765 /* the unicode string descriptor is not null-terminated. the string length is
766 computed by substracting two from the value of the first byte of the descriptor.
767 */
768
769 /* check which is lower size, the size of string or the length of bytes read from the device */
770
771 if (USB_DESCTYPE_STRING == psrc[1]){
772 /* make sure the descriptor is string type */
773
774 /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */
775 strlength = ((((uint16_t)psrc[0] - 2U) <= len) ? ((uint16_t)psrc[0] - 2U) : len);
776 psrc += 2; /* adjust the offset ignoring the string len and descriptor type */
777
778 for (idx = 0U; idx < strlength; idx += 2U) {
779 /* copy only the string and ignore the unicode id, hence add the src */
780 *pdest = psrc[idx];
781 pdest++;
782 }
783
784 *pdest = 0U; /* mark end of string */
785 }
786 }
USB_DESCTYPE_STRING
#define USB_DESCTYPE_STRING
Definition: usb_std.h:57

Variable Documentation

state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]

Definition at line 48 of file usbh_std.c.

uint8_t enum_polling_handle_flag

Definition at line 19 of file usbh_std.c.

uint8_t usbh_cfg_desc[512]

Definition at line 18 of file usbh_std.c.

Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source Directory Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
Source Directory Reference

Files

file | system_gd32f3x0.c [code]
CMSIS Cortex-M4 Device Peripheral Access Layer Source File for GD32F3x0 Device Series.
file | usb_core.c [code]
USB core driver which can operate in host-mode and device-mode.
file | usbd_core.c [code]
USB device mode core driver.
file | usbd_int.c [code]
USB device mode interrupt routines.
file | usbd_std.c [code]
USB 2.0 standard handler driver.
file | usbh_core.c [code]
this file implements the functions for the core state machine process
file | usbh_ctrl.c [code]
this file implements the functions for the control transmit process
file | usbh_hcs.c [code]
this file implements functions for opening and closing host channels
file | usbh_int.c [code]
USB host mode interrupt handler file.
file | usbh_std.c [code]
USB 2.0 standard function definition.


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/system_gd32f3x0.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
Macros | Functions | Variables
system_gd32f3x0.c File Reference

CMSIS Cortex-M4 Device Peripheral Access Layer Source File for GD32F3x0 Device Series. More...

#include "gd32f3x0.h"

Go to the source code of this file.

Macros

#define | __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
#define | __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
#define | __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
#define | SEL_IRC8M 0x00
#define | SEL_HXTAL 0x01
#define | SEL_PLL 0x02

Functions

void | SystemInit (void)
setup the microcontroller system, initialize the system More...
void | SystemCoreClockUpdate (void)
update the SystemCoreClock with current core clock retrieved from cpu registers More...

Variables

uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M

Detailed Description

CMSIS Cortex-M4 Device Peripheral Access Layer Source File for GD32F3x0 Device Series.

Definition in file system_gd32f3x0.c.

Macro Definition Documentation

#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */

Definition at line 40 of file system_gd32f3x0.c.

#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */

Definition at line 39 of file system_gd32f3x0.c.

#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */

Definition at line 41 of file system_gd32f3x0.c.

#define SEL_HXTAL 0x01

Definition at line 67 of file system_gd32f3x0.c.

#define SEL_IRC8M 0x00

Definition at line 66 of file system_gd32f3x0.c.

#define SEL_PLL 0x02

Definition at line 68 of file system_gd32f3x0.c.

Function Documentation

void SystemCoreClockUpdate ( void )

update the SystemCoreClock with current core clock retrieved from cpu registers

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 611 of file system_gd32f3x0.c.

612 {
613 uint32_t sws = 0U;
614 uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
615 /* exponent of AHB clock divider */
616 const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
617
618 sws = GET_BITS(RCU_CFG0, 2, 3);
619 switch(sws){
620 /* IRC8M is selected as CK_SYS */
621 case SEL_IRC8M:
622 SystemCoreClock = IRC8M_VALUE;
623 break;
624 /* HXTAL is selected as CK_SYS */
625 case SEL_HXTAL:
626 SystemCoreClock = HXTAL_VALUE;
627 break;
628 /* PLL is selected as CK_SYS */
629 case SEL_PLL:
630 /* get the value of PLLMF[3:0] */
631 pllmf = GET_BITS(RCU_CFG0, 18, 21);
632 pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
633 pllmf5 = GET_BITS(RCU_CFG1, 31, 31);
634 /* high 16 bits */
635 if(1U == pllmf4){
636 pllmf += 17U;
637 }else{
638 pllmf += 2U;
639 }
640 if(1U == pllmf5){
641 pllmf += 31U;
642 }
643 /* PLL clock source selection, HXTAL or IRC8M/2 */
644 pllsel = GET_BITS(RCU_CFG0, 16, 16);
645 if(0U != pllsel){
646 prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U);
647 if(0U == pllpresel){
648 SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf;
649 }else{
650 SystemCoreClock = (IRC48M_VALUE / prediv) * pllmf;
651 }
652 }else{
653 SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf;
654 }
655 break;
656 /* IRC8M is selected as CK_SYS */
657 default:
658 SystemCoreClock = IRC8M_VALUE;
659 break;
660 }
661 /* calculate AHB clock frequency */
662 idx = GET_BITS(RCU_CFG0, 4, 7);
663 clk_exp = ahb_exp[idx];
664 SystemCoreClock >>= clk_exp;
665 }
SystemCoreClock
uint32_t SystemCoreClock
Definition: system_gd32f3x0.c:108
SEL_HXTAL
#define SEL_HXTAL
Definition: system_gd32f3x0.c:67
RCU_CFG1
#define RCU_CFG1
Definition: gd32f3x0_rcu.h:32
SEL_IRC8M
#define SEL_IRC8M
Definition: system_gd32f3x0.c:66
SEL_PLL
#define SEL_PLL
Definition: system_gd32f3x0.c:68
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
void SystemInit ( void )

setup the microcontroller system, initialize the system

Parameters
[in] | none
[out] | none
Return values
none

Definition at line 121 of file system_gd32f3x0.c.

122 {
123 /* enable IRC8M */
124 RCU_CTL0 |= RCU_CTL0_IRC8MEN;
125 while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
126 }
127 /* reset RCU */
128 RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
129 RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
130 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
131 #if (defined(GD32F350))
132 RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC);
133 RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2);
134 #endif /* GD32F350 */
135 RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
136 RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL);
137 RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
138 RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
139 RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
140 RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
141 RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN;
142 RCU_INT = 0x00000000U;
143 RCU_ADDINT = 0x00000000U;
144 /* configure system clock */
145 system_clock_config();
146 }
RCU_CFG1_PLLMF5
#define RCU_CFG1_PLLMF5
Definition: gd32f3x0_rcu.h:190
RCU_CFG2_ADCPSC2
#define RCU_CFG2_ADCPSC2
Definition: gd32f3x0_rcu.h:198
RCU_INT
#define RCU_INT
Definition: gd32f3x0_rcu.h:23
RCU_CFG1_PLLPRESEL
#define RCU_CFG1_PLLPRESEL
Definition: gd32f3x0_rcu.h:189
RCU_CFG2_USBFSPSC2
#define RCU_CFG2_USBFSPSC2
Definition: gd32f3x0_rcu.h:197
RCU_CTL1_IRC28MEN
#define RCU_CTL1_IRC28MEN
Definition: gd32f3x0_rcu.h:201
RCU_CFG2_USART0SEL
#define RCU_CFG2_USART0SEL
Definition: gd32f3x0_rcu.h:193
RCU_CFG0_ADCPSC
#define RCU_CFG0_ADCPSC
Definition: gd32f3x0_rcu.h:61
RCU_CFG2_IRC28MDIV
#define RCU_CFG2_IRC28MDIV
Definition: gd32f3x0_rcu.h:196
RCU_CFG0_APB1PSC
#define RCU_CFG0_APB1PSC
Definition: gd32f3x0_rcu.h:59
RCU_CFG0_PLLMF4
#define RCU_CFG0_PLLMF4
Definition: gd32f3x0_rcu.h:67
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
RCU_CFG2_ADCSEL
#define RCU_CFG2_ADCSEL
Definition: gd32f3x0_rcu.h:195
RCU_CTL1
#define RCU_CTL1
Definition: gd32f3x0_rcu.h:34
RCU_CFG1
#define RCU_CFG1
Definition: gd32f3x0_rcu.h:32
RCU_CTL0_PLLEN
#define RCU_CTL0_PLLEN
Definition: gd32f3x0_rcu.h:52
RCU_CFG0_PLLMF
#define RCU_CFG0_PLLMF
Definition: gd32f3x0_rcu.h:64
RCU_CFG0_SCS
#define RCU_CFG0_SCS
Definition: gd32f3x0_rcu.h:56
RCU_CTL0_IRC8MSTB
#define RCU_CTL0_IRC8MSTB
Definition: gd32f3x0_rcu.h:45
RCU_CTL0_IRC8MEN
#define RCU_CTL0_IRC8MEN
Definition: gd32f3x0_rcu.h:44
RCU_ADDCTL
#define RCU_ADDCTL
Definition: gd32f3x0_rcu.h:35
RCU_CFG0_CKOUTSEL
#define RCU_CFG0_CKOUTSEL
Definition: gd32f3x0_rcu.h:66
RCU_CFG2_CECSEL
#define RCU_CFG2_CECSEL
Definition: gd32f3x0_rcu.h:194
RCU_CFG1_PREDV
#define RCU_CFG1_PREDV
Definition: gd32f3x0_rcu.h:188
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
RCU_CFG0_USBFSPSC
#define RCU_CFG0_USBFSPSC
Definition: gd32f3x0_rcu.h:65
RCU_CTL0_CKMEN
#define RCU_CTL0_CKMEN
Definition: gd32f3x0_rcu.h:51
RCU_CFG0_APB2PSC
#define RCU_CFG0_APB2PSC
Definition: gd32f3x0_rcu.h:60
RCU_CTL0_HXTALEN
#define RCU_CTL0_HXTALEN
Definition: gd32f3x0_rcu.h:48
RCU_CFG0_PLLDV
#define RCU_CFG0_PLLDV
Definition: gd32f3x0_rcu.h:69
RCU_ADDCTL_IRC48MEN
#define RCU_ADDCTL_IRC48MEN
Definition: gd32f3x0_rcu.h:208
RCU_ADDINT
#define RCU_ADDINT
Definition: gd32f3x0_rcu.h:36
RCU_CTL0_HXTALBPS
#define RCU_CTL0_HXTALBPS
Definition: gd32f3x0_rcu.h:50
RCU_CFG0_CKOUTDIV
#define RCU_CFG0_CKOUTDIV
Definition: gd32f3x0_rcu.h:68
RCU_CFG0_PLLSEL
#define RCU_CFG0_PLLSEL
Definition: gd32f3x0_rcu.h:62
RCU_CFG0_AHBPSC
#define RCU_CFG0_AHBPSC
Definition: gd32f3x0_rcu.h:58

Variable Documentation

uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M

Definition at line 108 of file system_gd32f3x0.c.

Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usb_core.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
Functions
usb_core.c File Reference

USB core driver which can operate in host-mode and device-mode. More...

#include "usb_core.h"

Go to the source code of this file.

Functions

usb_status_enum | usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint More...
void * | usb_fifo_read (uint8_t *dest, uint16_t len)
read a packet from the Rx FIFO associated with the endpoint More...
usb_status_enum | usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters More...
usb_status_enum | usb_core_init (usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation More...
usb_status_enum | usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs More...
usb_status_enum | usb_rxfifo_flush (usb_core_handle_struct *pudev)
flush the entire Rx FIFO More...
usb_status_enum | usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device) More...

Detailed Description

USB core driver which can operate in host-mode and device-mode.

Definition in file usb_core.c.

Function Documentation

usb_status_enum usb_core_init ( usb_core_handle_struct * pudev )

initializes the USB controller registers and prepares the core device mode or host mode operation

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
operation status

Definition at line 167 of file usb_core.c.

168 {
169 /* soft reset the core */
170 usb_core_reset(pudev);
171
172 /* active the transceiver and enable vbus sensing */
173 USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN;
174
175 /* set Tx FIFO empty level to half empty mode */
176 USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF;
177
178 #ifndef VBUS_SENSING_ENABLED
179 USB_GCCFG |= GCCFG_VBUSIG;
180 #endif /* VBUS_SENSING_ENABLED */
181
182 if(pudev->cfg.sof_output){
183 USB_GCCFG |= GCCFG_SOFOEN;
184 }
185
186 if (NULL != pudev->mdelay) {
187 pudev->mdelay(20U);
188 }
189
190
191 #ifdef USE_OTG_MODE
192 /* enable OTG features */
193 USB_GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP;
194 USB_OTG_EnableCommonInt(pudev);
195
196 #endif /* USE_OTG_MODE */
197
198 return USB_OK;
199 }
USB_GCCFG
#define USB_GCCFG
Definition: usb_regs.h:48
GAHBCS_TXFTH
#define GAHBCS_TXFTH
Definition: usb_regs.h:117
GCCFG_VBUSBCEN
#define GCCFG_VBUSBCEN
Definition: usb_regs.h:228
USB_GUSBCS
#define USB_GUSBCS
Definition: usb_regs.h:38
GCCFG_PWRON
#define GCCFG_PWRON
Definition: usb_regs.h:230
USB_OK
Definition: usb_core.h:29
TXFIFO_EMPTY_HALF
#define TXFIFO_EMPTY_HALF
Definition: usb_regs.h:504
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:217
GCCFG_SOFOEN
#define GCCFG_SOFOEN
Definition: usb_regs.h:227
usb_core_cfgs_struct::sof_output
uint8_t sof_output
Definition: usb_core.h:66
GCCFG_VBUSACEN
#define GCCFG_VBUSACEN
Definition: usb_regs.h:229
GCCFG_VBUSIG
#define GCCFG_VBUSIG
Definition: usb_regs.h:226
NULL
#define NULL
Definition: usb_defines.h:18
USB_GAHBCS
#define USB_GAHBCS
Definition: usb_regs.h:37
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:202
usb_status_enum usb_core_select | ( | usb_core_handle_struct * | pudev,
 |  | usb_core_id_enum | core_id
 | ) |  |

initialize core parameters

Parameters
[in] | pudev | pointer to usb device
[in] | core_id | USB core id
[out] | none
Return values
operation status

Definition at line 125 of file usb_core.c.

126 {
127 /* at startup the core is in FS mode */
128 pudev->cfg.core_speed = USB_CORE_SPEED_FULL;
129 pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE;
130
131 /* initialize the core parameters */
132 if (USB_FS_CORE_ID == core_id) {
133
134 pudev->cfg.core_id = USB_FS_CORE_ID;
135
136 /* set the host channel numbers */
137 pudev->cfg.host_channel_num = USBFS_MAX_HOST_CHANNELCOUNT;
138
139 /* set the device endpoint numbers */
140 pudev->cfg.dev_endp_num = USBFS_MAX_DEV_EPCOUNT;
141
142 /* fifo size is in terms of DWORD */
143 pudev->cfg.max_fifo_size = USBFS_MAX_FIFO_WORDLEN;
144
145 /* OTG_FS core use embedded physical layer */
146 pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY;
147
148 #ifdef USBFS_SOF_OUTPUT_ENABLED
149 pudev->cfg.sof_output = 1U;
150 #endif /* USBFS_SOF_OUTPUT_ENABLED */
151
152 #ifdef USBFS_LOW_PWR_MGMT_SUPPORT
153 pudev->cfg.low_power = 1U;
154 #endif /* USBFS_LOW_PWR_MGMT_SUPPORT */
155 }
156
157 return USB_OK;
158 }
USBFS_MAX_PACKET_SIZE
#define USBFS_MAX_PACKET_SIZE
Definition: usb_defines.h:24
usb_core_cfgs_struct::dev_endp_num
uint8_t dev_endp_num
Definition: usb_core.h:65
usb_core_cfgs_struct::max_packet_size
uint16_t max_packet_size
Definition: usb_core.h:68
USBFS_MAX_HOST_CHANNELCOUNT
#define USBFS_MAX_HOST_CHANNELCOUNT
Definition: usb_defines.h:25
USB_OK
Definition: usb_core.h:29
usb_core_cfgs_struct::phy_interface
uint8_t phy_interface
Definition: usb_core.h:63
USB_CORE_SPEED_FULL
#define USB_CORE_SPEED_FULL
Definition: usb_defines.h:22
usb_core_cfgs_struct::sof_output
uint8_t sof_output
Definition: usb_core.h:66
USB_CORE_EMBEDDED_PHY
#define USB_CORE_EMBEDDED_PHY
Definition: usb_defines.h:35
usb_core_cfgs_struct::core_speed
uint8_t core_speed
Definition: usb_core.h:62
usb_core_cfgs_struct::low_power
uint8_t low_power
Definition: usb_core.h:67
USB_FS_CORE_ID
Definition: usb_defines.h:89
USBFS_MAX_FIFO_WORDLEN
#define USBFS_MAX_FIFO_WORDLEN
Definition: usb_defines.h:27
USBFS_MAX_DEV_EPCOUNT
#define USBFS_MAX_DEV_EPCOUNT
Definition: usb_defines.h:26
usb_core_cfgs_struct::max_fifo_size
uint16_t max_fifo_size
Definition: usb_core.h:69
usb_core_cfgs_struct::core_id
uint8_t core_id
Definition: usb_core.h:61
usb_core_cfgs_struct::host_channel_num
uint8_t host_channel_num
Definition: usb_core.h:64
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:202
void* usb_fifo_read | ( | uint8_t * | dest,
 |  | uint16_t | len
 | ) |  |

read a packet from the Rx FIFO associated with the endpoint

Parameters
[in] | dest | pointer to destination buffer
[in] | len | packet length
[out] | none
Return values
void type pointer

Definition at line 102 of file usb_core.c.

103 {
104 uint32_t i = 0U;
105 uint32_t count32b = (len + 3U) / 4U;
106
107 __IO uint32_t *fifo = USB_FIFO(0U);
108
109 for (i = 0U; i < count32b; i++) {
110 *(__packed uint32_t *)dest = *fifo;
111
112 dest += 4U;
113 }
114
115 return ((void *)dest);
116 }
USB_FIFO
#define USB_FIFO(x)
Definition: usb_regs.h:93
usb_status_enum usb_fifo_write | ( | uint8_t * | src,
 |  | uint8_t | chep_num,
 |  | uint16_t | len
 | ) |  |

write a packet into the Tx FIFO associated with the endpoint

Parameters
[in] | src | pointer to source buffer
[in] | chep_num | channel or endpoint identifier which is in (0..3)
[in] | len | packet length
[out] | none
Return values
operation status

Definition at line 79 of file usb_core.c.

80 {
81 uint32_t count32b = 0U, i = 0U;
82 __IO uint32_t *fifo = USB_FIFO(chep_num);
83
84 count32b = (len + 3U) / 4U;
85
86 for (i = 0U; i < count32b; i++) {
87 *fifo = *((__packed uint32_t *)src);
88
89 src += 4U;
90 }
91
92 return USB_OK;
93 }
USB_OK
Definition: usb_core.h:29
USB_FIFO
#define USB_FIFO(x)
Definition: usb_regs.h:93
usb_status_enum usb_mode_set | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | mode
 | ) |  |

set operation mode (host or device)

Parameters
[in] | pudev | pointer to usb device
[in] mode operation mode which need to set
  • HOST_MODE
  • DEVICE_MODE
[out] | none
Return values
operation status

Definition at line 266 of file usb_core.c.

267 {
268 if (HOST_MODE == mode) {
269 USB_GUSBCS &= ~GUSBCS_FDM;
270 USB_GUSBCS |= GUSBCS_FHM;
271 } else if (DEVICE_MODE == mode) {
272 USB_GUSBCS &= ~GUSBCS_FHM;
273 USB_GUSBCS |= GUSBCS_FDM;
274 } else {
275 /* no operation */
276 }
277
278 if (NULL != pudev->mdelay) {
279 pudev->mdelay(50U);
280 }
281
282 return USB_OK;
283 }
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:48
USB_GUSBCS
#define USB_GUSBCS
Definition: usb_regs.h:38
GUSBCS_FDM
#define GUSBCS_FDM
Definition: usb_regs.h:123
USB_OK
Definition: usb_core.h:29
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:217
GUSBCS_FHM
#define GUSBCS_FHM
Definition: usb_regs.h:124
NULL
#define NULL
Definition: usb_defines.h:18
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:47
usb_status_enum usb_rxfifo_flush ( usb_core_handle_struct * pudev )

flush the entire Rx FIFO

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
operation status

Definition at line 236 of file usb_core.c.

237 {
238 uint32_t count = 0U;
239
240 USB_GRSTCTL = GRSTCTL_RXFF;
241
242 /* wait for Rx FIFO flush bit is set */
243 do {
244 if (++count > 200000U) {
245 break;
246 }
247 } while (USB_GRSTCTL & GRSTCTL_RXFF);
248
249 /* wait for 3 PHY clocks */
250 if (NULL != pudev->udelay) {
251 pudev->udelay(3U);
252 }
253
254 return USB_OK;
255 }
usb_core_handle_struct::udelay
void(* udelay)(const uint32_t usec)
Definition: usb_core.h:216
USB_OK
Definition: usb_core.h:29
GRSTCTL_RXFF
#define GRSTCTL_RXFF
Definition: usb_regs.h:138
NULL
#define NULL
Definition: usb_defines.h:18
USB_GRSTCTL
#define USB_GRSTCTL
Definition: usb_regs.h:39
usb_status_enum usb_txfifo_flush | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | fifo_num
 | ) |  |

flush a Tx FIFO or all Tx FIFOs

Parameters
[in] | pudev | pointer to usb device
[in] | fifo_num | FIFO number which is in (0..3)
[out] | none
Return values
operation status

Definition at line 208 of file usb_core.c.

209 {
210 uint32_t count = 0U;
211
212 USB_GRSTCTL &= ~GRSTCTL_TXFNUM;
213 USB_GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF;
214
215 /* wait for Tx FIFO flush bit is set */
216 do {
217 if (++count > 200000U) {
218 break;
219 }
220 } while (USB_GRSTCTL & GRSTCTL_TXFF);
221
222 /* wait for 3 PHY clocks */
223 if (NULL != pudev->udelay) {
224 pudev->udelay(3U);
225 }
226
227 return USB_OK;
228 }
GRSTCTL_TXFNUM
#define GRSTCTL_TXFNUM
Definition: usb_regs.h:136
usb_core_handle_struct::udelay
void(* udelay)(const uint32_t usec)
Definition: usb_core.h:216
USB_OK
Definition: usb_core.h:29
GRSTCTL_TXFF
#define GRSTCTL_TXFF
Definition: usb_regs.h:137
NULL
#define NULL
Definition: usb_defines.h:18
USB_GRSTCTL
#define USB_GRSTCTL
Definition: usb_regs.h:39
Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbd_core.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
Functions
usbd_core.c File Reference

USB device mode core driver. More...

#include "usbd_core.h"
#include "usbd_std.h"

Go to the source code of this file.

Functions

void | usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initailizes the USB device-mode handler stack More...
void | usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc)
endpoint initialization More...
void | usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr)
endpoint deinitialize More...
void | usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data More...
void | usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
endpoint prepare to transmit data More...
usbd_status_enum | usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
transmit data on the control channel More...
usbd_status_enum | usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
receive data on the control channel More...
usbd_status_enum | usbd_ctlstatus_tx (usb_core_handle_struct *pudev)
transmit status on the control channel More...
usbd_status_enum | usbd_ctlstatus_rx (usb_core_handle_struct *pudev)
receive status on the control channel More...
void | usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status More...
void | usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status More...
void | usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr)
flushes the FIFOs More...
uint16_t | usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num)
get the received data length More...

Detailed Description

USB device mode core driver.

Definition in file usbd_core.c.

Function Documentation

usbd_status_enum usbd_ctlrx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | pbuf,
 |  | uint16_t | len
 | ) |  |

receive data on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[in] | pbuf | pointer to buffer
[in] | len | buffer length
[out] | none
Return values
usb device operation status

Definition at line 333 of file usbd_core.c.

334 {
335 pudev->dev.sum_len = len;
336 pudev->dev.remain_len = len;
337 pudev->dev.ctl_status = USB_CTRL_DATA_OUT;
338
339 usbd_ep_rx (pudev, 0U, pbuf, len);
340
341 return USBD_OK;
342 }
USBD_OK
Definition: usb_core.h:74
USB_CTRL_DATA_OUT
Definition: usb_core.h:85
usbd_ep_rx
void usbd_ep_rx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:161
usbd_status_enum usbd_ctlstatus_rx ( usb_core_handle_struct * pudev )

receive status on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
usb device operation status

Definition at line 367 of file usbd_core.c.

368 {
369 pudev->dev.ctl_status = USB_CTRL_STATUS_OUT;
370
371 usbd_ep_rx (pudev, 0U, NULL, 0U);
372
373 usb_ep0_startout(pudev);
374
375 return USBD_OK;
376 }
USB_CTRL_STATUS_OUT
Definition: usb_core.h:87
USBD_OK
Definition: usb_core.h:74
NULL
#define NULL
Definition: usb_defines.h:18
usbd_ep_rx
void usbd_ep_rx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:161
usbd_status_enum usbd_ctlstatus_tx ( usb_core_handle_struct * pudev )

transmit status on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
usb device operation status

Definition at line 350 of file usbd_core.c.

351 {
352 pudev->dev.ctl_status = USB_CTRL_STATUS_IN;
353
354 usbd_ep_tx (pudev, 0U, NULL, 0U);
355
356 usb_ep0_startout(pudev);
357
358 return USBD_OK;
359 }
USBD_OK
Definition: usb_core.h:74
USB_CTRL_STATUS_IN
Definition: usb_core.h:86
NULL
#define NULL
Definition: usb_defines.h:18
usbd_ep_tx
void usbd_ep_tx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:230
usbd_status_enum usbd_ctltx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | pbuf,
 |  | uint16_t | len
 | ) |  |

transmit data on the control channel

Parameters
[in] | pudev | pointer to usb device instance
[in] | pbuf | pointer to buffer
[in] | len | buffer length
[out] | none
Return values
usb device operation status

Definition at line 312 of file usbd_core.c.

313 {
314 usbd_status_enum ret = USBD_OK;
315
316 pudev->dev.sum_len = len;
317 pudev->dev.remain_len = len;
318 pudev->dev.ctl_status = USB_CTRL_DATA_IN;
319
320 usbd_ep_tx (pudev, 0U, pbuf, (uint32_t)len);
321
322 return ret;
323 }
USBD_OK
Definition: usb_core.h:74
USB_CTRL_DATA_IN
Definition: usb_core.h:84
usbd_status_enum
usbd_status_enum
Definition: usb_core.h:72
usbd_ep_tx
void usbd_ep_tx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:230
void usbd_ep_clear_stall | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

clear endpoint stalled status

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 415 of file usbd_core.c.

416 {
417 usb_ep_struct *ep;
418 uint8_t ep_num = ep_addr & 0x7FU;
419 __IO uint32_t devepctl = 0U;
420
421 if(ep_addr >> 7){
422 ep = &pudev->dev.in_ep[ep_num];
423
424 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
425
426 /* clear the IN endpoint stall bits */
427 devepctl &= ~DEPCTL_STALL;
428
429 if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) {
430 devepctl |= DEPCTL_SEVNFRM;
431 }
432
433 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
434 } else {
435 ep = &pudev->dev.out_ep[ep_num];
436
437 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
438
439 /* clear the OUT endpoint stall bits */
440 devepctl &= ~DEPCTL_STALL;
441
442 if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) {
443 devepctl |= DEPCTL_SEVNFRM;
444 }
445
446 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
447 }
448 }
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:54
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:101
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:83
usb_ep_struct
Definition: usb_core.h:99
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:84
DEPCTL_STALL
#define DEPCTL_STALL
Definition: usb_regs.h:440
DEPCTL_SEVNFRM
#define DEPCTL_SEVNFRM
Definition: usb_regs.h:435
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:53
void usbd_ep_deinit | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

endpoint deinitialize

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 133 of file usbd_core.c.

134 {
135 uint32_t devepinten = 0U;
136 uint8_t ep_num = ep_addr & 0x7FU;
137
138 if (ep_addr >> 7) {
139 devepinten |= 1U << ep_num;
140
141 USB_DIEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT;
142 } else {
143 devepinten |= (1U << ep_num) << 16U;
144
145 USB_DOEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT;
146 }
147
148 /* disable the interrupts for this endpoint */
149 USB_DAEPINTEN &= ~devepinten;
150 }
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:71
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:83
DEPCTL_EPACT
#define DEPCTL_EPACT
Definition: usb_regs.h:446
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:84
void usbd_ep_fifo_flush | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

flushes the FIFOs

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 457 of file usbd_core.c.

458 {
459 if (ep_addr >> 7) {
460 usb_txfifo_flush(pudev, ep_addr & 0x7FU);
461 } else {
462 usb_rxfifo_flush(pudev);
463 }
464 }
usb_txfifo_flush
usb_status_enum usb_txfifo_flush(usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs
Definition: usb_core.c:208
usb_rxfifo_flush
usb_status_enum usb_rxfifo_flush(usb_core_handle_struct *pudev)
flush the entire Rx FIFO
Definition: usb_core.c:236
void usbd_ep_init | ( | usb_core_handle_struct * | pudev,
 |  | const usb_descriptor_endpoint_struct * | ep_desc
 | ) |  |

endpoint initialization

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_desc | pointer to usb endpoint descriptor
[out] | none
Return values
none

Definition at line 66 of file usbd_core.c.

67 {
68 usb_ep_struct *ep;
69 usb_dir_enum ep_dir;
70
71 uint32_t devepinten = 0U;
72 uint32_t devepctl = 0U;
73
74 uint8_t ep_num = ep_desc->bEndpointAddress & 0x7FU;
75 uint8_t ep_type = ep_desc->bmAttributes & USB_EPTYPE_MASK;
76 uint16_t ep_mps = ep_desc->wMaxPacketSize;
77
78 if (ep_desc->bEndpointAddress >> 7) {
79 ep = &pudev->dev.in_ep[ep_num];
80
81 devepinten |= 1U << ep_num;
82 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
83
84 ep_dir = USB_TX;
85 } else {
86 ep = &pudev->dev.out_ep[ep_num];
87
88 devepinten |= (1U << ep_num) << 16;
89 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
90
91 ep_dir = USB_RX;
92 }
93
94 /* if the endpoint is not active, need change the endpoint control register */
95 if (!(devepctl & DEPCTL_EPACT)) {
96 devepctl &= ~DEPCTL_MPL;
97 devepctl |= ep_mps;
98
99 devepctl &= ~DEPCTL_EPTYPE;
100 devepctl |= (uint32_t)ep_type << 18;
101
102 if (USB_TX == ep_dir) {
103 devepctl &= ~DIEPCTL_TXFNUM;
104 devepctl |= (uint32_t)ep_num << 22;
105 }
106
107 devepctl |= DEPCTL_SD0PID;
108 devepctl |= DEPCTL_EPACT;
109 }
110
111 if (USB_TX == ep_dir) {
112 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
113 } else if (USB_RX == ep_dir) {
114 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
115 } else {
116 /* no operation */
117 }
118
119 ep->endp_mps = ep_mps;
120 ep->endp_type = ep_type;
121
122 /* enable the interrupts for this endpoint */
123 USB_DAEPINTEN |= devepinten;
124 }
usb_descriptor_endpoint_struct::bmAttributes
uint8_t bmAttributes
Definition: usb_std.h:175
USB_TX
Definition: usb_core.h:95
DEPCTL_EPTYPE
#define DEPCTL_EPTYPE
Definition: usb_regs.h:442
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:71
usb_descriptor_endpoint_struct::bEndpointAddress
uint8_t bEndpointAddress
Definition: usb_std.h:174
USB_EPTYPE_MASK
#define USB_EPTYPE_MASK
Definition: usb_defines.h:55
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:101
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:103
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:83
DEPCTL_EPACT
#define DEPCTL_EPACT
Definition: usb_regs.h:446
USB_RX
Definition: usb_core.h:94
usb_ep_struct
Definition: usb_core.h:99
usb_dir_enum
usb_dir_enum
Definition: usb_core.h:92
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:84
DEPCTL_MPL
#define DEPCTL_MPL
Definition: usb_regs.h:447
usb_descriptor_endpoint_struct::wMaxPacketSize
uint16_t wMaxPacketSize
Definition: usb_std.h:176
DIEPCTL_TXFNUM
#define DIEPCTL_TXFNUM
Definition: usb_regs.h:439
DEPCTL_SD0PID
#define DEPCTL_SD0PID
Definition: usb_regs.h:436
void usbd_ep_rx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pbuf,
 |  | uint16_t | buf_len
 | ) |  |

endpoint prepare to receive data

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[in] | pbuf | pointer to buffer
[in] | buf_len | buffer length
[out] | none
Return values
none

Definition at line 161 of file usbd_core.c.

162 {
163 usb_ep_struct *ep;
164 uint8_t ep_num = ep_addr & 0x7FU;
165 uint32_t devepctl = 0U, devepxlen = 0U;
166
167 ep = &pudev->dev.out_ep[ep_num];
168
169 /* setup and start the Xfer */
170 ep->xfer_buff = pbuf;
171 ep->xfer_len = buf_len;
172 ep->xfer_count = 0U;
173
174 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
175 devepxlen = USB_DOEPxLEN((uint16_t)ep_num);
176
177 devepxlen &= ~DEPLEN_TLEN;
178 devepxlen &= ~DEPLEN_PCNT;
179
180 /* zero length packet */
181 if (0U == ep->xfer_len) {
182 /* set the transfer length to max packet size */
183 devepxlen |= ep->endp_mps;
184
185 /* set the transfer packet count to 1 */
186 devepxlen |= 1U << 19U;
187 } else {
188
189 if (0U == ep_num) {
190 /* set the transfer length to max packet size */
191 devepxlen |= ep->endp_mps;
192
193 /* set the transfer packet count to 1 */
194 devepxlen |= 1U << 19U;
195 } else {
196 /* configure the transfer size and packet count as follows:
197 * pktcnt = N
198 * xfersize = N * maxpacket
199 */
200 devepxlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U;
201 devepxlen |= ((devepxlen & DEPLEN_PCNT) >> 19U) * ep->endp_mps;
202 }
203 }
204
205 USB_DOEPxLEN((uint16_t)ep_num) = devepxlen;
206
207 if (USB_EPTYPE_ISOC == ep->endp_type) {
208 if (ep->endp_frame) {
209 devepctl |= DEPCTL_SODDFRM;
210 } else {
211 devepctl |= DEPCTL_SEVNFRM;
212 }
213 }
214
215 /* enable the endpoint and clear the NAK */
216 devepctl |= DEPCTL_EPEN | DEPCTL_CNAK;
217
218 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
219 }
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:52
usb_ep_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:108
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:431
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:101
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:103
usb_ep_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:107
usb_ep_struct::endp_frame
uint8_t endp_frame
Definition: usb_core.h:102
DEPLEN_TLEN
#define DEPLEN_TLEN
Definition: usb_regs.h:480
DEPLEN_PCNT
#define DEPLEN_PCNT
Definition: usb_regs.h:479
usb_ep_struct
Definition: usb_core.h:99
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:84
USB_DOEPxLEN
#define USB_DOEPxLEN(x)
Definition: usb_regs.h:88
DEPCTL_CNAK
#define DEPCTL_CNAK
Definition: usb_regs.h:438
DEPCTL_SEVNFRM
#define DEPCTL_SEVNFRM
Definition: usb_regs.h:435
DEPCTL_SODDFRM
#define DEPCTL_SODDFRM
Definition: usb_regs.h:433
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:106
void usbd_ep_stall | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

set an endpoint to STALL status

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[out] | none
Return values
none

Definition at line 385 of file usbd_core.c.

386 {
387 uint8_t ep_num = ep_addr & 0x7FU;
388 __IO uint32_t devepctl = 0U;
389
390 if (ep_addr >> 7U) {
391 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
392
393 /* set the endpoint disable bit */
394 if (devepctl & DEPCTL_EPEN) {
395 devepctl |= DEPCTL_EPD;
396 }
397
398 /* set the endpoint stall bit */
399 devepctl |= DEPCTL_STALL;
400
401 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
402 } else {
403 /* set the endpoint stall bit */
404 USB_DOEPxCTL((uint16_t)ep_num) |= DEPCTL_STALL;
405 }
406 }
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:431
DEPCTL_EPD
#define DEPCTL_EPD
Definition: usb_regs.h:432
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:83
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:84
DEPCTL_STALL
#define DEPCTL_STALL
Definition: usb_regs.h:440
void usbd_ep_tx | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pbuf,
 |  | uint32_t | buf_len
 | ) |  |

endpoint prepare to transmit data

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_addr | endpoint address
[in] | pbuf | pointer to buffer
[in] | len | buffer length
[out] | none
Return values
none

Definition at line 230 of file usbd_core.c.

231 {
232 usb_ep_struct *ep;
233 uint8_t ep_num = ep_addr & 0x7FU;
234 __IO uint32_t devepctl = 0U;
235 __IO uint32_t deveplen = 0U;
236
237 ep = &pudev->dev.in_ep[ep_num];
238
239 /* setup and start the transfer */
240 ep->xfer_buff = pbuf;
241 ep->xfer_len = buf_len;
242 ep->xfer_count = 0U;
243
244 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
245 deveplen = USB_DIEPxLEN((uint16_t)ep_num);
246
247 /* clear transfer length to 0 */
248 deveplen &= ~DEPLEN_TLEN;
249
250 /* clear transfer packet to 0 */
251 deveplen &= ~DEPLEN_PCNT;
252
253 /* zero length packet */
254 if (0U == ep->xfer_len) {
255 /* set transfer packet count to 1 */
256 deveplen |= 1U << 19U;
257 } else {
258 if (0U == ep_num) {
259 if (ep->xfer_len > ep->endp_mps) {
260 ep->xfer_len = ep->endp_mps;
261 }
262
263 deveplen |= 1U << 19U;
264 } else {
265 deveplen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U;
266 }
267
268 /* configure the transfer size and packet count as follows:
269 * xfersize = N * maxpacket + short_packet
270 * pktcnt = N + (short_packet exist ? 1 : 0)
271 */
272 deveplen |= ep->xfer_len;
273
274 if (USB_EPTYPE_ISOC == ep->endp_type) {
275 deveplen |= DIEPLEN_MCNT & (1U << 29U);
276 }
277 }
278
279 USB_DIEPxLEN((uint16_t)ep_num) = deveplen;
280
281 if (USB_EPTYPE_ISOC == ep->endp_type) {
282 if (0U == (((USB_DSTAT & DSTAT_FNRSOF) >> 8U) & 0x1U)) {
283 devepctl |= DEPCTL_SODDFRM;
284 } else {
285 devepctl |= DEPCTL_SEVNFRM;
286 }
287 }
288
289 /* enable the endpoint and clear the NAK */
290 devepctl |= DEPCTL_EPEN | DEPCTL_CNAK;
291
292 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
293
294 if (USB_EPTYPE_ISOC != ep->endp_type) {
295 /* enable the Tx FIFO empty interrupt for this endpoint */
296 if (ep->xfer_len > 0U) {
297 USB_DIEPFEINTEN |= 1U << ep_num;
298 }
299 } else {
300 usb_fifo_write(ep->xfer_buff, ep_num, (uint16_t)ep->xfer_len);
301 }
302 }
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:52
usb_ep_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:108
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:431
usb_fifo_write
usb_status_enum usb_fifo_write(uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint
Definition: usb_core.c:79
DIEPLEN_MCNT
#define DIEPLEN_MCNT
Definition: usb_regs.h:478
USB_DIEPxLEN
#define USB_DIEPxLEN(x)
Definition: usb_regs.h:87
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:101
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:103
usb_ep_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:107
DEPLEN_TLEN
#define DEPLEN_TLEN
Definition: usb_regs.h:480
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:83
DEPLEN_PCNT
#define DEPLEN_PCNT
Definition: usb_regs.h:479
usb_ep_struct
Definition: usb_core.h:99
USB_DSTAT
#define USB_DSTAT
Definition: usb_regs.h:67
DSTAT_FNRSOF
#define DSTAT_FNRSOF
Definition: usb_regs.h:355
USB_DIEPFEINTEN
#define USB_DIEPFEINTEN
Definition: usb_regs.h:74
DEPCTL_CNAK
#define DEPCTL_CNAK
Definition: usb_regs.h:438
DEPCTL_SEVNFRM
#define DEPCTL_SEVNFRM
Definition: usb_regs.h:435
DEPCTL_SODDFRM
#define DEPCTL_SODDFRM
Definition: usb_regs.h:433
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:106
void usbd_init | ( | usb_core_handle_struct * | pudev,
 |  | usb_core_id_enum | core_id
 | ) |  |

initailizes the USB device-mode handler stack

Parameters
[in] | pudev | pointer to usb device instance
[in] | core_id | USB core ID
[out] | none
Return values
none

Definition at line 22 of file usbd_core.c.

23 {
24 /* select USB core */
25 usb_core_select (pudev, core_id);
26
27 pudev->dev.status = USB_STATUS_DEFAULT;
28
29 /* disable USB global interrupt */
30 USB_GLOBAL_INT_DISABLE();
31
32 /* init the core (common init.) */
33 usb_core_init(pudev);
34
35 /* force device mode*/
36 usb_mode_set(pudev, DEVICE_MODE);
37
38 /* set device disconnect */
39 USB_SOFT_DISCONNECT_ENABLE();
40
41 if ((void *)0 != pudev->mdelay) {
42 pudev->mdelay(3U);
43 }
44
45 /* init device */
46 usb_devcore_init(pudev);
47
48 /* set device Connect */
49 USB_SOFT_DISCONNECT_DISABLE();
50
51 if ((void *)0 != pudev->mdelay) {
52 pudev->mdelay(3U);
53 }
54
55 /* enable USB global interrupt */
56 USB_GLOBAL_INT_ENABLE();
57 }
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:125
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:266
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:217
USB_SOFT_DISCONNECT_DISABLE
#define USB_SOFT_DISCONNECT_DISABLE()
Definition: usb_regs.h:602
USB_GLOBAL_INT_DISABLE
#define USB_GLOBAL_INT_DISABLE()
Definition: usb_regs.h:545
USB_GLOBAL_INT_ENABLE
#define USB_GLOBAL_INT_ENABLE()
Definition: usb_regs.h:542
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:167
USB_SOFT_DISCONNECT_ENABLE
#define USB_SOFT_DISCONNECT_ENABLE()
Definition: usb_regs.h:599
USB_STATUS_DEFAULT
#define USB_STATUS_DEFAULT
Definition: usbd_core.h:20
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:47
uint16_t usbd_rxcount_get | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_num
 | ) |  |

get the received data length

Parameters
[in] | pudev | pointer to usb device instance
[in] | ep_num | endpoint identifier which is in (0..3)
[out] | none
Return values
received data length

Definition at line 473 of file usbd_core.c.

474 {
475 return (uint16_t)pudev->dev.out_ep[ep_num].xfer_count;
476 }
Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbd_int.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
Functions
usbd_int.c File Reference

USB device mode interrupt routines. More...

#include "usbd_int.h"
#include "usbd_std.h"

Go to the source code of this file.

Functions

uint32_t usbd_isr (usb_core_handle_struct *pudev)
USB device-mode interrupts global service routine handler. More...

Detailed Description

USB device mode interrupt routines.

Definition in file usbd_int.c.

Function Documentation

uint32_t usbd_isr ( usb_core_handle_struct * pudev )

USB device-mode interrupts global service routine handler.

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
operation status

Definition at line 57 of file usbd_int.c.

58 {
59 uint32_t retval = 0U;
60 uint32_t int_status = 0U, gintf = USB_GINTF, ginten = USB_GINTEN;
61
62 /* ensure the core is in device mode */
63 if (DEVICE_MODE == USB_CURRENT_MODE_GET()) {
64 int_status = gintf & ginten;
65
66 /* there are no interrupts, avoid spurious interrupt */
67 if (!int_status) {
68 return 0U;
69 }
70
71 /* OUT endpoints interrupts */
72 if (int_status & GINTF_OEPIF) {
73 retval |= usbd_intf_outep(pudev);
74 }
75
76 /* IN endpoints interrupts */
77 if (int_status & GINTF_IEPIF) {
78 retval |= usbd_intf_inep(pudev);
79 }
80
81 /* mode mismatch interrupt */
82 if (int_status & GINTF_MFIF) {
83 /* clear interrupt */
84 USB_GINTF = GINTF_MFIF;
85 }
86
87 /* early suspend interrupt */
88 if (int_status & GINTF_ESP) {
89 retval |= usbd_intf_earlysuspend(pudev);
90 }
91
92 /* suspend interrupt */
93 if (int_status & GINTF_SP) {
94 retval |= usbd_intf_suspend(pudev);
95 }
96
97 /* wakeup interrupt */
98 if (int_status & GINTF_WKUPIF) {
99 retval |= usbd_intf_resume(pudev);
100 }
101
102 /* start of frame interrupt */
103 if (int_status & GINTF_SOF) {
104 retval |= usbd_intf_sof(pudev);
105 }
106
107 /* reveive fifo not empty interrupt */
108 if (int_status & GINTF_RXFNEIF) {
109 retval |= usbd_intf_rxfifo(pudev);
110 }
111
112 /* USB reset interrupt */
113 if (int_status & GINTF_RST) {
114 retval |= usbd_intf_reset(pudev);
115 }
116
117 /* enumeration has been finished interrupt */
118 if (int_status & GINTF_ENUMF) {
119 retval |= usbd_intf_enumfinish(pudev);
120 }
121
122 /* incomplete synchronization in transfer interrupt*/
123 if (int_status & GINTF_ISOINCIF) {
124 retval |= usbd_intf_isoinincomplete(pudev);
125 }
126
127 /* incomplete synchronization out transfer interrupt*/
128 if (int_status & GINTF_ISOONCIF) {
129 retval |= usbd_intf_isooutincomplete(pudev);
130 }
131
132 #ifdef VBUS_SENSING_ENABLED
133
134 /* session request interrupt */
135 if (int_status & GINTF_SESIF) {
136 retval |= usbd_intf_sessionrequest(pudev);
137 }
138
139 /* OTG mode interrupt */
140 if (int_status & GINTF_OTGIF) {
141 retval |= usbd_intf_otg(pudev);
142 }
143 #endif /* VBUS_SENSING_ENABLED */
144 }
145
146 return retval;
147 }
GINTF_IEPIF
#define GINTF_IEPIF
Definition: usb_regs.h:155
GINTF_RXFNEIF
#define GINTF_RXFNEIF
Definition: usb_regs.h:165
GINTF_ISOINCIF
#define GINTF_ISOINCIF
Definition: usb_regs.h:153
USB_GINTEN
#define USB_GINTEN
Definition: usb_regs.h:41
GINTF_SESIF
#define GINTF_SESIF
Definition: usb_regs.h:145
USB_GINTF
#define USB_GINTF
Definition: usb_regs.h:40
USB_CURRENT_MODE_GET
#define USB_CURRENT_MODE_GET()
Definition: usb_regs.h:548
GINTF_OEPIF
#define GINTF_OEPIF
Definition: usb_regs.h:154
GINTF_ESP
#define GINTF_ESP
Definition: usb_regs.h:161
GINTF_OTGIF
#define GINTF_OTGIF
Definition: usb_regs.h:167
GINTF_SP
#define GINTF_SP
Definition: usb_regs.h:160
GINTF_WKUPIF
#define GINTF_WKUPIF
Definition: usb_regs.h:144
GINTF_RST
#define GINTF_RST
Definition: usb_regs.h:159
GINTF_ISOONCIF
#define GINTF_ISOONCIF
Definition: usb_regs.h:152
GINTF_ENUMF
#define GINTF_ENUMF
Definition: usb_regs.h:158
GINTF_SOF
#define GINTF_SOF
Definition: usb_regs.h:166
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:47
GINTF_MFIF
#define GINTF_MFIF
Definition: usb_regs.h:168
Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbd_std.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
Functions
usbd_std.c File Reference

USB 2.0 standard handler driver. More...

#include "usbd_std.h"
#include "usb_core.h"

Go to the source code of this file.

Functions

usbd_status_enum | usbd_setup_transaction (usb_core_handle_struct *pudev)
USB setup stage processing. More...
usbd_status_enum | usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num)
data out stage processing More...
usbd_status_enum | usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num)
data in stage processing More...
void | usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB low level error event More...

Detailed Description

USB 2.0 standard handler driver.

Definition in file usbd_std.c.

Function Documentation

void usbd_enum_error | ( | usb_core_handle_struct * | pudev,
 |  | usb_device_req_struct * | req
 | ) |  |

handle USB low level error event

Parameters
[in] | pudev | pointer to USB device instance
[in] | req | pointer to USB device request
[out] | none
Return values
none

Definition at line 688 of file usbd_std.c.

689 {
690 usbd_ep_stall(pudev, 0x80U);
691 usbd_ep_stall(pudev, 0x00U);
692 usb_ep0_startout(pudev);
693 }
usbd_ep_stall
void usbd_ep_stall(usb_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:385
usbd_status_enum usbd_in_transaction | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | endp_num
 | ) |  |

data in stage processing

Parameters
[in] | pudev | pointer to USB device instance
[in] | ep_id | endpoint identifier(0..7)
[out] | none
Return values
USB device operation status

Definition at line 142 of file usbd_std.c.

143 {
144 usb_ep_struct *ep;
145
146 if (0U == endp_num) {
147 ep = &pudev->dev.in_ep[0];
148
149 if (USB_CTRL_DATA_IN == pudev->dev.ctl_status) {
150 if (pudev->dev.remain_len > ep->endp_mps) {
151 pudev->dev.remain_len -= ep->endp_mps;
152
153 usbd_ep_tx (pudev, 0U, ep->xfer_buff, pudev->dev.remain_len);
154
155 usbd_ep_rx (pudev, 0U, NULL, 0U);
156 } else {
157 /* last packet is MPS multiple, so send ZLP packet */
158 if ((pudev->dev.sum_len % ep->endp_mps == 0U) &&
159 (pudev->dev.sum_len >= ep->endp_mps) &&
160 (pudev->dev.sum_len < pudev->dev.ctl_len)) {
161 usbd_ep_tx (pudev, 0U, NULL, 0U);
162 pudev->dev.ctl_len = 0U;
163
164 usbd_ep_rx (pudev, 0U, NULL, 0U);
165 } else {
166 if (USB_STATUS_CONFIGURED == pudev->dev.status) {
167 pudev->dev.class_data_handler(pudev, USB_TX, 0U);
168 }
169
170 usbd_ctlstatus_rx(pudev);
171 }
172 }
173 }
174 } else if (USB_STATUS_CONFIGURED == pudev->dev.status) {
175 pudev->dev.class_data_handler(pudev, USB_TX, endp_num);
176 } else {
177 /* no operation */
178 }
179
180 return USBD_OK;
181 }
USB_TX
Definition: usb_core.h:95
USBD_OK
Definition: usb_core.h:74
USB_STATUS_CONFIGURED
#define USB_STATUS_CONFIGURED
Definition: usbd_core.h:22
usbd_ctlstatus_rx
usbd_status_enum usbd_ctlstatus_rx(usb_core_handle_struct *pudev)
receive status on the control channel
Definition: usbd_core.c:367
USB_CTRL_DATA_IN
Definition: usb_core.h:84
usbd_ep_tx
void usbd_ep_tx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:230
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:103
usbd_ep_rx
void usbd_ep_rx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:161
usb_ep_struct
Definition: usb_core.h:99
NULL
#define NULL
Definition: usb_defines.h:18
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:106
usbd_status_enum usbd_out_transaction | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | endp_num
 | ) |  |

data out stage processing

Parameters
[in] | pudev | pointer to USB device instance
[in] | ep_id | endpoint identifier(0..7)
[out] | none
Return values
USB device operation status

Definition at line 103 of file usbd_std.c.

104 {
105 usb_ep_struct *ep;
106
107 if (0U == endp_num) {
108 ep = &pudev->dev.out_ep[0];
109
110 if (USB_CTRL_DATA_OUT == pudev->dev.ctl_status) {
111 if (pudev->dev.remain_len > ep->endp_mps) {
112 pudev->dev.remain_len -= ep->endp_mps;
113
114 usbd_ep_rx (pudev,
115 0U,
116 ep->xfer_buff,
117 (uint16_t)USB_MIN(pudev->dev.remain_len, ep->endp_mps));
118 } else {
119 if (USB_STATUS_CONFIGURED == pudev->dev.status) {
120 pudev->dev.class_data_handler(pudev, USB_RX, 0U);
121 }
122
123 usbd_ctlstatus_tx(pudev);
124 }
125 }
126 } else if (USB_STATUS_CONFIGURED == pudev->dev.status) {
127 pudev->dev.class_data_handler(pudev, USB_RX, endp_num);
128 } else {
129 /* no operation */
130 }
131
132 return USBD_OK;
133 }
USBD_OK
Definition: usb_core.h:74
USB_STATUS_CONFIGURED
#define USB_STATUS_CONFIGURED
Definition: usbd_core.h:22
USB_CTRL_DATA_OUT
Definition: usb_core.h:85
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:103
USB_RX
Definition: usb_core.h:94
usbd_ep_rx
void usbd_ep_rx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:161
usb_ep_struct
Definition: usb_core.h:99
usbd_ctlstatus_tx
usbd_status_enum usbd_ctlstatus_tx(usb_core_handle_struct *pudev)
transmit status on the control channel
Definition: usbd_core.c:350
USB_MIN
#define USB_MIN(a, b)
Definition: usbd_std.h:42
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:106
usbd_status_enum usbd_setup_transaction ( usb_core_handle_struct * pudev )

USB setup stage processing.

Parameters
[in] | pudev | pointer to USB device instance
[out] | none
Return values
USB device operation status

Definition at line 69 of file usbd_std.c.

70 {
71 usb_device_req_struct req;
72
73 usbd_setup_request_parse(pudev, &req);
74
75 switch (req.bmRequestType & USB_REQ_MASK) {
76 /* standard device request */
77 case USB_STANDARD_REQ:
78 usbd_standard_request(pudev, &req);
79 break;
80 /* device class request */
81 case USB_CLASS_REQ:
82 usbd_device_class_request(pudev, &req);
83 break;
84 /* vendor defined request */
85 case USB_VENDOR_REQ:
86 usbd_vendor_request(pudev, &req);
87 break;
88 default:
89 usbd_ep_stall(pudev, req.bmRequestType & 0x80U);
90 break;
91 }
92
93 return USBD_OK;
94 }
USB_CLASS_REQ
#define USB_CLASS_REQ
Definition: usb_std.h:31
USBD_OK
Definition: usb_core.h:74
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usb_std.h:30
usb_device_req_struct
Definition: usb_core.h:114
usb_device_req_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_core.h:116
usbd_ep_stall
void usbd_ep_stall(usb_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:385
USB_REQ_MASK
#define USB_REQ_MASK
Definition: usb_std.h:33
USB_VENDOR_REQ
#define USB_VENDOR_REQ
Definition: usb_std.h:32
Generated on Tue Jun 27 2017 14:36:14 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbh_core.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
Functions | Variables
usbh_core.c File Reference

this file implements the functions for the core state machine process More...

#include "usbh_hcs.h"
#include "usbh_core.h"
#include "usbh_int.h"
#include "stdio.h"
#include "usbh_std.h"
#include "usbh_ctrl.h"
#include "usb_core.h"

Go to the source code of this file.

Functions

uint8_t | usbh_sof (usb_core_handle_struct *pudev)
usb sof callback function from the interrupt. More...
uint8_t | usbh_connected (usb_core_handle_struct *pudev)
usb connect callback function from the interrupt. More...
uint8_t | usbh_disconnected (usb_core_handle_struct *pudev)
usb disconnect callback function from the interrupt. More...
usbh_status_enum | host_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of HOST state More...
uint32_t | hcd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize the host portion of the driver. More...
uint32_t | hcd_is_device_connected (usb_core_handle_struct *pudev)
check if the device is connected. More...
urb_state_enum | hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate More...
uint32_t | hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate More...
usbh_status_enum | usbh_deinit (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
de-initialize host More...
void | scd_init (usbh_state_handle_struct *pustate)
state core driver init More...
void | scd_table_regist (usbh_state_handle_struct *pustate, state_table_struct *pstate_table, uint8_t table_id, uint8_t current_table_size)
state core driver table regist More...
void | scd_begin (usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin More...
void | scd_state_move (usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state More...
usbh_status_enum | scd_event_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate, uint8_t event, uint8_t state)
state core driver event handle More...
void | scd_table_push (usbh_state_handle_struct *pustate)
state core driver table push More...
void | scd_table_pop (usbh_state_handle_struct *pustate)
state core driver table pop More...
usbh_status_enum | only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move More...
usbh_status_enum | goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state More...

Variables

class_polling_fun_cb_struct | class_polling_cb
usbh_hcd_int_cb_struct usbh_hcd_int_cb
usbh_hcd_int_cb_struct * usbh_hcd_int_fops = &usbh_hcd_int_cb
usbh_state_handle_struct usbh_state_core
void(* | host_state_handle [])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
state_table_struct host_handle_table [HOST_HANDLE_TABLE_SIZE]

Detailed Description

this file implements the functions for the core state machine process

Definition in file usbh_core.c.

Function Documentation

usbh_status_enum goto_up_state_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the function to the up state

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 705 of file usbh_core.c.

706 {
707 scd_table_pop((usbh_state_handle_struct *)pustate);
708
709 return USBH_OK;
710 }
usbh_state_handle_struct
Definition: usbh_core.h:227
scd_table_pop
void scd_table_pop(usbh_state_handle_struct *pustate)
state core driver table pop
Definition: usbh_core.c:644
USBH_OK
Definition: usbh_core.h:108
uint32_t hcd_init | ( | usb_core_handle_struct * | pudev,
 |  | usb_core_id_enum | core_id
 | ) |  |

initialize the host portion of the driver.

Parameters
[in] | pudev | pointer to usb device
[in] | core_id | usb otg core identifier(high-speed or full-speed)
[out] | none
Return values
operation status

Definition at line 385 of file usbh_core.c.

386 {
387 pudev->host.connect_status = 0U;
388
389 pudev->host.host_channel[0].endp_mps = 8U;
390
391 usb_core_select(pudev, core_id);
392
393 #ifndef DUAL_ROLE_MODE_ENABLED
394
395 USB_GLOBAL_INT_DISABLE();
396
397 usb_core_init(pudev);
398
399 /* force host mode*/
400 usb_mode_set(pudev, HOST_MODE);
401
402 usb_hostcore_init(pudev);
403
404 USB_GLOBAL_INT_ENABLE();
405
406 #endif
407
408 return 0U;
409 }
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:125
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:48
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:266
USB_GLOBAL_INT_DISABLE
#define USB_GLOBAL_INT_DISABLE()
Definition: usb_regs.h:545
USB_GLOBAL_INT_ENABLE
#define USB_GLOBAL_INT_ENABLE()
Definition: usb_regs.h:542
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:167
uint32_t hcd_is_device_connected ( usb_core_handle_struct * pudev )

check if the device is connected.

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
device connection status. 1 -> connected and 0 -> disconnected

Definition at line 417 of file usbh_core.c.

418 {
419 return (uint32_t)(pudev->host.connect_status);
420 }
urb_state_enum hcd_urb_state_get | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num
 | ) |  |

this function returns the last URBstate

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[out] | none
Return values
urb_state_enum

Definition at line 429 of file usbh_core.c.

430 {
431 return pudev->host.host_channel[channel_num].urb_state;
432 }
uint32_t hcd_xfer_count_get | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num
 | ) |  |

this function returns the last URBstate

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[out] | none
Return values
No. of data bytes transferred

Definition at line 441 of file usbh_core.c.

442 {
443 return pudev->host.host_channel[channel_num].xfer_count;
444 }
usbh_status_enum host_state_polling_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the polling function of HOST state

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 88 of file usbh_core.c.

91 {
92 usbh_state_handle_struct *p_state = (usbh_state_handle_struct *)pustate;
93
94 scd_begin(p_state, HOST_FSM_ID);
95
96 if (-1 == p_state->usbh_current_state_stack_top) {
97 uint8_t cur_state = p_state->usbh_current_state;
98
99 if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != cur_state)) {
100 if (HOST_DEV_DETACHED != cur_state) {
101 p_state->usbh_current_state = HOST_DEV_DETACHED;
102 cur_state = HOST_DEV_DETACHED;
103 }
104 }
105
106 host_state_handle[cur_state](pudev, puhost, p_state);
107 } else {
108 uint8_t stack0_state = p_state->stack[0].state;
109
110 if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != stack0_state)) {
111 if (HOST_DEV_DETACHED != stack0_state) {
112 p_state->stack[0].state = HOST_DEV_DETACHED;
113 stack0_state = HOST_DEV_DETACHED;
114 p_state->usbh_current_state = HOST_DEV_DETACHED;
115 }
116 }
117
118 host_state_handle[stack0_state](pudev, puhost, p_state);
119 }
120
121 return USBH_OK;
122 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
usbh_state_handle_struct
Definition: usbh_core.h:227
hcd_is_device_connected
uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev)
check if the device is connected.
Definition: usbh_core.c:417
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:213
HOST_DEV_DETACHED
Definition: usbh_core.h:55
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:538
HOST_FSM_ID
#define HOST_FSM_ID
Definition: usbh_core.h:38
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:233
host_state_handle
void(* host_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_core.c:51
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:234
USBH_OK
Definition: usbh_core.h:108
HOST_IDLE
Definition: usbh_core.h:53
usbh_status_enum only_state_move | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the function is only used to state move

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 692 of file usbh_core.c.

693 {
694 return USBH_OK;
695 }
USBH_OK
Definition: usbh_core.h:108
void scd_begin | ( | usbh_state_handle_struct * | pustate,
 |  | uint8_t | table_id
 | ) |  |

state core driver begin

Parameters
[in] | pustate | pointer to usb state driver
[in] | table_id | the id of the table to begin
[out] | none
Return values
none

Definition at line 538 of file usbh_core.c.

539 {
540 uint8_t i = 0U, table_num = pustate->usbh_regist_state_table_num;
541 usbh_state_regist_table_struct *cur_state_reg_table;
542
543 for (i = 0U; i < table_num; i++) {
544 cur_state_reg_table = &pustate->usbh_regist_state_table[i];
545
546 if (table_id == cur_state_reg_table->id) {
547 pustate->usbh_current_state_table = cur_state_reg_table->table;
548 pustate->usbh_current_state_table_size = cur_state_reg_table->table_size;
549 break;
550 }
551 }
552 }
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:231
usbh_state_handle_struct::usbh_regist_state_table
usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]
Definition: usbh_core.h:236
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:237
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:223
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:221
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:222
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:230
usbh_state_regist_table_struct
Definition: usbh_core.h:219
usbh_status_enum scd_event_handle | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | usbh_state_handle_struct * | pustate,
 |  | uint8_t | event,
 |  | uint8_t | state
 | ) |  |

state core driver event handle

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[in] | event | the current event
[in] | state | the current state
[out] | none
Return values
host status

Definition at line 576 of file usbh_core.c.

581 {
582 uint8_t i = 0U;
583 ACT_FUN event_act_fun = NULL;
584 state_table_struct *backup_state_t = pustate->usbh_current_state_table;
585 state_table_struct *executive_state_table = pustate->usbh_current_state_table;
586
587 /* look up the table to find the action function */
588 for (i = 0U; i < pustate->usbh_current_state_table_size; i++) {
589 if (state == executive_state_table->cur_state) {
590 if (event == executive_state_table->cur_event) {
591 state = executive_state_table->next_state;
592 event_act_fun = executive_state_table->event_action_fun;
593 break;
594 } else {
595 executive_state_table++;
596 }
597 } else {
598 executive_state_table++;
599 }
600 }
601
602 pustate->usbh_current_state_table = backup_state_t;
603
604 /* if the action function is not NULL, execute the action function */
605 if (event_act_fun) {
606 if (event_act_fun == &only_state_move) {
607 pustate->usbh_current_state = state;
608 } else {
609 return event_act_fun(pudev, puhost, pustate);
610 }
611 }
612
613 return USBH_BUSY;
614 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
state_table_struct::event_action_fun
ACT_FUN event_action_fun
Definition: usbh_core.h:207
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:231
state_table_struct::next_state
uint8_t next_state
Definition: usbh_core.h:206
state_table_struct
Definition: usbh_core.h:202
state_table_struct::cur_state
uint8_t cur_state
Definition: usbh_core.h:204
ACT_FUN
usbh_status_enum(* ACT_FUN)(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
Definition: usbh_core.h:199
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:230
NULL
#define NULL
Definition: usb_defines.h:18
USBH_BUSY
Definition: usbh_core.h:109
state_table_struct::cur_event
uint8_t cur_event
Definition: usbh_core.h:205
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:692
void scd_init ( usbh_state_handle_struct * pustate )

state core driver init

Parameters
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 484 of file usbh_core.c.

485 {
486 /* init the state core */
487 pustate->usbh_current_state = 0U;
488 pustate->usbh_current_state_table = NULL;
489 pustate->usbh_current_state_table_size = 0U;
490
491 pustate->usbh_current_state_stack_top = -1;
492 pustate->stack->state = 0U;
493 pustate->stack->table_size = 0U;
494 pustate->stack->table = NULL;
495
496 pustate->usbh_regist_state_table_num = 0U;
497 pustate->usbh_regist_state_table->table = NULL;
498 pustate->usbh_regist_state_table->table_size = 0U;
499 pustate->usbh_regist_state_table->id = 0U;
500
501 /* init the control and the enumeration polling handle flag */
502 ctrl_polling_handle_flag = 0U;
503 enum_polling_handle_flag = 0U;
504 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
enum_polling_handle_flag
uint8_t enum_polling_handle_flag
Definition: usbh_std.c:19
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:213
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:231
usbh_state_handle_struct::usbh_regist_state_table
usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]
Definition: usbh_core.h:236
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:237
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:223
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:221
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:233
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:214
ctrl_polling_handle_flag
uint8_t ctrl_polling_handle_flag
Definition: usbh_ctrl.c:16
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:222
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:234
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:230
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:215
NULL
#define NULL
Definition: usb_defines.h:18
void scd_state_move | ( | usbh_state_handle_struct * | pustate,
 |  | uint8_t | state
 | ) |  |

state core driver move state

Parameters
[in] | pustate | pointer to usb state driver
[in] | state | the state to move
[out] | none
Return values
none

Definition at line 561 of file usbh_core.c.

562 {
563 pustate->usbh_current_state = state;
564 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
void scd_table_pop ( usbh_state_handle_struct * pustate )

state core driver table pop

Parameters
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 644 of file usbh_core.c.

645 {
646 usbh_state_stack_struct *top_state_element;
647
648 top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top];
649
650 if (pustate->usbh_current_state_stack_top > -1) {
651 /* get the current state table from the state stack */
652 pustate->usbh_current_state = top_state_element->state;
653 pustate->usbh_current_state_table = top_state_element->table;
654 pustate->usbh_current_state_table_size = top_state_element->table_size;
655 pustate->usbh_current_state_stack_top--;
656 }
657 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:213
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:231
usbh_state_stack_struct
Definition: usbh_core.h:211
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:233
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:214
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:234
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:230
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:215
void scd_table_push ( usbh_state_handle_struct * pustate )

state core driver table push

Parameters
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 622 of file usbh_core.c.

623 {
624 usbh_state_stack_struct *top_state_element;
625
626 if (pustate->usbh_current_state_stack_top < MAX_USBH_STATE_STACK_DEEP) {
627 pustate->usbh_current_state_stack_top++;
628
629 top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top];
630
631 /* put the current state table into the state stack */
632 top_state_element->state = pustate->usbh_current_state;
633 top_state_element->table = pustate->usbh_current_state_table;
634 top_state_element->table_size = pustate->usbh_current_state_table_size;
635 }
636 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:213
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:231
usbh_state_stack_struct
Definition: usbh_core.h:211
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:233
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:214
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:234
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:230
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:215
MAX_USBH_STATE_STACK_DEEP
#define MAX_USBH_STATE_STACK_DEEP
Definition: usbh_core.h:35
void scd_table_regist | ( | usbh_state_handle_struct * | pustate,
 |  | state_table_struct * | pstate_table,
 |  | uint8_t | table_id,
 |  | uint8_t | current_table_size
 | ) |  |

state core driver table regist

Parameters
[in] | pustate | pointer to usb state driver
[in] | pstate_table | pointer to the table to regist
[in] | table_id | the id of the table to regist
[in] | current_table_size | the size of the current table to regist
[out] | none
Return values
none

Definition at line 515 of file usbh_core.c.

519 {
520 usbh_state_regist_table_struct *cur_state_reg_table;
521
522 cur_state_reg_table = &pustate->usbh_regist_state_table[pustate->usbh_regist_state_table_num];
523
524 cur_state_reg_table->id = table_id;
525 cur_state_reg_table->table = pstate_table;
526 cur_state_reg_table->table_size = current_table_size;
527
528 pustate->usbh_regist_state_table_num++;
529 }
usbh_state_handle_struct::usbh_regist_state_table
usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]
Definition: usbh_core.h:236
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:237
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:223
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:221
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:222
usbh_state_regist_table_struct
Definition: usbh_core.h:219
uint8_t usbh_connected ( usb_core_handle_struct * pudev )

usb connect callback function from the interrupt.

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
operation status

Definition at line 346 of file usbh_core.c.

347 {
348 pudev->host.connect_status = 1U;
349
350 return 0U;
351 }
usbh_status_enum usbh_deinit | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | usbh_state_handle_struct * | pustate
 | ) |  |

de-initialize host

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[out] | none
Return values
host status

Definition at line 453 of file usbh_core.c.

456 {
457 /* software init */
458
459 puhost->control.ep0_size = USB_MAX_EP0_SIZE;
460
461 puhost->device.address = USBH_DEVICE_ADDRESS_DEFAULT;
462 puhost->device.speed = HPRT_PRTSPD_FULL_SPEED;
463
464 usbh_channel_free(pudev, puhost->control.hc_in_num);
465 usbh_channel_free(pudev, puhost->control.hc_out_num);
466
467 scd_init(pustate);
468 scd_table_regist(pustate, host_handle_table, HOST_FSM_ID, HOST_HANDLE_TABLE_SIZE);
469 scd_table_regist(pustate, enum_handle_table, ENUM_FSM_ID, ENUM_HANDLE_TABLE_SIZE);
470 scd_table_regist(pustate, ctrl_handle_table, CTRL_FSM_ID, CTRL_HANDLE_TABLE_SIZE);
471
472 scd_begin(pustate,HOST_FSM_ID);
473 scd_state_move(pustate, HOST_IDLE);
474
475 return USBH_OK;
476 }
ENUM_FSM_ID
#define ENUM_FSM_ID
Definition: usbh_core.h:39
usbh_channel_free
uint8_t usbh_channel_free(usb_core_handle_struct *pudev, uint8_t index)
free the usb host channel
Definition: usbh_hcs.c:114
host_handle_table
state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE]
Definition: usbh_core.c:66
CTRL_FSM_ID
#define CTRL_FSM_ID
Definition: usbh_core.h:41
usbh_ctrl_struct::hc_in_num
uint8_t hc_in_num
Definition: usbh_core.h:127
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:561
scd_table_regist
void scd_table_regist(usbh_state_handle_struct *pustate, state_table_struct *pstate_table, uint8_t table_id, uint8_t current_table_size)
state core driver table regist
Definition: usbh_core.c:515
usbh_ctrl_struct::ep0_size
uint8_t ep0_size
Definition: usbh_core.h:129
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:538
scd_init
void scd_init(usbh_state_handle_struct *pustate)
state core driver init
Definition: usbh_core.c:484
CTRL_HANDLE_TABLE_SIZE
#define CTRL_HANDLE_TABLE_SIZE
Definition: usbh_ctrl.h:18
usbh_device_struct::speed
uint8_t speed
Definition: usbh_core.h:141
HOST_FSM_ID
#define HOST_FSM_ID
Definition: usbh_core.h:38
usbh_device_struct::address
uint8_t address
Definition: usbh_core.h:140
ctrl_handle_table
state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]
Definition: usbh_ctrl.c:46
HPRT_PRTSPD_FULL_SPEED
#define HPRT_PRTSPD_FULL_SPEED
Definition: usb_defines.h:74
USB_MAX_EP0_SIZE
#define USB_MAX_EP0_SIZE
Definition: usb_core.h:19
usbh_host_struct::device
usbh_device_struct device
Definition: usbh_core.h:192
USBH_OK
Definition: usbh_core.h:108
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:191
ENUM_HANDLE_TABLE_SIZE
#define ENUM_HANDLE_TABLE_SIZE
Definition: usbh_std.h:23
enum_handle_table
state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]
Definition: usbh_std.c:48
HOST_IDLE
Definition: usbh_core.h:53
USBH_DEVICE_ADDRESS_DEFAULT
#define USBH_DEVICE_ADDRESS_DEFAULT
Definition: usbh_core.h:24
usbh_ctrl_struct::hc_out_num
uint8_t hc_out_num
Definition: usbh_core.h:128
HOST_HANDLE_TABLE_SIZE
#define HOST_HANDLE_TABLE_SIZE
Definition: usbh_core.h:48
uint8_t usbh_disconnected ( usb_core_handle_struct * pudev )

usb disconnect callback function from the interrupt.

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
operation status

Definition at line 359 of file usbh_core.c.

360 {
361 pudev->host.connect_status = 0U;
362
363 return 0U;
364 }
uint8_t usbh_sof ( usb_core_handle_struct * pudev )

usb sof callback function from the interrupt.

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
operation status

Definition at line 372 of file usbh_core.c.

373 {
374 /* this callback could be used to implement a scheduler process */
375 return 0U;
376 }

Variable Documentation

class_polling_fun_cb_struct class_polling_cb
state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE]
Initial value:
=
{
{HOST_IDLE, HOST_EVENT_ATTACHED, HOST_DEV_ATTACHED, only_state_move },
{HOST_DEV_ATTACHED, HOST_EVENT_ENUM, HOST_ENUMERATION, only_state_move },
{HOST_ENUMERATION, HOST_EVENT_USER_INPUT, HOST_USER_INPUT, only_state_move },
{HOST_USER_INPUT, HOST_EVENT_CLASS_REQ, HOST_CLASS_REQUEST, only_state_move },
{HOST_CLASS_REQUEST, HOST_EVENT_CLASS, HOST_CLASS, only_state_move },
{HOST_CLASS, HOST_EVENT_ERROR, HOST_ERROR, only_state_move },
{HOST_ERROR, HOST_EVENT_IDLE, HOST_IDLE, only_state_move },
{HOST_DEV_DETACHED, HOST_EVENT_IDLE, HOST_IDLE, only_state_move },
{HOST_CLASS_REQUEST, HOST_EVENT_ERROR, HOST_ERROR, only_state_move },
}
HOST_EVENT_IDLE
Definition: usbh_core.h:75
HOST_EVENT_CLASS_REQ
Definition: usbh_core.h:71
HOST_EVENT_CLASS
Definition: usbh_core.h:72
HOST_EVENT_ENUM
Definition: usbh_core.h:69
HOST_CLASS
Definition: usbh_core.h:59
HOST_ERROR
Definition: usbh_core.h:62
HOST_DEV_DETACHED
Definition: usbh_core.h:55
HOST_EVENT_ERROR
Definition: usbh_core.h:73
HOST_DEV_ATTACHED
Definition: usbh_core.h:54
HOST_ENUMERATION
Definition: usbh_core.h:57
HOST_EVENT_ATTACHED
Definition: usbh_core.h:68
HOST_CLASS_REQUEST
Definition: usbh_core.h:58
HOST_USER_INPUT
Definition: usbh_core.h:60
HOST_IDLE
Definition: usbh_core.h:53
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:692
HOST_EVENT_USER_INPUT
Definition: usbh_core.h:70

Definition at line 66 of file usbh_core.c.

void(* host_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Initial value:
=
{
host_idle_handle,
host_dev_attached_handle,
host_dev_detached_handle,
host_detect_dev_speed_handle,
host_enum_handle,
host_class_request_handle,
host_class_handle,
host_user_input_handle,
host_suspended_handle,
host_error_handle,
}

Definition at line 51 of file usbh_core.c.

usbh_hcd_int_cb_struct usbh_hcd_int_cb
Initial value:
=
{
usbh_sof,
usbh_connected,
usbh_disconnected,
}
usbh_connected
uint8_t usbh_connected(usb_core_handle_struct *pudev)
usb connect callback function from the interrupt.
Definition: usbh_core.c:346
usbh_sof
uint8_t usbh_sof(usb_core_handle_struct *pudev)
usb sof callback function from the interrupt.
Definition: usbh_core.c:372
usbh_disconnected
uint8_t usbh_disconnected(usb_core_handle_struct *pudev)
usb disconnect callback function from the interrupt.
Definition: usbh_core.c:359

Definition at line 26 of file usbh_core.c.

usbh_hcd_int_cb_struct* usbh_hcd_int_fops = &usbh_hcd_int_cb

Definition at line 33 of file usbh_core.c.

usbh_state_handle_struct usbh_state_core


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbh_ctrl.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
Functions | Variables
usbh_ctrl.c File Reference

this file implements the functions for the control transmit process More...

#include "usbh_core.h"
#include "usbh_std.h"
#include "usbh_ctrl.h"

Go to the source code of this file.

Functions

usbh_status_enum | ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of CTRL state More...
usbh_status_enum | usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len)
send datas from the host channel More...
usbh_status_enum | usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num)
send the setup packet to the device More...
uint32_t | hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer More...

Variables

uint8_t | ctrl_polling_handle_flag = 0U
uint8_t | ctrl_setup_wait_flag = 0U
uint8_t | ctrl_data_wait_flag = 0U
uint8_t | ctrl_status_wait_flag = 0U
void(* | ctrl_state_handle [])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
state_table_struct ctrl_handle_table [CTRL_HANDLE_TABLE_SIZE]

Detailed Description

this file implements the functions for the control transmit process

Definition in file usbh_ctrl.c.

Function Documentation

usbh_status_enum ctrl_state_polling_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the polling function of CTRL state

Parameters
[in] | pudev | pointer to usb device
[in] | puhost | pointer to usb host
[in] | pustate | pointer to usb state driver
[out] | none
Return values
none

Definition at line 72 of file usbh_ctrl.c.

75 {
76 usbh_status_enum exe_state = USBH_BUSY;
77 usbh_state_handle_struct *p_state;
78
79 p_state = (usbh_state_handle_struct *)pustate;
80
81 /* if first enter this function, begin the ctrl state */
82 if (0U == ctrl_polling_handle_flag) {
83 ctrl_polling_handle_flag = 1U;
84 scd_table_push(p_state);
85 scd_state_move(p_state, CTRL_IDLE);
86 }
87
88 /* base on the current state to handle the ctrl state */
89 scd_begin(p_state, CTRL_FSM_ID);
90 ctrl_state_handle[p_state->usbh_current_state](pudev, puhost, p_state);
91
92 /* determine the control transfer whether to complete */
93 switch (puhost->usbh_backup_state.ctrl_backup_state) {
94 case CTRL_COMPLETE:
95 ctrl_polling_handle_flag = 0U;
96 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
97 exe_state = USBH_OK;
98 break;
99 case CTRL_STALLED:
100 ctrl_polling_handle_flag = 0U;
101 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
102 exe_state = USBH_NOT_SUPPORTED;
103 break;
104 case CTRL_ERROR:
105 ctrl_polling_handle_flag = 0U;
106 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
107 exe_state = USBH_FAIL;
108 break;
109 default:
110 exe_state = USBH_BUSY;
111 break;
112 }
113
114 return exe_state;
115 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
usbh_state_handle_struct
Definition: usbh_core.h:227
ctrl_state_handle
void(* ctrl_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_ctrl.c:32
CTRL_IDLE
Definition: usbh_core.h:96
CTRL_ERROR
Definition: usbh_core.h:100
CTRL_FSM_ID
#define CTRL_FSM_ID
Definition: usbh_core.h:41
ctrl_polling_handle_flag
uint8_t ctrl_polling_handle_flag
Definition: usbh_ctrl.c:16
USBH_NOT_SUPPORTED
Definition: usbh_core.h:111
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:106
CTRL_STALLED
Definition: usbh_core.h:101
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:561
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:538
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:622
USBH_OK
Definition: usbh_core.h:108
USBH_FAIL
Definition: usbh_core.h:110
CTRL_COMPLETE
Definition: usbh_core.h:102
USBH_BUSY
Definition: usbh_core.h:109
uint32_t hcd_submit_request | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num
 | ) |  |

this function prepare a hc and start a transfer

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[out] | none
Return values
host operation status

Definition at line 604 of file usbh_ctrl.c.

605 {
606 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
607
608 puhc->urb_state = URB_IDLE;
609 puhc->xfer_count = 0U;
610
611 return (uint32_t)usb_hostchannel_startxfer(pudev, channel_num);
612 }
usb_hostchannel_struct::urb_state
urb_state_enum urb_state
Definition: usb_core.h:172
URB_IDLE
Definition: usb_core.h:50
usb_hostchannel_struct
Definition: usb_core.h:154
usb_hostchannel_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:167
usbh_status_enum usbh_ctltx_setup | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | buf,
 |  | uint8_t | hc_num
 | ) |  |

send the setup packet to the device

Parameters
[in] | pudev | pointer to usb device
[in] | buf | buffer pointer from which the data will be send to device
[in] | hc_num | host channel number
[out] | none
Return values
host operation status

Definition at line 586 of file usbh_ctrl.c.

587 {
588 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
589
590 puhc->DPID = HC_PID_SETUP;
591 puhc->xfer_buff = buf;
592 puhc->xfer_len = USBH_SETUP_PACKET_SIZE;
593
594 return (usbh_status_enum)hcd_submit_request (pudev, hc_num);
595 }
hcd_submit_request
uint32_t hcd_submit_request(usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer
Definition: usbh_ctrl.c:604
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:165
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:106
usb_hostchannel_struct
Definition: usb_core.h:154
USBH_SETUP_PACKET_SIZE
#define USBH_SETUP_PACKET_SIZE
Definition: usbh_std.h:22
usb_hostchannel_struct::DPID
uint8_t DPID
Definition: usb_core.h:158
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:166
HC_PID_SETUP
#define HC_PID_SETUP
Definition: usb_defines.h:71
usbh_status_enum usbh_xfer | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t * | buf,
 |  | uint8_t | hc_num,
 |  | uint16_t | len
 | ) |  |

send datas from the host channel

Parameters
[in] | pudev | pointer to usb device
[in] | buf | data buffer address to send datas
[in] | hc_num | the number of the host channel
[in] | len | length of the send data
[out] | none
Return values
host operation status

Definition at line 493 of file usbh_ctrl.c.

497 {
498 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
499
500 puhc->xfer_buff = buf;
501 puhc->xfer_len = len;
502
503 switch (puhc->endp_type) {
504 case USB_EPTYPE_CTRL:
505 if (0U == puhc->endp_in) {
506 if (0U == len) {
507 /* for status out stage, length = 0, status out pid = 1 */
508 puhc->data_tg_out = 1U;
509 }
510
511 /* set the data toggle bit as per the flag */
512 if (0U == puhc->data_tg_out) {
513 /* put the pid 0 */
514 puhc->DPID = HC_PID_DATA0;
515 } else {
516 /* put the pid 1 */
517 puhc->DPID = HC_PID_DATA1;
518 }
519 } else {
520 puhc->DPID = HC_PID_DATA1;
521 }
522 break;
523
524 case USB_EPTYPE_ISOC:
525 puhc->DPID = HC_PID_DATA0;
526 break;
527
528 case USB_EPTYPE_BULK:
529 if (0U == puhc->endp_in) {
530 /* set the data toggle bit as per the flag */
531 if (0U == puhc->data_tg_out) {
532 /* put the pid 0 */
533 puhc->DPID = HC_PID_DATA0;
534 } else {
535 /* put the pid 1 */
536 puhc->DPID = HC_PID_DATA1;
537 }
538 } else {
539 if (0U == puhc->data_tg_in) {
540 puhc->DPID = HC_PID_DATA0;
541 } else {
542 puhc->DPID = HC_PID_DATA1;
543 }
544 }
545 break;
546
547 case USB_EPTYPE_INTR:
548 if (0U == puhc->endp_in) {
549 if (0U == puhc->data_tg_out) {
550 puhc->DPID = HC_PID_DATA0;
551 } else {
552 puhc->DPID = HC_PID_DATA1;
553 }
554
555 /* toggle data pid */
556 puhc->data_tg_out ^= 1U;
557 } else {
558 if (0U == puhc->data_tg_in) {
559 puhc->DPID = HC_PID_DATA0;
560 } else {
561 puhc->DPID = HC_PID_DATA1;
562 }
563
564 /* toggle data pid */
565 puhc->data_tg_in ^= 1U;
566 }
567 break;
568
569 default:
570 break;
571 }
572
573 hcd_submit_request (pudev, hc_num);
574
575 return USBH_OK;
576 }
hcd_submit_request
uint32_t hcd_submit_request(usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer
Definition: usbh_ctrl.c:604
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:52
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:165
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:175
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:54
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:160
USB_EPTYPE_CTRL
#define USB_EPTYPE_CTRL
Definition: usb_defines.h:51
HC_PID_DATA1
#define HC_PID_DATA1
Definition: usb_defines.h:70
usb_hostchannel_struct
Definition: usb_core.h:154
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:174
HC_PID_DATA0
#define HC_PID_DATA0
Definition: usb_defines.h:68
usb_hostchannel_struct::DPID
uint8_t DPID
Definition: usb_core.h:158
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:166
USBH_OK
Definition: usbh_core.h:108
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:161
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:53

Variable Documentation

uint8_t ctrl_data_wait_flag = 0U

Definition at line 18 of file usbh_ctrl.c.

state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]
Initial value:
=
{
{CTRL_IDLE, CTRL_EVENT_SETUP, CTRL_SETUP, only_state_move },
{CTRL_SETUP, CTRL_EVENT_DATA, CTRL_DATA, only_state_move },
{CTRL_SETUP, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move },
{CTRL_SETUP, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move },
{CTRL_DATA, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move },
{CTRL_DATA, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move },
{CTRL_DATA, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move },
{CTRL_STATUS, CTRL_EVENT_COMPLETE, CTRL_COMPLETE, only_state_move },
{CTRL_STATUS, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move },
{CTRL_STATUS, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move },
{CTRL_ERROR, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
{CTRL_STALLED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
{CTRL_COMPLETE, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
}
goto_up_state_fun
usbh_status_enum goto_up_state_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state
Definition: usbh_core.c:705
CTRL_EVENT_ERROR
Definition: usbh_ctrl.h:31
CTRL_IDLE
Definition: usbh_core.h:96
CTRL_ERROR
Definition: usbh_core.h:100
UP_STATE
#define UP_STATE
Definition: usbh_core.h:45
CTRL_EVENT_SETUP
Definition: usbh_ctrl.h:27
GO_TO_UP_STATE_EVENT
#define GO_TO_UP_STATE_EVENT
Definition: usbh_core.h:46
CTRL_STATUS
Definition: usbh_core.h:99
CTRL_STALLED
Definition: usbh_core.h:101
CTRL_EVENT_DATA
Definition: usbh_ctrl.h:28
CTRL_EVENT_STALLED
Definition: usbh_ctrl.h:32
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:692
CTRL_SETUP
Definition: usbh_core.h:97
CTRL_EVENT_COMPLETE
Definition: usbh_ctrl.h:30
CTRL_COMPLETE
Definition: usbh_core.h:102
CTRL_DATA
Definition: usbh_core.h:98
CTRL_EVENT_STATUS
Definition: usbh_ctrl.h:29

Definition at line 46 of file usbh_ctrl.c.

uint8_t ctrl_polling_handle_flag = 0U

Definition at line 16 of file usbh_ctrl.c.

uint8_t ctrl_setup_wait_flag = 0U

Definition at line 17 of file usbh_ctrl.c.

void(* ctrl_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Initial value:
=
{
ctrl_idle_handle,
ctrl_setup_handle,
ctrl_data_handle,
ctrl_status_handle,
ctrl_error_handle,
ctrl_stalled_handle,
ctrl_complete_handle,
}

Definition at line 32 of file usbh_ctrl.c.

uint8_t ctrl_status_wait_flag = 0U

Definition at line 19 of file usbh_ctrl.c.


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbh_hcs.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
Functions
usbh_hcs.c File Reference

this file implements functions for opening and closing host channels More...

#include "usbh_hcs.h"

Go to the source code of this file.

Functions

uint8_t | usbh_channel_open (usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
open a channel More...
uint8_t | usbh_channel_modify (usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
modify a channel More...
uint8_t | usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr)
allocate a new channel for the pipe More...
uint8_t | usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index)
free the usb host channel More...
uint8_t | usbh_allchannel_dealloc (usb_core_handle_struct *pudev)
free all usb host channel More...

Detailed Description

this file implements functions for opening and closing host channels

Definition in file usbh_hcs.c.

Function Documentation

uint8_t usbh_allchannel_dealloc ( usb_core_handle_struct * pudev )

free all usb host channel

Parameters
[in] | pudev | pointer to usb device
[out] | none
Return values
host operation status

Definition at line 129 of file usbh_hcs.c.

130 {
131 uint8_t index;
132
133 for (index = 2U; index < HC_MAX; index ++) {
134 pudev->host.host_channel[index].info = 0U;
135 }
136
137 return USBH_OK;
138 }
HC_MAX
#define HC_MAX
Definition: usbh_hcs.h:17
USBH_OK
Definition: usbh_core.h:108
uint8_t usbh_channel_alloc | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | ep_addr
 | ) |  |

allocate a new channel for the pipe

Parameters
[in] | pudev | pointer to usb device
[in] | ep_addr | endpoint for which the channel to be allocated
[out] | none
Return values
host channel number

Definition at line 96 of file usbh_hcs.c.

97 {
98 uint16_t hc_num = usbh_freechannel_get(pudev);
99
100 if ((uint16_t)HC_ERROR != hc_num) {
101 pudev->host.host_channel[hc_num].info = HC_USED | ep_addr;
102 }
103
104 return (uint8_t)hc_num;
105 }
HC_USED
#define HC_USED
Definition: usbh_hcs.h:20
HC_ERROR
#define HC_ERROR
Definition: usbh_hcs.h:21
uint8_t usbh_channel_free | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | index
 | ) |  |

free the usb host channel

Parameters
[in] | pudev | pointer to usb device
[in] | index | channel number to be freed which is in (0..7)
[out] | none
Return values
host operation status

Definition at line 114 of file usbh_hcs.c.

115 {
116 if (index < HC_MAX) {
117 pudev->host.host_channel[index].info &= HC_USED_MASK;
118 }
119
120 return USBH_OK;
121 }
HC_MAX
#define HC_MAX
Definition: usbh_hcs.h:17
HC_USED_MASK
#define HC_USED_MASK
Definition: usbh_hcs.h:22
USBH_OK
Definition: usbh_core.h:108
uint8_t usbh_channel_modify | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num,
 |  | uint8_t | dev_addr,
 |  | uint8_t | dev_speed,
 |  | uint8_t | ep_type,
 |  | uint16_t | ep_mps
 | ) |  |

modify a channel

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[in] | dev_addr | USB Device address allocated to attached device
[in] | dev_speed | USB device speed (Full speed/Low speed)
[in] | ep_type | endpoint type (bulk/int/ctl)
[in] | ep_mps | max packet size
[out] | none
Return values
operation status

Definition at line 63 of file usbh_hcs.c.

69 {
70 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
71
72 if (0U != dev_addr) {
73 puhc->dev_addr = dev_addr;
74 }
75
76 if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) {
77 puhc->endp_mps = ep_mps;
78 }
79
80 if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) {
81 puhc->dev_speed = dev_speed;
82 }
83
84 usb_hostchannel_init(pudev, channel_num);
85
86 return (uint8_t)HC_OK;
87 }
usb_hostchannel_struct
Definition: usb_core.h:154
usb_hostchannel_struct::endp_mps
uint16_t endp_mps
Definition: usb_core.h:162
usb_hostchannel_struct::dev_addr
uint8_t dev_addr
Definition: usb_core.h:156
usb_hostchannel_struct::dev_speed
uint8_t dev_speed
Definition: usb_core.h:157
HC_OK
#define HC_OK
Definition: usbh_hcs.h:19
uint8_t usbh_channel_open | ( | usb_core_handle_struct * | pudev,
 |  | uint8_t | channel_num,
 |  | uint8_t | dev_addr,
 |  | uint8_t | dev_speed,
 |  | uint8_t | ep_type,
 |  | uint16_t | ep_mps
 | ) |  |

open a channel

Parameters
[in] | pudev | pointer to usb device
[in] | channel_num | host channel number which is in (0..7)
[in] | dev_addr | USB device address allocated to attached device
[in] | dev_speed | USB device speed (Full speed/Low speed)
[in] | ep_type | endpoint type (bulk/int/ctl)
[in] | ep_mps | max packet size
[out] | none
Return values
operation status

Definition at line 27 of file usbh_hcs.c.

33 {
34 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
35 uint16_t channel_info = puhc->info;
36
37 puhc->endp_id = (uint8_t)channel_info & 0x7FU;
38 puhc->endp_in = (uint8_t)(channel_info & 0x80U) >> 7;
39 puhc->endp_type = ep_type;
40 puhc->endp_mps = ep_mps;
41 puhc->dev_addr = dev_addr;
42 puhc->dev_speed = dev_speed;
43
44 puhc->data_tg_in = 0U;
45 puhc->data_tg_out = 0U;
46
47 usb_hostchannel_init(pudev, channel_num);
48
49 return (uint8_t)HC_OK;
50 }
usb_hostchannel_struct::info
uint16_t info
Definition: usb_core.h:163
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:175
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:160
usb_hostchannel_struct
Definition: usb_core.h:154
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:174
usb_hostchannel_struct::endp_mps
uint16_t endp_mps
Definition: usb_core.h:162
usb_hostchannel_struct::dev_addr
uint8_t dev_addr
Definition: usb_core.h:156
usb_hostchannel_struct::dev_speed
uint8_t dev_speed
Definition: usb_core.h:157
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:161
HC_OK
#define HC_OK
Definition: usbh_hcs.h:19
usb_hostchannel_struct::endp_id
uint8_t endp_id
Definition: usb_core.h:159
Generated on Tue Jun 27 2017 14:36:15 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbh_int.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
Functions
usbh_int.c File Reference

USB host mode interrupt handler file. More...

#include "usb_core.h"
#include "usb_defines.h"
#include "usbh_int.h"

Go to the source code of this file.

Functions

uint32_t usbh_isr (usb_core_handle_struct *pudev)
handle global host interrupt More...

Detailed Description

USB host mode interrupt handler file.

Definition in file usbh_int.c.

Function Documentation

uint32_t usbh_isr ( usb_core_handle_struct * pudev )

handle global host interrupt

Parameters
[in] | pudev | pointer to usb device instance
[out] | none
Return values
operation status

Definition at line 33 of file usbh_int.c.

34 {
35 uint32_t retval = 0U;
36 uint32_t int_flag = 0U;
37
38 /* check if host mode */
39 if (USB_CURRENT_MODE_GET() == HOST_MODE) {
40 USB_CORE_INTR_READ(int_flag);
41
42 if (!int_flag) {
43 return 0U;
44 }
45
46 /* start of frame interrupt handle */
47 if (int_flag & GINTF_SOF) {
48 retval |= usbh_intf_sof (pudev);
49 }
50
51 /* Rx FIFO non-empty interrupt handle */
52 if (int_flag & GINTF_RXFNEIF) {
53 retval |= usbh_intf_rxfifo_noempty (pudev);
54 }
55
56 /* Non-Periodic Tx FIFO empty interrupt hanlde */
57 if (int_flag & GINTF_NPTXFEIF) {
58 retval |= usbh_intf_nptxfifo_empty (pudev);
59 }
60
61 /* periodic Tx FIFO empty interrupt handle */
62 if (int_flag & GINTF_PTXFEIF) {
63 retval |= usbh_intf_ptxfifo_empty (pudev);
64 }
65
66 /* host channels interrupt handle */
67 if (int_flag & GINTF_HCIF) {
68 retval |= usbh_intf_hc (pudev);
69 }
70
71 /* host port interrupt handle */
72 if (int_flag & GINTF_HPIF) {
73 retval |= usbh_intf_port (pudev);
74 }
75
76 /* disconnect interrupt handle */
77 if (int_flag & GINTF_DISCIF) {
78 retval |= usbh_intf_disconnect (pudev);
79 }
80
81 /* isochronous IN transfer not complete interrupt handle */
82 if (int_flag & GINTF_ISOONCIF) {
83 retval |= usbh_intf_iso_incomplete_xfer (pudev);
84 }
85 }
86
87 return retval;
88 }
USB_CORE_INTR_READ
#define USB_CORE_INTR_READ(x)
Definition: usb_regs.h:551
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:48
GINTF_RXFNEIF
#define GINTF_RXFNEIF
Definition: usb_regs.h:165
USB_CURRENT_MODE_GET
#define USB_CURRENT_MODE_GET()
Definition: usb_regs.h:548
GINTF_HCIF
#define GINTF_HCIF
Definition: usb_regs.h:149
GINTF_HPIF
#define GINTF_HPIF
Definition: usb_regs.h:150
GINTF_NPTXFEIF
#define GINTF_NPTXFEIF
Definition: usb_regs.h:164
GINTF_ISOONCIF
#define GINTF_ISOONCIF
Definition: usb_regs.h:152
GINTF_PTXFEIF
#define GINTF_PTXFEIF
Definition: usb_regs.h:148
GINTF_SOF
#define GINTF_SOF
Definition: usb_regs.h:166
GINTF_DISCIF
#define GINTF_DISCIF
Definition: usb_regs.h:146
Generated on Tue Jun 27 2017 14:36:15 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbh_std.c File Reference

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
Functions | Variables
usbh_std.c File Reference

USB 2.0 standard function definition. More...

#include "usbh_core.h"
#include "usbh_usr.h"
#include "usbh_std.h"
#include "usbh_ctrl.h"

Go to the source code of this file.

Functions

usbh_status_enum | enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of enumeration state More...
void | usbh_enum_desc_get (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t *buf, uint8_t req_type, uint16_t value_idx, uint16_t len)
get descriptor in usb host enumeration stage More...
void | usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address)
set address in usb host enumeration stage More...
void | usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx)
set configuration in usb host enumeration stage More...
void | usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len)
parse the device descriptor More...
void | usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, usb_descriptor_interface_struct *itf_desc, usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], uint8_t *buf, uint16_t len)
parse the configuration descriptor More...
void | usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf)
parse the interface descriptor More...
void | usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf)
parse the endpoint descriptor More...
void | usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len)
parse the string descriptor More...
usb_descriptor_header_struct * | usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr)
get the next descriptor header More...

Variables

uint8_t | local_buffer [64]
uint8_t | usbh_cfg_desc [512]
uint8_t | enum_polling_handle_flag = 0U
void(* | enum_state_handle [])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
state_table_struct enum_handle_table [ENUM_HANDLE_TABLE_SIZE]

Detailed Description

USB 2.0 standard function definition.

Definition in file usbh_std.c.

Function Documentation

usbh_status_enum enum_state_polling_fun | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | void * | pustate
 | ) |  |

the polling function of enumeration state

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | pustate | pointer to USB state driver
[out] | none
Return values
usb host status

Definition at line 71 of file usbh_std.c.

72 {
73 usbh_status_enum exe_state = USBH_BUSY;
74 usbh_state_handle_struct *p_state;
75 p_state = (usbh_state_handle_struct *)pustate;
76
77 if (0U == enum_polling_handle_flag) {
78 enum_polling_handle_flag = 1U;
79 scd_table_push(p_state);
80 scd_state_move(p_state, ENUM_IDLE);
81 }
82
83 /* start the enumeration state handle */
84 scd_begin(p_state,ENUM_FSM_ID);
85
86 if (0 == p_state->usbh_current_state_stack_top) {
87 enum_state_handle[p_state->usbh_current_state](pudev, puhost, p_state);
88 } else {
89 enum_state_handle[p_state->stack[1].state](pudev, puhost, p_state);
90 }
91
92 /* determine the enumeration whether to complete */
93 if (ENUM_DEV_CONFIGURED == puhost->usbh_backup_state.enum_backup_state) {
94 puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE;
95 enum_polling_handle_flag = 0U;
96 exe_state = USBH_OK;
97 }
98
99 return exe_state;
100 }
ENUM_DEV_CONFIGURED
Definition: usbh_core.h:90
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
enum_polling_handle_flag
uint8_t enum_polling_handle_flag
Definition: usbh_std.c:19
usbh_state_handle_struct
Definition: usbh_core.h:227
ENUM_FSM_ID
#define ENUM_FSM_ID
Definition: usbh_core.h:39
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:213
ENUM_IDLE
Definition: usbh_core.h:81
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:106
backup_state_struct::enum_backup_state
enum_state_enum enum_backup_state
Definition: usbh_core.h:181
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:561
enum_state_handle
void(* enum_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_std.c:33
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:538
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:233
usbh_host_struct::usbh_backup_state
backup_state_struct usbh_backup_state
Definition: usbh_core.h:190
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:622
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:234
USBH_OK
Definition: usbh_core.h:108
USBH_BUSY
Definition: usbh_core.h:109
void usbh_cfg_desc_parse | ( | usb_descriptor_configuration_struct * | cfg_desc,
 |  | usb_descriptor_interface_struct * | itf_desc,
 |  | usb_descriptor_endpoint_struct | ep_desc[][USBH_MAX_EP_NUM],
 |  | uint8_t * | buf,
 |  | uint16_t | len
 | ) |  |

parse the configuration descriptor

Parameters
[in] | cfg_desc | configuration descriptor address
[in] | itf_desc | interface descriptor address
[in] | ep_desc | endpoint descriptor address
[in] | buf | buffer where the source descriptor is available
[in] | len | length of the descriptor
[out] | none
Return values
none

Definition at line 637 of file usbh_std.c.

642 {
643 usb_descriptor_interface_struct *pitf = NULL;
644 usb_descriptor_interface_struct temp_pitf;
645 usb_descriptor_endpoint_struct *pep = NULL;
646 usb_descriptor_header_struct *pdesc = (usb_descriptor_header_struct *)buf;
647
648 uint8_t itf_ix = 0U;
649 uint8_t ep_ix = 0U;
650 uint16_t ptr = 0U;
651 static uint8_t prev_itf = 0U;
652 static uint16_t prev_ep_size = 0U;
653
654 /* parse configuration descriptor */
655 cfg_desc->Header.bLength = *(uint8_t *)(buf + 0);
656 cfg_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
657 cfg_desc->wTotalLength = SWAPBYTE(buf + 2);
658 cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4);
659 cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5);
660 cfg_desc->iConfiguration = *(uint8_t *)(buf + 6);
661 cfg_desc->bmAttributes = *(uint8_t *)(buf + 7);
662 cfg_desc->bMaxPower = *(uint8_t *)(buf + 8);
663
664 if (len > USB_CFGDESC_SIZE) {
665 ptr = USB_CFG_DESC_LEN;
666
667 if (cfg_desc->bNumInterfaces <= USBH_MAX_INTERFACES_NUM) {
668 pitf = (usb_descriptor_interface_struct *)0;
669
670 for (; ptr < cfg_desc->wTotalLength; ) {
671 pdesc = usbh_next_desc_get((uint8_t *)pdesc, &ptr);
672
673 if (USB_DESCTYPE_INTERFACE == pdesc->bDescriptorType) {
674 itf_ix = *((uint8_t *)pdesc + 2U);
675 pitf = &itf_desc[itf_ix];
676
677 if (*((uint8_t *)pdesc + 3U) < 3U) {
678 usbh_interface_desc_parse (&temp_pitf, (uint8_t *)pdesc);
679
680 /* parse endpoint descriptors relative to the current interface */
681 if (temp_pitf.bNumEndpoints <= USBH_MAX_EP_NUM) {
682 for (ep_ix = 0U; ep_ix < temp_pitf.bNumEndpoints;) {
683 pdesc = usbh_next_desc_get((void* )pdesc, &ptr);
684
685 if (USB_DESCTYPE_ENDPOINT == pdesc->bDescriptorType) {
686 pep = &ep_desc[itf_ix][ep_ix];
687
688 if (prev_itf != itf_ix) {
689 prev_itf = itf_ix;
690 usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf);
691 } else {
692 if (prev_ep_size > SWAPBYTE((uint8_t *)pdesc + 4)) {
693 break;
694 } else {
695 usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf);
696 }
697 }
698
699 usbh_endpoint_desc_parse (pep, (uint8_t *)pdesc);
700 prev_ep_size = SWAPBYTE((uint8_t *)pdesc + 4);
701 ep_ix++;
702 }
703 }
704 }
705 }
706 }
707 }
708 }
709
710 prev_ep_size = 0U;
711 prev_itf = 0U;
712 }
713 }
usb_descriptor_configuration_struct::bmAttributes
uint8_t bmAttributes
Definition: usb_std.h:153
usb_descriptor_configuration_struct::wTotalLength
uint16_t wTotalLength
Definition: usb_std.h:149
usb_descriptor_configuration_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:147
usbh_endpoint_desc_parse
void usbh_endpoint_desc_parse(usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf)
parse the endpoint descriptor
Definition: usbh_std.c:742
usb_descriptor_interface_struct::bNumEndpoints
uint8_t bNumEndpoints
Definition: usb_std.h:163
USB_CFG_DESC_LEN
#define USB_CFG_DESC_LEN
Definition: usb_std.h:19
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usb_std.h:123
usb_descriptor_interface_struct
Definition: usb_std.h:157
usb_descriptor_header_struct
Definition: usb_std.h:121
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usb_std.h:85
usbh_interface_desc_parse
void usbh_interface_desc_parse(usb_descriptor_interface_struct *itf_desc, uint8_t *buf)
parse the interface descriptor
Definition: usbh_std.c:722
usb_descriptor_configuration_struct::bConfigurationValue
uint8_t bConfigurationValue
Definition: usb_std.h:151
usb_descriptor_endpoint_struct
Definition: usb_std.h:170
USB_DESCTYPE_INTERFACE
#define USB_DESCTYPE_INTERFACE
Definition: usb_std.h:58
usbh_next_desc_get
usb_descriptor_header_struct * usbh_next_desc_get(uint8_t *pbuf, uint16_t *ptr)
get the next descriptor header
Definition: usbh_std.c:795
usb_descriptor_configuration_struct::bNumInterfaces
uint8_t bNumInterfaces
Definition: usb_std.h:150
USB_CFGDESC_SIZE
#define USB_CFGDESC_SIZE
Definition: usb_std.h:68
NULL
#define NULL
Definition: usb_defines.h:18
usb_descriptor_configuration_struct::iConfiguration
uint8_t iConfiguration
Definition: usb_std.h:152
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usb_std.h:124
usb_descriptor_configuration_struct::bMaxPower
uint8_t bMaxPower
Definition: usb_std.h:154
USB_DESCTYPE_ENDPOINT
#define USB_DESCTYPE_ENDPOINT
Definition: usb_std.h:59
void usbh_device_desc_parse | ( | usb_descriptor_device_struct * | dev_desc,
 |  | uint8_t * | buf,
 |  | uint16_t | len
 | ) |  |

parse the device descriptor

Parameters
[in] | dev_desc | device_descriptor destinaton address
[in] | buf | buffer where the source descriptor is available
[in] | len | length of the descriptor
[out] | none
Return values
none

Definition at line 605 of file usbh_std.c.

606 {
607 dev_desc->Header.bLength = *(uint8_t *)(buf + 0);
608 dev_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
609 dev_desc->bcdUSB = SWAPBYTE(buf + 2);
610 dev_desc->bDeviceClass = *(uint8_t *)(buf + 4);
611 dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5);
612 dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6);
613 dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7);
614
615 if (len > 8U){
616 /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */
617 dev_desc->idVendor = SWAPBYTE(buf + 8);
618 dev_desc->idProduct = SWAPBYTE(buf + 10);
619 dev_desc->bcdDevice = SWAPBYTE(buf + 12);
620 dev_desc->iManufacturer = *(uint8_t *)(buf + 14);
621 dev_desc->iProduct = *(uint8_t *)(buf + 15);
622 dev_desc->iSerialNumber = *(uint8_t *)(buf + 16);
623 dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17);
624 }
625 }
usb_descriptor_device_struct::idProduct
uint16_t idProduct
Definition: usb_std.h:137
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usb_std.h:123
usb_descriptor_device_struct::bcdUSB
uint16_t bcdUSB
Definition: usb_std.h:131
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usb_std.h:85
usb_descriptor_device_struct::bDeviceProtocol
uint8_t bDeviceProtocol
Definition: usb_std.h:134
usb_descriptor_device_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:129
usb_descriptor_device_struct::bcdDevice
uint16_t bcdDevice
Definition: usb_std.h:138
usb_descriptor_device_struct::bDeviceSubClass
uint8_t bDeviceSubClass
Definition: usb_std.h:133
usb_descriptor_device_struct::bNumberConfigurations
uint8_t bNumberConfigurations
Definition: usb_std.h:142
usb_descriptor_device_struct::idVendor
uint16_t idVendor
Definition: usb_std.h:136
usb_descriptor_device_struct::iProduct
uint8_t iProduct
Definition: usb_std.h:140
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usb_std.h:124
usb_descriptor_device_struct::bDeviceClass
uint8_t bDeviceClass
Definition: usb_std.h:132
usb_descriptor_device_struct::bMaxPacketSize0
uint8_t bMaxPacketSize0
Definition: usb_std.h:135
usb_descriptor_device_struct::iManufacturer
uint8_t iManufacturer
Definition: usb_std.h:139
usb_descriptor_device_struct::iSerialNumber
uint8_t iSerialNumber
Definition: usb_std.h:141
void usbh_endpoint_desc_parse | ( | usb_descriptor_endpoint_struct * | ep_desc,
 |  | uint8_t * | buf
 | ) |  |

parse the endpoint descriptor

Parameters
[in] | ep_desc | endpoint descriptor destination address
[in] | buf | buffer where the parsed descriptor stored
[out] | none
Return values
none

Definition at line 742 of file usbh_std.c.

743 {
744 ep_desc->Header.bLength = *(uint8_t *)(buf + 0);
745 ep_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
746 ep_desc->bEndpointAddress = *(uint8_t *)(buf + 2);
747 ep_desc->bmAttributes = *(uint8_t *)(buf + 3);
748 ep_desc->wMaxPacketSize = SWAPBYTE(buf + 4);
749 ep_desc->bInterval = *(uint8_t *)(buf + 6);
750 }
usb_descriptor_endpoint_struct::bmAttributes
uint8_t bmAttributes
Definition: usb_std.h:175
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usb_std.h:123
usb_descriptor_endpoint_struct::bEndpointAddress
uint8_t bEndpointAddress
Definition: usb_std.h:174
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usb_std.h:85
usb_descriptor_endpoint_struct::wMaxPacketSize
uint16_t wMaxPacketSize
Definition: usb_std.h:176
usb_descriptor_endpoint_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:172
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usb_std.h:124
usb_descriptor_endpoint_struct::bInterval
uint8_t bInterval
Definition: usb_std.h:177
void usbh_enum_addr_set | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | uint8_t | device_address
 | ) |  |

set address in usb host enumeration stage

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | device_address | the device address
[out] | none
Return values
none

Definition at line 559 of file usbh_std.c.

562 {
563 usb_setup_union *p_setup = &(puhost->control.setup);
564
565 p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ;
566 p_setup->b.bRequest = USBREQ_SET_ADDRESS;
567 p_setup->b.wValue = (uint16_t)device_address;
568 p_setup->b.wIndex = 0U;
569 p_setup->b.wLength = 0U;
570 puhost->control.buff = 0U;
571 puhost->control.length = 0U;
572 }
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:116
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usb_std.h:30
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:113
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:133
usb_setup_union
Definition: usb_std.h:107
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:117
USB_DIR_OUT
#define USB_DIR_OUT
Definition: usb_std.h:26
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:115
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:131
USB_REQTYPE_DEVICE
#define USB_REQTYPE_DEVICE
Definition: usb_std.h:36
USBREQ_SET_ADDRESS
#define USBREQ_SET_ADDRESS
Definition: usb_std.h:45
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:114
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:191
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:134
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
void usbh_enum_cfg_set | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | uint16_t | cfg_idx
 | ) |  |

set configuration in usb host enumeration stage

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | cfg_idx | the index of the configuration
[out] | none
Return values
none

Definition at line 582 of file usbh_std.c.

585 {
586 usb_setup_union *p_setup = &(puhost->control.setup);
587
588 p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ;
589 p_setup->b.bRequest = USBREQ_SET_CONFIGURATION;
590 p_setup->b.wValue = cfg_idx;
591 p_setup->b.wIndex = 0U;
592 p_setup->b.wLength = 0U;
593 puhost->control.buff = 0;
594 puhost->control.length = 0U;
595 }
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:116
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usb_std.h:30
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:113
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:133
usb_setup_union
Definition: usb_std.h:107
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:117
USB_DIR_OUT
#define USB_DIR_OUT
Definition: usb_std.h:26
USBREQ_SET_CONFIGURATION
#define USBREQ_SET_CONFIGURATION
Definition: usb_std.h:49
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:115
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:131
USB_REQTYPE_DEVICE
#define USB_REQTYPE_DEVICE
Definition: usb_std.h:36
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:114
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:191
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:134
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
void usbh_enum_desc_get | ( | usb_core_handle_struct * | pudev,
 |  | usbh_host_struct * | puhost,
 |  | uint8_t * | buf,
 |  | uint8_t | req_type,
 |  | uint16_t | value_idx,
 |  | uint16_t | len
 | ) |  |

get descriptor in usb host enumeration stage

Parameters
[in] | pudev | pointer to USB device
[in] | puhost | pointer to USB host
[in] | buf | buffer to store the descriptor
[in] | ReqType | descriptor type
[in] | ValueIdx | wValue for the GetDescriptr request
[in] | Len | length of the descriptor
[out] | none
Return values
none

Definition at line 525 of file usbh_std.c.

531 {
532 usb_setup_union *pSetup = &(puhost->control.setup);
533
534 pSetup->b.bmRequestType = USB_DIR_IN | req_type;
535 pSetup->b.bRequest = USBREQ_GET_DESCRIPTOR;
536 pSetup->b.wValue = value_idx;
537
538 if (USB_STRDESC == (value_idx & 0xff00U)){
539 pSetup->b.wIndex = 0x0409U;
540 } else {
541 pSetup->b.wIndex = 0U;
542 }
543
544 pSetup->b.wLength = len;
545
546 puhost->control.buff = buf;
547 puhost->control.length = len;
548
549 }
USB_STRDESC
#define USB_STRDESC
Definition: usb_std.h:76
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:116
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:113
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:133
USBREQ_GET_DESCRIPTOR
#define USBREQ_GET_DESCRIPTOR
Definition: usb_std.h:46
usb_setup_union
Definition: usb_std.h:107
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:117
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:115
USB_DIR_IN
#define USB_DIR_IN
Definition: usb_std.h:27
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:131
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:114
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:191
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:134
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
void usbh_interface_desc_parse | ( | usb_descriptor_interface_struct * | itf_desc,
 |  | uint8_t * | buf
 | ) |  |

parse the interface descriptor

Parameters
[in] | itf_desc | interface descriptor destination
[in] | buf | buffer where the descriptor data is available
[out] | none
Return values
none

Definition at line 722 of file usbh_std.c.

723 {
724 itf_desc->Header.bLength = *(uint8_t *)(buf + 0);
725 itf_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
726 itf_desc->bInterfaceNumber = *(uint8_t *)(buf + 2);
727 itf_desc->bAlternateSetting = *(uint8_t *)(buf + 3);
728 itf_desc->bNumEndpoints = *(uint8_t *)(buf + 4);
729 itf_desc->bInterfaceClass = *(uint8_t *)(buf + 5);
730 itf_desc->bInterfaceSubClass = *(uint8_t *)(buf + 6);
731 itf_desc->bInterfaceProtocol = *(uint8_t *)(buf + 7);
732 itf_desc->iInterface = *(uint8_t *)(buf + 8);
733 }
usb_descriptor_interface_struct::bInterfaceProtocol
uint8_t bInterfaceProtocol
Definition: usb_std.h:166
usb_descriptor_interface_struct::iInterface
uint8_t iInterface
Definition: usb_std.h:167
usb_descriptor_interface_struct::bNumEndpoints
uint8_t bNumEndpoints
Definition: usb_std.h:163
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usb_std.h:123
usb_descriptor_interface_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:159
usb_descriptor_interface_struct::bInterfaceClass
uint8_t bInterfaceClass
Definition: usb_std.h:164
usb_descriptor_interface_struct::bInterfaceSubClass
uint8_t bInterfaceSubClass
Definition: usb_std.h:165
usb_descriptor_interface_struct::bAlternateSetting
uint8_t bAlternateSetting
Definition: usb_std.h:162
usb_descriptor_interface_struct::bInterfaceNumber
uint8_t bInterfaceNumber
Definition: usb_std.h:161
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usb_std.h:124
usb_descriptor_header_struct* usbh_next_desc_get | ( | uint8_t * | pbuf,
 |  | uint16_t * | ptr
 | ) |  |

get the next descriptor header

Parameters
[in] | pbuf | pointer to buffer where the cfg descriptor is available
[in] | ptr | data popinter inside the configuration descriptor
[out] | none
Return values
next descriptor header

Definition at line 795 of file usbh_std.c.

796 {
797 uint8_t len = ((usb_descriptor_header_struct *)pbuf)->bLength;
798
799 usb_descriptor_header_struct *pnext;
800
801 *ptr += len;
802
803 pnext = (usb_descriptor_header_struct *)((uint8_t *)pbuf + len);
804
805 return(pnext);
806 }
usb_descriptor_header_struct
Definition: usb_std.h:121
void usbh_string_desc_parse | ( | uint8_t * | psrc,
 |  | uint8_t * | pdest,
 |  | uint16_t | len
 | ) |  |

parse the string descriptor

Parameters
[in] | psrc | source pointer containing the descriptor data
[in] | pdest | destination address pointer
[in] | len | length of the descriptor
[out] | none
Return values
none

Definition at line 760 of file usbh_std.c.

761 {
762 uint16_t strlength;
763 uint16_t idx;
764
765 /* the unicode string descriptor is not null-terminated. the string length is
766 computed by substracting two from the value of the first byte of the descriptor.
767 */
768
769 /* check which is lower size, the size of string or the length of bytes read from the device */
770
771 if (USB_DESCTYPE_STRING == psrc[1]){
772 /* make sure the descriptor is string type */
773
774 /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */
775 strlength = ((((uint16_t)psrc[0] - 2U) <= len) ? ((uint16_t)psrc[0] - 2U) : len);
776 psrc += 2; /* adjust the offset ignoring the string len and descriptor type */
777
778 for (idx = 0U; idx < strlength; idx += 2U) {
779 /* copy only the string and ignore the unicode id, hence add the src */
780 *pdest = psrc[idx];
781 pdest++;
782 }
783
784 *pdest = 0U; /* mark end of string */
785 }
786 }
USB_DESCTYPE_STRING
#define USB_DESCTYPE_STRING
Definition: usb_std.h:57

Variable Documentation

state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]
Initial value:
=
{
{ENUM_IDLE, ENUM_EVENT_SET_ADDR, ENUM_SET_ADDR, only_state_move },
{ENUM_SET_ADDR, ENUN_EVENT_GET_FULL_DEV_DESC, ENUM_GET_FULL_DEV_DESC, only_state_move },
{ENUM_GET_FULL_DEV_DESC, ENUN_EVENT_GET_CFG_DESC, ENUM_GET_CFG_DESC, only_state_move },
{ENUM_GET_CFG_DESC, ENUN_EVENT_GET_FULL_CFG_DESC, ENUM_GET_FULL_CFG_DESC, only_state_move },
{ENUM_GET_FULL_CFG_DESC, ENUN_EVENT_GET_MFC_STRING_DESC, ENUM_GET_MFC_STRING_DESC, only_state_move },
{ENUM_GET_MFC_STRING_DESC, ENUN_EVENT_GET_PRODUCT_STRING_DESC, ENUM_GET_PRODUCT_STRING_DESC, only_state_move },
{ENUM_GET_PRODUCT_STRING_DESC, ENUN_EVENT_GET_SERIALNUM_STRING_DESC, ENUM_GET_SERIALNUM_STRING_DESC, only_state_move },
{ENUM_GET_SERIALNUM_STRING_DESC, ENUN_EVENT_SET_CONFIGURATION, ENUM_SET_CONFIGURATION, only_state_move },
{ENUM_SET_CONFIGURATION, ENUN_EVENT_DEV_CONFIGURED, ENUM_DEV_CONFIGURED, only_state_move },
{ENUM_DEV_CONFIGURED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
}
ENUM_DEV_CONFIGURED
Definition: usbh_core.h:90
goto_up_state_fun
usbh_status_enum goto_up_state_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state
Definition: usbh_core.c:705
ENUN_EVENT_GET_SERIALNUM_STRING_DESC
Definition: usbh_std.h:38
ENUN_EVENT_DEV_CONFIGURED
Definition: usbh_std.h:40
ENUM_IDLE
Definition: usbh_core.h:81
ENUN_EVENT_SET_CONFIGURATION
Definition: usbh_std.h:39
ENUM_GET_PRODUCT_STRING_DESC
Definition: usbh_core.h:87
ENUM_GET_CFG_DESC
Definition: usbh_core.h:84
ENUN_EVENT_GET_PRODUCT_STRING_DESC
Definition: usbh_std.h:37
ENUN_EVENT_GET_CFG_DESC
Definition: usbh_std.h:34
ENUN_EVENT_GET_FULL_CFG_DESC
Definition: usbh_std.h:35
ENUN_EVENT_GET_MFC_STRING_DESC
Definition: usbh_std.h:36
UP_STATE
#define UP_STATE
Definition: usbh_core.h:45
GO_TO_UP_STATE_EVENT
#define GO_TO_UP_STATE_EVENT
Definition: usbh_core.h:46
ENUN_EVENT_GET_FULL_DEV_DESC
Definition: usbh_std.h:33
ENUM_SET_ADDR
Definition: usbh_core.h:82
ENUM_SET_CONFIGURATION
Definition: usbh_core.h:89
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:692
ENUM_GET_FULL_CFG_DESC
Definition: usbh_core.h:85
ENUM_GET_FULL_DEV_DESC
Definition: usbh_core.h:83
ENUM_EVENT_SET_ADDR
Definition: usbh_std.h:32
ENUM_GET_MFC_STRING_DESC
Definition: usbh_core.h:86
ENUM_GET_SERIALNUM_STRING_DESC
Definition: usbh_core.h:88

Definition at line 48 of file usbh_std.c.

uint8_t enum_polling_handle_flag = 0U

Definition at line 19 of file usbh_std.c.

void(* enum_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Initial value:
=
{
enum_idle_handle,
enum_set_addr_handle,
enum_get_full_dev_desc_handle,
enum_get_cfg_desc_handle,
enum_get_full_cfg_desc_handle,
enum_get_mfc_string_desc_handle,
enum_get_product_string_desc_handle,
enum_get_serialnum_string_desc_handle,
enum_set_configuration_handle,
enum_dev_configured_handle,
}

Definition at line 33 of file usbh_std.c.

uint8_t local_buffer[64]

Definition at line 17 of file usbh_std.c.

uint8_t usbh_cfg_desc[512]

Definition at line 18 of file usbh_std.c.


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • u
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __HXTAL : system_gd32f3x0.c
  • __IRC8M : system_gd32f3x0.c
  • __SYS_OSC_CLK : system_gd32f3x0.c
  • _WIDE_STRING : usbd_std.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
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  • f
  • g
  • h
  • i
  • l
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  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • ACT_FUN : usbh_core.h
  • ADC : gd32f3x0_adc.h
  • adc_calibration_enable() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • ADC_CHANNEL_0 : gd32f3x0_adc.h
  • ADC_CHANNEL_1 : gd32f3x0_adc.h
  • ADC_CHANNEL_10 : gd32f3x0_adc.h
  • ADC_CHANNEL_11 : gd32f3x0_adc.h
  • ADC_CHANNEL_12 : gd32f3x0_adc.h
  • ADC_CHANNEL_13 : gd32f3x0_adc.h
  • ADC_CHANNEL_14 : gd32f3x0_adc.h
  • ADC_CHANNEL_15 : gd32f3x0_adc.h
  • ADC_CHANNEL_16 : gd32f3x0_adc.h
  • ADC_CHANNEL_17 : gd32f3x0_adc.h
  • ADC_CHANNEL_18 : gd32f3x0_adc.h
  • ADC_CHANNEL_2 : gd32f3x0_adc.h
  • ADC_CHANNEL_3 : gd32f3x0_adc.h
  • ADC_CHANNEL_4 : gd32f3x0_adc.h
  • ADC_CHANNEL_5 : gd32f3x0_adc.h
  • ADC_CHANNEL_6 : gd32f3x0_adc.h
  • ADC_CHANNEL_7 : gd32f3x0_adc.h
  • ADC_CHANNEL_8 : gd32f3x0_adc.h
  • ADC_CHANNEL_9 : gd32f3x0_adc.h
  • ADC_CHANNEL_DISCON_DISABLE : gd32f3x0_adc.h
  • adc_channel_length_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • ADC_CONTINUOUS_MODE : gd32f3x0_adc.h
  • ADC_CTL0 : gd32f3x0_adc.h
  • ADC_CTL0_DISIC : gd32f3x0_adc.h
  • ADC_CTL0_DISNUM : gd32f3x0_adc.h
  • ADC_CTL0_DISRC : gd32f3x0_adc.h
  • ADC_CTL0_DRES : gd32f3x0_adc.h
  • ADC_CTL0_EOCIE : gd32f3x0_adc.h
  • ADC_CTL0_EOICIE : gd32f3x0_adc.h
  • ADC_CTL0_ICA : gd32f3x0_adc.h
  • ADC_CTL0_IWDEN : gd32f3x0_adc.h
  • ADC_CTL0_RWDEN : gd32f3x0_adc.h
  • ADC_CTL0_SM : gd32f3x0_adc.h
  • ADC_CTL0_WDCHSEL : gd32f3x0_adc.h
  • ADC_CTL0_WDEIE : gd32f3x0_adc.h
  • ADC_CTL0_WDSC : gd32f3x0_adc.h
  • ADC_CTL1 : gd32f3x0_adc.h
  • ADC_CTL1_ADCON : gd32f3x0_adc.h
  • ADC_CTL1_CLB : gd32f3x0_adc.h
  • ADC_CTL1_CTN : gd32f3x0_adc.h
  • ADC_CTL1_DAL : gd32f3x0_adc.h
  • ADC_CTL1_DMA : gd32f3x0_adc.h
  • ADC_CTL1_ETEIC : gd32f3x0_adc.h
  • ADC_CTL1_ETERC : gd32f3x0_adc.h
  • ADC_CTL1_ETSIC : gd32f3x0_adc.h
  • ADC_CTL1_ETSRC : gd32f3x0_adc.h
  • ADC_CTL1_RSTCLB : gd32f3x0_adc.h
  • ADC_CTL1_SWICST : gd32f3x0_adc.h
  • ADC_CTL1_SWRCST : gd32f3x0_adc.h
  • ADC_CTL1_TSVREN : gd32f3x0_adc.h
  • ADC_CTL1_VBETEN : gd32f3x0_adc.h
  • adc_data_alignment_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • ADC_DATAALIGN_LEFT : gd32f3x0_adc.h
  • ADC_DATAALIGN_RIGHT : gd32f3x0_adc.h
  • adc_deinit() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_disable() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • adc_discontinuous_mode_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_dma_mode_disable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_dma_mode_enable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_enable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_external_trigger_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_external_trigger_source_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • ADC_EXTTRIG_INSERTED_EXTI_15 : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_NONE : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_T0_CH3 : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_T0_TRGO : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_T14_TRGO : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_T1_CH0 : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_T1_TRGO : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_T2_CH3 : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_EXTI_11 : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_NONE : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_T0_CH0 : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_T0_CH1 : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_T0_CH2 : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_T14_CH1 : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_T1_CH1 : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_T2_TRGO : gd32f3x0_adc.h
  • adc_flag_clear() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • ADC_FLAG_EOC : gd32f3x0_adc.h
  • ADC_FLAG_EOIC : gd32f3x0_adc.h
  • adc_flag_get() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • ADC_FLAG_STIC : gd32f3x0_adc.h
  • ADC_FLAG_STRC : gd32f3x0_adc.h
  • ADC_FLAG_WDE : gd32f3x0_adc.h
  • ADC_IDATA0 : gd32f3x0_adc.h
  • ADC_IDATA1 : gd32f3x0_adc.h
  • ADC_IDATA2 : gd32f3x0_adc.h
  • ADC_IDATA3 : gd32f3x0_adc.h
  • ADC_IDATAX_IDATAN : gd32f3x0_adc.h
  • ADC_INSERTED_CHANNEL : gd32f3x0_adc.h
  • ADC_INSERTED_CHANNEL_0 : gd32f3x0_adc.h
  • ADC_INSERTED_CHANNEL_1 : gd32f3x0_adc.h
  • ADC_INSERTED_CHANNEL_2 : gd32f3x0_adc.h
  • ADC_INSERTED_CHANNEL_3 : gd32f3x0_adc.h
  • ADC_INSERTED_CHANNEL_AUTO : gd32f3x0_adc.h
  • adc_inserted_channel_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_inserted_channel_offset_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_inserted_data_read() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • ADC_INT_EOC : gd32f3x0_adc.h
  • ADC_INT_EOIC : gd32f3x0_adc.h
  • ADC_INT_FLAG_EOC : gd32f3x0_adc.h
  • ADC_INT_FLAG_EOIC : gd32f3x0_adc.h
  • ADC_INT_FLAG_WDE : gd32f3x0_adc.h
  • ADC_INT_WDE : gd32f3x0_adc.h
  • adc_interrupt_disable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_interrupt_enable() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • adc_interrupt_flag_clear() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_interrupt_flag_get() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • ADC_IOFF0 : gd32f3x0_adc.h
  • ADC_IOFF1 : gd32f3x0_adc.h
  • ADC_IOFF2 : gd32f3x0_adc.h
  • ADC_IOFF3 : gd32f3x0_adc.h
  • ADC_IOFFX_IOFF : gd32f3x0_adc.h
  • ADC_ISQ : gd32f3x0_adc.h
  • ADC_ISQ_IL : gd32f3x0_adc.h
  • ADC_ISQ_ISQN : gd32f3x0_adc.h
  • adc_oversample_mode_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_oversample_mode_disable() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • adc_oversample_mode_enable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • ADC_OVERSAMPLING_ALL_CONVERT : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_ONE_CONVERT : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL128 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL16 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL2 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL256 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL32 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL4 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL64 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL8 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_1B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_2B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_3B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_4B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_5B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_6B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_7B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_8B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_NONE : gd32f3x0_adc.h
  • ADC_OVSAMPCTL : gd32f3x0_adc.h
  • ADC_OVSAMPCTL_OVSEN : gd32f3x0_adc.h
  • ADC_OVSAMPCTL_OVSR : gd32f3x0_adc.h
  • ADC_OVSAMPCTL_OVSS : gd32f3x0_adc.h
  • ADC_OVSAMPCTL_TOVS : gd32f3x0_adc.h
  • ADC_RDATA : gd32f3x0_adc.h
  • ADC_RDATA_RDATA : gd32f3x0_adc.h
  • ADC_REGULAR_CHANNEL : gd32f3x0_adc.h
  • adc_regular_channel_config() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • adc_regular_data_read() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • ADC_REGULAR_INSERTED_CHANNEL : gd32f3x0_adc.h
  • ADC_RESOLUTION_10B : gd32f3x0_adc.h
  • ADC_RESOLUTION_12B : gd32f3x0_adc.h
  • ADC_RESOLUTION_6B : gd32f3x0_adc.h
  • ADC_RESOLUTION_8B : gd32f3x0_adc.h
  • adc_resolution_config() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • ADC_RSQ0 : gd32f3x0_adc.h
  • ADC_RSQ0_RL : gd32f3x0_adc.h
  • ADC_RSQ1 : gd32f3x0_adc.h
  • ADC_RSQ2 : gd32f3x0_adc.h
  • ADC_RSQX_RSQN : gd32f3x0_adc.h
  • ADC_SAMPLETIME_13POINT5 : gd32f3x0_adc.h
  • ADC_SAMPLETIME_1POINT5 : gd32f3x0_adc.h
  • ADC_SAMPLETIME_239POINT5 : gd32f3x0_adc.h
  • ADC_SAMPLETIME_28POINT5 : gd32f3x0_adc.h
  • ADC_SAMPLETIME_41POINT5 : gd32f3x0_adc.h
  • ADC_SAMPLETIME_55POINT5 : gd32f3x0_adc.h
  • ADC_SAMPLETIME_71POINT5 : gd32f3x0_adc.h
  • ADC_SAMPLETIME_7POINT5 : gd32f3x0_adc.h
  • ADC_SAMPT0 : gd32f3x0_adc.h
  • ADC_SAMPT1 : gd32f3x0_adc.h
  • ADC_SAMPTX_SPTN : gd32f3x0_adc.h
  • ADC_SCAN_MODE : gd32f3x0_adc.h
  • adc_software_trigger_enable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_special_function_config() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • ADC_STAT : gd32f3x0_adc.h
  • ADC_STAT_EOC : gd32f3x0_adc.h
  • ADC_STAT_EOIC : gd32f3x0_adc.h
  • ADC_STAT_STIC : gd32f3x0_adc.h
  • ADC_STAT_STRC : gd32f3x0_adc.h
  • ADC_STAT_WDE : gd32f3x0_adc.h
  • adc_tempsensor_vrefint_disable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_tempsensor_vrefint_enable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_vbat_disable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_vbat_enable() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • adc_watchdog_disable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_watchdog_group_channel_enable() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • adc_watchdog_single_channel_enable() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • adc_watchdog_threshold_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • ADC_WDHT : gd32f3x0_adc.h
  • ADC_WDHT_WDHT : gd32f3x0_adc.h
  • ADC_WDLT : gd32f3x0_adc.h
  • ADC_WDLT_WDLT : gd32f3x0_adc.h
  • AF : gd32f3x0_gpio.h
  • ALRM0SS_MASKSSC : gd32f3x0_rtc.h
  • ALRM0SS_SSC : gd32f3x0_rtc.h
  • ALRM0TD_DAY : gd32f3x0_rtc.h
  • ALRM0TD_HR : gd32f3x0_rtc.h
  • ALRM0TD_MN : gd32f3x0_rtc.h
  • ALRM0TD_SC : gd32f3x0_rtc.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BDCTL_LXTALDRI : gd32f3x0_rcu.h
  • BDCTL_RTCSRC : gd32f3x0_rcu.h
  • bit_status : gd32f3x0_gpio.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CBI_PROTOCOL : usbh_core.h
  • CCHP_PROT : gd32f3x0_timer.h
  • CFG0_ADCPSC : gd32f3x0_rcu.h
  • CFG0_AHBPSC : gd32f3x0_rcu.h
  • CFG0_APB1PSC : gd32f3x0_rcu.h
  • CFG0_APB2PSC : gd32f3x0_rcu.h
  • CFG0_CKOUTDIV : gd32f3x0_rcu.h
  • CFG0_CKOUTSEL : gd32f3x0_rcu.h
  • CFG0_PLLMF : gd32f3x0_rcu.h
  • CFG0_SCS : gd32f3x0_rcu.h
  • CFG0_SCSS : gd32f3x0_rcu.h
  • CFG0_USBFSPSC : gd32f3x0_rcu.h
  • CFG1_PREDV : gd32f3x0_rcu.h
  • CFG2_USART0SEL : gd32f3x0_rcu.h
  • CFG_PSC : gd32f3x0_wwdgt.h
  • CFG_WIN : gd32f3x0_wwdgt.h
  • CHCTL_MWIDTH : gd32f3x0_dma.h
  • CHCTL_PRIO : gd32f3x0_dma.h
  • CHCTL_PWIDTH : gd32f3x0_dma.h
  • CHN_LANGID : usbd_std.h
  • CID_CID : usb_regs.h
  • CK_ADC : gd32f3x0_rcu.h
  • CK_AHB : gd32f3x0_rcu.h
  • CK_APB1 : gd32f3x0_rcu.h
  • CK_APB2 : gd32f3x0_rcu.h
  • CK_CEC : gd32f3x0_rcu.h
  • CK_SYS : gd32f3x0_rcu.h
  • CK_USART : gd32f3x0_rcu.h
  • CKCFG_DTCY : gd32f3x0_i2c.h
  • CLASS_FSM_ID : usbh_core.h
  • class_polling_cb : usbh_core.c
  • CLASS_REQ_FSM_ID : usbh_core.h
  • CMD_FSM_ID : usbh_core.h
  • CMP : gd32f3x0_cmp.h
  • CMP0 : gd32f3x0_cmp.h
  • CMP1 : gd32f3x0_cmp.h
  • CMP_1_2VREFINT : gd32f3x0_cmp.h
  • CMP_1_4VREFINT : gd32f3x0_cmp.h
  • CMP_3_4VREFINT : gd32f3x0_cmp.h
  • CMP_CS : gd32f3x0_cmp.h
  • CMP_CS_CMP0EN : gd32f3x0_cmp.h
  • CMP_CS_CMP0HST : gd32f3x0_cmp.h
  • CMP_CS_CMP0LK : gd32f3x0_cmp.h
  • CMP_CS_CMP0M : gd32f3x0_cmp.h
  • CMP_CS_CMP0MSEL : gd32f3x0_cmp.h
  • CMP_CS_CMP0O : gd32f3x0_cmp.h
  • CMP_CS_CMP0OSEL : gd32f3x0_cmp.h
  • CMP_CS_CMP0PL : gd32f3x0_cmp.h
  • CMP_CS_CMP0SW : gd32f3x0_cmp.h
  • CMP_CS_CMP1EN : gd32f3x0_cmp.h
  • CMP_CS_CMP1HST : gd32f3x0_cmp.h
  • CMP_CS_CMP1LK : gd32f3x0_cmp.h
  • CMP_CS_CMP1M : gd32f3x0_cmp.h
  • CMP_CS_CMP1MSEL : gd32f3x0_cmp.h
  • CMP_CS_CMP1O : gd32f3x0_cmp.h
  • CMP_CS_CMP1OSEL : gd32f3x0_cmp.h
  • CMP_CS_CMP1PL : gd32f3x0_cmp.h
  • CMP_CS_WNDEN : gd32f3x0_cmp.h
  • CMP_DAC : gd32f3x0_cmp.h
  • cmp_deinit() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_disable() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_enable() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • CMP_HIGHSPEED : gd32f3x0_cmp.h
  • cmp_hysteresis_enum : gd32f3x0_cmp.h
  • CMP_HYSTERESIS_HIGH : gd32f3x0_cmp.h
  • CMP_HYSTERESIS_LOW : gd32f3x0_cmp.h
  • CMP_HYSTERESIS_MIDDLE : gd32f3x0_cmp.h
  • CMP_HYSTERESIS_NO : gd32f3x0_cmp.h
  • cmp_lock_disable() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_lock_enable() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • CMP_LOWSPEED : gd32f3x0_cmp.h
  • CMP_MIDDLESPEED : gd32f3x0_cmp.h
  • cmp_mode_init() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_output_enum : gd32f3x0_cmp.h
  • cmp_output_init() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_output_level_get() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • CMP_OUTPUT_NONE : gd32f3x0_cmp.h
  • CMP_OUTPUT_POLARITY_INVERTED : gd32f3x0_cmp.h
  • CMP_OUTPUT_POLARITY_NOINVERTED : gd32f3x0_cmp.h
  • CMP_OUTPUT_TIMER0BKIN : gd32f3x0_cmp.h
  • CMP_OUTPUT_TIMER0IC0 : gd32f3x0_cmp.h
  • CMP_OUTPUT_TIMER0OCPRECLR : gd32f3x0_cmp.h
  • CMP_OUTPUT_TIMER1IC3 : gd32f3x0_cmp.h
  • CMP_OUTPUT_TIMER1OCPRECLR : gd32f3x0_cmp.h
  • CMP_OUTPUT_TIMER2IC0 : gd32f3x0_cmp.h
  • CMP_OUTPUT_TIMER2OCPRECLR : gd32f3x0_cmp.h
  • CMP_OUTPUTLEVEL_HIGH : gd32f3x0_cmp.h
  • CMP_OUTPUTLEVEL_LOW : gd32f3x0_cmp.h
  • CMP_PA5 : gd32f3x0_cmp.h
  • CMP_PA_0_2 : gd32f3x0_cmp.h
  • cmp_switch_disable() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_switch_enable() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • CMP_VERYLOWSPEED : gd32f3x0_cmp.h
  • CMP_VREFINT : gd32f3x0_cmp.h
  • cmp_window_disable() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_window_enable() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • CRC : gd32f3x0_crc.h
  • crc_block_data_calculate() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • CRC_CTL : gd32f3x0_crc.h
  • CRC_CTL_PS : gd32f3x0_crc.h
  • CRC_CTL_PS_16 : gd32f3x0_crc.h
  • CRC_CTL_PS_32 : gd32f3x0_crc.h
  • CRC_CTL_PS_7 : gd32f3x0_crc.h
  • CRC_CTL_PS_8 : gd32f3x0_crc.h
  • CRC_CTL_REV_I : gd32f3x0_crc.h
  • CRC_CTL_REV_O : gd32f3x0_crc.h
  • CRC_CTL_RST : gd32f3x0_crc.h
  • CRC_DATA : gd32f3x0_crc.h
  • CRC_DATA_DATA : gd32f3x0_crc.h
  • crc_data_register_read() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_data_register_reset() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_deinit() : gd32f3x0_crc.c , gd32f3x0_crc.h
  • CRC_FDATA : gd32f3x0_crc.h
  • CRC_FDATA_FDATA : gd32f3x0_crc.h
  • crc_free_data_register_read() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_free_data_register_write() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • CRC_IDATA : gd32f3x0_crc.h
  • CRC_IDATA_IDATA : gd32f3x0_crc.h
  • crc_init_data_register_write() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • CRC_INPUT_DATA_BYTE : gd32f3x0_crc.h
  • CRC_INPUT_DATA_HALFWORD : gd32f3x0_crc.h
  • CRC_INPUT_DATA_NOT : gd32f3x0_crc.h
  • crc_input_data_reverse_config() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • CRC_INPUT_DATA_WORD : gd32f3x0_crc.h
  • CRC_POLY : gd32f3x0_crc.h
  • CRC_POLY_POLY : gd32f3x0_crc.h
  • crc_polynomial_set() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_polynomial_size_set() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_reverse_output_data_disable() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_reverse_output_data_enable() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_single_data_calculate() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • CS_CMP0HST : gd32f3x0_cmp.h
  • CS_CMP0HST_HYSTERESIS_HIGH : gd32f3x0_cmp.h
  • CS_CMP0HST_HYSTERESIS_LOW : gd32f3x0_cmp.h
  • CS_CMP0HST_HYSTERESIS_MIDDLE : gd32f3x0_cmp.h
  • CS_CMP0HST_HYSTERESIS_NO : gd32f3x0_cmp.h
  • CS_CMP0M : gd32f3x0_cmp.h
  • CS_CMP0M_HIGHSPEED : gd32f3x0_cmp.h
  • CS_CMP0M_LOWSPEED : gd32f3x0_cmp.h
  • CS_CMP0M_MIDDLESPEED : gd32f3x0_cmp.h
  • CS_CMP0M_VERYLOWSPEED : gd32f3x0_cmp.h
  • CS_CMP0MSEL : gd32f3x0_cmp.h
  • CS_CMP0MSEL_1_2VREFINT : gd32f3x0_cmp.h
  • CS_CMP0MSEL_1_4VREFINT : gd32f3x0_cmp.h
  • CS_CMP0MSEL_3_4VREFINT : gd32f3x0_cmp.h
  • CS_CMP0MSEL_DAC : gd32f3x0_cmp.h
  • CS_CMP0MSEL_PA0 : gd32f3x0_cmp.h
  • CS_CMP0MSEL_PA5 : gd32f3x0_cmp.h
  • CS_CMP0MSEL_VREFINT : gd32f3x0_cmp.h
  • CS_CMP0OSEL : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_NONE : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_TIMER0BKIN : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_TIMER0IC0 : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_TIMER0OCPRECLR : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_TIMER1IC3 : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_TIMER1OCPRECLR : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_TIMER2IC0 : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_TIMER2OCPRECLR : gd32f3x0_cmp.h
  • CS_CMP1HST : gd32f3x0_cmp.h
  • CS_CMP1HST_HSTHYSTERESIS_NO : gd32f3x0_cmp.h
  • CS_CMP1HST_HYSTERESIS_HIGH : gd32f3x0_cmp.h
  • CS_CMP1HST_HYSTERESIS_LOW : gd32f3x0_cmp.h
  • CS_CMP1HST_HYSTERESIS_MIDDLE : gd32f3x0_cmp.h
  • CS_CMP1M : gd32f3x0_cmp.h
  • CS_CMP1M_HIGHSPEED : gd32f3x0_cmp.h
  • CS_CMP1M_LOWSPEED : gd32f3x0_cmp.h
  • CS_CMP1M_MIDDLESPEED : gd32f3x0_cmp.h
  • CS_CMP1M_VERYLOWSPEED : gd32f3x0_cmp.h
  • CS_CMP1MSEL : gd32f3x0_cmp.h
  • CS_CMP1MSEL_1_2VREFINT : gd32f3x0_cmp.h
  • CS_CMP1MSEL_1_4VREFINT : gd32f3x0_cmp.h
  • CS_CMP1MSEL_3_4VREFINT : gd32f3x0_cmp.h
  • CS_CMP1MSEL_DAC : gd32f3x0_cmp.h
  • CS_CMP1MSEL_PA2 : gd32f3x0_cmp.h
  • CS_CMP1MSEL_PA5 : gd32f3x0_cmp.h
  • CS_CMP1MSEL_VREFINT : gd32f3x0_cmp.h
  • CS_CMP1OSEL : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_NONE : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_TIMER0BKIN : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_TIMER0IC0 : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_TIMER0OCPRECLR : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_TIMER1IC3 : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_TIMER1OCPRECLR : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_TIMER2IC0 : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_TIMER2OCPRECLR : gd32f3x0_cmp.h
  • CS_LDRF : gd32f3x0_pmu.h
  • CTC : gd32f3x0_ctc.h
  • ctc_clock_limit_value_config() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_counter_capture_value_read() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_counter_direction_read() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_counter_disable() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_counter_enable() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_counter_reload_value_config() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_counter_reload_value_read() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • CTC_CTL0 : gd32f3x0_ctc.h
  • CTC_CTL0_AUTOTRIM : gd32f3x0_ctc.h
  • CTC_CTL0_CKOKIE : gd32f3x0_ctc.h
  • CTC_CTL0_CKWARNIE : gd32f3x0_ctc.h
  • CTC_CTL0_CNTEN : gd32f3x0_ctc.h
  • CTC_CTL0_EREFIE : gd32f3x0_ctc.h
  • CTC_CTL0_ERRIE : gd32f3x0_ctc.h
  • CTC_CTL0_SWREFPUL : gd32f3x0_ctc.h
  • CTC_CTL0_TRIMVALUE : gd32f3x0_ctc.h
  • CTC_CTL1 : gd32f3x0_ctc.h
  • CTC_CTL1_CKLIM : gd32f3x0_ctc.h
  • CTC_CTL1_REFPOL : gd32f3x0_ctc.h
  • CTC_CTL1_REFPSC : gd32f3x0_ctc.h
  • CTC_CTL1_REFSEL : gd32f3x0_ctc.h
  • CTC_CTL1_RLVALUE : gd32f3x0_ctc.h
  • ctc_deinit() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • CTC_FLAG_CKERR : gd32f3x0_ctc.h
  • CTC_FLAG_CKOK : gd32f3x0_ctc.h
  • CTC_FLAG_CKWARN : gd32f3x0_ctc.h
  • ctc_flag_clear() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • CTC_FLAG_EREF : gd32f3x0_ctc.h
  • CTC_FLAG_ERR : gd32f3x0_ctc.h
  • ctc_flag_get() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • CTC_FLAG_MASK : gd32f3x0_ctc.c
  • CTC_FLAG_REFMISS : gd32f3x0_ctc.h
  • CTC_FLAG_TRIMERR : gd32f3x0_ctc.h
  • ctc_hardware_trim_mode_config() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • CTC_HARDWARE_TRIM_MODE_DISABLE : gd32f3x0_ctc.h
  • CTC_HARDWARE_TRIM_MODE_ENABLE : gd32f3x0_ctc.h
  • CTC_INT_CKOK : gd32f3x0_ctc.h
  • CTC_INT_CKWARN : gd32f3x0_ctc.h
  • CTC_INT_EREF : gd32f3x0_ctc.h
  • CTC_INT_ERR : gd32f3x0_ctc.h
  • CTC_INT_FLAG_CKERR : gd32f3x0_ctc.h
  • CTC_INT_FLAG_CKOK : gd32f3x0_ctc.h
  • CTC_INT_FLAG_CKWARN : gd32f3x0_ctc.h
  • CTC_INT_FLAG_EREF : gd32f3x0_ctc.h
  • CTC_INT_FLAG_ERR : gd32f3x0_ctc.h
  • CTC_INT_FLAG_REFMISS : gd32f3x0_ctc.h
  • CTC_INT_FLAG_TRIMERR : gd32f3x0_ctc.h
  • CTC_INTC : gd32f3x0_ctc.h
  • CTC_INTC_CKOKIC : gd32f3x0_ctc.h
  • CTC_INTC_CKWARNIC : gd32f3x0_ctc.h
  • CTC_INTC_EREFIC : gd32f3x0_ctc.h
  • CTC_INTC_ERRIC : gd32f3x0_ctc.h
  • ctc_interrupt_disable() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_interrupt_enable() : gd32f3x0_ctc.c , gd32f3x0_ctc.h
  • ctc_interrupt_flag_clear() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_interrupt_flag_get() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_irc48m_trim_value_config() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_irc48m_trim_value_read() : gd32f3x0_ctc.c , gd32f3x0_ctc.h
  • CTC_REFSOURCE_GPIO : gd32f3x0_ctc.h
  • CTC_REFSOURCE_LXTAL : gd32f3x0_ctc.h
  • ctc_refsource_polarity_config() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • CTC_REFSOURCE_POLARITY_FALLING : gd32f3x0_ctc.h
  • CTC_REFSOURCE_POLARITY_RISING : gd32f3x0_ctc.h
  • ctc_refsource_prescaler_config() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • CTC_REFSOURCE_PSC_DIV128 : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_DIV16 : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_DIV2 : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_DIV32 : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_DIV4 : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_DIV64 : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_DIV8 : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_OFF : gd32f3x0_ctc.h
  • ctc_refsource_signal_select() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • CTC_REFSOURCE_USBSOF : gd32f3x0_ctc.h
  • ctc_software_refsource_pulse_generate() : gd32f3x0_ctc.c , gd32f3x0_ctc.h
  • CTC_STAT : gd32f3x0_ctc.h
  • CTC_STAT_CKERR : gd32f3x0_ctc.h
  • CTC_STAT_CKOKIF : gd32f3x0_ctc.h
  • CTC_STAT_CKWARNIF : gd32f3x0_ctc.h
  • CTC_STAT_EREFIF : gd32f3x0_ctc.h
  • CTC_STAT_ERRIF : gd32f3x0_ctc.h
  • CTC_STAT_REFCAP : gd32f3x0_ctc.h
  • CTC_STAT_REFDIR : gd32f3x0_ctc.h
  • CTC_STAT_REFMISS : gd32f3x0_ctc.h
  • CTC_STAT_TRIMERR : gd32f3x0_ctc.h
  • CTL0_CAM : gd32f3x0_timer.h
  • CTL0_CKDIV : gd32f3x0_timer.h
  • CTL0_DISNUM : gd32f3x0_adc.h
  • CTL0_DRES : gd32f3x0_adc.h
  • CTL0_OVSMOD : gd32f3x0_usart.h
  • CTL0_PM : gd32f3x0_usart.h
  • CTL0_PSC : gd32f3x0_spi.h
  • CTL0_REN : gd32f3x0_usart.h
  • CTL0_TEN : gd32f3x0_usart.h
  • CTL0_TRIMVALUE : gd32f3x0_ctc.h
  • CTL0_WL : gd32f3x0_usart.h
  • CTL0_WM : gd32f3x0_usart.h
  • CTL1_ABDM : gd32f3x0_usart.h
  • CTL1_ADDM : gd32f3x0_usart.h
  • CTL1_CKLIM : gd32f3x0_ctc.h
  • CTL1_CLEN : gd32f3x0_usart.h
  • CTL1_CPH : gd32f3x0_usart.h
  • CTL1_CPL : gd32f3x0_usart.h
  • CTL1_ETSIC : gd32f3x0_adc.h
  • CTL1_ETSRC : gd32f3x0_adc.h
  • CTL1_LBLEN : gd32f3x0_usart.h
  • CTL1_MMC : gd32f3x0_timer.h
  • CTL1_MSBF : gd32f3x0_usart.h
  • CTL1_REFPSC : gd32f3x0_ctc.h
  • CTL1_REFSEL : gd32f3x0_ctc.h
  • CTL1_STB : gd32f3x0_usart.h
  • CTL2_CTSEN : gd32f3x0_usart.h
  • CTL2_DENR : gd32f3x0_usart.h
  • CTL2_DENT : gd32f3x0_usart.h
  • CTL2_DEP : gd32f3x0_usart.h
  • CTL2_IRLP : gd32f3x0_usart.h
  • CTL2_OSB : gd32f3x0_usart.h
  • CTL2_RTSEN : gd32f3x0_usart.h
  • CTL2_WUM : gd32f3x0_usart.h
  • CTL_CDT : gd32f3x0_tsi.h
  • CTL_CLTR : gd32f3x0_gpio.h
  • CTL_CMD : gd32f3x0_fwdgt.h
  • CTL_CNT : gd32f3x0_wwdgt.h
  • CTL_CTDT : gd32f3x0_tsi.h
  • CTL_LDEN : gd32f3x0_pmu.h
  • CTL_LDOVS : gd32f3x0_pmu.h
  • CTL_LVDT : gd32f3x0_pmu.h
  • CTL_MCN : gd32f3x0_tsi.h
  • CTL_OS : gd32f3x0_rtc.h
  • CTL_PS : gd32f3x0_crc.h
  • CTL_REV_I : gd32f3x0_crc.h
  • CTRL_COMPLETE : usbh_core.h
  • CTRL_DATA : usbh_core.h
  • ctrl_data_wait_flag : usbh_ctrl.c
  • CTRL_ERROR : usbh_core.h
  • CTRL_EVENT_COMPLETE : usbh_ctrl.h
  • CTRL_EVENT_DATA : usbh_ctrl.h
  • ctrl_event_enum : usbh_ctrl.h
  • CTRL_EVENT_ERROR : usbh_ctrl.h
  • CTRL_EVENT_IDLE : usbh_ctrl.h
  • CTRL_EVENT_SETUP : usbh_ctrl.h
  • CTRL_EVENT_STALLED : usbh_ctrl.h
  • CTRL_EVENT_STATUS : usbh_ctrl.h
  • CTRL_FSM_ID : usbh_core.h
  • ctrl_handle_table : usbh_ctrl.c , usbh_ctrl.h
  • CTRL_HANDLE_TABLE_SIZE : usbh_ctrl.h
  • CTRL_IDLE : usbh_core.h
  • ctrl_polling_handle_flag : usbh_ctrl.c , usbh_ctrl.h
  • CTRL_SETUP : usbh_core.h
  • ctrl_setup_wait_flag : usbh_ctrl.c
  • CTRL_STALLED : usbh_core.h
  • ctrl_state_enum : usbh_core.h
  • ctrl_state_handle : usbh_ctrl.c
  • ctrl_state_polling_fun() : usbh_ctrl.c , usbh_ctrl.h
  • CTRL_STATUS : usbh_core.h
  • ctrl_status_wait_flag : usbh_ctrl.c


GD32F3x0_Firmware_Library: Globals

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  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DAEPINT_IEPITB : usb_regs.h
  • DAEPINT_OEPITB : usb_regs.h
  • DAEPINTEN_IEPIE : usb_regs.h
  • DAEPINTEN_OEPIE : usb_regs.h
  • DATA_RECV : gd32f3x0_i2c.h
  • DATA_STAGE_TIMEOUT : usb_std.h
  • DATA_TRANS : gd32f3x0_i2c.h
  • DATE_DAY : gd32f3x0_rtc.h
  • DATE_DOW : gd32f3x0_rtc.h
  • DATE_MON : gd32f3x0_rtc.h
  • DATE_YR : gd32f3x0_rtc.h
  • DBG : gd32f3x0_dbg.h
  • DBG_BIT_POS : gd32f3x0_dbg.h
  • DBG_CTL0 : gd32f3x0_dbg.h
  • DBG_CTL0_DSLP_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_FWDGT_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_I2C0_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_I2C1_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_I2C2_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_SLP_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_STB_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_TIMER0_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_TIMER13_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_TIMER1_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_TIMER2_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_WWDGT_HOLD : gd32f3x0_dbg.h
  • DBG_CTL1 : gd32f3x0_dbg.h
  • DBG_CTL1_RTC_HOLD : gd32f3x0_dbg.h
  • DBG_CTL1_TIMER14_HOLD : gd32f3x0_dbg.h
  • DBG_CTL1_TIMER15_HOLD : gd32f3x0_dbg.h
  • DBG_CTL1_TIMER16_HOLD : gd32f3x0_dbg.h
  • dbg_deinit() : gd32f3x0_dbg.h , gd32f3x0_dbg.c
  • DBG_FWDGT_HOLD : gd32f3x0_dbg.h
  • DBG_I2C0_HOLD : gd32f3x0_dbg.h
  • DBG_I2C1_HOLD : gd32f3x0_dbg.h
  • DBG_I2C2_HOLD : gd32f3x0_dbg.h
  • DBG_ID : gd32f3x0_dbg.h
  • dbg_id_get() : gd32f3x0_dbg.h , gd32f3x0_dbg.c
  • DBG_ID_ID_CODE : gd32f3x0_dbg.h
  • DBG_IDX_CTL0 : gd32f3x0_dbg.h
  • DBG_IDX_CTL1 : gd32f3x0_dbg.h
  • DBG_LOW_POWER_DEEPSLEEP : gd32f3x0_dbg.h
  • dbg_low_power_disable() : gd32f3x0_dbg.h , gd32f3x0_dbg.c
  • dbg_low_power_enable() : gd32f3x0_dbg.h , gd32f3x0_dbg.c
  • DBG_LOW_POWER_SLEEP : gd32f3x0_dbg.h
  • DBG_LOW_POWER_STANDBY : gd32f3x0_dbg.h
  • dbg_periph_disable() : gd32f3x0_dbg.h , gd32f3x0_dbg.c
  • dbg_periph_enable() : gd32f3x0_dbg.h , gd32f3x0_dbg.c
  • dbg_periph_enum : gd32f3x0_dbg.h
  • dbg_reg_idx : gd32f3x0_dbg.h
  • DBG_REG_VAL : gd32f3x0_dbg.h
  • DBG_REGIDX_BIT : gd32f3x0_dbg.h
  • DBG_RESET_VAL : gd32f3x0_dbg.c
  • DBG_RTC_HOLD : gd32f3x0_dbg.h
  • DBG_TIMER0_HOLD : gd32f3x0_dbg.h
  • DBG_TIMER13_HOLD : gd32f3x0_dbg.h
  • DBG_TIMER14_HOLD : gd32f3x0_dbg.h
  • DBG_TIMER15_HOLD : gd32f3x0_dbg.h
  • DBG_TIMER16_HOLD : gd32f3x0_dbg.h
  • DBG_TIMER1_HOLD : gd32f3x0_dbg.h
  • DBG_TIMER2_HOLD : gd32f3x0_dbg.h
  • DBG_WWDGT_HOLD : gd32f3x0_dbg.h
  • DCFG_DAR : usb_regs.h
  • DCFG_DEVSPEED : usb_regs.h
  • DCFG_DS : usb_regs.h
  • DCFG_EOPFT : usb_regs.h
  • DCFG_NZLSOH : usb_regs.h
  • DCFG_PFRI : usb_regs.h
  • DCTL_CGINAK : usb_regs.h
  • DCTL_CGONAK : usb_regs.h
  • DCTL_GINS : usb_regs.h
  • DCTL_GONS : usb_regs.h
  • DCTL_POIF : usb_regs.h
  • DCTL_RWKUP : usb_regs.h
  • DCTL_SD : usb_regs.h
  • DCTL_SGINAK : usb_regs.h
  • DCTL_SGONAK : usb_regs.h
  • DEP0_MPL : usb_regs.h
  • DEP0CTL_CNAK : usb_regs.h
  • DEP0CTL_EPACT : usb_regs.h
  • DEP0CTL_EPD : usb_regs.h
  • DEP0CTL_EPEN : usb_regs.h
  • DEP0CTL_EPTYPE : usb_regs.h
  • DEP0CTL_MPL : usb_regs.h
  • DEP0CTL_NAKS : usb_regs.h
  • DEP0CTL_SNAK : usb_regs.h
  • DEP0CTL_STALL : usb_regs.h
  • DEPCTL_CNAK : usb_regs.h
  • DEPCTL_DPID : usb_regs.h
  • DEPCTL_EOFRM : usb_regs.h
  • DEPCTL_EPACT : usb_regs.h
  • DEPCTL_EPD : usb_regs.h
  • DEPCTL_EPEN : usb_regs.h
  • DEPCTL_EPTYPE : usb_regs.h
  • DEPCTL_MPL : usb_regs.h
  • DEPCTL_NAKS : usb_regs.h
  • DEPCTL_SD0PID : usb_regs.h
  • DEPCTL_SD1PID : usb_regs.h
  • DEPCTL_SEVNFRM : usb_regs.h
  • DEPCTL_SNAK : usb_regs.h
  • DEPCTL_SODDFRM : usb_regs.h
  • DEPCTL_STALL : usb_regs.h
  • DEPLEN_PCNT : usb_regs.h
  • DEPLEN_TLEN : usb_regs.h
  • DEVICE_MODE : usb_defines.h
  • DIEP0CTL_TXFNUM : usb_regs.h
  • DIEP0LEN_PCNT : usb_regs.h
  • DIEP0LEN_TLEN : usb_regs.h
  • DIEP0TFLEN_IEP0TXFD : usb_regs.h
  • DIEP0TFLEN_IEP0TXRSAR : usb_regs.h
  • DIEPCTL_TXFNUM : usb_regs.h
  • DIEPFEINTEN_IEPTXFEIE : usb_regs.h
  • DIEPINTEN_CITOEN : usb_regs.h
  • DIEPINTEN_EPDISEN : usb_regs.h
  • DIEPINTEN_EPTXFUDEN : usb_regs.h
  • DIEPINTEN_IEPNEEN : usb_regs.h
  • DIEPINTEN_TFEN : usb_regs.h
  • DIEPINTEN_TXFEEN : usb_regs.h
  • DIEPINTF_CITO : usb_regs.h
  • DIEPINTF_EPDIS : usb_regs.h
  • DIEPINTF_EPTXFUD : usb_regs.h
  • DIEPINTF_IEPNE : usb_regs.h
  • DIEPINTF_TF : usb_regs.h
  • DIEPINTF_TXFE : usb_regs.h
  • DIEPLEN_MCNT : usb_regs.h
  • DIEPTFLEN_IEPTXFD : usb_regs.h
  • DIEPTFLEN_IEPTXRSAR : usb_regs.h
  • DIEPTFSTAT_IEPTFS : usb_regs.h
  • DMA : gd32f3x0_dma.h
  • DMA_CH0 : gd32f3x0_dma.h
  • DMA_CH0CNT : gd32f3x0_dma.h
  • DMA_CH0CTL : gd32f3x0_dma.h
  • DMA_CH0MADDR : gd32f3x0_dma.h
  • DMA_CH0PADDR : gd32f3x0_dma.h
  • DMA_CH1 : gd32f3x0_dma.h
  • DMA_CH1CNT : gd32f3x0_dma.h
  • DMA_CH1CTL : gd32f3x0_dma.h
  • DMA_CH1MADDR : gd32f3x0_dma.h
  • DMA_CH1PADDR : gd32f3x0_dma.h
  • DMA_CH2 : gd32f3x0_dma.h
  • DMA_CH2CNT : gd32f3x0_dma.h
  • DMA_CH2CTL : gd32f3x0_dma.h
  • DMA_CH2MADDR : gd32f3x0_dma.h
  • DMA_CH2PADDR : gd32f3x0_dma.h
  • DMA_CH3 : gd32f3x0_dma.h
  • DMA_CH3CNT : gd32f3x0_dma.h
  • DMA_CH3CTL : gd32f3x0_dma.h
  • DMA_CH3MADDR : gd32f3x0_dma.h
  • DMA_CH3PADDR : gd32f3x0_dma.h
  • DMA_CH4 : gd32f3x0_dma.h
  • DMA_CH4CNT : gd32f3x0_dma.h
  • DMA_CH4CTL : gd32f3x0_dma.h
  • DMA_CH4MADDR : gd32f3x0_dma.h
  • DMA_CH4PADDR : gd32f3x0_dma.h
  • DMA_CH5 : gd32f3x0_dma.h
  • DMA_CH5CNT : gd32f3x0_dma.h
  • DMA_CH5CTL : gd32f3x0_dma.h
  • DMA_CH5MADDR : gd32f3x0_dma.h
  • DMA_CH5PADDR : gd32f3x0_dma.h
  • DMA_CH6 : gd32f3x0_dma.h
  • DMA_CH6CNT : gd32f3x0_dma.h
  • DMA_CH6CTL : gd32f3x0_dma.h
  • DMA_CH6MADDR : gd32f3x0_dma.h
  • DMA_CH6PADDR : gd32f3x0_dma.h
  • DMA_CHANNEL_CNT_MASK : gd32f3x0_dma.h
  • dma_channel_disable() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_channel_enable() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • dma_channel_enum : gd32f3x0_dma.h
  • DMA_CHCNT : gd32f3x0_dma.h
  • DMA_CHCNT_RESET_VALUE : gd32f3x0_dma.h
  • DMA_CHCTL : gd32f3x0_dma.h
  • DMA_CHCTL_RESET_VALUE : gd32f3x0_dma.h
  • DMA_CHINTF_RESET_VALUE : gd32f3x0_dma.h
  • DMA_CHMADDR : gd32f3x0_dma.h
  • DMA_CHMADDR_RESET_VALUE : gd32f3x0_dma.h
  • DMA_CHPADDR : gd32f3x0_dma.h
  • DMA_CHPADDR_RESET_VALUE : gd32f3x0_dma.h
  • DMA_CHXCNT_BASE : gd32f3x0_dma.h
  • DMA_CHXCNT_CNT : gd32f3x0_dma.h
  • DMA_CHXCTL_BASE : gd32f3x0_dma.h
  • DMA_CHXCTL_CHEN : gd32f3x0_dma.h
  • DMA_CHXCTL_CMEN : gd32f3x0_dma.h
  • DMA_CHXCTL_DIR : gd32f3x0_dma.h
  • DMA_CHXCTL_ERRIE : gd32f3x0_dma.h
  • DMA_CHXCTL_FTFIE : gd32f3x0_dma.h
  • DMA_CHXCTL_HTFIE : gd32f3x0_dma.h
  • DMA_CHXCTL_M2M : gd32f3x0_dma.h
  • DMA_CHXCTL_MNAGA : gd32f3x0_dma.h
  • DMA_CHXCTL_MWIDTH : gd32f3x0_dma.h
  • DMA_CHXCTL_PNAGA : gd32f3x0_dma.h
  • DMA_CHXCTL_PRIO : gd32f3x0_dma.h
  • DMA_CHXCTL_PWIDTH : gd32f3x0_dma.h
  • DMA_CHXMADDR_BASE : gd32f3x0_dma.h
  • DMA_CHXMADDR_MADDR : gd32f3x0_dma.h
  • DMA_CHXPADDR_BASE : gd32f3x0_dma.h
  • DMA_CHXPADDR_PADDR : gd32f3x0_dma.h
  • dma_circulation_disable() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_circulation_enable() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • dma_deinit() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • DMA_FLAG_ADD : gd32f3x0_dma.h
  • dma_flag_clear() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • DMA_FLAG_ERR : gd32f3x0_dma.h
  • DMA_FLAG_FTF : gd32f3x0_dma.h
  • DMA_FLAG_G : gd32f3x0_dma.h
  • dma_flag_get() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • DMA_FLAG_HTF : gd32f3x0_dma.h
  • DMA_INCR0 : usb_regs.h
  • DMA_INCR1 : usb_regs.h
  • DMA_INCR16 : usb_regs.h
  • DMA_INCR4 : usb_regs.h
  • DMA_INCR8 : usb_regs.h
  • dma_init() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • DMA_INT_ERR : gd32f3x0_dma.h
  • DMA_INT_FLAG_ERR : gd32f3x0_dma.h
  • DMA_INT_FLAG_FTF : gd32f3x0_dma.h
  • DMA_INT_FLAG_G : gd32f3x0_dma.h
  • DMA_INT_FLAG_HTF : gd32f3x0_dma.h
  • DMA_INT_FTF : gd32f3x0_dma.h
  • DMA_INT_HTF : gd32f3x0_dma.h
  • DMA_INTC : gd32f3x0_dma.h
  • DMA_INTC_ERRIFC : gd32f3x0_dma.h
  • DMA_INTC_FTFIFC : gd32f3x0_dma.h
  • DMA_INTC_GIFC : gd32f3x0_dma.h
  • DMA_INTC_HTFIFC : gd32f3x0_dma.h
  • dma_interrupt_disable() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_interrupt_enable() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • dma_interrupt_flag_clear() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_interrupt_flag_get() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • DMA_INTF : gd32f3x0_dma.h
  • DMA_INTF_ERRIF : gd32f3x0_dma.h
  • DMA_INTF_FTFIF : gd32f3x0_dma.h
  • DMA_INTF_GIF : gd32f3x0_dma.h
  • DMA_INTF_HTFIF : gd32f3x0_dma.h
  • dma_memory_address_config() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • dma_memory_increase_disable() : gd32f3x0_dma.c
  • DMA_MEMORY_INCREASE_DISABLE : gd32f3x0_dma.h
  • dma_memory_increase_disable() : gd32f3x0_dma.h
  • DMA_MEMORY_INCREASE_ENABLE : gd32f3x0_dma.h
  • dma_memory_increase_enable() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_memory_to_memory_disable() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_memory_to_memory_enable() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • DMA_MEMORY_TO_PERIPHERAL : gd32f3x0_dma.h
  • DMA_MEMORY_WIDTH_16BIT : gd32f3x0_dma.h
  • DMA_MEMORY_WIDTH_32BIT : gd32f3x0_dma.h
  • DMA_MEMORY_WIDTH_8BIT : gd32f3x0_dma.h
  • dma_memory_width_config() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_periph_address_config() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • DMA_PERIPH_INCREASE_DISABLE : gd32f3x0_dma.h
  • dma_periph_increase_disable() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_periph_increase_enable() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • DMA_PERIPH_INCREASE_ENABLE : gd32f3x0_dma.h
  • dma_periph_width_config() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • DMA_PERIPHERAL_TO_MEMORY : gd32f3x0_dma.h
  • DMA_PERIPHERAL_WIDTH_16BIT : gd32f3x0_dma.h
  • DMA_PERIPHERAL_WIDTH_32BIT : gd32f3x0_dma.h
  • DMA_PERIPHERAL_WIDTH_8BIT : gd32f3x0_dma.h
  • dma_priority_config() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • DMA_PRIORITY_HIGH : gd32f3x0_dma.h
  • DMA_PRIORITY_LOW : gd32f3x0_dma.h
  • DMA_PRIORITY_MEDIUM : gd32f3x0_dma.h
  • DMA_PRIORITY_ULTRA_HIGH : gd32f3x0_dma.h
  • dma_transfer_direction_config() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • dma_transfer_number_config() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_transfer_number_get() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • DMACFG_DMATA : gd32f3x0_timer.h
  • DMACFG_DMATC : gd32f3x0_timer.h
  • DOEP0LEN_PCNT : usb_regs.h
  • DOEP0LEN_STPCNT : usb_regs.h
  • DOEP0LEN_TLEN : usb_regs.h
  • DOEPINTEN_BTBSTPEN : usb_regs.h
  • DOEPINTEN_EPDISEN : usb_regs.h
  • DOEPINTEN_EPRXFOVREN : usb_regs.h
  • DOEPINTEN_STPFEN : usb_regs.h
  • DOEPINTEN_TFEN : usb_regs.h
  • DOEPINTF_BTBSTP : usb_regs.h
  • DOEPINTF_EPDIS : usb_regs.h
  • DOEPINTF_EPRXFOVR : usb_regs.h
  • DOEPINTF_STPF : usb_regs.h
  • DOEPINTF_TF : usb_regs.h
  • DOEPLEN_RXDPID : usb_regs.h
  • DOEPLEN_STPCNT : usb_regs.h
  • DPID_DATA0 : usb_defines.h
  • DPID_DATA1 : usb_defines.h
  • DPID_DATA2 : usb_defines.h
  • DPID_MDATA : usb_defines.h
  • DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ : usb_defines.h
  • DSTAT_ENUMSPD_FS_PHY_48MHZ : usb_defines.h
  • DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ : usb_defines.h
  • DSTAT_ENUMSPD_LS_PHY_6MHZ : usb_defines.h
  • DSTAT_ES : usb_regs.h
  • DSTAT_FNRSOF : usb_regs.h
  • DSTAT_SPST : usb_regs.h
  • DSV_DSLPVS : gd32f3x0_rcu.h
  • DTS_DAY : gd32f3x0_rtc.h
  • DTS_DOW : gd32f3x0_rtc.h
  • DTS_MON : gd32f3x0_rtc.h
  • DVBUSDT_DVBUSDT : usb_regs.h
  • DVBUSPT_DVBUSPT : usb_regs.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • ENG_LANGID : usbd_std.h
  • ENUM_DEV_CONFIGURED : usbh_core.h
  • enum_event_enum : usbh_std.h
  • ENUM_EVENT_SET_ADDR : usbh_std.h
  • ENUM_FSM_ID : usbh_core.h
  • ENUM_GET_CFG_DESC : usbh_core.h
  • ENUM_GET_FULL_CFG_DESC : usbh_core.h
  • ENUM_GET_FULL_DEV_DESC : usbh_core.h
  • ENUM_GET_MFC_STRING_DESC : usbh_core.h
  • ENUM_GET_PRODUCT_STRING_DESC : usbh_core.h
  • ENUM_GET_SERIALNUM_STRING_DESC : usbh_core.h
  • enum_handle_table : usbh_std.h , usbh_std.c
  • ENUM_HANDLE_TABLE_SIZE : usbh_std.h
  • ENUM_IDLE : usbh_core.h
  • enum_polling_handle_flag : usbh_std.h , usbh_std.c
  • ENUM_SET_ADDR : usbh_core.h
  • ENUM_SET_CONFIGURATION : usbh_core.h
  • enum_state_enum : usbh_core.h
  • enum_state_handle : usbh_std.c
  • enum_state_polling_fun() : usbh_std.h , usbh_std.c
  • ENUN_EVENT_DEV_CONFIGURED : usbh_std.h
  • ENUN_EVENT_GET_CFG_DESC : usbh_std.h
  • ENUN_EVENT_GET_FULL_CFG_DESC : usbh_std.h
  • ENUN_EVENT_GET_FULL_DEV_DESC : usbh_std.h
  • ENUN_EVENT_GET_MFC_STRING_DESC : usbh_std.h
  • ENUN_EVENT_GET_PRODUCT_STRING_DESC : usbh_std.h
  • ENUN_EVENT_GET_SERIALNUM_STRING_DESC : usbh_std.h
  • ENUN_EVENT_IDLE : usbh_std.h
  • ENUN_EVENT_SET_CONFIGURATION : usbh_std.h
  • EP0_IN : usb_regs.h
  • EP0_OUT : usb_regs.h
  • EP0MPL_16 : usb_regs.h
  • EP0MPL_32 : usb_regs.h
  • EP0MPL_64 : usb_regs.h
  • EP0MPL_8 : usb_regs.h
  • EP1_IN : usb_regs.h
  • EP1_OUT : usb_regs.h
  • EP2_IN : usb_regs.h
  • EP2_OUT : usb_regs.h
  • EP3_IN : usb_regs.h
  • EP3_OUT : usb_regs.h
  • EXTI : gd32f3x0_exti.h
  • EXTI_0 : gd32f3x0_exti.h
  • EXTI_1 : gd32f3x0_exti.h
  • EXTI_10 : gd32f3x0_exti.h
  • EXTI_11 : gd32f3x0_exti.h
  • EXTI_12 : gd32f3x0_exti.h
  • EXTI_13 : gd32f3x0_exti.h
  • EXTI_14 : gd32f3x0_exti.h
  • EXTI_15 : gd32f3x0_exti.h
  • EXTI_16 : gd32f3x0_exti.h
  • EXTI_17 : gd32f3x0_exti.h
  • EXTI_18 : gd32f3x0_exti.h
  • EXTI_19 : gd32f3x0_exti.h
  • EXTI_2 : gd32f3x0_exti.h
  • EXTI_20 : gd32f3x0_exti.h
  • EXTI_21 : gd32f3x0_exti.h
  • EXTI_22 : gd32f3x0_exti.h
  • EXTI_23 : gd32f3x0_exti.h
  • EXTI_24 : gd32f3x0_exti.h
  • EXTI_25 : gd32f3x0_exti.h
  • EXTI_26 : gd32f3x0_exti.h
  • EXTI_27 : gd32f3x0_exti.h
  • EXTI_3 : gd32f3x0_exti.h
  • EXTI_4 : gd32f3x0_exti.h
  • EXTI_5 : gd32f3x0_exti.h
  • EXTI_6 : gd32f3x0_exti.h
  • EXTI_7 : gd32f3x0_exti.h
  • EXTI_8 : gd32f3x0_exti.h
  • EXTI_9 : gd32f3x0_exti.h
  • exti_deinit() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • EXTI_EVEN : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN0 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN1 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN10 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN11 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN12 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN13 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN14 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN15 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN16 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN17 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN18 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN19 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN2 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN20 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN21 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN22 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN23 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN24 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN25 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN26 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN27 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN3 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN4 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN5 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN6 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN7 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN8 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN9 : gd32f3x0_exti.h
  • EXTI_EVENT : gd32f3x0_exti.h
  • exti_event_disable() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • exti_event_enable() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • exti_flag_clear() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • exti_flag_get() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • EXTI_FTEN : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN0 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN1 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN10 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN11 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN12 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN13 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN14 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN15 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN16 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN17 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN18 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN19 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN2 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN21 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN22 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN3 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN4 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN5 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN6 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN7 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN8 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN9 : gd32f3x0_exti.h
  • exti_init() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • EXTI_INTEN : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN0 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN1 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN10 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN11 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN12 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN13 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN14 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN15 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN16 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN17 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN18 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN19 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN2 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN20 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN21 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN22 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN23 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN24 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN25 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN26 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN27 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN3 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN4 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN5 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN6 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN7 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN8 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN9 : gd32f3x0_exti.h
  • EXTI_INTERRUPT : gd32f3x0_exti.h
  • exti_interrupt_disable() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • exti_interrupt_enable() : gd32f3x0_exti.c , gd32f3x0_exti.h
  • exti_interrupt_flag_clear() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • exti_interrupt_flag_get() : gd32f3x0_exti.c , gd32f3x0_exti.h
  • exti_line_enum : gd32f3x0_exti.h
  • exti_mode_enum : gd32f3x0_exti.h
  • EXTI_PD : gd32f3x0_exti.h
  • EXTI_PD_PD0 : gd32f3x0_exti.h
  • EXTI_PD_PD1 : gd32f3x0_exti.h
  • EXTI_PD_PD10 : gd32f3x0_exti.h
  • EXTI_PD_PD11 : gd32f3x0_exti.h
  • EXTI_PD_PD12 : gd32f3x0_exti.h
  • EXTI_PD_PD13 : gd32f3x0_exti.h
  • EXTI_PD_PD14 : gd32f3x0_exti.h
  • EXTI_PD_PD15 : gd32f3x0_exti.h
  • EXTI_PD_PD16 : gd32f3x0_exti.h
  • EXTI_PD_PD17 : gd32f3x0_exti.h
  • EXTI_PD_PD18 : gd32f3x0_exti.h
  • EXTI_PD_PD19 : gd32f3x0_exti.h
  • EXTI_PD_PD2 : gd32f3x0_exti.h
  • EXTI_PD_PD21 : gd32f3x0_exti.h
  • EXTI_PD_PD22 : gd32f3x0_exti.h
  • EXTI_PD_PD3 : gd32f3x0_exti.h
  • EXTI_PD_PD4 : gd32f3x0_exti.h
  • EXTI_PD_PD5 : gd32f3x0_exti.h
  • EXTI_PD_PD6 : gd32f3x0_exti.h
  • EXTI_PD_PD7 : gd32f3x0_exti.h
  • EXTI_PD_PD8 : gd32f3x0_exti.h
  • EXTI_PD_PD9 : gd32f3x0_exti.h
  • EXTI_RTEN : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN0 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN1 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN10 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN11 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN12 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN13 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN14 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN15 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN16 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN17 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN18 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN19 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN2 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN21 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN22 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN3 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN4 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN5 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN6 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN7 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN8 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN9 : gd32f3x0_exti.h
  • exti_software_interrupt_disable() : gd32f3x0_exti.c , gd32f3x0_exti.h
  • exti_software_interrupt_enable() : gd32f3x0_exti.c , gd32f3x0_exti.h
  • EXTI_SOURCE_GPIOA : gd32f3x0_syscfg.h
  • EXTI_SOURCE_GPIOB : gd32f3x0_syscfg.h
  • EXTI_SOURCE_GPIOC : gd32f3x0_syscfg.h
  • EXTI_SOURCE_GPIOD : gd32f3x0_syscfg.h
  • EXTI_SOURCE_GPIOF : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN0 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN1 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN10 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN11 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN12 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN13 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN14 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN15 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN2 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN3 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN4 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN5 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN6 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN7 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN8 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN9 : gd32f3x0_syscfg.h
  • EXTI_SS_JSTEP : gd32f3x0_syscfg.h
  • EXTI_SS_MASK : gd32f3x0_syscfg.h
  • EXTI_SS_MSTEP : gd32f3x0_syscfg.h
  • EXTI_SWIEV : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV0 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV1 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV10 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV11 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV12 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV13 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV14 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV15 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV16 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV17 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV18 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV19 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV2 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV21 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV22 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV3 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV4 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV5 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV6 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV7 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV8 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV9 : gd32f3x0_exti.h
  • EXTI_TRIG_BOTH : gd32f3x0_exti.h
  • EXTI_TRIG_FALLING : gd32f3x0_exti.h
  • EXTI_TRIG_RISING : gd32f3x0_exti.h
  • exti_trig_type_enum : gd32f3x0_exti.h
  • EXTISS0 : gd32f3x0_syscfg.h
  • EXTISS1 : gd32f3x0_syscfg.h
  • EXTISS2 : gd32f3x0_syscfg.h
  • EXTISS3 : gd32f3x0_syscfg.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FEATURE_SELECTOR_DEVICE : usbh_std.h
  • FEATURE_SELECTOR_ENDPOINT : usbh_std.h
  • FMC : gd32f3x0_fmc.h
  • FMC_ADDR : gd32f3x0_fmc.h
  • FMC_ADDR_ADDR : gd32f3x0_fmc.h
  • FMC_BUSY : gd32f3x0_fmc.h
  • FMC_CTL : gd32f3x0_fmc.h
  • FMC_CTL_ENDIE : gd32f3x0_fmc.h
  • FMC_CTL_ERRIE : gd32f3x0_fmc.h
  • FMC_CTL_LK : gd32f3x0_fmc.h
  • FMC_CTL_MER : gd32f3x0_fmc.h
  • FMC_CTL_OBER : gd32f3x0_fmc.h
  • FMC_CTL_OBPG : gd32f3x0_fmc.h
  • FMC_CTL_OBRLD : gd32f3x0_fmc.h
  • FMC_CTL_OBWEN : gd32f3x0_fmc.h
  • FMC_CTL_PER : gd32f3x0_fmc.h
  • FMC_CTL_PG : gd32f3x0_fmc.h
  • FMC_CTL_START : gd32f3x0_fmc.h
  • FMC_FLAG_BUSY : gd32f3x0_fmc.h
  • fmc_flag_clear() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • FMC_FLAG_END : gd32f3x0_fmc.h
  • fmc_flag_get() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • FMC_FLAG_PGERR : gd32f3x0_fmc.h
  • FMC_FLAG_WPERR : gd32f3x0_fmc.h
  • fmc_halfword_program() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • FMC_HSPC : gd32f3x0_fmc.h
  • FMC_INTEN_END : gd32f3x0_fmc.h
  • FMC_INTEN_ERR : gd32f3x0_fmc.h
  • fmc_interrupt_disable() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_interrupt_enable() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • FMC_KEY : gd32f3x0_fmc.h
  • FMC_KEY_KEY : gd32f3x0_fmc.h
  • fmc_lock() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • FMC_LSPC : gd32f3x0_fmc.h
  • fmc_mass_erase() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • FMC_NSPC : gd32f3x0_fmc.h
  • FMC_OB_HSPC : gd32f3x0_fmc.h
  • FMC_OBKEY : gd32f3x0_fmc.h
  • FMC_OBKEY_OBKEY : gd32f3x0_fmc.h
  • FMC_OBSTAT : gd32f3x0_fmc.h
  • FMC_OBSTAT_DATA : gd32f3x0_fmc.h
  • FMC_OBSTAT_OBERR : gd32f3x0_fmc.h
  • FMC_OBSTAT_PLVL_BIT0 : gd32f3x0_fmc.h
  • FMC_OBSTAT_PLVL_BIT1 : gd32f3x0_fmc.h
  • FMC_OBSTAT_USER : gd32f3x0_fmc.h
  • fmc_page_erase() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • FMC_PGERR : gd32f3x0_fmc.h
  • FMC_PID : gd32f3x0_fmc.h
  • FMC_PID_PID : gd32f3x0_fmc.h
  • FMC_READY : gd32f3x0_fmc.h
  • fmc_ready_wait() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • FMC_STAT : gd32f3x0_fmc.h
  • FMC_STAT_BUSY : gd32f3x0_fmc.h
  • FMC_STAT_ENDF : gd32f3x0_fmc.h
  • FMC_STAT_PGERR : gd32f3x0_fmc.h
  • FMC_STAT_WPERR : gd32f3x0_fmc.h
  • fmc_state_enum : gd32f3x0_fmc.h
  • fmc_state_get() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • FMC_TIMEOUT_COUNT : gd32f3x0_fmc.h
  • FMC_TOERR : gd32f3x0_fmc.h
  • fmc_unlock() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_wait_state_disable() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_wait_state_enable() : gd32f3x0_fmc.c , gd32f3x0_fmc.h
  • fmc_word_program() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_word_reprogram() : gd32f3x0_fmc.c , gd32f3x0_fmc.h
  • FMC_WP : gd32f3x0_fmc.h
  • FMC_WPERR : gd32f3x0_fmc.h
  • FMC_WS : gd32f3x0_fmc.h
  • FMC_WS_WSCNT : gd32f3x0_fmc.h
  • fmc_wscnt_set() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • FMC_WSEN : gd32f3x0_fmc.h
  • FMC_WSEN_BPEN : gd32f3x0_fmc.h
  • FMC_WSEN_WSEN : gd32f3x0_fmc.h
  • FRAME_INTERVAL_80 : usb_regs.h
  • FRAME_INTERVAL_85 : usb_regs.h
  • FRAME_INTERVAL_90 : usb_regs.h
  • FRAME_INTERVAL_95 : usb_regs.h
  • FWDGT : gd32f3x0_fwdgt.h
  • fwdgt_config() : gd32f3x0_fwdgt.h , gd32f3x0_fwdgt.c
  • fwdgt_counter_reload() : gd32f3x0_fwdgt.h , gd32f3x0_fwdgt.c
  • FWDGT_CTL : gd32f3x0_fwdgt.h
  • FWDGT_CTL_CMD : gd32f3x0_fwdgt.h
  • fwdgt_enable() : gd32f3x0_fwdgt.c , gd32f3x0_fwdgt.h
  • fwdgt_flag_get() : gd32f3x0_fwdgt.h , gd32f3x0_fwdgt.c
  • FWDGT_FLAG_PUD : gd32f3x0_fwdgt.h
  • FWDGT_FLAG_RUD : gd32f3x0_fwdgt.h
  • FWDGT_FLAG_WUD : gd32f3x0_fwdgt.h
  • FWDGT_KEY_ENABLE : gd32f3x0_fwdgt.h
  • FWDGT_KEY_RELOAD : gd32f3x0_fwdgt.h
  • FWDGT_PSC : gd32f3x0_fwdgt.h
  • FWDGT_PSC_DIV128 : gd32f3x0_fwdgt.h
  • FWDGT_PSC_DIV16 : gd32f3x0_fwdgt.h
  • FWDGT_PSC_DIV256 : gd32f3x0_fwdgt.h
  • FWDGT_PSC_DIV32 : gd32f3x0_fwdgt.h
  • FWDGT_PSC_DIV4 : gd32f3x0_fwdgt.h
  • FWDGT_PSC_DIV64 : gd32f3x0_fwdgt.h
  • FWDGT_PSC_DIV8 : gd32f3x0_fwdgt.h
  • FWDGT_PSC_PSC : gd32f3x0_fwdgt.h
  • FWDGT_PSC_TIMEOUT : gd32f3x0_fwdgt.h
  • FWDGT_RLD : gd32f3x0_fwdgt.h
  • FWDGT_RLD_RLD : gd32f3x0_fwdgt.h
  • FWDGT_RLD_TIMEOUT : gd32f3x0_fwdgt.h
  • FWDGT_STAT : gd32f3x0_fwdgt.h
  • FWDGT_STAT_PUD : gd32f3x0_fwdgt.h
  • FWDGT_STAT_RUD : gd32f3x0_fwdgt.h
  • FWDGT_STAT_WUD : gd32f3x0_fwdgt.h
  • fwdgt_window_value_config() : gd32f3x0_fwdgt.c , gd32f3x0_fwdgt.h
  • FWDGT_WND : gd32f3x0_fwdgt.h
  • FWDGT_WND_TIMEOUT : gd32f3x0_fwdgt.h
  • FWDGT_WND_WND : gd32f3x0_fwdgt.h
  • fwdgt_write_disable() : gd32f3x0_fwdgt.c , gd32f3x0_fwdgt.h
  • FWDGT_WRITEACCESS_DISABLE : gd32f3x0_fwdgt.h
  • FWDGT_WRITEACCESS_ENABLE : gd32f3x0_fwdgt.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GAHBCS_DMAINCR : usb_regs.h
  • GAHBCS_GINTEN : usb_regs.h
  • GAHBCS_PTXFTH : usb_regs.h
  • GAHBCS_TFEL : usb_regs.h
  • GAHBCS_TXFTH : usb_regs.h
  • GCCFG_PWRON : usb_regs.h
  • GCCFG_SOFOEN : usb_regs.h
  • GCCFG_VBUSACEN : usb_regs.h
  • GCCFG_VBUSBCEN : usb_regs.h
  • GCCFG_VBUSIG : usb_regs.h
  • GET_ALRM0TD_DAY : gd32f3x0_rtc.h
  • GET_ALRM0TD_HR : gd32f3x0_rtc.h
  • GET_ALRM0TD_MN : gd32f3x0_rtc.h
  • GET_ALRM0TD_SC : gd32f3x0_rtc.h
  • GET_CTL0_TRIMVALUE : gd32f3x0_ctc.h
  • GET_DATE_DAY : gd32f3x0_rtc.h
  • GET_DATE_DOW : gd32f3x0_rtc.h
  • GET_DATE_MON : gd32f3x0_rtc.h
  • GET_DATE_YR : gd32f3x0_rtc.h
  • GET_DTS_DAY : gd32f3x0_rtc.h
  • GET_DTS_DOW : gd32f3x0_rtc.h
  • GET_DTS_MON : gd32f3x0_rtc.h
  • GET_PSC_FACTOR_A : gd32f3x0_rtc.h
  • GET_PSC_FACTOR_S : gd32f3x0_rtc.h
  • GET_STAT_REFCAP : gd32f3x0_ctc.h
  • GET_TIME_HR : gd32f3x0_rtc.h
  • GET_TIME_MN : gd32f3x0_rtc.h
  • GET_TIME_SC : gd32f3x0_rtc.h
  • GET_TTS_HR : gd32f3x0_rtc.h
  • GET_TTS_MN : gd32f3x0_rtc.h
  • GET_TTS_SC : gd32f3x0_rtc.h
  • GINTEN_DISCIE : usb_regs.h
  • GINTEN_ENUMFIE : usb_regs.h
  • GINTEN_EOPFIE : usb_regs.h
  • GINTEN_ESPIE : usb_regs.h
  • GINTEN_GNPINAKIE : usb_regs.h
  • GINTEN_GONAKIE : usb_regs.h
  • GINTEN_HCIE : usb_regs.h
  • GINTEN_HPIE : usb_regs.h
  • GINTEN_IDPSCIE : usb_regs.h
  • GINTEN_IEPIE : usb_regs.h
  • GINTEN_ISOINCIE : usb_regs.h
  • GINTEN_ISOONCIE : usb_regs.h
  • GINTEN_ISOOPDIE : usb_regs.h
  • GINTEN_MFIE : usb_regs.h
  • GINTEN_NPTXFEIE : usb_regs.h
  • GINTEN_OEPIE : usb_regs.h
  • GINTEN_OTGIE : usb_regs.h
  • GINTEN_PTXFEIE : usb_regs.h
  • GINTEN_PXNCIE : usb_regs.h
  • GINTEN_RSTIE : usb_regs.h
  • GINTEN_RXFNEIE : usb_regs.h
  • GINTEN_SESIE : usb_regs.h
  • GINTEN_SOFIE : usb_regs.h
  • GINTEN_SPIE : usb_regs.h
  • GINTEN_WKUPIE : usb_regs.h
  • GINTF_COPM : usb_regs.h
  • GINTF_DISCIF : usb_regs.h
  • GINTF_ENUMF : usb_regs.h
  • GINTF_EOPFIF : usb_regs.h
  • GINTF_ESP : usb_regs.h
  • GINTF_GNPINAK : usb_regs.h
  • GINTF_GONAK : usb_regs.h
  • GINTF_HCIF : usb_regs.h
  • GINTF_HPIF : usb_regs.h
  • GINTF_IDPSC : usb_regs.h
  • GINTF_IEPIF : usb_regs.h
  • GINTF_ISOINCIF : usb_regs.h
  • GINTF_ISOONCIF : usb_regs.h
  • GINTF_ISOOPDIF : usb_regs.h
  • GINTF_MFIF : usb_regs.h
  • GINTF_NPTXFEIF : usb_regs.h
  • GINTF_OEPIF : usb_regs.h
  • GINTF_OTGIF : usb_regs.h
  • GINTF_PTXFEIF : usb_regs.h
  • GINTF_PXNCIF : usb_regs.h
  • GINTF_RST : usb_regs.h
  • GINTF_RXFNEIF : usb_regs.h
  • GINTF_SESIF : usb_regs.h
  • GINTF_SOF : usb_regs.h
  • GINTF_SP : usb_regs.h
  • GINTF_WKUPIF : usb_regs.h
  • GO_TO_UP_STATE_EVENT : usbh_core.h
  • GOTGCS_ASV : usb_regs.h
  • GOTGCS_BSV : usb_regs.h
  • GOTGCS_DHNPEN : usb_regs.h
  • GOTGCS_DI : usb_regs.h
  • GOTGCS_HHNPEN : usb_regs.h
  • GOTGCS_HNPREQ : usb_regs.h
  • GOTGCS_HNPS : usb_regs.h
  • GOTGCS_IDPS : usb_regs.h
  • GOTGCS_SRPREQ : usb_regs.h
  • GOTGCS_SRPS : usb_regs.h
  • GOTGINTF_ADTO : usb_regs.h
  • GOTGINTF_DF : usb_regs.h
  • GOTGINTF_HNPDET : usb_regs.h
  • GOTGINTF_HNPEND : usb_regs.h
  • GOTGINTF_SESEND : usb_regs.h
  • GOTGINTF_SRPEND : usb_regs.h
  • goto_up_state_fun() : usbh_core.h , usbh_core.c
  • GPIO_AF_0 : gd32f3x0_gpio.h
  • GPIO_AF_1 : gd32f3x0_gpio.h
  • GPIO_AF_2 : gd32f3x0_gpio.h
  • GPIO_AF_3 : gd32f3x0_gpio.h
  • GPIO_AF_4 : gd32f3x0_gpio.h
  • GPIO_AF_5 : gd32f3x0_gpio.h
  • GPIO_AF_6 : gd32f3x0_gpio.h
  • GPIO_AF_7 : gd32f3x0_gpio.h
  • gpio_af_set() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • GPIO_AFR_MASK : gd32f3x0_gpio.h
  • GPIO_AFR_SET : gd32f3x0_gpio.h
  • GPIO_AFSEL0 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL0 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL1 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL2 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL3 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL4 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL5 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL6 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL7 : gd32f3x0_gpio.h
  • GPIO_AFSEL1 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL10 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL11 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL12 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL13 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL14 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL15 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL8 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL9 : gd32f3x0_gpio.h
  • GPIO_BC : gd32f3x0_gpio.h
  • GPIO_BC_CR0 : gd32f3x0_gpio.h
  • GPIO_BC_CR1 : gd32f3x0_gpio.h
  • GPIO_BC_CR10 : gd32f3x0_gpio.h
  • GPIO_BC_CR11 : gd32f3x0_gpio.h
  • GPIO_BC_CR12 : gd32f3x0_gpio.h
  • GPIO_BC_CR13 : gd32f3x0_gpio.h
  • GPIO_BC_CR14 : gd32f3x0_gpio.h
  • GPIO_BC_CR15 : gd32f3x0_gpio.h
  • GPIO_BC_CR2 : gd32f3x0_gpio.h
  • GPIO_BC_CR3 : gd32f3x0_gpio.h
  • GPIO_BC_CR4 : gd32f3x0_gpio.h
  • GPIO_BC_CR5 : gd32f3x0_gpio.h
  • GPIO_BC_CR6 : gd32f3x0_gpio.h
  • GPIO_BC_CR7 : gd32f3x0_gpio.h
  • GPIO_BC_CR8 : gd32f3x0_gpio.h
  • GPIO_BC_CR9 : gd32f3x0_gpio.h
  • gpio_bit_reset() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_bit_set() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_bit_toggle() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_bit_write() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • GPIO_BOP : gd32f3x0_gpio.h
  • GPIO_BOP_BOP0 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP1 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP10 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP11 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP12 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP13 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP14 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP15 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP2 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP3 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP4 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP5 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP6 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP7 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP8 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP9 : gd32f3x0_gpio.h
  • GPIO_BOP_CR0 : gd32f3x0_gpio.h
  • GPIO_BOP_CR1 : gd32f3x0_gpio.h
  • GPIO_BOP_CR10 : gd32f3x0_gpio.h
  • GPIO_BOP_CR11 : gd32f3x0_gpio.h
  • GPIO_BOP_CR12 : gd32f3x0_gpio.h
  • GPIO_BOP_CR13 : gd32f3x0_gpio.h
  • GPIO_BOP_CR14 : gd32f3x0_gpio.h
  • GPIO_BOP_CR15 : gd32f3x0_gpio.h
  • GPIO_BOP_CR2 : gd32f3x0_gpio.h
  • GPIO_BOP_CR3 : gd32f3x0_gpio.h
  • GPIO_BOP_CR4 : gd32f3x0_gpio.h
  • GPIO_BOP_CR5 : gd32f3x0_gpio.h
  • GPIO_BOP_CR6 : gd32f3x0_gpio.h
  • GPIO_BOP_CR7 : gd32f3x0_gpio.h
  • GPIO_BOP_CR8 : gd32f3x0_gpio.h
  • GPIO_BOP_CR9 : gd32f3x0_gpio.h
  • GPIO_CTL : gd32f3x0_gpio.h
  • GPIO_CTL_CTL0 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL1 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL10 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL11 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL12 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL13 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL14 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL15 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL2 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL3 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL4 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL5 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL6 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL7 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL8 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL9 : gd32f3x0_gpio.h
  • gpio_deinit() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_input_bit_get() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_input_port_get() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • GPIO_ISTAT : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT0 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT1 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT10 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT11 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT12 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT13 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT14 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT15 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT2 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT3 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT4 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT5 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT6 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT7 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT8 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT9 : gd32f3x0_gpio.h
  • GPIO_LOCK : gd32f3x0_gpio.h
  • GPIO_LOCK_LK0 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK1 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK10 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK11 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK12 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK13 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK14 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK15 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK2 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK3 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK4 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK5 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK6 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK7 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK8 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK9 : gd32f3x0_gpio.h
  • GPIO_LOCK_LKK : gd32f3x0_gpio.h
  • GPIO_MODE_AF : gd32f3x0_gpio.h
  • GPIO_MODE_ANALOG : gd32f3x0_gpio.h
  • GPIO_MODE_INPUT : gd32f3x0_gpio.h
  • GPIO_MODE_MASK : gd32f3x0_gpio.h
  • GPIO_MODE_OUTPUT : gd32f3x0_gpio.h
  • GPIO_MODE_SET : gd32f3x0_gpio.h
  • gpio_mode_set() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • GPIO_OCTL : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL0 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL1 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL10 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL11 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL12 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL13 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL14 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL15 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL2 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL3 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL4 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL5 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL6 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL7 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL8 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL9 : gd32f3x0_gpio.h
  • GPIO_OMODE : gd32f3x0_gpio.h
  • GPIO_OMODE_OM0 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM1 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM10 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM11 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM12 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM13 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM14 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM15 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM2 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM3 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM4 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM5 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM6 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM7 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM8 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM9 : gd32f3x0_gpio.h
  • GPIO_OSPD0 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD0 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD1 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD10 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD11 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD12 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD13 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD14 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD15 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD2 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD3 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD4 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD5 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD6 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD7 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD8 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD9 : gd32f3x0_gpio.h
  • GPIO_OSPD1 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD0 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD1 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD10 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD11 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD12 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD13 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD14 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD15 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD2 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD3 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD4 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD5 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD6 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD7 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD8 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD9 : gd32f3x0_gpio.h
  • GPIO_OSPEED_10MHZ : gd32f3x0_gpio.h
  • GPIO_OSPEED_2MHZ : gd32f3x0_gpio.h
  • GPIO_OSPEED_50MHZ : gd32f3x0_gpio.h
  • GPIO_OSPEED_MASK : gd32f3x0_gpio.h
  • GPIO_OSPEED_MAX : gd32f3x0_gpio.h
  • GPIO_OSPEED_SET : gd32f3x0_gpio.h
  • GPIO_OTYPE_OD : gd32f3x0_gpio.h
  • GPIO_OTYPE_PP : gd32f3x0_gpio.h
  • gpio_output_bit_get() : gd32f3x0_gpio.c , gd32f3x0_gpio.h
  • gpio_output_options_set() : gd32f3x0_gpio.c , gd32f3x0_gpio.h
  • gpio_output_port_get() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • GPIO_PIN_0 : gd32f3x0_gpio.h
  • GPIO_PIN_1 : gd32f3x0_gpio.h
  • GPIO_PIN_10 : gd32f3x0_gpio.h
  • GPIO_PIN_11 : gd32f3x0_gpio.h
  • GPIO_PIN_12 : gd32f3x0_gpio.h
  • GPIO_PIN_13 : gd32f3x0_gpio.h
  • GPIO_PIN_14 : gd32f3x0_gpio.h
  • GPIO_PIN_15 : gd32f3x0_gpio.h
  • GPIO_PIN_2 : gd32f3x0_gpio.h
  • GPIO_PIN_3 : gd32f3x0_gpio.h
  • GPIO_PIN_4 : gd32f3x0_gpio.h
  • GPIO_PIN_5 : gd32f3x0_gpio.h
  • GPIO_PIN_6 : gd32f3x0_gpio.h
  • GPIO_PIN_7 : gd32f3x0_gpio.h
  • GPIO_PIN_8 : gd32f3x0_gpio.h
  • GPIO_PIN_9 : gd32f3x0_gpio.h
  • GPIO_PIN_ALL : gd32f3x0_gpio.h
  • gpio_pin_lock() : gd32f3x0_gpio.c , gd32f3x0_gpio.h
  • gpio_port_toggle() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_port_write() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • GPIO_PUD : gd32f3x0_gpio.h
  • GPIO_PUD_PUD0 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD1 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD10 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD11 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD12 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD13 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD14 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD15 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD2 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD3 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD4 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD5 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD6 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD7 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD8 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD9 : gd32f3x0_gpio.h
  • GPIO_PUPD_MASK : gd32f3x0_gpio.h
  • GPIO_PUPD_NONE : gd32f3x0_gpio.h
  • GPIO_PUPD_PULLDOWN : gd32f3x0_gpio.h
  • GPIO_PUPD_PULLUP : gd32f3x0_gpio.h
  • GPIO_PUPD_SET : gd32f3x0_gpio.h
  • GPIO_TG : gd32f3x0_gpio.h
  • GPIO_TG_TG0 : gd32f3x0_gpio.h
  • GPIO_TG_TG1 : gd32f3x0_gpio.h
  • GPIO_TG_TG10 : gd32f3x0_gpio.h
  • GPIO_TG_TG11 : gd32f3x0_gpio.h
  • GPIO_TG_TG12 : gd32f3x0_gpio.h
  • GPIO_TG_TG13 : gd32f3x0_gpio.h
  • GPIO_TG_TG14 : gd32f3x0_gpio.h
  • GPIO_TG_TG15 : gd32f3x0_gpio.h
  • GPIO_TG_TG2 : gd32f3x0_gpio.h
  • GPIO_TG_TG3 : gd32f3x0_gpio.h
  • GPIO_TG_TG4 : gd32f3x0_gpio.h
  • GPIO_TG_TG5 : gd32f3x0_gpio.h
  • GPIO_TG_TG6 : gd32f3x0_gpio.h
  • GPIO_TG_TG7 : gd32f3x0_gpio.h
  • GPIO_TG_TG8 : gd32f3x0_gpio.h
  • GPIO_TG_TG9 : gd32f3x0_gpio.h
  • GPIOA : gd32f3x0_gpio.h
  • GPIOB : gd32f3x0_gpio.h
  • GPIOC : gd32f3x0_gpio.h
  • GPIOD : gd32f3x0_gpio.h
  • GPIOF : gd32f3x0_gpio.h
  • GRFLEN_RXFD : usb_regs.h
  • GRSTATR_RPCKST_CH_HALTED : usb_defines.h
  • GRSTATR_RPCKST_DATA_TOGGLE_ERR : usb_defines.h
  • GRSTATR_RPCKST_IN : usb_defines.h
  • GRSTATR_RPCKST_IN_XFER_COMP : usb_defines.h
  • GRSTATRP_BCOUNT : usb_regs.h
  • GRSTATRP_CNUM : usb_regs.h
  • GRSTATRP_DPID : usb_regs.h
  • GRSTATRP_EPNUM : usb_regs.h
  • GRSTATRP_RPCKST : usb_regs.h
  • GRSTCTL_CSRST : usb_regs.h
  • GRSTCTL_HCSRST : usb_regs.h
  • GRSTCTL_HFCRST : usb_regs.h
  • GRSTCTL_RXFF : usb_regs.h
  • GRSTCTL_TXFF : usb_regs.h
  • GRSTCTL_TXFNUM : usb_regs.h
  • GUSBCS_FDM : usb_regs.h
  • GUSBCS_FHM : usb_regs.h
  • GUSBCS_HNPCEN : usb_regs.h
  • GUSBCS_SRPCEN : usb_regs.h
  • GUSBCS_TOC : usb_regs.h
  • GUSBCS_UTT : usb_regs.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • HACHINT_HACHINT : usb_regs.h
  • HACHINTEN_CINTEN : usb_regs.h
  • HC_BBERR : usb_core.h
  • HC_DTGERR : usb_core.h
  • HC_ERROR : usbh_hcs.h
  • HC_HALTED : usb_core.h
  • HC_IDLE : usb_core.h
  • HC_MAX : usbh_hcs.h
  • HC_MAX_PACKET_COUNT : usb_core.h
  • HC_NAK : usb_core.h
  • HC_NYET : usb_core.h
  • HC_OK : usbh_hcs.h
  • HC_PID_DATA0 : usb_defines.h
  • HC_PID_DATA1 : usb_defines.h
  • HC_PID_DATA2 : usb_defines.h
  • HC_PID_SETUP : usb_defines.h
  • HC_STALL : usb_core.h
  • hc_status_enum : usb_core.h
  • HC_TRACERR : usb_core.h
  • HC_USED : usbh_hcs.h
  • HC_USED_MASK : usbh_hcs.h
  • HC_XF : usb_core.h
  • HCCHAR_BULK : usb_defines.h
  • HCCHAR_CTRL : usb_defines.h
  • HCCHAR_INTR : usb_defines.h
  • HCCHAR_ISOC : usb_defines.h
  • hcd_init() : usbh_core.h , usbh_core.c
  • hcd_is_device_connected() : usbh_core.h , usbh_core.c
  • hcd_submit_request() : usbh_ctrl.c , usbh_ctrl.h
  • hcd_urb_state_get() : usbh_core.h , usbh_core.c
  • hcd_xfer_count_get() : usbh_core.h , usbh_core.c
  • HCHCTL_CDIS : usb_regs.h
  • HCHCTL_CEN : usb_regs.h
  • HCHCTL_DAR : usb_regs.h
  • HCHCTL_EPDIR : usb_regs.h
  • HCHCTL_EPNUM : usb_regs.h
  • HCHCTL_EPTYPE : usb_regs.h
  • HCHCTL_LSD : usb_regs.h
  • HCHCTL_MPC : usb_regs.h
  • HCHCTL_MPL : usb_regs.h
  • HCHCTL_ODDFRM : usb_regs.h
  • HCHINTEN_ACKIE : usb_regs.h
  • HCHINTEN_BBERIE : usb_regs.h
  • HCHINTEN_CHIE : usb_regs.h
  • HCHINTEN_DTERIE : usb_regs.h
  • HCHINTEN_NAKIE : usb_regs.h
  • HCHINTEN_NYETIE : usb_regs.h
  • HCHINTEN_REQOVRIE : usb_regs.h
  • HCHINTEN_STALLIE : usb_regs.h
  • HCHINTEN_TFIE : usb_regs.h
  • HCHINTEN_USBERIE : usb_regs.h
  • HCHINTF_ACK : usb_regs.h
  • HCHINTF_BBER : usb_regs.h
  • HCHINTF_CH : usb_regs.h
  • HCHINTF_DTER : usb_regs.h
  • HCHINTF_NAK : usb_regs.h
  • HCHINTF_NYET : usb_regs.h
  • HCHINTF_REQOVR : usb_regs.h
  • HCHINTF_STALL : usb_regs.h
  • HCHINTF_TF : usb_regs.h
  • HCHINTF_USBER : usb_regs.h
  • HCHLEN_DPID : usb_regs.h
  • HCHLEN_PCNT : usb_regs.h
  • HCHLEN_TLEN : usb_regs.h
  • HCTL_CLKSEL : usb_regs.h
  • HCTLR_30_60_MHZ : usb_defines.h
  • HCTLR_48_MHZ : usb_defines.h
  • HCTLR_6_MHZ : usb_defines.h
  • HFINFR_FRNUM : usb_regs.h
  • HFINFR_FRT : usb_regs.h
  • HFT_FRI : usb_regs.h
  • HID_BOOT_CODE : usb_std.h
  • HID_CLASS : usbh_core.h
  • HID_KEYBRD_BOOT_CODE : usb_std.h
  • HID_MOUSE_BOOT_CODE : usb_std.h
  • HIGHBYTE : usbd_std.h
  • HNPTFLEN_HNPTXFD : usb_regs.h
  • HNPTFLEN_HNPTXRSAR : usb_regs.h
  • HNPTFQSTAT_CNUM : usb_regs.h
  • HNPTFQSTAT_EPNUM : usb_regs.h
  • HNPTFQSTAT_NPTXFS : usb_regs.h
  • HNPTFQSTAT_NPTXRQS : usb_regs.h
  • HNPTFQSTAT_NPTXRQTOP : usb_regs.h
  • HNPTFQSTAT_TMF : usb_regs.h
  • HNPTFQSTAT_TYPE : usb_regs.h
  • HOST_CLASS : usbh_core.h
  • HOST_CLASS_REQUEST : usbh_core.h
  • HOST_DETECT_DEV_SPEED : usbh_core.h
  • HOST_DEV_ATTACHED : usbh_core.h
  • HOST_DEV_DETACHED : usbh_core.h
  • HOST_ENUMERATION : usbh_core.h
  • HOST_ERROR : usbh_core.h
  • HOST_EVENT_ATTACHED : usbh_core.h
  • HOST_EVENT_CLASS : usbh_core.h
  • HOST_EVENT_CLASS_REQ : usbh_core.h
  • HOST_EVENT_DEV_DETACHED : usbh_core.h
  • host_event_enum : usbh_core.h
  • HOST_EVENT_ENUM : usbh_core.h
  • HOST_EVENT_ERROR : usbh_core.h
  • HOST_EVENT_IDLE : usbh_core.h
  • HOST_EVENT_USER_INPUT : usbh_core.h
  • HOST_FSM_ID : usbh_core.h
  • host_handle_table : usbh_core.c
  • HOST_HANDLE_TABLE_SIZE : usbh_core.h
  • HOST_IDLE : usbh_core.h
  • HOST_MODE : usb_defines.h
  • host_state_enum : usbh_core.h
  • host_state_handle : usbh_core.c
  • host_state_polling_fun() : usbh_core.c , usbh_core.h
  • HOST_SUSPENDED : usbh_core.h
  • HOST_USER_CLASS_ACTIVE : usbh_core.h
  • HOST_USER_CLASS_SELECTED : usbh_core.h
  • HOST_USER_CONNECTION : usbh_core.h
  • HOST_USER_DISCONNECTION : usbh_core.h
  • HOST_USER_INPUT : usbh_core.h
  • HOST_USER_SELECT_CONFIGURATION : usbh_core.h
  • HOST_USER_UNRECOVERED_ERROR : usbh_core.h
  • HPCS_PCD : usb_regs.h
  • HPCS_PCST : usb_regs.h
  • HPCS_PE : usb_regs.h
  • HPCS_PEDC : usb_regs.h
  • HPCS_PLST : usb_regs.h
  • HPCS_PP : usb_regs.h
  • HPCS_PREM : usb_regs.h
  • HPCS_PRST : usb_regs.h
  • HPCS_PS : usb_regs.h
  • HPCS_PSP : usb_regs.h
  • HPRT_PRTSPD_FULL_SPEED : usb_defines.h
  • HPRT_PRTSPD_HIGH_SPEED : usb_defines.h
  • HPRT_PRTSPD_LOW_SPEED : usb_defines.h
  • HPTFLEN_HPTXFD : usb_regs.h
  • HPTFLEN_HPTXFSAR : usb_regs.h
  • HPTFQSTAT_CNUM : usb_regs.h
  • HPTFQSTAT_EPNUM : usb_regs.h
  • HPTFQSTAT_OEFRM : usb_regs.h
  • HPTFQSTAT_PTXFS : usb_regs.h
  • HPTFQSTAT_PTXREQS : usb_regs.h
  • HPTFQSTAT_PTXREQT : usb_regs.h
  • HPTFQSTAT_TMF : usb_regs.h
  • HPTFQSTAT_TYPE : usb_regs.h
  • HRFC_CMSK : gd32f3x0_rtc.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C0 : gd32f3x0_i2c.h
  • I2C1 : gd32f3x0_i2c.h
  • I2C2 : gd32f3x0_i2c.h
  • i2c_ack_config() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_ACK_DISABLE : gd32f3x0_i2c.h
  • I2C_ACK_ENABLE : gd32f3x0_i2c.h
  • i2c_ackpos_config() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_ACKPOS_CURRENT : gd32f3x0_i2c.h
  • I2C_ACKPOS_NEXT : gd32f3x0_i2c.h
  • I2C_ADDFORMAT_10BITS : gd32f3x0_i2c.h
  • I2C_ADDFORMAT_7BITS : gd32f3x0_i2c.h
  • I2C_ARP_DISABLE : gd32f3x0_i2c.h
  • I2C_ARP_ENABLE : gd32f3x0_i2c.h
  • I2C_CKCFG : gd32f3x0_i2c.h
  • I2C_CKCFG_CLKC : gd32f3x0_i2c.h
  • I2C_CKCFG_DTCY : gd32f3x0_i2c.h
  • I2C_CKCFG_FAST : gd32f3x0_i2c.h
  • i2c_clock_config() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_CTL0 : gd32f3x0_i2c.h
  • I2C_CTL0_ACKEN : gd32f3x0_i2c.h
  • I2C_CTL0_ARPEN : gd32f3x0_i2c.h
  • I2C_CTL0_DISSTRC : gd32f3x0_i2c.h
  • I2C_CTL0_GCEN : gd32f3x0_i2c.h
  • I2C_CTL0_I2CEN : gd32f3x0_i2c.h
  • I2C_CTL0_PECEN : gd32f3x0_i2c.h
  • I2C_CTL0_PECTRANS : gd32f3x0_i2c.h
  • I2C_CTL0_POAP : gd32f3x0_i2c.h
  • I2C_CTL0_SALT : gd32f3x0_i2c.h
  • I2C_CTL0_SMBEN : gd32f3x0_i2c.h
  • I2C_CTL0_SMBSEL : gd32f3x0_i2c.h
  • I2C_CTL0_SRESET : gd32f3x0_i2c.h
  • I2C_CTL0_START : gd32f3x0_i2c.h
  • I2C_CTL0_STOP : gd32f3x0_i2c.h
  • I2C_CTL1 : gd32f3x0_i2c.h
  • I2C_CTL1_BUFIE : gd32f3x0_i2c.h
  • I2C_CTL1_DMALST : gd32f3x0_i2c.h
  • I2C_CTL1_DMAON : gd32f3x0_i2c.h
  • I2C_CTL1_ERRIE : gd32f3x0_i2c.h
  • I2C_CTL1_EVIE : gd32f3x0_i2c.h
  • I2C_CTL1_I2CCLK : gd32f3x0_i2c.h
  • I2C_DATA : gd32f3x0_i2c.h
  • i2c_data_receive() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_data_transmit() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_DATA_TRB : gd32f3x0_i2c.h
  • i2c_deinit() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_disable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_dma_enable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_dma_last_transfer_enable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_DMA_OFF : gd32f3x0_i2c.h
  • I2C_DMA_ON : gd32f3x0_i2c.h
  • I2C_DMALST_OFF : gd32f3x0_i2c.h
  • I2C_DMALST_ON : gd32f3x0_i2c.h
  • I2C_DTCY_16_9 : gd32f3x0_i2c.h
  • I2C_DTCY_2 : gd32f3x0_i2c.h
  • I2C_DUADEN_DISABLE : gd32f3x0_i2c.h
  • I2C_DUADEN_ENABLE : gd32f3x0_i2c.h
  • i2c_dualaddr_enable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_enable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_FAST_MODE_PLUS_DISABLE : gd32f3x0_i2c.h
  • I2C_FAST_MODE_PLUS_ENABLE : gd32f3x0_i2c.h
  • I2C_FLAG_ADD10SEND : gd32f3x0_i2c.h
  • I2C_FLAG_ADDSEND : gd32f3x0_i2c.h
  • I2C_FLAG_AERR : gd32f3x0_i2c.h
  • I2C_FLAG_BERR : gd32f3x0_i2c.h
  • I2C_FLAG_BTC : gd32f3x0_i2c.h
  • i2c_flag_clear() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_FLAG_DEFSMB : gd32f3x0_i2c.h
  • I2C_FLAG_DUMOD : gd32f3x0_i2c.h
  • i2c_flag_get() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_FLAG_HSTSMB : gd32f3x0_i2c.h
  • I2C_FLAG_I2CBSY : gd32f3x0_i2c.h
  • I2C_FLAG_LOSTARB : gd32f3x0_i2c.h
  • I2C_FLAG_MASK : gd32f3x0_i2c.c
  • I2C_FLAG_MASTER : gd32f3x0_i2c.h
  • I2C_FLAG_OUERR : gd32f3x0_i2c.h
  • I2C_FLAG_PECERR : gd32f3x0_i2c.h
  • I2C_FLAG_RBNE : gd32f3x0_i2c.h
  • I2C_FLAG_RXGC : gd32f3x0_i2c.h
  • I2C_FLAG_SBSEND : gd32f3x0_i2c.h
  • I2C_FLAG_SMBALT : gd32f3x0_i2c.h
  • I2C_FLAG_SMBTO : gd32f3x0_i2c.h
  • I2C_FLAG_STPDET : gd32f3x0_i2c.h
  • I2C_FLAG_TBE : gd32f3x0_i2c.h
  • I2C_FLAG_TRS : gd32f3x0_i2c.h
  • I2C_FMPCFG : gd32f3x0_i2c.h
  • I2C_FMPCFG_FMPEN : gd32f3x0_i2c.h
  • I2C_GCEN_DISABLE : gd32f3x0_i2c.h
  • I2C_GCEN_ENABLE : gd32f3x0_i2c.h
  • I2C_I2CMODE_ENABLE : gd32f3x0_i2c.h
  • I2C_INT_BUF : gd32f3x0_i2c.h
  • I2C_INT_ERR : gd32f3x0_i2c.h
  • I2C_INT_EV : gd32f3x0_i2c.h
  • I2C_INT_FLAG_ADD10SEND : gd32f3x0_i2c.h
  • I2C_INT_FLAG_ADDSEND : gd32f3x0_i2c.h
  • I2C_INT_FLAG_AERR : gd32f3x0_i2c.h
  • I2C_INT_FLAG_BERR : gd32f3x0_i2c.h
  • I2C_INT_FLAG_BTC : gd32f3x0_i2c.h
  • I2C_INT_FLAG_LOSTARB : gd32f3x0_i2c.h
  • I2C_INT_FLAG_OUERR : gd32f3x0_i2c.h
  • I2C_INT_FLAG_PECERR : gd32f3x0_i2c.h
  • I2C_INT_FLAG_RBNE : gd32f3x0_i2c.h
  • I2C_INT_FLAG_SBSEND : gd32f3x0_i2c.h
  • I2C_INT_FLAG_SMBALT : gd32f3x0_i2c.h
  • I2C_INT_FLAG_SMBTO : gd32f3x0_i2c.h
  • I2C_INT_FLAG_STPDET : gd32f3x0_i2c.h
  • I2C_INT_FLAG_TBE : gd32f3x0_i2c.h
  • i2c_interrupt_disable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_interrupt_enable() : gd32f3x0_i2c.c , gd32f3x0_i2c.h
  • i2c_interrupt_flag_clear() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_interrupt_flag_get() : gd32f3x0_i2c.c , gd32f3x0_i2c.h
  • i2c_master_addressing() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_mode_addr_config() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_PEC_DISABLE : gd32f3x0_i2c.h
  • i2c_pec_enable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_PEC_ENABLE : gd32f3x0_i2c.h
  • i2c_pec_transfer_enable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_pec_value_get() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_PECTRANS_DISABLE : gd32f3x0_i2c.h
  • I2C_PECTRANS_ENABLE : gd32f3x0_i2c.h
  • I2C_RECEIVER : gd32f3x0_i2c.h
  • I2C_RT : gd32f3x0_i2c.h
  • I2C_RT_RISETIME : gd32f3x0_i2c.h
  • I2C_SADDR0 : gd32f3x0_i2c.h
  • I2C_SADDR0_ADDFORMAT : gd32f3x0_i2c.h
  • I2C_SADDR0_ADDRESS : gd32f3x0_i2c.h
  • I2C_SADDR0_ADDRESS0 : gd32f3x0_i2c.h
  • I2C_SADDR0_ADDRESS_H : gd32f3x0_i2c.h
  • I2C_SADDR1 : gd32f3x0_i2c.h
  • I2C_SADDR1_ADDRESS2 : gd32f3x0_i2c.h
  • I2C_SADDR1_DUADEN : gd32f3x0_i2c.h
  • I2C_SALTSEND_DISABLE : gd32f3x0_i2c.h
  • I2C_SALTSEND_ENABLE : gd32f3x0_i2c.h
  • I2C_SCLSTRETCH_DISABLE : gd32f3x0_i2c.h
  • I2C_SCLSTRETCH_ENABLE : gd32f3x0_i2c.h
  • i2c_slave_response_to_gcall_config() : gd32f3x0_i2c.c , gd32f3x0_i2c.h
  • i2c_smbus_arp_enable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_SMBUS_DEVICE : gd32f3x0_i2c.h
  • I2C_SMBUS_HOST : gd32f3x0_i2c.h
  • i2c_smbus_issue_alert() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_smbus_type_config() : gd32f3x0_i2c.c , gd32f3x0_i2c.h
  • I2C_SMBUSMODE_ENABLE : gd32f3x0_i2c.h
  • i2c_software_reset_config() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_SRESET_RESET : gd32f3x0_i2c.h
  • I2C_SRESET_SET : gd32f3x0_i2c.h
  • i2c_start_on_bus() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_STAT0 : gd32f3x0_i2c.h
  • I2C_STAT0_ADD10SEND : gd32f3x0_i2c.h
  • I2C_STAT0_ADDSEND : gd32f3x0_i2c.h
  • I2C_STAT0_AERR : gd32f3x0_i2c.h
  • I2C_STAT0_BERR : gd32f3x0_i2c.h
  • I2C_STAT0_BTC : gd32f3x0_i2c.h
  • I2C_STAT0_LOSTARB : gd32f3x0_i2c.h
  • I2C_STAT0_OUERR : gd32f3x0_i2c.h
  • I2C_STAT0_PECERR : gd32f3x0_i2c.h
  • I2C_STAT0_RBNE : gd32f3x0_i2c.h
  • I2C_STAT0_SBSEND : gd32f3x0_i2c.h
  • I2C_STAT0_SMBALT : gd32f3x0_i2c.h
  • I2C_STAT0_SMBTO : gd32f3x0_i2c.h
  • I2C_STAT0_STPDET : gd32f3x0_i2c.h
  • I2C_STAT0_TBE : gd32f3x0_i2c.h
  • I2C_STAT1 : gd32f3x0_i2c.h
  • I2C_STAT1_DEFSMB : gd32f3x0_i2c.h
  • I2C_STAT1_DUMODF : gd32f3x0_i2c.h
  • I2C_STAT1_ECV : gd32f3x0_i2c.h
  • I2C_STAT1_HSTSMB : gd32f3x0_i2c.h
  • I2C_STAT1_I2CBSY : gd32f3x0_i2c.h
  • I2C_STAT1_MASTER : gd32f3x0_i2c.h
  • I2C_STAT1_RXGC : gd32f3x0_i2c.h
  • I2C_STAT1_TRS : gd32f3x0_i2c.h
  • i2c_stop_on_bus() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_stretch_scl_low_config() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • I2C_TRANSMITTER : gd32f3x0_i2c.h
  • I2CCLK_MAX : gd32f3x0_i2c.c
  • I2S_INIT_MASK : gd32f3x0_spi.c
  • I2S_INT_FLAG_TXURERR : gd32f3x0_spi.h
  • IDX_ADDAPB1EN : gd32f3x0_rcu.h
  • IDX_ADDAPB1RST : gd32f3x0_rcu.h
  • IDX_ADDCTL : gd32f3x0_rcu.h
  • IDX_ADDINT : gd32f3x0_rcu.h
  • IDX_AHBEN : gd32f3x0_rcu.h
  • IDX_AHBRST : gd32f3x0_rcu.h
  • IDX_APB1EN : gd32f3x0_rcu.h
  • IDX_APB1RST : gd32f3x0_rcu.h
  • IDX_APB2EN : gd32f3x0_rcu.h
  • IDX_APB2RST : gd32f3x0_rcu.h
  • IDX_BDCTL : gd32f3x0_rcu.h
  • IDX_CFG0 : gd32f3x0_rcu.h
  • IDX_CFG2 : gd32f3x0_rcu.h
  • IDX_CTL0 : gd32f3x0_rcu.h
  • IDX_CTL1 : gd32f3x0_rcu.h
  • IDX_INT : gd32f3x0_rcu.h
  • IDX_RSTSCK : gd32f3x0_rcu.h
  • inverting_input_enum : gd32f3x0_cmp.h
  • IOFFX_IOFF : gd32f3x0_adc.h
  • IS_NOT_EP0 : usbd_std.h
  • ISQ_IL : gd32f3x0_adc.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • local_buffer : usbh_std.c
  • LOCATE_DIEPCTL : usb_regs.h
  • LOCATE_DIEPINTF : usb_regs.h
  • LOCATE_DIEPLEN : usb_regs.h
  • LOCATE_DIEPTFLEN : usb_regs.h
  • LOCATE_DIEPxTFSTAT : usb_regs.h
  • LOCATE_DOEPCTL : usb_regs.h
  • LOCATE_DOEPINTF : usb_regs.h
  • LOCATE_DOEPLEN : usb_regs.h
  • LOCATE_FIFO : usb_regs.h
  • LOCATE_HCHCTL : usb_regs.h
  • LOCATE_HCHINTEN : usb_regs.h
  • LOCATE_HCHINTF : usb_regs.h
  • LOCATE_HCHLEN : usb_regs.h
  • LOWBYTE : usbd_std.h
  • LXTAL_STARTUP_TIMEOUT : gd32f3x0_rcu.c


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MAX_USBH_STATE_STACK_DEEP : usbh_core.h
  • MAX_USBH_STATE_TABLE_NUM : usbh_core.h
  • MSC_CLASS : usbh_core.h
  • MSC_PROTOCOL : usbh_core.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NODATA_STAGE_TIMEOUT : usb_std.h
  • NULL : usb_defines.h
  • NVIC_AIRCR_VECTKEY_MASK : gd32f3x0_misc.h
  • nvic_irq_disable() : gd32f3x0_misc.h , gd32f3x0_misc.c
  • nvic_irq_enable() : gd32f3x0_misc.h , gd32f3x0_misc.c
  • NVIC_PRIGROUP_PRE0_SUB4 : gd32f3x0_misc.h
  • NVIC_PRIGROUP_PRE1_SUB3 : gd32f3x0_misc.h
  • NVIC_PRIGROUP_PRE2_SUB2 : gd32f3x0_misc.h
  • NVIC_PRIGROUP_PRE3_SUB1 : gd32f3x0_misc.h
  • NVIC_PRIGROUP_PRE4_SUB0 : gd32f3x0_misc.h
  • nvic_priority_group_set() : gd32f3x0_misc.h , gd32f3x0_misc.c
  • nvic_vector_table_set() : gd32f3x0_misc.h , gd32f3x0_misc.c
  • NVIC_VECTTAB_FLASH : gd32f3x0_misc.h
  • NVIC_VECTTAB_OFFSET_MASK : gd32f3x0_misc.h
  • NVIC_VECTTAB_RAM : gd32f3x0_misc.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OB : gd32f3x0_fmc.h
  • OB_BOOT1_SET_0 : gd32f3x0_fmc.h
  • OB_BOOT1_SET_1 : gd32f3x0_fmc.h
  • OB_DATA_ADDR0 : gd32f3x0_fmc.h
  • OB_DATA_ADDR1 : gd32f3x0_fmc.h
  • ob_data_get() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • ob_data_program() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • OB_DEEPSLEEP_NRST : gd32f3x0_fmc.h
  • OB_DEEPSLEEP_RST : gd32f3x0_fmc.h
  • ob_erase() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • OB_FWDGT_HW : gd32f3x0_fmc.h
  • OB_FWDGT_SW : gd32f3x0_fmc.h
  • OB_HWP : gd32f3x0_fmc.h
  • ob_lock() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • OB_LWP : gd32f3x0_fmc.h
  • ob_obstat_plevel_get() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • OB_OBSTAT_PLEVEL_HIGH : gd32f3x0_fmc.h
  • OB_OBSTAT_PLEVEL_LOW : gd32f3x0_fmc.h
  • OB_OBSTAT_PLEVEL_NO : gd32f3x0_fmc.h
  • ob_reset() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • ob_security_protection_config() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • OB_SPC : gd32f3x0_fmc.h
  • OB_SRAM_PARITY_DISABLE : gd32f3x0_fmc.h
  • OB_SRAM_PARITY_ENABLE : gd32f3x0_fmc.h
  • OB_STDBY_NRST : gd32f3x0_fmc.h
  • OB_STDBY_RST : gd32f3x0_fmc.h
  • ob_unlock() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • OB_USER : gd32f3x0_fmc.h
  • ob_user_get() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • OB_USER_MASK : gd32f3x0_fmc.h
  • ob_user_write() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • OB_VDDA_DISABLE : gd32f3x0_fmc.h
  • OB_VDDA_ENABLE : gd32f3x0_fmc.h
  • OB_WP0 : gd32f3x0_fmc.h
  • OB_WP1 : gd32f3x0_fmc.h
  • ob_write_protection_enable() : gd32f3x0_fmc.c , gd32f3x0_fmc.h
  • ob_write_protection_get() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • OBUSER_BOOT1_N : gd32f3x0_fmc.h
  • OBUSER_NRST_DPSLP : gd32f3x0_fmc.h
  • OBUSER_NRST_STDBY : gd32f3x0_fmc.h
  • OBUSER_NWDG_HW : gd32f3x0_fmc.h
  • OBUSER_SRAM_PARITY : gd32f3x0_fmc.h
  • OBUSER_VDDA_VISOR : gd32f3x0_fmc.h
  • only_state_move() : usbh_core.h , usbh_core.c
  • operating_mode_enum : gd32f3x0_cmp.h
  • OSC_STARTUP_TIMEOUT : gd32f3x0_rcu.c
  • OSPD_OSPD0 : gd32f3x0_gpio.h
  • OTG_MODE : usb_defines.h
  • OVSAMPCTL_OVSR : gd32f3x0_adc.h
  • OVSAMPCTL_OVSS : gd32f3x0_adc.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • PMU : gd32f3x0_pmu.h
  • pmu_backup_write_disable() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_backup_write_enable() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • PMU_CS : gd32f3x0_pmu.h
  • PMU_CS_HDRF : gd32f3x0_pmu.h
  • PMU_CS_HDSRF : gd32f3x0_pmu.h
  • PMU_CS_LDOVSRF : gd32f3x0_pmu.h
  • PMU_CS_LDRF : gd32f3x0_pmu.h
  • PMU_CS_LVDF : gd32f3x0_pmu.h
  • PMU_CS_STBF : gd32f3x0_pmu.h
  • PMU_CS_WUF : gd32f3x0_pmu.h
  • PMU_CS_WUPEN0 : gd32f3x0_pmu.h
  • PMU_CS_WUPEN1 : gd32f3x0_pmu.h
  • PMU_CS_WUPEN4 : gd32f3x0_pmu.h
  • PMU_CS_WUPEN5 : gd32f3x0_pmu.h
  • PMU_CS_WUPEN6 : gd32f3x0_pmu.h
  • PMU_CTL : gd32f3x0_pmu.h
  • PMU_CTL_BKPWEN : gd32f3x0_pmu.h
  • PMU_CTL_HDEN : gd32f3x0_pmu.h
  • PMU_CTL_HDS : gd32f3x0_pmu.h
  • PMU_CTL_LDEN : gd32f3x0_pmu.h
  • PMU_CTL_LDLP : gd32f3x0_pmu.h
  • PMU_CTL_LDNP : gd32f3x0_pmu.h
  • PMU_CTL_LDOLP : gd32f3x0_pmu.h
  • PMU_CTL_LDOVS : gd32f3x0_pmu.h
  • PMU_CTL_LVDEN : gd32f3x0_pmu.h
  • PMU_CTL_LVDT : gd32f3x0_pmu.h
  • PMU_CTL_STBMOD : gd32f3x0_pmu.h
  • PMU_CTL_STBRST : gd32f3x0_pmu.h
  • PMU_CTL_WURST : gd32f3x0_pmu.h
  • pmu_deinit() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_flag_clear() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_flag_get() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • PMU_FLAG_HDR : gd32f3x0_pmu.h
  • PMU_FLAG_HDSR : gd32f3x0_pmu.h
  • PMU_FLAG_LDOVSR : gd32f3x0_pmu.h
  • PMU_FLAG_LDR : gd32f3x0_pmu.h
  • PMU_FLAG_LVD : gd32f3x0_pmu.h
  • PMU_FLAG_RESET_STANDBY : gd32f3x0_pmu.h
  • PMU_FLAG_RESET_WAKEUP : gd32f3x0_pmu.h
  • PMU_FLAG_STANDBY : gd32f3x0_pmu.h
  • PMU_FLAG_WAKEUP : gd32f3x0_pmu.h
  • PMU_HIGHDR_SWITCH_EN : gd32f3x0_pmu.h
  • PMU_HIGHDR_SWITCH_NONE : gd32f3x0_pmu.h
  • pmu_highdriver_mode_disable() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_highdriver_mode_enable() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_highdriver_switch_select() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • PMU_LDO_LOWPOWER : gd32f3x0_pmu.h
  • PMU_LDO_NORMAL : gd32f3x0_pmu.h
  • pmu_ldo_output_select() : gd32f3x0_pmu.c , gd32f3x0_pmu.h
  • PMU_LDOVS_HIGH : gd32f3x0_pmu.h
  • PMU_LDOVS_LOW : gd32f3x0_pmu.h
  • PMU_LDOVS_MID : gd32f3x0_pmu.h
  • PMU_LDRF_LOWDRIVER : gd32f3x0_pmu.h
  • PMU_LDRF_NORMAL : gd32f3x0_pmu.h
  • PMU_LOWDR_LOWPWR : gd32f3x0_pmu.h
  • PMU_LOWDR_NORMALPWR : gd32f3x0_pmu.h
  • PMU_LOWDRIVER_DISABLE : gd32f3x0_pmu.h
  • PMU_LOWDRIVER_ENABLE : gd32f3x0_pmu.h
  • pmu_lowdriver_mode_disable() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_lowdriver_mode_enable() : gd32f3x0_pmu.c , gd32f3x0_pmu.h
  • pmu_lowpower_driver_config() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_lvd_disable() : gd32f3x0_pmu.c , gd32f3x0_pmu.h
  • pmu_lvd_select() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • PMU_LVDT_0 : gd32f3x0_pmu.h
  • PMU_LVDT_1 : gd32f3x0_pmu.h
  • PMU_LVDT_2 : gd32f3x0_pmu.h
  • PMU_LVDT_3 : gd32f3x0_pmu.h
  • PMU_LVDT_4 : gd32f3x0_pmu.h
  • PMU_LVDT_5 : gd32f3x0_pmu.h
  • PMU_LVDT_6 : gd32f3x0_pmu.h
  • PMU_LVDT_7 : gd32f3x0_pmu.h
  • PMU_NORMALDR_LOWPWR : gd32f3x0_pmu.h
  • PMU_NORMALDR_NORMALPWR : gd32f3x0_pmu.h
  • pmu_normalpower_driver_config() : gd32f3x0_pmu.c , gd32f3x0_pmu.h
  • pmu_to_deepsleepmode() : gd32f3x0_pmu.c , gd32f3x0_pmu.h
  • pmu_to_sleepmode() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_to_standbymode() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • PMU_WAKEUP_PIN0 : gd32f3x0_pmu.h
  • PMU_WAKEUP_PIN1 : gd32f3x0_pmu.h
  • PMU_WAKEUP_PIN4 : gd32f3x0_pmu.h
  • PMU_WAKEUP_PIN5 : gd32f3x0_pmu.h
  • PMU_WAKEUP_PIN6 : gd32f3x0_pmu.h
  • pmu_wakeup_pin_disable() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_wakeup_pin_enable() : gd32f3x0_pmu.c , gd32f3x0_pmu.h
  • PSC_FACTOR_A : gd32f3x0_rtc.h
  • PSC_FACTOR_S : gd32f3x0_rtc.h
  • PSC_PSC : gd32f3x0_fwdgt.h
  • PUD_PUPD : gd32f3x0_gpio.h
  • PWRCLKCTL_SHCLK : usb_regs.h
  • PWRCLKCTL_SUCLK : usb_regs.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- q -

  • qspi_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • qspi_enable() : gd32f3x0_spi.c , gd32f3x0_spi.h
  • qspi_io23_output_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • qspi_io23_output_enable() : gd32f3x0_spi.c , gd32f3x0_spi.h
  • qspi_read_enable() : gd32f3x0_spi.c , gd32f3x0_spi.h
  • qspi_write_enable() : gd32f3x0_spi.h , gd32f3x0_spi.c


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • RCU : gd32f3x0_rcu.h
  • RCU_ADC : gd32f3x0_rcu.h
  • RCU_ADC_CKAPB2_DIV2 : gd32f3x0_rcu.h
  • RCU_ADC_CKAPB2_DIV4 : gd32f3x0_rcu.h
  • RCU_ADC_CKAPB2_DIV6 : gd32f3x0_rcu.h
  • RCU_ADC_CKAPB2_DIV8 : gd32f3x0_rcu.h
  • rcu_adc_clock_config() : gd32f3x0_rcu.c , gd32f3x0_rcu.h
  • rcu_adc_clock_enum : gd32f3x0_rcu.h
  • RCU_ADC_IRC28M_DIV1 : gd32f3x0_rcu.h
  • RCU_ADC_IRC28M_DIV2 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV2 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV3 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV4 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV5 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV6 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV7 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV8 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV9 : gd32f3x0_rcu.h
  • RCU_ADCCK_IRC28M : gd32f3x0_rcu.h
  • RCU_ADCCK_IRC28M_DIV2 : gd32f3x0_rcu.h
  • RCU_ADCRST : gd32f3x0_rcu.h
  • RCU_ADCSRC_APB2DIV : gd32f3x0_rcu.h
  • RCU_ADCSRC_IRC28M : gd32f3x0_rcu.h
  • RCU_ADDAPB1EN : gd32f3x0_rcu.h
  • RCU_ADDAPB1EN_CTCEN : gd32f3x0_rcu.h
  • RCU_ADDAPB1EN_I2C2EN : gd32f3x0_rcu.h
  • RCU_ADDAPB1RST : gd32f3x0_rcu.h
  • RCU_ADDAPB1RST_CTCRST : gd32f3x0_rcu.h
  • RCU_ADDAPB1RST_I2C2RST : gd32f3x0_rcu.h
  • RCU_ADDCTL : gd32f3x0_rcu.h
  • RCU_ADDCTL_CK48MSEL : gd32f3x0_rcu.h
  • RCU_ADDCTL_IRC48MCALIB : gd32f3x0_rcu.h
  • RCU_ADDCTL_IRC48MEN : gd32f3x0_rcu.h
  • RCU_ADDCTL_IRC48MSTB : gd32f3x0_rcu.h
  • RCU_ADDINT : gd32f3x0_rcu.h
  • RCU_ADDINT_IRC48MSTBIC : gd32f3x0_rcu.h
  • RCU_ADDINT_IRC48MSTBIE : gd32f3x0_rcu.h
  • RCU_ADDINT_IRC48MSTBIF : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV1 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV128 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV16 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV2 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV256 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV4 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV512 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV64 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV8 : gd32f3x0_rcu.h
  • rcu_ahb_clock_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_AHBEN : gd32f3x0_rcu.h
  • RCU_AHBEN_CRCEN : gd32f3x0_rcu.h
  • RCU_AHBEN_DMAEN : gd32f3x0_rcu.h
  • RCU_AHBEN_FMCSPEN : gd32f3x0_rcu.h
  • RCU_AHBEN_PAEN : gd32f3x0_rcu.h
  • RCU_AHBEN_PBEN : gd32f3x0_rcu.h
  • RCU_AHBEN_PCEN : gd32f3x0_rcu.h
  • RCU_AHBEN_PDEN : gd32f3x0_rcu.h
  • RCU_AHBEN_PFEN : gd32f3x0_rcu.h
  • RCU_AHBEN_SRAMSPEN : gd32f3x0_rcu.h
  • RCU_AHBEN_TSIEN : gd32f3x0_rcu.h
  • RCU_AHBEN_USBFS : gd32f3x0_rcu.h
  • RCU_AHBRST : gd32f3x0_rcu.h
  • RCU_AHBRST_PARST : gd32f3x0_rcu.h
  • RCU_AHBRST_PBRST : gd32f3x0_rcu.h
  • RCU_AHBRST_PCRST : gd32f3x0_rcu.h
  • RCU_AHBRST_PDRST : gd32f3x0_rcu.h
  • RCU_AHBRST_PFRST : gd32f3x0_rcu.h
  • RCU_AHBRST_TSIRST : gd32f3x0_rcu.h
  • RCU_AHBRST_USBFSRST : gd32f3x0_rcu.h
  • rcu_all_reset_flag_clear() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_APB1_CKAHB_DIV1 : gd32f3x0_rcu.h
  • RCU_APB1_CKAHB_DIV16 : gd32f3x0_rcu.h
  • RCU_APB1_CKAHB_DIV2 : gd32f3x0_rcu.h
  • RCU_APB1_CKAHB_DIV4 : gd32f3x0_rcu.h
  • RCU_APB1_CKAHB_DIV8 : gd32f3x0_rcu.h
  • rcu_apb1_clock_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_APB1EN : gd32f3x0_rcu.h
  • RCU_APB1EN_CECEN : gd32f3x0_rcu.h
  • RCU_APB1EN_DACEN : gd32f3x0_rcu.h
  • RCU_APB1EN_I2C0EN : gd32f3x0_rcu.h
  • RCU_APB1EN_I2C1EN : gd32f3x0_rcu.h
  • RCU_APB1EN_PMUEN : gd32f3x0_rcu.h
  • RCU_APB1EN_SPI1EN : gd32f3x0_rcu.h
  • RCU_APB1EN_SPI2EN : gd32f3x0_rcu.h
  • RCU_APB1EN_TIMER13EN : gd32f3x0_rcu.h
  • RCU_APB1EN_TIMER1EN : gd32f3x0_rcu.h
  • RCU_APB1EN_TIMER2EN : gd32f3x0_rcu.h
  • RCU_APB1EN_TIMER5EN : gd32f3x0_rcu.h
  • RCU_APB1EN_USART1EN : gd32f3x0_rcu.h
  • RCU_APB1EN_WWDGTEN : gd32f3x0_rcu.h
  • RCU_APB1RST : gd32f3x0_rcu.h
  • RCU_APB1RST_CECRST : gd32f3x0_rcu.h
  • RCU_APB1RST_DACRST : gd32f3x0_rcu.h
  • RCU_APB1RST_I2C0RST : gd32f3x0_rcu.h
  • RCU_APB1RST_I2C1RST : gd32f3x0_rcu.h
  • RCU_APB1RST_PMURST : gd32f3x0_rcu.h
  • RCU_APB1RST_SPI1RST : gd32f3x0_rcu.h
  • RCU_APB1RST_SPI2RST : gd32f3x0_rcu.h
  • RCU_APB1RST_TIMER13RST : gd32f3x0_rcu.h
  • RCU_APB1RST_TIMER1RST : gd32f3x0_rcu.h
  • RCU_APB1RST_TIMER2RST : gd32f3x0_rcu.h
  • RCU_APB1RST_TIMER5RST : gd32f3x0_rcu.h
  • RCU_APB1RST_USART1RST : gd32f3x0_rcu.h
  • RCU_APB1RST_WWDGTRST : gd32f3x0_rcu.h
  • RCU_APB2_CKAHB_DIV1 : gd32f3x0_rcu.h
  • RCU_APB2_CKAHB_DIV16 : gd32f3x0_rcu.h
  • RCU_APB2_CKAHB_DIV2 : gd32f3x0_rcu.h
  • RCU_APB2_CKAHB_DIV4 : gd32f3x0_rcu.h
  • RCU_APB2_CKAHB_DIV8 : gd32f3x0_rcu.h
  • rcu_apb2_clock_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_APB2EN : gd32f3x0_rcu.h
  • RCU_APB2EN_ADCEN : gd32f3x0_rcu.h
  • RCU_APB2EN_CFGCMPEN : gd32f3x0_rcu.h
  • RCU_APB2EN_SPI0EN : gd32f3x0_rcu.h
  • RCU_APB2EN_TIMER0EN : gd32f3x0_rcu.h
  • RCU_APB2EN_TIMER14EN : gd32f3x0_rcu.h
  • RCU_APB2EN_TIMER15EN : gd32f3x0_rcu.h
  • RCU_APB2EN_TIMER16EN : gd32f3x0_rcu.h
  • RCU_APB2EN_USART0EN : gd32f3x0_rcu.h
  • RCU_APB2RST : gd32f3x0_rcu.h
  • RCU_APB2RST_ADCRST : gd32f3x0_rcu.h
  • RCU_APB2RST_CFGRST : gd32f3x0_rcu.h
  • RCU_APB2RST_SPI0RST : gd32f3x0_rcu.h
  • RCU_APB2RST_TIMER0RST : gd32f3x0_rcu.h
  • RCU_APB2RST_TIMER14RST : gd32f3x0_rcu.h
  • RCU_APB2RST_TIMER15RST : gd32f3x0_rcu.h
  • RCU_APB2RST_TIMER16RST : gd32f3x0_rcu.h
  • RCU_APB2RST_USART0RST : gd32f3x0_rcu.h
  • RCU_BDCTL : gd32f3x0_rcu.h
  • RCU_BDCTL_BKPRST : gd32f3x0_rcu.h
  • RCU_BDCTL_LXTALBPS : gd32f3x0_rcu.h
  • RCU_BDCTL_LXTALDRI : gd32f3x0_rcu.h
  • RCU_BDCTL_LXTALEN : gd32f3x0_rcu.h
  • RCU_BDCTL_LXTALSTB : gd32f3x0_rcu.h
  • RCU_BDCTL_RTCEN : gd32f3x0_rcu.h
  • RCU_BDCTL_RTCSRC : gd32f3x0_rcu.h
  • RCU_BIT_POS : gd32f3x0_rcu.h
  • rcu_bkp_reset_disable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_bkp_reset_enable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_cec_clock_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_CECSRC_IRC8M_DIV244 : gd32f3x0_rcu.h
  • RCU_CECSRC_LXTAL : gd32f3x0_rcu.h
  • RCU_CFG0 : gd32f3x0_rcu.h
  • RCU_CFG0_ADCPSC : gd32f3x0_rcu.h
  • RCU_CFG0_AHBPSC : gd32f3x0_rcu.h
  • RCU_CFG0_APB1PSC : gd32f3x0_rcu.h
  • RCU_CFG0_APB2PSC : gd32f3x0_rcu.h
  • RCU_CFG0_CKOUTDIV : gd32f3x0_rcu.h
  • RCU_CFG0_CKOUTSEL : gd32f3x0_rcu.h
  • RCU_CFG0_PLLDV : gd32f3x0_rcu.h
  • RCU_CFG0_PLLMF : gd32f3x0_rcu.h
  • RCU_CFG0_PLLMF4 : gd32f3x0_rcu.h
  • RCU_CFG0_PLLPREDV : gd32f3x0_rcu.h
  • RCU_CFG0_PLLSEL : gd32f3x0_rcu.h
  • RCU_CFG0_SCS : gd32f3x0_rcu.h
  • RCU_CFG0_SCSS : gd32f3x0_rcu.h
  • RCU_CFG0_USBFSPSC : gd32f3x0_rcu.h
  • RCU_CFG1 : gd32f3x0_rcu.h
  • RCU_CFG1_PLLMF5 : gd32f3x0_rcu.h
  • RCU_CFG1_PLLPRESEL : gd32f3x0_rcu.h
  • RCU_CFG1_PREDV : gd32f3x0_rcu.h
  • RCU_CFG2 : gd32f3x0_rcu.h
  • RCU_CFG2_ADCPSC2 : gd32f3x0_rcu.h
  • RCU_CFG2_ADCSEL : gd32f3x0_rcu.h
  • RCU_CFG2_CECSEL : gd32f3x0_rcu.h
  • RCU_CFG2_IRC28MDIV : gd32f3x0_rcu.h
  • RCU_CFG2_USART0SEL : gd32f3x0_rcu.h
  • RCU_CFG2_USBFSPSC2 : gd32f3x0_rcu.h
  • RCU_CFGCMP : gd32f3x0_rcu.h
  • RCU_CFGCMPRST : gd32f3x0_rcu.h
  • rcu_ckout_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_CKOUT_DIV1 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV128 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV16 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV2 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV32 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV4 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV64 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV8 : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_CKPLL_DIV1 : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_CKPLL_DIV2 : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_CKSYS : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_HXTAL : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_IRC28M : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_IRC40K : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_IRC8M : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_LXTAL : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_NONE : gd32f3x0_rcu.h
  • RCU_CKSYSSRC_HXTAL : gd32f3x0_rcu.h
  • RCU_CKSYSSRC_IRC8M : gd32f3x0_rcu.h
  • RCU_CKSYSSRC_PLL : gd32f3x0_rcu.h
  • rcu_clock_freq_enum : gd32f3x0_rcu.h
  • rcu_clock_freq_get() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_CRC : gd32f3x0_rcu.h
  • RCU_CTC : gd32f3x0_rcu.h
  • RCU_CTCRST : gd32f3x0_rcu.h
  • RCU_CTL0 : gd32f3x0_rcu.h
  • RCU_CTL0_CKMEN : gd32f3x0_rcu.h
  • RCU_CTL0_HXTALBPS : gd32f3x0_rcu.h
  • RCU_CTL0_HXTALEN : gd32f3x0_rcu.h
  • RCU_CTL0_HXTALSTB : gd32f3x0_rcu.h
  • RCU_CTL0_IRC8MADJ : gd32f3x0_rcu.h
  • RCU_CTL0_IRC8MCALIB : gd32f3x0_rcu.h
  • RCU_CTL0_IRC8MEN : gd32f3x0_rcu.h
  • RCU_CTL0_IRC8MSTB : gd32f3x0_rcu.h
  • RCU_CTL0_PLLEN : gd32f3x0_rcu.h
  • RCU_CTL0_PLLSTB : gd32f3x0_rcu.h
  • RCU_CTL1 : gd32f3x0_rcu.h
  • RCU_CTL1_IRC28MADJ : gd32f3x0_rcu.h
  • RCU_CTL1_IRC28MCALIB : gd32f3x0_rcu.h
  • RCU_CTL1_IRC28MEN : gd32f3x0_rcu.h
  • RCU_CTL1_IRC28MSTB : gd32f3x0_rcu.h
  • RCU_DEEPSLEEP_V_0_7 : gd32f3x0_rcu.h
  • RCU_DEEPSLEEP_V_0_8 : gd32f3x0_rcu.h
  • RCU_DEEPSLEEP_V_0_9 : gd32f3x0_rcu.h
  • RCU_DEEPSLEEP_V_1_0 : gd32f3x0_rcu.h
  • rcu_deepsleep_voltage_set() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_deinit() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_DMA : gd32f3x0_rcu.h
  • RCU_DSV : gd32f3x0_rcu.h
  • RCU_DSV_DSLPVS : gd32f3x0_rcu.h
  • rcu_flag_enum : gd32f3x0_rcu.h
  • RCU_FLAG_EPRST : gd32f3x0_rcu.h
  • RCU_FLAG_FWDGTRST : gd32f3x0_rcu.h
  • rcu_flag_get() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_FLAG_HXTALSTB : gd32f3x0_rcu.h
  • RCU_FLAG_IRC28MSTB : gd32f3x0_rcu.h
  • RCU_FLAG_IRC40KSTB : gd32f3x0_rcu.h
  • RCU_FLAG_IRC48MSTB : gd32f3x0_rcu.h
  • RCU_FLAG_IRC8MSTB : gd32f3x0_rcu.h
  • RCU_FLAG_LPRST : gd32f3x0_rcu.h
  • RCU_FLAG_LXTALSTB : gd32f3x0_rcu.h
  • RCU_FLAG_OBLRST : gd32f3x0_rcu.h
  • RCU_FLAG_PLLSTB : gd32f3x0_rcu.h
  • RCU_FLAG_PORRST : gd32f3x0_rcu.h
  • RCU_FLAG_SWRST : gd32f3x0_rcu.h
  • RCU_FLAG_V12RST : gd32f3x0_rcu.h
  • RCU_FLAG_WWDGTRST : gd32f3x0_rcu.h
  • RCU_FMC_SLP : gd32f3x0_rcu.h
  • RCU_GPIOA : gd32f3x0_rcu.h
  • RCU_GPIOARST : gd32f3x0_rcu.h
  • RCU_GPIOB : gd32f3x0_rcu.h
  • RCU_GPIOBRST : gd32f3x0_rcu.h
  • RCU_GPIOC : gd32f3x0_rcu.h
  • RCU_GPIOCRST : gd32f3x0_rcu.h
  • RCU_GPIOD : gd32f3x0_rcu.h
  • RCU_GPIODRST : gd32f3x0_rcu.h
  • RCU_GPIOF : gd32f3x0_rcu.h
  • RCU_GPIOFRST : gd32f3x0_rcu.h
  • RCU_HXTAL : gd32f3x0_rcu.h
  • rcu_hxtal_clock_monitor_disable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_hxtal_clock_monitor_enable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_hxtal_prediv_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_I2C0 : gd32f3x0_rcu.h
  • RCU_I2C0RST : gd32f3x0_rcu.h
  • RCU_I2C1 : gd32f3x0_rcu.h
  • RCU_I2C1RST : gd32f3x0_rcu.h
  • RCU_I2C2 : gd32f3x0_rcu.h
  • RCU_I2C2RST : gd32f3x0_rcu.h
  • RCU_INT : gd32f3x0_rcu.h
  • RCU_INT_CKMIC : gd32f3x0_rcu.h
  • RCU_INT_CKMIF : gd32f3x0_rcu.h
  • rcu_int_enum : gd32f3x0_rcu.h
  • RCU_INT_FLAG_CKM : gd32f3x0_rcu.h
  • RCU_INT_FLAG_CKM_CLR : gd32f3x0_rcu.h
  • rcu_int_flag_clear_enum : gd32f3x0_rcu.h
  • rcu_int_flag_enum : gd32f3x0_rcu.h
  • RCU_INT_FLAG_HXTALSTB : gd32f3x0_rcu.h
  • RCU_INT_FLAG_HXTALSTB_CLR : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC28MSTB : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC28MSTB_CLR : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC40KSTB : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC40KSTB_CLR : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC48MSTB : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC48MSTB_CLR : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC8MSTB : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC8MSTB_CLR : gd32f3x0_rcu.h
  • RCU_INT_FLAG_LXTALSTB : gd32f3x0_rcu.h
  • RCU_INT_FLAG_LXTALSTB_CLR : gd32f3x0_rcu.h
  • RCU_INT_FLAG_PLLSTB : gd32f3x0_rcu.h
  • RCU_INT_FLAG_PLLSTB_CLR : gd32f3x0_rcu.h
  • RCU_INT_HXTALSTB : gd32f3x0_rcu.h
  • RCU_INT_HXTALSTBIC : gd32f3x0_rcu.h
  • RCU_INT_HXTALSTBIE : gd32f3x0_rcu.h
  • RCU_INT_HXTALSTBIF : gd32f3x0_rcu.h
  • RCU_INT_IRC28MSTB : gd32f3x0_rcu.h
  • RCU_INT_IRC28MSTBIC : gd32f3x0_rcu.h
  • RCU_INT_IRC28MSTBIE : gd32f3x0_rcu.h
  • RCU_INT_IRC28MSTBIF : gd32f3x0_rcu.h
  • RCU_INT_IRC40KSTB : gd32f3x0_rcu.h
  • RCU_INT_IRC40KSTBIC : gd32f3x0_rcu.h
  • RCU_INT_IRC40KSTBIE : gd32f3x0_rcu.h
  • RCU_INT_IRC40KSTBIF : gd32f3x0_rcu.h
  • RCU_INT_IRC48MSTB : gd32f3x0_rcu.h
  • RCU_INT_IRC8MSTB : gd32f3x0_rcu.h
  • RCU_INT_IRC8MSTBIC : gd32f3x0_rcu.h
  • RCU_INT_IRC8MSTBIE : gd32f3x0_rcu.h
  • RCU_INT_IRC8MSTBIF : gd32f3x0_rcu.h
  • RCU_INT_LXTALSTB : gd32f3x0_rcu.h
  • RCU_INT_LXTALSTBIC : gd32f3x0_rcu.h
  • RCU_INT_LXTALSTBIE : gd32f3x0_rcu.h
  • RCU_INT_LXTALSTBIF : gd32f3x0_rcu.h
  • RCU_INT_PLLSTB : gd32f3x0_rcu.h
  • RCU_INT_PLLSTBIC : gd32f3x0_rcu.h
  • RCU_INT_PLLSTBIE : gd32f3x0_rcu.h
  • RCU_INT_PLLSTBIF : gd32f3x0_rcu.h
  • rcu_interrupt_disable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_interrupt_enable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_interrupt_flag_clear() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_interrupt_flag_get() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_IRC28M : gd32f3x0_rcu.h
  • rcu_irc28m_adjust_value_set() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_IRC40K : gd32f3x0_rcu.h
  • RCU_IRC48M : gd32f3x0_rcu.h
  • RCU_IRC8M : gd32f3x0_rcu.h
  • rcu_irc8m_adjust_value_set() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_LXTAL : gd32f3x0_rcu.h
  • rcu_lxtal_drive_capability_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_LXTAL_HIGHDRI : gd32f3x0_rcu.h
  • RCU_LXTAL_LOWDRI : gd32f3x0_rcu.h
  • RCU_LXTAL_MED_HIGHDRI : gd32f3x0_rcu.h
  • RCU_LXTAL_MED_LOWDRI : gd32f3x0_rcu.h
  • rcu_osci_bypass_mode_disable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_osci_bypass_mode_enable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_osci_off() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_osci_on() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_osci_stab_wait() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_osci_type_enum : gd32f3x0_rcu.h
  • rcu_periph_clock_disable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_periph_clock_enable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_periph_clock_sleep_disable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_periph_clock_sleep_enable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_periph_enum : gd32f3x0_rcu.h
  • rcu_periph_reset_disable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_periph_reset_enable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_periph_reset_enum : gd32f3x0_rcu.h
  • rcu_periph_sleep_enum : gd32f3x0_rcu.h
  • RCU_PLL_CK : gd32f3x0_rcu.h
  • rcu_pll_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_PLL_MUL10 : gd32f3x0_rcu.h
  • RCU_PLL_MUL11 : gd32f3x0_rcu.h
  • RCU_PLL_MUL12 : gd32f3x0_rcu.h
  • RCU_PLL_MUL13 : gd32f3x0_rcu.h
  • RCU_PLL_MUL14 : gd32f3x0_rcu.h
  • RCU_PLL_MUL15 : gd32f3x0_rcu.h
  • RCU_PLL_MUL16 : gd32f3x0_rcu.h
  • RCU_PLL_MUL17 : gd32f3x0_rcu.h
  • RCU_PLL_MUL18 : gd32f3x0_rcu.h
  • RCU_PLL_MUL19 : gd32f3x0_rcu.h
  • RCU_PLL_MUL2 : gd32f3x0_rcu.h
  • RCU_PLL_MUL20 : gd32f3x0_rcu.h
  • RCU_PLL_MUL21 : gd32f3x0_rcu.h
  • RCU_PLL_MUL22 : gd32f3x0_rcu.h
  • RCU_PLL_MUL23 : gd32f3x0_rcu.h
  • RCU_PLL_MUL24 : gd32f3x0_rcu.h
  • RCU_PLL_MUL25 : gd32f3x0_rcu.h
  • RCU_PLL_MUL26 : gd32f3x0_rcu.h
  • RCU_PLL_MUL27 : gd32f3x0_rcu.h
  • RCU_PLL_MUL28 : gd32f3x0_rcu.h
  • RCU_PLL_MUL29 : gd32f3x0_rcu.h
  • RCU_PLL_MUL3 : gd32f3x0_rcu.h
  • RCU_PLL_MUL30 : gd32f3x0_rcu.h
  • RCU_PLL_MUL31 : gd32f3x0_rcu.h
  • RCU_PLL_MUL32 : gd32f3x0_rcu.h
  • RCU_PLL_MUL33 : gd32f3x0_rcu.h
  • RCU_PLL_MUL34 : gd32f3x0_rcu.h
  • RCU_PLL_MUL35 : gd32f3x0_rcu.h
  • RCU_PLL_MUL36 : gd32f3x0_rcu.h
  • RCU_PLL_MUL37 : gd32f3x0_rcu.h
  • RCU_PLL_MUL38 : gd32f3x0_rcu.h
  • RCU_PLL_MUL39 : gd32f3x0_rcu.h
  • RCU_PLL_MUL4 : gd32f3x0_rcu.h
  • RCU_PLL_MUL40 : gd32f3x0_rcu.h
  • RCU_PLL_MUL41 : gd32f3x0_rcu.h
  • RCU_PLL_MUL42 : gd32f3x0_rcu.h
  • RCU_PLL_MUL43 : gd32f3x0_rcu.h
  • RCU_PLL_MUL44 : gd32f3x0_rcu.h
  • RCU_PLL_MUL45 : gd32f3x0_rcu.h
  • RCU_PLL_MUL46 : gd32f3x0_rcu.h
  • RCU_PLL_MUL47 : gd32f3x0_rcu.h
  • RCU_PLL_MUL48 : gd32f3x0_rcu.h
  • RCU_PLL_MUL49 : gd32f3x0_rcu.h
  • RCU_PLL_MUL5 : gd32f3x0_rcu.h
  • RCU_PLL_MUL50 : gd32f3x0_rcu.h
  • RCU_PLL_MUL51 : gd32f3x0_rcu.h
  • RCU_PLL_MUL52 : gd32f3x0_rcu.h
  • RCU_PLL_MUL53 : gd32f3x0_rcu.h
  • RCU_PLL_MUL54 : gd32f3x0_rcu.h
  • RCU_PLL_MUL55 : gd32f3x0_rcu.h
  • RCU_PLL_MUL56 : gd32f3x0_rcu.h
  • RCU_PLL_MUL57 : gd32f3x0_rcu.h
  • RCU_PLL_MUL58 : gd32f3x0_rcu.h
  • RCU_PLL_MUL59 : gd32f3x0_rcu.h
  • RCU_PLL_MUL6 : gd32f3x0_rcu.h
  • RCU_PLL_MUL60 : gd32f3x0_rcu.h
  • RCU_PLL_MUL61 : gd32f3x0_rcu.h
  • RCU_PLL_MUL62 : gd32f3x0_rcu.h
  • RCU_PLL_MUL63 : gd32f3x0_rcu.h
  • RCU_PLL_MUL64 : gd32f3x0_rcu.h
  • RCU_PLL_MUL7 : gd32f3x0_rcu.h
  • RCU_PLL_MUL8 : gd32f3x0_rcu.h
  • RCU_PLL_MUL9 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV1 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV10 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV11 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV12 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV13 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV14 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV15 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV16 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV2 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV3 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV4 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV5 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV6 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV7 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV8 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV9 : gd32f3x0_rcu.h
  • rcu_pll_preselection_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_PLLDV_CKPLL : gd32f3x0_rcu.h
  • RCU_PLLDV_CKPLL_DIV2 : gd32f3x0_rcu.h
  • RCU_PLLPREDV : gd32f3x0_rcu.h
  • RCU_PLLPREDV_DIV2 : gd32f3x0_rcu.h
  • RCU_PLLPRESEL_HXTAL : gd32f3x0_rcu.h
  • RCU_PLLPRESEL_IRC48M : gd32f3x0_rcu.h
  • RCU_PLLSRC_HXTAL_IRC48M : gd32f3x0_rcu.h
  • RCU_PLLSRC_IRC8M_DIV2 : gd32f3x0_rcu.h
  • RCU_PMU : gd32f3x0_rcu.h
  • RCU_PMURST : gd32f3x0_rcu.h
  • RCU_REG_VAL : gd32f3x0_rcu.h
  • RCU_REGIDX_BIT : gd32f3x0_rcu.h
  • RCU_RSTSCK : gd32f3x0_rcu.h
  • RCU_RSTSCK_EPRSTF : gd32f3x0_rcu.h
  • RCU_RSTSCK_FWDGTRSTF : gd32f3x0_rcu.h
  • RCU_RSTSCK_IRC40KEN : gd32f3x0_rcu.h
  • RCU_RSTSCK_IRC40KSTB : gd32f3x0_rcu.h
  • RCU_RSTSCK_LPRSTF : gd32f3x0_rcu.h
  • RCU_RSTSCK_OBLRSTF : gd32f3x0_rcu.h
  • RCU_RSTSCK_PORRSTF : gd32f3x0_rcu.h
  • RCU_RSTSCK_RSTFC : gd32f3x0_rcu.h
  • RCU_RSTSCK_SWRSTF : gd32f3x0_rcu.h
  • RCU_RSTSCK_V12RSTF : gd32f3x0_rcu.h
  • RCU_RSTSCK_WWDGTRSTF : gd32f3x0_rcu.h
  • RCU_RTC : gd32f3x0_rcu.h
  • rcu_rtc_clock_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_RTCSRC_HXTAL_DIV32 : gd32f3x0_rcu.h
  • RCU_RTCSRC_IRC40K : gd32f3x0_rcu.h
  • RCU_RTCSRC_LXTAL : gd32f3x0_rcu.h
  • RCU_RTCSRC_NONE : gd32f3x0_rcu.h
  • RCU_SCSS_HXTAL : gd32f3x0_rcu.h
  • RCU_SCSS_IRC8M : gd32f3x0_rcu.h
  • RCU_SCSS_PLL : gd32f3x0_rcu.h
  • RCU_SPI0 : gd32f3x0_rcu.h
  • RCU_SPI0RST : gd32f3x0_rcu.h
  • RCU_SPI1 : gd32f3x0_rcu.h
  • RCU_SPI1RST : gd32f3x0_rcu.h
  • RCU_SPI2 : gd32f3x0_rcu.h
  • RCU_SPI2RST : gd32f3x0_rcu.h
  • RCU_SRAM_SLP : gd32f3x0_rcu.h
  • rcu_system_clock_source_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_system_clock_source_get() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_TIMER0 : gd32f3x0_rcu.h
  • RCU_TIMER0RST : gd32f3x0_rcu.h
  • RCU_TIMER1 : gd32f3x0_rcu.h
  • RCU_TIMER13 : gd32f3x0_rcu.h
  • RCU_TIMER13RST : gd32f3x0_rcu.h
  • RCU_TIMER14 : gd32f3x0_rcu.h
  • RCU_TIMER14RST : gd32f3x0_rcu.h
  • RCU_TIMER15 : gd32f3x0_rcu.h
  • RCU_TIMER15RST : gd32f3x0_rcu.h
  • RCU_TIMER16 : gd32f3x0_rcu.h
  • RCU_TIMER16RST : gd32f3x0_rcu.h
  • RCU_TIMER1RST : gd32f3x0_rcu.h
  • RCU_TIMER2 : gd32f3x0_rcu.h
  • RCU_TIMER2RST : gd32f3x0_rcu.h
  • RCU_TSI : gd32f3x0_rcu.h
  • RCU_TSIRST : gd32f3x0_rcu.h
  • RCU_USART0 : gd32f3x0_rcu.h
  • RCU_USART0RST : gd32f3x0_rcu.h
  • RCU_USART0SRC_CKAPB2 : gd32f3x0_rcu.h
  • RCU_USART0SRC_CKSYS : gd32f3x0_rcu.h
  • RCU_USART0SRC_IRC8M : gd32f3x0_rcu.h
  • RCU_USART0SRC_LXTAL : gd32f3x0_rcu.h
  • RCU_USART1 : gd32f3x0_rcu.h
  • RCU_USART1RST : gd32f3x0_rcu.h
  • rcu_usart_clock_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_USBFS_CKPLL_DIV1 : gd32f3x0_rcu.h
  • RCU_USBFS_CKPLL_DIV1_5 : gd32f3x0_rcu.h
  • RCU_USBFS_CKPLL_DIV2 : gd32f3x0_rcu.h
  • RCU_USBFS_CKPLL_DIV2_5 : gd32f3x0_rcu.h
  • RCU_USBFS_CKPLL_DIV3 : gd32f3x0_rcu.h
  • RCU_USBFS_CKPLL_DIV3_5 : gd32f3x0_rcu.h
  • rcu_usbfs_clock_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_VKEY : gd32f3x0_rcu.h
  • RCU_VKEY_KEY : gd32f3x0_rcu.h
  • RCU_VKEY_UNLOCK : gd32f3x0_rcu.h
  • rcu_voltage_key_unlock() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • RCU_WWDGT : gd32f3x0_rcu.h
  • RCU_WWDGTRST : gd32f3x0_rcu.h
  • reg_idx : gd32f3x0_rcu.h
  • RLD_RLD : gd32f3x0_fwdgt.h
  • RSQ0_RL : gd32f3x0_adc.h
  • RTC : gd32f3x0_rtc.h
  • RTC_12HOUR : gd32f3x0_rtc.h
  • RTC_24HOUR : gd32f3x0_rtc.h
  • RTC_ALARM_ALL_MASK : gd32f3x0_rtc.h
  • rtc_alarm_config() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • RTC_ALARM_DATE_MASK : gd32f3x0_rtc.h
  • RTC_ALARM_DATE_SELECTED : gd32f3x0_rtc.h
  • rtc_alarm_disable() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_alarm_enable() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_alarm_get() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • RTC_ALARM_HIGH : gd32f3x0_rtc.h
  • RTC_ALARM_HOUR_MASK : gd32f3x0_rtc.h
  • RTC_ALARM_LOW : gd32f3x0_rtc.h
  • RTC_ALARM_MINUTE_MASK : gd32f3x0_rtc.h
  • RTC_ALARM_NONE_MASK : gd32f3x0_rtc.h
  • RTC_ALARM_OUTPUT_OD : gd32f3x0_rtc.h
  • RTC_ALARM_OUTPUT_PP : gd32f3x0_rtc.h
  • RTC_ALARM_SECOND_MASK : gd32f3x0_rtc.h
  • rtc_alarm_subsecond_config() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_alarm_subsecond_get() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • RTC_ALARM_WEEKDAY_SELECTED : gd32f3x0_rtc.h
  • RTC_ALRM0SS : gd32f3x0_rtc.h
  • RTC_ALRM0SS_MASKSSC : gd32f3x0_rtc.h
  • RTC_ALRM0SS_SSC : gd32f3x0_rtc.h
  • RTC_ALRM0TD : gd32f3x0_rtc.h
  • RTC_ALRM0TD_DAYT : gd32f3x0_rtc.h
  • RTC_ALRM0TD_DAYU : gd32f3x0_rtc.h
  • RTC_ALRM0TD_DOWS : gd32f3x0_rtc.h
  • RTC_ALRM0TD_HRT : gd32f3x0_rtc.h
  • RTC_ALRM0TD_HRU : gd32f3x0_rtc.h
  • RTC_ALRM0TD_MNT : gd32f3x0_rtc.h
  • RTC_ALRM0TD_MNU : gd32f3x0_rtc.h
  • RTC_ALRM0TD_MSKD : gd32f3x0_rtc.h
  • RTC_ALRM0TD_MSKH : gd32f3x0_rtc.h
  • RTC_ALRM0TD_MSKM : gd32f3x0_rtc.h
  • RTC_ALRM0TD_MSKS : gd32f3x0_rtc.h
  • RTC_ALRM0TD_PM : gd32f3x0_rtc.h
  • RTC_ALRM0TD_SCT : gd32f3x0_rtc.h
  • RTC_ALRM0TD_SCU : gd32f3x0_rtc.h
  • RTC_ALRM0WF_TIMEOUT : gd32f3x0_rtc.h
  • rtc_alter_output_config() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • RTC_AM : gd32f3x0_rtc.h
  • RTC_APR : gd32f3x0_rtc.h
  • RTC_AUG : gd32f3x0_rtc.h
  • RTC_BKP0 : gd32f3x0_rtc.h
  • RTC_BKP0_DATA : gd32f3x0_rtc.h
  • RTC_BKP1 : gd32f3x0_rtc.h
  • RTC_BKP1_DATA : gd32f3x0_rtc.h
  • RTC_BKP2 : gd32f3x0_rtc.h
  • RTC_BKP2_DATA : gd32f3x0_rtc.h
  • RTC_BKP3 : gd32f3x0_rtc.h
  • RTC_BKP3_DATA : gd32f3x0_rtc.h
  • RTC_BKP4 : gd32f3x0_rtc.h
  • RTC_BKP4_DATA : gd32f3x0_rtc.h
  • rtc_bypass_shadow_disable() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_bypass_shadow_enable() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • RTC_CALIBRATION_1HZ : gd32f3x0_rtc.h
  • RTC_CALIBRATION_512HZ : gd32f3x0_rtc.h
  • rtc_calibration_config() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • RTC_CALIBRATION_PLUS_RESET : gd32f3x0_rtc.h
  • RTC_CALIBRATION_PLUS_SET : gd32f3x0_rtc.h
  • RTC_CALIBRATION_WINDOW_16S : gd32f3x0_rtc.h
  • RTC_CALIBRATION_WINDOW_32S : gd32f3x0_rtc.h
  • RTC_CALIBRATION_WINDOW_8S : gd32f3x0_rtc.h
  • RTC_CTL : gd32f3x0_rtc.h
  • RTC_CTL_A1H : gd32f3x0_rtc.h
  • RTC_CTL_ALRM0EN : gd32f3x0_rtc.h
  • RTC_CTL_ALRM0IE : gd32f3x0_rtc.h
  • RTC_CTL_BPSHAD : gd32f3x0_rtc.h
  • RTC_CTL_COEN : gd32f3x0_rtc.h
  • RTC_CTL_COS : gd32f3x0_rtc.h
  • RTC_CTL_CS : gd32f3x0_rtc.h
  • RTC_CTL_DSM : gd32f3x0_rtc.h
  • RTC_CTL_OPOL : gd32f3x0_rtc.h
  • RTC_CTL_OS : gd32f3x0_rtc.h
  • RTC_CTL_REFEN : gd32f3x0_rtc.h
  • RTC_CTL_S1H : gd32f3x0_rtc.h
  • RTC_CTL_TSEG : gd32f3x0_rtc.h
  • RTC_CTL_TSEN : gd32f3x0_rtc.h
  • RTC_CTL_TSIE : gd32f3x0_rtc.h
  • rtc_current_time_get() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • RTC_DATE : gd32f3x0_rtc.h
  • RTC_DATE_DAYT : gd32f3x0_rtc.h
  • RTC_DATE_DAYU : gd32f3x0_rtc.h
  • RTC_DATE_DOW : gd32f3x0_rtc.h
  • RTC_DATE_MONT : gd32f3x0_rtc.h
  • RTC_DATE_MONU : gd32f3x0_rtc.h
  • RTC_DATE_RESET : gd32f3x0_rtc.h
  • RTC_DATE_YRT : gd32f3x0_rtc.h
  • RTC_DATE_YRU : gd32f3x0_rtc.h
  • RTC_DEC : gd32f3x0_rtc.h
  • rtc_deinit() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • RTC_DTS : gd32f3x0_rtc.h
  • RTC_DTS_DAYT : gd32f3x0_rtc.h
  • RTC_DTS_DAYU : gd32f3x0_rtc.h
  • RTC_DTS_DOW : gd32f3x0_rtc.h
  • RTC_DTS_MONT : gd32f3x0_rtc.h
  • RTC_DTS_MONU : gd32f3x0_rtc.h
  • RTC_FEB : gd32f3x0_rtc.h
  • RTC_FLAG_ALARM0 : gd32f3x0_rtc.h
  • RTC_FLAG_ALARM0_WRITTEN : gd32f3x0_rtc.h
  • rtc_flag_clear() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_flag_get() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • RTC_FLAG_INIT : gd32f3x0_rtc.h
  • RTC_FLAG_RECALIBRATION : gd32f3x0_rtc.h
  • RTC_FLAG_RSYN : gd32f3x0_rtc.h
  • RTC_FLAG_SHIFT : gd32f3x0_rtc.h
  • RTC_FLAG_TAMP0 : gd32f3x0_rtc.h
  • RTC_FLAG_TAMP1 : gd32f3x0_rtc.h
  • RTC_FLAG_TIMESTAMP : gd32f3x0_rtc.h
  • RTC_FLAG_TIMESTAMP_OVERFLOW : gd32f3x0_rtc.h
  • RTC_FLAG_YCM : gd32f3x0_rtc.h
  • RTC_FLT_2S : gd32f3x0_rtc.h
  • RTC_FLT_4S : gd32f3x0_rtc.h
  • RTC_FLT_8S : gd32f3x0_rtc.h
  • RTC_FLT_EDGE : gd32f3x0_rtc.h
  • RTC_FREQ_DIV1024 : gd32f3x0_rtc.h
  • RTC_FREQ_DIV16384 : gd32f3x0_rtc.h
  • RTC_FREQ_DIV2048 : gd32f3x0_rtc.h
  • RTC_FREQ_DIV256 : gd32f3x0_rtc.h
  • RTC_FREQ_DIV32768 : gd32f3x0_rtc.h
  • RTC_FREQ_DIV4096 : gd32f3x0_rtc.h
  • RTC_FREQ_DIV512 : gd32f3x0_rtc.h
  • RTC_FREQ_DIV8192 : gd32f3x0_rtc.h
  • RTC_FRIDAY : gd32f3x0_rtc.h
  • rtc_hour_adjust() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • RTC_HRFC : gd32f3x0_rtc.h
  • RTC_HRFC_CMSK : gd32f3x0_rtc.h
  • RTC_HRFC_CWND16 : gd32f3x0_rtc.h
  • RTC_HRFC_CWND8 : gd32f3x0_rtc.h
  • RTC_HRFC_FREQI : gd32f3x0_rtc.h
  • RTC_HRFC_TIMEOUT : gd32f3x0_rtc.h
  • rtc_init() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_init_mode_enter() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_init_mode_exit() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • RTC_INITM_TIMEOUT : gd32f3x0_rtc.h
  • RTC_INT_ALARM : gd32f3x0_rtc.h
  • RTC_INT_TAMP : gd32f3x0_rtc.h
  • RTC_INT_TIMESTAMP : gd32f3x0_rtc.h
  • rtc_interrupt_disable() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_interrupt_enable() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • RTC_JAN : gd32f3x0_rtc.h
  • RTC_JUL : gd32f3x0_rtc.h
  • RTC_JUN : gd32f3x0_rtc.h
  • RTC_LOCK_KEY : gd32f3x0_rtc.h
  • RTC_MAR : gd32f3x0_rtc.h
  • RTC_MASKSSC_0_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_10_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_11_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_12_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_13_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_1_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_2_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_3_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_4_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_5_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_6_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_7_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_8_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_9_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_NONE : gd32f3x0_rtc.h
  • RTC_MAY : gd32f3x0_rtc.h
  • RTC_MONDAY : gd32f3x0_rtc.h
  • RTC_NOV : gd32f3x0_rtc.h
  • RTC_OCT : gd32f3x0_rtc.h
  • RTC_OS_DISABLE : gd32f3x0_rtc.h
  • RTC_OS_ENABLE : gd32f3x0_rtc.h
  • RTC_PM : gd32f3x0_rtc.h
  • RTC_PRCH_1C : gd32f3x0_rtc.h
  • RTC_PRCH_2C : gd32f3x0_rtc.h
  • RTC_PRCH_4C : gd32f3x0_rtc.h
  • RTC_PRCH_8C : gd32f3x0_rtc.h
  • RTC_PSC : gd32f3x0_rtc.h
  • RTC_PSC_FACTOR_A : gd32f3x0_rtc.h
  • RTC_PSC_FACTOR_S : gd32f3x0_rtc.h
  • RTC_PSC_RESET : gd32f3x0_rtc.h
  • rtc_refclock_detection_disable() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_refclock_detection_enable() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • RTC_REGISTER_RESET : gd32f3x0_rtc.h
  • rtc_register_sync_wait() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • RTC_RSYNF_TIMEOUT : gd32f3x0_rtc.h
  • RTC_SATURDAY : gd32f3x0_rtc.h
  • rtc_second_ajust() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • RTC_SEP : gd32f3x0_rtc.h
  • RTC_SHIFT_ADD1S_RESET : gd32f3x0_rtc.h
  • RTC_SHIFT_ADD1S_SET : gd32f3x0_rtc.h
  • RTC_SHIFTCTL : gd32f3x0_rtc.h
  • RTC_SHIFTCTL_A1S : gd32f3x0_rtc.h
  • RTC_SHIFTCTL_SFS : gd32f3x0_rtc.h
  • RTC_SHIFTCTL_TIMEOUT : gd32f3x0_rtc.h
  • RTC_SS : gd32f3x0_rtc.h
  • RTC_SS_SSC : gd32f3x0_rtc.h
  • RTC_SSTS : gd32f3x0_rtc.h
  • RTC_SSTS_SSC : gd32f3x0_rtc.h
  • RTC_STAT : gd32f3x0_rtc.h
  • RTC_STAT_ALRM0F : gd32f3x0_rtc.h
  • RTC_STAT_ALRM0WF : gd32f3x0_rtc.h
  • RTC_STAT_INITF : gd32f3x0_rtc.h
  • RTC_STAT_INITM : gd32f3x0_rtc.h
  • RTC_STAT_RESET : gd32f3x0_rtc.h
  • RTC_STAT_RSYNF : gd32f3x0_rtc.h
  • RTC_STAT_SCPF : gd32f3x0_rtc.h
  • RTC_STAT_SOPF : gd32f3x0_rtc.h
  • RTC_STAT_TP0F : gd32f3x0_rtc.h
  • RTC_STAT_TP1F : gd32f3x0_rtc.h
  • RTC_STAT_TSF : gd32f3x0_rtc.h
  • RTC_STAT_TSOVRF : gd32f3x0_rtc.h
  • RTC_STAT_YCM : gd32f3x0_rtc.h
  • rtc_subsecond_get() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • RTC_SUNDAY : gd32f3x0_rtc.h
  • RTC_TAMP : gd32f3x0_rtc.h
  • RTC_TAMP_DISPU : gd32f3x0_rtc.h
  • RTC_TAMP_FLT : gd32f3x0_rtc.h
  • RTC_TAMP_FREQ : gd32f3x0_rtc.h
  • RTC_TAMP_PC13MDE : gd32f3x0_rtc.h
  • RTC_TAMP_PC13VAL : gd32f3x0_rtc.h
  • RTC_TAMP_PC14MDE : gd32f3x0_rtc.h
  • RTC_TAMP_PC14VAL : gd32f3x0_rtc.h
  • RTC_TAMP_PC15MDE : gd32f3x0_rtc.h
  • RTC_TAMP_PC15VAL : gd32f3x0_rtc.h
  • RTC_TAMP_PRCH : gd32f3x0_rtc.h
  • RTC_TAMP_TP0EG : gd32f3x0_rtc.h
  • RTC_TAMP_TP0EN : gd32f3x0_rtc.h
  • RTC_TAMP_TP1EG : gd32f3x0_rtc.h
  • RTC_TAMP_TP1EN : gd32f3x0_rtc.h
  • RTC_TAMP_TPIE : gd32f3x0_rtc.h
  • RTC_TAMP_TPTS : gd32f3x0_rtc.h
  • RTC_TAMPER0 : gd32f3x0_rtc.h
  • RTC_TAMPER1 : gd32f3x0_rtc.h
  • rtc_tamper_disable() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_tamper_enable() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • RTC_TAMPER_TRIGGER_EDGE_FALLING : gd32f3x0_rtc.h
  • RTC_TAMPER_TRIGGER_EDGE_RISING : gd32f3x0_rtc.h
  • RTC_TAMPER_TRIGGER_LEVEL_HIGH : gd32f3x0_rtc.h
  • RTC_TAMPER_TRIGGER_LEVEL_LOW : gd32f3x0_rtc.h
  • RTC_TAMPER_TRIGGER_POS : gd32f3x0_rtc.h
  • RTC_THURSDAY : gd32f3x0_rtc.h
  • RTC_TIME : gd32f3x0_rtc.h
  • RTC_TIME_HRT : gd32f3x0_rtc.h
  • RTC_TIME_HRU : gd32f3x0_rtc.h
  • RTC_TIME_MNT : gd32f3x0_rtc.h
  • RTC_TIME_MNU : gd32f3x0_rtc.h
  • RTC_TIME_PM : gd32f3x0_rtc.h
  • RTC_TIME_SCT : gd32f3x0_rtc.h
  • RTC_TIME_SCU : gd32f3x0_rtc.h
  • rtc_timestamp_disable() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_timestamp_enable() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • RTC_TIMESTAMP_FALLING_EDGE : gd32f3x0_rtc.h
  • rtc_timestamp_get() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • RTC_TIMESTAMP_RISING_EDGE : gd32f3x0_rtc.h
  • rtc_timestamp_subsecond_get() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • RTC_TTS : gd32f3x0_rtc.h
  • RTC_TTS_HRT : gd32f3x0_rtc.h
  • RTC_TTS_HRU : gd32f3x0_rtc.h
  • RTC_TTS_MNT : gd32f3x0_rtc.h
  • RTC_TTS_MNU : gd32f3x0_rtc.h
  • RTC_TTS_PM : gd32f3x0_rtc.h
  • RTC_TTS_SCT : gd32f3x0_rtc.h
  • RTC_TTS_SCU : gd32f3x0_rtc.h
  • RTC_TUESDAY : gd32f3x0_rtc.h
  • RTC_UNLOCK_KEY1 : gd32f3x0_rtc.h
  • RTC_UNLOCK_KEY2 : gd32f3x0_rtc.h
  • RTC_WEDSDAY : gd32f3x0_rtc.h
  • RTC_WPK : gd32f3x0_rtc.h
  • RTC_WPK_WPK : gd32f3x0_rtc.h
  • RX_MAX_DATA_LENGTH : usb_core.h
  • RXSTAT_DATA_UPDT : usb_defines.h
  • RXSTAT_GOUT_NAK : usb_defines.h
  • RXSTAT_SETUP_COMP : usb_defines.h
  • RXSTAT_SETUP_UPDT : usb_defines.h
  • RXSTAT_XFER_COMP : usb_defines.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • SADDR0_ADDFORMAT : gd32f3x0_i2c.h
  • SAMPTX_SPT : gd32f3x0_adc.h
  • SCB_LPM_DEEPSLEEP : gd32f3x0_misc.h
  • SCB_LPM_SLEEP_EXIT_ISR : gd32f3x0_misc.h
  • SCB_LPM_WAKE_BY_ALL_INT : gd32f3x0_misc.h
  • SCB_SCR_SEVONPEND : gd32f3x0_misc.h
  • SCB_SCR_SLEEPDEEP : gd32f3x0_misc.h
  • SCB_SCR_SLEEPONEXIT : gd32f3x0_misc.h
  • scd_begin() : usbh_core.h , usbh_core.c
  • scd_event_handle() : usbh_core.h , usbh_core.c
  • scd_init() : usbh_core.h , usbh_core.c
  • scd_state_move() : usbh_core.c , usbh_core.h
  • scd_table_pop() : usbh_core.h , usbh_core.c
  • scd_table_push() : usbh_core.h , usbh_core.c
  • scd_table_regist() : usbh_core.h , usbh_core.c
  • SEL_HXTAL : gd32f3x0_rcu.c , system_gd32f3x0.c
  • SEL_IRC8M : gd32f3x0_rcu.c , system_gd32f3x0.c
  • SEL_PLL : gd32f3x0_rcu.c , system_gd32f3x0.c
  • SHIFTCTL_SFS : gd32f3x0_rtc.h
  • SMCFG_ETPSC : gd32f3x0_timer.h
  • SMCFG_SMC : gd32f3x0_timer.h
  • SMCFG_TRGSEL : gd32f3x0_timer.h
  • SPI0 : gd32f3x0_spi.h
  • SPI1 : gd32f3x0_spi.h
  • SPI2 : gd32f3x0_spi.h
  • SPI_BIDIRECTIONAL_RECEIVE : gd32f3x0_spi.h
  • spi_bidirectional_transfer_config() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • SPI_BIDIRECTIONAL_TRANSMIT : gd32f3x0_spi.h
  • SPI_CK_PL_HIGH_PH_1EDGE : gd32f3x0_spi.h
  • SPI_CK_PL_HIGH_PH_2EDGE : gd32f3x0_spi.h
  • SPI_CK_PL_LOW_PH_1EDGE : gd32f3x0_spi.h
  • SPI_CK_PL_LOW_PH_2EDGE : gd32f3x0_spi.h
  • spi_crc_error_clear() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_crc_get() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_crc_next() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_crc_off() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_crc_on() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_crc_polynomial_get() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_crc_polynomial_set() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • SPI_CRC_RX : gd32f3x0_spi.h
  • SPI_CRC_TX : gd32f3x0_spi.h
  • SPI_CRCPOLY : gd32f3x0_spi.h
  • SPI_CRCPOLY_CPR : gd32f3x0_spi.h
  • SPI_CTL0 : gd32f3x0_spi.h
  • SPI_CTL0_BDEN : gd32f3x0_spi.h
  • SPI_CTL0_BDOEN : gd32f3x0_spi.h
  • SPI_CTL0_CKPH : gd32f3x0_spi.h
  • SPI_CTL0_CKPL : gd32f3x0_spi.h
  • SPI_CTL0_CRCEN : gd32f3x0_spi.h
  • SPI_CTL0_CRCNT : gd32f3x0_spi.h
  • SPI_CTL0_FF16 : gd32f3x0_spi.h
  • SPI_CTL0_LF : gd32f3x0_spi.h
  • SPI_CTL0_MSTMOD : gd32f3x0_spi.h
  • SPI_CTL0_PSC : gd32f3x0_spi.h
  • SPI_CTL0_RO : gd32f3x0_spi.h
  • SPI_CTL0_SPIEN : gd32f3x0_spi.h
  • SPI_CTL0_SWNSS : gd32f3x0_spi.h
  • SPI_CTL0_SWNSSEN : gd32f3x0_spi.h
  • SPI_CTL1 : gd32f3x0_spi.h
  • SPI_CTL1_DMAREN : gd32f3x0_spi.h
  • SPI_CTL1_DMATEN : gd32f3x0_spi.h
  • SPI_CTL1_ERRIE : gd32f3x0_spi.h
  • SPI_CTL1_NSSDRV : gd32f3x0_spi.h
  • SPI_CTL1_NSSP : gd32f3x0_spi.h
  • SPI_CTL1_RBNEIE : gd32f3x0_spi.h
  • SPI_CTL1_TBEIE : gd32f3x0_spi.h
  • SPI_CTL1_TMOD : gd32f3x0_spi.h
  • SPI_DATA : gd32f3x0_spi.h
  • SPI_DATA_DATA : gd32f3x0_spi.h
  • spi_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_dma_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_dma_enable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • SPI_DMA_RECEIVE : gd32f3x0_spi.h
  • SPI_DMA_TRANSMIT : gd32f3x0_spi.h
  • spi_enable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • SPI_ENDIAN_LSB : gd32f3x0_spi.h
  • SPI_ENDIAN_MSB : gd32f3x0_spi.h
  • SPI_FLAG_CONFERR : gd32f3x0_spi.h
  • SPI_FLAG_CRCERR : gd32f3x0_spi.h
  • SPI_FLAG_FERR : gd32f3x0_spi.h
  • SPI_FLAG_RBNE : gd32f3x0_spi.h
  • SPI_FLAG_RXORERR : gd32f3x0_spi.h
  • SPI_FLAG_TBE : gd32f3x0_spi.h
  • SPI_FLAG_TRANS : gd32f3x0_spi.h
  • SPI_FRAMESIZE_16BIT : gd32f3x0_spi.h
  • SPI_FRAMESIZE_8BIT : gd32f3x0_spi.h
  • spi_i2s_data_frame_format_config() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_i2s_data_receive() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_i2s_data_transmit() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_i2s_deinit() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_i2s_flag_get() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • SPI_I2S_INT_ERR : gd32f3x0_spi.h
  • SPI_I2S_INT_FLAG_FERR : gd32f3x0_spi.h
  • SPI_I2S_INT_FLAG_RBNE : gd32f3x0_spi.h
  • SPI_I2S_INT_FLAG_RXORERR : gd32f3x0_spi.h
  • SPI_I2S_INT_FLAG_TBE : gd32f3x0_spi.h
  • SPI_I2S_INT_RBNE : gd32f3x0_spi.h
  • SPI_I2S_INT_TBE : gd32f3x0_spi.h
  • spi_i2s_interrupt_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_i2s_interrupt_enable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_i2s_interrupt_flag_get() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • SPI_I2SCTL : gd32f3x0_spi.h
  • SPI_I2SCTL_CHLEN : gd32f3x0_spi.h
  • SPI_I2SCTL_CKPL : gd32f3x0_spi.h
  • SPI_I2SCTL_DTLEN : gd32f3x0_spi.h
  • SPI_I2SCTL_I2SEN : gd32f3x0_spi.h
  • SPI_I2SCTL_I2SOPMOD : gd32f3x0_spi.h
  • SPI_I2SCTL_I2SSEL : gd32f3x0_spi.h
  • SPI_I2SCTL_I2SSTD : gd32f3x0_spi.h
  • SPI_I2SCTL_PCMSMOD : gd32f3x0_spi.h
  • SPI_I2SPSC : gd32f3x0_spi.h
  • SPI_I2SPSC_DIV : gd32f3x0_spi.h
  • SPI_I2SPSC_MCKOEN : gd32f3x0_spi.h
  • SPI_I2SPSC_OF : gd32f3x0_spi.h
  • SPI_I2SPSC_RESET : gd32f3x0_spi.c
  • spi_init() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • SPI_INIT_MASK : gd32f3x0_spi.c
  • SPI_INT_FLAG_CONFERR : gd32f3x0_spi.h
  • SPI_INT_FLAG_CRCERR : gd32f3x0_spi.h
  • SPI_MASTER : gd32f3x0_spi.h
  • SPI_NSS_HARD : gd32f3x0_spi.h
  • spi_nss_internal_high() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_nss_internal_low() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_nss_output_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_nss_output_enable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • SPI_NSS_SOFT : gd32f3x0_spi.h
  • spi_nssp_mode_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_nssp_mode_enable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • SPI_PSC_128 : gd32f3x0_spi.h
  • SPI_PSC_16 : gd32f3x0_spi.h
  • SPI_PSC_2 : gd32f3x0_spi.h
  • SPI_PSC_256 : gd32f3x0_spi.h
  • SPI_PSC_32 : gd32f3x0_spi.h
  • SPI_PSC_4 : gd32f3x0_spi.h
  • SPI_PSC_64 : gd32f3x0_spi.h
  • SPI_PSC_8 : gd32f3x0_spi.h
  • SPI_QCTL : gd32f3x0_spi.h
  • SPI_QCTL_IO23_DRV : gd32f3x0_spi.h
  • SPI_QCTL_QMOD : gd32f3x0_spi.h
  • SPI_QCTL_QRD : gd32f3x0_spi.h
  • SPI_RCRC : gd32f3x0_spi.h
  • SPI_RCRC_RCR : gd32f3x0_spi.h
  • SPI_SLAVE : gd32f3x0_spi.h
  • SPI_STAT : gd32f3x0_spi.h
  • SPI_STAT_CONFERR : gd32f3x0_spi.h
  • SPI_STAT_CRCERR : gd32f3x0_spi.h
  • SPI_STAT_FERR : gd32f3x0_spi.h
  • SPI_STAT_I2SCH : gd32f3x0_spi.h
  • SPI_STAT_RBNE : gd32f3x0_spi.h
  • SPI_STAT_RXORERR : gd32f3x0_spi.h
  • SPI_STAT_TBE : gd32f3x0_spi.h
  • SPI_STAT_TRANS : gd32f3x0_spi.h
  • SPI_STAT_TXURERR : gd32f3x0_spi.h
  • SPI_TCRC : gd32f3x0_spi.h
  • SPI_TCRC_TCR : gd32f3x0_spi.h
  • spi_ti_mode_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_ti_mode_enable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • SPI_TRANSMODE_BDRECEIVE : gd32f3x0_spi.h
  • SPI_TRANSMODE_BDTRANSMIT : gd32f3x0_spi.h
  • SPI_TRANSMODE_FULLDUPLEX : gd32f3x0_spi.h
  • SPI_TRANSMODE_RECEIVEONLY : gd32f3x0_spi.h
  • SS_SSC : gd32f3x0_rtc.h
  • SSTS_SSC : gd32f3x0_rtc.h
  • SWAPBYTE : usb_std.h
  • SYSCFG : gd32f3x0_syscfg.h
  • SYSCFG_CFG0 : gd32f3x0_syscfg.h
  • SYSCFG_CFG0_ADC_DMA_RMP : gd32f3x0_syscfg.h
  • SYSCFG_CFG0_BOOT_MODE : gd32f3x0_syscfg.h
  • SYSCFG_CFG0_PB9_HCCE : gd32f3x0_syscfg.h
  • SYSCFG_CFG0_TIMER15_DMA_RMP : gd32f3x0_syscfg.h
  • SYSCFG_CFG0_TIMER16_DMA_RMP : gd32f3x0_syscfg.h
  • SYSCFG_CFG0_USART0_RX_DMA_RMP : gd32f3x0_syscfg.h
  • SYSCFG_CFG0_USART0_TX_DMA_RMP : gd32f3x0_syscfg.h
  • SYSCFG_CFG2 : gd32f3x0_syscfg.h
  • SYSCFG_CFG2_LOCKUP_LOCK : gd32f3x0_syscfg.h
  • SYSCFG_CFG2_LVD_LOCK : gd32f3x0_syscfg.h
  • SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK : gd32f3x0_syscfg.h
  • SYSCFG_CFG2_SRAM_PCEF : gd32f3x0_syscfg.h
  • SYSCFG_COMPENSATION : gd32f3x0_syscfg.h
  • syscfg_compensation_config() : gd32f3x0_syscfg.h , gd32f3x0_syscfg.c
  • SYSCFG_COMPENSATION_DISABLE : gd32f3x0_syscfg.h
  • SYSCFG_COMPENSATION_ENABLE : gd32f3x0_syscfg.h
  • syscfg_cps_rdy_flag_get() : gd32f3x0_syscfg.h , gd32f3x0_syscfg.c
  • SYSCFG_CPSCTL : gd32f3x0_syscfg.h
  • SYSCFG_CPSCTL_CPS_EN : gd32f3x0_syscfg.h
  • SYSCFG_CPSCTL_CPS_RDY : gd32f3x0_syscfg.h
  • syscfg_deinit() : gd32f3x0_syscfg.h , gd32f3x0_syscfg.c
  • SYSCFG_DMA_REMAP_ADC : gd32f3x0_syscfg.h
  • syscfg_dma_remap_disable() : gd32f3x0_syscfg.c , gd32f3x0_syscfg.h
  • syscfg_dma_remap_enable() : gd32f3x0_syscfg.h , gd32f3x0_syscfg.c
  • SYSCFG_DMA_REMAP_TIMER15 : gd32f3x0_syscfg.h
  • SYSCFG_DMA_REMAP_TIMER16 : gd32f3x0_syscfg.h
  • SYSCFG_DMA_REMAP_USART0RX : gd32f3x0_syscfg.h
  • SYSCFG_DMA_REMAP_USART0TX : gd32f3x0_syscfg.h
  • syscfg_exti_line_config() : gd32f3x0_syscfg.c , gd32f3x0_syscfg.h
  • SYSCFG_EXTISS0 : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS0_EXTI0_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS0_EXTI1_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS0_EXTI2_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS0_EXTI3_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS1 : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS1_EXTI4_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS1_EXTI5_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS1_EXTI6_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS1_EXTI7_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS2 : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS2_EXTI10_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS2_EXTI11_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS2_EXTI8_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS2_EXTI9_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS3 : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS3_EXTI12_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS3_EXTI13_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS3_EXTI14_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS3_EXTI15_SS : gd32f3x0_syscfg.h
  • syscfg_flag_clear() : gd32f3x0_syscfg.h , gd32f3x0_syscfg.c
  • syscfg_flag_get() : gd32f3x0_syscfg.h , gd32f3x0_syscfg.c
  • syscfg_high_current_disable() : gd32f3x0_syscfg.c
  • SYSCFG_HIGH_CURRENT_DISABLE : gd32f3x0_syscfg.h
  • syscfg_high_current_disable() : gd32f3x0_syscfg.h
  • syscfg_high_current_enable() : gd32f3x0_syscfg.h , gd32f3x0_syscfg.c
  • SYSCFG_HIGH_CURRENT_ENABLE : gd32f3x0_syscfg.h
  • syscfg_lock_config() : gd32f3x0_syscfg.c , gd32f3x0_syscfg.h
  • SYSCFG_LOCK_LOCKUP : gd32f3x0_syscfg.h
  • SYSCFG_LOCK_LVD : gd32f3x0_syscfg.h
  • SYSCFG_LOCK_SRAM_PARITY_ERROR : gd32f3x0_syscfg.h
  • SYSCFG_SRAM_PCEF : gd32f3x0_syscfg.h
  • system_lowpower_reset() : gd32f3x0_misc.h , gd32f3x0_misc.c
  • system_lowpower_set() : gd32f3x0_misc.h , gd32f3x0_misc.c
  • SystemCoreClock : system_gd32f3x0.c
  • SystemCoreClockUpdate() : system_gd32f3x0.c
  • SystemInit() : system_gd32f3x0.c
  • SYSTICK_CLKSOURCE_HCLK : gd32f3x0_misc.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : gd32f3x0_misc.h
  • systick_clksource_set() : gd32f3x0_misc.c , gd32f3x0_misc.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TAMP_FLT : gd32f3x0_rtc.h
  • TAMP_FREQ : gd32f3x0_rtc.h
  • TAMP_PRCH : gd32f3x0_rtc.h
  • TIME_HR : gd32f3x0_rtc.h
  • TIME_MN : gd32f3x0_rtc.h
  • TIME_SC : gd32f3x0_rtc.h
  • TIMER0 : gd32f3x0_timer.h
  • TIMER1 : gd32f3x0_timer.h
  • TIMER13 : gd32f3x0_timer.h
  • TIMER13_CI0_RMP_CKOUTSEL : gd32f3x0_timer.h
  • TIMER13_CI0_RMP_GPIO : gd32f3x0_timer.h
  • TIMER13_CI0_RMP_HXTAL_DIV32 : gd32f3x0_timer.h
  • TIMER13_CI0_RMP_RTCCLK : gd32f3x0_timer.h
  • TIMER13_IRMP : gd32f3x0_timer.h
  • TIMER13_IRMP_CI0_RMP : gd32f3x0_timer.h
  • TIMER14 : gd32f3x0_timer.h
  • TIMER15 : gd32f3x0_timer.h
  • TIMER16 : gd32f3x0_timer.h
  • TIMER2 : gd32f3x0_timer.h
  • timer_auto_reload_shadow_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_auto_reload_shadow_enable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_automatic_output_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_automatic_output_enable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_autoreload_value_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_break_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_break_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_BREAK_DISABLE : gd32f3x0_timer.h
  • TIMER_BREAK_ENABLE : gd32f3x0_timer.h
  • timer_break_enable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_BREAK_POLARITY_HIGH : gd32f3x0_timer.h
  • TIMER_BREAK_POLARITY_LOW : gd32f3x0_timer.h
  • TIMER_CAR : gd32f3x0_timer.h
  • TIMER_CAR_CARL16 : gd32f3x0_timer.h
  • TIMER_CAR_CARL32 : gd32f3x0_timer.h
  • TIMER_CCHP : gd32f3x0_timer.h
  • TIMER_CCHP_BRKEN : gd32f3x0_timer.h
  • TIMER_CCHP_BRKP : gd32f3x0_timer.h
  • TIMER_CCHP_DTCFG : gd32f3x0_timer.h
  • TIMER_CCHP_IOS : gd32f3x0_timer.h
  • TIMER_CCHP_OAEN : gd32f3x0_timer.h
  • TIMER_CCHP_POEN : gd32f3x0_timer.h
  • TIMER_CCHP_PROT : gd32f3x0_timer.h
  • TIMER_CCHP_PROT_0 : gd32f3x0_timer.h
  • TIMER_CCHP_PROT_1 : gd32f3x0_timer.h
  • TIMER_CCHP_PROT_2 : gd32f3x0_timer.h
  • TIMER_CCHP_PROT_OFF : gd32f3x0_timer.h
  • TIMER_CCHP_ROS : gd32f3x0_timer.h
  • TIMER_CCSEL_DISABLE : gd32f3x0_timer.h
  • TIMER_CCSEL_ENABLE : gd32f3x0_timer.h
  • TIMER_CCX_DISABLE : gd32f3x0_timer.h
  • TIMER_CCX_ENABLE : gd32f3x0_timer.h
  • TIMER_CCXN_DISABLE : gd32f3x0_timer.h
  • TIMER_CCXN_ENABLE : gd32f3x0_timer.h
  • TIMER_CFG : gd32f3x0_timer.h
  • TIMER_CFG_CHVSEL : gd32f3x0_timer.h
  • TIMER_CFG_OUTSEL : gd32f3x0_timer.h
  • TIMER_CH0CV : gd32f3x0_timer.h
  • TIMER_CH0CV_CH0VAL16 : gd32f3x0_timer.h
  • TIMER_CH0CV_CH0VAL32 : gd32f3x0_timer.h
  • TIMER_CH1CV : gd32f3x0_timer.h
  • TIMER_CH1CV_CH1VAL16 : gd32f3x0_timer.h
  • TIMER_CH1CV_CH1VAL32 : gd32f3x0_timer.h
  • TIMER_CH2CV : gd32f3x0_timer.h
  • TIMER_CH2CV_CH2VAL16 : gd32f3x0_timer.h
  • TIMER_CH2CV_CH2VAL32 : gd32f3x0_timer.h
  • TIMER_CH3CV : gd32f3x0_timer.h
  • TIMER_CH3CV_CH3VAL16 : gd32f3x0_timer.h
  • TIMER_CH3CV_CH3VAL32 : gd32f3x0_timer.h
  • TIMER_CH_0 : gd32f3x0_timer.h
  • TIMER_CH_1 : gd32f3x0_timer.h
  • TIMER_CH_2 : gd32f3x0_timer.h
  • TIMER_CH_3 : gd32f3x0_timer.h
  • timer_channel_capture_value_register_read() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_complementary_output_polarity_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_complementary_output_state_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_control_shadow_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_control_shadow_update_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_dma_request_source_select() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_input_capture_prescaler_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_clear_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_fast_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_mode_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_polarity_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_pulse_value_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_shadow_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_state_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_remap_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_CHCTL0 : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH0CAPFLT : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH0CAPPSC : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH0COMCEN : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH0COMCTL : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH0COMFEN : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH0COMSEN : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH0MS : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH1CAPFLT : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH1CAPPSC : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH1COMCEN : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH1COMCTL : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH1COMFEN : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH1COMSEN : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH1MS : gd32f3x0_timer.h
  • TIMER_CHCTL1 : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH2CAPFLT : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH2CAPPSC : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH2COMCEN : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH2COMCTL : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH2COMFEN : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH2COMSEN : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH2MS : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH3CAPFLT : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH3CAPPSC : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH3COMCEN : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH3COMCTL : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH3COMFEN : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH3COMSEN : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH3MS : gd32f3x0_timer.h
  • TIMER_CHCTL2 : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH0EN : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH0NEN : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH0NP : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH0P : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH1EN : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH1NEN : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH1NP : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH1P : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH2EN : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH2NEN : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH2NP : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH2P : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH3EN : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH3NP : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH3P : gd32f3x0_timer.h
  • TIMER_CKDIV_DIV1 : gd32f3x0_timer.h
  • TIMER_CKDIV_DIV2 : gd32f3x0_timer.h
  • TIMER_CKDIV_DIV4 : gd32f3x0_timer.h
  • TIMER_CNT : gd32f3x0_timer.h
  • TIMER_CNT_CNT16 : gd32f3x0_timer.h
  • TIMER_CNT_CNT32 : gd32f3x0_timer.h
  • timer_counter_alignment() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_COUNTER_CENTER_BOTH : gd32f3x0_timer.h
  • TIMER_COUNTER_CENTER_DOWN : gd32f3x0_timer.h
  • TIMER_COUNTER_CENTER_UP : gd32f3x0_timer.h
  • TIMER_COUNTER_DOWN : gd32f3x0_timer.h
  • timer_counter_down_direction() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_COUNTER_EDGE : gd32f3x0_timer.h
  • timer_counter_read() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_COUNTER_UP : gd32f3x0_timer.h
  • timer_counter_up_direction() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_counter_value_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_CREP : gd32f3x0_timer.h
  • TIMER_CREP_CREP : gd32f3x0_timer.h
  • TIMER_CTL0 : gd32f3x0_timer.h
  • TIMER_CTL0_ARSE : gd32f3x0_timer.h
  • TIMER_CTL0_CAM : gd32f3x0_timer.h
  • TIMER_CTL0_CEN : gd32f3x0_timer.h
  • TIMER_CTL0_CKDIV : gd32f3x0_timer.h
  • TIMER_CTL0_DIR : gd32f3x0_timer.h
  • TIMER_CTL0_SPM : gd32f3x0_timer.h
  • TIMER_CTL0_UPDIS : gd32f3x0_timer.h
  • TIMER_CTL0_UPS : gd32f3x0_timer.h
  • TIMER_CTL1 : gd32f3x0_timer.h
  • TIMER_CTL1_CCSE : gd32f3x0_timer.h
  • TIMER_CTL1_CCUC : gd32f3x0_timer.h
  • TIMER_CTL1_DMAS : gd32f3x0_timer.h
  • TIMER_CTL1_ISO0 : gd32f3x0_timer.h
  • TIMER_CTL1_ISO0N : gd32f3x0_timer.h
  • TIMER_CTL1_ISO1 : gd32f3x0_timer.h
  • TIMER_CTL1_ISO1N : gd32f3x0_timer.h
  • TIMER_CTL1_ISO2 : gd32f3x0_timer.h
  • TIMER_CTL1_ISO2N : gd32f3x0_timer.h
  • TIMER_CTL1_ISO3 : gd32f3x0_timer.h
  • TIMER_CTL1_MMC : gd32f3x0_timer.h
  • TIMER_CTL1_TI0S : gd32f3x0_timer.h
  • timer_deinit() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_DMA_CH0D : gd32f3x0_timer.h
  • TIMER_DMA_CH1D : gd32f3x0_timer.h
  • TIMER_DMA_CH2D : gd32f3x0_timer.h
  • TIMER_DMA_CH3D : gd32f3x0_timer.h
  • TIMER_DMA_CMTD : gd32f3x0_timer.h
  • timer_dma_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_dma_enable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_dma_transfer_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_DMA_TRGD : gd32f3x0_timer.h
  • TIMER_DMA_UPD : gd32f3x0_timer.h
  • TIMER_DMACFG : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CAR : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CCHP : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CH0CV : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CH1CV : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CH2CV : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CH3CV : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CHCTL0 : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CHCTL1 : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CHCTL2 : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CNT : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CREP : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CTL0 : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CTL1 : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_DMACFG : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_DMAINTEN : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_DMATB : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_INTF : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_PSC : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_SMCFG : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_SWEVG : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_10TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_11TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_12TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_13TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_14TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_15TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_16TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_17TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_18TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_1TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_2TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_3TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_4TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_5TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_6TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_7TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_8TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_9TRANSFER : gd32f3x0_timer.h
  • TIMER_DMAINTEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_BRKIE : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH0DEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH0IE : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH1DEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH1IE : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH2DEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH2IE : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH3DEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH3IE : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CMTDEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CMTIE : gd32f3x0_timer.h
  • TIMER_DMAINTEN_TRGDEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_TRGIE : gd32f3x0_timer.h
  • TIMER_DMAINTEN_UPDEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_UPIE : gd32f3x0_timer.h
  • TIMER_DMAREQUEST_CHANNELEVENT : gd32f3x0_timer.h
  • TIMER_DMAREQUEST_UPDATEEVENT : gd32f3x0_timer.h
  • TIMER_DMATB : gd32f3x0_timer.h
  • TIMER_DMATB_DMATB : gd32f3x0_timer.h
  • timer_enable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_ENCODER_MODE0 : gd32f3x0_timer.h
  • TIMER_ENCODER_MODE1 : gd32f3x0_timer.h
  • TIMER_ENCODER_MODE2 : gd32f3x0_timer.h
  • TIMER_ETP_FALLING : gd32f3x0_timer.h
  • TIMER_ETP_RISING : gd32f3x0_timer.h
  • timer_event_software_generate() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_EVENT_SRC_BRKG : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_CH0G : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_CH1G : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_CH2G : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_CH3G : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_CMTG : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_TRGG : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_UPG : gd32f3x0_timer.h
  • TIMER_EXT_TRI_PSC_DIV2 : gd32f3x0_timer.h
  • TIMER_EXT_TRI_PSC_DIV4 : gd32f3x0_timer.h
  • TIMER_EXT_TRI_PSC_DIV8 : gd32f3x0_timer.h
  • TIMER_EXT_TRI_PSC_OFF : gd32f3x0_timer.h
  • timer_external_clock_mode0_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_external_clock_mode1_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_external_clock_mode1_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_external_trigger_as_external_clock_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_external_trigger_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_FLAG_BRK : gd32f3x0_timer.h
  • TIMER_FLAG_CH0 : gd32f3x0_timer.h
  • TIMER_FLAG_CH0O : gd32f3x0_timer.h
  • TIMER_FLAG_CH1 : gd32f3x0_timer.h
  • TIMER_FLAG_CH1O : gd32f3x0_timer.h
  • TIMER_FLAG_CH2 : gd32f3x0_timer.h
  • TIMER_FLAG_CH2O : gd32f3x0_timer.h
  • TIMER_FLAG_CH3 : gd32f3x0_timer.h
  • TIMER_FLAG_CH3O : gd32f3x0_timer.h
  • timer_flag_clear() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_FLAG_CMT : gd32f3x0_timer.h
  • timer_flag_get() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_FLAG_TRG : gd32f3x0_timer.h
  • TIMER_FLAG_UP : gd32f3x0_timer.h
  • timer_hall_mode_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_HALLINTERFACE_DISABLE : gd32f3x0_timer.h
  • TIMER_HALLINTERFACE_ENABLE : gd32f3x0_timer.h
  • TIMER_IC_POLARITY_BOTH_EDGE : gd32f3x0_timer.h
  • TIMER_IC_POLARITY_FALLING : gd32f3x0_timer.h
  • TIMER_IC_POLARITY_RISING : gd32f3x0_timer.h
  • TIMER_IC_PSC_DIV1 : gd32f3x0_timer.h
  • TIMER_IC_PSC_DIV2 : gd32f3x0_timer.h
  • TIMER_IC_PSC_DIV4 : gd32f3x0_timer.h
  • TIMER_IC_PSC_DIV8 : gd32f3x0_timer.h
  • TIMER_IC_SELECTION_DIRECTTI : gd32f3x0_timer.h
  • TIMER_IC_SELECTION_INDIRECTTI : gd32f3x0_timer.h
  • TIMER_IC_SELECTION_ITS : gd32f3x0_timer.h
  • timer_init() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_input_capture_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_input_pwm_capture_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_input_trigger_source_select() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_INT_BRK : gd32f3x0_timer.h
  • TIMER_INT_CH0 : gd32f3x0_timer.h
  • TIMER_INT_CH1 : gd32f3x0_timer.h
  • TIMER_INT_CH2 : gd32f3x0_timer.h
  • TIMER_INT_CH3 : gd32f3x0_timer.h
  • TIMER_INT_CMT : gd32f3x0_timer.h
  • TIMER_INT_FLAG_BRK : gd32f3x0_timer.h
  • TIMER_INT_FLAG_CH0 : gd32f3x0_timer.h
  • TIMER_INT_FLAG_CH1 : gd32f3x0_timer.h
  • TIMER_INT_FLAG_CH2 : gd32f3x0_timer.h
  • TIMER_INT_FLAG_CH3 : gd32f3x0_timer.h
  • TIMER_INT_FLAG_CMT : gd32f3x0_timer.h
  • TIMER_INT_FLAG_TRG : gd32f3x0_timer.h
  • TIMER_INT_FLAG_UP : gd32f3x0_timer.h
  • TIMER_INT_TRG : gd32f3x0_timer.h
  • TIMER_INT_UP : gd32f3x0_timer.h
  • timer_internal_clock_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_internal_trigger_as_external_clock_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_interrupt_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_interrupt_enable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_interrupt_flag_clear() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_interrupt_flag_get() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_INTF : gd32f3x0_timer.h
  • TIMER_INTF_BRKIF : gd32f3x0_timer.h
  • TIMER_INTF_CH0IF : gd32f3x0_timer.h
  • TIMER_INTF_CH0OF : gd32f3x0_timer.h
  • TIMER_INTF_CH1IF : gd32f3x0_timer.h
  • TIMER_INTF_CH1OF : gd32f3x0_timer.h
  • TIMER_INTF_CH2IF : gd32f3x0_timer.h
  • TIMER_INTF_CH2OF : gd32f3x0_timer.h
  • TIMER_INTF_CH3IF : gd32f3x0_timer.h
  • TIMER_INTF_CH3OF : gd32f3x0_timer.h
  • TIMER_INTF_CMTIF : gd32f3x0_timer.h
  • TIMER_INTF_TRGIF : gd32f3x0_timer.h
  • TIMER_INTF_UPIF : gd32f3x0_timer.h
  • TIMER_IOS_STATE_DISABLE : gd32f3x0_timer.h
  • TIMER_IOS_STATE_ENABLE : gd32f3x0_timer.h
  • TIMER_IRMP : gd32f3x0_timer.h
  • timer_master_output_trigger_source_select() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_master_slave_mode_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_MASTER_SLAVE_MODE_DISABLE : gd32f3x0_timer.h
  • TIMER_MASTER_SLAVE_MODE_ENABLE : gd32f3x0_timer.h
  • TIMER_OC_CLEAR_DISABLE : gd32f3x0_timer.h
  • TIMER_OC_CLEAR_ENABLE : gd32f3x0_timer.h
  • TIMER_OC_FAST_DISABLE : gd32f3x0_timer.h
  • TIMER_OC_FAST_ENABLE : gd32f3x0_timer.h
  • TIMER_OC_IDLE_STATE_HIGH : gd32f3x0_timer.h
  • TIMER_OC_IDLE_STATE_LOW : gd32f3x0_timer.h
  • TIMER_OC_MODE_ACTIVE : gd32f3x0_timer.h
  • TIMER_OC_MODE_HIGH : gd32f3x0_timer.h
  • TIMER_OC_MODE_INACTIVE : gd32f3x0_timer.h
  • TIMER_OC_MODE_LOW : gd32f3x0_timer.h
  • TIMER_OC_MODE_PWM0 : gd32f3x0_timer.h
  • TIMER_OC_MODE_PWM1 : gd32f3x0_timer.h
  • TIMER_OC_MODE_TIMING : gd32f3x0_timer.h
  • TIMER_OC_MODE_TOGGLE : gd32f3x0_timer.h
  • TIMER_OC_POLARITY_HIGH : gd32f3x0_timer.h
  • TIMER_OC_POLARITY_LOW : gd32f3x0_timer.h
  • TIMER_OC_SHADOW_DISABLE : gd32f3x0_timer.h
  • TIMER_OC_SHADOW_ENABLE : gd32f3x0_timer.h
  • TIMER_OCN_IDLE_STATE_HIGH : gd32f3x0_timer.h
  • TIMER_OCN_IDLE_STATE_LOW : gd32f3x0_timer.h
  • TIMER_OCN_POLARITY_HIGH : gd32f3x0_timer.h
  • TIMER_OCN_POLARITY_LOW : gd32f3x0_timer.h
  • TIMER_OCPRE_CLEAR_SOURCE_CLR : gd32f3x0_timer.h
  • timer_ocpre_clear_source_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_OCPRE_CLEAR_SOURCE_ETIF : gd32f3x0_timer.h
  • TIMER_OUTAUTO_DISABLE : gd32f3x0_timer.h
  • TIMER_OUTAUTO_ENABLE : gd32f3x0_timer.h
  • timer_output_value_selection_config() : gd32f3x0_timer.c , gd32f3x0_timer.h
  • TIMER_OUTSEL_DISABLE : gd32f3x0_timer.h
  • TIMER_OUTSEL_ENABLE : gd32f3x0_timer.h
  • timer_prescaler_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_prescaler_read() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_primary_output_config() : gd32f3x0_timer.c , gd32f3x0_timer.h
  • TIMER_PSC : gd32f3x0_timer.h
  • TIMER_PSC_PSC : gd32f3x0_timer.h
  • TIMER_PSC_RELOAD_NOW : gd32f3x0_timer.h
  • TIMER_PSC_RELOAD_UPDATE : gd32f3x0_timer.h
  • timer_quadrature_decoder_mode_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_repetition_value_config() : gd32f3x0_timer.c , gd32f3x0_timer.h
  • TIMER_ROS_STATE_DISABLE : gd32f3x0_timer.h
  • TIMER_ROS_STATE_ENABLE : gd32f3x0_timer.h
  • timer_single_pulse_mode_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_SLAVE_MODE_DISABLE : gd32f3x0_timer.h
  • TIMER_SLAVE_MODE_EVENT : gd32f3x0_timer.h
  • TIMER_SLAVE_MODE_EXTERNAL0 : gd32f3x0_timer.h
  • TIMER_SLAVE_MODE_PAUSE : gd32f3x0_timer.h
  • TIMER_SLAVE_MODE_RESTART : gd32f3x0_timer.h
  • timer_slave_mode_select() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_SMCFG : gd32f3x0_timer.h
  • TIMER_SMCFG_ETFC : gd32f3x0_timer.h
  • TIMER_SMCFG_ETP : gd32f3x0_timer.h
  • TIMER_SMCFG_ETPSC : gd32f3x0_timer.h
  • TIMER_SMCFG_MSM : gd32f3x0_timer.h
  • TIMER_SMCFG_OCRC : gd32f3x0_timer.h
  • TIMER_SMCFG_SMC : gd32f3x0_timer.h
  • TIMER_SMCFG_SMC1 : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGS : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_CI0F_ED : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_CI0FE0 : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_CI1FE1 : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_ETIFP : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_ITI0 : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_ITI1 : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_ITI2 : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_ITI3 : gd32f3x0_timer.h
  • TIMER_SP_MODE_REPETITIVE : gd32f3x0_timer.h
  • TIMER_SP_MODE_SINGLE : gd32f3x0_timer.h
  • TIMER_SWEVG : gd32f3x0_timer.h
  • TIMER_SWEVG_BRKG : gd32f3x0_timer.h
  • TIMER_SWEVG_CH0G : gd32f3x0_timer.h
  • TIMER_SWEVG_CH1G : gd32f3x0_timer.h
  • TIMER_SWEVG_CH2G : gd32f3x0_timer.h
  • TIMER_SWEVG_CH3G : gd32f3x0_timer.h
  • TIMER_SWEVG_CMTG : gd32f3x0_timer.h
  • TIMER_SWEVG_TRGG : gd32f3x0_timer.h
  • TIMER_SWEVG_UPG : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_CC0 : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_ENABLE : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_O0CPRE : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_O1CPRE : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_O2CPRE : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_O3CPRE : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_RESET : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_UPDATE : gd32f3x0_timer.h
  • timer_update_event_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_update_event_enable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_update_source_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TIMER_UPDATE_SRC_GLOBAL : gd32f3x0_timer.h
  • TIMER_UPDATE_SRC_REGULAR : gd32f3x0_timer.h
  • TIMER_UPDATECTL_CCU : gd32f3x0_timer.h
  • TIMER_UPDATECTL_CCUTRI : gd32f3x0_timer.h
  • timer_write_cc_register_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • TSI : gd32f3x0_tsi.h
  • tsi_analog_off() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_analog_on() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • TSI_ASW : gd32f3x0_tsi.h
  • TSI_ASW_G0P0 : gd32f3x0_tsi.h
  • TSI_ASW_G0P1 : gd32f3x0_tsi.h
  • TSI_ASW_G0P2 : gd32f3x0_tsi.h
  • TSI_ASW_G0P3 : gd32f3x0_tsi.h
  • TSI_ASW_G1P0 : gd32f3x0_tsi.h
  • TSI_ASW_G1P1 : gd32f3x0_tsi.h
  • TSI_ASW_G1P2 : gd32f3x0_tsi.h
  • TSI_ASW_G1P3 : gd32f3x0_tsi.h
  • TSI_ASW_G2P0 : gd32f3x0_tsi.h
  • TSI_ASW_G2P1 : gd32f3x0_tsi.h
  • TSI_ASW_G2P2 : gd32f3x0_tsi.h
  • TSI_ASW_G2P3 : gd32f3x0_tsi.h
  • TSI_ASW_G3P0 : gd32f3x0_tsi.h
  • TSI_ASW_G3P1 : gd32f3x0_tsi.h
  • TSI_ASW_G3P2 : gd32f3x0_tsi.h
  • TSI_ASW_G3P3 : gd32f3x0_tsi.h
  • TSI_ASW_G4P0 : gd32f3x0_tsi.h
  • TSI_ASW_G4P1 : gd32f3x0_tsi.h
  • TSI_ASW_G4P2 : gd32f3x0_tsi.h
  • TSI_ASW_G4P3 : gd32f3x0_tsi.h
  • TSI_ASW_G5P0 : gd32f3x0_tsi.h
  • TSI_ASW_G5P1 : gd32f3x0_tsi.h
  • TSI_ASW_G5P2 : gd32f3x0_tsi.h
  • TSI_ASW_G5P3 : gd32f3x0_tsi.h
  • tsi_channel_pin_disable() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_channel_pin_enable() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • TSI_CHARGE_10CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_11CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_12CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_13CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_14CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_15CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_16CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_1CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_2CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_3CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_4CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_5CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_6CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_7CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_8CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_9CTCLK : gd32f3x0_tsi.h
  • TSI_CHCFG : gd32f3x0_tsi.h
  • TSI_CHCFG_G0P0 : gd32f3x0_tsi.h
  • TSI_CHCFG_G0P1 : gd32f3x0_tsi.h
  • TSI_CHCFG_G0P2 : gd32f3x0_tsi.h
  • TSI_CHCFG_G0P3 : gd32f3x0_tsi.h
  • TSI_CHCFG_G1P0 : gd32f3x0_tsi.h
  • TSI_CHCFG_G1P1 : gd32f3x0_tsi.h
  • TSI_CHCFG_G1P2 : gd32f3x0_tsi.h
  • TSI_CHCFG_G1P3 : gd32f3x0_tsi.h
  • TSI_CHCFG_G2P0 : gd32f3x0_tsi.h
  • TSI_CHCFG_G2P1 : gd32f3x0_tsi.h
  • TSI_CHCFG_G2P2 : gd32f3x0_tsi.h
  • TSI_CHCFG_G2P3 : gd32f3x0_tsi.h
  • TSI_CHCFG_G3P0 : gd32f3x0_tsi.h
  • TSI_CHCFG_G3P1 : gd32f3x0_tsi.h
  • TSI_CHCFG_G3P2 : gd32f3x0_tsi.h
  • TSI_CHCFG_G3P3 : gd32f3x0_tsi.h
  • TSI_CHCFG_G4P0 : gd32f3x0_tsi.h
  • TSI_CHCFG_G4P1 : gd32f3x0_tsi.h
  • TSI_CHCFG_G4P2 : gd32f3x0_tsi.h
  • TSI_CHCFG_G4P3 : gd32f3x0_tsi.h
  • TSI_CHCFG_G5P0 : gd32f3x0_tsi.h
  • TSI_CHCFG_G5P1 : gd32f3x0_tsi.h
  • TSI_CHCFG_G5P2 : gd32f3x0_tsi.h
  • TSI_CHCFG_G5P3 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV1 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV1024 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV128 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV16 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV16384 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV2 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV2048 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV256 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV32 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV32768 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV4 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV4096 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV512 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV64 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV8 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV8192 : gd32f3x0_tsi.h
  • TSI_CTL0 : gd32f3x0_tsi.h
  • TSI_CTL0_CDT : gd32f3x0_tsi.h
  • TSI_CTL0_CTCDIV : gd32f3x0_tsi.h
  • TSI_CTL0_CTDT : gd32f3x0_tsi.h
  • TSI_CTL0_ECDIV : gd32f3x0_tsi.h
  • TSI_CTL0_ECDT : gd32f3x0_tsi.h
  • TSI_CTL0_ECEN : gd32f3x0_tsi.h
  • TSI_CTL0_EGSEL : gd32f3x0_tsi.h
  • TSI_CTL0_MCN : gd32f3x0_tsi.h
  • TSI_CTL0_PINMOD : gd32f3x0_tsi.h
  • TSI_CTL0_TRGMOD : gd32f3x0_tsi.h
  • TSI_CTL0_TSIEN : gd32f3x0_tsi.h
  • TSI_CTL0_TSIS : gd32f3x0_tsi.h
  • TSI_CTL1 : gd32f3x0_tsi.h
  • TSI_CTL1_CTCDIV : gd32f3x0_tsi.h
  • TSI_CTL1_ECDIV : gd32f3x0_tsi.h
  • tsi_deinit() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_disable() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_enable() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_extend_charge_config() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • TSI_EXTEND_DIV1 : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV2 : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV3 : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV4 : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV5 : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV6 : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV7 : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV8 : gd32f3x0_tsi.h
  • TSI_EXTENDMAX : gd32f3x0_tsi.h
  • TSI_FALLING_TRIGGER : gd32f3x0_tsi.h
  • tsi_flag_clear() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • TSI_FLAG_CTCF : gd32f3x0_tsi.h
  • TSI_FLAG_CTCF_CLR : gd32f3x0_tsi.h
  • tsi_flag_get() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • TSI_FLAG_MNERR : gd32f3x0_tsi.h
  • TSI_FLAG_MNERR_CLR : gd32f3x0_tsi.h
  • TSI_G0CYCN : gd32f3x0_tsi.h
  • TSI_G1CYCN : gd32f3x0_tsi.h
  • TSI_G2CYCN : gd32f3x0_tsi.h
  • TSI_G3CYCN : gd32f3x0_tsi.h
  • TSI_G4CYCN : gd32f3x0_tsi.h
  • TSI_G5CYCN : gd32f3x0_tsi.h
  • TSI_GCTL : gd32f3x0_tsi.h
  • TSI_GCTL_GC0 : gd32f3x0_tsi.h
  • TSI_GCTL_GC1 : gd32f3x0_tsi.h
  • TSI_GCTL_GC2 : gd32f3x0_tsi.h
  • TSI_GCTL_GC3 : gd32f3x0_tsi.h
  • TSI_GCTL_GC4 : gd32f3x0_tsi.h
  • TSI_GCTL_GC5 : gd32f3x0_tsi.h
  • TSI_GCTL_GE0 : gd32f3x0_tsi.h
  • TSI_GCTL_GE1 : gd32f3x0_tsi.h
  • TSI_GCTL_GE2 : gd32f3x0_tsi.h
  • TSI_GCTL_GE3 : gd32f3x0_tsi.h
  • TSI_GCTL_GE4 : gd32f3x0_tsi.h
  • TSI_GCTL_GE5 : gd32f3x0_tsi.h
  • tsi_group0_cycle_get() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_group1_cycle_get() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_group2_cycle_get() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_group3_cycle_get() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_group4_cycle_get() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_group5_cycle_get() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_group_disable() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_group_enable() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_group_status_get() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_hardware_mode_config() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_hysteresis_off() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_hysteresis_on() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_init() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • TSI_INPUT_FLOATING : gd32f3x0_tsi.h
  • TSI_INT_CCTCF : gd32f3x0_tsi.h
  • TSI_INT_FLAG_CTCF : gd32f3x0_tsi.h
  • TSI_INT_FLAG_CTCF_CLR : gd32f3x0_tsi.h
  • TSI_INT_FLAG_MNERR : gd32f3x0_tsi.h
  • TSI_INT_FLAG_MNERR_CLR : gd32f3x0_tsi.h
  • TSI_INT_MNERR : gd32f3x0_tsi.h
  • TSI_INTC : gd32f3x0_tsi.h
  • TSI_INTC_CCTCF : gd32f3x0_tsi.h
  • TSI_INTC_CMNERR : gd32f3x0_tsi.h
  • TSI_INTEN : gd32f3x0_tsi.h
  • TSI_INTEN_CTCFIE : gd32f3x0_tsi.h
  • TSI_INTEN_MNERRIE : gd32f3x0_tsi.h
  • tsi_interrupt_disable() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_interrupt_enable() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_interrupt_flag_clear() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_interrupt_flag_get() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • TSI_INTF : gd32f3x0_tsi.h
  • TSI_INTF_CTCF : gd32f3x0_tsi.h
  • TSI_INTF_MNERR : gd32f3x0_tsi.h
  • tsi_max_number_config() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • TSI_MAXNUM1023 : gd32f3x0_tsi.h
  • TSI_MAXNUM16383 : gd32f3x0_tsi.h
  • TSI_MAXNUM2047 : gd32f3x0_tsi.h
  • TSI_MAXNUM255 : gd32f3x0_tsi.h
  • TSI_MAXNUM4095 : gd32f3x0_tsi.h
  • TSI_MAXNUM511 : gd32f3x0_tsi.h
  • TSI_MAXNUM8191 : gd32f3x0_tsi.h
  • TSI_OUTPUT_LOW : gd32f3x0_tsi.h
  • TSI_PHM : gd32f3x0_tsi.h
  • TSI_PHM_G0P0 : gd32f3x0_tsi.h
  • TSI_PHM_G0P1 : gd32f3x0_tsi.h
  • TSI_PHM_G0P2 : gd32f3x0_tsi.h
  • TSI_PHM_G0P3 : gd32f3x0_tsi.h
  • TSI_PHM_G1P0 : gd32f3x0_tsi.h
  • TSI_PHM_G1P1 : gd32f3x0_tsi.h
  • TSI_PHM_G1P2 : gd32f3x0_tsi.h
  • TSI_PHM_G1P3 : gd32f3x0_tsi.h
  • TSI_PHM_G2P0 : gd32f3x0_tsi.h
  • TSI_PHM_G2P1 : gd32f3x0_tsi.h
  • TSI_PHM_G2P2 : gd32f3x0_tsi.h
  • TSI_PHM_G2P3 : gd32f3x0_tsi.h
  • TSI_PHM_G3P0 : gd32f3x0_tsi.h
  • TSI_PHM_G3P1 : gd32f3x0_tsi.h
  • TSI_PHM_G3P2 : gd32f3x0_tsi.h
  • TSI_PHM_G3P3 : gd32f3x0_tsi.h
  • TSI_PHM_G4P0 : gd32f3x0_tsi.h
  • TSI_PHM_G4P1 : gd32f3x0_tsi.h
  • TSI_PHM_G4P2 : gd32f3x0_tsi.h
  • TSI_PHM_G4P3 : gd32f3x0_tsi.h
  • TSI_PHM_G5P0 : gd32f3x0_tsi.h
  • TSI_PHM_G5P1 : gd32f3x0_tsi.h
  • TSI_PHM_G5P2 : gd32f3x0_tsi.h
  • TSI_PHM_G5P3 : gd32f3x0_tsi.h
  • tsi_pin_mode_config() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_plus_config() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • TSI_RISING_TRIGGER : gd32f3x0_tsi.h
  • TSI_SAMPCFG : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G0P0 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G0P1 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G0P2 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G0P3 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G1P0 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G1P1 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G1P2 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G1P3 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G2P0 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G2P1 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G2P2 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G2P3 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G3P0 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G3P1 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G3P2 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G3P3 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G4P0 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G4P1 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G4P2 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G4P3 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G5P0 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G5P1 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G5P2 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G5P3 : gd32f3x0_tsi.h
  • tsi_sample_pin_disable() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_sample_pin_enable() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_sofeware_mode_config() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_software_start() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_software_stop() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • TSI_TRANSFER_10CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_11CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_12CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_13CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_14CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_15CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_16CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_1CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_2CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_3CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_4CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_5CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_6CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_7CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_8CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_9CTCLK : gd32f3x0_tsi.h
  • TTS_HR : gd32f3x0_rtc.h
  • TTS_MN : gd32f3x0_rtc.h
  • TTS_SC : gd32f3x0_rtc.h
  • TXFIFO_EMPTY : usb_regs.h
  • TXFIFO_EMPTY_HALF : usb_regs.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
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  • r
  • s
  • t
  • u
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • UNLOCK_KEY0 : gd32f3x0_fmc.h
  • UNLOCK_KEY1 : gd32f3x0_fmc.h
  • UP_STATE : usbh_core.h
  • URB_DONE : usb_core.h
  • URB_ERROR : usb_core.h
  • URB_IDLE : usb_core.h
  • URB_NOTREADY : usb_core.h
  • URB_PING : usb_core.h
  • URB_STALL : usb_core.h
  • urb_state_enum : usb_core.h
  • USART0 : gd32f3x0_usart.h
  • USART1 : gd32f3x0_usart.h
  • USART_ABDM_FTOF : gd32f3x0_usart.h
  • USART_ABDM_FTOR : gd32f3x0_usart.h
  • USART_ADDM_4BIT : gd32f3x0_usart.h
  • USART_ADDM_FULLBIT : gd32f3x0_usart.h
  • usart_address_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_address_detection_mode_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_autobaud_detection_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_autobaud_detection_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_autobaud_detection_mode_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_BAUD : gd32f3x0_usart.h
  • USART_BAUD_FRADIV : gd32f3x0_usart.h
  • USART_BAUD_INTDIV : gd32f3x0_usart.h
  • usart_baudrate_set() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_BIT_POS : gd32f3x0_usart.h
  • USART_BIT_POS2 : gd32f3x0_usart.h
  • usart_block_length_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_CLEN_EN : gd32f3x0_usart.h
  • USART_CLEN_NONE : gd32f3x0_usart.h
  • usart_clock_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_clock_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_CMD : gd32f3x0_usart.h
  • USART_CMD_ABDCMD : gd32f3x0_usart.h
  • USART_CMD_MMCMD : gd32f3x0_usart.h
  • USART_CMD_RXFCMD : gd32f3x0_usart.h
  • USART_CMD_SBKCMD : gd32f3x0_usart.h
  • USART_CMD_TXFCMD : gd32f3x0_usart.h
  • usart_command_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_CPH_1CK : gd32f3x0_usart.h
  • USART_CPH_2CK : gd32f3x0_usart.h
  • USART_CPL_HIGH : gd32f3x0_usart.h
  • USART_CPL_LOW : gd32f3x0_usart.h
  • USART_CTL0 : gd32f3x0_usart.h
  • USART_CTL0_AMIE : gd32f3x0_usart.h
  • USART_CTL0_DEA : gd32f3x0_usart.h
  • USART_CTL0_DED : gd32f3x0_usart.h
  • USART_CTL0_EBIE : gd32f3x0_usart.h
  • USART_CTL0_IDLEIE : gd32f3x0_usart.h
  • USART_CTL0_MEN : gd32f3x0_usart.h
  • USART_CTL0_OVSMOD : gd32f3x0_usart.h
  • USART_CTL0_PCEN : gd32f3x0_usart.h
  • USART_CTL0_PERRIE : gd32f3x0_usart.h
  • USART_CTL0_PM : gd32f3x0_usart.h
  • USART_CTL0_RBNEIE : gd32f3x0_usart.h
  • USART_CTL0_REG_OFFSET : gd32f3x0_usart.h
  • USART_CTL0_REN : gd32f3x0_usart.h
  • USART_CTL0_RTIE : gd32f3x0_usart.h
  • USART_CTL0_TBEIE : gd32f3x0_usart.h
  • USART_CTL0_TCIE : gd32f3x0_usart.h
  • USART_CTL0_TEN : gd32f3x0_usart.h
  • USART_CTL0_UEN : gd32f3x0_usart.h
  • USART_CTL0_UESM : gd32f3x0_usart.h
  • USART_CTL0_WL : gd32f3x0_usart.h
  • USART_CTL0_WM : gd32f3x0_usart.h
  • USART_CTL1 : gd32f3x0_usart.h
  • USART_CTL1_ABDEN : gd32f3x0_usart.h
  • USART_CTL1_ABDM : gd32f3x0_usart.h
  • USART_CTL1_ADDM : gd32f3x0_usart.h
  • USART_CTL1_ADDR : gd32f3x0_usart.h
  • USART_CTL1_CKEN : gd32f3x0_usart.h
  • USART_CTL1_CLEN : gd32f3x0_usart.h
  • USART_CTL1_CPH : gd32f3x0_usart.h
  • USART_CTL1_CPL : gd32f3x0_usart.h
  • USART_CTL1_DINV : gd32f3x0_usart.h
  • USART_CTL1_LBDIE : gd32f3x0_usart.h
  • USART_CTL1_LBLEN : gd32f3x0_usart.h
  • USART_CTL1_LMEN : gd32f3x0_usart.h
  • USART_CTL1_MSBF : gd32f3x0_usart.h
  • USART_CTL1_REG_OFFSET : gd32f3x0_usart.h
  • USART_CTL1_RINV : gd32f3x0_usart.h
  • USART_CTL1_RTEN : gd32f3x0_usart.h
  • USART_CTL1_STB : gd32f3x0_usart.h
  • USART_CTL1_STRP : gd32f3x0_usart.h
  • USART_CTL1_TINV : gd32f3x0_usart.h
  • USART_CTL2 : gd32f3x0_usart.h
  • USART_CTL2_CTSEN : gd32f3x0_usart.h
  • USART_CTL2_CTSIE : gd32f3x0_usart.h
  • USART_CTL2_DDRE : gd32f3x0_usart.h
  • USART_CTL2_DEM : gd32f3x0_usart.h
  • USART_CTL2_DENR : gd32f3x0_usart.h
  • USART_CTL2_DENT : gd32f3x0_usart.h
  • USART_CTL2_DEP : gd32f3x0_usart.h
  • USART_CTL2_ERRIE : gd32f3x0_usart.h
  • USART_CTL2_HDEN : gd32f3x0_usart.h
  • USART_CTL2_IREN : gd32f3x0_usart.h
  • USART_CTL2_IRLP : gd32f3x0_usart.h
  • USART_CTL2_NKEN : gd32f3x0_usart.h
  • USART_CTL2_OSB : gd32f3x0_usart.h
  • USART_CTL2_OVRD : gd32f3x0_usart.h
  • USART_CTL2_REG_OFFSET : gd32f3x0_usart.h
  • USART_CTL2_RTSEN : gd32f3x0_usart.h
  • USART_CTL2_SCEN : gd32f3x0_usart.h
  • USART_CTL2_SCRTNUM : gd32f3x0_usart.h
  • USART_CTL2_WUIE : gd32f3x0_usart.h
  • USART_CTL2_WUM : gd32f3x0_usart.h
  • USART_CTS_DISABLE : gd32f3x0_usart.h
  • USART_CTS_ENABLE : gd32f3x0_usart.h
  • usart_data_first_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_data_receive() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_data_transmit() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_deinit() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_DENR_DISABLE : gd32f3x0_usart.h
  • USART_DENR_ENABLE : gd32f3x0_usart.h
  • USART_DENT_DISABLE : gd32f3x0_usart.h
  • USART_DENT_ENABLE : gd32f3x0_usart.h
  • USART_DEP_HIGH : gd32f3x0_usart.h
  • USART_DEP_LOW : gd32f3x0_usart.h
  • usart_depolarity_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_DINV_DISABLE : gd32f3x0_usart.h
  • USART_DINV_ENABLE : gd32f3x0_usart.h
  • usart_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_dma_receive_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_dma_transmit_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_driver_assertime_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_driver_deassertime_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_FLAG_ABD : gd32f3x0_usart.h
  • USART_FLAG_ABDE : gd32f3x0_usart.h
  • USART_FLAG_AM : gd32f3x0_usart.h
  • USART_FLAG_BSY : gd32f3x0_usart.h
  • usart_flag_clear() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_FLAG_CTS : gd32f3x0_usart.h
  • USART_FLAG_CTSF : gd32f3x0_usart.h
  • USART_FLAG_EB : gd32f3x0_usart.h
  • usart_flag_enum : gd32f3x0_usart.h
  • USART_FLAG_FERR : gd32f3x0_usart.h
  • usart_flag_get() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_FLAG_IDLE : gd32f3x0_usart.h
  • USART_FLAG_LBD : gd32f3x0_usart.h
  • USART_FLAG_NERR : gd32f3x0_usart.h
  • USART_FLAG_ORERR : gd32f3x0_usart.h
  • USART_FLAG_PERR : gd32f3x0_usart.h
  • USART_FLAG_RBNE : gd32f3x0_usart.h
  • USART_FLAG_REA : gd32f3x0_usart.h
  • USART_FLAG_RFE : gd32f3x0_usart.h
  • USART_FLAG_RFF : gd32f3x0_usart.h
  • USART_FLAG_RFFINT : gd32f3x0_usart.h
  • USART_FLAG_RT : gd32f3x0_usart.h
  • USART_FLAG_RWU : gd32f3x0_usart.h
  • USART_FLAG_SB : gd32f3x0_usart.h
  • USART_FLAG_TBE : gd32f3x0_usart.h
  • USART_FLAG_TC : gd32f3x0_usart.h
  • USART_FLAG_TEA : gd32f3x0_usart.h
  • USART_FLAG_WU : gd32f3x0_usart.h
  • USART_GP : gd32f3x0_usart.h
  • USART_GP_GUAT : gd32f3x0_usart.h
  • USART_GP_PSC : gd32f3x0_usart.h
  • usart_guard_time_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_halfduplex_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_halfduplex_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_hardware_flow_cts_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_hardware_flow_rts_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_INT_AM : gd32f3x0_usart.h
  • USART_INT_CTS : gd32f3x0_usart.h
  • USART_INT_EB : gd32f3x0_usart.h
  • USART_INT_ERR : gd32f3x0_usart.h
  • USART_INT_FLAG_AM : gd32f3x0_usart.h
  • USART_INT_FLAG_CTS : gd32f3x0_usart.h
  • USART_INT_FLAG_EB : gd32f3x0_usart.h
  • USART_INT_FLAG_ERR_FERR : gd32f3x0_usart.h
  • USART_INT_FLAG_ERR_NERR : gd32f3x0_usart.h
  • USART_INT_FLAG_ERR_ORERR : gd32f3x0_usart.h
  • USART_INT_FLAG_IDLE : gd32f3x0_usart.h
  • USART_INT_FLAG_LBD : gd32f3x0_usart.h
  • USART_INT_FLAG_PERR : gd32f3x0_usart.h
  • USART_INT_FLAG_RBNE : gd32f3x0_usart.h
  • USART_INT_FLAG_RBNE_ORERR : gd32f3x0_usart.h
  • USART_INT_FLAG_RFF : gd32f3x0_usart.h
  • USART_INT_FLAG_RT : gd32f3x0_usart.h
  • USART_INT_FLAG_TBE : gd32f3x0_usart.h
  • USART_INT_FLAG_TC : gd32f3x0_usart.h
  • USART_INT_FLAG_WU : gd32f3x0_usart.h
  • USART_INT_IDLE : gd32f3x0_usart.h
  • USART_INT_LBD : gd32f3x0_usart.h
  • USART_INT_PERR : gd32f3x0_usart.h
  • USART_INT_RBNE : gd32f3x0_usart.h
  • USART_INT_RFF : gd32f3x0_usart.h
  • USART_INT_RT : gd32f3x0_usart.h
  • USART_INT_TBE : gd32f3x0_usart.h
  • USART_INT_TC : gd32f3x0_usart.h
  • USART_INT_WU : gd32f3x0_usart.h
  • USART_INTC : gd32f3x0_usart.h
  • USART_INTC_AMC : gd32f3x0_usart.h
  • USART_INTC_CTSC : gd32f3x0_usart.h
  • USART_INTC_EBC : gd32f3x0_usart.h
  • USART_INTC_FEC : gd32f3x0_usart.h
  • USART_INTC_IDLEC : gd32f3x0_usart.h
  • USART_INTC_LBDC : gd32f3x0_usart.h
  • USART_INTC_NEC : gd32f3x0_usart.h
  • USART_INTC_OREC : gd32f3x0_usart.h
  • USART_INTC_PEC : gd32f3x0_usart.h
  • USART_INTC_RTC : gd32f3x0_usart.h
  • USART_INTC_TCC : gd32f3x0_usart.h
  • USART_INTC_WUC : gd32f3x0_usart.h
  • usart_interrupt_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_interrupt_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_interrupt_enum : gd32f3x0_usart.h
  • usart_interrupt_flag_clear() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_interrupt_flag_enum : gd32f3x0_usart.h
  • usart_interrupt_flag_get() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_invert_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_invert_enum : gd32f3x0_usart.h
  • usart_irda_lowpower_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_irda_mode_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_irda_mode_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_IRLP_LOW : gd32f3x0_usart.h
  • USART_IRLP_NORMAL : gd32f3x0_usart.h
  • USART_LBLEN_10B : gd32f3x0_usart.h
  • USART_LBLEN_11B : gd32f3x0_usart.h
  • usart_lin_break_dection_length_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_lin_mode_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_lin_mode_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_MSBF_LSB : gd32f3x0_usart.h
  • USART_MSBF_MSB : gd32f3x0_usart.h
  • usart_mute_mode_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_mute_mode_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_mute_mode_wakeup_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_OSB_1BIT : gd32f3x0_usart.h
  • USART_OSB_3BIT : gd32f3x0_usart.h
  • usart_overrun_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_overrun_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_oversample_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_OVSMOD_16 : gd32f3x0_usart.h
  • USART_OVSMOD_8 : gd32f3x0_usart.h
  • usart_parity_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_PM_EVEN : gd32f3x0_usart.h
  • USART_PM_NONE : gd32f3x0_usart.h
  • USART_PM_ODD : gd32f3x0_usart.h
  • usart_prescaler_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_RDATA : gd32f3x0_usart.h
  • USART_RDATA_RDATA : gd32f3x0_usart.h
  • usart_receive_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_RECEIVE_DISABLE : gd32f3x0_usart.h
  • USART_RECEIVE_ENABLE : gd32f3x0_usart.h
  • usart_receive_fifo_counter_number() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_receive_fifo_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_receive_fifo_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_receiver_timeout_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_receiver_timeout_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_receiver_timeout_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_reception_error_dma_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_reception_error_dma_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_REG_VAL : gd32f3x0_usart.h
  • USART_REG_VAL2 : gd32f3x0_usart.h
  • USART_REGIDX_BIT : gd32f3x0_usart.h
  • USART_REGIDX_BIT2 : gd32f3x0_usart.h
  • USART_RFCS : gd32f3x0_usart.h
  • USART_RFCS_ELNACK : gd32f3x0_usart.h
  • USART_RFCS_REG_OFFSET : gd32f3x0_usart.h
  • USART_RFCS_RFCNT : gd32f3x0_usart.h
  • USART_RFCS_RFE : gd32f3x0_usart.h
  • USART_RFCS_RFEN : gd32f3x0_usart.h
  • USART_RFCS_RFF : gd32f3x0_usart.h
  • USART_RFCS_RFFIE : gd32f3x0_usart.h
  • USART_RFCS_RFFINT : gd32f3x0_usart.h
  • usart_rs485_driver_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_rs485_driver_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_RT : gd32f3x0_usart.h
  • USART_RT_BL : gd32f3x0_usart.h
  • USART_RT_RT : gd32f3x0_usart.h
  • USART_RTS_DISABLE : gd32f3x0_usart.h
  • USART_RTS_ENABLE : gd32f3x0_usart.h
  • USART_RXPIN_DISABLE : gd32f3x0_usart.h
  • USART_RXPIN_ENABLE : gd32f3x0_usart.h
  • usart_sample_bit_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_smartcard_autoretry_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_smartcard_mode_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_smartcard_mode_early_nack_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_smartcard_mode_early_nack_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_smartcard_mode_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_smartcard_mode_nack_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_smartcard_mode_nack_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_STAT : gd32f3x0_usart.h
  • USART_STAT_ABDE : gd32f3x0_usart.h
  • USART_STAT_ABDF : gd32f3x0_usart.h
  • USART_STAT_AMF : gd32f3x0_usart.h
  • USART_STAT_BSY : gd32f3x0_usart.h
  • USART_STAT_CTS : gd32f3x0_usart.h
  • USART_STAT_CTSF : gd32f3x0_usart.h
  • USART_STAT_EBF : gd32f3x0_usart.h
  • USART_STAT_FERR : gd32f3x0_usart.h
  • USART_STAT_IDLEF : gd32f3x0_usart.h
  • USART_STAT_LBDF : gd32f3x0_usart.h
  • USART_STAT_NERR : gd32f3x0_usart.h
  • USART_STAT_ORERR : gd32f3x0_usart.h
  • USART_STAT_PERR : gd32f3x0_usart.h
  • USART_STAT_RBNE : gd32f3x0_usart.h
  • USART_STAT_REA : gd32f3x0_usart.h
  • USART_STAT_REG_OFFSET : gd32f3x0_usart.h
  • USART_STAT_RTF : gd32f3x0_usart.h
  • USART_STAT_RWU : gd32f3x0_usart.h
  • USART_STAT_SBF : gd32f3x0_usart.h
  • USART_STAT_TBE : gd32f3x0_usart.h
  • USART_STAT_TC : gd32f3x0_usart.h
  • USART_STAT_TEA : gd32f3x0_usart.h
  • USART_STAT_WUF : gd32f3x0_usart.h
  • USART_STB_0_5BIT : gd32f3x0_usart.h
  • USART_STB_1_5BIT : gd32f3x0_usart.h
  • USART_STB_1BIT : gd32f3x0_usart.h
  • USART_STB_2BIT : gd32f3x0_usart.h
  • usart_stop_bit_set() : gd32f3x0_usart.c , gd32f3x0_usart.h
  • USART_SWAP_DISABLE : gd32f3x0_usart.h
  • USART_SWAP_ENABLE : gd32f3x0_usart.h
  • usart_synchronous_clock_config() : gd32f3x0_usart.c , gd32f3x0_usart.h
  • USART_TDATA : gd32f3x0_usart.h
  • USART_TDATA_TDATA : gd32f3x0_usart.h
  • usart_transmit_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_TRANSMIT_DISABLE : gd32f3x0_usart.h
  • USART_TRANSMIT_ENABLE : gd32f3x0_usart.h
  • USART_TXPIN_DISABLE : gd32f3x0_usart.h
  • USART_TXPIN_ENABLE : gd32f3x0_usart.h
  • usart_wakeup_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_wakeup_enable() : gd32f3x0_usart.c , gd32f3x0_usart.h
  • usart_wakeup_mode_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_WL_8BIT : gd32f3x0_usart.h
  • USART_WL_9BIT : gd32f3x0_usart.h
  • USART_WM_ADDR : gd32f3x0_usart.h
  • USART_WM_IDLE : gd32f3x0_usart.h
  • usart_word_length_set() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • USART_WUM_ADDR : gd32f3x0_usart.h
  • USART_WUM_RBNE : gd32f3x0_usart.h
  • USART_WUM_STARTB : gd32f3x0_usart.h
  • USB_CFG_DESC_LEN : usb_std.h
  • USB_CFGDESC : usb_std.h
  • USB_CFGDESC_SIZE : usb_std.h
  • USB_CID : usb_regs.h
  • USB_CLASS_REQ : usb_std.h
  • USB_CORE_EMBEDDED_PHY : usb_defines.h
  • usb_core_id_enum : usb_defines.h
  • usb_core_init() : usb_core.c , usb_core.h
  • USB_CORE_INTR_READ : usb_regs.h
  • usb_core_select() : usb_core.h , usb_core.c
  • USB_CORE_SPEED_FULL : usb_defines.h
  • USB_CORE_SPEED_HIGH : usb_defines.h
  • USB_CORE_ULPI_PHY : usb_defines.h
  • USB_CTRL_DATA_IN : usb_core.h
  • USB_CTRL_DATA_OUT : usb_core.h
  • USB_CTRL_IDLE : usb_core.h
  • USB_CTRL_SETUP : usb_core.h
  • USB_CTRL_STALL : usb_core.h
  • USB_CTRL_STATUS_IN : usb_core.h
  • USB_CTRL_STATUS_OUT : usb_core.h
  • USB_CURRENT_FRAME_GET : usb_regs.h
  • USB_CURRENT_MODE_GET : usb_regs.h
  • USB_CURRENT_SPEED_GET : usb_regs.h
  • USB_DAEPINT : usb_regs.h
  • USB_DAEPINTEN : usb_regs.h
  • USB_DAIEP_INTR_READ : usb_regs.h
  • USB_DAOEP_INTR_READ : usb_regs.h
  • USB_DCFG : usb_regs.h
  • USB_DCTL : usb_regs.h
  • USB_DEP1INT : usb_regs.h
  • USB_DEP1INTEN : usb_regs.h
  • USB_DESCTYPE_CONFIGURATION : usb_std.h
  • USB_DESCTYPE_DEVICE : usb_std.h
  • USB_DESCTYPE_DEVICE_QUALIFIER : usb_std.h
  • USB_DESCTYPE_ENDPOINT : usb_std.h
  • USB_DESCTYPE_HID : usb_std.h
  • USB_DESCTYPE_HID_REPORT : usb_std.h
  • USB_DESCTYPE_INTERFACE : usb_std.h
  • USB_DESCTYPE_INTERFACE_POWER : usb_std.h
  • USB_DESCTYPE_OTHER_SPEED_CONFIGURATION : usb_std.h
  • USB_DESCTYPE_STRING : usb_std.h
  • USB_DEV_DESC_LEN : usb_std.h
  • USB_DEV_QUALIFIER_DESC_LEN : usb_std.h
  • USB_DEVDESC : usb_std.h
  • USB_DEVDESC_SIZE : usb_std.h
  • USB_DEVICE_DESC_SIZE : usbd_std.h
  • USB_DEVQUADESC : usb_std.h
  • USB_DIEP0CTL : usb_regs.h
  • USB_DIEP0LEN : usb_regs.h
  • USB_DIEP0TFLEN : usb_regs.h
  • USB_DIEP1INTEN : usb_regs.h
  • USB_DIEP_INTR_READ : usb_regs.h
  • USB_DIEPFEINTEN : usb_regs.h
  • USB_DIEPINTEN : usb_regs.h
  • USB_DIEPxCTL : usb_regs.h
  • USB_DIEPxINTF : usb_regs.h
  • USB_DIEPxLEN : usb_regs.h
  • USB_DIEPxTFLEN : usb_regs.h
  • USB_DIEPxTFSTAT : usb_regs.h
  • usb_dir_enum : usb_core.h
  • USB_DIR_IN : usb_std.h
  • USB_DIR_MASK : usb_std.h
  • USB_DIR_OUT : usb_std.h
  • USB_DOEP0CTL : usb_regs.h
  • USB_DOEP0LEN : usb_regs.h
  • USB_DOEP1INTEN : usb_regs.h
  • USB_DOEP_INTR_READ : usb_regs.h
  • USB_DOEPINTEN : usb_regs.h
  • USB_DOEPxCTL : usb_regs.h
  • USB_DOEPxINTF : usb_regs.h
  • USB_DOEPxLEN : usb_regs.h
  • USB_DSTAT : usb_regs.h
  • USB_DVBUSDT : usb_regs.h
  • USB_DVBUSPT : usb_regs.h
  • USB_EP_DESC_LEN : usb_std.h
  • USB_EPDESC : usb_std.h
  • USB_EPDESC_SIZE : usb_std.h
  • USB_EPTYPE_BULK : usb_defines.h
  • USB_EPTYPE_CTRL : usb_defines.h
  • USB_EPTYPE_INTR : usb_defines.h
  • USB_EPTYPE_ISOC : usb_defines.h
  • USB_EPTYPE_MASK : usb_defines.h
  • USB_EVEN_FRAME : usb_regs.h
  • USB_FAIL : usb_core.h
  • USB_FEATURE_ENDP_HALT : usbd_std.h
  • USB_FEATURE_REMOTE_WAKEUP : usbd_std.h
  • USB_FEATURE_TEST_MODE : usbd_std.h
  • USB_FIFO : usb_regs.h
  • usb_fifo_read() : usb_core.c , usb_core.h
  • usb_fifo_write() : usb_core.h , usb_core.c
  • USB_FS_CORE_ID : usb_defines.h
  • USB_FSLSCLOCK_INIT : usb_regs.h
  • USB_GAHBCS : usb_regs.h
  • USB_GCCFG : usb_regs.h
  • USB_GINTEN : usb_regs.h
  • USB_GINTF : usb_regs.h
  • USB_GLOBAL_INT_DISABLE : usb_regs.h
  • USB_GLOBAL_INT_ENABLE : usb_regs.h
  • USB_GOTGCS : usb_regs.h
  • USB_GOTGINTF : usb_regs.h
  • USB_GRFLEN : usb_regs.h
  • USB_GRSTATP : usb_regs.h
  • USB_GRSTATR : usb_regs.h
  • USB_GRSTCTL : usb_regs.h
  • USB_GUSBCS : usb_regs.h
  • USB_HACHINT : usb_regs.h
  • USB_HACHINTEN : usb_regs.h
  • USB_HCHxCTL : usb_regs.h
  • USB_HCHxINTEN : usb_regs.h
  • USB_HCHxINTF : usb_regs.h
  • USB_HCHxLEN : usb_regs.h
  • USB_HCTL : usb_regs.h
  • USB_HFINFR : usb_regs.h
  • USB_HFT : usb_regs.h
  • USB_HID_CLASS : usb_std.h
  • USB_HIDDESC : usb_std.h
  • USB_HIDREPDESC : usb_std.h
  • USB_HNPTFLEN : usb_regs.h
  • USB_HNPTFQSTAT : usb_regs.h
  • USB_HPCS : usb_regs.h
  • USB_HPTFLEN : usb_regs.h
  • USB_HPTFQSTAT : usb_regs.h
  • USB_HS_CORE_ID : usb_defines.h
  • USB_IF_DESC_LEN : usb_std.h
  • USB_INTDESC : usb_std.h
  • USB_INTDESC_SIZE : usb_std.h
  • USB_INTPWRDESC : usb_std.h
  • USB_MAX_DEV_EPCOUNT : usb_core.h
  • USB_MAX_EP0_SIZE : usb_core.h
  • USB_MAX_FIFOS : usb_core.h
  • USB_MIN : usbd_std.h
  • usb_mode_set() : usb_core.h , usb_core.c
  • USB_MSC_CLASS : usb_std.h
  • USB_OK : usb_core.h
  • USB_OSPCFGDESC : usb_std.h
  • USB_OTG_DESC_LEN : usb_std.h
  • USB_PORT_READ : usb_regs.h
  • USB_PWRCLKCTL : usb_regs.h
  • USB_REMOTE_WAKEUP_RESET : usb_regs.h
  • USB_REMOTE_WAKEUP_SET : usb_regs.h
  • USB_REQ_MASK : usb_std.h
  • USB_REQTYPE_DEVICE : usb_std.h
  • USB_REQTYPE_ENDPOINT : usb_std.h
  • USB_REQTYPE_INTERFACE : usb_std.h
  • USB_REQTYPE_MASK : usb_std.h
  • USB_RX : usb_core.h
  • usb_rxfifo_flush() : usb_core.h , usb_core.c
  • USB_SET_DEVADDR : usb_regs.h
  • USB_SOFT_DISCONNECT_DISABLE : usb_regs.h
  • USB_SOFT_DISCONNECT_ENABLE : usb_regs.h
  • usb_speed_enum : usb_defines.h
  • USB_SPEED_EXP_FULL : usb_regs.h
  • USB_SPEED_EXP_HIGH : usb_regs.h
  • USB_SPEED_FULL : usb_defines.h
  • USB_SPEED_HIGH : usb_defines.h
  • USB_SPEED_INP_FULL : usb_regs.h
  • USB_SPEED_LOW : usb_defines.h
  • USB_SPEED_UNKNOWN : usb_defines.h
  • USB_STANDARD_REQ : usb_std.h
  • USB_STATUS_ADDRESSED : usbd_core.h
  • USB_STATUS_CONFIGURED : usbd_core.h
  • USB_STATUS_DEFAULT : usbd_core.h
  • usb_status_enum : usb_core.h
  • USB_STATUS_REMOTE_WAKEUP : usbd_std.h
  • USB_STATUS_SELF_POWERED : usbd_std.h
  • USB_STATUS_SUSPENDED : usbd_core.h
  • USB_STRDESC : usb_std.h
  • USB_TX : usb_core.h
  • usb_txfifo_flush() : usb_core.c , usb_core.h
  • USB_VENDOR_REQ : usb_std.h
  • USBD_BUSY : usb_core.h
  • USBD_CONFIG_STR_IDX : usbd_std.h
  • usbd_control_state_enum : usb_core.h
  • usbd_ctlrx() : usbd_core.c , usbd_core.h
  • usbd_ctlstatus_rx() : usbd_core.h , usbd_core.c
  • usbd_ctlstatus_tx() : usbd_core.h , usbd_core.c
  • usbd_ctltx() : usbd_core.h , usbd_core.c
  • usbd_enum_error() : usbd_std.c , usbd_std.h
  • usbd_ep_clear_stall() : usbd_core.h , usbd_core.c
  • usbd_ep_deinit() : usbd_core.c , usbd_core.h
  • usbd_ep_fifo_flush() : usbd_core.h , usbd_core.c
  • usbd_ep_init() : usbd_core.c , usbd_core.h
  • usbd_ep_rx() : usbd_core.h , usbd_core.c
  • usbd_ep_stall() : usbd_core.c , usbd_core.h
  • usbd_ep_tx() : usbd_core.c , usbd_core.h
  • USBD_FAIL : usb_core.h
  • usbd_in_transaction() : usbd_std.c , usbd_std.h
  • usbd_init() : usbd_core.h , usbd_core.c
  • usbd_int_fops : usbd_int.h
  • USBD_INTERFACE_STR_IDX : usbd_std.h
  • usbd_isr() : usbd_int.h , usbd_int.c
  • USBD_LANGID_STR_IDX : usbd_std.h
  • USBD_MFC_STR_IDX : usbd_std.h
  • USBD_OK : usb_core.h
  • usbd_out_transaction() : usbd_std.c , usbd_std.h
  • USBD_PRODUCT_STR_IDX : usbd_std.h
  • usbd_rxcount_get() : usbd_core.h , usbd_core.c
  • USBD_SERIAL_STR_IDX : usbd_std.h
  • usbd_setup_transaction() : usbd_std.c , usbd_std.h
  • usbd_status_enum : usb_core.h
  • USBD_STRING_DESC : usbd_std.h
  • USBFS : usb_regs.h
  • USBFS_MAX_DEV_EPCOUNT : usb_defines.h
  • USBFS_MAX_FIFO_WORDLEN : usb_defines.h
  • USBFS_MAX_HOST_CHANNELCOUNT : usb_defines.h
  • USBFS_MAX_PACKET_SIZE : usb_defines.h
  • usbh_allchannel_dealloc() : usbh_hcs.h , usbh_hcs.c
  • USBH_APPLY_DEINIT : usbh_core.h
  • USBH_BUSY : usbh_core.h
  • usbh_cfg_desc : usbh_std.h , usbh_std.c
  • usbh_cfg_desc_parse() : usbh_std.h , usbh_std.c
  • USBH_CFG_DESC_SET_SIZE : usb_std.h
  • usbh_channel_alloc() : usbh_hcs.c , usbh_hcs.h
  • usbh_channel_free() : usbh_hcs.c , usbh_hcs.h
  • usbh_channel_modify() : usbh_hcs.h , usbh_hcs.c
  • usbh_channel_open() : usbh_hcs.h , usbh_hcs.c
  • usbh_connected() : usbh_core.c
  • usbh_ctltx_setup() : usbh_ctrl.h , usbh_ctrl.c
  • usbh_deinit() : usbh_core.h , usbh_core.c
  • USBH_DEVICE_ADDRESS : usbh_core.h
  • USBH_DEVICE_ADDRESS_DEFAULT : usbh_core.h
  • usbh_device_desc_parse() : usbh_std.h , usbh_std.c
  • usbh_disconnected() : usbh_core.c
  • usbh_endpoint_desc_parse() : usbh_std.h , usbh_std.c
  • usbh_enum_addr_set() : usbh_std.h , usbh_std.c
  • usbh_enum_cfg_set() : usbh_std.c , usbh_std.h
  • usbh_enum_desc_get() : usbh_std.h , usbh_std.c
  • USBH_FAIL : usbh_core.h
  • usbh_hcd_int_cb : usbh_core.c
  • usbh_hcd_int_fops : usbh_int.h , usbh_core.c
  • usbh_interface_desc_parse() : usbh_std.c , usbh_std.h
  • usbh_isr() : usbh_int.h , usbh_int.c
  • USBH_MAX_ERROR_COUNT : usbh_core.h
  • usbh_next_desc_get() : usbh_std.c , usbh_std.h
  • USBH_NOT_SUPPORTED : usbh_core.h
  • USBH_OK : usbh_core.h
  • USBH_SETUP_PACKET_SIZE : usbh_std.h
  • usbh_sof() : usbh_core.c
  • USBH_SPEED_UNKNOWN_ERROR : usbh_core.h
  • usbh_state_core : usbh_core.c
  • usbh_status_enum : usbh_core.h
  • usbh_string_desc_parse() : usbh_std.h , usbh_std.c
  • USBH_UNRECOVERED_ERROR : usbh_core.h
  • USBH_USER_NO_RESP : usbh_core.h
  • USBH_USER_RESP_OK : usbh_core.h
  • usbh_user_status_enum : usbh_core.h
  • usbh_xfer() : usbh_ctrl.c , usbh_ctrl.h
  • USBHS_MAX_DEV_EPCOUNT : usb_defines.h
  • USBHS_MAX_FIFO_WORDLEN : usb_defines.h
  • USBHS_MAX_HOST_CHANNELCOUNT : usb_defines.h
  • USBHS_MAX_PACKET_SIZE : usb_defines.h
  • USBREQ_CLEAR_FEATURE : usb_std.h
  • USBREQ_GET_CONFIGURATION : usb_std.h
  • USBREQ_GET_DESCRIPTOR : usb_std.h
  • USBREQ_GET_INTERFACE : usb_std.h
  • USBREQ_GET_STATUS : usb_std.h
  • USBREQ_SET_ADDRESS : usb_std.h
  • USBREQ_SET_CONFIGURATION : usb_std.h
  • USBREQ_SET_DESCRIPTOR : usb_std.h
  • USBREQ_SET_FEATURE : usb_std.h
  • USBREQ_SET_INTERFACE : usb_std.h
  • USBREQ_SYNCH_FRAME : usb_std.h


GD32F3x0_Firmware_Library: Globals

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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • WDHT_WDHT : gd32f3x0_adc.h
  • WDLT_WDLT : gd32f3x0_adc.h
  • WFE_CMD : gd32f3x0_pmu.h
  • WFI_CMD : gd32f3x0_pmu.h
  • WIDE_STRING : usbd_std.h
  • WND_WND : gd32f3x0_fwdgt.h
  • WPK_WPK : gd32f3x0_rtc.h
  • WS_WSCNT_0 : gd32f3x0_fmc.h
  • WS_WSCNT_1 : gd32f3x0_fmc.h
  • WS_WSCNT_2 : gd32f3x0_fmc.h
  • WWDGT : gd32f3x0_wwdgt.h
  • WWDGT_CFG : gd32f3x0_wwdgt.h
  • WWDGT_CFG_EWIE : gd32f3x0_wwdgt.h
  • WWDGT_CFG_PSC : gd32f3x0_wwdgt.h
  • WWDGT_CFG_PSC_DIV1 : gd32f3x0_wwdgt.h
  • WWDGT_CFG_PSC_DIV2 : gd32f3x0_wwdgt.h
  • WWDGT_CFG_PSC_DIV4 : gd32f3x0_wwdgt.h
  • WWDGT_CFG_PSC_DIV8 : gd32f3x0_wwdgt.h
  • WWDGT_CFG_WIN : gd32f3x0_wwdgt.h
  • wwdgt_config() : gd32f3x0_wwdgt.h , gd32f3x0_wwdgt.c
  • wwdgt_counter_update() : gd32f3x0_wwdgt.c , gd32f3x0_wwdgt.h
  • WWDGT_CTL : gd32f3x0_wwdgt.h
  • WWDGT_CTL_CNT : gd32f3x0_wwdgt.h
  • WWDGT_CTL_WDGTEN : gd32f3x0_wwdgt.h
  • wwdgt_deinit() : gd32f3x0_wwdgt.h , gd32f3x0_wwdgt.c
  • wwdgt_enable() : gd32f3x0_wwdgt.h , gd32f3x0_wwdgt.c
  • wwdgt_flag_clear() : gd32f3x0_wwdgt.c , gd32f3x0_wwdgt.h
  • wwdgt_flag_get() : gd32f3x0_wwdgt.c , gd32f3x0_wwdgt.h
  • wwdgt_interrupt_enable() : gd32f3x0_wwdgt.c , gd32f3x0_wwdgt.h
  • WWDGT_STAT : gd32f3x0_wwdgt.h
  • WWDGT_STAT_EWIF : gd32f3x0_wwdgt.h


GD32F3x0_Firmware_Library: Globals

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- a -

  • adc_calibration_enable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_channel_length_config() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • adc_data_alignment_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_deinit() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • adc_disable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_discontinuous_mode_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_dma_mode_disable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_dma_mode_enable() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • adc_enable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_external_trigger_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_external_trigger_source_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_flag_clear() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_flag_get() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_inserted_channel_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_inserted_channel_offset_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_inserted_data_read() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • adc_interrupt_disable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_interrupt_enable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_interrupt_flag_clear() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_interrupt_flag_get() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_oversample_mode_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_oversample_mode_disable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_oversample_mode_enable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_regular_channel_config() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • adc_regular_data_read() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_resolution_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_software_trigger_enable() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • adc_special_function_config() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_tempsensor_vrefint_disable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_tempsensor_vrefint_enable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_vbat_disable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_vbat_enable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_watchdog_disable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_watchdog_group_channel_enable() : gd32f3x0_adc.c , gd32f3x0_adc.h
  • adc_watchdog_single_channel_enable() : gd32f3x0_adc.h , gd32f3x0_adc.c
  • adc_watchdog_threshold_config() : gd32f3x0_adc.c , gd32f3x0_adc.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
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  • Enumerations
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- c -

  • cmp_deinit() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_disable() : gd32f3x0_cmp.c , gd32f3x0_cmp.h
  • cmp_enable() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_lock_disable() : gd32f3x0_cmp.c , gd32f3x0_cmp.h
  • cmp_lock_enable() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_mode_init() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_output_init() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_output_level_get() : gd32f3x0_cmp.c , gd32f3x0_cmp.h
  • cmp_switch_disable() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_switch_enable() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_window_disable() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • cmp_window_enable() : gd32f3x0_cmp.h , gd32f3x0_cmp.c
  • crc_block_data_calculate() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_data_register_read() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_data_register_reset() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_deinit() : gd32f3x0_crc.c , gd32f3x0_crc.h
  • crc_free_data_register_read() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_free_data_register_write() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_init_data_register_write() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_input_data_reverse_config() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_polynomial_set() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_polynomial_size_set() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_reverse_output_data_disable() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_reverse_output_data_enable() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • crc_single_data_calculate() : gd32f3x0_crc.h , gd32f3x0_crc.c
  • ctc_clock_limit_value_config() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_counter_capture_value_read() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_counter_direction_read() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_counter_disable() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_counter_enable() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_counter_reload_value_config() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_counter_reload_value_read() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_deinit() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_flag_clear() : gd32f3x0_ctc.c , gd32f3x0_ctc.h
  • ctc_flag_get() : gd32f3x0_ctc.c , gd32f3x0_ctc.h
  • ctc_hardware_trim_mode_config() : gd32f3x0_ctc.c , gd32f3x0_ctc.h
  • ctc_interrupt_disable() : gd32f3x0_ctc.c , gd32f3x0_ctc.h
  • ctc_interrupt_enable() : gd32f3x0_ctc.c , gd32f3x0_ctc.h
  • ctc_interrupt_flag_clear() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_interrupt_flag_get() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_irc48m_trim_value_config() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_irc48m_trim_value_read() : gd32f3x0_ctc.h , gd32f3x0_ctc.c
  • ctc_refsource_polarity_config() : gd32f3x0_ctc.c , gd32f3x0_ctc.h
  • ctc_refsource_prescaler_config() : gd32f3x0_ctc.c , gd32f3x0_ctc.h
  • ctc_refsource_signal_select() : gd32f3x0_ctc.c , gd32f3x0_ctc.h
  • ctc_software_refsource_pulse_generate() : gd32f3x0_ctc.c , gd32f3x0_ctc.h
  • ctrl_state_polling_fun() : usbh_ctrl.c , usbh_ctrl.h


GD32F3x0_Firmware_Library: Globals

  • All
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  • Typedefs
  • Enumerations
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  • w

- d -

  • dbg_deinit() : gd32f3x0_dbg.h , gd32f3x0_dbg.c
  • dbg_id_get() : gd32f3x0_dbg.c , gd32f3x0_dbg.h
  • dbg_low_power_disable() : gd32f3x0_dbg.h , gd32f3x0_dbg.c
  • dbg_low_power_enable() : gd32f3x0_dbg.c , gd32f3x0_dbg.h
  • dbg_periph_disable() : gd32f3x0_dbg.h , gd32f3x0_dbg.c
  • dbg_periph_enable() : gd32f3x0_dbg.h , gd32f3x0_dbg.c
  • dma_channel_disable() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_channel_enable() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • dma_circulation_disable() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_circulation_enable() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_deinit() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_flag_clear() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_flag_get() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_init() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_interrupt_disable() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_interrupt_enable() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • dma_interrupt_flag_clear() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_interrupt_flag_get() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_memory_address_config() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_memory_increase_disable() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • dma_memory_increase_enable() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_memory_to_memory_disable() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_memory_to_memory_enable() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • dma_memory_width_config() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_periph_address_config() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_periph_increase_disable() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • dma_periph_increase_enable() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • dma_periph_width_config() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_priority_config() : gd32f3x0_dma.c , gd32f3x0_dma.h
  • dma_transfer_direction_config() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_transfer_number_config() : gd32f3x0_dma.h , gd32f3x0_dma.c
  • dma_transfer_number_get() : gd32f3x0_dma.h , gd32f3x0_dma.c


GD32F3x0_Firmware_Library: Globals

  • All
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  • w

- e -

  • enum_state_polling_fun() : usbh_std.h , usbh_std.c
  • exti_deinit() : gd32f3x0_exti.c , gd32f3x0_exti.h
  • exti_event_disable() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • exti_event_enable() : gd32f3x0_exti.c , gd32f3x0_exti.h
  • exti_flag_clear() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • exti_flag_get() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • exti_init() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • exti_interrupt_disable() : gd32f3x0_exti.c , gd32f3x0_exti.h
  • exti_interrupt_enable() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • exti_interrupt_flag_clear() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • exti_interrupt_flag_get() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • exti_software_interrupt_disable() : gd32f3x0_exti.h , gd32f3x0_exti.c
  • exti_software_interrupt_enable() : gd32f3x0_exti.c , gd32f3x0_exti.h


GD32F3x0_Firmware_Library: Globals

  • All
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  • u
  • w

- f -

  • fmc_flag_clear() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_flag_get() : gd32f3x0_fmc.c , gd32f3x0_fmc.h
  • fmc_halfword_program() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_interrupt_disable() : gd32f3x0_fmc.c , gd32f3x0_fmc.h
  • fmc_interrupt_enable() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_lock() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_mass_erase() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_page_erase() : gd32f3x0_fmc.c , gd32f3x0_fmc.h
  • fmc_ready_wait() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_state_get() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_unlock() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_wait_state_disable() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_wait_state_enable() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_word_program() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_word_reprogram() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • fmc_wscnt_set() : gd32f3x0_fmc.c , gd32f3x0_fmc.h
  • fwdgt_config() : gd32f3x0_fwdgt.h , gd32f3x0_fwdgt.c
  • fwdgt_counter_reload() : gd32f3x0_fwdgt.c , gd32f3x0_fwdgt.h
  • fwdgt_enable() : gd32f3x0_fwdgt.h , gd32f3x0_fwdgt.c
  • fwdgt_flag_get() : gd32f3x0_fwdgt.h , gd32f3x0_fwdgt.c
  • fwdgt_window_value_config() : gd32f3x0_fwdgt.c , gd32f3x0_fwdgt.h
  • fwdgt_write_disable() : gd32f3x0_fwdgt.c , gd32f3x0_fwdgt.h


GD32F3x0_Firmware_Library: Globals

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- g -

  • goto_up_state_fun() : usbh_core.h , usbh_core.c
  • gpio_af_set() : gd32f3x0_gpio.c , gd32f3x0_gpio.h
  • gpio_bit_reset() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_bit_set() : gd32f3x0_gpio.c , gd32f3x0_gpio.h
  • gpio_bit_toggle() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_bit_write() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_deinit() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_input_bit_get() : gd32f3x0_gpio.c , gd32f3x0_gpio.h
  • gpio_input_port_get() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_mode_set() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_output_bit_get() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_output_options_set() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_output_port_get() : gd32f3x0_gpio.c , gd32f3x0_gpio.h
  • gpio_pin_lock() : gd32f3x0_gpio.h , gd32f3x0_gpio.c
  • gpio_port_toggle() : gd32f3x0_gpio.c , gd32f3x0_gpio.h
  • gpio_port_write() : gd32f3x0_gpio.h , gd32f3x0_gpio.c


GD32F3x0_Firmware_Library: Globals

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- h -

  • hcd_init() : usbh_core.h , usbh_core.c
  • hcd_is_device_connected() : usbh_core.c , usbh_core.h
  • hcd_submit_request() : usbh_ctrl.h , usbh_ctrl.c
  • hcd_urb_state_get() : usbh_core.c , usbh_core.h
  • hcd_xfer_count_get() : usbh_core.c , usbh_core.h
  • host_state_polling_fun() : usbh_core.h , usbh_core.c


GD32F3x0_Firmware_Library: Globals

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- i -

  • i2c_ack_config() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_ackpos_config() : gd32f3x0_i2c.c , gd32f3x0_i2c.h
  • i2c_clock_config() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_data_receive() : gd32f3x0_i2c.c , gd32f3x0_i2c.h
  • i2c_data_transmit() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_deinit() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_disable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_dma_enable() : gd32f3x0_i2c.c , gd32f3x0_i2c.h
  • i2c_dma_last_transfer_enable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_dualaddr_enable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_enable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_flag_clear() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_flag_get() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_interrupt_disable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_interrupt_enable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_interrupt_flag_clear() : gd32f3x0_i2c.c , gd32f3x0_i2c.h
  • i2c_interrupt_flag_get() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_master_addressing() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_mode_addr_config() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_pec_enable() : gd32f3x0_i2c.c , gd32f3x0_i2c.h
  • i2c_pec_transfer_enable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_pec_value_get() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_slave_response_to_gcall_config() : gd32f3x0_i2c.c , gd32f3x0_i2c.h
  • i2c_smbus_arp_enable() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_smbus_issue_alert() : gd32f3x0_i2c.c , gd32f3x0_i2c.h
  • i2c_smbus_type_config() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_software_reset_config() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_start_on_bus() : gd32f3x0_i2c.c , gd32f3x0_i2c.h
  • i2c_stop_on_bus() : gd32f3x0_i2c.h , gd32f3x0_i2c.c
  • i2c_stretch_scl_low_config() : gd32f3x0_i2c.h , gd32f3x0_i2c.c


GD32F3x0_Firmware_Library: Globals

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- n -

  • nvic_irq_disable() : gd32f3x0_misc.h , gd32f3x0_misc.c
  • nvic_irq_enable() : gd32f3x0_misc.c , gd32f3x0_misc.h
  • nvic_priority_group_set() : gd32f3x0_misc.h , gd32f3x0_misc.c
  • nvic_vector_table_set() : gd32f3x0_misc.c , gd32f3x0_misc.h


GD32F3x0_Firmware_Library: Globals

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- o -

  • ob_data_get() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • ob_data_program() : gd32f3x0_fmc.c , gd32f3x0_fmc.h
  • ob_erase() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • ob_lock() : gd32f3x0_fmc.c , gd32f3x0_fmc.h
  • ob_obstat_plevel_get() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • ob_reset() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • ob_security_protection_config() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • ob_unlock() : gd32f3x0_fmc.c , gd32f3x0_fmc.h
  • ob_user_get() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • ob_user_write() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • ob_write_protection_enable() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • ob_write_protection_get() : gd32f3x0_fmc.h , gd32f3x0_fmc.c
  • only_state_move() : usbh_core.c , usbh_core.h


GD32F3x0_Firmware_Library: Globals

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- p -

  • pmu_backup_write_disable() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_backup_write_enable() : gd32f3x0_pmu.c , gd32f3x0_pmu.h
  • pmu_deinit() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_flag_clear() : gd32f3x0_pmu.c , gd32f3x0_pmu.h
  • pmu_flag_get() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_highdriver_mode_disable() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_highdriver_mode_enable() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_highdriver_switch_select() : gd32f3x0_pmu.c , gd32f3x0_pmu.h
  • pmu_ldo_output_select() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_lowdriver_mode_disable() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_lowdriver_mode_enable() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_lowpower_driver_config() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_lvd_disable() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_lvd_select() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_normalpower_driver_config() : gd32f3x0_pmu.c , gd32f3x0_pmu.h
  • pmu_to_deepsleepmode() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_to_sleepmode() : gd32f3x0_pmu.h , gd32f3x0_pmu.c
  • pmu_to_standbymode() : gd32f3x0_pmu.c , gd32f3x0_pmu.h
  • pmu_wakeup_pin_disable() : gd32f3x0_pmu.c , gd32f3x0_pmu.h
  • pmu_wakeup_pin_enable() : gd32f3x0_pmu.h , gd32f3x0_pmu.c


GD32F3x0_Firmware_Library: Globals

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- q -

  • qspi_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • qspi_enable() : gd32f3x0_spi.c , gd32f3x0_spi.h
  • qspi_io23_output_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • qspi_io23_output_enable() : gd32f3x0_spi.c , gd32f3x0_spi.h
  • qspi_read_enable() : gd32f3x0_spi.c , gd32f3x0_spi.h
  • qspi_write_enable() : gd32f3x0_spi.h , gd32f3x0_spi.c


GD32F3x0_Firmware_Library: Globals

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- r -

  • rcu_adc_clock_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_ahb_clock_config() : gd32f3x0_rcu.c , gd32f3x0_rcu.h
  • rcu_all_reset_flag_clear() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_apb1_clock_config() : gd32f3x0_rcu.c , gd32f3x0_rcu.h
  • rcu_apb2_clock_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_bkp_reset_disable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_bkp_reset_enable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_cec_clock_config() : gd32f3x0_rcu.c , gd32f3x0_rcu.h
  • rcu_ckout_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_clock_freq_get() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_deepsleep_voltage_set() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_deinit() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_flag_get() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_hxtal_clock_monitor_disable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_hxtal_clock_monitor_enable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_hxtal_prediv_config() : gd32f3x0_rcu.c , gd32f3x0_rcu.h
  • rcu_interrupt_disable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_interrupt_enable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_interrupt_flag_clear() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_interrupt_flag_get() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_irc28m_adjust_value_set() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_irc8m_adjust_value_set() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_lxtal_drive_capability_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_osci_bypass_mode_disable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_osci_bypass_mode_enable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_osci_off() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_osci_on() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_osci_stab_wait() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_periph_clock_disable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_periph_clock_enable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_periph_clock_sleep_disable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_periph_clock_sleep_enable() : gd32f3x0_rcu.c , gd32f3x0_rcu.h
  • rcu_periph_reset_disable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_periph_reset_enable() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_pll_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_pll_preselection_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_rtc_clock_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_system_clock_source_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_system_clock_source_get() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_usart_clock_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_usbfs_clock_config() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rcu_voltage_key_unlock() : gd32f3x0_rcu.h , gd32f3x0_rcu.c
  • rtc_alarm_config() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_alarm_disable() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_alarm_enable() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_alarm_get() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_alarm_subsecond_config() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_alarm_subsecond_get() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_alter_output_config() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_bypass_shadow_disable() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_bypass_shadow_enable() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_calibration_config() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_current_time_get() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_deinit() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_flag_clear() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_flag_get() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_hour_adjust() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_init() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_init_mode_enter() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_init_mode_exit() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_interrupt_disable() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_interrupt_enable() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_refclock_detection_disable() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_refclock_detection_enable() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_register_sync_wait() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_second_ajust() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_subsecond_get() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_tamper_disable() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_tamper_enable() : gd32f3x0_rtc.c , gd32f3x0_rtc.h
  • rtc_timestamp_disable() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_timestamp_enable() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_timestamp_get() : gd32f3x0_rtc.h , gd32f3x0_rtc.c
  • rtc_timestamp_subsecond_get() : gd32f3x0_rtc.c , gd32f3x0_rtc.h


GD32F3x0_Firmware_Library: Globals

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- s -

  • scd_begin() : usbh_core.h , usbh_core.c
  • scd_event_handle() : usbh_core.c , usbh_core.h
  • scd_init() : usbh_core.h , usbh_core.c
  • scd_state_move() : usbh_core.c , usbh_core.h
  • scd_table_pop() : usbh_core.h , usbh_core.c
  • scd_table_push() : usbh_core.h , usbh_core.c
  • scd_table_regist() : usbh_core.h , usbh_core.c
  • spi_bidirectional_transfer_config() : gd32f3x0_spi.c , gd32f3x0_spi.h
  • spi_crc_error_clear() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_crc_get() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_crc_next() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_crc_off() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_crc_on() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_crc_polynomial_get() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_crc_polynomial_set() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_disable() : gd32f3x0_spi.c , gd32f3x0_spi.h
  • spi_dma_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_dma_enable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_enable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_i2s_data_frame_format_config() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_i2s_data_receive() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_i2s_data_transmit() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_i2s_deinit() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_i2s_flag_get() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_i2s_interrupt_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_i2s_interrupt_enable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_i2s_interrupt_flag_get() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_init() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_nss_internal_high() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_nss_internal_low() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_nss_output_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_nss_output_enable() : gd32f3x0_spi.c , gd32f3x0_spi.h
  • spi_nssp_mode_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_nssp_mode_enable() : gd32f3x0_spi.c , gd32f3x0_spi.h
  • spi_ti_mode_disable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • spi_ti_mode_enable() : gd32f3x0_spi.h , gd32f3x0_spi.c
  • syscfg_compensation_config() : gd32f3x0_syscfg.c , gd32f3x0_syscfg.h
  • syscfg_cps_rdy_flag_get() : gd32f3x0_syscfg.c , gd32f3x0_syscfg.h
  • syscfg_deinit() : gd32f3x0_syscfg.c , gd32f3x0_syscfg.h
  • syscfg_dma_remap_disable() : gd32f3x0_syscfg.c , gd32f3x0_syscfg.h
  • syscfg_dma_remap_enable() : gd32f3x0_syscfg.h , gd32f3x0_syscfg.c
  • syscfg_exti_line_config() : gd32f3x0_syscfg.c , gd32f3x0_syscfg.h
  • syscfg_flag_clear() : gd32f3x0_syscfg.h , gd32f3x0_syscfg.c
  • syscfg_flag_get() : gd32f3x0_syscfg.h , gd32f3x0_syscfg.c
  • syscfg_high_current_disable() : gd32f3x0_syscfg.h , gd32f3x0_syscfg.c
  • syscfg_high_current_enable() : gd32f3x0_syscfg.h , gd32f3x0_syscfg.c
  • syscfg_lock_config() : gd32f3x0_syscfg.c , gd32f3x0_syscfg.h
  • system_lowpower_reset() : gd32f3x0_misc.h , gd32f3x0_misc.c
  • system_lowpower_set() : gd32f3x0_misc.c , gd32f3x0_misc.h
  • SystemCoreClockUpdate() : system_gd32f3x0.c
  • SystemInit() : system_gd32f3x0.c
  • systick_clksource_set() : gd32f3x0_misc.c , gd32f3x0_misc.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
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  • c
  • d
  • e
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  • n
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  • s
  • t
  • u
  • w

- t -

  • timer_auto_reload_shadow_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_auto_reload_shadow_enable() : gd32f3x0_timer.c , gd32f3x0_timer.h
  • timer_automatic_output_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_automatic_output_enable() : gd32f3x0_timer.c , gd32f3x0_timer.h
  • timer_autoreload_value_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_break_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_break_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_break_enable() : gd32f3x0_timer.c , gd32f3x0_timer.h
  • timer_channel_capture_value_register_read() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_complementary_output_polarity_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_complementary_output_state_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_control_shadow_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_control_shadow_update_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_dma_request_source_select() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_input_capture_prescaler_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_clear_config() : gd32f3x0_timer.c , gd32f3x0_timer.h
  • timer_channel_output_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_fast_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_mode_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_polarity_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_pulse_value_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_shadow_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_output_state_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_channel_remap_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_counter_alignment() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_counter_down_direction() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_counter_read() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_counter_up_direction() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_counter_value_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_deinit() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_dma_disable() : gd32f3x0_timer.c , gd32f3x0_timer.h
  • timer_dma_enable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_dma_transfer_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_enable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_event_software_generate() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_external_clock_mode0_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_external_clock_mode1_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_external_clock_mode1_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_external_trigger_as_external_clock_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_external_trigger_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_flag_clear() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_flag_get() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_hall_mode_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_init() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_input_capture_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_input_pwm_capture_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_input_trigger_source_select() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_internal_clock_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_internal_trigger_as_external_clock_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_interrupt_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_interrupt_enable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_interrupt_flag_clear() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_interrupt_flag_get() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_master_output_trigger_source_select() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_master_slave_mode_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_ocpre_clear_source_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_output_value_selection_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_prescaler_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_prescaler_read() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_primary_output_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_quadrature_decoder_mode_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_repetition_value_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_single_pulse_mode_config() : gd32f3x0_timer.c , gd32f3x0_timer.h
  • timer_slave_mode_select() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_update_event_disable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_update_event_enable() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • timer_update_source_config() : gd32f3x0_timer.c , gd32f3x0_timer.h
  • timer_write_cc_register_config() : gd32f3x0_timer.h , gd32f3x0_timer.c
  • tsi_analog_off() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_analog_on() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_channel_pin_disable() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_channel_pin_enable() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_deinit() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_disable() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_enable() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_extend_charge_config() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_flag_clear() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_flag_get() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_group0_cycle_get() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_group1_cycle_get() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_group2_cycle_get() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_group3_cycle_get() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_group4_cycle_get() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_group5_cycle_get() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_group_disable() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_group_enable() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_group_status_get() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_hardware_mode_config() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_hysteresis_off() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_hysteresis_on() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_init() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_interrupt_disable() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_interrupt_enable() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_interrupt_flag_clear() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_interrupt_flag_get() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_max_number_config() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_pin_mode_config() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_plus_config() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_sample_pin_disable() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_sample_pin_enable() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_sofeware_mode_config() : gd32f3x0_tsi.c , gd32f3x0_tsi.h
  • tsi_software_start() : gd32f3x0_tsi.h , gd32f3x0_tsi.c
  • tsi_software_stop() : gd32f3x0_tsi.c , gd32f3x0_tsi.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • a
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • n
  • o
  • p
  • q
  • r
  • s
  • t
  • u
  • w

- u -

  • usart_address_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_address_detection_mode_config() : gd32f3x0_usart.c , gd32f3x0_usart.h
  • usart_autobaud_detection_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_autobaud_detection_enable() : gd32f3x0_usart.c , gd32f3x0_usart.h
  • usart_autobaud_detection_mode_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_baudrate_set() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_block_length_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_clock_disable() : gd32f3x0_usart.c , gd32f3x0_usart.h
  • usart_clock_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_command_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_data_first_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_data_receive() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_data_transmit() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_deinit() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_depolarity_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_disable() : gd32f3x0_usart.c , gd32f3x0_usart.h
  • usart_dma_receive_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_dma_transmit_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_driver_assertime_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_driver_deassertime_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_flag_clear() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_flag_get() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_guard_time_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_halfduplex_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_halfduplex_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_hardware_flow_cts_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_hardware_flow_rts_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_interrupt_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_interrupt_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_interrupt_flag_clear() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_interrupt_flag_get() : gd32f3x0_usart.c , gd32f3x0_usart.h
  • usart_invert_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_irda_lowpower_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_irda_mode_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_irda_mode_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_lin_break_dection_length_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_lin_mode_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_lin_mode_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_mute_mode_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_mute_mode_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_mute_mode_wakeup_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_overrun_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_overrun_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_oversample_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_parity_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_prescaler_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_receive_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_receive_fifo_counter_number() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_receive_fifo_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_receive_fifo_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_receiver_timeout_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_receiver_timeout_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_receiver_timeout_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_reception_error_dma_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_reception_error_dma_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_rs485_driver_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_rs485_driver_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_sample_bit_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_smartcard_autoretry_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_smartcard_mode_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_smartcard_mode_early_nack_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_smartcard_mode_early_nack_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_smartcard_mode_enable() : gd32f3x0_usart.c , gd32f3x0_usart.h
  • usart_smartcard_mode_nack_disable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_smartcard_mode_nack_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_stop_bit_set() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_synchronous_clock_config() : gd32f3x0_usart.c , gd32f3x0_usart.h
  • usart_transmit_config() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_wakeup_disable() : gd32f3x0_usart.c , gd32f3x0_usart.h
  • usart_wakeup_enable() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usart_wakeup_mode_config() : gd32f3x0_usart.c , gd32f3x0_usart.h
  • usart_word_length_set() : gd32f3x0_usart.h , gd32f3x0_usart.c
  • usb_core_init() : usb_core.h , usb_core.c
  • usb_core_select() : usb_core.h , usb_core.c
  • usb_fifo_read() : usb_core.c , usb_core.h
  • usb_fifo_write() : usb_core.h , usb_core.c
  • usb_mode_set() : usb_core.c , usb_core.h
  • usb_rxfifo_flush() : usb_core.h , usb_core.c
  • usb_txfifo_flush() : usb_core.h , usb_core.c
  • usbd_ctlrx() : usbd_core.h , usbd_core.c
  • usbd_ctlstatus_rx() : usbd_core.c , usbd_core.h
  • usbd_ctlstatus_tx() : usbd_core.h , usbd_core.c
  • usbd_ctltx() : usbd_core.c , usbd_core.h
  • usbd_enum_error() : usbd_std.h , usbd_std.c
  • usbd_ep_clear_stall() : usbd_core.h , usbd_core.c
  • usbd_ep_deinit() : usbd_core.c , usbd_core.h
  • usbd_ep_fifo_flush() : usbd_core.c , usbd_core.h
  • usbd_ep_init() : usbd_core.c , usbd_core.h
  • usbd_ep_rx() : usbd_core.c , usbd_core.h
  • usbd_ep_stall() : usbd_core.h , usbd_core.c
  • usbd_ep_tx() : usbd_core.c , usbd_core.h
  • usbd_in_transaction() : usbd_std.c , usbd_std.h
  • usbd_init() : usbd_core.c , usbd_core.h
  • usbd_isr() : usbd_int.h , usbd_int.c
  • usbd_out_transaction() : usbd_std.h , usbd_std.c
  • usbd_rxcount_get() : usbd_core.c , usbd_core.h
  • usbd_setup_transaction() : usbd_std.c , usbd_std.h
  • usbh_allchannel_dealloc() : usbh_hcs.h , usbh_hcs.c
  • usbh_cfg_desc_parse() : usbh_std.c , usbh_std.h
  • usbh_channel_alloc() : usbh_hcs.c , usbh_hcs.h
  • usbh_channel_free() : usbh_hcs.c , usbh_hcs.h
  • usbh_channel_modify() : usbh_hcs.c , usbh_hcs.h
  • usbh_channel_open() : usbh_hcs.c , usbh_hcs.h
  • usbh_connected() : usbh_core.c
  • usbh_ctltx_setup() : usbh_ctrl.c , usbh_ctrl.h
  • usbh_deinit() : usbh_core.h , usbh_core.c
  • usbh_device_desc_parse() : usbh_std.c , usbh_std.h
  • usbh_disconnected() : usbh_core.c
  • usbh_endpoint_desc_parse() : usbh_std.h , usbh_std.c
  • usbh_enum_addr_set() : usbh_std.h , usbh_std.c
  • usbh_enum_cfg_set() : usbh_std.c , usbh_std.h
  • usbh_enum_desc_get() : usbh_std.c , usbh_std.h
  • usbh_interface_desc_parse() : usbh_std.h , usbh_std.c
  • usbh_isr() : usbh_int.h , usbh_int.c
  • usbh_next_desc_get() : usbh_std.c , usbh_std.h
  • usbh_sof() : usbh_core.c
  • usbh_string_desc_parse() : usbh_std.h , usbh_std.c
  • usbh_xfer() : usbh_ctrl.c , usbh_ctrl.h


GD32F3x0_Firmware_Library: Globals

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- w -

  • wwdgt_config() : gd32f3x0_wwdgt.h , gd32f3x0_wwdgt.c
  • wwdgt_counter_update() : gd32f3x0_wwdgt.c , gd32f3x0_wwdgt.h
  • wwdgt_deinit() : gd32f3x0_wwdgt.h , gd32f3x0_wwdgt.c
  • wwdgt_enable() : gd32f3x0_wwdgt.c , gd32f3x0_wwdgt.h
  • wwdgt_flag_clear() : gd32f3x0_wwdgt.h , gd32f3x0_wwdgt.c
  • wwdgt_flag_get() : gd32f3x0_wwdgt.h , gd32f3x0_wwdgt.c
  • wwdgt_interrupt_enable() : gd32f3x0_wwdgt.c , gd32f3x0_wwdgt.h


GD32F3x0_Firmware_Library: Globals

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  • class_polling_cb : usbh_core.c
  • ctrl_data_wait_flag : usbh_ctrl.c
  • ctrl_handle_table : usbh_ctrl.h , usbh_ctrl.c
  • ctrl_polling_handle_flag : usbh_ctrl.h , usbh_ctrl.c
  • ctrl_setup_wait_flag : usbh_ctrl.c
  • ctrl_state_handle : usbh_ctrl.c
  • ctrl_status_wait_flag : usbh_ctrl.c
  • enum_handle_table : usbh_std.h , usbh_std.c
  • enum_polling_handle_flag : usbh_std.h , usbh_std.c
  • enum_state_handle : usbh_std.c
  • host_handle_table : usbh_core.c
  • host_state_handle : usbh_core.c
  • local_buffer : usbh_std.c
  • SystemCoreClock : system_gd32f3x0.c
  • usbd_int_fops : usbd_int.h
  • usbh_cfg_desc : usbh_std.h , usbh_std.c
  • usbh_hcd_int_cb : usbh_core.c
  • usbh_hcd_int_fops : usbh_int.h , usbh_core.c
  • usbh_state_core : usbh_core.c


GD32F3x0_Firmware_Library: Globals

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  • ACT_FUN : usbh_core.h
  • bit_status : gd32f3x0_gpio.h


GD32F3x0_Firmware_Library: Globals

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- c -

  • cmp_hysteresis_enum : gd32f3x0_cmp.h
  • cmp_output_enum : gd32f3x0_cmp.h
  • ctrl_event_enum : usbh_ctrl.h
  • ctrl_state_enum : usbh_core.h

- d -

  • dbg_periph_enum : gd32f3x0_dbg.h
  • dbg_reg_idx : gd32f3x0_dbg.h
  • dma_channel_enum : gd32f3x0_dma.h

- e -

  • enum_event_enum : usbh_std.h
  • enum_state_enum : usbh_core.h
  • exti_line_enum : gd32f3x0_exti.h
  • exti_mode_enum : gd32f3x0_exti.h
  • exti_trig_type_enum : gd32f3x0_exti.h

- f -

  • fmc_state_enum : gd32f3x0_fmc.h

- h -

  • hc_status_enum : usb_core.h
  • host_event_enum : usbh_core.h
  • host_state_enum : usbh_core.h

- i -

  • inverting_input_enum : gd32f3x0_cmp.h

- o -

  • operating_mode_enum : gd32f3x0_cmp.h

- r -

  • rcu_adc_clock_enum : gd32f3x0_rcu.h
  • rcu_clock_freq_enum : gd32f3x0_rcu.h
  • rcu_flag_enum : gd32f3x0_rcu.h
  • rcu_int_enum : gd32f3x0_rcu.h
  • rcu_int_flag_clear_enum : gd32f3x0_rcu.h
  • rcu_int_flag_enum : gd32f3x0_rcu.h
  • rcu_osci_type_enum : gd32f3x0_rcu.h
  • rcu_periph_enum : gd32f3x0_rcu.h
  • rcu_periph_reset_enum : gd32f3x0_rcu.h
  • rcu_periph_sleep_enum : gd32f3x0_rcu.h
  • reg_idx : gd32f3x0_rcu.h

- u -

  • urb_state_enum : usb_core.h
  • usart_flag_enum : gd32f3x0_usart.h
  • usart_interrupt_enum : gd32f3x0_usart.h
  • usart_interrupt_flag_enum : gd32f3x0_usart.h
  • usart_invert_enum : gd32f3x0_usart.h
  • usb_core_id_enum : usb_defines.h
  • usb_dir_enum : usb_core.h
  • usb_speed_enum : usb_defines.h
  • usb_status_enum : usb_core.h
  • usbd_control_state_enum : usb_core.h
  • usbd_status_enum : usb_core.h
  • usbh_status_enum : usbh_core.h
  • usbh_user_status_enum : usbh_core.h


GD32F3x0_Firmware_Library: Globals

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- c -

  • CK_ADC : gd32f3x0_rcu.h
  • CK_AHB : gd32f3x0_rcu.h
  • CK_APB1 : gd32f3x0_rcu.h
  • CK_APB2 : gd32f3x0_rcu.h
  • CK_CEC : gd32f3x0_rcu.h
  • CK_SYS : gd32f3x0_rcu.h
  • CK_USART : gd32f3x0_rcu.h
  • CMP_1_2VREFINT : gd32f3x0_cmp.h
  • CMP_1_4VREFINT : gd32f3x0_cmp.h
  • CMP_3_4VREFINT : gd32f3x0_cmp.h
  • CMP_DAC : gd32f3x0_cmp.h
  • CMP_HIGHSPEED : gd32f3x0_cmp.h
  • CMP_HYSTERESIS_HIGH : gd32f3x0_cmp.h
  • CMP_HYSTERESIS_LOW : gd32f3x0_cmp.h
  • CMP_HYSTERESIS_MIDDLE : gd32f3x0_cmp.h
  • CMP_HYSTERESIS_NO : gd32f3x0_cmp.h
  • CMP_LOWSPEED : gd32f3x0_cmp.h
  • CMP_MIDDLESPEED : gd32f3x0_cmp.h
  • CMP_OUTPUT_NONE : gd32f3x0_cmp.h
  • CMP_OUTPUT_TIMER0BKIN : gd32f3x0_cmp.h
  • CMP_OUTPUT_TIMER0IC0 : gd32f3x0_cmp.h
  • CMP_OUTPUT_TIMER0OCPRECLR : gd32f3x0_cmp.h
  • CMP_OUTPUT_TIMER1IC3 : gd32f3x0_cmp.h
  • CMP_OUTPUT_TIMER1OCPRECLR : gd32f3x0_cmp.h
  • CMP_OUTPUT_TIMER2IC0 : gd32f3x0_cmp.h
  • CMP_OUTPUT_TIMER2OCPRECLR : gd32f3x0_cmp.h
  • CMP_PA5 : gd32f3x0_cmp.h
  • CMP_PA_0_2 : gd32f3x0_cmp.h
  • CMP_VERYLOWSPEED : gd32f3x0_cmp.h
  • CMP_VREFINT : gd32f3x0_cmp.h
  • CTRL_COMPLETE : usbh_core.h
  • CTRL_DATA : usbh_core.h
  • CTRL_ERROR : usbh_core.h
  • CTRL_EVENT_COMPLETE : usbh_ctrl.h
  • CTRL_EVENT_DATA : usbh_ctrl.h
  • CTRL_EVENT_ERROR : usbh_ctrl.h
  • CTRL_EVENT_IDLE : usbh_ctrl.h
  • CTRL_EVENT_SETUP : usbh_ctrl.h
  • CTRL_EVENT_STALLED : usbh_ctrl.h
  • CTRL_EVENT_STATUS : usbh_ctrl.h
  • CTRL_IDLE : usbh_core.h
  • CTRL_SETUP : usbh_core.h
  • CTRL_STALLED : usbh_core.h
  • CTRL_STATUS : usbh_core.h


GD32F3x0_Firmware_Library: Globals

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- d -

  • DBG_FWDGT_HOLD : gd32f3x0_dbg.h
  • DBG_I2C0_HOLD : gd32f3x0_dbg.h
  • DBG_I2C1_HOLD : gd32f3x0_dbg.h
  • DBG_I2C2_HOLD : gd32f3x0_dbg.h
  • DBG_IDX_CTL0 : gd32f3x0_dbg.h
  • DBG_IDX_CTL1 : gd32f3x0_dbg.h
  • DBG_RTC_HOLD : gd32f3x0_dbg.h
  • DBG_TIMER0_HOLD : gd32f3x0_dbg.h
  • DBG_TIMER13_HOLD : gd32f3x0_dbg.h
  • DBG_TIMER14_HOLD : gd32f3x0_dbg.h
  • DBG_TIMER15_HOLD : gd32f3x0_dbg.h
  • DBG_TIMER16_HOLD : gd32f3x0_dbg.h
  • DBG_TIMER1_HOLD : gd32f3x0_dbg.h
  • DBG_TIMER2_HOLD : gd32f3x0_dbg.h
  • DBG_WWDGT_HOLD : gd32f3x0_dbg.h
  • DMA_CH0 : gd32f3x0_dma.h
  • DMA_CH1 : gd32f3x0_dma.h
  • DMA_CH2 : gd32f3x0_dma.h
  • DMA_CH3 : gd32f3x0_dma.h
  • DMA_CH4 : gd32f3x0_dma.h
  • DMA_CH5 : gd32f3x0_dma.h
  • DMA_CH6 : gd32f3x0_dma.h


GD32F3x0_Firmware_Library: Globals

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- e -

  • ENUM_DEV_CONFIGURED : usbh_core.h
  • ENUM_EVENT_SET_ADDR : usbh_std.h
  • ENUM_GET_CFG_DESC : usbh_core.h
  • ENUM_GET_FULL_CFG_DESC : usbh_core.h
  • ENUM_GET_FULL_DEV_DESC : usbh_core.h
  • ENUM_GET_MFC_STRING_DESC : usbh_core.h
  • ENUM_GET_PRODUCT_STRING_DESC : usbh_core.h
  • ENUM_GET_SERIALNUM_STRING_DESC : usbh_core.h
  • ENUM_IDLE : usbh_core.h
  • ENUM_SET_ADDR : usbh_core.h
  • ENUM_SET_CONFIGURATION : usbh_core.h
  • ENUN_EVENT_DEV_CONFIGURED : usbh_std.h
  • ENUN_EVENT_GET_CFG_DESC : usbh_std.h
  • ENUN_EVENT_GET_FULL_CFG_DESC : usbh_std.h
  • ENUN_EVENT_GET_FULL_DEV_DESC : usbh_std.h
  • ENUN_EVENT_GET_MFC_STRING_DESC : usbh_std.h
  • ENUN_EVENT_GET_PRODUCT_STRING_DESC : usbh_std.h
  • ENUN_EVENT_GET_SERIALNUM_STRING_DESC : usbh_std.h
  • ENUN_EVENT_IDLE : usbh_std.h
  • ENUN_EVENT_SET_CONFIGURATION : usbh_std.h
  • EXTI_0 : gd32f3x0_exti.h
  • EXTI_1 : gd32f3x0_exti.h
  • EXTI_10 : gd32f3x0_exti.h
  • EXTI_11 : gd32f3x0_exti.h
  • EXTI_12 : gd32f3x0_exti.h
  • EXTI_13 : gd32f3x0_exti.h
  • EXTI_14 : gd32f3x0_exti.h
  • EXTI_15 : gd32f3x0_exti.h
  • EXTI_16 : gd32f3x0_exti.h
  • EXTI_17 : gd32f3x0_exti.h
  • EXTI_18 : gd32f3x0_exti.h
  • EXTI_19 : gd32f3x0_exti.h
  • EXTI_2 : gd32f3x0_exti.h
  • EXTI_20 : gd32f3x0_exti.h
  • EXTI_21 : gd32f3x0_exti.h
  • EXTI_22 : gd32f3x0_exti.h
  • EXTI_23 : gd32f3x0_exti.h
  • EXTI_24 : gd32f3x0_exti.h
  • EXTI_25 : gd32f3x0_exti.h
  • EXTI_26 : gd32f3x0_exti.h
  • EXTI_27 : gd32f3x0_exti.h
  • EXTI_3 : gd32f3x0_exti.h
  • EXTI_4 : gd32f3x0_exti.h
  • EXTI_5 : gd32f3x0_exti.h
  • EXTI_6 : gd32f3x0_exti.h
  • EXTI_7 : gd32f3x0_exti.h
  • EXTI_8 : gd32f3x0_exti.h
  • EXTI_9 : gd32f3x0_exti.h
  • EXTI_EVENT : gd32f3x0_exti.h
  • EXTI_INTERRUPT : gd32f3x0_exti.h
  • EXTI_TRIG_BOTH : gd32f3x0_exti.h
  • EXTI_TRIG_FALLING : gd32f3x0_exti.h
  • EXTI_TRIG_RISING : gd32f3x0_exti.h


GD32F3x0_Firmware_Library: Globals

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- f -

  • FMC_BUSY : gd32f3x0_fmc.h
  • FMC_OB_HSPC : gd32f3x0_fmc.h
  • FMC_PGERR : gd32f3x0_fmc.h
  • FMC_READY : gd32f3x0_fmc.h
  • FMC_TOERR : gd32f3x0_fmc.h
  • FMC_WPERR : gd32f3x0_fmc.h


GD32F3x0_Firmware_Library: Globals

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- h -

  • HC_BBERR : usb_core.h
  • HC_DTGERR : usb_core.h
  • HC_HALTED : usb_core.h
  • HC_IDLE : usb_core.h
  • HC_NAK : usb_core.h
  • HC_NYET : usb_core.h
  • HC_STALL : usb_core.h
  • HC_TRACERR : usb_core.h
  • HC_XF : usb_core.h
  • HOST_CLASS : usbh_core.h
  • HOST_CLASS_REQUEST : usbh_core.h
  • HOST_DETECT_DEV_SPEED : usbh_core.h
  • HOST_DEV_ATTACHED : usbh_core.h
  • HOST_DEV_DETACHED : usbh_core.h
  • HOST_ENUMERATION : usbh_core.h
  • HOST_ERROR : usbh_core.h
  • HOST_EVENT_ATTACHED : usbh_core.h
  • HOST_EVENT_CLASS : usbh_core.h
  • HOST_EVENT_CLASS_REQ : usbh_core.h
  • HOST_EVENT_DEV_DETACHED : usbh_core.h
  • HOST_EVENT_ENUM : usbh_core.h
  • HOST_EVENT_ERROR : usbh_core.h
  • HOST_EVENT_IDLE : usbh_core.h
  • HOST_EVENT_USER_INPUT : usbh_core.h
  • HOST_IDLE : usbh_core.h
  • HOST_SUSPENDED : usbh_core.h
  • HOST_USER_INPUT : usbh_core.h


GD32F3x0_Firmware_Library: Globals

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- i -

  • IDX_ADDAPB1EN : gd32f3x0_rcu.h
  • IDX_ADDAPB1RST : gd32f3x0_rcu.h
  • IDX_ADDCTL : gd32f3x0_rcu.h
  • IDX_ADDINT : gd32f3x0_rcu.h
  • IDX_AHBEN : gd32f3x0_rcu.h
  • IDX_AHBRST : gd32f3x0_rcu.h
  • IDX_APB1EN : gd32f3x0_rcu.h
  • IDX_APB1RST : gd32f3x0_rcu.h
  • IDX_APB2EN : gd32f3x0_rcu.h
  • IDX_APB2RST : gd32f3x0_rcu.h
  • IDX_BDCTL : gd32f3x0_rcu.h
  • IDX_CFG0 : gd32f3x0_rcu.h
  • IDX_CFG2 : gd32f3x0_rcu.h
  • IDX_CTL0 : gd32f3x0_rcu.h
  • IDX_CTL1 : gd32f3x0_rcu.h
  • IDX_INT : gd32f3x0_rcu.h
  • IDX_RSTSCK : gd32f3x0_rcu.h


GD32F3x0_Firmware_Library: Globals

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  • u

- r -

  • RCU_ADC : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV2 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV3 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV4 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV5 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV6 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV7 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV8 : gd32f3x0_rcu.h
  • RCU_ADCCK_APB2_DIV9 : gd32f3x0_rcu.h
  • RCU_ADCCK_IRC28M : gd32f3x0_rcu.h
  • RCU_ADCCK_IRC28M_DIV2 : gd32f3x0_rcu.h
  • RCU_ADCRST : gd32f3x0_rcu.h
  • RCU_CFGCMP : gd32f3x0_rcu.h
  • RCU_CFGCMPRST : gd32f3x0_rcu.h
  • RCU_CRC : gd32f3x0_rcu.h
  • RCU_CTC : gd32f3x0_rcu.h
  • RCU_CTCRST : gd32f3x0_rcu.h
  • RCU_DMA : gd32f3x0_rcu.h
  • RCU_FLAG_EPRST : gd32f3x0_rcu.h
  • RCU_FLAG_FWDGTRST : gd32f3x0_rcu.h
  • RCU_FLAG_HXTALSTB : gd32f3x0_rcu.h
  • RCU_FLAG_IRC28MSTB : gd32f3x0_rcu.h
  • RCU_FLAG_IRC40KSTB : gd32f3x0_rcu.h
  • RCU_FLAG_IRC48MSTB : gd32f3x0_rcu.h
  • RCU_FLAG_IRC8MSTB : gd32f3x0_rcu.h
  • RCU_FLAG_LPRST : gd32f3x0_rcu.h
  • RCU_FLAG_LXTALSTB : gd32f3x0_rcu.h
  • RCU_FLAG_OBLRST : gd32f3x0_rcu.h
  • RCU_FLAG_PLLSTB : gd32f3x0_rcu.h
  • RCU_FLAG_PORRST : gd32f3x0_rcu.h
  • RCU_FLAG_SWRST : gd32f3x0_rcu.h
  • RCU_FLAG_V12RST : gd32f3x0_rcu.h
  • RCU_FLAG_WWDGTRST : gd32f3x0_rcu.h
  • RCU_FMC_SLP : gd32f3x0_rcu.h
  • RCU_GPIOA : gd32f3x0_rcu.h
  • RCU_GPIOARST : gd32f3x0_rcu.h
  • RCU_GPIOB : gd32f3x0_rcu.h
  • RCU_GPIOBRST : gd32f3x0_rcu.h
  • RCU_GPIOC : gd32f3x0_rcu.h
  • RCU_GPIOCRST : gd32f3x0_rcu.h
  • RCU_GPIOD : gd32f3x0_rcu.h
  • RCU_GPIODRST : gd32f3x0_rcu.h
  • RCU_GPIOF : gd32f3x0_rcu.h
  • RCU_GPIOFRST : gd32f3x0_rcu.h
  • RCU_HXTAL : gd32f3x0_rcu.h
  • RCU_I2C0 : gd32f3x0_rcu.h
  • RCU_I2C0RST : gd32f3x0_rcu.h
  • RCU_I2C1 : gd32f3x0_rcu.h
  • RCU_I2C1RST : gd32f3x0_rcu.h
  • RCU_I2C2 : gd32f3x0_rcu.h
  • RCU_I2C2RST : gd32f3x0_rcu.h
  • RCU_INT_FLAG_CKM : gd32f3x0_rcu.h
  • RCU_INT_FLAG_CKM_CLR : gd32f3x0_rcu.h
  • RCU_INT_FLAG_HXTALSTB : gd32f3x0_rcu.h
  • RCU_INT_FLAG_HXTALSTB_CLR : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC28MSTB : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC28MSTB_CLR : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC40KSTB : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC40KSTB_CLR : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC48MSTB : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC48MSTB_CLR : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC8MSTB : gd32f3x0_rcu.h
  • RCU_INT_FLAG_IRC8MSTB_CLR : gd32f3x0_rcu.h
  • RCU_INT_FLAG_LXTALSTB : gd32f3x0_rcu.h
  • RCU_INT_FLAG_LXTALSTB_CLR : gd32f3x0_rcu.h
  • RCU_INT_FLAG_PLLSTB : gd32f3x0_rcu.h
  • RCU_INT_FLAG_PLLSTB_CLR : gd32f3x0_rcu.h
  • RCU_INT_HXTALSTB : gd32f3x0_rcu.h
  • RCU_INT_IRC28MSTB : gd32f3x0_rcu.h
  • RCU_INT_IRC40KSTB : gd32f3x0_rcu.h
  • RCU_INT_IRC48MSTB : gd32f3x0_rcu.h
  • RCU_INT_IRC8MSTB : gd32f3x0_rcu.h
  • RCU_INT_LXTALSTB : gd32f3x0_rcu.h
  • RCU_INT_PLLSTB : gd32f3x0_rcu.h
  • RCU_IRC28M : gd32f3x0_rcu.h
  • RCU_IRC40K : gd32f3x0_rcu.h
  • RCU_IRC48M : gd32f3x0_rcu.h
  • RCU_IRC8M : gd32f3x0_rcu.h
  • RCU_LXTAL : gd32f3x0_rcu.h
  • RCU_PLL_CK : gd32f3x0_rcu.h
  • RCU_PMU : gd32f3x0_rcu.h
  • RCU_PMURST : gd32f3x0_rcu.h
  • RCU_RTC : gd32f3x0_rcu.h
  • RCU_SPI0 : gd32f3x0_rcu.h
  • RCU_SPI0RST : gd32f3x0_rcu.h
  • RCU_SPI1 : gd32f3x0_rcu.h
  • RCU_SPI1RST : gd32f3x0_rcu.h
  • RCU_SPI2 : gd32f3x0_rcu.h
  • RCU_SPI2RST : gd32f3x0_rcu.h
  • RCU_SRAM_SLP : gd32f3x0_rcu.h
  • RCU_TIMER0 : gd32f3x0_rcu.h
  • RCU_TIMER0RST : gd32f3x0_rcu.h
  • RCU_TIMER1 : gd32f3x0_rcu.h
  • RCU_TIMER13 : gd32f3x0_rcu.h
  • RCU_TIMER13RST : gd32f3x0_rcu.h
  • RCU_TIMER14 : gd32f3x0_rcu.h
  • RCU_TIMER14RST : gd32f3x0_rcu.h
  • RCU_TIMER15 : gd32f3x0_rcu.h
  • RCU_TIMER15RST : gd32f3x0_rcu.h
  • RCU_TIMER16 : gd32f3x0_rcu.h
  • RCU_TIMER16RST : gd32f3x0_rcu.h
  • RCU_TIMER1RST : gd32f3x0_rcu.h
  • RCU_TIMER2 : gd32f3x0_rcu.h
  • RCU_TIMER2RST : gd32f3x0_rcu.h
  • RCU_TSI : gd32f3x0_rcu.h
  • RCU_TSIRST : gd32f3x0_rcu.h
  • RCU_USART0 : gd32f3x0_rcu.h
  • RCU_USART0RST : gd32f3x0_rcu.h
  • RCU_USART1 : gd32f3x0_rcu.h
  • RCU_USART1RST : gd32f3x0_rcu.h
  • RCU_WWDGT : gd32f3x0_rcu.h
  • RCU_WWDGTRST : gd32f3x0_rcu.h


GD32F3x0_Firmware_Library: Globals

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  • Enumerations
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- u -

  • URB_DONE : usb_core.h
  • URB_ERROR : usb_core.h
  • URB_IDLE : usb_core.h
  • URB_NOTREADY : usb_core.h
  • URB_PING : usb_core.h
  • URB_STALL : usb_core.h
  • USART_DINV_DISABLE : gd32f3x0_usart.h
  • USART_DINV_ENABLE : gd32f3x0_usart.h
  • USART_FLAG_ABD : gd32f3x0_usart.h
  • USART_FLAG_ABDE : gd32f3x0_usart.h
  • USART_FLAG_AM : gd32f3x0_usart.h
  • USART_FLAG_BSY : gd32f3x0_usart.h
  • USART_FLAG_CTS : gd32f3x0_usart.h
  • USART_FLAG_CTSF : gd32f3x0_usart.h
  • USART_FLAG_EB : gd32f3x0_usart.h
  • USART_FLAG_FERR : gd32f3x0_usart.h
  • USART_FLAG_IDLE : gd32f3x0_usart.h
  • USART_FLAG_LBD : gd32f3x0_usart.h
  • USART_FLAG_NERR : gd32f3x0_usart.h
  • USART_FLAG_ORERR : gd32f3x0_usart.h
  • USART_FLAG_PERR : gd32f3x0_usart.h
  • USART_FLAG_RBNE : gd32f3x0_usart.h
  • USART_FLAG_REA : gd32f3x0_usart.h
  • USART_FLAG_RFE : gd32f3x0_usart.h
  • USART_FLAG_RFF : gd32f3x0_usart.h
  • USART_FLAG_RFFINT : gd32f3x0_usart.h
  • USART_FLAG_RT : gd32f3x0_usart.h
  • USART_FLAG_RWU : gd32f3x0_usart.h
  • USART_FLAG_SB : gd32f3x0_usart.h
  • USART_FLAG_TBE : gd32f3x0_usart.h
  • USART_FLAG_TC : gd32f3x0_usart.h
  • USART_FLAG_TEA : gd32f3x0_usart.h
  • USART_FLAG_WU : gd32f3x0_usart.h
  • USART_INT_AM : gd32f3x0_usart.h
  • USART_INT_CTS : gd32f3x0_usart.h
  • USART_INT_EB : gd32f3x0_usart.h
  • USART_INT_ERR : gd32f3x0_usart.h
  • USART_INT_FLAG_AM : gd32f3x0_usart.h
  • USART_INT_FLAG_CTS : gd32f3x0_usart.h
  • USART_INT_FLAG_EB : gd32f3x0_usart.h
  • USART_INT_FLAG_ERR_FERR : gd32f3x0_usart.h
  • USART_INT_FLAG_ERR_NERR : gd32f3x0_usart.h
  • USART_INT_FLAG_ERR_ORERR : gd32f3x0_usart.h
  • USART_INT_FLAG_IDLE : gd32f3x0_usart.h
  • USART_INT_FLAG_LBD : gd32f3x0_usart.h
  • USART_INT_FLAG_PERR : gd32f3x0_usart.h
  • USART_INT_FLAG_RBNE : gd32f3x0_usart.h
  • USART_INT_FLAG_RBNE_ORERR : gd32f3x0_usart.h
  • USART_INT_FLAG_RFF : gd32f3x0_usart.h
  • USART_INT_FLAG_RT : gd32f3x0_usart.h
  • USART_INT_FLAG_TBE : gd32f3x0_usart.h
  • USART_INT_FLAG_TC : gd32f3x0_usart.h
  • USART_INT_FLAG_WU : gd32f3x0_usart.h
  • USART_INT_IDLE : gd32f3x0_usart.h
  • USART_INT_LBD : gd32f3x0_usart.h
  • USART_INT_PERR : gd32f3x0_usart.h
  • USART_INT_RBNE : gd32f3x0_usart.h
  • USART_INT_RFF : gd32f3x0_usart.h
  • USART_INT_RT : gd32f3x0_usart.h
  • USART_INT_TBE : gd32f3x0_usart.h
  • USART_INT_TC : gd32f3x0_usart.h
  • USART_INT_WU : gd32f3x0_usart.h
  • USART_RXPIN_DISABLE : gd32f3x0_usart.h
  • USART_RXPIN_ENABLE : gd32f3x0_usart.h
  • USART_SWAP_DISABLE : gd32f3x0_usart.h
  • USART_SWAP_ENABLE : gd32f3x0_usart.h
  • USART_TXPIN_DISABLE : gd32f3x0_usart.h
  • USART_TXPIN_ENABLE : gd32f3x0_usart.h
  • USB_CTRL_DATA_IN : usb_core.h
  • USB_CTRL_DATA_OUT : usb_core.h
  • USB_CTRL_IDLE : usb_core.h
  • USB_CTRL_SETUP : usb_core.h
  • USB_CTRL_STALL : usb_core.h
  • USB_CTRL_STATUS_IN : usb_core.h
  • USB_CTRL_STATUS_OUT : usb_core.h
  • USB_FAIL : usb_core.h
  • USB_FS_CORE_ID : usb_defines.h
  • USB_HS_CORE_ID : usb_defines.h
  • USB_OK : usb_core.h
  • USB_RX : usb_core.h
  • USB_SPEED_FULL : usb_defines.h
  • USB_SPEED_HIGH : usb_defines.h
  • USB_SPEED_LOW : usb_defines.h
  • USB_SPEED_UNKNOWN : usb_defines.h
  • USB_TX : usb_core.h
  • USBD_BUSY : usb_core.h
  • USBD_FAIL : usb_core.h
  • USBD_OK : usb_core.h
  • USBH_APPLY_DEINIT : usbh_core.h
  • USBH_BUSY : usbh_core.h
  • USBH_FAIL : usbh_core.h
  • USBH_NOT_SUPPORTED : usbh_core.h
  • USBH_OK : usbh_core.h
  • USBH_SPEED_UNKNOWN_ERROR : usbh_core.h
  • USBH_UNRECOVERED_ERROR : usbh_core.h
  • USBH_USER_NO_RESP : usbh_core.h
  • USBH_USER_RESP_OK : usbh_core.h


GD32F3x0_Firmware_Library: Globals

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- _ -

  • __HXTAL : system_gd32f3x0.c
  • __IRC8M : system_gd32f3x0.c
  • __SYS_OSC_CLK : system_gd32f3x0.c
  • _WIDE_STRING : usbd_std.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • w

- a -

  • ADC : gd32f3x0_adc.h
  • ADC_CHANNEL_0 : gd32f3x0_adc.h
  • ADC_CHANNEL_1 : gd32f3x0_adc.h
  • ADC_CHANNEL_10 : gd32f3x0_adc.h
  • ADC_CHANNEL_11 : gd32f3x0_adc.h
  • ADC_CHANNEL_12 : gd32f3x0_adc.h
  • ADC_CHANNEL_13 : gd32f3x0_adc.h
  • ADC_CHANNEL_14 : gd32f3x0_adc.h
  • ADC_CHANNEL_15 : gd32f3x0_adc.h
  • ADC_CHANNEL_16 : gd32f3x0_adc.h
  • ADC_CHANNEL_17 : gd32f3x0_adc.h
  • ADC_CHANNEL_18 : gd32f3x0_adc.h
  • ADC_CHANNEL_2 : gd32f3x0_adc.h
  • ADC_CHANNEL_3 : gd32f3x0_adc.h
  • ADC_CHANNEL_4 : gd32f3x0_adc.h
  • ADC_CHANNEL_5 : gd32f3x0_adc.h
  • ADC_CHANNEL_6 : gd32f3x0_adc.h
  • ADC_CHANNEL_7 : gd32f3x0_adc.h
  • ADC_CHANNEL_8 : gd32f3x0_adc.h
  • ADC_CHANNEL_9 : gd32f3x0_adc.h
  • ADC_CHANNEL_DISCON_DISABLE : gd32f3x0_adc.h
  • ADC_CONTINUOUS_MODE : gd32f3x0_adc.h
  • ADC_CTL0 : gd32f3x0_adc.h
  • ADC_CTL0_DISIC : gd32f3x0_adc.h
  • ADC_CTL0_DISNUM : gd32f3x0_adc.h
  • ADC_CTL0_DISRC : gd32f3x0_adc.h
  • ADC_CTL0_DRES : gd32f3x0_adc.h
  • ADC_CTL0_EOCIE : gd32f3x0_adc.h
  • ADC_CTL0_EOICIE : gd32f3x0_adc.h
  • ADC_CTL0_ICA : gd32f3x0_adc.h
  • ADC_CTL0_IWDEN : gd32f3x0_adc.h
  • ADC_CTL0_RWDEN : gd32f3x0_adc.h
  • ADC_CTL0_SM : gd32f3x0_adc.h
  • ADC_CTL0_WDCHSEL : gd32f3x0_adc.h
  • ADC_CTL0_WDEIE : gd32f3x0_adc.h
  • ADC_CTL0_WDSC : gd32f3x0_adc.h
  • ADC_CTL1 : gd32f3x0_adc.h
  • ADC_CTL1_ADCON : gd32f3x0_adc.h
  • ADC_CTL1_CLB : gd32f3x0_adc.h
  • ADC_CTL1_CTN : gd32f3x0_adc.h
  • ADC_CTL1_DAL : gd32f3x0_adc.h
  • ADC_CTL1_DMA : gd32f3x0_adc.h
  • ADC_CTL1_ETEIC : gd32f3x0_adc.h
  • ADC_CTL1_ETERC : gd32f3x0_adc.h
  • ADC_CTL1_ETSIC : gd32f3x0_adc.h
  • ADC_CTL1_ETSRC : gd32f3x0_adc.h
  • ADC_CTL1_RSTCLB : gd32f3x0_adc.h
  • ADC_CTL1_SWICST : gd32f3x0_adc.h
  • ADC_CTL1_SWRCST : gd32f3x0_adc.h
  • ADC_CTL1_TSVREN : gd32f3x0_adc.h
  • ADC_CTL1_VBETEN : gd32f3x0_adc.h
  • ADC_DATAALIGN_LEFT : gd32f3x0_adc.h
  • ADC_DATAALIGN_RIGHT : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_EXTI_15 : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_NONE : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_T0_CH3 : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_T0_TRGO : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_T14_TRGO : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_T1_CH0 : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_T1_TRGO : gd32f3x0_adc.h
  • ADC_EXTTRIG_INSERTED_T2_CH3 : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_EXTI_11 : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_NONE : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_T0_CH0 : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_T0_CH1 : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_T0_CH2 : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_T14_CH1 : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_T1_CH1 : gd32f3x0_adc.h
  • ADC_EXTTRIG_REGULAR_T2_TRGO : gd32f3x0_adc.h
  • ADC_FLAG_EOC : gd32f3x0_adc.h
  • ADC_FLAG_EOIC : gd32f3x0_adc.h
  • ADC_FLAG_STIC : gd32f3x0_adc.h
  • ADC_FLAG_STRC : gd32f3x0_adc.h
  • ADC_FLAG_WDE : gd32f3x0_adc.h
  • ADC_IDATA0 : gd32f3x0_adc.h
  • ADC_IDATA1 : gd32f3x0_adc.h
  • ADC_IDATA2 : gd32f3x0_adc.h
  • ADC_IDATA3 : gd32f3x0_adc.h
  • ADC_IDATAX_IDATAN : gd32f3x0_adc.h
  • ADC_INSERTED_CHANNEL : gd32f3x0_adc.h
  • ADC_INSERTED_CHANNEL_0 : gd32f3x0_adc.h
  • ADC_INSERTED_CHANNEL_1 : gd32f3x0_adc.h
  • ADC_INSERTED_CHANNEL_2 : gd32f3x0_adc.h
  • ADC_INSERTED_CHANNEL_3 : gd32f3x0_adc.h
  • ADC_INSERTED_CHANNEL_AUTO : gd32f3x0_adc.h
  • ADC_INT_EOC : gd32f3x0_adc.h
  • ADC_INT_EOIC : gd32f3x0_adc.h
  • ADC_INT_FLAG_EOC : gd32f3x0_adc.h
  • ADC_INT_FLAG_EOIC : gd32f3x0_adc.h
  • ADC_INT_FLAG_WDE : gd32f3x0_adc.h
  • ADC_INT_WDE : gd32f3x0_adc.h
  • ADC_IOFF0 : gd32f3x0_adc.h
  • ADC_IOFF1 : gd32f3x0_adc.h
  • ADC_IOFF2 : gd32f3x0_adc.h
  • ADC_IOFF3 : gd32f3x0_adc.h
  • ADC_IOFFX_IOFF : gd32f3x0_adc.h
  • ADC_ISQ : gd32f3x0_adc.h
  • ADC_ISQ_IL : gd32f3x0_adc.h
  • ADC_ISQ_ISQN : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_ALL_CONVERT : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_ONE_CONVERT : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL128 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL16 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL2 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL256 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL32 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL4 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL64 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_RATIO_MUL8 : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_1B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_2B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_3B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_4B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_5B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_6B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_7B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_8B : gd32f3x0_adc.h
  • ADC_OVERSAMPLING_SHIFT_NONE : gd32f3x0_adc.h
  • ADC_OVSAMPCTL : gd32f3x0_adc.h
  • ADC_OVSAMPCTL_OVSEN : gd32f3x0_adc.h
  • ADC_OVSAMPCTL_OVSR : gd32f3x0_adc.h
  • ADC_OVSAMPCTL_OVSS : gd32f3x0_adc.h
  • ADC_OVSAMPCTL_TOVS : gd32f3x0_adc.h
  • ADC_RDATA : gd32f3x0_adc.h
  • ADC_RDATA_RDATA : gd32f3x0_adc.h
  • ADC_REGULAR_CHANNEL : gd32f3x0_adc.h
  • ADC_REGULAR_INSERTED_CHANNEL : gd32f3x0_adc.h
  • ADC_RESOLUTION_10B : gd32f3x0_adc.h
  • ADC_RESOLUTION_12B : gd32f3x0_adc.h
  • ADC_RESOLUTION_6B : gd32f3x0_adc.h
  • ADC_RESOLUTION_8B : gd32f3x0_adc.h
  • ADC_RSQ0 : gd32f3x0_adc.h
  • ADC_RSQ0_RL : gd32f3x0_adc.h
  • ADC_RSQ1 : gd32f3x0_adc.h
  • ADC_RSQ2 : gd32f3x0_adc.h
  • ADC_RSQX_RSQN : gd32f3x0_adc.h
  • ADC_SAMPLETIME_13POINT5 : gd32f3x0_adc.h
  • ADC_SAMPLETIME_1POINT5 : gd32f3x0_adc.h
  • ADC_SAMPLETIME_239POINT5 : gd32f3x0_adc.h
  • ADC_SAMPLETIME_28POINT5 : gd32f3x0_adc.h
  • ADC_SAMPLETIME_41POINT5 : gd32f3x0_adc.h
  • ADC_SAMPLETIME_55POINT5 : gd32f3x0_adc.h
  • ADC_SAMPLETIME_71POINT5 : gd32f3x0_adc.h
  • ADC_SAMPLETIME_7POINT5 : gd32f3x0_adc.h
  • ADC_SAMPT0 : gd32f3x0_adc.h
  • ADC_SAMPT1 : gd32f3x0_adc.h
  • ADC_SAMPTX_SPTN : gd32f3x0_adc.h
  • ADC_SCAN_MODE : gd32f3x0_adc.h
  • ADC_STAT : gd32f3x0_adc.h
  • ADC_STAT_EOC : gd32f3x0_adc.h
  • ADC_STAT_EOIC : gd32f3x0_adc.h
  • ADC_STAT_STIC : gd32f3x0_adc.h
  • ADC_STAT_STRC : gd32f3x0_adc.h
  • ADC_STAT_WDE : gd32f3x0_adc.h
  • ADC_WDHT : gd32f3x0_adc.h
  • ADC_WDHT_WDHT : gd32f3x0_adc.h
  • ADC_WDLT : gd32f3x0_adc.h
  • ADC_WDLT_WDLT : gd32f3x0_adc.h
  • AF : gd32f3x0_gpio.h
  • ALRM0SS_MASKSSC : gd32f3x0_rtc.h
  • ALRM0SS_SSC : gd32f3x0_rtc.h
  • ALRM0TD_DAY : gd32f3x0_rtc.h
  • ALRM0TD_HR : gd32f3x0_rtc.h
  • ALRM0TD_MN : gd32f3x0_rtc.h
  • ALRM0TD_SC : gd32f3x0_rtc.h


GD32F3x0_Firmware_Library: Globals

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- b -

  • BDCTL_LXTALDRI : gd32f3x0_rcu.h
  • BDCTL_RTCSRC : gd32f3x0_rcu.h


GD32F3x0_Firmware_Library: Globals

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- c -

  • CBI_PROTOCOL : usbh_core.h
  • CCHP_PROT : gd32f3x0_timer.h
  • CFG0_ADCPSC : gd32f3x0_rcu.h
  • CFG0_AHBPSC : gd32f3x0_rcu.h
  • CFG0_APB1PSC : gd32f3x0_rcu.h
  • CFG0_APB2PSC : gd32f3x0_rcu.h
  • CFG0_CKOUTDIV : gd32f3x0_rcu.h
  • CFG0_CKOUTSEL : gd32f3x0_rcu.h
  • CFG0_PLLMF : gd32f3x0_rcu.h
  • CFG0_SCS : gd32f3x0_rcu.h
  • CFG0_SCSS : gd32f3x0_rcu.h
  • CFG0_USBFSPSC : gd32f3x0_rcu.h
  • CFG1_PREDV : gd32f3x0_rcu.h
  • CFG2_USART0SEL : gd32f3x0_rcu.h
  • CFG_PSC : gd32f3x0_wwdgt.h
  • CFG_WIN : gd32f3x0_wwdgt.h
  • CHCTL_MWIDTH : gd32f3x0_dma.h
  • CHCTL_PRIO : gd32f3x0_dma.h
  • CHCTL_PWIDTH : gd32f3x0_dma.h
  • CHN_LANGID : usbd_std.h
  • CID_CID : usb_regs.h
  • CKCFG_DTCY : gd32f3x0_i2c.h
  • CLASS_FSM_ID : usbh_core.h
  • CLASS_REQ_FSM_ID : usbh_core.h
  • CMD_FSM_ID : usbh_core.h
  • CMP : gd32f3x0_cmp.h
  • CMP0 : gd32f3x0_cmp.h
  • CMP1 : gd32f3x0_cmp.h
  • CMP_CS : gd32f3x0_cmp.h
  • CMP_CS_CMP0EN : gd32f3x0_cmp.h
  • CMP_CS_CMP0HST : gd32f3x0_cmp.h
  • CMP_CS_CMP0LK : gd32f3x0_cmp.h
  • CMP_CS_CMP0M : gd32f3x0_cmp.h
  • CMP_CS_CMP0MSEL : gd32f3x0_cmp.h
  • CMP_CS_CMP0O : gd32f3x0_cmp.h
  • CMP_CS_CMP0OSEL : gd32f3x0_cmp.h
  • CMP_CS_CMP0PL : gd32f3x0_cmp.h
  • CMP_CS_CMP0SW : gd32f3x0_cmp.h
  • CMP_CS_CMP1EN : gd32f3x0_cmp.h
  • CMP_CS_CMP1HST : gd32f3x0_cmp.h
  • CMP_CS_CMP1LK : gd32f3x0_cmp.h
  • CMP_CS_CMP1M : gd32f3x0_cmp.h
  • CMP_CS_CMP1MSEL : gd32f3x0_cmp.h
  • CMP_CS_CMP1O : gd32f3x0_cmp.h
  • CMP_CS_CMP1OSEL : gd32f3x0_cmp.h
  • CMP_CS_CMP1PL : gd32f3x0_cmp.h
  • CMP_CS_WNDEN : gd32f3x0_cmp.h
  • CMP_OUTPUT_POLARITY_INVERTED : gd32f3x0_cmp.h
  • CMP_OUTPUT_POLARITY_NOINVERTED : gd32f3x0_cmp.h
  • CMP_OUTPUTLEVEL_HIGH : gd32f3x0_cmp.h
  • CMP_OUTPUTLEVEL_LOW : gd32f3x0_cmp.h
  • CRC : gd32f3x0_crc.h
  • CRC_CTL : gd32f3x0_crc.h
  • CRC_CTL_PS : gd32f3x0_crc.h
  • CRC_CTL_PS_16 : gd32f3x0_crc.h
  • CRC_CTL_PS_32 : gd32f3x0_crc.h
  • CRC_CTL_PS_7 : gd32f3x0_crc.h
  • CRC_CTL_PS_8 : gd32f3x0_crc.h
  • CRC_CTL_REV_I : gd32f3x0_crc.h
  • CRC_CTL_REV_O : gd32f3x0_crc.h
  • CRC_CTL_RST : gd32f3x0_crc.h
  • CRC_DATA : gd32f3x0_crc.h
  • CRC_DATA_DATA : gd32f3x0_crc.h
  • CRC_FDATA : gd32f3x0_crc.h
  • CRC_FDATA_FDATA : gd32f3x0_crc.h
  • CRC_IDATA : gd32f3x0_crc.h
  • CRC_IDATA_IDATA : gd32f3x0_crc.h
  • CRC_INPUT_DATA_BYTE : gd32f3x0_crc.h
  • CRC_INPUT_DATA_HALFWORD : gd32f3x0_crc.h
  • CRC_INPUT_DATA_NOT : gd32f3x0_crc.h
  • CRC_INPUT_DATA_WORD : gd32f3x0_crc.h
  • CRC_POLY : gd32f3x0_crc.h
  • CRC_POLY_POLY : gd32f3x0_crc.h
  • CS_CMP0HST : gd32f3x0_cmp.h
  • CS_CMP0HST_HYSTERESIS_HIGH : gd32f3x0_cmp.h
  • CS_CMP0HST_HYSTERESIS_LOW : gd32f3x0_cmp.h
  • CS_CMP0HST_HYSTERESIS_MIDDLE : gd32f3x0_cmp.h
  • CS_CMP0HST_HYSTERESIS_NO : gd32f3x0_cmp.h
  • CS_CMP0M : gd32f3x0_cmp.h
  • CS_CMP0M_HIGHSPEED : gd32f3x0_cmp.h
  • CS_CMP0M_LOWSPEED : gd32f3x0_cmp.h
  • CS_CMP0M_MIDDLESPEED : gd32f3x0_cmp.h
  • CS_CMP0M_VERYLOWSPEED : gd32f3x0_cmp.h
  • CS_CMP0MSEL : gd32f3x0_cmp.h
  • CS_CMP0MSEL_1_2VREFINT : gd32f3x0_cmp.h
  • CS_CMP0MSEL_1_4VREFINT : gd32f3x0_cmp.h
  • CS_CMP0MSEL_3_4VREFINT : gd32f3x0_cmp.h
  • CS_CMP0MSEL_DAC : gd32f3x0_cmp.h
  • CS_CMP0MSEL_PA0 : gd32f3x0_cmp.h
  • CS_CMP0MSEL_PA5 : gd32f3x0_cmp.h
  • CS_CMP0MSEL_VREFINT : gd32f3x0_cmp.h
  • CS_CMP0OSEL : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_NONE : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_TIMER0BKIN : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_TIMER0IC0 : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_TIMER0OCPRECLR : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_TIMER1IC3 : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_TIMER1OCPRECLR : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_TIMER2IC0 : gd32f3x0_cmp.h
  • CS_CMP0OSEL_OUTPUT_TIMER2OCPRECLR : gd32f3x0_cmp.h
  • CS_CMP1HST : gd32f3x0_cmp.h
  • CS_CMP1HST_HSTHYSTERESIS_NO : gd32f3x0_cmp.h
  • CS_CMP1HST_HYSTERESIS_HIGH : gd32f3x0_cmp.h
  • CS_CMP1HST_HYSTERESIS_LOW : gd32f3x0_cmp.h
  • CS_CMP1HST_HYSTERESIS_MIDDLE : gd32f3x0_cmp.h
  • CS_CMP1M : gd32f3x0_cmp.h
  • CS_CMP1M_HIGHSPEED : gd32f3x0_cmp.h
  • CS_CMP1M_LOWSPEED : gd32f3x0_cmp.h
  • CS_CMP1M_MIDDLESPEED : gd32f3x0_cmp.h
  • CS_CMP1M_VERYLOWSPEED : gd32f3x0_cmp.h
  • CS_CMP1MSEL : gd32f3x0_cmp.h
  • CS_CMP1MSEL_1_2VREFINT : gd32f3x0_cmp.h
  • CS_CMP1MSEL_1_4VREFINT : gd32f3x0_cmp.h
  • CS_CMP1MSEL_3_4VREFINT : gd32f3x0_cmp.h
  • CS_CMP1MSEL_DAC : gd32f3x0_cmp.h
  • CS_CMP1MSEL_PA2 : gd32f3x0_cmp.h
  • CS_CMP1MSEL_PA5 : gd32f3x0_cmp.h
  • CS_CMP1MSEL_VREFINT : gd32f3x0_cmp.h
  • CS_CMP1OSEL : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_NONE : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_TIMER0BKIN : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_TIMER0IC0 : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_TIMER0OCPRECLR : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_TIMER1IC3 : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_TIMER1OCPRECLR : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_TIMER2IC0 : gd32f3x0_cmp.h
  • CS_CMP1OSEL_OUTPUT_TIMER2OCPRECLR : gd32f3x0_cmp.h
  • CS_LDRF : gd32f3x0_pmu.h
  • CTC : gd32f3x0_ctc.h
  • CTC_CTL0 : gd32f3x0_ctc.h
  • CTC_CTL0_AUTOTRIM : gd32f3x0_ctc.h
  • CTC_CTL0_CKOKIE : gd32f3x0_ctc.h
  • CTC_CTL0_CKWARNIE : gd32f3x0_ctc.h
  • CTC_CTL0_CNTEN : gd32f3x0_ctc.h
  • CTC_CTL0_EREFIE : gd32f3x0_ctc.h
  • CTC_CTL0_ERRIE : gd32f3x0_ctc.h
  • CTC_CTL0_SWREFPUL : gd32f3x0_ctc.h
  • CTC_CTL0_TRIMVALUE : gd32f3x0_ctc.h
  • CTC_CTL1 : gd32f3x0_ctc.h
  • CTC_CTL1_CKLIM : gd32f3x0_ctc.h
  • CTC_CTL1_REFPOL : gd32f3x0_ctc.h
  • CTC_CTL1_REFPSC : gd32f3x0_ctc.h
  • CTC_CTL1_REFSEL : gd32f3x0_ctc.h
  • CTC_CTL1_RLVALUE : gd32f3x0_ctc.h
  • CTC_FLAG_CKERR : gd32f3x0_ctc.h
  • CTC_FLAG_CKOK : gd32f3x0_ctc.h
  • CTC_FLAG_CKWARN : gd32f3x0_ctc.h
  • CTC_FLAG_EREF : gd32f3x0_ctc.h
  • CTC_FLAG_ERR : gd32f3x0_ctc.h
  • CTC_FLAG_MASK : gd32f3x0_ctc.c
  • CTC_FLAG_REFMISS : gd32f3x0_ctc.h
  • CTC_FLAG_TRIMERR : gd32f3x0_ctc.h
  • CTC_HARDWARE_TRIM_MODE_DISABLE : gd32f3x0_ctc.h
  • CTC_HARDWARE_TRIM_MODE_ENABLE : gd32f3x0_ctc.h
  • CTC_INT_CKOK : gd32f3x0_ctc.h
  • CTC_INT_CKWARN : gd32f3x0_ctc.h
  • CTC_INT_EREF : gd32f3x0_ctc.h
  • CTC_INT_ERR : gd32f3x0_ctc.h
  • CTC_INT_FLAG_CKERR : gd32f3x0_ctc.h
  • CTC_INT_FLAG_CKOK : gd32f3x0_ctc.h
  • CTC_INT_FLAG_CKWARN : gd32f3x0_ctc.h
  • CTC_INT_FLAG_EREF : gd32f3x0_ctc.h
  • CTC_INT_FLAG_ERR : gd32f3x0_ctc.h
  • CTC_INT_FLAG_REFMISS : gd32f3x0_ctc.h
  • CTC_INT_FLAG_TRIMERR : gd32f3x0_ctc.h
  • CTC_INTC : gd32f3x0_ctc.h
  • CTC_INTC_CKOKIC : gd32f3x0_ctc.h
  • CTC_INTC_CKWARNIC : gd32f3x0_ctc.h
  • CTC_INTC_EREFIC : gd32f3x0_ctc.h
  • CTC_INTC_ERRIC : gd32f3x0_ctc.h
  • CTC_REFSOURCE_GPIO : gd32f3x0_ctc.h
  • CTC_REFSOURCE_LXTAL : gd32f3x0_ctc.h
  • CTC_REFSOURCE_POLARITY_FALLING : gd32f3x0_ctc.h
  • CTC_REFSOURCE_POLARITY_RISING : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_DIV128 : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_DIV16 : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_DIV2 : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_DIV32 : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_DIV4 : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_DIV64 : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_DIV8 : gd32f3x0_ctc.h
  • CTC_REFSOURCE_PSC_OFF : gd32f3x0_ctc.h
  • CTC_REFSOURCE_USBSOF : gd32f3x0_ctc.h
  • CTC_STAT : gd32f3x0_ctc.h
  • CTC_STAT_CKERR : gd32f3x0_ctc.h
  • CTC_STAT_CKOKIF : gd32f3x0_ctc.h
  • CTC_STAT_CKWARNIF : gd32f3x0_ctc.h
  • CTC_STAT_EREFIF : gd32f3x0_ctc.h
  • CTC_STAT_ERRIF : gd32f3x0_ctc.h
  • CTC_STAT_REFCAP : gd32f3x0_ctc.h
  • CTC_STAT_REFDIR : gd32f3x0_ctc.h
  • CTC_STAT_REFMISS : gd32f3x0_ctc.h
  • CTC_STAT_TRIMERR : gd32f3x0_ctc.h
  • CTL0_CAM : gd32f3x0_timer.h
  • CTL0_CKDIV : gd32f3x0_timer.h
  • CTL0_DISNUM : gd32f3x0_adc.h
  • CTL0_DRES : gd32f3x0_adc.h
  • CTL0_OVSMOD : gd32f3x0_usart.h
  • CTL0_PM : gd32f3x0_usart.h
  • CTL0_PSC : gd32f3x0_spi.h
  • CTL0_REN : gd32f3x0_usart.h
  • CTL0_TEN : gd32f3x0_usart.h
  • CTL0_TRIMVALUE : gd32f3x0_ctc.h
  • CTL0_WL : gd32f3x0_usart.h
  • CTL0_WM : gd32f3x0_usart.h
  • CTL1_ABDM : gd32f3x0_usart.h
  • CTL1_ADDM : gd32f3x0_usart.h
  • CTL1_CKLIM : gd32f3x0_ctc.h
  • CTL1_CLEN : gd32f3x0_usart.h
  • CTL1_CPH : gd32f3x0_usart.h
  • CTL1_CPL : gd32f3x0_usart.h
  • CTL1_ETSIC : gd32f3x0_adc.h
  • CTL1_ETSRC : gd32f3x0_adc.h
  • CTL1_LBLEN : gd32f3x0_usart.h
  • CTL1_MMC : gd32f3x0_timer.h
  • CTL1_MSBF : gd32f3x0_usart.h
  • CTL1_REFPSC : gd32f3x0_ctc.h
  • CTL1_REFSEL : gd32f3x0_ctc.h
  • CTL1_STB : gd32f3x0_usart.h
  • CTL2_CTSEN : gd32f3x0_usart.h
  • CTL2_DENR : gd32f3x0_usart.h
  • CTL2_DENT : gd32f3x0_usart.h
  • CTL2_DEP : gd32f3x0_usart.h
  • CTL2_IRLP : gd32f3x0_usart.h
  • CTL2_OSB : gd32f3x0_usart.h
  • CTL2_RTSEN : gd32f3x0_usart.h
  • CTL2_WUM : gd32f3x0_usart.h
  • CTL_CDT : gd32f3x0_tsi.h
  • CTL_CLTR : gd32f3x0_gpio.h
  • CTL_CMD : gd32f3x0_fwdgt.h
  • CTL_CNT : gd32f3x0_wwdgt.h
  • CTL_CTDT : gd32f3x0_tsi.h
  • CTL_LDEN : gd32f3x0_pmu.h
  • CTL_LDOVS : gd32f3x0_pmu.h
  • CTL_LVDT : gd32f3x0_pmu.h
  • CTL_MCN : gd32f3x0_tsi.h
  • CTL_OS : gd32f3x0_rtc.h
  • CTL_PS : gd32f3x0_crc.h
  • CTL_REV_I : gd32f3x0_crc.h
  • CTRL_FSM_ID : usbh_core.h
  • CTRL_HANDLE_TABLE_SIZE : usbh_ctrl.h


GD32F3x0_Firmware_Library: Globals

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- d -

  • DAEPINT_IEPITB : usb_regs.h
  • DAEPINT_OEPITB : usb_regs.h
  • DAEPINTEN_IEPIE : usb_regs.h
  • DAEPINTEN_OEPIE : usb_regs.h
  • DATA_RECV : gd32f3x0_i2c.h
  • DATA_STAGE_TIMEOUT : usb_std.h
  • DATA_TRANS : gd32f3x0_i2c.h
  • DATE_DAY : gd32f3x0_rtc.h
  • DATE_DOW : gd32f3x0_rtc.h
  • DATE_MON : gd32f3x0_rtc.h
  • DATE_YR : gd32f3x0_rtc.h
  • DBG : gd32f3x0_dbg.h
  • DBG_BIT_POS : gd32f3x0_dbg.h
  • DBG_CTL0 : gd32f3x0_dbg.h
  • DBG_CTL0_DSLP_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_FWDGT_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_I2C0_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_I2C1_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_I2C2_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_SLP_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_STB_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_TIMER0_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_TIMER13_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_TIMER1_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_TIMER2_HOLD : gd32f3x0_dbg.h
  • DBG_CTL0_WWDGT_HOLD : gd32f3x0_dbg.h
  • DBG_CTL1 : gd32f3x0_dbg.h
  • DBG_CTL1_RTC_HOLD : gd32f3x0_dbg.h
  • DBG_CTL1_TIMER14_HOLD : gd32f3x0_dbg.h
  • DBG_CTL1_TIMER15_HOLD : gd32f3x0_dbg.h
  • DBG_CTL1_TIMER16_HOLD : gd32f3x0_dbg.h
  • DBG_ID : gd32f3x0_dbg.h
  • DBG_ID_ID_CODE : gd32f3x0_dbg.h
  • DBG_LOW_POWER_DEEPSLEEP : gd32f3x0_dbg.h
  • DBG_LOW_POWER_SLEEP : gd32f3x0_dbg.h
  • DBG_LOW_POWER_STANDBY : gd32f3x0_dbg.h
  • DBG_REG_VAL : gd32f3x0_dbg.h
  • DBG_REGIDX_BIT : gd32f3x0_dbg.h
  • DBG_RESET_VAL : gd32f3x0_dbg.c
  • DCFG_DAR : usb_regs.h
  • DCFG_DEVSPEED : usb_regs.h
  • DCFG_DS : usb_regs.h
  • DCFG_EOPFT : usb_regs.h
  • DCFG_NZLSOH : usb_regs.h
  • DCFG_PFRI : usb_regs.h
  • DCTL_CGINAK : usb_regs.h
  • DCTL_CGONAK : usb_regs.h
  • DCTL_GINS : usb_regs.h
  • DCTL_GONS : usb_regs.h
  • DCTL_POIF : usb_regs.h
  • DCTL_RWKUP : usb_regs.h
  • DCTL_SD : usb_regs.h
  • DCTL_SGINAK : usb_regs.h
  • DCTL_SGONAK : usb_regs.h
  • DEP0_MPL : usb_regs.h
  • DEP0CTL_CNAK : usb_regs.h
  • DEP0CTL_EPACT : usb_regs.h
  • DEP0CTL_EPD : usb_regs.h
  • DEP0CTL_EPEN : usb_regs.h
  • DEP0CTL_EPTYPE : usb_regs.h
  • DEP0CTL_MPL : usb_regs.h
  • DEP0CTL_NAKS : usb_regs.h
  • DEP0CTL_SNAK : usb_regs.h
  • DEP0CTL_STALL : usb_regs.h
  • DEPCTL_CNAK : usb_regs.h
  • DEPCTL_DPID : usb_regs.h
  • DEPCTL_EOFRM : usb_regs.h
  • DEPCTL_EPACT : usb_regs.h
  • DEPCTL_EPD : usb_regs.h
  • DEPCTL_EPEN : usb_regs.h
  • DEPCTL_EPTYPE : usb_regs.h
  • DEPCTL_MPL : usb_regs.h
  • DEPCTL_NAKS : usb_regs.h
  • DEPCTL_SD0PID : usb_regs.h
  • DEPCTL_SD1PID : usb_regs.h
  • DEPCTL_SEVNFRM : usb_regs.h
  • DEPCTL_SNAK : usb_regs.h
  • DEPCTL_SODDFRM : usb_regs.h
  • DEPCTL_STALL : usb_regs.h
  • DEPLEN_PCNT : usb_regs.h
  • DEPLEN_TLEN : usb_regs.h
  • DEVICE_MODE : usb_defines.h
  • DIEP0CTL_TXFNUM : usb_regs.h
  • DIEP0LEN_PCNT : usb_regs.h
  • DIEP0LEN_TLEN : usb_regs.h
  • DIEP0TFLEN_IEP0TXFD : usb_regs.h
  • DIEP0TFLEN_IEP0TXRSAR : usb_regs.h
  • DIEPCTL_TXFNUM : usb_regs.h
  • DIEPFEINTEN_IEPTXFEIE : usb_regs.h
  • DIEPINTEN_CITOEN : usb_regs.h
  • DIEPINTEN_EPDISEN : usb_regs.h
  • DIEPINTEN_EPTXFUDEN : usb_regs.h
  • DIEPINTEN_IEPNEEN : usb_regs.h
  • DIEPINTEN_TFEN : usb_regs.h
  • DIEPINTEN_TXFEEN : usb_regs.h
  • DIEPINTF_CITO : usb_regs.h
  • DIEPINTF_EPDIS : usb_regs.h
  • DIEPINTF_EPTXFUD : usb_regs.h
  • DIEPINTF_IEPNE : usb_regs.h
  • DIEPINTF_TF : usb_regs.h
  • DIEPINTF_TXFE : usb_regs.h
  • DIEPLEN_MCNT : usb_regs.h
  • DIEPTFLEN_IEPTXFD : usb_regs.h
  • DIEPTFLEN_IEPTXRSAR : usb_regs.h
  • DIEPTFSTAT_IEPTFS : usb_regs.h
  • DMA : gd32f3x0_dma.h
  • DMA_CH0CNT : gd32f3x0_dma.h
  • DMA_CH0CTL : gd32f3x0_dma.h
  • DMA_CH0MADDR : gd32f3x0_dma.h
  • DMA_CH0PADDR : gd32f3x0_dma.h
  • DMA_CH1CNT : gd32f3x0_dma.h
  • DMA_CH1CTL : gd32f3x0_dma.h
  • DMA_CH1MADDR : gd32f3x0_dma.h
  • DMA_CH1PADDR : gd32f3x0_dma.h
  • DMA_CH2CNT : gd32f3x0_dma.h
  • DMA_CH2CTL : gd32f3x0_dma.h
  • DMA_CH2MADDR : gd32f3x0_dma.h
  • DMA_CH2PADDR : gd32f3x0_dma.h
  • DMA_CH3CNT : gd32f3x0_dma.h
  • DMA_CH3CTL : gd32f3x0_dma.h
  • DMA_CH3MADDR : gd32f3x0_dma.h
  • DMA_CH3PADDR : gd32f3x0_dma.h
  • DMA_CH4CNT : gd32f3x0_dma.h
  • DMA_CH4CTL : gd32f3x0_dma.h
  • DMA_CH4MADDR : gd32f3x0_dma.h
  • DMA_CH4PADDR : gd32f3x0_dma.h
  • DMA_CH5CNT : gd32f3x0_dma.h
  • DMA_CH5CTL : gd32f3x0_dma.h
  • DMA_CH5MADDR : gd32f3x0_dma.h
  • DMA_CH5PADDR : gd32f3x0_dma.h
  • DMA_CH6CNT : gd32f3x0_dma.h
  • DMA_CH6CTL : gd32f3x0_dma.h
  • DMA_CH6MADDR : gd32f3x0_dma.h
  • DMA_CH6PADDR : gd32f3x0_dma.h
  • DMA_CHANNEL_CNT_MASK : gd32f3x0_dma.h
  • DMA_CHCNT : gd32f3x0_dma.h
  • DMA_CHCNT_RESET_VALUE : gd32f3x0_dma.h
  • DMA_CHCTL : gd32f3x0_dma.h
  • DMA_CHCTL_RESET_VALUE : gd32f3x0_dma.h
  • DMA_CHINTF_RESET_VALUE : gd32f3x0_dma.h
  • DMA_CHMADDR : gd32f3x0_dma.h
  • DMA_CHMADDR_RESET_VALUE : gd32f3x0_dma.h
  • DMA_CHPADDR : gd32f3x0_dma.h
  • DMA_CHPADDR_RESET_VALUE : gd32f3x0_dma.h
  • DMA_CHXCNT_BASE : gd32f3x0_dma.h
  • DMA_CHXCNT_CNT : gd32f3x0_dma.h
  • DMA_CHXCTL_BASE : gd32f3x0_dma.h
  • DMA_CHXCTL_CHEN : gd32f3x0_dma.h
  • DMA_CHXCTL_CMEN : gd32f3x0_dma.h
  • DMA_CHXCTL_DIR : gd32f3x0_dma.h
  • DMA_CHXCTL_ERRIE : gd32f3x0_dma.h
  • DMA_CHXCTL_FTFIE : gd32f3x0_dma.h
  • DMA_CHXCTL_HTFIE : gd32f3x0_dma.h
  • DMA_CHXCTL_M2M : gd32f3x0_dma.h
  • DMA_CHXCTL_MNAGA : gd32f3x0_dma.h
  • DMA_CHXCTL_MWIDTH : gd32f3x0_dma.h
  • DMA_CHXCTL_PNAGA : gd32f3x0_dma.h
  • DMA_CHXCTL_PRIO : gd32f3x0_dma.h
  • DMA_CHXCTL_PWIDTH : gd32f3x0_dma.h
  • DMA_CHXMADDR_BASE : gd32f3x0_dma.h
  • DMA_CHXMADDR_MADDR : gd32f3x0_dma.h
  • DMA_CHXPADDR_BASE : gd32f3x0_dma.h
  • DMA_CHXPADDR_PADDR : gd32f3x0_dma.h
  • DMA_FLAG_ADD : gd32f3x0_dma.h
  • DMA_FLAG_ERR : gd32f3x0_dma.h
  • DMA_FLAG_FTF : gd32f3x0_dma.h
  • DMA_FLAG_G : gd32f3x0_dma.h
  • DMA_FLAG_HTF : gd32f3x0_dma.h
  • DMA_INCR0 : usb_regs.h
  • DMA_INCR1 : usb_regs.h
  • DMA_INCR16 : usb_regs.h
  • DMA_INCR4 : usb_regs.h
  • DMA_INCR8 : usb_regs.h
  • DMA_INT_ERR : gd32f3x0_dma.h
  • DMA_INT_FLAG_ERR : gd32f3x0_dma.h
  • DMA_INT_FLAG_FTF : gd32f3x0_dma.h
  • DMA_INT_FLAG_G : gd32f3x0_dma.h
  • DMA_INT_FLAG_HTF : gd32f3x0_dma.h
  • DMA_INT_FTF : gd32f3x0_dma.h
  • DMA_INT_HTF : gd32f3x0_dma.h
  • DMA_INTC : gd32f3x0_dma.h
  • DMA_INTC_ERRIFC : gd32f3x0_dma.h
  • DMA_INTC_FTFIFC : gd32f3x0_dma.h
  • DMA_INTC_GIFC : gd32f3x0_dma.h
  • DMA_INTC_HTFIFC : gd32f3x0_dma.h
  • DMA_INTF : gd32f3x0_dma.h
  • DMA_INTF_ERRIF : gd32f3x0_dma.h
  • DMA_INTF_FTFIF : gd32f3x0_dma.h
  • DMA_INTF_GIF : gd32f3x0_dma.h
  • DMA_INTF_HTFIF : gd32f3x0_dma.h
  • DMA_MEMORY_INCREASE_DISABLE : gd32f3x0_dma.h
  • DMA_MEMORY_INCREASE_ENABLE : gd32f3x0_dma.h
  • DMA_MEMORY_TO_PERIPHERAL : gd32f3x0_dma.h
  • DMA_MEMORY_WIDTH_16BIT : gd32f3x0_dma.h
  • DMA_MEMORY_WIDTH_32BIT : gd32f3x0_dma.h
  • DMA_MEMORY_WIDTH_8BIT : gd32f3x0_dma.h
  • DMA_PERIPH_INCREASE_DISABLE : gd32f3x0_dma.h
  • DMA_PERIPH_INCREASE_ENABLE : gd32f3x0_dma.h
  • DMA_PERIPHERAL_TO_MEMORY : gd32f3x0_dma.h
  • DMA_PERIPHERAL_WIDTH_16BIT : gd32f3x0_dma.h
  • DMA_PERIPHERAL_WIDTH_32BIT : gd32f3x0_dma.h
  • DMA_PERIPHERAL_WIDTH_8BIT : gd32f3x0_dma.h
  • DMA_PRIORITY_HIGH : gd32f3x0_dma.h
  • DMA_PRIORITY_LOW : gd32f3x0_dma.h
  • DMA_PRIORITY_MEDIUM : gd32f3x0_dma.h
  • DMA_PRIORITY_ULTRA_HIGH : gd32f3x0_dma.h
  • DMACFG_DMATA : gd32f3x0_timer.h
  • DMACFG_DMATC : gd32f3x0_timer.h
  • DOEP0LEN_PCNT : usb_regs.h
  • DOEP0LEN_STPCNT : usb_regs.h
  • DOEP0LEN_TLEN : usb_regs.h
  • DOEPINTEN_BTBSTPEN : usb_regs.h
  • DOEPINTEN_EPDISEN : usb_regs.h
  • DOEPINTEN_EPRXFOVREN : usb_regs.h
  • DOEPINTEN_STPFEN : usb_regs.h
  • DOEPINTEN_TFEN : usb_regs.h
  • DOEPINTF_BTBSTP : usb_regs.h
  • DOEPINTF_EPDIS : usb_regs.h
  • DOEPINTF_EPRXFOVR : usb_regs.h
  • DOEPINTF_STPF : usb_regs.h
  • DOEPINTF_TF : usb_regs.h
  • DOEPLEN_RXDPID : usb_regs.h
  • DOEPLEN_STPCNT : usb_regs.h
  • DPID_DATA0 : usb_defines.h
  • DPID_DATA1 : usb_defines.h
  • DPID_DATA2 : usb_defines.h
  • DPID_MDATA : usb_defines.h
  • DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ : usb_defines.h
  • DSTAT_ENUMSPD_FS_PHY_48MHZ : usb_defines.h
  • DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ : usb_defines.h
  • DSTAT_ENUMSPD_LS_PHY_6MHZ : usb_defines.h
  • DSTAT_ES : usb_regs.h
  • DSTAT_FNRSOF : usb_regs.h
  • DSTAT_SPST : usb_regs.h
  • DSV_DSLPVS : gd32f3x0_rcu.h
  • DTS_DAY : gd32f3x0_rtc.h
  • DTS_DOW : gd32f3x0_rtc.h
  • DTS_MON : gd32f3x0_rtc.h
  • DVBUSDT_DVBUSDT : usb_regs.h
  • DVBUSPT_DVBUSPT : usb_regs.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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- e -

  • ENG_LANGID : usbd_std.h
  • ENUM_FSM_ID : usbh_core.h
  • ENUM_HANDLE_TABLE_SIZE : usbh_std.h
  • EP0_IN : usb_regs.h
  • EP0_OUT : usb_regs.h
  • EP0MPL_16 : usb_regs.h
  • EP0MPL_32 : usb_regs.h
  • EP0MPL_64 : usb_regs.h
  • EP0MPL_8 : usb_regs.h
  • EP1_IN : usb_regs.h
  • EP1_OUT : usb_regs.h
  • EP2_IN : usb_regs.h
  • EP2_OUT : usb_regs.h
  • EP3_IN : usb_regs.h
  • EP3_OUT : usb_regs.h
  • EXTI : gd32f3x0_exti.h
  • EXTI_EVEN : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN0 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN1 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN10 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN11 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN12 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN13 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN14 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN15 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN16 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN17 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN18 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN19 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN2 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN20 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN21 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN22 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN23 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN24 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN25 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN26 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN27 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN3 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN4 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN5 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN6 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN7 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN8 : gd32f3x0_exti.h
  • EXTI_EVEN_EVEN9 : gd32f3x0_exti.h
  • EXTI_FTEN : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN0 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN1 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN10 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN11 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN12 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN13 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN14 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN15 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN16 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN17 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN18 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN19 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN2 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN21 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN22 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN3 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN4 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN5 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN6 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN7 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN8 : gd32f3x0_exti.h
  • EXTI_FTEN_FTEN9 : gd32f3x0_exti.h
  • EXTI_INTEN : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN0 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN1 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN10 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN11 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN12 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN13 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN14 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN15 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN16 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN17 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN18 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN19 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN2 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN20 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN21 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN22 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN23 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN24 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN25 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN26 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN27 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN3 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN4 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN5 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN6 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN7 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN8 : gd32f3x0_exti.h
  • EXTI_INTEN_INTEN9 : gd32f3x0_exti.h
  • EXTI_PD : gd32f3x0_exti.h
  • EXTI_PD_PD0 : gd32f3x0_exti.h
  • EXTI_PD_PD1 : gd32f3x0_exti.h
  • EXTI_PD_PD10 : gd32f3x0_exti.h
  • EXTI_PD_PD11 : gd32f3x0_exti.h
  • EXTI_PD_PD12 : gd32f3x0_exti.h
  • EXTI_PD_PD13 : gd32f3x0_exti.h
  • EXTI_PD_PD14 : gd32f3x0_exti.h
  • EXTI_PD_PD15 : gd32f3x0_exti.h
  • EXTI_PD_PD16 : gd32f3x0_exti.h
  • EXTI_PD_PD17 : gd32f3x0_exti.h
  • EXTI_PD_PD18 : gd32f3x0_exti.h
  • EXTI_PD_PD19 : gd32f3x0_exti.h
  • EXTI_PD_PD2 : gd32f3x0_exti.h
  • EXTI_PD_PD21 : gd32f3x0_exti.h
  • EXTI_PD_PD22 : gd32f3x0_exti.h
  • EXTI_PD_PD3 : gd32f3x0_exti.h
  • EXTI_PD_PD4 : gd32f3x0_exti.h
  • EXTI_PD_PD5 : gd32f3x0_exti.h
  • EXTI_PD_PD6 : gd32f3x0_exti.h
  • EXTI_PD_PD7 : gd32f3x0_exti.h
  • EXTI_PD_PD8 : gd32f3x0_exti.h
  • EXTI_PD_PD9 : gd32f3x0_exti.h
  • EXTI_RTEN : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN0 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN1 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN10 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN11 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN12 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN13 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN14 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN15 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN16 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN17 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN18 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN19 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN2 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN21 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN22 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN3 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN4 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN5 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN6 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN7 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN8 : gd32f3x0_exti.h
  • EXTI_RTEN_RTEN9 : gd32f3x0_exti.h
  • EXTI_SOURCE_GPIOA : gd32f3x0_syscfg.h
  • EXTI_SOURCE_GPIOB : gd32f3x0_syscfg.h
  • EXTI_SOURCE_GPIOC : gd32f3x0_syscfg.h
  • EXTI_SOURCE_GPIOD : gd32f3x0_syscfg.h
  • EXTI_SOURCE_GPIOF : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN0 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN1 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN10 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN11 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN12 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN13 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN14 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN15 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN2 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN3 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN4 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN5 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN6 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN7 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN8 : gd32f3x0_syscfg.h
  • EXTI_SOURCE_PIN9 : gd32f3x0_syscfg.h
  • EXTI_SS_JSTEP : gd32f3x0_syscfg.h
  • EXTI_SS_MASK : gd32f3x0_syscfg.h
  • EXTI_SS_MSTEP : gd32f3x0_syscfg.h
  • EXTI_SWIEV : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV0 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV1 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV10 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV11 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV12 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV13 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV14 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV15 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV16 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV17 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV18 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV19 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV2 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV21 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV22 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV3 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV4 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV5 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV6 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV7 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV8 : gd32f3x0_exti.h
  • EXTI_SWIEV_SWIEV9 : gd32f3x0_exti.h
  • EXTISS0 : gd32f3x0_syscfg.h
  • EXTISS1 : gd32f3x0_syscfg.h
  • EXTISS2 : gd32f3x0_syscfg.h
  • EXTISS3 : gd32f3x0_syscfg.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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- f -

  • FEATURE_SELECTOR_DEVICE : usbh_std.h
  • FEATURE_SELECTOR_ENDPOINT : usbh_std.h
  • FMC : gd32f3x0_fmc.h
  • FMC_ADDR : gd32f3x0_fmc.h
  • FMC_ADDR_ADDR : gd32f3x0_fmc.h
  • FMC_CTL : gd32f3x0_fmc.h
  • FMC_CTL_ENDIE : gd32f3x0_fmc.h
  • FMC_CTL_ERRIE : gd32f3x0_fmc.h
  • FMC_CTL_LK : gd32f3x0_fmc.h
  • FMC_CTL_MER : gd32f3x0_fmc.h
  • FMC_CTL_OBER : gd32f3x0_fmc.h
  • FMC_CTL_OBPG : gd32f3x0_fmc.h
  • FMC_CTL_OBRLD : gd32f3x0_fmc.h
  • FMC_CTL_OBWEN : gd32f3x0_fmc.h
  • FMC_CTL_PER : gd32f3x0_fmc.h
  • FMC_CTL_PG : gd32f3x0_fmc.h
  • FMC_CTL_START : gd32f3x0_fmc.h
  • FMC_FLAG_BUSY : gd32f3x0_fmc.h
  • FMC_FLAG_END : gd32f3x0_fmc.h
  • FMC_FLAG_PGERR : gd32f3x0_fmc.h
  • FMC_FLAG_WPERR : gd32f3x0_fmc.h
  • FMC_HSPC : gd32f3x0_fmc.h
  • FMC_INTEN_END : gd32f3x0_fmc.h
  • FMC_INTEN_ERR : gd32f3x0_fmc.h
  • FMC_KEY : gd32f3x0_fmc.h
  • FMC_KEY_KEY : gd32f3x0_fmc.h
  • FMC_LSPC : gd32f3x0_fmc.h
  • FMC_NSPC : gd32f3x0_fmc.h
  • FMC_OBKEY : gd32f3x0_fmc.h
  • FMC_OBKEY_OBKEY : gd32f3x0_fmc.h
  • FMC_OBSTAT : gd32f3x0_fmc.h
  • FMC_OBSTAT_DATA : gd32f3x0_fmc.h
  • FMC_OBSTAT_OBERR : gd32f3x0_fmc.h
  • FMC_OBSTAT_PLVL_BIT0 : gd32f3x0_fmc.h
  • FMC_OBSTAT_PLVL_BIT1 : gd32f3x0_fmc.h
  • FMC_OBSTAT_USER : gd32f3x0_fmc.h
  • FMC_PID : gd32f3x0_fmc.h
  • FMC_PID_PID : gd32f3x0_fmc.h
  • FMC_STAT : gd32f3x0_fmc.h
  • FMC_STAT_BUSY : gd32f3x0_fmc.h
  • FMC_STAT_ENDF : gd32f3x0_fmc.h
  • FMC_STAT_PGERR : gd32f3x0_fmc.h
  • FMC_STAT_WPERR : gd32f3x0_fmc.h
  • FMC_TIMEOUT_COUNT : gd32f3x0_fmc.h
  • FMC_WP : gd32f3x0_fmc.h
  • FMC_WS : gd32f3x0_fmc.h
  • FMC_WS_WSCNT : gd32f3x0_fmc.h
  • FMC_WSEN : gd32f3x0_fmc.h
  • FMC_WSEN_BPEN : gd32f3x0_fmc.h
  • FMC_WSEN_WSEN : gd32f3x0_fmc.h
  • FRAME_INTERVAL_80 : usb_regs.h
  • FRAME_INTERVAL_85 : usb_regs.h
  • FRAME_INTERVAL_90 : usb_regs.h
  • FRAME_INTERVAL_95 : usb_regs.h
  • FWDGT : gd32f3x0_fwdgt.h
  • FWDGT_CTL : gd32f3x0_fwdgt.h
  • FWDGT_CTL_CMD : gd32f3x0_fwdgt.h
  • FWDGT_FLAG_PUD : gd32f3x0_fwdgt.h
  • FWDGT_FLAG_RUD : gd32f3x0_fwdgt.h
  • FWDGT_FLAG_WUD : gd32f3x0_fwdgt.h
  • FWDGT_KEY_ENABLE : gd32f3x0_fwdgt.h
  • FWDGT_KEY_RELOAD : gd32f3x0_fwdgt.h
  • FWDGT_PSC : gd32f3x0_fwdgt.h
  • FWDGT_PSC_DIV128 : gd32f3x0_fwdgt.h
  • FWDGT_PSC_DIV16 : gd32f3x0_fwdgt.h
  • FWDGT_PSC_DIV256 : gd32f3x0_fwdgt.h
  • FWDGT_PSC_DIV32 : gd32f3x0_fwdgt.h
  • FWDGT_PSC_DIV4 : gd32f3x0_fwdgt.h
  • FWDGT_PSC_DIV64 : gd32f3x0_fwdgt.h
  • FWDGT_PSC_DIV8 : gd32f3x0_fwdgt.h
  • FWDGT_PSC_PSC : gd32f3x0_fwdgt.h
  • FWDGT_PSC_TIMEOUT : gd32f3x0_fwdgt.h
  • FWDGT_RLD : gd32f3x0_fwdgt.h
  • FWDGT_RLD_RLD : gd32f3x0_fwdgt.h
  • FWDGT_RLD_TIMEOUT : gd32f3x0_fwdgt.h
  • FWDGT_STAT : gd32f3x0_fwdgt.h
  • FWDGT_STAT_PUD : gd32f3x0_fwdgt.h
  • FWDGT_STAT_RUD : gd32f3x0_fwdgt.h
  • FWDGT_STAT_WUD : gd32f3x0_fwdgt.h
  • FWDGT_WND : gd32f3x0_fwdgt.h
  • FWDGT_WND_TIMEOUT : gd32f3x0_fwdgt.h
  • FWDGT_WND_WND : gd32f3x0_fwdgt.h
  • FWDGT_WRITEACCESS_DISABLE : gd32f3x0_fwdgt.h
  • FWDGT_WRITEACCESS_ENABLE : gd32f3x0_fwdgt.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • _
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  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • w

- g -

  • GAHBCS_DMAINCR : usb_regs.h
  • GAHBCS_GINTEN : usb_regs.h
  • GAHBCS_PTXFTH : usb_regs.h
  • GAHBCS_TFEL : usb_regs.h
  • GAHBCS_TXFTH : usb_regs.h
  • GCCFG_PWRON : usb_regs.h
  • GCCFG_SOFOEN : usb_regs.h
  • GCCFG_VBUSACEN : usb_regs.h
  • GCCFG_VBUSBCEN : usb_regs.h
  • GCCFG_VBUSIG : usb_regs.h
  • GET_ALRM0TD_DAY : gd32f3x0_rtc.h
  • GET_ALRM0TD_HR : gd32f3x0_rtc.h
  • GET_ALRM0TD_MN : gd32f3x0_rtc.h
  • GET_ALRM0TD_SC : gd32f3x0_rtc.h
  • GET_CTL0_TRIMVALUE : gd32f3x0_ctc.h
  • GET_DATE_DAY : gd32f3x0_rtc.h
  • GET_DATE_DOW : gd32f3x0_rtc.h
  • GET_DATE_MON : gd32f3x0_rtc.h
  • GET_DATE_YR : gd32f3x0_rtc.h
  • GET_DTS_DAY : gd32f3x0_rtc.h
  • GET_DTS_DOW : gd32f3x0_rtc.h
  • GET_DTS_MON : gd32f3x0_rtc.h
  • GET_PSC_FACTOR_A : gd32f3x0_rtc.h
  • GET_PSC_FACTOR_S : gd32f3x0_rtc.h
  • GET_STAT_REFCAP : gd32f3x0_ctc.h
  • GET_TIME_HR : gd32f3x0_rtc.h
  • GET_TIME_MN : gd32f3x0_rtc.h
  • GET_TIME_SC : gd32f3x0_rtc.h
  • GET_TTS_HR : gd32f3x0_rtc.h
  • GET_TTS_MN : gd32f3x0_rtc.h
  • GET_TTS_SC : gd32f3x0_rtc.h
  • GINTEN_DISCIE : usb_regs.h
  • GINTEN_ENUMFIE : usb_regs.h
  • GINTEN_EOPFIE : usb_regs.h
  • GINTEN_ESPIE : usb_regs.h
  • GINTEN_GNPINAKIE : usb_regs.h
  • GINTEN_GONAKIE : usb_regs.h
  • GINTEN_HCIE : usb_regs.h
  • GINTEN_HPIE : usb_regs.h
  • GINTEN_IDPSCIE : usb_regs.h
  • GINTEN_IEPIE : usb_regs.h
  • GINTEN_ISOINCIE : usb_regs.h
  • GINTEN_ISOONCIE : usb_regs.h
  • GINTEN_ISOOPDIE : usb_regs.h
  • GINTEN_MFIE : usb_regs.h
  • GINTEN_NPTXFEIE : usb_regs.h
  • GINTEN_OEPIE : usb_regs.h
  • GINTEN_OTGIE : usb_regs.h
  • GINTEN_PTXFEIE : usb_regs.h
  • GINTEN_PXNCIE : usb_regs.h
  • GINTEN_RSTIE : usb_regs.h
  • GINTEN_RXFNEIE : usb_regs.h
  • GINTEN_SESIE : usb_regs.h
  • GINTEN_SOFIE : usb_regs.h
  • GINTEN_SPIE : usb_regs.h
  • GINTEN_WKUPIE : usb_regs.h
  • GINTF_COPM : usb_regs.h
  • GINTF_DISCIF : usb_regs.h
  • GINTF_ENUMF : usb_regs.h
  • GINTF_EOPFIF : usb_regs.h
  • GINTF_ESP : usb_regs.h
  • GINTF_GNPINAK : usb_regs.h
  • GINTF_GONAK : usb_regs.h
  • GINTF_HCIF : usb_regs.h
  • GINTF_HPIF : usb_regs.h
  • GINTF_IDPSC : usb_regs.h
  • GINTF_IEPIF : usb_regs.h
  • GINTF_ISOINCIF : usb_regs.h
  • GINTF_ISOONCIF : usb_regs.h
  • GINTF_ISOOPDIF : usb_regs.h
  • GINTF_MFIF : usb_regs.h
  • GINTF_NPTXFEIF : usb_regs.h
  • GINTF_OEPIF : usb_regs.h
  • GINTF_OTGIF : usb_regs.h
  • GINTF_PTXFEIF : usb_regs.h
  • GINTF_PXNCIF : usb_regs.h
  • GINTF_RST : usb_regs.h
  • GINTF_RXFNEIF : usb_regs.h
  • GINTF_SESIF : usb_regs.h
  • GINTF_SOF : usb_regs.h
  • GINTF_SP : usb_regs.h
  • GINTF_WKUPIF : usb_regs.h
  • GO_TO_UP_STATE_EVENT : usbh_core.h
  • GOTGCS_ASV : usb_regs.h
  • GOTGCS_BSV : usb_regs.h
  • GOTGCS_DHNPEN : usb_regs.h
  • GOTGCS_DI : usb_regs.h
  • GOTGCS_HHNPEN : usb_regs.h
  • GOTGCS_HNPREQ : usb_regs.h
  • GOTGCS_HNPS : usb_regs.h
  • GOTGCS_IDPS : usb_regs.h
  • GOTGCS_SRPREQ : usb_regs.h
  • GOTGCS_SRPS : usb_regs.h
  • GOTGINTF_ADTO : usb_regs.h
  • GOTGINTF_DF : usb_regs.h
  • GOTGINTF_HNPDET : usb_regs.h
  • GOTGINTF_HNPEND : usb_regs.h
  • GOTGINTF_SESEND : usb_regs.h
  • GOTGINTF_SRPEND : usb_regs.h
  • GPIO_AF_0 : gd32f3x0_gpio.h
  • GPIO_AF_1 : gd32f3x0_gpio.h
  • GPIO_AF_2 : gd32f3x0_gpio.h
  • GPIO_AF_3 : gd32f3x0_gpio.h
  • GPIO_AF_4 : gd32f3x0_gpio.h
  • GPIO_AF_5 : gd32f3x0_gpio.h
  • GPIO_AF_6 : gd32f3x0_gpio.h
  • GPIO_AF_7 : gd32f3x0_gpio.h
  • GPIO_AFR_MASK : gd32f3x0_gpio.h
  • GPIO_AFR_SET : gd32f3x0_gpio.h
  • GPIO_AFSEL0 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL0 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL1 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL2 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL3 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL4 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL5 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL6 : gd32f3x0_gpio.h
  • GPIO_AFSEL0_SEL7 : gd32f3x0_gpio.h
  • GPIO_AFSEL1 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL10 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL11 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL12 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL13 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL14 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL15 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL8 : gd32f3x0_gpio.h
  • GPIO_AFSEL1_SEL9 : gd32f3x0_gpio.h
  • GPIO_BC : gd32f3x0_gpio.h
  • GPIO_BC_CR0 : gd32f3x0_gpio.h
  • GPIO_BC_CR1 : gd32f3x0_gpio.h
  • GPIO_BC_CR10 : gd32f3x0_gpio.h
  • GPIO_BC_CR11 : gd32f3x0_gpio.h
  • GPIO_BC_CR12 : gd32f3x0_gpio.h
  • GPIO_BC_CR13 : gd32f3x0_gpio.h
  • GPIO_BC_CR14 : gd32f3x0_gpio.h
  • GPIO_BC_CR15 : gd32f3x0_gpio.h
  • GPIO_BC_CR2 : gd32f3x0_gpio.h
  • GPIO_BC_CR3 : gd32f3x0_gpio.h
  • GPIO_BC_CR4 : gd32f3x0_gpio.h
  • GPIO_BC_CR5 : gd32f3x0_gpio.h
  • GPIO_BC_CR6 : gd32f3x0_gpio.h
  • GPIO_BC_CR7 : gd32f3x0_gpio.h
  • GPIO_BC_CR8 : gd32f3x0_gpio.h
  • GPIO_BC_CR9 : gd32f3x0_gpio.h
  • GPIO_BOP : gd32f3x0_gpio.h
  • GPIO_BOP_BOP0 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP1 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP10 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP11 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP12 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP13 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP14 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP15 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP2 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP3 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP4 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP5 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP6 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP7 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP8 : gd32f3x0_gpio.h
  • GPIO_BOP_BOP9 : gd32f3x0_gpio.h
  • GPIO_BOP_CR0 : gd32f3x0_gpio.h
  • GPIO_BOP_CR1 : gd32f3x0_gpio.h
  • GPIO_BOP_CR10 : gd32f3x0_gpio.h
  • GPIO_BOP_CR11 : gd32f3x0_gpio.h
  • GPIO_BOP_CR12 : gd32f3x0_gpio.h
  • GPIO_BOP_CR13 : gd32f3x0_gpio.h
  • GPIO_BOP_CR14 : gd32f3x0_gpio.h
  • GPIO_BOP_CR15 : gd32f3x0_gpio.h
  • GPIO_BOP_CR2 : gd32f3x0_gpio.h
  • GPIO_BOP_CR3 : gd32f3x0_gpio.h
  • GPIO_BOP_CR4 : gd32f3x0_gpio.h
  • GPIO_BOP_CR5 : gd32f3x0_gpio.h
  • GPIO_BOP_CR6 : gd32f3x0_gpio.h
  • GPIO_BOP_CR7 : gd32f3x0_gpio.h
  • GPIO_BOP_CR8 : gd32f3x0_gpio.h
  • GPIO_BOP_CR9 : gd32f3x0_gpio.h
  • GPIO_CTL : gd32f3x0_gpio.h
  • GPIO_CTL_CTL0 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL1 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL10 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL11 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL12 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL13 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL14 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL15 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL2 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL3 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL4 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL5 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL6 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL7 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL8 : gd32f3x0_gpio.h
  • GPIO_CTL_CTL9 : gd32f3x0_gpio.h
  • GPIO_ISTAT : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT0 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT1 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT10 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT11 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT12 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT13 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT14 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT15 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT2 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT3 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT4 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT5 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT6 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT7 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT8 : gd32f3x0_gpio.h
  • GPIO_ISTAT_ISTAT9 : gd32f3x0_gpio.h
  • GPIO_LOCK : gd32f3x0_gpio.h
  • GPIO_LOCK_LK0 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK1 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK10 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK11 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK12 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK13 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK14 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK15 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK2 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK3 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK4 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK5 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK6 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK7 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK8 : gd32f3x0_gpio.h
  • GPIO_LOCK_LK9 : gd32f3x0_gpio.h
  • GPIO_LOCK_LKK : gd32f3x0_gpio.h
  • GPIO_MODE_AF : gd32f3x0_gpio.h
  • GPIO_MODE_ANALOG : gd32f3x0_gpio.h
  • GPIO_MODE_INPUT : gd32f3x0_gpio.h
  • GPIO_MODE_MASK : gd32f3x0_gpio.h
  • GPIO_MODE_OUTPUT : gd32f3x0_gpio.h
  • GPIO_MODE_SET : gd32f3x0_gpio.h
  • GPIO_OCTL : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL0 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL1 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL10 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL11 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL12 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL13 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL14 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL15 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL2 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL3 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL4 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL5 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL6 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL7 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL8 : gd32f3x0_gpio.h
  • GPIO_OCTL_OCTL9 : gd32f3x0_gpio.h
  • GPIO_OMODE : gd32f3x0_gpio.h
  • GPIO_OMODE_OM0 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM1 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM10 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM11 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM12 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM13 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM14 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM15 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM2 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM3 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM4 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM5 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM6 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM7 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM8 : gd32f3x0_gpio.h
  • GPIO_OMODE_OM9 : gd32f3x0_gpio.h
  • GPIO_OSPD0 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD0 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD1 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD10 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD11 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD12 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD13 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD14 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD15 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD2 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD3 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD4 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD5 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD6 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD7 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD8 : gd32f3x0_gpio.h
  • GPIO_OSPD0_OSPD9 : gd32f3x0_gpio.h
  • GPIO_OSPD1 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD0 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD1 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD10 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD11 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD12 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD13 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD14 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD15 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD2 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD3 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD4 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD5 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD6 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD7 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD8 : gd32f3x0_gpio.h
  • GPIO_OSPD1_SPD9 : gd32f3x0_gpio.h
  • GPIO_OSPEED_10MHZ : gd32f3x0_gpio.h
  • GPIO_OSPEED_2MHZ : gd32f3x0_gpio.h
  • GPIO_OSPEED_50MHZ : gd32f3x0_gpio.h
  • GPIO_OSPEED_MASK : gd32f3x0_gpio.h
  • GPIO_OSPEED_MAX : gd32f3x0_gpio.h
  • GPIO_OSPEED_SET : gd32f3x0_gpio.h
  • GPIO_OTYPE_OD : gd32f3x0_gpio.h
  • GPIO_OTYPE_PP : gd32f3x0_gpio.h
  • GPIO_PIN_0 : gd32f3x0_gpio.h
  • GPIO_PIN_1 : gd32f3x0_gpio.h
  • GPIO_PIN_10 : gd32f3x0_gpio.h
  • GPIO_PIN_11 : gd32f3x0_gpio.h
  • GPIO_PIN_12 : gd32f3x0_gpio.h
  • GPIO_PIN_13 : gd32f3x0_gpio.h
  • GPIO_PIN_14 : gd32f3x0_gpio.h
  • GPIO_PIN_15 : gd32f3x0_gpio.h
  • GPIO_PIN_2 : gd32f3x0_gpio.h
  • GPIO_PIN_3 : gd32f3x0_gpio.h
  • GPIO_PIN_4 : gd32f3x0_gpio.h
  • GPIO_PIN_5 : gd32f3x0_gpio.h
  • GPIO_PIN_6 : gd32f3x0_gpio.h
  • GPIO_PIN_7 : gd32f3x0_gpio.h
  • GPIO_PIN_8 : gd32f3x0_gpio.h
  • GPIO_PIN_9 : gd32f3x0_gpio.h
  • GPIO_PIN_ALL : gd32f3x0_gpio.h
  • GPIO_PUD : gd32f3x0_gpio.h
  • GPIO_PUD_PUD0 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD1 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD10 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD11 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD12 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD13 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD14 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD15 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD2 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD3 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD4 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD5 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD6 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD7 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD8 : gd32f3x0_gpio.h
  • GPIO_PUD_PUD9 : gd32f3x0_gpio.h
  • GPIO_PUPD_MASK : gd32f3x0_gpio.h
  • GPIO_PUPD_NONE : gd32f3x0_gpio.h
  • GPIO_PUPD_PULLDOWN : gd32f3x0_gpio.h
  • GPIO_PUPD_PULLUP : gd32f3x0_gpio.h
  • GPIO_PUPD_SET : gd32f3x0_gpio.h
  • GPIO_TG : gd32f3x0_gpio.h
  • GPIO_TG_TG0 : gd32f3x0_gpio.h
  • GPIO_TG_TG1 : gd32f3x0_gpio.h
  • GPIO_TG_TG10 : gd32f3x0_gpio.h
  • GPIO_TG_TG11 : gd32f3x0_gpio.h
  • GPIO_TG_TG12 : gd32f3x0_gpio.h
  • GPIO_TG_TG13 : gd32f3x0_gpio.h
  • GPIO_TG_TG14 : gd32f3x0_gpio.h
  • GPIO_TG_TG15 : gd32f3x0_gpio.h
  • GPIO_TG_TG2 : gd32f3x0_gpio.h
  • GPIO_TG_TG3 : gd32f3x0_gpio.h
  • GPIO_TG_TG4 : gd32f3x0_gpio.h
  • GPIO_TG_TG5 : gd32f3x0_gpio.h
  • GPIO_TG_TG6 : gd32f3x0_gpio.h
  • GPIO_TG_TG7 : gd32f3x0_gpio.h
  • GPIO_TG_TG8 : gd32f3x0_gpio.h
  • GPIO_TG_TG9 : gd32f3x0_gpio.h
  • GPIOA : gd32f3x0_gpio.h
  • GPIOB : gd32f3x0_gpio.h
  • GPIOC : gd32f3x0_gpio.h
  • GPIOD : gd32f3x0_gpio.h
  • GPIOF : gd32f3x0_gpio.h
  • GRFLEN_RXFD : usb_regs.h
  • GRSTATR_RPCKST_CH_HALTED : usb_defines.h
  • GRSTATR_RPCKST_DATA_TOGGLE_ERR : usb_defines.h
  • GRSTATR_RPCKST_IN : usb_defines.h
  • GRSTATR_RPCKST_IN_XFER_COMP : usb_defines.h
  • GRSTATRP_BCOUNT : usb_regs.h
  • GRSTATRP_CNUM : usb_regs.h
  • GRSTATRP_DPID : usb_regs.h
  • GRSTATRP_EPNUM : usb_regs.h
  • GRSTATRP_RPCKST : usb_regs.h
  • GRSTCTL_CSRST : usb_regs.h
  • GRSTCTL_HCSRST : usb_regs.h
  • GRSTCTL_HFCRST : usb_regs.h
  • GRSTCTL_RXFF : usb_regs.h
  • GRSTCTL_TXFF : usb_regs.h
  • GRSTCTL_TXFNUM : usb_regs.h
  • GUSBCS_FDM : usb_regs.h
  • GUSBCS_FHM : usb_regs.h
  • GUSBCS_HNPCEN : usb_regs.h
  • GUSBCS_SRPCEN : usb_regs.h
  • GUSBCS_TOC : usb_regs.h
  • GUSBCS_UTT : usb_regs.h


GD32F3x0_Firmware_Library: Globals

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- h -

  • HACHINT_HACHINT : usb_regs.h
  • HACHINTEN_CINTEN : usb_regs.h
  • HC_ERROR : usbh_hcs.h
  • HC_MAX : usbh_hcs.h
  • HC_MAX_PACKET_COUNT : usb_core.h
  • HC_OK : usbh_hcs.h
  • HC_PID_DATA0 : usb_defines.h
  • HC_PID_DATA1 : usb_defines.h
  • HC_PID_DATA2 : usb_defines.h
  • HC_PID_SETUP : usb_defines.h
  • HC_USED : usbh_hcs.h
  • HC_USED_MASK : usbh_hcs.h
  • HCCHAR_BULK : usb_defines.h
  • HCCHAR_CTRL : usb_defines.h
  • HCCHAR_INTR : usb_defines.h
  • HCCHAR_ISOC : usb_defines.h
  • HCHCTL_CDIS : usb_regs.h
  • HCHCTL_CEN : usb_regs.h
  • HCHCTL_DAR : usb_regs.h
  • HCHCTL_EPDIR : usb_regs.h
  • HCHCTL_EPNUM : usb_regs.h
  • HCHCTL_EPTYPE : usb_regs.h
  • HCHCTL_LSD : usb_regs.h
  • HCHCTL_MPC : usb_regs.h
  • HCHCTL_MPL : usb_regs.h
  • HCHCTL_ODDFRM : usb_regs.h
  • HCHINTEN_ACKIE : usb_regs.h
  • HCHINTEN_BBERIE : usb_regs.h
  • HCHINTEN_CHIE : usb_regs.h
  • HCHINTEN_DTERIE : usb_regs.h
  • HCHINTEN_NAKIE : usb_regs.h
  • HCHINTEN_NYETIE : usb_regs.h
  • HCHINTEN_REQOVRIE : usb_regs.h
  • HCHINTEN_STALLIE : usb_regs.h
  • HCHINTEN_TFIE : usb_regs.h
  • HCHINTEN_USBERIE : usb_regs.h
  • HCHINTF_ACK : usb_regs.h
  • HCHINTF_BBER : usb_regs.h
  • HCHINTF_CH : usb_regs.h
  • HCHINTF_DTER : usb_regs.h
  • HCHINTF_NAK : usb_regs.h
  • HCHINTF_NYET : usb_regs.h
  • HCHINTF_REQOVR : usb_regs.h
  • HCHINTF_STALL : usb_regs.h
  • HCHINTF_TF : usb_regs.h
  • HCHINTF_USBER : usb_regs.h
  • HCHLEN_DPID : usb_regs.h
  • HCHLEN_PCNT : usb_regs.h
  • HCHLEN_TLEN : usb_regs.h
  • HCTL_CLKSEL : usb_regs.h
  • HCTLR_30_60_MHZ : usb_defines.h
  • HCTLR_48_MHZ : usb_defines.h
  • HCTLR_6_MHZ : usb_defines.h
  • HFINFR_FRNUM : usb_regs.h
  • HFINFR_FRT : usb_regs.h
  • HFT_FRI : usb_regs.h
  • HID_BOOT_CODE : usb_std.h
  • HID_CLASS : usbh_core.h
  • HID_KEYBRD_BOOT_CODE : usb_std.h
  • HID_MOUSE_BOOT_CODE : usb_std.h
  • HIGHBYTE : usbd_std.h
  • HNPTFLEN_HNPTXFD : usb_regs.h
  • HNPTFLEN_HNPTXRSAR : usb_regs.h
  • HNPTFQSTAT_CNUM : usb_regs.h
  • HNPTFQSTAT_EPNUM : usb_regs.h
  • HNPTFQSTAT_NPTXFS : usb_regs.h
  • HNPTFQSTAT_NPTXRQS : usb_regs.h
  • HNPTFQSTAT_NPTXRQTOP : usb_regs.h
  • HNPTFQSTAT_TMF : usb_regs.h
  • HNPTFQSTAT_TYPE : usb_regs.h
  • HOST_FSM_ID : usbh_core.h
  • HOST_HANDLE_TABLE_SIZE : usbh_core.h
  • HOST_MODE : usb_defines.h
  • HOST_USER_CLASS_ACTIVE : usbh_core.h
  • HOST_USER_CLASS_SELECTED : usbh_core.h
  • HOST_USER_CONNECTION : usbh_core.h
  • HOST_USER_DISCONNECTION : usbh_core.h
  • HOST_USER_SELECT_CONFIGURATION : usbh_core.h
  • HOST_USER_UNRECOVERED_ERROR : usbh_core.h
  • HPCS_PCD : usb_regs.h
  • HPCS_PCST : usb_regs.h
  • HPCS_PE : usb_regs.h
  • HPCS_PEDC : usb_regs.h
  • HPCS_PLST : usb_regs.h
  • HPCS_PP : usb_regs.h
  • HPCS_PREM : usb_regs.h
  • HPCS_PRST : usb_regs.h
  • HPCS_PS : usb_regs.h
  • HPCS_PSP : usb_regs.h
  • HPRT_PRTSPD_FULL_SPEED : usb_defines.h
  • HPRT_PRTSPD_HIGH_SPEED : usb_defines.h
  • HPRT_PRTSPD_LOW_SPEED : usb_defines.h
  • HPTFLEN_HPTXFD : usb_regs.h
  • HPTFLEN_HPTXFSAR : usb_regs.h
  • HPTFQSTAT_CNUM : usb_regs.h
  • HPTFQSTAT_EPNUM : usb_regs.h
  • HPTFQSTAT_OEFRM : usb_regs.h
  • HPTFQSTAT_PTXFS : usb_regs.h
  • HPTFQSTAT_PTXREQS : usb_regs.h
  • HPTFQSTAT_PTXREQT : usb_regs.h
  • HPTFQSTAT_TMF : usb_regs.h
  • HPTFQSTAT_TYPE : usb_regs.h
  • HRFC_CMSK : gd32f3x0_rtc.h


GD32F3x0_Firmware_Library: Globals

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- i -

  • I2C0 : gd32f3x0_i2c.h
  • I2C1 : gd32f3x0_i2c.h
  • I2C2 : gd32f3x0_i2c.h
  • I2C_ACK_DISABLE : gd32f3x0_i2c.h
  • I2C_ACK_ENABLE : gd32f3x0_i2c.h
  • I2C_ACKPOS_CURRENT : gd32f3x0_i2c.h
  • I2C_ACKPOS_NEXT : gd32f3x0_i2c.h
  • I2C_ADDFORMAT_10BITS : gd32f3x0_i2c.h
  • I2C_ADDFORMAT_7BITS : gd32f3x0_i2c.h
  • I2C_ARP_DISABLE : gd32f3x0_i2c.h
  • I2C_ARP_ENABLE : gd32f3x0_i2c.h
  • I2C_CKCFG : gd32f3x0_i2c.h
  • I2C_CKCFG_CLKC : gd32f3x0_i2c.h
  • I2C_CKCFG_DTCY : gd32f3x0_i2c.h
  • I2C_CKCFG_FAST : gd32f3x0_i2c.h
  • I2C_CTL0 : gd32f3x0_i2c.h
  • I2C_CTL0_ACKEN : gd32f3x0_i2c.h
  • I2C_CTL0_ARPEN : gd32f3x0_i2c.h
  • I2C_CTL0_DISSTRC : gd32f3x0_i2c.h
  • I2C_CTL0_GCEN : gd32f3x0_i2c.h
  • I2C_CTL0_I2CEN : gd32f3x0_i2c.h
  • I2C_CTL0_PECEN : gd32f3x0_i2c.h
  • I2C_CTL0_PECTRANS : gd32f3x0_i2c.h
  • I2C_CTL0_POAP : gd32f3x0_i2c.h
  • I2C_CTL0_SALT : gd32f3x0_i2c.h
  • I2C_CTL0_SMBEN : gd32f3x0_i2c.h
  • I2C_CTL0_SMBSEL : gd32f3x0_i2c.h
  • I2C_CTL0_SRESET : gd32f3x0_i2c.h
  • I2C_CTL0_START : gd32f3x0_i2c.h
  • I2C_CTL0_STOP : gd32f3x0_i2c.h
  • I2C_CTL1 : gd32f3x0_i2c.h
  • I2C_CTL1_BUFIE : gd32f3x0_i2c.h
  • I2C_CTL1_DMALST : gd32f3x0_i2c.h
  • I2C_CTL1_DMAON : gd32f3x0_i2c.h
  • I2C_CTL1_ERRIE : gd32f3x0_i2c.h
  • I2C_CTL1_EVIE : gd32f3x0_i2c.h
  • I2C_CTL1_I2CCLK : gd32f3x0_i2c.h
  • I2C_DATA : gd32f3x0_i2c.h
  • I2C_DATA_TRB : gd32f3x0_i2c.h
  • I2C_DMA_OFF : gd32f3x0_i2c.h
  • I2C_DMA_ON : gd32f3x0_i2c.h
  • I2C_DMALST_OFF : gd32f3x0_i2c.h
  • I2C_DMALST_ON : gd32f3x0_i2c.h
  • I2C_DTCY_16_9 : gd32f3x0_i2c.h
  • I2C_DTCY_2 : gd32f3x0_i2c.h
  • I2C_DUADEN_DISABLE : gd32f3x0_i2c.h
  • I2C_DUADEN_ENABLE : gd32f3x0_i2c.h
  • I2C_FAST_MODE_PLUS_DISABLE : gd32f3x0_i2c.h
  • I2C_FAST_MODE_PLUS_ENABLE : gd32f3x0_i2c.h
  • I2C_FLAG_ADD10SEND : gd32f3x0_i2c.h
  • I2C_FLAG_ADDSEND : gd32f3x0_i2c.h
  • I2C_FLAG_AERR : gd32f3x0_i2c.h
  • I2C_FLAG_BERR : gd32f3x0_i2c.h
  • I2C_FLAG_BTC : gd32f3x0_i2c.h
  • I2C_FLAG_DEFSMB : gd32f3x0_i2c.h
  • I2C_FLAG_DUMOD : gd32f3x0_i2c.h
  • I2C_FLAG_HSTSMB : gd32f3x0_i2c.h
  • I2C_FLAG_I2CBSY : gd32f3x0_i2c.h
  • I2C_FLAG_LOSTARB : gd32f3x0_i2c.h
  • I2C_FLAG_MASK : gd32f3x0_i2c.c
  • I2C_FLAG_MASTER : gd32f3x0_i2c.h
  • I2C_FLAG_OUERR : gd32f3x0_i2c.h
  • I2C_FLAG_PECERR : gd32f3x0_i2c.h
  • I2C_FLAG_RBNE : gd32f3x0_i2c.h
  • I2C_FLAG_RXGC : gd32f3x0_i2c.h
  • I2C_FLAG_SBSEND : gd32f3x0_i2c.h
  • I2C_FLAG_SMBALT : gd32f3x0_i2c.h
  • I2C_FLAG_SMBTO : gd32f3x0_i2c.h
  • I2C_FLAG_STPDET : gd32f3x0_i2c.h
  • I2C_FLAG_TBE : gd32f3x0_i2c.h
  • I2C_FLAG_TRS : gd32f3x0_i2c.h
  • I2C_FMPCFG : gd32f3x0_i2c.h
  • I2C_FMPCFG_FMPEN : gd32f3x0_i2c.h
  • I2C_GCEN_DISABLE : gd32f3x0_i2c.h
  • I2C_GCEN_ENABLE : gd32f3x0_i2c.h
  • I2C_I2CMODE_ENABLE : gd32f3x0_i2c.h
  • I2C_INT_BUF : gd32f3x0_i2c.h
  • I2C_INT_ERR : gd32f3x0_i2c.h
  • I2C_INT_EV : gd32f3x0_i2c.h
  • I2C_INT_FLAG_ADD10SEND : gd32f3x0_i2c.h
  • I2C_INT_FLAG_ADDSEND : gd32f3x0_i2c.h
  • I2C_INT_FLAG_AERR : gd32f3x0_i2c.h
  • I2C_INT_FLAG_BERR : gd32f3x0_i2c.h
  • I2C_INT_FLAG_BTC : gd32f3x0_i2c.h
  • I2C_INT_FLAG_LOSTARB : gd32f3x0_i2c.h
  • I2C_INT_FLAG_OUERR : gd32f3x0_i2c.h
  • I2C_INT_FLAG_PECERR : gd32f3x0_i2c.h
  • I2C_INT_FLAG_RBNE : gd32f3x0_i2c.h
  • I2C_INT_FLAG_SBSEND : gd32f3x0_i2c.h
  • I2C_INT_FLAG_SMBALT : gd32f3x0_i2c.h
  • I2C_INT_FLAG_SMBTO : gd32f3x0_i2c.h
  • I2C_INT_FLAG_STPDET : gd32f3x0_i2c.h
  • I2C_INT_FLAG_TBE : gd32f3x0_i2c.h
  • I2C_PEC_DISABLE : gd32f3x0_i2c.h
  • I2C_PEC_ENABLE : gd32f3x0_i2c.h
  • I2C_PECTRANS_DISABLE : gd32f3x0_i2c.h
  • I2C_PECTRANS_ENABLE : gd32f3x0_i2c.h
  • I2C_RECEIVER : gd32f3x0_i2c.h
  • I2C_RT : gd32f3x0_i2c.h
  • I2C_RT_RISETIME : gd32f3x0_i2c.h
  • I2C_SADDR0 : gd32f3x0_i2c.h
  • I2C_SADDR0_ADDFORMAT : gd32f3x0_i2c.h
  • I2C_SADDR0_ADDRESS : gd32f3x0_i2c.h
  • I2C_SADDR0_ADDRESS0 : gd32f3x0_i2c.h
  • I2C_SADDR0_ADDRESS_H : gd32f3x0_i2c.h
  • I2C_SADDR1 : gd32f3x0_i2c.h
  • I2C_SADDR1_ADDRESS2 : gd32f3x0_i2c.h
  • I2C_SADDR1_DUADEN : gd32f3x0_i2c.h
  • I2C_SALTSEND_DISABLE : gd32f3x0_i2c.h
  • I2C_SALTSEND_ENABLE : gd32f3x0_i2c.h
  • I2C_SCLSTRETCH_DISABLE : gd32f3x0_i2c.h
  • I2C_SCLSTRETCH_ENABLE : gd32f3x0_i2c.h
  • I2C_SMBUS_DEVICE : gd32f3x0_i2c.h
  • I2C_SMBUS_HOST : gd32f3x0_i2c.h
  • I2C_SMBUSMODE_ENABLE : gd32f3x0_i2c.h
  • I2C_SRESET_RESET : gd32f3x0_i2c.h
  • I2C_SRESET_SET : gd32f3x0_i2c.h
  • I2C_STAT0 : gd32f3x0_i2c.h
  • I2C_STAT0_ADD10SEND : gd32f3x0_i2c.h
  • I2C_STAT0_ADDSEND : gd32f3x0_i2c.h
  • I2C_STAT0_AERR : gd32f3x0_i2c.h
  • I2C_STAT0_BERR : gd32f3x0_i2c.h
  • I2C_STAT0_BTC : gd32f3x0_i2c.h
  • I2C_STAT0_LOSTARB : gd32f3x0_i2c.h
  • I2C_STAT0_OUERR : gd32f3x0_i2c.h
  • I2C_STAT0_PECERR : gd32f3x0_i2c.h
  • I2C_STAT0_RBNE : gd32f3x0_i2c.h
  • I2C_STAT0_SBSEND : gd32f3x0_i2c.h
  • I2C_STAT0_SMBALT : gd32f3x0_i2c.h
  • I2C_STAT0_SMBTO : gd32f3x0_i2c.h
  • I2C_STAT0_STPDET : gd32f3x0_i2c.h
  • I2C_STAT0_TBE : gd32f3x0_i2c.h
  • I2C_STAT1 : gd32f3x0_i2c.h
  • I2C_STAT1_DEFSMB : gd32f3x0_i2c.h
  • I2C_STAT1_DUMODF : gd32f3x0_i2c.h
  • I2C_STAT1_ECV : gd32f3x0_i2c.h
  • I2C_STAT1_HSTSMB : gd32f3x0_i2c.h
  • I2C_STAT1_I2CBSY : gd32f3x0_i2c.h
  • I2C_STAT1_MASTER : gd32f3x0_i2c.h
  • I2C_STAT1_RXGC : gd32f3x0_i2c.h
  • I2C_STAT1_TRS : gd32f3x0_i2c.h
  • I2C_TRANSMITTER : gd32f3x0_i2c.h
  • I2CCLK_MAX : gd32f3x0_i2c.c
  • I2S_INIT_MASK : gd32f3x0_spi.c
  • I2S_INT_FLAG_TXURERR : gd32f3x0_spi.h
  • IOFFX_IOFF : gd32f3x0_adc.h
  • IS_NOT_EP0 : usbd_std.h
  • ISQ_IL : gd32f3x0_adc.h


GD32F3x0_Firmware_Library: Globals

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- l -

  • LOCATE_DIEPCTL : usb_regs.h
  • LOCATE_DIEPINTF : usb_regs.h
  • LOCATE_DIEPLEN : usb_regs.h
  • LOCATE_DIEPTFLEN : usb_regs.h
  • LOCATE_DIEPxTFSTAT : usb_regs.h
  • LOCATE_DOEPCTL : usb_regs.h
  • LOCATE_DOEPINTF : usb_regs.h
  • LOCATE_DOEPLEN : usb_regs.h
  • LOCATE_FIFO : usb_regs.h
  • LOCATE_HCHCTL : usb_regs.h
  • LOCATE_HCHINTEN : usb_regs.h
  • LOCATE_HCHINTF : usb_regs.h
  • LOCATE_HCHLEN : usb_regs.h
  • LOWBYTE : usbd_std.h
  • LXTAL_STARTUP_TIMEOUT : gd32f3x0_rcu.c


GD32F3x0_Firmware_Library: Globals

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- m -

  • MAX_USBH_STATE_STACK_DEEP : usbh_core.h
  • MAX_USBH_STATE_TABLE_NUM : usbh_core.h
  • MSC_CLASS : usbh_core.h
  • MSC_PROTOCOL : usbh_core.h


GD32F3x0_Firmware_Library: Globals

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- n -

  • NODATA_STAGE_TIMEOUT : usb_std.h
  • NULL : usb_defines.h
  • NVIC_AIRCR_VECTKEY_MASK : gd32f3x0_misc.h
  • NVIC_PRIGROUP_PRE0_SUB4 : gd32f3x0_misc.h
  • NVIC_PRIGROUP_PRE1_SUB3 : gd32f3x0_misc.h
  • NVIC_PRIGROUP_PRE2_SUB2 : gd32f3x0_misc.h
  • NVIC_PRIGROUP_PRE3_SUB1 : gd32f3x0_misc.h
  • NVIC_PRIGROUP_PRE4_SUB0 : gd32f3x0_misc.h
  • NVIC_VECTTAB_FLASH : gd32f3x0_misc.h
  • NVIC_VECTTAB_OFFSET_MASK : gd32f3x0_misc.h
  • NVIC_VECTTAB_RAM : gd32f3x0_misc.h


GD32F3x0_Firmware_Library: Globals

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- o -

  • OB : gd32f3x0_fmc.h
  • OB_BOOT1_SET_0 : gd32f3x0_fmc.h
  • OB_BOOT1_SET_1 : gd32f3x0_fmc.h
  • OB_DATA_ADDR0 : gd32f3x0_fmc.h
  • OB_DATA_ADDR1 : gd32f3x0_fmc.h
  • OB_DEEPSLEEP_NRST : gd32f3x0_fmc.h
  • OB_DEEPSLEEP_RST : gd32f3x0_fmc.h
  • OB_FWDGT_HW : gd32f3x0_fmc.h
  • OB_FWDGT_SW : gd32f3x0_fmc.h
  • OB_HWP : gd32f3x0_fmc.h
  • OB_LWP : gd32f3x0_fmc.h
  • OB_OBSTAT_PLEVEL_HIGH : gd32f3x0_fmc.h
  • OB_OBSTAT_PLEVEL_LOW : gd32f3x0_fmc.h
  • OB_OBSTAT_PLEVEL_NO : gd32f3x0_fmc.h
  • OB_SPC : gd32f3x0_fmc.h
  • OB_SRAM_PARITY_DISABLE : gd32f3x0_fmc.h
  • OB_SRAM_PARITY_ENABLE : gd32f3x0_fmc.h
  • OB_STDBY_NRST : gd32f3x0_fmc.h
  • OB_STDBY_RST : gd32f3x0_fmc.h
  • OB_USER : gd32f3x0_fmc.h
  • OB_USER_MASK : gd32f3x0_fmc.h
  • OB_VDDA_DISABLE : gd32f3x0_fmc.h
  • OB_VDDA_ENABLE : gd32f3x0_fmc.h
  • OB_WP0 : gd32f3x0_fmc.h
  • OB_WP1 : gd32f3x0_fmc.h
  • OBUSER_BOOT1_N : gd32f3x0_fmc.h
  • OBUSER_NRST_DPSLP : gd32f3x0_fmc.h
  • OBUSER_NRST_STDBY : gd32f3x0_fmc.h
  • OBUSER_NWDG_HW : gd32f3x0_fmc.h
  • OBUSER_SRAM_PARITY : gd32f3x0_fmc.h
  • OBUSER_VDDA_VISOR : gd32f3x0_fmc.h
  • OSC_STARTUP_TIMEOUT : gd32f3x0_rcu.c
  • OSPD_OSPD0 : gd32f3x0_gpio.h
  • OTG_MODE : usb_defines.h
  • OVSAMPCTL_OVSR : gd32f3x0_adc.h
  • OVSAMPCTL_OVSS : gd32f3x0_adc.h


GD32F3x0_Firmware_Library: Globals

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- p -

  • PMU : gd32f3x0_pmu.h
  • PMU_CS : gd32f3x0_pmu.h
  • PMU_CS_HDRF : gd32f3x0_pmu.h
  • PMU_CS_HDSRF : gd32f3x0_pmu.h
  • PMU_CS_LDOVSRF : gd32f3x0_pmu.h
  • PMU_CS_LDRF : gd32f3x0_pmu.h
  • PMU_CS_LVDF : gd32f3x0_pmu.h
  • PMU_CS_STBF : gd32f3x0_pmu.h
  • PMU_CS_WUF : gd32f3x0_pmu.h
  • PMU_CS_WUPEN0 : gd32f3x0_pmu.h
  • PMU_CS_WUPEN1 : gd32f3x0_pmu.h
  • PMU_CS_WUPEN4 : gd32f3x0_pmu.h
  • PMU_CS_WUPEN5 : gd32f3x0_pmu.h
  • PMU_CS_WUPEN6 : gd32f3x0_pmu.h
  • PMU_CTL : gd32f3x0_pmu.h
  • PMU_CTL_BKPWEN : gd32f3x0_pmu.h
  • PMU_CTL_HDEN : gd32f3x0_pmu.h
  • PMU_CTL_HDS : gd32f3x0_pmu.h
  • PMU_CTL_LDEN : gd32f3x0_pmu.h
  • PMU_CTL_LDLP : gd32f3x0_pmu.h
  • PMU_CTL_LDNP : gd32f3x0_pmu.h
  • PMU_CTL_LDOLP : gd32f3x0_pmu.h
  • PMU_CTL_LDOVS : gd32f3x0_pmu.h
  • PMU_CTL_LVDEN : gd32f3x0_pmu.h
  • PMU_CTL_LVDT : gd32f3x0_pmu.h
  • PMU_CTL_STBMOD : gd32f3x0_pmu.h
  • PMU_CTL_STBRST : gd32f3x0_pmu.h
  • PMU_CTL_WURST : gd32f3x0_pmu.h
  • PMU_FLAG_HDR : gd32f3x0_pmu.h
  • PMU_FLAG_HDSR : gd32f3x0_pmu.h
  • PMU_FLAG_LDOVSR : gd32f3x0_pmu.h
  • PMU_FLAG_LDR : gd32f3x0_pmu.h
  • PMU_FLAG_LVD : gd32f3x0_pmu.h
  • PMU_FLAG_RESET_STANDBY : gd32f3x0_pmu.h
  • PMU_FLAG_RESET_WAKEUP : gd32f3x0_pmu.h
  • PMU_FLAG_STANDBY : gd32f3x0_pmu.h
  • PMU_FLAG_WAKEUP : gd32f3x0_pmu.h
  • PMU_HIGHDR_SWITCH_EN : gd32f3x0_pmu.h
  • PMU_HIGHDR_SWITCH_NONE : gd32f3x0_pmu.h
  • PMU_LDO_LOWPOWER : gd32f3x0_pmu.h
  • PMU_LDO_NORMAL : gd32f3x0_pmu.h
  • PMU_LDOVS_HIGH : gd32f3x0_pmu.h
  • PMU_LDOVS_LOW : gd32f3x0_pmu.h
  • PMU_LDOVS_MID : gd32f3x0_pmu.h
  • PMU_LDRF_LOWDRIVER : gd32f3x0_pmu.h
  • PMU_LDRF_NORMAL : gd32f3x0_pmu.h
  • PMU_LOWDR_LOWPWR : gd32f3x0_pmu.h
  • PMU_LOWDR_NORMALPWR : gd32f3x0_pmu.h
  • PMU_LOWDRIVER_DISABLE : gd32f3x0_pmu.h
  • PMU_LOWDRIVER_ENABLE : gd32f3x0_pmu.h
  • PMU_LVDT_0 : gd32f3x0_pmu.h
  • PMU_LVDT_1 : gd32f3x0_pmu.h
  • PMU_LVDT_2 : gd32f3x0_pmu.h
  • PMU_LVDT_3 : gd32f3x0_pmu.h
  • PMU_LVDT_4 : gd32f3x0_pmu.h
  • PMU_LVDT_5 : gd32f3x0_pmu.h
  • PMU_LVDT_6 : gd32f3x0_pmu.h
  • PMU_LVDT_7 : gd32f3x0_pmu.h
  • PMU_NORMALDR_LOWPWR : gd32f3x0_pmu.h
  • PMU_NORMALDR_NORMALPWR : gd32f3x0_pmu.h
  • PMU_WAKEUP_PIN0 : gd32f3x0_pmu.h
  • PMU_WAKEUP_PIN1 : gd32f3x0_pmu.h
  • PMU_WAKEUP_PIN4 : gd32f3x0_pmu.h
  • PMU_WAKEUP_PIN5 : gd32f3x0_pmu.h
  • PMU_WAKEUP_PIN6 : gd32f3x0_pmu.h
  • PSC_FACTOR_A : gd32f3x0_rtc.h
  • PSC_FACTOR_S : gd32f3x0_rtc.h
  • PSC_PSC : gd32f3x0_fwdgt.h
  • PUD_PUPD : gd32f3x0_gpio.h
  • PWRCLKCTL_SHCLK : usb_regs.h
  • PWRCLKCTL_SUCLK : usb_regs.h


GD32F3x0_Firmware_Library: Globals

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- r -

  • RCU : gd32f3x0_rcu.h
  • RCU_ADC_CKAPB2_DIV2 : gd32f3x0_rcu.h
  • RCU_ADC_CKAPB2_DIV4 : gd32f3x0_rcu.h
  • RCU_ADC_CKAPB2_DIV6 : gd32f3x0_rcu.h
  • RCU_ADC_CKAPB2_DIV8 : gd32f3x0_rcu.h
  • RCU_ADC_IRC28M_DIV1 : gd32f3x0_rcu.h
  • RCU_ADC_IRC28M_DIV2 : gd32f3x0_rcu.h
  • RCU_ADCSRC_APB2DIV : gd32f3x0_rcu.h
  • RCU_ADCSRC_IRC28M : gd32f3x0_rcu.h
  • RCU_ADDAPB1EN : gd32f3x0_rcu.h
  • RCU_ADDAPB1EN_CTCEN : gd32f3x0_rcu.h
  • RCU_ADDAPB1EN_I2C2EN : gd32f3x0_rcu.h
  • RCU_ADDAPB1RST : gd32f3x0_rcu.h
  • RCU_ADDAPB1RST_CTCRST : gd32f3x0_rcu.h
  • RCU_ADDAPB1RST_I2C2RST : gd32f3x0_rcu.h
  • RCU_ADDCTL : gd32f3x0_rcu.h
  • RCU_ADDCTL_CK48MSEL : gd32f3x0_rcu.h
  • RCU_ADDCTL_IRC48MCALIB : gd32f3x0_rcu.h
  • RCU_ADDCTL_IRC48MEN : gd32f3x0_rcu.h
  • RCU_ADDCTL_IRC48MSTB : gd32f3x0_rcu.h
  • RCU_ADDINT : gd32f3x0_rcu.h
  • RCU_ADDINT_IRC48MSTBIC : gd32f3x0_rcu.h
  • RCU_ADDINT_IRC48MSTBIE : gd32f3x0_rcu.h
  • RCU_ADDINT_IRC48MSTBIF : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV1 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV128 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV16 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV2 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV256 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV4 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV512 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV64 : gd32f3x0_rcu.h
  • RCU_AHB_CKSYS_DIV8 : gd32f3x0_rcu.h
  • RCU_AHBEN : gd32f3x0_rcu.h
  • RCU_AHBEN_CRCEN : gd32f3x0_rcu.h
  • RCU_AHBEN_DMAEN : gd32f3x0_rcu.h
  • RCU_AHBEN_FMCSPEN : gd32f3x0_rcu.h
  • RCU_AHBEN_PAEN : gd32f3x0_rcu.h
  • RCU_AHBEN_PBEN : gd32f3x0_rcu.h
  • RCU_AHBEN_PCEN : gd32f3x0_rcu.h
  • RCU_AHBEN_PDEN : gd32f3x0_rcu.h
  • RCU_AHBEN_PFEN : gd32f3x0_rcu.h
  • RCU_AHBEN_SRAMSPEN : gd32f3x0_rcu.h
  • RCU_AHBEN_TSIEN : gd32f3x0_rcu.h
  • RCU_AHBEN_USBFS : gd32f3x0_rcu.h
  • RCU_AHBRST : gd32f3x0_rcu.h
  • RCU_AHBRST_PARST : gd32f3x0_rcu.h
  • RCU_AHBRST_PBRST : gd32f3x0_rcu.h
  • RCU_AHBRST_PCRST : gd32f3x0_rcu.h
  • RCU_AHBRST_PDRST : gd32f3x0_rcu.h
  • RCU_AHBRST_PFRST : gd32f3x0_rcu.h
  • RCU_AHBRST_TSIRST : gd32f3x0_rcu.h
  • RCU_AHBRST_USBFSRST : gd32f3x0_rcu.h
  • RCU_APB1_CKAHB_DIV1 : gd32f3x0_rcu.h
  • RCU_APB1_CKAHB_DIV16 : gd32f3x0_rcu.h
  • RCU_APB1_CKAHB_DIV2 : gd32f3x0_rcu.h
  • RCU_APB1_CKAHB_DIV4 : gd32f3x0_rcu.h
  • RCU_APB1_CKAHB_DIV8 : gd32f3x0_rcu.h
  • RCU_APB1EN : gd32f3x0_rcu.h
  • RCU_APB1EN_CECEN : gd32f3x0_rcu.h
  • RCU_APB1EN_DACEN : gd32f3x0_rcu.h
  • RCU_APB1EN_I2C0EN : gd32f3x0_rcu.h
  • RCU_APB1EN_I2C1EN : gd32f3x0_rcu.h
  • RCU_APB1EN_PMUEN : gd32f3x0_rcu.h
  • RCU_APB1EN_SPI1EN : gd32f3x0_rcu.h
  • RCU_APB1EN_SPI2EN : gd32f3x0_rcu.h
  • RCU_APB1EN_TIMER13EN : gd32f3x0_rcu.h
  • RCU_APB1EN_TIMER1EN : gd32f3x0_rcu.h
  • RCU_APB1EN_TIMER2EN : gd32f3x0_rcu.h
  • RCU_APB1EN_TIMER5EN : gd32f3x0_rcu.h
  • RCU_APB1EN_USART1EN : gd32f3x0_rcu.h
  • RCU_APB1EN_WWDGTEN : gd32f3x0_rcu.h
  • RCU_APB1RST : gd32f3x0_rcu.h
  • RCU_APB1RST_CECRST : gd32f3x0_rcu.h
  • RCU_APB1RST_DACRST : gd32f3x0_rcu.h
  • RCU_APB1RST_I2C0RST : gd32f3x0_rcu.h
  • RCU_APB1RST_I2C1RST : gd32f3x0_rcu.h
  • RCU_APB1RST_PMURST : gd32f3x0_rcu.h
  • RCU_APB1RST_SPI1RST : gd32f3x0_rcu.h
  • RCU_APB1RST_SPI2RST : gd32f3x0_rcu.h
  • RCU_APB1RST_TIMER13RST : gd32f3x0_rcu.h
  • RCU_APB1RST_TIMER1RST : gd32f3x0_rcu.h
  • RCU_APB1RST_TIMER2RST : gd32f3x0_rcu.h
  • RCU_APB1RST_TIMER5RST : gd32f3x0_rcu.h
  • RCU_APB1RST_USART1RST : gd32f3x0_rcu.h
  • RCU_APB1RST_WWDGTRST : gd32f3x0_rcu.h
  • RCU_APB2_CKAHB_DIV1 : gd32f3x0_rcu.h
  • RCU_APB2_CKAHB_DIV16 : gd32f3x0_rcu.h
  • RCU_APB2_CKAHB_DIV2 : gd32f3x0_rcu.h
  • RCU_APB2_CKAHB_DIV4 : gd32f3x0_rcu.h
  • RCU_APB2_CKAHB_DIV8 : gd32f3x0_rcu.h
  • RCU_APB2EN : gd32f3x0_rcu.h
  • RCU_APB2EN_ADCEN : gd32f3x0_rcu.h
  • RCU_APB2EN_CFGCMPEN : gd32f3x0_rcu.h
  • RCU_APB2EN_SPI0EN : gd32f3x0_rcu.h
  • RCU_APB2EN_TIMER0EN : gd32f3x0_rcu.h
  • RCU_APB2EN_TIMER14EN : gd32f3x0_rcu.h
  • RCU_APB2EN_TIMER15EN : gd32f3x0_rcu.h
  • RCU_APB2EN_TIMER16EN : gd32f3x0_rcu.h
  • RCU_APB2EN_USART0EN : gd32f3x0_rcu.h
  • RCU_APB2RST : gd32f3x0_rcu.h
  • RCU_APB2RST_ADCRST : gd32f3x0_rcu.h
  • RCU_APB2RST_CFGRST : gd32f3x0_rcu.h
  • RCU_APB2RST_SPI0RST : gd32f3x0_rcu.h
  • RCU_APB2RST_TIMER0RST : gd32f3x0_rcu.h
  • RCU_APB2RST_TIMER14RST : gd32f3x0_rcu.h
  • RCU_APB2RST_TIMER15RST : gd32f3x0_rcu.h
  • RCU_APB2RST_TIMER16RST : gd32f3x0_rcu.h
  • RCU_APB2RST_USART0RST : gd32f3x0_rcu.h
  • RCU_BDCTL : gd32f3x0_rcu.h
  • RCU_BDCTL_BKPRST : gd32f3x0_rcu.h
  • RCU_BDCTL_LXTALBPS : gd32f3x0_rcu.h
  • RCU_BDCTL_LXTALDRI : gd32f3x0_rcu.h
  • RCU_BDCTL_LXTALEN : gd32f3x0_rcu.h
  • RCU_BDCTL_LXTALSTB : gd32f3x0_rcu.h
  • RCU_BDCTL_RTCEN : gd32f3x0_rcu.h
  • RCU_BDCTL_RTCSRC : gd32f3x0_rcu.h
  • RCU_BIT_POS : gd32f3x0_rcu.h
  • RCU_CECSRC_IRC8M_DIV244 : gd32f3x0_rcu.h
  • RCU_CECSRC_LXTAL : gd32f3x0_rcu.h
  • RCU_CFG0 : gd32f3x0_rcu.h
  • RCU_CFG0_ADCPSC : gd32f3x0_rcu.h
  • RCU_CFG0_AHBPSC : gd32f3x0_rcu.h
  • RCU_CFG0_APB1PSC : gd32f3x0_rcu.h
  • RCU_CFG0_APB2PSC : gd32f3x0_rcu.h
  • RCU_CFG0_CKOUTDIV : gd32f3x0_rcu.h
  • RCU_CFG0_CKOUTSEL : gd32f3x0_rcu.h
  • RCU_CFG0_PLLDV : gd32f3x0_rcu.h
  • RCU_CFG0_PLLMF : gd32f3x0_rcu.h
  • RCU_CFG0_PLLMF4 : gd32f3x0_rcu.h
  • RCU_CFG0_PLLPREDV : gd32f3x0_rcu.h
  • RCU_CFG0_PLLSEL : gd32f3x0_rcu.h
  • RCU_CFG0_SCS : gd32f3x0_rcu.h
  • RCU_CFG0_SCSS : gd32f3x0_rcu.h
  • RCU_CFG0_USBFSPSC : gd32f3x0_rcu.h
  • RCU_CFG1 : gd32f3x0_rcu.h
  • RCU_CFG1_PLLMF5 : gd32f3x0_rcu.h
  • RCU_CFG1_PLLPRESEL : gd32f3x0_rcu.h
  • RCU_CFG1_PREDV : gd32f3x0_rcu.h
  • RCU_CFG2 : gd32f3x0_rcu.h
  • RCU_CFG2_ADCPSC2 : gd32f3x0_rcu.h
  • RCU_CFG2_ADCSEL : gd32f3x0_rcu.h
  • RCU_CFG2_CECSEL : gd32f3x0_rcu.h
  • RCU_CFG2_IRC28MDIV : gd32f3x0_rcu.h
  • RCU_CFG2_USART0SEL : gd32f3x0_rcu.h
  • RCU_CFG2_USBFSPSC2 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV1 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV128 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV16 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV2 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV32 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV4 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV64 : gd32f3x0_rcu.h
  • RCU_CKOUT_DIV8 : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_CKPLL_DIV1 : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_CKPLL_DIV2 : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_CKSYS : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_HXTAL : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_IRC28M : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_IRC40K : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_IRC8M : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_LXTAL : gd32f3x0_rcu.h
  • RCU_CKOUTSRC_NONE : gd32f3x0_rcu.h
  • RCU_CKSYSSRC_HXTAL : gd32f3x0_rcu.h
  • RCU_CKSYSSRC_IRC8M : gd32f3x0_rcu.h
  • RCU_CKSYSSRC_PLL : gd32f3x0_rcu.h
  • RCU_CTL0 : gd32f3x0_rcu.h
  • RCU_CTL0_CKMEN : gd32f3x0_rcu.h
  • RCU_CTL0_HXTALBPS : gd32f3x0_rcu.h
  • RCU_CTL0_HXTALEN : gd32f3x0_rcu.h
  • RCU_CTL0_HXTALSTB : gd32f3x0_rcu.h
  • RCU_CTL0_IRC8MADJ : gd32f3x0_rcu.h
  • RCU_CTL0_IRC8MCALIB : gd32f3x0_rcu.h
  • RCU_CTL0_IRC8MEN : gd32f3x0_rcu.h
  • RCU_CTL0_IRC8MSTB : gd32f3x0_rcu.h
  • RCU_CTL0_PLLEN : gd32f3x0_rcu.h
  • RCU_CTL0_PLLSTB : gd32f3x0_rcu.h
  • RCU_CTL1 : gd32f3x0_rcu.h
  • RCU_CTL1_IRC28MADJ : gd32f3x0_rcu.h
  • RCU_CTL1_IRC28MCALIB : gd32f3x0_rcu.h
  • RCU_CTL1_IRC28MEN : gd32f3x0_rcu.h
  • RCU_CTL1_IRC28MSTB : gd32f3x0_rcu.h
  • RCU_DEEPSLEEP_V_0_7 : gd32f3x0_rcu.h
  • RCU_DEEPSLEEP_V_0_8 : gd32f3x0_rcu.h
  • RCU_DEEPSLEEP_V_0_9 : gd32f3x0_rcu.h
  • RCU_DEEPSLEEP_V_1_0 : gd32f3x0_rcu.h
  • RCU_DSV : gd32f3x0_rcu.h
  • RCU_DSV_DSLPVS : gd32f3x0_rcu.h
  • RCU_INT : gd32f3x0_rcu.h
  • RCU_INT_CKMIC : gd32f3x0_rcu.h
  • RCU_INT_CKMIF : gd32f3x0_rcu.h
  • RCU_INT_HXTALSTBIC : gd32f3x0_rcu.h
  • RCU_INT_HXTALSTBIE : gd32f3x0_rcu.h
  • RCU_INT_HXTALSTBIF : gd32f3x0_rcu.h
  • RCU_INT_IRC28MSTBIC : gd32f3x0_rcu.h
  • RCU_INT_IRC28MSTBIE : gd32f3x0_rcu.h
  • RCU_INT_IRC28MSTBIF : gd32f3x0_rcu.h
  • RCU_INT_IRC40KSTBIC : gd32f3x0_rcu.h
  • RCU_INT_IRC40KSTBIE : gd32f3x0_rcu.h
  • RCU_INT_IRC40KSTBIF : gd32f3x0_rcu.h
  • RCU_INT_IRC8MSTBIC : gd32f3x0_rcu.h
  • RCU_INT_IRC8MSTBIE : gd32f3x0_rcu.h
  • RCU_INT_IRC8MSTBIF : gd32f3x0_rcu.h
  • RCU_INT_LXTALSTBIC : gd32f3x0_rcu.h
  • RCU_INT_LXTALSTBIE : gd32f3x0_rcu.h
  • RCU_INT_LXTALSTBIF : gd32f3x0_rcu.h
  • RCU_INT_PLLSTBIC : gd32f3x0_rcu.h
  • RCU_INT_PLLSTBIE : gd32f3x0_rcu.h
  • RCU_INT_PLLSTBIF : gd32f3x0_rcu.h
  • RCU_LXTAL_HIGHDRI : gd32f3x0_rcu.h
  • RCU_LXTAL_LOWDRI : gd32f3x0_rcu.h
  • RCU_LXTAL_MED_HIGHDRI : gd32f3x0_rcu.h
  • RCU_LXTAL_MED_LOWDRI : gd32f3x0_rcu.h
  • RCU_PLL_MUL10 : gd32f3x0_rcu.h
  • RCU_PLL_MUL11 : gd32f3x0_rcu.h
  • RCU_PLL_MUL12 : gd32f3x0_rcu.h
  • RCU_PLL_MUL13 : gd32f3x0_rcu.h
  • RCU_PLL_MUL14 : gd32f3x0_rcu.h
  • RCU_PLL_MUL15 : gd32f3x0_rcu.h
  • RCU_PLL_MUL16 : gd32f3x0_rcu.h
  • RCU_PLL_MUL17 : gd32f3x0_rcu.h
  • RCU_PLL_MUL18 : gd32f3x0_rcu.h
  • RCU_PLL_MUL19 : gd32f3x0_rcu.h
  • RCU_PLL_MUL2 : gd32f3x0_rcu.h
  • RCU_PLL_MUL20 : gd32f3x0_rcu.h
  • RCU_PLL_MUL21 : gd32f3x0_rcu.h
  • RCU_PLL_MUL22 : gd32f3x0_rcu.h
  • RCU_PLL_MUL23 : gd32f3x0_rcu.h
  • RCU_PLL_MUL24 : gd32f3x0_rcu.h
  • RCU_PLL_MUL25 : gd32f3x0_rcu.h
  • RCU_PLL_MUL26 : gd32f3x0_rcu.h
  • RCU_PLL_MUL27 : gd32f3x0_rcu.h
  • RCU_PLL_MUL28 : gd32f3x0_rcu.h
  • RCU_PLL_MUL29 : gd32f3x0_rcu.h
  • RCU_PLL_MUL3 : gd32f3x0_rcu.h
  • RCU_PLL_MUL30 : gd32f3x0_rcu.h
  • RCU_PLL_MUL31 : gd32f3x0_rcu.h
  • RCU_PLL_MUL32 : gd32f3x0_rcu.h
  • RCU_PLL_MUL33 : gd32f3x0_rcu.h
  • RCU_PLL_MUL34 : gd32f3x0_rcu.h
  • RCU_PLL_MUL35 : gd32f3x0_rcu.h
  • RCU_PLL_MUL36 : gd32f3x0_rcu.h
  • RCU_PLL_MUL37 : gd32f3x0_rcu.h
  • RCU_PLL_MUL38 : gd32f3x0_rcu.h
  • RCU_PLL_MUL39 : gd32f3x0_rcu.h
  • RCU_PLL_MUL4 : gd32f3x0_rcu.h
  • RCU_PLL_MUL40 : gd32f3x0_rcu.h
  • RCU_PLL_MUL41 : gd32f3x0_rcu.h
  • RCU_PLL_MUL42 : gd32f3x0_rcu.h
  • RCU_PLL_MUL43 : gd32f3x0_rcu.h
  • RCU_PLL_MUL44 : gd32f3x0_rcu.h
  • RCU_PLL_MUL45 : gd32f3x0_rcu.h
  • RCU_PLL_MUL46 : gd32f3x0_rcu.h
  • RCU_PLL_MUL47 : gd32f3x0_rcu.h
  • RCU_PLL_MUL48 : gd32f3x0_rcu.h
  • RCU_PLL_MUL49 : gd32f3x0_rcu.h
  • RCU_PLL_MUL5 : gd32f3x0_rcu.h
  • RCU_PLL_MUL50 : gd32f3x0_rcu.h
  • RCU_PLL_MUL51 : gd32f3x0_rcu.h
  • RCU_PLL_MUL52 : gd32f3x0_rcu.h
  • RCU_PLL_MUL53 : gd32f3x0_rcu.h
  • RCU_PLL_MUL54 : gd32f3x0_rcu.h
  • RCU_PLL_MUL55 : gd32f3x0_rcu.h
  • RCU_PLL_MUL56 : gd32f3x0_rcu.h
  • RCU_PLL_MUL57 : gd32f3x0_rcu.h
  • RCU_PLL_MUL58 : gd32f3x0_rcu.h
  • RCU_PLL_MUL59 : gd32f3x0_rcu.h
  • RCU_PLL_MUL6 : gd32f3x0_rcu.h
  • RCU_PLL_MUL60 : gd32f3x0_rcu.h
  • RCU_PLL_MUL61 : gd32f3x0_rcu.h
  • RCU_PLL_MUL62 : gd32f3x0_rcu.h
  • RCU_PLL_MUL63 : gd32f3x0_rcu.h
  • RCU_PLL_MUL64 : gd32f3x0_rcu.h
  • RCU_PLL_MUL7 : gd32f3x0_rcu.h
  • RCU_PLL_MUL8 : gd32f3x0_rcu.h
  • RCU_PLL_MUL9 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV1 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV10 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV11 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV12 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV13 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV14 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV15 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV16 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV2 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV3 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV4 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV5 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV6 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV7 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV8 : gd32f3x0_rcu.h
  • RCU_PLL_PREDV9 : gd32f3x0_rcu.h
  • RCU_PLLDV_CKPLL : gd32f3x0_rcu.h
  • RCU_PLLDV_CKPLL_DIV2 : gd32f3x0_rcu.h
  • RCU_PLLPREDV : gd32f3x0_rcu.h
  • RCU_PLLPREDV_DIV2 : gd32f3x0_rcu.h
  • RCU_PLLPRESEL_HXTAL : gd32f3x0_rcu.h
  • RCU_PLLPRESEL_IRC48M : gd32f3x0_rcu.h
  • RCU_PLLSRC_HXTAL_IRC48M : gd32f3x0_rcu.h
  • RCU_PLLSRC_IRC8M_DIV2 : gd32f3x0_rcu.h
  • RCU_REG_VAL : gd32f3x0_rcu.h
  • RCU_REGIDX_BIT : gd32f3x0_rcu.h
  • RCU_RSTSCK : gd32f3x0_rcu.h
  • RCU_RSTSCK_EPRSTF : gd32f3x0_rcu.h
  • RCU_RSTSCK_FWDGTRSTF : gd32f3x0_rcu.h
  • RCU_RSTSCK_IRC40KEN : gd32f3x0_rcu.h
  • RCU_RSTSCK_IRC40KSTB : gd32f3x0_rcu.h
  • RCU_RSTSCK_LPRSTF : gd32f3x0_rcu.h
  • RCU_RSTSCK_OBLRSTF : gd32f3x0_rcu.h
  • RCU_RSTSCK_PORRSTF : gd32f3x0_rcu.h
  • RCU_RSTSCK_RSTFC : gd32f3x0_rcu.h
  • RCU_RSTSCK_SWRSTF : gd32f3x0_rcu.h
  • RCU_RSTSCK_V12RSTF : gd32f3x0_rcu.h
  • RCU_RSTSCK_WWDGTRSTF : gd32f3x0_rcu.h
  • RCU_RTCSRC_HXTAL_DIV32 : gd32f3x0_rcu.h
  • RCU_RTCSRC_IRC40K : gd32f3x0_rcu.h
  • RCU_RTCSRC_LXTAL : gd32f3x0_rcu.h
  • RCU_RTCSRC_NONE : gd32f3x0_rcu.h
  • RCU_SCSS_HXTAL : gd32f3x0_rcu.h
  • RCU_SCSS_IRC8M : gd32f3x0_rcu.h
  • RCU_SCSS_PLL : gd32f3x0_rcu.h
  • RCU_USART0SRC_CKAPB2 : gd32f3x0_rcu.h
  • RCU_USART0SRC_CKSYS : gd32f3x0_rcu.h
  • RCU_USART0SRC_IRC8M : gd32f3x0_rcu.h
  • RCU_USART0SRC_LXTAL : gd32f3x0_rcu.h
  • RCU_USBFS_CKPLL_DIV1 : gd32f3x0_rcu.h
  • RCU_USBFS_CKPLL_DIV1_5 : gd32f3x0_rcu.h
  • RCU_USBFS_CKPLL_DIV2 : gd32f3x0_rcu.h
  • RCU_USBFS_CKPLL_DIV2_5 : gd32f3x0_rcu.h
  • RCU_USBFS_CKPLL_DIV3 : gd32f3x0_rcu.h
  • RCU_USBFS_CKPLL_DIV3_5 : gd32f3x0_rcu.h
  • RCU_VKEY : gd32f3x0_rcu.h
  • RCU_VKEY_KEY : gd32f3x0_rcu.h
  • RCU_VKEY_UNLOCK : gd32f3x0_rcu.h
  • RLD_RLD : gd32f3x0_fwdgt.h
  • RSQ0_RL : gd32f3x0_adc.h
  • RTC : gd32f3x0_rtc.h
  • RTC_12HOUR : gd32f3x0_rtc.h
  • RTC_24HOUR : gd32f3x0_rtc.h
  • RTC_ALARM_ALL_MASK : gd32f3x0_rtc.h
  • RTC_ALARM_DATE_MASK : gd32f3x0_rtc.h
  • RTC_ALARM_DATE_SELECTED : gd32f3x0_rtc.h
  • RTC_ALARM_HIGH : gd32f3x0_rtc.h
  • RTC_ALARM_HOUR_MASK : gd32f3x0_rtc.h
  • RTC_ALARM_LOW : gd32f3x0_rtc.h
  • RTC_ALARM_MINUTE_MASK : gd32f3x0_rtc.h
  • RTC_ALARM_NONE_MASK : gd32f3x0_rtc.h
  • RTC_ALARM_OUTPUT_OD : gd32f3x0_rtc.h
  • RTC_ALARM_OUTPUT_PP : gd32f3x0_rtc.h
  • RTC_ALARM_SECOND_MASK : gd32f3x0_rtc.h
  • RTC_ALARM_WEEKDAY_SELECTED : gd32f3x0_rtc.h
  • RTC_ALRM0SS : gd32f3x0_rtc.h
  • RTC_ALRM0SS_MASKSSC : gd32f3x0_rtc.h
  • RTC_ALRM0SS_SSC : gd32f3x0_rtc.h
  • RTC_ALRM0TD : gd32f3x0_rtc.h
  • RTC_ALRM0TD_DAYT : gd32f3x0_rtc.h
  • RTC_ALRM0TD_DAYU : gd32f3x0_rtc.h
  • RTC_ALRM0TD_DOWS : gd32f3x0_rtc.h
  • RTC_ALRM0TD_HRT : gd32f3x0_rtc.h
  • RTC_ALRM0TD_HRU : gd32f3x0_rtc.h
  • RTC_ALRM0TD_MNT : gd32f3x0_rtc.h
  • RTC_ALRM0TD_MNU : gd32f3x0_rtc.h
  • RTC_ALRM0TD_MSKD : gd32f3x0_rtc.h
  • RTC_ALRM0TD_MSKH : gd32f3x0_rtc.h
  • RTC_ALRM0TD_MSKM : gd32f3x0_rtc.h
  • RTC_ALRM0TD_MSKS : gd32f3x0_rtc.h
  • RTC_ALRM0TD_PM : gd32f3x0_rtc.h
  • RTC_ALRM0TD_SCT : gd32f3x0_rtc.h
  • RTC_ALRM0TD_SCU : gd32f3x0_rtc.h
  • RTC_ALRM0WF_TIMEOUT : gd32f3x0_rtc.h
  • RTC_AM : gd32f3x0_rtc.h
  • RTC_APR : gd32f3x0_rtc.h
  • RTC_AUG : gd32f3x0_rtc.h
  • RTC_BKP0 : gd32f3x0_rtc.h
  • RTC_BKP0_DATA : gd32f3x0_rtc.h
  • RTC_BKP1 : gd32f3x0_rtc.h
  • RTC_BKP1_DATA : gd32f3x0_rtc.h
  • RTC_BKP2 : gd32f3x0_rtc.h
  • RTC_BKP2_DATA : gd32f3x0_rtc.h
  • RTC_BKP3 : gd32f3x0_rtc.h
  • RTC_BKP3_DATA : gd32f3x0_rtc.h
  • RTC_BKP4 : gd32f3x0_rtc.h
  • RTC_BKP4_DATA : gd32f3x0_rtc.h
  • RTC_CALIBRATION_1HZ : gd32f3x0_rtc.h
  • RTC_CALIBRATION_512HZ : gd32f3x0_rtc.h
  • RTC_CALIBRATION_PLUS_RESET : gd32f3x0_rtc.h
  • RTC_CALIBRATION_PLUS_SET : gd32f3x0_rtc.h
  • RTC_CALIBRATION_WINDOW_16S : gd32f3x0_rtc.h
  • RTC_CALIBRATION_WINDOW_32S : gd32f3x0_rtc.h
  • RTC_CALIBRATION_WINDOW_8S : gd32f3x0_rtc.h
  • RTC_CTL : gd32f3x0_rtc.h
  • RTC_CTL_A1H : gd32f3x0_rtc.h
  • RTC_CTL_ALRM0EN : gd32f3x0_rtc.h
  • RTC_CTL_ALRM0IE : gd32f3x0_rtc.h
  • RTC_CTL_BPSHAD : gd32f3x0_rtc.h
  • RTC_CTL_COEN : gd32f3x0_rtc.h
  • RTC_CTL_COS : gd32f3x0_rtc.h
  • RTC_CTL_CS : gd32f3x0_rtc.h
  • RTC_CTL_DSM : gd32f3x0_rtc.h
  • RTC_CTL_OPOL : gd32f3x0_rtc.h
  • RTC_CTL_OS : gd32f3x0_rtc.h
  • RTC_CTL_REFEN : gd32f3x0_rtc.h
  • RTC_CTL_S1H : gd32f3x0_rtc.h
  • RTC_CTL_TSEG : gd32f3x0_rtc.h
  • RTC_CTL_TSEN : gd32f3x0_rtc.h
  • RTC_CTL_TSIE : gd32f3x0_rtc.h
  • RTC_DATE : gd32f3x0_rtc.h
  • RTC_DATE_DAYT : gd32f3x0_rtc.h
  • RTC_DATE_DAYU : gd32f3x0_rtc.h
  • RTC_DATE_DOW : gd32f3x0_rtc.h
  • RTC_DATE_MONT : gd32f3x0_rtc.h
  • RTC_DATE_MONU : gd32f3x0_rtc.h
  • RTC_DATE_RESET : gd32f3x0_rtc.h
  • RTC_DATE_YRT : gd32f3x0_rtc.h
  • RTC_DATE_YRU : gd32f3x0_rtc.h
  • RTC_DEC : gd32f3x0_rtc.h
  • RTC_DTS : gd32f3x0_rtc.h
  • RTC_DTS_DAYT : gd32f3x0_rtc.h
  • RTC_DTS_DAYU : gd32f3x0_rtc.h
  • RTC_DTS_DOW : gd32f3x0_rtc.h
  • RTC_DTS_MONT : gd32f3x0_rtc.h
  • RTC_DTS_MONU : gd32f3x0_rtc.h
  • RTC_FEB : gd32f3x0_rtc.h
  • RTC_FLAG_ALARM0 : gd32f3x0_rtc.h
  • RTC_FLAG_ALARM0_WRITTEN : gd32f3x0_rtc.h
  • RTC_FLAG_INIT : gd32f3x0_rtc.h
  • RTC_FLAG_RECALIBRATION : gd32f3x0_rtc.h
  • RTC_FLAG_RSYN : gd32f3x0_rtc.h
  • RTC_FLAG_SHIFT : gd32f3x0_rtc.h
  • RTC_FLAG_TAMP0 : gd32f3x0_rtc.h
  • RTC_FLAG_TAMP1 : gd32f3x0_rtc.h
  • RTC_FLAG_TIMESTAMP : gd32f3x0_rtc.h
  • RTC_FLAG_TIMESTAMP_OVERFLOW : gd32f3x0_rtc.h
  • RTC_FLAG_YCM : gd32f3x0_rtc.h
  • RTC_FLT_2S : gd32f3x0_rtc.h
  • RTC_FLT_4S : gd32f3x0_rtc.h
  • RTC_FLT_8S : gd32f3x0_rtc.h
  • RTC_FLT_EDGE : gd32f3x0_rtc.h
  • RTC_FREQ_DIV1024 : gd32f3x0_rtc.h
  • RTC_FREQ_DIV16384 : gd32f3x0_rtc.h
  • RTC_FREQ_DIV2048 : gd32f3x0_rtc.h
  • RTC_FREQ_DIV256 : gd32f3x0_rtc.h
  • RTC_FREQ_DIV32768 : gd32f3x0_rtc.h
  • RTC_FREQ_DIV4096 : gd32f3x0_rtc.h
  • RTC_FREQ_DIV512 : gd32f3x0_rtc.h
  • RTC_FREQ_DIV8192 : gd32f3x0_rtc.h
  • RTC_FRIDAY : gd32f3x0_rtc.h
  • RTC_HRFC : gd32f3x0_rtc.h
  • RTC_HRFC_CMSK : gd32f3x0_rtc.h
  • RTC_HRFC_CWND16 : gd32f3x0_rtc.h
  • RTC_HRFC_CWND8 : gd32f3x0_rtc.h
  • RTC_HRFC_FREQI : gd32f3x0_rtc.h
  • RTC_HRFC_TIMEOUT : gd32f3x0_rtc.h
  • RTC_INITM_TIMEOUT : gd32f3x0_rtc.h
  • RTC_INT_ALARM : gd32f3x0_rtc.h
  • RTC_INT_TAMP : gd32f3x0_rtc.h
  • RTC_INT_TIMESTAMP : gd32f3x0_rtc.h
  • RTC_JAN : gd32f3x0_rtc.h
  • RTC_JUL : gd32f3x0_rtc.h
  • RTC_JUN : gd32f3x0_rtc.h
  • RTC_LOCK_KEY : gd32f3x0_rtc.h
  • RTC_MAR : gd32f3x0_rtc.h
  • RTC_MASKSSC_0_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_10_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_11_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_12_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_13_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_1_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_2_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_3_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_4_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_5_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_6_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_7_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_8_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_9_14 : gd32f3x0_rtc.h
  • RTC_MASKSSC_NONE : gd32f3x0_rtc.h
  • RTC_MAY : gd32f3x0_rtc.h
  • RTC_MONDAY : gd32f3x0_rtc.h
  • RTC_NOV : gd32f3x0_rtc.h
  • RTC_OCT : gd32f3x0_rtc.h
  • RTC_OS_DISABLE : gd32f3x0_rtc.h
  • RTC_OS_ENABLE : gd32f3x0_rtc.h
  • RTC_PM : gd32f3x0_rtc.h
  • RTC_PRCH_1C : gd32f3x0_rtc.h
  • RTC_PRCH_2C : gd32f3x0_rtc.h
  • RTC_PRCH_4C : gd32f3x0_rtc.h
  • RTC_PRCH_8C : gd32f3x0_rtc.h
  • RTC_PSC : gd32f3x0_rtc.h
  • RTC_PSC_FACTOR_A : gd32f3x0_rtc.h
  • RTC_PSC_FACTOR_S : gd32f3x0_rtc.h
  • RTC_PSC_RESET : gd32f3x0_rtc.h
  • RTC_REGISTER_RESET : gd32f3x0_rtc.h
  • RTC_RSYNF_TIMEOUT : gd32f3x0_rtc.h
  • RTC_SATURDAY : gd32f3x0_rtc.h
  • RTC_SEP : gd32f3x0_rtc.h
  • RTC_SHIFT_ADD1S_RESET : gd32f3x0_rtc.h
  • RTC_SHIFT_ADD1S_SET : gd32f3x0_rtc.h
  • RTC_SHIFTCTL : gd32f3x0_rtc.h
  • RTC_SHIFTCTL_A1S : gd32f3x0_rtc.h
  • RTC_SHIFTCTL_SFS : gd32f3x0_rtc.h
  • RTC_SHIFTCTL_TIMEOUT : gd32f3x0_rtc.h
  • RTC_SS : gd32f3x0_rtc.h
  • RTC_SS_SSC : gd32f3x0_rtc.h
  • RTC_SSTS : gd32f3x0_rtc.h
  • RTC_SSTS_SSC : gd32f3x0_rtc.h
  • RTC_STAT : gd32f3x0_rtc.h
  • RTC_STAT_ALRM0F : gd32f3x0_rtc.h
  • RTC_STAT_ALRM0WF : gd32f3x0_rtc.h
  • RTC_STAT_INITF : gd32f3x0_rtc.h
  • RTC_STAT_INITM : gd32f3x0_rtc.h
  • RTC_STAT_RESET : gd32f3x0_rtc.h
  • RTC_STAT_RSYNF : gd32f3x0_rtc.h
  • RTC_STAT_SCPF : gd32f3x0_rtc.h
  • RTC_STAT_SOPF : gd32f3x0_rtc.h
  • RTC_STAT_TP0F : gd32f3x0_rtc.h
  • RTC_STAT_TP1F : gd32f3x0_rtc.h
  • RTC_STAT_TSF : gd32f3x0_rtc.h
  • RTC_STAT_TSOVRF : gd32f3x0_rtc.h
  • RTC_STAT_YCM : gd32f3x0_rtc.h
  • RTC_SUNDAY : gd32f3x0_rtc.h
  • RTC_TAMP : gd32f3x0_rtc.h
  • RTC_TAMP_DISPU : gd32f3x0_rtc.h
  • RTC_TAMP_FLT : gd32f3x0_rtc.h
  • RTC_TAMP_FREQ : gd32f3x0_rtc.h
  • RTC_TAMP_PC13MDE : gd32f3x0_rtc.h
  • RTC_TAMP_PC13VAL : gd32f3x0_rtc.h
  • RTC_TAMP_PC14MDE : gd32f3x0_rtc.h
  • RTC_TAMP_PC14VAL : gd32f3x0_rtc.h
  • RTC_TAMP_PC15MDE : gd32f3x0_rtc.h
  • RTC_TAMP_PC15VAL : gd32f3x0_rtc.h
  • RTC_TAMP_PRCH : gd32f3x0_rtc.h
  • RTC_TAMP_TP0EG : gd32f3x0_rtc.h
  • RTC_TAMP_TP0EN : gd32f3x0_rtc.h
  • RTC_TAMP_TP1EG : gd32f3x0_rtc.h
  • RTC_TAMP_TP1EN : gd32f3x0_rtc.h
  • RTC_TAMP_TPIE : gd32f3x0_rtc.h
  • RTC_TAMP_TPTS : gd32f3x0_rtc.h
  • RTC_TAMPER0 : gd32f3x0_rtc.h
  • RTC_TAMPER1 : gd32f3x0_rtc.h
  • RTC_TAMPER_TRIGGER_EDGE_FALLING : gd32f3x0_rtc.h
  • RTC_TAMPER_TRIGGER_EDGE_RISING : gd32f3x0_rtc.h
  • RTC_TAMPER_TRIGGER_LEVEL_HIGH : gd32f3x0_rtc.h
  • RTC_TAMPER_TRIGGER_LEVEL_LOW : gd32f3x0_rtc.h
  • RTC_TAMPER_TRIGGER_POS : gd32f3x0_rtc.h
  • RTC_THURSDAY : gd32f3x0_rtc.h
  • RTC_TIME : gd32f3x0_rtc.h
  • RTC_TIME_HRT : gd32f3x0_rtc.h
  • RTC_TIME_HRU : gd32f3x0_rtc.h
  • RTC_TIME_MNT : gd32f3x0_rtc.h
  • RTC_TIME_MNU : gd32f3x0_rtc.h
  • RTC_TIME_PM : gd32f3x0_rtc.h
  • RTC_TIME_SCT : gd32f3x0_rtc.h
  • RTC_TIME_SCU : gd32f3x0_rtc.h
  • RTC_TIMESTAMP_FALLING_EDGE : gd32f3x0_rtc.h
  • RTC_TIMESTAMP_RISING_EDGE : gd32f3x0_rtc.h
  • RTC_TTS : gd32f3x0_rtc.h
  • RTC_TTS_HRT : gd32f3x0_rtc.h
  • RTC_TTS_HRU : gd32f3x0_rtc.h
  • RTC_TTS_MNT : gd32f3x0_rtc.h
  • RTC_TTS_MNU : gd32f3x0_rtc.h
  • RTC_TTS_PM : gd32f3x0_rtc.h
  • RTC_TTS_SCT : gd32f3x0_rtc.h
  • RTC_TTS_SCU : gd32f3x0_rtc.h
  • RTC_TUESDAY : gd32f3x0_rtc.h
  • RTC_UNLOCK_KEY1 : gd32f3x0_rtc.h
  • RTC_UNLOCK_KEY2 : gd32f3x0_rtc.h
  • RTC_WEDSDAY : gd32f3x0_rtc.h
  • RTC_WPK : gd32f3x0_rtc.h
  • RTC_WPK_WPK : gd32f3x0_rtc.h
  • RX_MAX_DATA_LENGTH : usb_core.h
  • RXSTAT_DATA_UPDT : usb_defines.h
  • RXSTAT_GOUT_NAK : usb_defines.h
  • RXSTAT_SETUP_COMP : usb_defines.h
  • RXSTAT_SETUP_UPDT : usb_defines.h
  • RXSTAT_XFER_COMP : usb_defines.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
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  • Typedefs
  • Enumerations
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- s -

  • SADDR0_ADDFORMAT : gd32f3x0_i2c.h
  • SAMPTX_SPT : gd32f3x0_adc.h
  • SCB_LPM_DEEPSLEEP : gd32f3x0_misc.h
  • SCB_LPM_SLEEP_EXIT_ISR : gd32f3x0_misc.h
  • SCB_LPM_WAKE_BY_ALL_INT : gd32f3x0_misc.h
  • SCB_SCR_SEVONPEND : gd32f3x0_misc.h
  • SCB_SCR_SLEEPDEEP : gd32f3x0_misc.h
  • SCB_SCR_SLEEPONEXIT : gd32f3x0_misc.h
  • SEL_HXTAL : gd32f3x0_rcu.c , system_gd32f3x0.c
  • SEL_IRC8M : gd32f3x0_rcu.c , system_gd32f3x0.c
  • SEL_PLL : gd32f3x0_rcu.c , system_gd32f3x0.c
  • SHIFTCTL_SFS : gd32f3x0_rtc.h
  • SMCFG_ETPSC : gd32f3x0_timer.h
  • SMCFG_SMC : gd32f3x0_timer.h
  • SMCFG_TRGSEL : gd32f3x0_timer.h
  • SPI0 : gd32f3x0_spi.h
  • SPI1 : gd32f3x0_spi.h
  • SPI2 : gd32f3x0_spi.h
  • SPI_BIDIRECTIONAL_RECEIVE : gd32f3x0_spi.h
  • SPI_BIDIRECTIONAL_TRANSMIT : gd32f3x0_spi.h
  • SPI_CK_PL_HIGH_PH_1EDGE : gd32f3x0_spi.h
  • SPI_CK_PL_HIGH_PH_2EDGE : gd32f3x0_spi.h
  • SPI_CK_PL_LOW_PH_1EDGE : gd32f3x0_spi.h
  • SPI_CK_PL_LOW_PH_2EDGE : gd32f3x0_spi.h
  • SPI_CRC_RX : gd32f3x0_spi.h
  • SPI_CRC_TX : gd32f3x0_spi.h
  • SPI_CRCPOLY : gd32f3x0_spi.h
  • SPI_CRCPOLY_CPR : gd32f3x0_spi.h
  • SPI_CTL0 : gd32f3x0_spi.h
  • SPI_CTL0_BDEN : gd32f3x0_spi.h
  • SPI_CTL0_BDOEN : gd32f3x0_spi.h
  • SPI_CTL0_CKPH : gd32f3x0_spi.h
  • SPI_CTL0_CKPL : gd32f3x0_spi.h
  • SPI_CTL0_CRCEN : gd32f3x0_spi.h
  • SPI_CTL0_CRCNT : gd32f3x0_spi.h
  • SPI_CTL0_FF16 : gd32f3x0_spi.h
  • SPI_CTL0_LF : gd32f3x0_spi.h
  • SPI_CTL0_MSTMOD : gd32f3x0_spi.h
  • SPI_CTL0_PSC : gd32f3x0_spi.h
  • SPI_CTL0_RO : gd32f3x0_spi.h
  • SPI_CTL0_SPIEN : gd32f3x0_spi.h
  • SPI_CTL0_SWNSS : gd32f3x0_spi.h
  • SPI_CTL0_SWNSSEN : gd32f3x0_spi.h
  • SPI_CTL1 : gd32f3x0_spi.h
  • SPI_CTL1_DMAREN : gd32f3x0_spi.h
  • SPI_CTL1_DMATEN : gd32f3x0_spi.h
  • SPI_CTL1_ERRIE : gd32f3x0_spi.h
  • SPI_CTL1_NSSDRV : gd32f3x0_spi.h
  • SPI_CTL1_NSSP : gd32f3x0_spi.h
  • SPI_CTL1_RBNEIE : gd32f3x0_spi.h
  • SPI_CTL1_TBEIE : gd32f3x0_spi.h
  • SPI_CTL1_TMOD : gd32f3x0_spi.h
  • SPI_DATA : gd32f3x0_spi.h
  • SPI_DATA_DATA : gd32f3x0_spi.h
  • SPI_DMA_RECEIVE : gd32f3x0_spi.h
  • SPI_DMA_TRANSMIT : gd32f3x0_spi.h
  • SPI_ENDIAN_LSB : gd32f3x0_spi.h
  • SPI_ENDIAN_MSB : gd32f3x0_spi.h
  • SPI_FLAG_CONFERR : gd32f3x0_spi.h
  • SPI_FLAG_CRCERR : gd32f3x0_spi.h
  • SPI_FLAG_FERR : gd32f3x0_spi.h
  • SPI_FLAG_RBNE : gd32f3x0_spi.h
  • SPI_FLAG_RXORERR : gd32f3x0_spi.h
  • SPI_FLAG_TBE : gd32f3x0_spi.h
  • SPI_FLAG_TRANS : gd32f3x0_spi.h
  • SPI_FRAMESIZE_16BIT : gd32f3x0_spi.h
  • SPI_FRAMESIZE_8BIT : gd32f3x0_spi.h
  • SPI_I2S_INT_ERR : gd32f3x0_spi.h
  • SPI_I2S_INT_FLAG_FERR : gd32f3x0_spi.h
  • SPI_I2S_INT_FLAG_RBNE : gd32f3x0_spi.h
  • SPI_I2S_INT_FLAG_RXORERR : gd32f3x0_spi.h
  • SPI_I2S_INT_FLAG_TBE : gd32f3x0_spi.h
  • SPI_I2S_INT_RBNE : gd32f3x0_spi.h
  • SPI_I2S_INT_TBE : gd32f3x0_spi.h
  • SPI_I2SCTL : gd32f3x0_spi.h
  • SPI_I2SCTL_CHLEN : gd32f3x0_spi.h
  • SPI_I2SCTL_CKPL : gd32f3x0_spi.h
  • SPI_I2SCTL_DTLEN : gd32f3x0_spi.h
  • SPI_I2SCTL_I2SEN : gd32f3x0_spi.h
  • SPI_I2SCTL_I2SOPMOD : gd32f3x0_spi.h
  • SPI_I2SCTL_I2SSEL : gd32f3x0_spi.h
  • SPI_I2SCTL_I2SSTD : gd32f3x0_spi.h
  • SPI_I2SCTL_PCMSMOD : gd32f3x0_spi.h
  • SPI_I2SPSC : gd32f3x0_spi.h
  • SPI_I2SPSC_DIV : gd32f3x0_spi.h
  • SPI_I2SPSC_MCKOEN : gd32f3x0_spi.h
  • SPI_I2SPSC_OF : gd32f3x0_spi.h
  • SPI_I2SPSC_RESET : gd32f3x0_spi.c
  • SPI_INIT_MASK : gd32f3x0_spi.c
  • SPI_INT_FLAG_CONFERR : gd32f3x0_spi.h
  • SPI_INT_FLAG_CRCERR : gd32f3x0_spi.h
  • SPI_MASTER : gd32f3x0_spi.h
  • SPI_NSS_HARD : gd32f3x0_spi.h
  • SPI_NSS_SOFT : gd32f3x0_spi.h
  • SPI_PSC_128 : gd32f3x0_spi.h
  • SPI_PSC_16 : gd32f3x0_spi.h
  • SPI_PSC_2 : gd32f3x0_spi.h
  • SPI_PSC_256 : gd32f3x0_spi.h
  • SPI_PSC_32 : gd32f3x0_spi.h
  • SPI_PSC_4 : gd32f3x0_spi.h
  • SPI_PSC_64 : gd32f3x0_spi.h
  • SPI_PSC_8 : gd32f3x0_spi.h
  • SPI_QCTL : gd32f3x0_spi.h
  • SPI_QCTL_IO23_DRV : gd32f3x0_spi.h
  • SPI_QCTL_QMOD : gd32f3x0_spi.h
  • SPI_QCTL_QRD : gd32f3x0_spi.h
  • SPI_RCRC : gd32f3x0_spi.h
  • SPI_RCRC_RCR : gd32f3x0_spi.h
  • SPI_SLAVE : gd32f3x0_spi.h
  • SPI_STAT : gd32f3x0_spi.h
  • SPI_STAT_CONFERR : gd32f3x0_spi.h
  • SPI_STAT_CRCERR : gd32f3x0_spi.h
  • SPI_STAT_FERR : gd32f3x0_spi.h
  • SPI_STAT_I2SCH : gd32f3x0_spi.h
  • SPI_STAT_RBNE : gd32f3x0_spi.h
  • SPI_STAT_RXORERR : gd32f3x0_spi.h
  • SPI_STAT_TBE : gd32f3x0_spi.h
  • SPI_STAT_TRANS : gd32f3x0_spi.h
  • SPI_STAT_TXURERR : gd32f3x0_spi.h
  • SPI_TCRC : gd32f3x0_spi.h
  • SPI_TCRC_TCR : gd32f3x0_spi.h
  • SPI_TRANSMODE_BDRECEIVE : gd32f3x0_spi.h
  • SPI_TRANSMODE_BDTRANSMIT : gd32f3x0_spi.h
  • SPI_TRANSMODE_FULLDUPLEX : gd32f3x0_spi.h
  • SPI_TRANSMODE_RECEIVEONLY : gd32f3x0_spi.h
  • SS_SSC : gd32f3x0_rtc.h
  • SSTS_SSC : gd32f3x0_rtc.h
  • SWAPBYTE : usb_std.h
  • SYSCFG : gd32f3x0_syscfg.h
  • SYSCFG_CFG0 : gd32f3x0_syscfg.h
  • SYSCFG_CFG0_ADC_DMA_RMP : gd32f3x0_syscfg.h
  • SYSCFG_CFG0_BOOT_MODE : gd32f3x0_syscfg.h
  • SYSCFG_CFG0_PB9_HCCE : gd32f3x0_syscfg.h
  • SYSCFG_CFG0_TIMER15_DMA_RMP : gd32f3x0_syscfg.h
  • SYSCFG_CFG0_TIMER16_DMA_RMP : gd32f3x0_syscfg.h
  • SYSCFG_CFG0_USART0_RX_DMA_RMP : gd32f3x0_syscfg.h
  • SYSCFG_CFG0_USART0_TX_DMA_RMP : gd32f3x0_syscfg.h
  • SYSCFG_CFG2 : gd32f3x0_syscfg.h
  • SYSCFG_CFG2_LOCKUP_LOCK : gd32f3x0_syscfg.h
  • SYSCFG_CFG2_LVD_LOCK : gd32f3x0_syscfg.h
  • SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK : gd32f3x0_syscfg.h
  • SYSCFG_CFG2_SRAM_PCEF : gd32f3x0_syscfg.h
  • SYSCFG_COMPENSATION : gd32f3x0_syscfg.h
  • SYSCFG_COMPENSATION_DISABLE : gd32f3x0_syscfg.h
  • SYSCFG_COMPENSATION_ENABLE : gd32f3x0_syscfg.h
  • SYSCFG_CPSCTL : gd32f3x0_syscfg.h
  • SYSCFG_CPSCTL_CPS_EN : gd32f3x0_syscfg.h
  • SYSCFG_CPSCTL_CPS_RDY : gd32f3x0_syscfg.h
  • SYSCFG_DMA_REMAP_ADC : gd32f3x0_syscfg.h
  • SYSCFG_DMA_REMAP_TIMER15 : gd32f3x0_syscfg.h
  • SYSCFG_DMA_REMAP_TIMER16 : gd32f3x0_syscfg.h
  • SYSCFG_DMA_REMAP_USART0RX : gd32f3x0_syscfg.h
  • SYSCFG_DMA_REMAP_USART0TX : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS0 : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS0_EXTI0_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS0_EXTI1_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS0_EXTI2_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS0_EXTI3_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS1 : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS1_EXTI4_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS1_EXTI5_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS1_EXTI6_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS1_EXTI7_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS2 : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS2_EXTI10_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS2_EXTI11_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS2_EXTI8_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS2_EXTI9_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS3 : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS3_EXTI12_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS3_EXTI13_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS3_EXTI14_SS : gd32f3x0_syscfg.h
  • SYSCFG_EXTISS3_EXTI15_SS : gd32f3x0_syscfg.h
  • SYSCFG_HIGH_CURRENT_DISABLE : gd32f3x0_syscfg.h
  • SYSCFG_HIGH_CURRENT_ENABLE : gd32f3x0_syscfg.h
  • SYSCFG_LOCK_LOCKUP : gd32f3x0_syscfg.h
  • SYSCFG_LOCK_LVD : gd32f3x0_syscfg.h
  • SYSCFG_LOCK_SRAM_PARITY_ERROR : gd32f3x0_syscfg.h
  • SYSCFG_SRAM_PCEF : gd32f3x0_syscfg.h
  • SYSTICK_CLKSOURCE_HCLK : gd32f3x0_misc.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : gd32f3x0_misc.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
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  • Enumerations
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- t -

  • TAMP_FLT : gd32f3x0_rtc.h
  • TAMP_FREQ : gd32f3x0_rtc.h
  • TAMP_PRCH : gd32f3x0_rtc.h
  • TIME_HR : gd32f3x0_rtc.h
  • TIME_MN : gd32f3x0_rtc.h
  • TIME_SC : gd32f3x0_rtc.h
  • TIMER0 : gd32f3x0_timer.h
  • TIMER1 : gd32f3x0_timer.h
  • TIMER13 : gd32f3x0_timer.h
  • TIMER13_CI0_RMP_CKOUTSEL : gd32f3x0_timer.h
  • TIMER13_CI0_RMP_GPIO : gd32f3x0_timer.h
  • TIMER13_CI0_RMP_HXTAL_DIV32 : gd32f3x0_timer.h
  • TIMER13_CI0_RMP_RTCCLK : gd32f3x0_timer.h
  • TIMER13_IRMP : gd32f3x0_timer.h
  • TIMER13_IRMP_CI0_RMP : gd32f3x0_timer.h
  • TIMER14 : gd32f3x0_timer.h
  • TIMER15 : gd32f3x0_timer.h
  • TIMER16 : gd32f3x0_timer.h
  • TIMER2 : gd32f3x0_timer.h
  • TIMER_BREAK_DISABLE : gd32f3x0_timer.h
  • TIMER_BREAK_ENABLE : gd32f3x0_timer.h
  • TIMER_BREAK_POLARITY_HIGH : gd32f3x0_timer.h
  • TIMER_BREAK_POLARITY_LOW : gd32f3x0_timer.h
  • TIMER_CAR : gd32f3x0_timer.h
  • TIMER_CAR_CARL16 : gd32f3x0_timer.h
  • TIMER_CAR_CARL32 : gd32f3x0_timer.h
  • TIMER_CCHP : gd32f3x0_timer.h
  • TIMER_CCHP_BRKEN : gd32f3x0_timer.h
  • TIMER_CCHP_BRKP : gd32f3x0_timer.h
  • TIMER_CCHP_DTCFG : gd32f3x0_timer.h
  • TIMER_CCHP_IOS : gd32f3x0_timer.h
  • TIMER_CCHP_OAEN : gd32f3x0_timer.h
  • TIMER_CCHP_POEN : gd32f3x0_timer.h
  • TIMER_CCHP_PROT : gd32f3x0_timer.h
  • TIMER_CCHP_PROT_0 : gd32f3x0_timer.h
  • TIMER_CCHP_PROT_1 : gd32f3x0_timer.h
  • TIMER_CCHP_PROT_2 : gd32f3x0_timer.h
  • TIMER_CCHP_PROT_OFF : gd32f3x0_timer.h
  • TIMER_CCHP_ROS : gd32f3x0_timer.h
  • TIMER_CCSEL_DISABLE : gd32f3x0_timer.h
  • TIMER_CCSEL_ENABLE : gd32f3x0_timer.h
  • TIMER_CCX_DISABLE : gd32f3x0_timer.h
  • TIMER_CCX_ENABLE : gd32f3x0_timer.h
  • TIMER_CCXN_DISABLE : gd32f3x0_timer.h
  • TIMER_CCXN_ENABLE : gd32f3x0_timer.h
  • TIMER_CFG : gd32f3x0_timer.h
  • TIMER_CFG_CHVSEL : gd32f3x0_timer.h
  • TIMER_CFG_OUTSEL : gd32f3x0_timer.h
  • TIMER_CH0CV : gd32f3x0_timer.h
  • TIMER_CH0CV_CH0VAL16 : gd32f3x0_timer.h
  • TIMER_CH0CV_CH0VAL32 : gd32f3x0_timer.h
  • TIMER_CH1CV : gd32f3x0_timer.h
  • TIMER_CH1CV_CH1VAL16 : gd32f3x0_timer.h
  • TIMER_CH1CV_CH1VAL32 : gd32f3x0_timer.h
  • TIMER_CH2CV : gd32f3x0_timer.h
  • TIMER_CH2CV_CH2VAL16 : gd32f3x0_timer.h
  • TIMER_CH2CV_CH2VAL32 : gd32f3x0_timer.h
  • TIMER_CH3CV : gd32f3x0_timer.h
  • TIMER_CH3CV_CH3VAL16 : gd32f3x0_timer.h
  • TIMER_CH3CV_CH3VAL32 : gd32f3x0_timer.h
  • TIMER_CH_0 : gd32f3x0_timer.h
  • TIMER_CH_1 : gd32f3x0_timer.h
  • TIMER_CH_2 : gd32f3x0_timer.h
  • TIMER_CH_3 : gd32f3x0_timer.h
  • TIMER_CHCTL0 : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH0CAPFLT : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH0CAPPSC : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH0COMCEN : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH0COMCTL : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH0COMFEN : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH0COMSEN : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH0MS : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH1CAPFLT : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH1CAPPSC : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH1COMCEN : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH1COMCTL : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH1COMFEN : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH1COMSEN : gd32f3x0_timer.h
  • TIMER_CHCTL0_CH1MS : gd32f3x0_timer.h
  • TIMER_CHCTL1 : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH2CAPFLT : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH2CAPPSC : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH2COMCEN : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH2COMCTL : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH2COMFEN : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH2COMSEN : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH2MS : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH3CAPFLT : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH3CAPPSC : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH3COMCEN : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH3COMCTL : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH3COMFEN : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH3COMSEN : gd32f3x0_timer.h
  • TIMER_CHCTL1_CH3MS : gd32f3x0_timer.h
  • TIMER_CHCTL2 : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH0EN : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH0NEN : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH0NP : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH0P : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH1EN : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH1NEN : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH1NP : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH1P : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH2EN : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH2NEN : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH2NP : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH2P : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH3EN : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH3NP : gd32f3x0_timer.h
  • TIMER_CHCTL2_CH3P : gd32f3x0_timer.h
  • TIMER_CKDIV_DIV1 : gd32f3x0_timer.h
  • TIMER_CKDIV_DIV2 : gd32f3x0_timer.h
  • TIMER_CKDIV_DIV4 : gd32f3x0_timer.h
  • TIMER_CNT : gd32f3x0_timer.h
  • TIMER_CNT_CNT16 : gd32f3x0_timer.h
  • TIMER_CNT_CNT32 : gd32f3x0_timer.h
  • TIMER_COUNTER_CENTER_BOTH : gd32f3x0_timer.h
  • TIMER_COUNTER_CENTER_DOWN : gd32f3x0_timer.h
  • TIMER_COUNTER_CENTER_UP : gd32f3x0_timer.h
  • TIMER_COUNTER_DOWN : gd32f3x0_timer.h
  • TIMER_COUNTER_EDGE : gd32f3x0_timer.h
  • TIMER_COUNTER_UP : gd32f3x0_timer.h
  • TIMER_CREP : gd32f3x0_timer.h
  • TIMER_CREP_CREP : gd32f3x0_timer.h
  • TIMER_CTL0 : gd32f3x0_timer.h
  • TIMER_CTL0_ARSE : gd32f3x0_timer.h
  • TIMER_CTL0_CAM : gd32f3x0_timer.h
  • TIMER_CTL0_CEN : gd32f3x0_timer.h
  • TIMER_CTL0_CKDIV : gd32f3x0_timer.h
  • TIMER_CTL0_DIR : gd32f3x0_timer.h
  • TIMER_CTL0_SPM : gd32f3x0_timer.h
  • TIMER_CTL0_UPDIS : gd32f3x0_timer.h
  • TIMER_CTL0_UPS : gd32f3x0_timer.h
  • TIMER_CTL1 : gd32f3x0_timer.h
  • TIMER_CTL1_CCSE : gd32f3x0_timer.h
  • TIMER_CTL1_CCUC : gd32f3x0_timer.h
  • TIMER_CTL1_DMAS : gd32f3x0_timer.h
  • TIMER_CTL1_ISO0 : gd32f3x0_timer.h
  • TIMER_CTL1_ISO0N : gd32f3x0_timer.h
  • TIMER_CTL1_ISO1 : gd32f3x0_timer.h
  • TIMER_CTL1_ISO1N : gd32f3x0_timer.h
  • TIMER_CTL1_ISO2 : gd32f3x0_timer.h
  • TIMER_CTL1_ISO2N : gd32f3x0_timer.h
  • TIMER_CTL1_ISO3 : gd32f3x0_timer.h
  • TIMER_CTL1_MMC : gd32f3x0_timer.h
  • TIMER_CTL1_TI0S : gd32f3x0_timer.h
  • TIMER_DMA_CH0D : gd32f3x0_timer.h
  • TIMER_DMA_CH1D : gd32f3x0_timer.h
  • TIMER_DMA_CH2D : gd32f3x0_timer.h
  • TIMER_DMA_CH3D : gd32f3x0_timer.h
  • TIMER_DMA_CMTD : gd32f3x0_timer.h
  • TIMER_DMA_TRGD : gd32f3x0_timer.h
  • TIMER_DMA_UPD : gd32f3x0_timer.h
  • TIMER_DMACFG : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CAR : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CCHP : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CH0CV : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CH1CV : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CH2CV : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CH3CV : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CHCTL0 : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CHCTL1 : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CHCTL2 : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CNT : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CREP : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CTL0 : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_CTL1 : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_DMACFG : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_DMAINTEN : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_DMATB : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_INTF : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_PSC : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_SMCFG : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATA_SWEVG : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_10TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_11TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_12TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_13TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_14TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_15TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_16TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_17TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_18TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_1TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_2TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_3TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_4TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_5TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_6TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_7TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_8TRANSFER : gd32f3x0_timer.h
  • TIMER_DMACFG_DMATC_9TRANSFER : gd32f3x0_timer.h
  • TIMER_DMAINTEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_BRKIE : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH0DEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH0IE : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH1DEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH1IE : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH2DEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH2IE : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH3DEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CH3IE : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CMTDEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_CMTIE : gd32f3x0_timer.h
  • TIMER_DMAINTEN_TRGDEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_TRGIE : gd32f3x0_timer.h
  • TIMER_DMAINTEN_UPDEN : gd32f3x0_timer.h
  • TIMER_DMAINTEN_UPIE : gd32f3x0_timer.h
  • TIMER_DMAREQUEST_CHANNELEVENT : gd32f3x0_timer.h
  • TIMER_DMAREQUEST_UPDATEEVENT : gd32f3x0_timer.h
  • TIMER_DMATB : gd32f3x0_timer.h
  • TIMER_DMATB_DMATB : gd32f3x0_timer.h
  • TIMER_ENCODER_MODE0 : gd32f3x0_timer.h
  • TIMER_ENCODER_MODE1 : gd32f3x0_timer.h
  • TIMER_ENCODER_MODE2 : gd32f3x0_timer.h
  • TIMER_ETP_FALLING : gd32f3x0_timer.h
  • TIMER_ETP_RISING : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_BRKG : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_CH0G : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_CH1G : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_CH2G : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_CH3G : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_CMTG : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_TRGG : gd32f3x0_timer.h
  • TIMER_EVENT_SRC_UPG : gd32f3x0_timer.h
  • TIMER_EXT_TRI_PSC_DIV2 : gd32f3x0_timer.h
  • TIMER_EXT_TRI_PSC_DIV4 : gd32f3x0_timer.h
  • TIMER_EXT_TRI_PSC_DIV8 : gd32f3x0_timer.h
  • TIMER_EXT_TRI_PSC_OFF : gd32f3x0_timer.h
  • TIMER_FLAG_BRK : gd32f3x0_timer.h
  • TIMER_FLAG_CH0 : gd32f3x0_timer.h
  • TIMER_FLAG_CH0O : gd32f3x0_timer.h
  • TIMER_FLAG_CH1 : gd32f3x0_timer.h
  • TIMER_FLAG_CH1O : gd32f3x0_timer.h
  • TIMER_FLAG_CH2 : gd32f3x0_timer.h
  • TIMER_FLAG_CH2O : gd32f3x0_timer.h
  • TIMER_FLAG_CH3 : gd32f3x0_timer.h
  • TIMER_FLAG_CH3O : gd32f3x0_timer.h
  • TIMER_FLAG_CMT : gd32f3x0_timer.h
  • TIMER_FLAG_TRG : gd32f3x0_timer.h
  • TIMER_FLAG_UP : gd32f3x0_timer.h
  • TIMER_HALLINTERFACE_DISABLE : gd32f3x0_timer.h
  • TIMER_HALLINTERFACE_ENABLE : gd32f3x0_timer.h
  • TIMER_IC_POLARITY_BOTH_EDGE : gd32f3x0_timer.h
  • TIMER_IC_POLARITY_FALLING : gd32f3x0_timer.h
  • TIMER_IC_POLARITY_RISING : gd32f3x0_timer.h
  • TIMER_IC_PSC_DIV1 : gd32f3x0_timer.h
  • TIMER_IC_PSC_DIV2 : gd32f3x0_timer.h
  • TIMER_IC_PSC_DIV4 : gd32f3x0_timer.h
  • TIMER_IC_PSC_DIV8 : gd32f3x0_timer.h
  • TIMER_IC_SELECTION_DIRECTTI : gd32f3x0_timer.h
  • TIMER_IC_SELECTION_INDIRECTTI : gd32f3x0_timer.h
  • TIMER_IC_SELECTION_ITS : gd32f3x0_timer.h
  • TIMER_INT_BRK : gd32f3x0_timer.h
  • TIMER_INT_CH0 : gd32f3x0_timer.h
  • TIMER_INT_CH1 : gd32f3x0_timer.h
  • TIMER_INT_CH2 : gd32f3x0_timer.h
  • TIMER_INT_CH3 : gd32f3x0_timer.h
  • TIMER_INT_CMT : gd32f3x0_timer.h
  • TIMER_INT_FLAG_BRK : gd32f3x0_timer.h
  • TIMER_INT_FLAG_CH0 : gd32f3x0_timer.h
  • TIMER_INT_FLAG_CH1 : gd32f3x0_timer.h
  • TIMER_INT_FLAG_CH2 : gd32f3x0_timer.h
  • TIMER_INT_FLAG_CH3 : gd32f3x0_timer.h
  • TIMER_INT_FLAG_CMT : gd32f3x0_timer.h
  • TIMER_INT_FLAG_TRG : gd32f3x0_timer.h
  • TIMER_INT_FLAG_UP : gd32f3x0_timer.h
  • TIMER_INT_TRG : gd32f3x0_timer.h
  • TIMER_INT_UP : gd32f3x0_timer.h
  • TIMER_INTF : gd32f3x0_timer.h
  • TIMER_INTF_BRKIF : gd32f3x0_timer.h
  • TIMER_INTF_CH0IF : gd32f3x0_timer.h
  • TIMER_INTF_CH0OF : gd32f3x0_timer.h
  • TIMER_INTF_CH1IF : gd32f3x0_timer.h
  • TIMER_INTF_CH1OF : gd32f3x0_timer.h
  • TIMER_INTF_CH2IF : gd32f3x0_timer.h
  • TIMER_INTF_CH2OF : gd32f3x0_timer.h
  • TIMER_INTF_CH3IF : gd32f3x0_timer.h
  • TIMER_INTF_CH3OF : gd32f3x0_timer.h
  • TIMER_INTF_CMTIF : gd32f3x0_timer.h
  • TIMER_INTF_TRGIF : gd32f3x0_timer.h
  • TIMER_INTF_UPIF : gd32f3x0_timer.h
  • TIMER_IOS_STATE_DISABLE : gd32f3x0_timer.h
  • TIMER_IOS_STATE_ENABLE : gd32f3x0_timer.h
  • TIMER_IRMP : gd32f3x0_timer.h
  • TIMER_MASTER_SLAVE_MODE_DISABLE : gd32f3x0_timer.h
  • TIMER_MASTER_SLAVE_MODE_ENABLE : gd32f3x0_timer.h
  • TIMER_OC_CLEAR_DISABLE : gd32f3x0_timer.h
  • TIMER_OC_CLEAR_ENABLE : gd32f3x0_timer.h
  • TIMER_OC_FAST_DISABLE : gd32f3x0_timer.h
  • TIMER_OC_FAST_ENABLE : gd32f3x0_timer.h
  • TIMER_OC_IDLE_STATE_HIGH : gd32f3x0_timer.h
  • TIMER_OC_IDLE_STATE_LOW : gd32f3x0_timer.h
  • TIMER_OC_MODE_ACTIVE : gd32f3x0_timer.h
  • TIMER_OC_MODE_HIGH : gd32f3x0_timer.h
  • TIMER_OC_MODE_INACTIVE : gd32f3x0_timer.h
  • TIMER_OC_MODE_LOW : gd32f3x0_timer.h
  • TIMER_OC_MODE_PWM0 : gd32f3x0_timer.h
  • TIMER_OC_MODE_PWM1 : gd32f3x0_timer.h
  • TIMER_OC_MODE_TIMING : gd32f3x0_timer.h
  • TIMER_OC_MODE_TOGGLE : gd32f3x0_timer.h
  • TIMER_OC_POLARITY_HIGH : gd32f3x0_timer.h
  • TIMER_OC_POLARITY_LOW : gd32f3x0_timer.h
  • TIMER_OC_SHADOW_DISABLE : gd32f3x0_timer.h
  • TIMER_OC_SHADOW_ENABLE : gd32f3x0_timer.h
  • TIMER_OCN_IDLE_STATE_HIGH : gd32f3x0_timer.h
  • TIMER_OCN_IDLE_STATE_LOW : gd32f3x0_timer.h
  • TIMER_OCN_POLARITY_HIGH : gd32f3x0_timer.h
  • TIMER_OCN_POLARITY_LOW : gd32f3x0_timer.h
  • TIMER_OCPRE_CLEAR_SOURCE_CLR : gd32f3x0_timer.h
  • TIMER_OCPRE_CLEAR_SOURCE_ETIF : gd32f3x0_timer.h
  • TIMER_OUTAUTO_DISABLE : gd32f3x0_timer.h
  • TIMER_OUTAUTO_ENABLE : gd32f3x0_timer.h
  • TIMER_OUTSEL_DISABLE : gd32f3x0_timer.h
  • TIMER_OUTSEL_ENABLE : gd32f3x0_timer.h
  • TIMER_PSC : gd32f3x0_timer.h
  • TIMER_PSC_PSC : gd32f3x0_timer.h
  • TIMER_PSC_RELOAD_NOW : gd32f3x0_timer.h
  • TIMER_PSC_RELOAD_UPDATE : gd32f3x0_timer.h
  • TIMER_ROS_STATE_DISABLE : gd32f3x0_timer.h
  • TIMER_ROS_STATE_ENABLE : gd32f3x0_timer.h
  • TIMER_SLAVE_MODE_DISABLE : gd32f3x0_timer.h
  • TIMER_SLAVE_MODE_EVENT : gd32f3x0_timer.h
  • TIMER_SLAVE_MODE_EXTERNAL0 : gd32f3x0_timer.h
  • TIMER_SLAVE_MODE_PAUSE : gd32f3x0_timer.h
  • TIMER_SLAVE_MODE_RESTART : gd32f3x0_timer.h
  • TIMER_SMCFG : gd32f3x0_timer.h
  • TIMER_SMCFG_ETFC : gd32f3x0_timer.h
  • TIMER_SMCFG_ETP : gd32f3x0_timer.h
  • TIMER_SMCFG_ETPSC : gd32f3x0_timer.h
  • TIMER_SMCFG_MSM : gd32f3x0_timer.h
  • TIMER_SMCFG_OCRC : gd32f3x0_timer.h
  • TIMER_SMCFG_SMC : gd32f3x0_timer.h
  • TIMER_SMCFG_SMC1 : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGS : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_CI0F_ED : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_CI0FE0 : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_CI1FE1 : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_ETIFP : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_ITI0 : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_ITI1 : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_ITI2 : gd32f3x0_timer.h
  • TIMER_SMCFG_TRGSEL_ITI3 : gd32f3x0_timer.h
  • TIMER_SP_MODE_REPETITIVE : gd32f3x0_timer.h
  • TIMER_SP_MODE_SINGLE : gd32f3x0_timer.h
  • TIMER_SWEVG : gd32f3x0_timer.h
  • TIMER_SWEVG_BRKG : gd32f3x0_timer.h
  • TIMER_SWEVG_CH0G : gd32f3x0_timer.h
  • TIMER_SWEVG_CH1G : gd32f3x0_timer.h
  • TIMER_SWEVG_CH2G : gd32f3x0_timer.h
  • TIMER_SWEVG_CH3G : gd32f3x0_timer.h
  • TIMER_SWEVG_CMTG : gd32f3x0_timer.h
  • TIMER_SWEVG_TRGG : gd32f3x0_timer.h
  • TIMER_SWEVG_UPG : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_CC0 : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_ENABLE : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_O0CPRE : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_O1CPRE : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_O2CPRE : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_O3CPRE : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_RESET : gd32f3x0_timer.h
  • TIMER_TRI_OUT_SRC_UPDATE : gd32f3x0_timer.h
  • TIMER_UPDATE_SRC_GLOBAL : gd32f3x0_timer.h
  • TIMER_UPDATE_SRC_REGULAR : gd32f3x0_timer.h
  • TIMER_UPDATECTL_CCU : gd32f3x0_timer.h
  • TIMER_UPDATECTL_CCUTRI : gd32f3x0_timer.h
  • TSI : gd32f3x0_tsi.h
  • TSI_ASW : gd32f3x0_tsi.h
  • TSI_ASW_G0P0 : gd32f3x0_tsi.h
  • TSI_ASW_G0P1 : gd32f3x0_tsi.h
  • TSI_ASW_G0P2 : gd32f3x0_tsi.h
  • TSI_ASW_G0P3 : gd32f3x0_tsi.h
  • TSI_ASW_G1P0 : gd32f3x0_tsi.h
  • TSI_ASW_G1P1 : gd32f3x0_tsi.h
  • TSI_ASW_G1P2 : gd32f3x0_tsi.h
  • TSI_ASW_G1P3 : gd32f3x0_tsi.h
  • TSI_ASW_G2P0 : gd32f3x0_tsi.h
  • TSI_ASW_G2P1 : gd32f3x0_tsi.h
  • TSI_ASW_G2P2 : gd32f3x0_tsi.h
  • TSI_ASW_G2P3 : gd32f3x0_tsi.h
  • TSI_ASW_G3P0 : gd32f3x0_tsi.h
  • TSI_ASW_G3P1 : gd32f3x0_tsi.h
  • TSI_ASW_G3P2 : gd32f3x0_tsi.h
  • TSI_ASW_G3P3 : gd32f3x0_tsi.h
  • TSI_ASW_G4P0 : gd32f3x0_tsi.h
  • TSI_ASW_G4P1 : gd32f3x0_tsi.h
  • TSI_ASW_G4P2 : gd32f3x0_tsi.h
  • TSI_ASW_G4P3 : gd32f3x0_tsi.h
  • TSI_ASW_G5P0 : gd32f3x0_tsi.h
  • TSI_ASW_G5P1 : gd32f3x0_tsi.h
  • TSI_ASW_G5P2 : gd32f3x0_tsi.h
  • TSI_ASW_G5P3 : gd32f3x0_tsi.h
  • TSI_CHARGE_10CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_11CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_12CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_13CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_14CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_15CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_16CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_1CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_2CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_3CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_4CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_5CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_6CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_7CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_8CTCLK : gd32f3x0_tsi.h
  • TSI_CHARGE_9CTCLK : gd32f3x0_tsi.h
  • TSI_CHCFG : gd32f3x0_tsi.h
  • TSI_CHCFG_G0P0 : gd32f3x0_tsi.h
  • TSI_CHCFG_G0P1 : gd32f3x0_tsi.h
  • TSI_CHCFG_G0P2 : gd32f3x0_tsi.h
  • TSI_CHCFG_G0P3 : gd32f3x0_tsi.h
  • TSI_CHCFG_G1P0 : gd32f3x0_tsi.h
  • TSI_CHCFG_G1P1 : gd32f3x0_tsi.h
  • TSI_CHCFG_G1P2 : gd32f3x0_tsi.h
  • TSI_CHCFG_G1P3 : gd32f3x0_tsi.h
  • TSI_CHCFG_G2P0 : gd32f3x0_tsi.h
  • TSI_CHCFG_G2P1 : gd32f3x0_tsi.h
  • TSI_CHCFG_G2P2 : gd32f3x0_tsi.h
  • TSI_CHCFG_G2P3 : gd32f3x0_tsi.h
  • TSI_CHCFG_G3P0 : gd32f3x0_tsi.h
  • TSI_CHCFG_G3P1 : gd32f3x0_tsi.h
  • TSI_CHCFG_G3P2 : gd32f3x0_tsi.h
  • TSI_CHCFG_G3P3 : gd32f3x0_tsi.h
  • TSI_CHCFG_G4P0 : gd32f3x0_tsi.h
  • TSI_CHCFG_G4P1 : gd32f3x0_tsi.h
  • TSI_CHCFG_G4P2 : gd32f3x0_tsi.h
  • TSI_CHCFG_G4P3 : gd32f3x0_tsi.h
  • TSI_CHCFG_G5P0 : gd32f3x0_tsi.h
  • TSI_CHCFG_G5P1 : gd32f3x0_tsi.h
  • TSI_CHCFG_G5P2 : gd32f3x0_tsi.h
  • TSI_CHCFG_G5P3 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV1 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV1024 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV128 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV16 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV16384 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV2 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV2048 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV256 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV32 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV32768 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV4 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV4096 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV512 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV64 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV8 : gd32f3x0_tsi.h
  • TSI_CTCDIV_DIV8192 : gd32f3x0_tsi.h
  • TSI_CTL0 : gd32f3x0_tsi.h
  • TSI_CTL0_CDT : gd32f3x0_tsi.h
  • TSI_CTL0_CTCDIV : gd32f3x0_tsi.h
  • TSI_CTL0_CTDT : gd32f3x0_tsi.h
  • TSI_CTL0_ECDIV : gd32f3x0_tsi.h
  • TSI_CTL0_ECDT : gd32f3x0_tsi.h
  • TSI_CTL0_ECEN : gd32f3x0_tsi.h
  • TSI_CTL0_EGSEL : gd32f3x0_tsi.h
  • TSI_CTL0_MCN : gd32f3x0_tsi.h
  • TSI_CTL0_PINMOD : gd32f3x0_tsi.h
  • TSI_CTL0_TRGMOD : gd32f3x0_tsi.h
  • TSI_CTL0_TSIEN : gd32f3x0_tsi.h
  • TSI_CTL0_TSIS : gd32f3x0_tsi.h
  • TSI_CTL1 : gd32f3x0_tsi.h
  • TSI_CTL1_CTCDIV : gd32f3x0_tsi.h
  • TSI_CTL1_ECDIV : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV1 : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV2 : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV3 : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV4 : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV5 : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV6 : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV7 : gd32f3x0_tsi.h
  • TSI_EXTEND_DIV8 : gd32f3x0_tsi.h
  • TSI_EXTENDMAX : gd32f3x0_tsi.h
  • TSI_FALLING_TRIGGER : gd32f3x0_tsi.h
  • TSI_FLAG_CTCF : gd32f3x0_tsi.h
  • TSI_FLAG_CTCF_CLR : gd32f3x0_tsi.h
  • TSI_FLAG_MNERR : gd32f3x0_tsi.h
  • TSI_FLAG_MNERR_CLR : gd32f3x0_tsi.h
  • TSI_G0CYCN : gd32f3x0_tsi.h
  • TSI_G1CYCN : gd32f3x0_tsi.h
  • TSI_G2CYCN : gd32f3x0_tsi.h
  • TSI_G3CYCN : gd32f3x0_tsi.h
  • TSI_G4CYCN : gd32f3x0_tsi.h
  • TSI_G5CYCN : gd32f3x0_tsi.h
  • TSI_GCTL : gd32f3x0_tsi.h
  • TSI_GCTL_GC0 : gd32f3x0_tsi.h
  • TSI_GCTL_GC1 : gd32f3x0_tsi.h
  • TSI_GCTL_GC2 : gd32f3x0_tsi.h
  • TSI_GCTL_GC3 : gd32f3x0_tsi.h
  • TSI_GCTL_GC4 : gd32f3x0_tsi.h
  • TSI_GCTL_GC5 : gd32f3x0_tsi.h
  • TSI_GCTL_GE0 : gd32f3x0_tsi.h
  • TSI_GCTL_GE1 : gd32f3x0_tsi.h
  • TSI_GCTL_GE2 : gd32f3x0_tsi.h
  • TSI_GCTL_GE3 : gd32f3x0_tsi.h
  • TSI_GCTL_GE4 : gd32f3x0_tsi.h
  • TSI_GCTL_GE5 : gd32f3x0_tsi.h
  • TSI_INPUT_FLOATING : gd32f3x0_tsi.h
  • TSI_INT_CCTCF : gd32f3x0_tsi.h
  • TSI_INT_FLAG_CTCF : gd32f3x0_tsi.h
  • TSI_INT_FLAG_CTCF_CLR : gd32f3x0_tsi.h
  • TSI_INT_FLAG_MNERR : gd32f3x0_tsi.h
  • TSI_INT_FLAG_MNERR_CLR : gd32f3x0_tsi.h
  • TSI_INT_MNERR : gd32f3x0_tsi.h
  • TSI_INTC : gd32f3x0_tsi.h
  • TSI_INTC_CCTCF : gd32f3x0_tsi.h
  • TSI_INTC_CMNERR : gd32f3x0_tsi.h
  • TSI_INTEN : gd32f3x0_tsi.h
  • TSI_INTEN_CTCFIE : gd32f3x0_tsi.h
  • TSI_INTEN_MNERRIE : gd32f3x0_tsi.h
  • TSI_INTF : gd32f3x0_tsi.h
  • TSI_INTF_CTCF : gd32f3x0_tsi.h
  • TSI_INTF_MNERR : gd32f3x0_tsi.h
  • TSI_MAXNUM1023 : gd32f3x0_tsi.h
  • TSI_MAXNUM16383 : gd32f3x0_tsi.h
  • TSI_MAXNUM2047 : gd32f3x0_tsi.h
  • TSI_MAXNUM255 : gd32f3x0_tsi.h
  • TSI_MAXNUM4095 : gd32f3x0_tsi.h
  • TSI_MAXNUM511 : gd32f3x0_tsi.h
  • TSI_MAXNUM8191 : gd32f3x0_tsi.h
  • TSI_OUTPUT_LOW : gd32f3x0_tsi.h
  • TSI_PHM : gd32f3x0_tsi.h
  • TSI_PHM_G0P0 : gd32f3x0_tsi.h
  • TSI_PHM_G0P1 : gd32f3x0_tsi.h
  • TSI_PHM_G0P2 : gd32f3x0_tsi.h
  • TSI_PHM_G0P3 : gd32f3x0_tsi.h
  • TSI_PHM_G1P0 : gd32f3x0_tsi.h
  • TSI_PHM_G1P1 : gd32f3x0_tsi.h
  • TSI_PHM_G1P2 : gd32f3x0_tsi.h
  • TSI_PHM_G1P3 : gd32f3x0_tsi.h
  • TSI_PHM_G2P0 : gd32f3x0_tsi.h
  • TSI_PHM_G2P1 : gd32f3x0_tsi.h
  • TSI_PHM_G2P2 : gd32f3x0_tsi.h
  • TSI_PHM_G2P3 : gd32f3x0_tsi.h
  • TSI_PHM_G3P0 : gd32f3x0_tsi.h
  • TSI_PHM_G3P1 : gd32f3x0_tsi.h
  • TSI_PHM_G3P2 : gd32f3x0_tsi.h
  • TSI_PHM_G3P3 : gd32f3x0_tsi.h
  • TSI_PHM_G4P0 : gd32f3x0_tsi.h
  • TSI_PHM_G4P1 : gd32f3x0_tsi.h
  • TSI_PHM_G4P2 : gd32f3x0_tsi.h
  • TSI_PHM_G4P3 : gd32f3x0_tsi.h
  • TSI_PHM_G5P0 : gd32f3x0_tsi.h
  • TSI_PHM_G5P1 : gd32f3x0_tsi.h
  • TSI_PHM_G5P2 : gd32f3x0_tsi.h
  • TSI_PHM_G5P3 : gd32f3x0_tsi.h
  • TSI_RISING_TRIGGER : gd32f3x0_tsi.h
  • TSI_SAMPCFG : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G0P0 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G0P1 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G0P2 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G0P3 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G1P0 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G1P1 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G1P2 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G1P3 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G2P0 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G2P1 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G2P2 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G2P3 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G3P0 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G3P1 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G3P2 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G3P3 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G4P0 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G4P1 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G4P2 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G4P3 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G5P0 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G5P1 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G5P2 : gd32f3x0_tsi.h
  • TSI_SAMPCFG_G5P3 : gd32f3x0_tsi.h
  • TSI_TRANSFER_10CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_11CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_12CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_13CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_14CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_15CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_16CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_1CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_2CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_3CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_4CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_5CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_6CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_7CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_8CTCLK : gd32f3x0_tsi.h
  • TSI_TRANSFER_9CTCLK : gd32f3x0_tsi.h
  • TTS_HR : gd32f3x0_rtc.h
  • TTS_MN : gd32f3x0_rtc.h
  • TTS_SC : gd32f3x0_rtc.h
  • TXFIFO_EMPTY : usb_regs.h
  • TXFIFO_EMPTY_HALF : usb_regs.h


GD32F3x0_Firmware_Library: Globals

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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- u -

  • UNLOCK_KEY0 : gd32f3x0_fmc.h
  • UNLOCK_KEY1 : gd32f3x0_fmc.h
  • UP_STATE : usbh_core.h
  • USART0 : gd32f3x0_usart.h
  • USART1 : gd32f3x0_usart.h
  • USART_ABDM_FTOF : gd32f3x0_usart.h
  • USART_ABDM_FTOR : gd32f3x0_usart.h
  • USART_ADDM_4BIT : gd32f3x0_usart.h
  • USART_ADDM_FULLBIT : gd32f3x0_usart.h
  • USART_BAUD : gd32f3x0_usart.h
  • USART_BAUD_FRADIV : gd32f3x0_usart.h
  • USART_BAUD_INTDIV : gd32f3x0_usart.h
  • USART_BIT_POS : gd32f3x0_usart.h
  • USART_BIT_POS2 : gd32f3x0_usart.h
  • USART_CLEN_EN : gd32f3x0_usart.h
  • USART_CLEN_NONE : gd32f3x0_usart.h
  • USART_CMD : gd32f3x0_usart.h
  • USART_CMD_ABDCMD : gd32f3x0_usart.h
  • USART_CMD_MMCMD : gd32f3x0_usart.h
  • USART_CMD_RXFCMD : gd32f3x0_usart.h
  • USART_CMD_SBKCMD : gd32f3x0_usart.h
  • USART_CMD_TXFCMD : gd32f3x0_usart.h
  • USART_CPH_1CK : gd32f3x0_usart.h
  • USART_CPH_2CK : gd32f3x0_usart.h
  • USART_CPL_HIGH : gd32f3x0_usart.h
  • USART_CPL_LOW : gd32f3x0_usart.h
  • USART_CTL0 : gd32f3x0_usart.h
  • USART_CTL0_AMIE : gd32f3x0_usart.h
  • USART_CTL0_DEA : gd32f3x0_usart.h
  • USART_CTL0_DED : gd32f3x0_usart.h
  • USART_CTL0_EBIE : gd32f3x0_usart.h
  • USART_CTL0_IDLEIE : gd32f3x0_usart.h
  • USART_CTL0_MEN : gd32f3x0_usart.h
  • USART_CTL0_OVSMOD : gd32f3x0_usart.h
  • USART_CTL0_PCEN : gd32f3x0_usart.h
  • USART_CTL0_PERRIE : gd32f3x0_usart.h
  • USART_CTL0_PM : gd32f3x0_usart.h
  • USART_CTL0_RBNEIE : gd32f3x0_usart.h
  • USART_CTL0_REG_OFFSET : gd32f3x0_usart.h
  • USART_CTL0_REN : gd32f3x0_usart.h
  • USART_CTL0_RTIE : gd32f3x0_usart.h
  • USART_CTL0_TBEIE : gd32f3x0_usart.h
  • USART_CTL0_TCIE : gd32f3x0_usart.h
  • USART_CTL0_TEN : gd32f3x0_usart.h
  • USART_CTL0_UEN : gd32f3x0_usart.h
  • USART_CTL0_UESM : gd32f3x0_usart.h
  • USART_CTL0_WL : gd32f3x0_usart.h
  • USART_CTL0_WM : gd32f3x0_usart.h
  • USART_CTL1 : gd32f3x0_usart.h
  • USART_CTL1_ABDEN : gd32f3x0_usart.h
  • USART_CTL1_ABDM : gd32f3x0_usart.h
  • USART_CTL1_ADDM : gd32f3x0_usart.h
  • USART_CTL1_ADDR : gd32f3x0_usart.h
  • USART_CTL1_CKEN : gd32f3x0_usart.h
  • USART_CTL1_CLEN : gd32f3x0_usart.h
  • USART_CTL1_CPH : gd32f3x0_usart.h
  • USART_CTL1_CPL : gd32f3x0_usart.h
  • USART_CTL1_DINV : gd32f3x0_usart.h
  • USART_CTL1_LBDIE : gd32f3x0_usart.h
  • USART_CTL1_LBLEN : gd32f3x0_usart.h
  • USART_CTL1_LMEN : gd32f3x0_usart.h
  • USART_CTL1_MSBF : gd32f3x0_usart.h
  • USART_CTL1_REG_OFFSET : gd32f3x0_usart.h
  • USART_CTL1_RINV : gd32f3x0_usart.h
  • USART_CTL1_RTEN : gd32f3x0_usart.h
  • USART_CTL1_STB : gd32f3x0_usart.h
  • USART_CTL1_STRP : gd32f3x0_usart.h
  • USART_CTL1_TINV : gd32f3x0_usart.h
  • USART_CTL2 : gd32f3x0_usart.h
  • USART_CTL2_CTSEN : gd32f3x0_usart.h
  • USART_CTL2_CTSIE : gd32f3x0_usart.h
  • USART_CTL2_DDRE : gd32f3x0_usart.h
  • USART_CTL2_DEM : gd32f3x0_usart.h
  • USART_CTL2_DENR : gd32f3x0_usart.h
  • USART_CTL2_DENT : gd32f3x0_usart.h
  • USART_CTL2_DEP : gd32f3x0_usart.h
  • USART_CTL2_ERRIE : gd32f3x0_usart.h
  • USART_CTL2_HDEN : gd32f3x0_usart.h
  • USART_CTL2_IREN : gd32f3x0_usart.h
  • USART_CTL2_IRLP : gd32f3x0_usart.h
  • USART_CTL2_NKEN : gd32f3x0_usart.h
  • USART_CTL2_OSB : gd32f3x0_usart.h
  • USART_CTL2_OVRD : gd32f3x0_usart.h
  • USART_CTL2_REG_OFFSET : gd32f3x0_usart.h
  • USART_CTL2_RTSEN : gd32f3x0_usart.h
  • USART_CTL2_SCEN : gd32f3x0_usart.h
  • USART_CTL2_SCRTNUM : gd32f3x0_usart.h
  • USART_CTL2_WUIE : gd32f3x0_usart.h
  • USART_CTL2_WUM : gd32f3x0_usart.h
  • USART_CTS_DISABLE : gd32f3x0_usart.h
  • USART_CTS_ENABLE : gd32f3x0_usart.h
  • USART_DENR_DISABLE : gd32f3x0_usart.h
  • USART_DENR_ENABLE : gd32f3x0_usart.h
  • USART_DENT_DISABLE : gd32f3x0_usart.h
  • USART_DENT_ENABLE : gd32f3x0_usart.h
  • USART_DEP_HIGH : gd32f3x0_usart.h
  • USART_DEP_LOW : gd32f3x0_usart.h
  • USART_GP : gd32f3x0_usart.h
  • USART_GP_GUAT : gd32f3x0_usart.h
  • USART_GP_PSC : gd32f3x0_usart.h
  • USART_INTC : gd32f3x0_usart.h
  • USART_INTC_AMC : gd32f3x0_usart.h
  • USART_INTC_CTSC : gd32f3x0_usart.h
  • USART_INTC_EBC : gd32f3x0_usart.h
  • USART_INTC_FEC : gd32f3x0_usart.h
  • USART_INTC_IDLEC : gd32f3x0_usart.h
  • USART_INTC_LBDC : gd32f3x0_usart.h
  • USART_INTC_NEC : gd32f3x0_usart.h
  • USART_INTC_OREC : gd32f3x0_usart.h
  • USART_INTC_PEC : gd32f3x0_usart.h
  • USART_INTC_RTC : gd32f3x0_usart.h
  • USART_INTC_TCC : gd32f3x0_usart.h
  • USART_INTC_WUC : gd32f3x0_usart.h
  • USART_IRLP_LOW : gd32f3x0_usart.h
  • USART_IRLP_NORMAL : gd32f3x0_usart.h
  • USART_LBLEN_10B : gd32f3x0_usart.h
  • USART_LBLEN_11B : gd32f3x0_usart.h
  • USART_MSBF_LSB : gd32f3x0_usart.h
  • USART_MSBF_MSB : gd32f3x0_usart.h
  • USART_OSB_1BIT : gd32f3x0_usart.h
  • USART_OSB_3BIT : gd32f3x0_usart.h
  • USART_OVSMOD_16 : gd32f3x0_usart.h
  • USART_OVSMOD_8 : gd32f3x0_usart.h
  • USART_PM_EVEN : gd32f3x0_usart.h
  • USART_PM_NONE : gd32f3x0_usart.h
  • USART_PM_ODD : gd32f3x0_usart.h
  • USART_RDATA : gd32f3x0_usart.h
  • USART_RDATA_RDATA : gd32f3x0_usart.h
  • USART_RECEIVE_DISABLE : gd32f3x0_usart.h
  • USART_RECEIVE_ENABLE : gd32f3x0_usart.h
  • USART_REG_VAL : gd32f3x0_usart.h
  • USART_REG_VAL2 : gd32f3x0_usart.h
  • USART_REGIDX_BIT : gd32f3x0_usart.h
  • USART_REGIDX_BIT2 : gd32f3x0_usart.h
  • USART_RFCS : gd32f3x0_usart.h
  • USART_RFCS_ELNACK : gd32f3x0_usart.h
  • USART_RFCS_REG_OFFSET : gd32f3x0_usart.h
  • USART_RFCS_RFCNT : gd32f3x0_usart.h
  • USART_RFCS_RFE : gd32f3x0_usart.h
  • USART_RFCS_RFEN : gd32f3x0_usart.h
  • USART_RFCS_RFF : gd32f3x0_usart.h
  • USART_RFCS_RFFIE : gd32f3x0_usart.h
  • USART_RFCS_RFFINT : gd32f3x0_usart.h
  • USART_RT : gd32f3x0_usart.h
  • USART_RT_BL : gd32f3x0_usart.h
  • USART_RT_RT : gd32f3x0_usart.h
  • USART_RTS_DISABLE : gd32f3x0_usart.h
  • USART_RTS_ENABLE : gd32f3x0_usart.h
  • USART_STAT : gd32f3x0_usart.h
  • USART_STAT_ABDE : gd32f3x0_usart.h
  • USART_STAT_ABDF : gd32f3x0_usart.h
  • USART_STAT_AMF : gd32f3x0_usart.h
  • USART_STAT_BSY : gd32f3x0_usart.h
  • USART_STAT_CTS : gd32f3x0_usart.h
  • USART_STAT_CTSF : gd32f3x0_usart.h
  • USART_STAT_EBF : gd32f3x0_usart.h
  • USART_STAT_FERR : gd32f3x0_usart.h
  • USART_STAT_IDLEF : gd32f3x0_usart.h
  • USART_STAT_LBDF : gd32f3x0_usart.h
  • USART_STAT_NERR : gd32f3x0_usart.h
  • USART_STAT_ORERR : gd32f3x0_usart.h
  • USART_STAT_PERR : gd32f3x0_usart.h
  • USART_STAT_RBNE : gd32f3x0_usart.h
  • USART_STAT_REA : gd32f3x0_usart.h
  • USART_STAT_REG_OFFSET : gd32f3x0_usart.h
  • USART_STAT_RTF : gd32f3x0_usart.h
  • USART_STAT_RWU : gd32f3x0_usart.h
  • USART_STAT_SBF : gd32f3x0_usart.h
  • USART_STAT_TBE : gd32f3x0_usart.h
  • USART_STAT_TC : gd32f3x0_usart.h
  • USART_STAT_TEA : gd32f3x0_usart.h
  • USART_STAT_WUF : gd32f3x0_usart.h
  • USART_STB_0_5BIT : gd32f3x0_usart.h
  • USART_STB_1_5BIT : gd32f3x0_usart.h
  • USART_STB_1BIT : gd32f3x0_usart.h
  • USART_STB_2BIT : gd32f3x0_usart.h
  • USART_TDATA : gd32f3x0_usart.h
  • USART_TDATA_TDATA : gd32f3x0_usart.h
  • USART_TRANSMIT_DISABLE : gd32f3x0_usart.h
  • USART_TRANSMIT_ENABLE : gd32f3x0_usart.h
  • USART_WL_8BIT : gd32f3x0_usart.h
  • USART_WL_9BIT : gd32f3x0_usart.h
  • USART_WM_ADDR : gd32f3x0_usart.h
  • USART_WM_IDLE : gd32f3x0_usart.h
  • USART_WUM_ADDR : gd32f3x0_usart.h
  • USART_WUM_RBNE : gd32f3x0_usart.h
  • USART_WUM_STARTB : gd32f3x0_usart.h
  • USB_CFG_DESC_LEN : usb_std.h
  • USB_CFGDESC : usb_std.h
  • USB_CFGDESC_SIZE : usb_std.h
  • USB_CID : usb_regs.h
  • USB_CLASS_REQ : usb_std.h
  • USB_CORE_EMBEDDED_PHY : usb_defines.h
  • USB_CORE_INTR_READ : usb_regs.h
  • USB_CORE_SPEED_FULL : usb_defines.h
  • USB_CORE_SPEED_HIGH : usb_defines.h
  • USB_CORE_ULPI_PHY : usb_defines.h
  • USB_CURRENT_FRAME_GET : usb_regs.h
  • USB_CURRENT_MODE_GET : usb_regs.h
  • USB_CURRENT_SPEED_GET : usb_regs.h
  • USB_DAEPINT : usb_regs.h
  • USB_DAEPINTEN : usb_regs.h
  • USB_DAIEP_INTR_READ : usb_regs.h
  • USB_DAOEP_INTR_READ : usb_regs.h
  • USB_DCFG : usb_regs.h
  • USB_DCTL : usb_regs.h
  • USB_DEP1INT : usb_regs.h
  • USB_DEP1INTEN : usb_regs.h
  • USB_DESCTYPE_CONFIGURATION : usb_std.h
  • USB_DESCTYPE_DEVICE : usb_std.h
  • USB_DESCTYPE_DEVICE_QUALIFIER : usb_std.h
  • USB_DESCTYPE_ENDPOINT : usb_std.h
  • USB_DESCTYPE_HID : usb_std.h
  • USB_DESCTYPE_HID_REPORT : usb_std.h
  • USB_DESCTYPE_INTERFACE : usb_std.h
  • USB_DESCTYPE_INTERFACE_POWER : usb_std.h
  • USB_DESCTYPE_OTHER_SPEED_CONFIGURATION : usb_std.h
  • USB_DESCTYPE_STRING : usb_std.h
  • USB_DEV_DESC_LEN : usb_std.h
  • USB_DEV_QUALIFIER_DESC_LEN : usb_std.h
  • USB_DEVDESC : usb_std.h
  • USB_DEVDESC_SIZE : usb_std.h
  • USB_DEVICE_DESC_SIZE : usbd_std.h
  • USB_DEVQUADESC : usb_std.h
  • USB_DIEP0CTL : usb_regs.h
  • USB_DIEP0LEN : usb_regs.h
  • USB_DIEP0TFLEN : usb_regs.h
  • USB_DIEP1INTEN : usb_regs.h
  • USB_DIEP_INTR_READ : usb_regs.h
  • USB_DIEPFEINTEN : usb_regs.h
  • USB_DIEPINTEN : usb_regs.h
  • USB_DIEPxCTL : usb_regs.h
  • USB_DIEPxINTF : usb_regs.h
  • USB_DIEPxLEN : usb_regs.h
  • USB_DIEPxTFLEN : usb_regs.h
  • USB_DIEPxTFSTAT : usb_regs.h
  • USB_DIR_IN : usb_std.h
  • USB_DIR_MASK : usb_std.h
  • USB_DIR_OUT : usb_std.h
  • USB_DOEP0CTL : usb_regs.h
  • USB_DOEP0LEN : usb_regs.h
  • USB_DOEP1INTEN : usb_regs.h
  • USB_DOEP_INTR_READ : usb_regs.h
  • USB_DOEPINTEN : usb_regs.h
  • USB_DOEPxCTL : usb_regs.h
  • USB_DOEPxINTF : usb_regs.h
  • USB_DOEPxLEN : usb_regs.h
  • USB_DSTAT : usb_regs.h
  • USB_DVBUSDT : usb_regs.h
  • USB_DVBUSPT : usb_regs.h
  • USB_EP_DESC_LEN : usb_std.h
  • USB_EPDESC : usb_std.h
  • USB_EPDESC_SIZE : usb_std.h
  • USB_EPTYPE_BULK : usb_defines.h
  • USB_EPTYPE_CTRL : usb_defines.h
  • USB_EPTYPE_INTR : usb_defines.h
  • USB_EPTYPE_ISOC : usb_defines.h
  • USB_EPTYPE_MASK : usb_defines.h
  • USB_EVEN_FRAME : usb_regs.h
  • USB_FEATURE_ENDP_HALT : usbd_std.h
  • USB_FEATURE_REMOTE_WAKEUP : usbd_std.h
  • USB_FEATURE_TEST_MODE : usbd_std.h
  • USB_FIFO : usb_regs.h
  • USB_FSLSCLOCK_INIT : usb_regs.h
  • USB_GAHBCS : usb_regs.h
  • USB_GCCFG : usb_regs.h
  • USB_GINTEN : usb_regs.h
  • USB_GINTF : usb_regs.h
  • USB_GLOBAL_INT_DISABLE : usb_regs.h
  • USB_GLOBAL_INT_ENABLE : usb_regs.h
  • USB_GOTGCS : usb_regs.h
  • USB_GOTGINTF : usb_regs.h
  • USB_GRFLEN : usb_regs.h
  • USB_GRSTATP : usb_regs.h
  • USB_GRSTATR : usb_regs.h
  • USB_GRSTCTL : usb_regs.h
  • USB_GUSBCS : usb_regs.h
  • USB_HACHINT : usb_regs.h
  • USB_HACHINTEN : usb_regs.h
  • USB_HCHxCTL : usb_regs.h
  • USB_HCHxINTEN : usb_regs.h
  • USB_HCHxINTF : usb_regs.h
  • USB_HCHxLEN : usb_regs.h
  • USB_HCTL : usb_regs.h
  • USB_HFINFR : usb_regs.h
  • USB_HFT : usb_regs.h
  • USB_HID_CLASS : usb_std.h
  • USB_HIDDESC : usb_std.h
  • USB_HIDREPDESC : usb_std.h
  • USB_HNPTFLEN : usb_regs.h
  • USB_HNPTFQSTAT : usb_regs.h
  • USB_HPCS : usb_regs.h
  • USB_HPTFLEN : usb_regs.h
  • USB_HPTFQSTAT : usb_regs.h
  • USB_IF_DESC_LEN : usb_std.h
  • USB_INTDESC : usb_std.h
  • USB_INTDESC_SIZE : usb_std.h
  • USB_INTPWRDESC : usb_std.h
  • USB_MAX_DEV_EPCOUNT : usb_core.h
  • USB_MAX_EP0_SIZE : usb_core.h
  • USB_MAX_FIFOS : usb_core.h
  • USB_MIN : usbd_std.h
  • USB_MSC_CLASS : usb_std.h
  • USB_OSPCFGDESC : usb_std.h
  • USB_OTG_DESC_LEN : usb_std.h
  • USB_PORT_READ : usb_regs.h
  • USB_PWRCLKCTL : usb_regs.h
  • USB_REMOTE_WAKEUP_RESET : usb_regs.h
  • USB_REMOTE_WAKEUP_SET : usb_regs.h
  • USB_REQ_MASK : usb_std.h
  • USB_REQTYPE_DEVICE : usb_std.h
  • USB_REQTYPE_ENDPOINT : usb_std.h
  • USB_REQTYPE_INTERFACE : usb_std.h
  • USB_REQTYPE_MASK : usb_std.h
  • USB_SET_DEVADDR : usb_regs.h
  • USB_SOFT_DISCONNECT_DISABLE : usb_regs.h
  • USB_SOFT_DISCONNECT_ENABLE : usb_regs.h
  • USB_SPEED_EXP_FULL : usb_regs.h
  • USB_SPEED_EXP_HIGH : usb_regs.h
  • USB_SPEED_INP_FULL : usb_regs.h
  • USB_STANDARD_REQ : usb_std.h
  • USB_STATUS_ADDRESSED : usbd_core.h
  • USB_STATUS_CONFIGURED : usbd_core.h
  • USB_STATUS_DEFAULT : usbd_core.h
  • USB_STATUS_REMOTE_WAKEUP : usbd_std.h
  • USB_STATUS_SELF_POWERED : usbd_std.h
  • USB_STATUS_SUSPENDED : usbd_core.h
  • USB_STRDESC : usb_std.h
  • USB_VENDOR_REQ : usb_std.h
  • USBD_CONFIG_STR_IDX : usbd_std.h
  • USBD_INTERFACE_STR_IDX : usbd_std.h
  • USBD_LANGID_STR_IDX : usbd_std.h
  • USBD_MFC_STR_IDX : usbd_std.h
  • USBD_PRODUCT_STR_IDX : usbd_std.h
  • USBD_SERIAL_STR_IDX : usbd_std.h
  • USBD_STRING_DESC : usbd_std.h
  • USBFS : usb_regs.h
  • USBFS_MAX_DEV_EPCOUNT : usb_defines.h
  • USBFS_MAX_FIFO_WORDLEN : usb_defines.h
  • USBFS_MAX_HOST_CHANNELCOUNT : usb_defines.h
  • USBFS_MAX_PACKET_SIZE : usb_defines.h
  • USBH_CFG_DESC_SET_SIZE : usb_std.h
  • USBH_DEVICE_ADDRESS : usbh_core.h
  • USBH_DEVICE_ADDRESS_DEFAULT : usbh_core.h
  • USBH_MAX_ERROR_COUNT : usbh_core.h
  • USBH_SETUP_PACKET_SIZE : usbh_std.h
  • USBHS_MAX_DEV_EPCOUNT : usb_defines.h
  • USBHS_MAX_FIFO_WORDLEN : usb_defines.h
  • USBHS_MAX_HOST_CHANNELCOUNT : usb_defines.h
  • USBHS_MAX_PACKET_SIZE : usb_defines.h
  • USBREQ_CLEAR_FEATURE : usb_std.h
  • USBREQ_GET_CONFIGURATION : usb_std.h
  • USBREQ_GET_DESCRIPTOR : usb_std.h
  • USBREQ_GET_INTERFACE : usb_std.h
  • USBREQ_GET_STATUS : usb_std.h
  • USBREQ_SET_ADDRESS : usb_std.h
  • USBREQ_SET_CONFIGURATION : usb_std.h
  • USBREQ_SET_DESCRIPTOR : usb_std.h
  • USBREQ_SET_FEATURE : usb_std.h
  • USBREQ_SET_INTERFACE : usb_std.h
  • USBREQ_SYNCH_FRAME : usb_std.h


GD32F3x0_Firmware_Library: Globals

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- w -

  • WDHT_WDHT : gd32f3x0_adc.h
  • WDLT_WDLT : gd32f3x0_adc.h
  • WFE_CMD : gd32f3x0_pmu.h
  • WFI_CMD : gd32f3x0_pmu.h
  • WIDE_STRING : usbd_std.h
  • WND_WND : gd32f3x0_fwdgt.h
  • WPK_WPK : gd32f3x0_rtc.h
  • WS_WSCNT_0 : gd32f3x0_fmc.h
  • WS_WSCNT_1 : gd32f3x0_fmc.h
  • WS_WSCNT_2 : gd32f3x0_fmc.h
  • WWDGT : gd32f3x0_wwdgt.h
  • WWDGT_CFG : gd32f3x0_wwdgt.h
  • WWDGT_CFG_EWIE : gd32f3x0_wwdgt.h
  • WWDGT_CFG_PSC : gd32f3x0_wwdgt.h
  • WWDGT_CFG_PSC_DIV1 : gd32f3x0_wwdgt.h
  • WWDGT_CFG_PSC_DIV2 : gd32f3x0_wwdgt.h
  • WWDGT_CFG_PSC_DIV4 : gd32f3x0_wwdgt.h
  • WWDGT_CFG_PSC_DIV8 : gd32f3x0_wwdgt.h
  • WWDGT_CFG_WIN : gd32f3x0_wwdgt.h
  • WWDGT_CTL : gd32f3x0_wwdgt.h
  • WWDGT_CTL_CNT : gd32f3x0_wwdgt.h
  • WWDGT_CTL_WDGTEN : gd32f3x0_wwdgt.h
  • WWDGT_STAT : gd32f3x0_wwdgt.h
  • WWDGT_STAT_EWIF : gd32f3x0_wwdgt.h


GD32F3x0_Firmware_Library: Main Page

GD32F3x0_Firmware_Library Documentation
Generated on Tue Jun 27 2017 14:36:15 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_hcs.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
usbh_hcs.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef USBH_HCS_H
13 #define USBH_HCS_H
14
15 #include "usbh_core.h"
16
17 #define HC_MAX 8U
18
19 #define HC_OK 0x0000U
20 #define HC_USED 0x8000U
21 #define HC_ERROR 0xFFFFU
22 #define HC_USED_MASK 0x7FFFU
23
24 /* function declarations */
25 /* allocate a new channel for the pipe */
26 uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr);
27 /* free all usb host channel */
28 uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev);
29 /* free the usb host channel */
30 uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index);
31 /* open a channel */
32 uint8_t usbh_channel_open (usb_core_handle_struct *pudev,
33 uint8_t channel_num,
34 uint8_t dev_addr,
35 uint8_t dev_speed,
36 uint8_t ep_type,
37 uint16_t ep_mps);
38 /* modify a channel */
39 uint8_t usbh_channel_modify (usb_core_handle_struct *pudev,
40 uint8_t channel_num,
41 uint8_t dev_addr,
42 uint8_t dev_speed,
43 uint8_t ep_type,
44 uint16_t ep_mps);
45
46 #endif /* USBH_HCS_H */
usbh_core.h
header file for usbh_core.c
usbh_channel_free
uint8_t usbh_channel_free(usb_core_handle_struct *pudev, uint8_t index)
free the usb host channel
Definition: usbh_hcs.c:114
usbh_channel_modify
uint8_t usbh_channel_modify(usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
modify a channel
Definition: usbh_hcs.c:63
usb_core_handle_struct
Definition: usb_core.h:200
usbh_allchannel_dealloc
uint8_t usbh_allchannel_dealloc(usb_core_handle_struct *pudev)
free all usb host channel
Definition: usbh_hcs.c:129
usbh_channel_open
uint8_t usbh_channel_open(usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
open a channel
Definition: usbh_hcs.c:27
usbh_channel_alloc
uint8_t usbh_channel_alloc(usb_core_handle_struct *pudev, uint8_t ep_addr)
allocate a new channel for the pipe
Definition: usbh_hcs.c:96
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_usart.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_usart.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_USART_H
13 #define GD32F3X0_USART_H
14
15 #include "gd32f3x0.h"
16
17 /* USARTx(x=0,1) definitions */
18 #define USART0 (USART_BASE + 0x0000F400U)
19 #define USART1 USART_BASE
20
21 /* registers definitions */
22 #define USART_CTL0(usartx) REG32((usartx) + 0x00U)
23 #define USART_CTL1(usartx) REG32((usartx) + 0x04U)
24 #define USART_CTL2(usartx) REG32((usartx) + 0x08U)
25 #define USART_BAUD(usartx) REG32((usartx) + 0x0CU)
26 #define USART_GP(usartx) REG32((usartx) + 0x10U)
27 #define USART_RT(usartx) REG32((usartx) + 0x14U)
28 #define USART_CMD(usartx) REG32((usartx) + 0x18U)
29 #define USART_STAT(usartx) REG32((usartx) + 0x1CU)
30 #define USART_INTC(usartx) REG32((usartx) + 0x20U)
31 #define USART_RDATA(usartx) REG32((usartx) + 0x24U)
32 #define USART_TDATA(usartx) REG32((usartx) + 0x28U)
33 #define USART_RFCS(usartx) REG32((usartx) + 0xD0U)
35 /* bits definitions */
36 /* USARTx_CTL0 */
37 #define USART_CTL0_UEN BIT(0)
38 #define USART_CTL0_UESM BIT(1)
39 #define USART_CTL0_REN BIT(2)
40 #define USART_CTL0_TEN BIT(3)
41 #define USART_CTL0_IDLEIE BIT(4)
42 #define USART_CTL0_RBNEIE BIT(5)
43 #define USART_CTL0_TCIE BIT(6)
44 #define USART_CTL0_TBEIE BIT(7)
45 #define USART_CTL0_PERRIE BIT(8)
46 #define USART_CTL0_PM BIT(9)
47 #define USART_CTL0_PCEN BIT(10)
48 #define USART_CTL0_WM BIT(11)
49 #define USART_CTL0_WL BIT(12)
50 #define USART_CTL0_MEN BIT(13)
51 #define USART_CTL0_AMIE BIT(14)
52 #define USART_CTL0_OVSMOD BIT(15)
53 #define USART_CTL0_DED BITS(16,20)
54 #define USART_CTL0_DEA BITS(21,25)
55 #define USART_CTL0_RTIE BIT(26)
56 #define USART_CTL0_EBIE BIT(27)
58 /* USARTx_CTL1 */
59 #define USART_CTL1_ADDM BIT(4)
60 #define USART_CTL1_LBLEN BIT(5)
61 #define USART_CTL1_LBDIE BIT(6)
62 #define USART_CTL1_CLEN BIT(8)
63 #define USART_CTL1_CPH BIT(9)
64 #define USART_CTL1_CPL BIT(10)
65 #define USART_CTL1_CKEN BIT(11)
66 #define USART_CTL1_STB BITS(12,13)
67 #define USART_CTL1_LMEN BIT(14)
68 #define USART_CTL1_STRP BIT(15)
69 #define USART_CTL1_RINV BIT(16)
70 #define USART_CTL1_TINV BIT(17)
71 #define USART_CTL1_DINV BIT(18)
72 #define USART_CTL1_MSBF BIT(19)
73 #define USART_CTL1_ABDEN BIT(20)
74 #define USART_CTL1_ABDM BITS(21,22)
75 #define USART_CTL1_RTEN BIT(23)
76 #define USART_CTL1_ADDR BITS(24,31)
78 /* USARTx_CTL2 */
79 #define USART_CTL2_ERRIE BIT(0)
80 #define USART_CTL2_IREN BIT(1)
81 #define USART_CTL2_IRLP BIT(2)
82 #define USART_CTL2_HDEN BIT(3)
83 #define USART_CTL2_NKEN BIT(4)
84 #define USART_CTL2_SCEN BIT(5)
85 #define USART_CTL2_DENR BIT(6)
86 #define USART_CTL2_DENT BIT(7)
87 #define USART_CTL2_RTSEN BIT(8)
88 #define USART_CTL2_CTSEN BIT(9)
89 #define USART_CTL2_CTSIE BIT(10)
90 #define USART_CTL2_OSB BIT(11)
91 #define USART_CTL2_OVRD BIT(12)
92 #define USART_CTL2_DDRE BIT(13)
93 #define USART_CTL2_DEM BIT(14)
94 #define USART_CTL2_DEP BIT(15)
95 #define USART_CTL2_SCRTNUM BITS(17,19)
96 #define USART_CTL2_WUM BITS(20,21)
97 #define USART_CTL2_WUIE BIT(22)
99 /* USARTx_BAUD */
100 #define USART_BAUD_FRADIV BITS(0,3)
101 #define USART_BAUD_INTDIV BITS(4,15)
103 /* USARTx_GP */
104 #define USART_GP_PSC BITS(0,7)
105 #define USART_GP_GUAT BITS(8,15)
107 /* USARTx_RT */
108 #define USART_RT_RT BITS(0,23)
109 #define USART_RT_BL BITS(24,31)
111 /* USARTx_CMD */
112 #define USART_CMD_ABDCMD BIT(0)
113 #define USART_CMD_SBKCMD BIT(1)
114 #define USART_CMD_MMCMD BIT(2)
115 #define USART_CMD_RXFCMD BIT(3)
116 #define USART_CMD_TXFCMD BIT(4)
118 /* USARTx_STAT */
119 #define USART_STAT_PERR BIT(0)
120 #define USART_STAT_FERR BIT(1)
121 #define USART_STAT_NERR BIT(2)
122 #define USART_STAT_ORERR BIT(3)
123 #define USART_STAT_IDLEF BIT(4)
124 #define USART_STAT_RBNE BIT(5)
125 #define USART_STAT_TC BIT(6)
126 #define USART_STAT_TBE BIT(7)
127 #define USART_STAT_LBDF BIT(8)
128 #define USART_STAT_CTSF BIT(9)
129 #define USART_STAT_CTS BIT(10)
130 #define USART_STAT_RTF BIT(11)
131 #define USART_STAT_EBF BIT(12)
132 #define USART_STAT_ABDE BIT(14)
133 #define USART_STAT_ABDF BIT(15)
134 #define USART_STAT_BSY BIT(16)
135 #define USART_STAT_AMF BIT(17)
136 #define USART_STAT_SBF BIT(18)
137 #define USART_STAT_RWU BIT(19)
138 #define USART_STAT_WUF BIT(20)
139 #define USART_STAT_TEA BIT(21)
140 #define USART_STAT_REA BIT(22)
142 /* USARTx_INTC */
143 #define USART_INTC_PEC BIT(0)
144 #define USART_INTC_FEC BIT(1)
145 #define USART_INTC_NEC BIT(2)
146 #define USART_INTC_OREC BIT(3)
147 #define USART_INTC_IDLEC BIT(4)
148 #define USART_INTC_TCC BIT(6)
149 #define USART_INTC_LBDC BIT(8)
150 #define USART_INTC_CTSC BIT(9)
151 #define USART_INTC_RTC BIT(11)
152 #define USART_INTC_EBC BIT(12)
153 #define USART_INTC_AMC BIT(17)
154 #define USART_INTC_WUC BIT(20)
156 /* USARTx_RDATA */
157 #define USART_RDATA_RDATA BITS(0,8)
159 /* USARTx_TDATA */
160 #define USART_TDATA_TDATA BITS(0,8)
162 /* USARTx_RFCS */
163 #define USART_RFCS_ELNACK BIT(0)
164 #define USART_RFCS_RFEN BIT(8)
165 #define USART_RFCS_RFFIE BIT(9)
166 #define USART_RFCS_RFE BIT(10)
167 #define USART_RFCS_RFF BIT(11)
168 #define USART_RFCS_RFCNT BITS(12,14)
169 #define USART_RFCS_RFFINT BIT(15)
171 /* constants definitions */
172
173 /* define the USART bit position and its register index offset */
174 #define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
175 #define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
176 #define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
177 #define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
178 | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
179 #define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
180 #define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
181
182 /* register offset */
183 #define USART_CTL0_REG_OFFSET 0x00U
184 #define USART_CTL1_REG_OFFSET 0x04U
185 #define USART_CTL2_REG_OFFSET 0x08U
186 #define USART_STAT_REG_OFFSET 0x1CU
187 #define USART_RFCS_REG_OFFSET 0xD0U
189 /* USART flags */
190 typedef enum{
191 /* flags in STAT register */
192 USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U),
193 USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U),
194 USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U),
195 USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U),
196 USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U),
197 USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U),
198 USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U),
199 USART_FLAG_ABD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 15U),
200 USART_FLAG_ABDE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 14U),
201 USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U),
202 USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U),
203 USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U),
204 USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U),
205 USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U),
206 USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U),
207 USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U),
208 USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U),
209 USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U),
210 USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U),
211 USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U),
212 USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U),
213 USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U),
214 /* flags in RFCS register */
215 USART_FLAG_RFFINT = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 15U),
216 USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U),
217 USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U),
218 }usart_flag_enum;
219
220 /* USART interrupt flags */
221 typedef enum
222 {
223 /* interrupt flags in CTL0 register */
224 USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U),
225 USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U),
226 USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U),
227 USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U),
228 USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U),
229 USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U),
230 USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U),
231 USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U),
232 USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U),
233 /* interrupt flags in CTL1 register */
234 USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U),
235 /* interrupt flags in CTL2 register */
236 USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U),
237 USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U),
238 USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U),
239 USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U),
240 USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U),
241 /* interrupt flags in RFCS register */
242 USART_INT_FLAG_RFF = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U),
243 }usart_interrupt_flag_enum;
244
245 /* USART interrupt enable or disable */
246 typedef enum
247 {
248 /* interrupt in CTL0 register */
249 USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U),
250 USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U),
251 USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U),
252 USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U),
253 USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U),
254 USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U),
255 USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U),
256 USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U),
257 /* interrupt in CTL1 register */
258 USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U),
259 /* interrupt in CTL2 register */
260 USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U),
261 USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U),
262 USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U),
263 /* interrupt in RFCS register */
264 USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U),
265 }usart_interrupt_enum;
266
267 /* USART invert configure */
268 typedef enum {
269 /* data bit level inversion */
270 USART_DINV_ENABLE,
271 USART_DINV_DISABLE,
272 /* TX pin level inversion */
273 USART_TXPIN_ENABLE,
274 USART_TXPIN_DISABLE,
275 /* RX pin level inversion */
276 USART_RXPIN_ENABLE,
277 USART_RXPIN_DISABLE,
278 /* swap TX/RX pins */
279 USART_SWAP_ENABLE,
280 USART_SWAP_DISABLE,
281 }usart_invert_enum;
282
283 /* USART receiver configure */
284 #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
285 #define USART_RECEIVE_ENABLE CTL0_REN(1)
286 #define USART_RECEIVE_DISABLE CTL0_REN(0)
288 /* USART transmitter configure */
289 #define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
290 #define USART_TRANSMIT_ENABLE CTL0_TEN(1)
291 #define USART_TRANSMIT_DISABLE CTL0_TEN(0)
293 /* USART parity bits definitions */
294 #define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
295 #define USART_PM_NONE CTL0_PM(0)
296 #define USART_PM_EVEN CTL0_PM(2)
297 #define USART_PM_ODD CTL0_PM(3)
299 /* USART wakeup method in mute mode */
300 #define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11))
301 #define USART_WM_IDLE CTL0_WM(0)
302 #define USART_WM_ADDR CTL0_WM(1)
304 /* USART word length definitions */
305 #define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12))
306 #define USART_WL_8BIT CTL0_WL(0)
307 #define USART_WL_9BIT CTL0_WL(1)
309 /* USART oversample mode */
310 #define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15))
311 #define USART_OVSMOD_8 CTL0_OVSMOD(1)
312 #define USART_OVSMOD_16 CTL0_OVSMOD(0)
314 /* USART address detection mode */
315 #define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4))
316 #define USART_ADDM_4BIT CTL1_ADDM(0)
317 #define USART_ADDM_FULLBIT CTL1_ADDM(1)
319 /* USART LIN break frame length */
320 #define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5))
321 #define USART_LBLEN_10B CTL1_LBLEN(0)
322 #define USART_LBLEN_11B CTL1_LBLEN(1)
324 /* USART last bit clock pulse */
325 #define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
326 #define USART_CLEN_NONE CTL1_CLEN(0)
327 #define USART_CLEN_EN CTL1_CLEN(1)
329 /* USART clock phase */
330 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9))
331 #define USART_CPH_1CK CTL1_CPH(0)
332 #define USART_CPH_2CK CTL1_CPH(1)
334 /* USART clock polarity */
335 #define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10))
336 #define USART_CPL_LOW CTL1_CPL(0)
337 #define USART_CPL_HIGH CTL1_CPL(1)
339 /* USART stop bits definitions */
340 #define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
341 #define USART_STB_1BIT CTL1_STB(0)
342 #define USART_STB_0_5BIT CTL1_STB(1)
343 #define USART_STB_2BIT CTL1_STB(2)
344 #define USART_STB_1_5BIT CTL1_STB(3)
346 /* USART data is transmitted/received with the LSB/MSB first */
347 #define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19))
348 #define USART_MSBF_LSB CTL1_MSBF(0)
349 #define USART_MSBF_MSB CTL1_MSBF(1)
351 /* USART auto baud rate detection mode bits definitions */
352 #define CTL1_ABDM(regval) (BITS(21,22) & ((uint32_t)(regval) << 21))
353 #define USART_ABDM_FTOR CTL1_ABDM(0)
354 #define USART_ABDM_FTOF CTL1_ABDM(1)
356 /* USART IrDA low-power enable */
357 #define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
358 #define USART_IRLP_LOW CTL2_IRLP(1)
359 #define USART_IRLP_NORMAL CTL2_IRLP(0)
361 /* DMA enable for reception */
362 #define CTL2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6))
363 #define USART_DENR_ENABLE CTL2_DENR(1)
364 #define USART_DENR_DISABLE CTL2_DENR(0)
366 /* DMA enable for transmission */
367 #define CTL2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
368 #define USART_DENT_ENABLE CTL2_DENT(1)
369 #define USART_DENT_DISABLE CTL2_DENT(0)
371 /* USART RTS hardware flow control configure */
372 #define CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
373 #define USART_RTS_ENABLE CTL2_RTSEN(1)
374 #define USART_RTS_DISABLE CTL2_RTSEN(0)
376 /* USART CTS hardware flow control configure */
377 #define CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
378 #define USART_CTS_ENABLE CTL2_CTSEN(1)
379 #define USART_CTS_DISABLE CTL2_CTSEN(0)
381 /* USART one sample bit method configure */
382 #define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11))
383 #define USART_OSB_1BIT CTL2_OSB(1)
384 #define USART_OSB_3BIT CTL2_OSB(0)
386 /* USART driver enable polarity mode */
387 #define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15))
388 #define USART_DEP_HIGH CTL2_DEP(0)
389 #define USART_DEP_LOW CTL2_DEP(1)
391 /* USART wakeup mode from deep-sleep mode */
392 #define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
393 #define USART_WUM_ADDR CTL2_WUM(0)
394 #define USART_WUM_STARTB CTL2_WUM(2)
395 #define USART_WUM_RBNE CTL2_WUM(3)
397 /* function declarations */
398 /* initialization functions */
399 /* reset USART */
400 void usart_deinit(uint32_t usart_periph);
401 /* configure USART baud rate value */
402 void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
403 /* configure USART parity function */
404 void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
405 /* configure USART word length */
406 void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
407 /* configure USART stop bit length */
408 void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
409
410 /* USART normal mode communication */
411 /* enable USART */
412 void usart_enable(uint32_t usart_periph);
413 /* disable USART */
414 void usart_disable(uint32_t usart_periph);
415 /* configure USART transmitter */
416 void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
417 /* configure USART receiver */
418 void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
419 /* USART transmit data function */
420 void usart_data_transmit(uint32_t usart_periph, uint32_t data);
421 /* USART receive data function */
422 uint16_t usart_data_receive(uint32_t usart_periph);
423 /* data is transmitted/received with the LSB/MSB first */
424 void usart_data_first_config(uint32_t usart_periph, uint32_t msbf);
425 /* configure USART inverted */
426 void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara);
427 /* overrun function is enabled */
428 void usart_overrun_enable(uint32_t usart_periph);
429 /* overrun function is disabled */
430 void usart_overrun_disable(uint32_t usart_periph);
431 /* configure the USART oversample mode */
432 void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp);
433 /* sample bit method configure */
434 void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb);
435
436 /* auto baud rate detection */
437 /* auto baud rate detection enable */
438 void usart_autobaud_detection_enable(uint32_t usart_periph);
439 /* auto baud rate detection disable */
440 void usart_autobaud_detection_disable(uint32_t usart_periph);
441 /* auto baud rate detection mode configure */
442 void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod);
443
444 /* multi-processor communication */
445 /* enable mute mode */
446 void usart_mute_mode_enable(uint32_t usart_periph);
447 /* disable mute mode */
448 void usart_mute_mode_disable(uint32_t usart_periph);
449 /* configure wakeup method in mute mode */
450 void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod);
451 /* address detection mode configure */
452 void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod);
453 /* configure address of the USART */
454 void usart_address_config(uint32_t usart_periph, uint8_t addr);
455 /* enable receiver timeout */
456 void usart_receiver_timeout_enable(uint32_t usart_periph);
457 /* disable receiver timeout */
458 void usart_receiver_timeout_disable(uint32_t usart_periph);
459 /* configure receiver timeout threshold */
460 void usart_receiver_timeout_config(uint32_t usart_periph, uint32_t rtimeout);
461
462 /* LIN mode communication */
463 /* LIN mode enable */
464 void usart_lin_mode_enable(uint32_t usart_periph);
465 /* LIN mode disable */
466 void usart_lin_mode_disable(uint32_t usart_periph);
467 /* LIN break detection length */
468 void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen);
469
470 /* half-duplex communication */
471 /* half-duplex enable */
472 void usart_halfduplex_enable(uint32_t usart_periph);
473 /* half-duplex disable */
474 void usart_halfduplex_disable(uint32_t usart_periph);
475
476 /* synchronous communication */
477 /* clock enable */
478 void usart_clock_enable(uint32_t usart_periph);
479 /* clock disable*/
480 void usart_clock_disable(uint32_t usart_periph);
481 /* configure USART synchronous mode parameters */
482 void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
483
484 /* smartcard communication */
485 /* smartcard mode enable */
486 void usart_smartcard_mode_enable(uint32_t usart_periph);
487 /* smartcard mode disable */
488 void usart_smartcard_mode_disable(uint32_t usart_periph);
489 /* NACK enable in smartcard mode */
490 void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
491 /* NACK disable in smartcard mode */
492 void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
493 /* guard time value configure in smartcard mode */
494 void usart_guard_time_config(uint32_t usart_periph, uint32_t guat);
495 /* block length configure */
496 void usart_block_length_config(uint32_t usart_periph, uint32_t bl);
497 /* smartcard auto-retry number configure */
498 void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum);
499 /* early NACK enable */
500 void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph);
501 /* early NACK disable */
502 void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph);
503
504 /* IrDA communication */
505 /* enable IrDA mode */
506 void usart_irda_mode_enable(uint32_t usart_periph);
507 /* disable IrDA mode */
508 void usart_irda_mode_disable(uint32_t usart_periph);
509 /* configure IrDA low-power */
510 void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
511 /* configure the peripheral clock prescaler */
512 void usart_prescaler_config(uint32_t usart_periph, uint32_t psc);
513
514 /* hardware flow communication */
515 /* configure hardware flow control RTS */
516 void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
517 /* configure hardware flow control CTS */
518 void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
519
520 /* RS485 driver enable */
521 void usart_rs485_driver_enable(uint32_t usart_periph);
522 /* RS485 driver disable */
523 void usart_rs485_driver_disable(uint32_t usart_periph);
524 /* driver enable assertion time configure */
525 void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime);
526 /* driver enable de-assertion time configure */
527 void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime);
528 /* configure driver enable polarity mode */
529 void usart_depolarity_config(uint32_t usart_periph, uint32_t dep);
530
531 /* USART DMA */
532 /* configure USART DMA for reception */
533 void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd);
534 /* configure USART DMA for transmission */
535 void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd);
536 /* disable DMA on reception error */
537 void usart_reception_error_dma_disable(uint32_t usart_periph);
538 /* enable DMA on reception error */
539 void usart_reception_error_dma_enable(uint32_t usart_periph);
540
541 /* USART be able to wake up the mcu from deep-sleep mode */
542 void usart_wakeup_enable(uint32_t usart_periph);
543 /* USART be not able to wake up the mcu from deep-sleep mode */
544 void usart_wakeup_disable(uint32_t usart_periph);
545 /* wakeup mode from deep-sleep mode */
546 void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum);
547
548 /* USART receive FIFO */
549 /* receive FIFO enable */
550 void usart_receive_fifo_enable(uint32_t usart_periph);
551 /* receive FIFO disable */
552 void usart_receive_fifo_disable(uint32_t usart_periph);
553 /* read receive FIFO counter number */
554 uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph);
555
556 /* get flag in STAT/RFCS register */
557 FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
558 /* clear USART status */
559 void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
560
561 /* enable USART interrupt */
562 void usart_interrupt_enable(uint32_t usart_periph, uint32_t inttype);
563 /* disable USART interrupt */
564 void usart_interrupt_disable(uint32_t usart_periph, uint32_t inttype);
565 /* enable USART command */
566 void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype);
567 /* get USART interrupt and flag status */
568 FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag);
569 /* clear USART interrupt flag */
570 void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag);
571 #endif /* GD32F3X0_USART_H */
usart_lin_mode_disable
void usart_lin_mode_disable(uint32_t usart_periph)
LIN mode disable.
Definition: gd32f3x0_usart.c:494
usart_parity_config
void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg)
configure USART parity
Definition: gd32f3x0_usart.c:81
USART_DINV_DISABLE
Definition: gd32f3x0_usart.h:271
USART_FLAG_ABDE
Definition: gd32f3x0_usart.h:200
USART_STAT_REG_OFFSET
#define USART_STAT_REG_OFFSET
Definition: gd32f3x0_usart.h:186
usart_receive_fifo_disable
void usart_receive_fifo_disable(uint32_t usart_periph)
receive FIFO disable
Definition: gd32f3x0_usart.c:1016
usart_halfduplex_disable
void usart_halfduplex_disable(uint32_t usart_periph)
half-duplex disable
Definition: gd32f3x0_usart.c:539
USART_FLAG_EB
Definition: gd32f3x0_usart.h:201
USART_FLAG_NERR
Definition: gd32f3x0_usart.h:211
usart_clock_enable
void usart_clock_enable(uint32_t usart_periph)
clock enable
Definition: gd32f3x0_usart.c:553
usart_irda_lowpower_config
void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp)
IrDA low-power configure.
Definition: gd32f3x0_usart.c:761
usart_transmit_config
void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig)
configure USART transmitter
Definition: gd32f3x0_usart.c:161
usart_lin_break_dection_length_config
void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen)
LIN break detection length.
Definition: gd32f3x0_usart.c:511
USART_FLAG_BSY
Definition: gd32f3x0_usart.h:198
usart_oversample_config
void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp)
configure the USART oversample mode
Definition: gd32f3x0_usart.c:300
usart_prescaler_config
void usart_prescaler_config(uint32_t usart_periph, uint32_t psc)
configure the peripheral clock prescaler in USART IrDA low-power mode
Definition: gd32f3x0_usart.c:776
usart_rs485_driver_disable
void usart_rs485_driver_disable(uint32_t usart_periph)
RS485 driver disable.
Definition: gd32f3x0_usart.c:840
USART_INT_FLAG_WU
Definition: gd32f3x0_usart.h:236
USART_FLAG_RFE
Definition: gd32f3x0_usart.h:217
usart_word_length_set
void usart_word_length_set(uint32_t usart_periph, uint32_t wlen)
configure USART word length
Definition: gd32f3x0_usart.c:100
USART_INT_IDLE
Definition: gd32f3x0_usart.h:256
USART_FLAG_CTS
Definition: gd32f3x0_usart.h:203
usart_irda_mode_disable
void usart_irda_mode_disable(uint32_t usart_periph)
IrDA mode disable.
Definition: gd32f3x0_usart.c:744
USART_INT_FLAG_ERR_FERR
Definition: gd32f3x0_usart.h:240
USART_FLAG_RFFINT
Definition: gd32f3x0_usart.h:215
USART_INT_FLAG_PERR
Definition: gd32f3x0_usart.h:227
usart_smartcard_mode_nack_disable
void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
NACK disable in smartcard mode.
Definition: gd32f3x0_usart.c:650
usart_overrun_enable
void usart_overrun_enable(uint32_t usart_periph)
overrun function is enabled
Definition: gd32f3x0_usart.c:271
USART_INT_FLAG_ERR_NERR
Definition: gd32f3x0_usart.h:238
usart_interrupt_flag_clear
void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag)
clear USART interrupt flag
Definition: gd32f3x0_usart.c:1223
usart_hardware_flow_rts_config
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
configure hardware flow control RTS
Definition: gd32f3x0_usart.c:793
USART_FLAG_TC
Definition: gd32f3x0_usart.h:207
usart_command_enable
void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype)
enable USART command
Definition: gd32f3x0_usart.c:1161
usart_invert_enum
usart_invert_enum
Definition: gd32f3x0_usart.h:268
USART_FLAG_REA
Definition: gd32f3x0_usart.h:192
USART_INT_FLAG_CTS
Definition: gd32f3x0_usart.h:237
USART_TXPIN_ENABLE
Definition: gd32f3x0_usart.h:273
usart_dma_transmit_config
void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA transmission
Definition: gd32f3x0_usart.c:923
usart_disable
void usart_disable(uint32_t usart_periph)
disable USART
Definition: gd32f3x0_usart.c:147
USART_CTL0_REG_OFFSET
#define USART_CTL0_REG_OFFSET
Definition: gd32f3x0_usart.h:183
usart_deinit
void usart_deinit(uint32_t usart_periph)
reset USART
Definition: gd32f3x0_usart.c:20
USART_INT_LBD
Definition: gd32f3x0_usart.h:258
usart_block_length_config
void usart_block_length_config(uint32_t usart_periph, uint32_t bl)
block length configure
Definition: gd32f3x0_usart.c:681
USART_FLAG_PERR
Definition: gd32f3x0_usart.h:213
usart_stop_bit_set
void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen)
configure USART stop bit length
Definition: gd32f3x0_usart.c:121
usart_address_detection_mode_config
void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod)
address detection mode configure
Definition: gd32f3x0_usart.c:414
USART_INT_FLAG_RFF
Definition: gd32f3x0_usart.h:242
USART_INT_FLAG_RBNE_ORERR
Definition: gd32f3x0_usart.h:231
usart_receiver_timeout_enable
void usart_receiver_timeout_enable(uint32_t usart_periph)
receiver timeout enable
Definition: gd32f3x0_usart.c:445
usart_overrun_disable
void usart_overrun_disable(uint32_t usart_periph)
overrun function is disabled
Definition: gd32f3x0_usart.c:284
usart_sample_bit_config
void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb)
sample bit method configure
Definition: gd32f3x0_usart.c:318
usart_smartcard_mode_early_nack_disable
void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph)
early NACK disable in smartcard mode
Definition: gd32f3x0_usart.c:719
usart_interrupt_enable
void usart_interrupt_enable(uint32_t usart_periph, uint32_t inttype)
enable USART interrupt
Definition: gd32f3x0_usart.c:1118
USART_TXPIN_DISABLE
Definition: gd32f3x0_usart.h:274
usart_driver_assertime_config
void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime)
driver enable assertion time configure
Definition: gd32f3x0_usart.c:855
USART_RXPIN_ENABLE
Definition: gd32f3x0_usart.h:276
USART_SWAP_DISABLE
Definition: gd32f3x0_usart.h:280
USART_INT_FLAG_EB
Definition: gd32f3x0_usart.h:224
usart_synchronous_clock_config
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
configure USART synchronous mode parameters
Definition: gd32f3x0_usart.c:590
usart_flag_enum
usart_flag_enum
Definition: gd32f3x0_usart.h:190
USART_REGIDX_BIT2
#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2)
Definition: gd32f3x0_usart.h:177
USART_DINV_ENABLE
Definition: gd32f3x0_usart.h:270
usart_smartcard_autoretry_config
void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum)
smartcard auto-retry number configure
Definition: gd32f3x0_usart.c:694
USART_INT_AM
Definition: gd32f3x0_usart.h:251
USART_INT_RFF
Definition: gd32f3x0_usart.h:264
USART_INT_FLAG_LBD
Definition: gd32f3x0_usart.h:234
USART_FLAG_CTSF
Definition: gd32f3x0_usart.h:204
USART_CTL2_REG_OFFSET
#define USART_CTL2_REG_OFFSET
Definition: gd32f3x0_usart.h:185
usart_smartcard_mode_disable
void usart_smartcard_mode_disable(uint32_t usart_periph)
smartcard mode disable
Definition: gd32f3x0_usart.c:622
USART_REGIDX_BIT
#define USART_REGIDX_BIT(regidx, bitpos)
Definition: gd32f3x0_usart.h:174
usart_mute_mode_wakeup_config
void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod)
wakeup method in mute mode configure
Definition: gd32f3x0_usart.c:396
USART_FLAG_SB
Definition: gd32f3x0_usart.h:196
usart_wakeup_mode_config
void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum)
wakeup mode from deep-sleep mode
Definition: gd32f3x0_usart.c:990
usart_smartcard_mode_enable
void usart_smartcard_mode_enable(uint32_t usart_periph)
smartcard mode enable
Definition: gd32f3x0_usart.c:608
USART_INT_WU
Definition: gd32f3x0_usart.h:260
usart_flag_clear
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
clear USART status
Definition: gd32f3x0_usart.c:1092
USART_RFCS_REG_OFFSET
#define USART_RFCS_REG_OFFSET
Definition: gd32f3x0_usart.h:187
usart_interrupt_enum
usart_interrupt_enum
Definition: gd32f3x0_usart.h:246
usart_flag_get
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
get flag in STAT/RFCS register
Definition: gd32f3x0_usart.c:1064
USART_INT_FLAG_TBE
Definition: gd32f3x0_usart.h:228
usart_address_config
void usart_address_config(uint32_t usart_periph, uint8_t addr)
address of the USART terminal
Definition: gd32f3x0_usart.c:430
usart_lin_mode_enable
void usart_lin_mode_enable(uint32_t usart_periph)
LIN mode enable.
Definition: gd32f3x0_usart.c:480
usart_wakeup_enable
void usart_wakeup_enable(uint32_t usart_periph)
USART be able to wake up the MCU from deep-sleep mode.
Definition: gd32f3x0_usart.c:964
USART_INT_FLAG_RT
Definition: gd32f3x0_usart.h:225
USART_INT_FLAG_TC
Definition: gd32f3x0_usart.h:229
usart_smartcard_mode_early_nack_enable
void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph)
early NACK enable in smartcard mode
Definition: gd32f3x0_usart.c:708
usart_driver_deassertime_config
void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime)
driver enable de-assertion time configure
Definition: gd32f3x0_usart.c:871
USART_FLAG_ABD
Definition: gd32f3x0_usart.h:199
usart_interrupt_flag_get
FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
get USART interrupt and flag status
Definition: gd32f3x0_usart.c:1189
USART_SWAP_ENABLE
Definition: gd32f3x0_usart.h:279
usart_receive_config
void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig)
configure USART receiver
Definition: gd32f3x0_usart.c:177
USART_FLAG_RFF
Definition: gd32f3x0_usart.h:216
usart_mute_mode_enable
void usart_mute_mode_enable(uint32_t usart_periph)
mute mode enable
Definition: gd32f3x0_usart.c:371
usart_wakeup_disable
void usart_wakeup_disable(uint32_t usart_periph)
USART be not able to wake up the MCU from deep-sleep mode.
Definition: gd32f3x0_usart.c:975
USART_INT_EB
Definition: gd32f3x0_usart.h:249
USART_INT_PERR
Definition: gd32f3x0_usart.h:252
USART_FLAG_ORERR
Definition: gd32f3x0_usart.h:210
USART_INT_CTS
Definition: gd32f3x0_usart.h:261
USART_INT_FLAG_AM
Definition: gd32f3x0_usart.h:226
usart_reception_error_dma_enable
void usart_reception_error_dma_enable(uint32_t usart_periph)
enable DMA on reception error
Definition: gd32f3x0_usart.c:950
usart_receiver_timeout_disable
void usart_receiver_timeout_disable(uint32_t usart_periph)
receiver timeout disable
Definition: gd32f3x0_usart.c:456
usart_clock_disable
void usart_clock_disable(uint32_t usart_periph)
clock disable
Definition: gd32f3x0_usart.c:567
USART_FLAG_TBE
Definition: gd32f3x0_usart.h:206
usart_autobaud_detection_enable
void usart_autobaud_detection_enable(uint32_t usart_periph)
auto baud rate detection enable
Definition: gd32f3x0_usart.c:333
usart_smartcard_mode_nack_enable
void usart_smartcard_mode_nack_enable(uint32_t usart_periph)
NACK enable in smartcard mode.
Definition: gd32f3x0_usart.c:636
USART_FLAG_AM
Definition: gd32f3x0_usart.h:197
usart_receive_fifo_enable
void usart_receive_fifo_enable(uint32_t usart_periph)
receive FIFO enable
Definition: gd32f3x0_usart.c:1005
usart_data_first_config
void usart_data_first_config(uint32_t usart_periph, uint32_t msbf)
data is transmitted/received with the LSB/MSB first
Definition: gd32f3x0_usart.c:216
usart_receiver_timeout_config
void usart_receiver_timeout_config(uint32_t usart_periph, uint32_t rtimeout)
receiver timeout threshold configure
Definition: gd32f3x0_usart.c:468
USART_FLAG_FERR
Definition: gd32f3x0_usart.h:212
USART_CTL1_REG_OFFSET
#define USART_CTL1_REG_OFFSET
Definition: gd32f3x0_usart.h:184
USART_FLAG_RT
Definition: gd32f3x0_usart.h:202
USART_INT_TBE
Definition: gd32f3x0_usart.h:253
USART_FLAG_WU
Definition: gd32f3x0_usart.h:194
usart_autobaud_detection_mode_config
void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod)
auto baud rate detection mode configure
Definition: gd32f3x0_usart.c:358
usart_autobaud_detection_disable
void usart_autobaud_detection_disable(uint32_t usart_periph)
auto baud rate detection disable
Definition: gd32f3x0_usart.c:344
usart_baudrate_set
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
configure USART baud rate value
Definition: gd32f3x0_usart.c:43
usart_dma_receive_config
void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA reception
Definition: gd32f3x0_usart.c:907
USART_INT_RT
Definition: gd32f3x0_usart.h:250
USART_INT_FLAG_IDLE
Definition: gd32f3x0_usart.h:232
USART_FLAG_TEA
Definition: gd32f3x0_usart.h:193
USART_INT_ERR
Definition: gd32f3x0_usart.h:262
usart_interrupt_disable
void usart_interrupt_disable(uint32_t usart_periph, uint32_t inttype)
disable USART interrupt
Definition: gd32f3x0_usart.c:1144
USART_FLAG_RBNE
Definition: gd32f3x0_usart.h:208
USART_FLAG_IDLE
Definition: gd32f3x0_usart.h:209
USART_FLAG_LBD
Definition: gd32f3x0_usart.h:205
USART_INT_RBNE
Definition: gd32f3x0_usart.h:255
USART_INT_TC
Definition: gd32f3x0_usart.h:254
usart_data_transmit
void usart_data_transmit(uint32_t usart_periph, uint32_t data)
USART transmit data function.
Definition: gd32f3x0_usart.c:191
usart_reception_error_dma_disable
void usart_reception_error_dma_disable(uint32_t usart_periph)
disable DMA on reception error
Definition: gd32f3x0_usart.c:936
usart_halfduplex_enable
void usart_halfduplex_enable(uint32_t usart_periph)
half-duplex enable
Definition: gd32f3x0_usart.c:525
usart_depolarity_config
void usart_depolarity_config(uint32_t usart_periph, uint32_t dep)
configure driver enable polarity mode
Definition: gd32f3x0_usart.c:889
USART_INT_FLAG_ERR_ORERR
Definition: gd32f3x0_usart.h:239
usart_rs485_driver_enable
void usart_rs485_driver_enable(uint32_t usart_periph)
RS485 driver enable.
Definition: gd32f3x0_usart.c:826
usart_enable
void usart_enable(uint32_t usart_periph)
enable USART
Definition: gd32f3x0_usart.c:136
USART_INT_FLAG_RBNE
Definition: gd32f3x0_usart.h:230
USART_RXPIN_DISABLE
Definition: gd32f3x0_usart.h:277
usart_mute_mode_disable
void usart_mute_mode_disable(uint32_t usart_periph)
mute mode disable
Definition: gd32f3x0_usart.c:382
usart_irda_mode_enable
void usart_irda_mode_enable(uint32_t usart_periph)
IrDA mode enable.
Definition: gd32f3x0_usart.c:730
usart_interrupt_flag_enum
usart_interrupt_flag_enum
Definition: gd32f3x0_usart.h:221
usart_data_receive
uint16_t usart_data_receive(uint32_t usart_periph)
USART receive data function.
Definition: gd32f3x0_usart.c:202
usart_receive_fifo_counter_number
uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph)
read receive FIFO counter number
Definition: gd32f3x0_usart.c:1027
usart_invert_config
void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara)
USART inverted configure.
Definition: gd32f3x0_usart.c:231
USART_FLAG_RWU
Definition: gd32f3x0_usart.h:195
usart_hardware_flow_cts_config
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
configure hardware flow control CTS
Definition: gd32f3x0_usart.c:811
usart_guard_time_config
void usart_guard_time_config(uint32_t usart_periph, uint32_t guat)
guard time value configure in smartcard mode
Definition: gd32f3x0_usart.c:665
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_timer.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_timer.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_timer.h"
13
20 void timer_deinit(uint32_t timer_periph)
21 {
22 switch(timer_periph){
23 case TIMER0:
24 /* reset TIMER0 */
25 rcu_periph_reset_enable(RCU_TIMER0RST);
26 rcu_periph_reset_disable(RCU_TIMER0RST);
27 break;
28 case TIMER1:
29 /* reset TIMER1 */
30 rcu_periph_reset_enable(RCU_TIMER1RST);
31 rcu_periph_reset_disable(RCU_TIMER1RST);
32 break;
33 case TIMER2:
34 /* reset TIMER2 */
35 rcu_periph_reset_enable(RCU_TIMER2RST);
36 rcu_periph_reset_disable(RCU_TIMER2RST);
37 break;
38 #ifdef GD32F350
39 case TIMER5:
40 /* reset TIMER5 */
41 rcu_periph_reset_enable(RCU_TIMER5RST);
42 rcu_periph_reset_disable(RCU_TIMER5RST);
43 break;
44 #endif
45 case TIMER13:
46 /* reset TIMER13 */
47 rcu_periph_reset_enable(RCU_TIMER13RST);
48 rcu_periph_reset_disable(RCU_TIMER13RST);
49 break;
50 case TIMER14:
51 /* reset TIMER14 */
52 rcu_periph_reset_enable(RCU_TIMER14RST);
53 rcu_periph_reset_disable(RCU_TIMER14RST);
54 break;
55 case TIMER15:
56 /* reset TIMER15 */
57 rcu_periph_reset_enable(RCU_TIMER15RST);
58 rcu_periph_reset_disable(RCU_TIMER15RST);
59 break;
60 case TIMER16:
61 /* reset TIMER16 */
62 rcu_periph_reset_enable(RCU_TIMER16RST);
63 rcu_periph_reset_disable(RCU_TIMER16RST);
64 break;
65 default:
66 break;
67 }
68 }
69
83 void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
84 {
85 /* configure the counter prescaler value */
86 TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
87
88 /* configure the counter direction and aligned mode */
89 if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph)){
90 TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM);
91 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode;
92 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection;
93 }
94
95 /* configure the autoreload value */
96 TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
97
98 if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER13 == timer_periph)
99 || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){
100 /* reset the CKDIV bit */
101 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV;
102 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision;
103 }
104
105 if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){
106 /* configure the repetition counter value */
107 TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
108 }
109
110 /* generate an update event */
111 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
112 }
113
120 void timer_enable(uint32_t timer_periph)
121 {
122 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
123 }
124
131 void timer_disable(uint32_t timer_periph)
132 {
133 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
134 }
135
142 void timer_auto_reload_shadow_enable(uint32_t timer_periph)
143 {
144 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
145 }
146
153 void timer_auto_reload_shadow_disable(uint32_t timer_periph)
154 {
155 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
156 }
157
164 void timer_update_event_enable(uint32_t timer_periph)
165 {
166 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
167 }
168
175 void timer_update_event_disable(uint32_t timer_periph)
176 {
177 TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
178 }
179
191 void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
192 {
193 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM;
194 TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
195 }
196
203 void timer_counter_up_direction(uint32_t timer_periph)
204 {
205 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
206 }
207
214 void timer_counter_down_direction(uint32_t timer_periph)
215 {
216 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
217 }
218
229 void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
230 {
231 TIMER_PSC(timer_periph) = (uint32_t)prescaler;
232
233 if(TIMER_PSC_RELOAD_NOW == pscreload){
234 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
235 }
236 }
237
245 void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
246 {
247 TIMER_CREP(timer_periph) = (uint32_t)repetition;
248 }
249
257 void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload)
258 {
259 TIMER_CAR(timer_periph) = (uint32_t)autoreload;
260 }
261
269 void timer_counter_value_config(uint32_t timer_periph, uint32_t counter)
270 {
271 TIMER_CNT(timer_periph) = (uint32_t)counter;
272 }
273
280 uint32_t timer_counter_read(uint32_t timer_periph)
281 {
282 uint32_t count_value = 0U;
283 count_value = TIMER_CNT(timer_periph);
284 return (count_value);
285 }
286
293 uint16_t timer_prescaler_read(uint32_t timer_periph)
294 {
295 uint16_t prescaler_value = 0U;
296 prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
297 return (prescaler_value);
298 }
299
309 void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode)
310 {
311 if(TIMER_SP_MODE_SINGLE == spmode){
312 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
313 }else if(TIMER_SP_MODE_REPETITIVE == spmode){
314 TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
315 }else{
316 }
317 }
318
328 void timer_update_source_config(uint32_t timer_periph, uint8_t update)
329 {
330 if(TIMER_UPDATE_SRC_REGULAR == update){
331 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
332 }else if(TIMER_UPDATE_SRC_GLOBAL == update){
333 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
334 }else{
335 }
336 }
337
347 void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear)
348 {
349 if(TIMER_OCPRE_CLEAR_SOURCE_ETIF == ocpreclear){
350 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_OCRC;
351 }else if(TIMER_OCPRE_CLEAR_SOURCE_CLR == ocpreclear){
352 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_OCRC;
353 }else{
354 }
355 }
356
372 void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
373 {
374 TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
375 }
376
392 void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
393 {
394 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
395 }
396
412 FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
413 {
414 uint32_t val;
415 val = (TIMER_DMAINTEN(timer_periph) & interrupt);
416 if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){
417 return SET;
418 }else{
419 return RESET;
420 }
421 }
422
438 void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
439 {
440 TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt);
441 }
442
462 FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
463 {
464 if(RESET != (TIMER_INTF(timer_periph) & flag)){
465 return SET;
466 }else{
467 return RESET;
468 }
469 }
470
490 void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
491 {
492 TIMER_INTF(timer_periph) &= (~(uint32_t)flag);
493 }
494
509 void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
510 {
511 TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
512 }
513
528 void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
529 {
530 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma));
531 }
532
542 void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request)
543 {
544 if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
545 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
546 }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
547 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
548 }else{
549 }
550 }
551
581 void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
582 {
583 TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
584 TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
585 }
586
602 void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
603 {
604 TIMER_SWEVG(timer_periph) |= (uint32_t)event;
605 }
606
621 void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara)
622 {
623 TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))|
624 ((uint32_t)(breakpara->ideloffstate))|
625 ((uint32_t)(breakpara->deadtime))|
626 ((uint32_t)(breakpara->breakpolarity))|
627 ((uint32_t)(breakpara->outputautostate)) |
628 ((uint32_t)(breakpara->protectmode))|
629 ((uint32_t)(breakpara->breakstate))) ;
630 }
631
638 void timer_break_enable(uint32_t timer_periph)
639 {
640 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
641 }
642
649 void timer_break_disable(uint32_t timer_periph)
650 {
651 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
652 }
653
660 void timer_automatic_output_enable(uint32_t timer_periph)
661 {
662 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
663 }
664
671 void timer_automatic_output_disable(uint32_t timer_periph)
672 {
673 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
674 }
675
683 void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
684 {
685 if(ENABLE == newvalue){
686 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
687 }else{
688 TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
689 }
690 }
691
699 void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
700 {
701 if(ENABLE == newvalue){
702 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
703 }else{
704 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
705 }
706 }
707
717 void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl)
718 {
719 if(TIMER_UPDATECTL_CCU == ccuctl){
720 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
721 }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
722 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
723 }else{
724 }
725 }
726
745 void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara)
746 {
747 switch(channel){
748 /* configure TIMER_CH_0 */
749 case TIMER_CH_0:
750 /* reset the CH0EN bit */
751 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
752 /* set the CH0EN bit */
753 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
754 /* reset the CH0P bit */
755 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
756 /* set the CH0P bit */
757 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
758
759 if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){
760 /* reset the CH0NEN bit */
761 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
762 /* set the CH0NEN bit */
763 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
764 /* reset the CH0NP bit */
765 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
766 /* set the CH0NP bit */
767 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
768 /* reset the ISO0 bit */
769 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
770 /* set the ISO0 bit */
771 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
772 /* reset the ISO0N bit */
773 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
774 /* set the ISO0N bit */
775 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
776 }
777 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
778 break;
779 /* configure TIMER_CH_1 */
780 case TIMER_CH_1:
781 /* reset the CH1EN bit */
782 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
783 /* set the CH1EN bit */
784 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 4U);
785 /* reset the CH1P bit */
786 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
787 /* set the CH1P bit */
788 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U);
789
790 if(TIMER0 == timer_periph){
791 /* reset the CH1NEN bit */
792 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
793 /* set the CH1NEN bit */
794 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U);
795 /* reset the CH1NP bit */
796 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
797 /* set the CH1NP bit */
798 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U);
799 /* reset the ISO1 bit */
800 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
801 /* set the ISO1 bit */
802 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
803 /* reset the ISO1N bit */
804 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
805 /* set the ISO1N bit */
806 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U);
807 }
808
809 if(TIMER14 == timer_periph){
810 /* reset the ISO1 bit */
811 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
812 /* set the ISO1 bit */
813 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
814 }
815
816 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
817 break;
818 /* configure TIMER_CH_2 */
819 case TIMER_CH_2:
820 /* reset the CH2EN bit */
821 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
822 /* set the CH2EN bit */
823 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 8U);
824 /* reset the CH2P bit */
825 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
826 /* set the CH2P bit */
827 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U);
828
829 if(TIMER0 == timer_periph){
830 /* reset the CH2NEN bit */
831 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
832 /* set the CH2NEN bit */
833 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U);
834 /* reset the CH2NP bit */
835 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
836 /* set the CH2NP bit */
837 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U);
838 /* reset the ISO2 bit */
839 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
840 /* set the ISO2 bit */
841 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U);
842 /* reset the ISO2N bit */
843 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
844 /* set the ISO2N bit */
845 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U);
846 }
847 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
848 break;
849 /* configure TIMER_CH_3 */
850 case TIMER_CH_3:
851 /* reset the CH3EN bit */
852 TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN);
853 /* set the CH3EN bit */
854 TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 12U);
855 /* reset the CH3P bit */
856 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
857 /* set the CH3P bit */
858 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U);
859
860 if(TIMER0 == timer_periph){
861 /* reset the ISO3 bit */
862 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
863 /* set the ISO3 bit */
864 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U);
865 }
866 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
867 break;
868 default:
869 break;
870 }
871 }
872
893 void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
894 {
895 switch(channel){
896 /* configure TIMER_CH_0 */
897 case TIMER_CH_0:
898 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
899 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
900 break;
901 /* configure TIMER_CH_1 */
902 case TIMER_CH_1:
903 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
904 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
905 break;
906 /* configure TIMER_CH_2 */
907 case TIMER_CH_2:
908 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
909 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
910 break;
911 /* configure TIMER_CH_3 */
912 case TIMER_CH_3:
913 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
914 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
915 break;
916 default:
917 break;
918 }
919 }
920
933 void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
934 {
935 switch(channel){
936 case TIMER_CH_0:
937 TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
938 break;
939 case TIMER_CH_1:
940 TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
941 break;
942 case TIMER_CH_2:
943 TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
944 break;
945 case TIMER_CH_3:
946 TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
947 break;
948 default:
949 break;
950 }
951 }
952
967 void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
968 {
969 switch(channel){
970 /* configure TIMER_CH_0 */
971 case TIMER_CH_0:
972 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
973 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
974 break;
975 /* configure TIMER_CH_1 */
976 case TIMER_CH_1:
977 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
978 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
979 break;
980 /* configure TIMER_CH_2 */
981 case TIMER_CH_2:
982 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
983 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
984 break;
985 /* configure TIMER_CH_3 */
986 case TIMER_CH_3:
987 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
988 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
989 break;
990 default:
991 break;
992 }
993 }
994
1009 void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
1010 {
1011 switch(channel){
1012 /* configure TIMER_CH_0 */
1013 case TIMER_CH_0:
1014 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
1015 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
1016 break;
1017 /* configure TIMER_CH_1 */
1018 case TIMER_CH_1:
1019 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN);
1020 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1021 break;
1022 /* configure TIMER_CH_2 */
1023 case TIMER_CH_2:
1024 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN);
1025 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
1026 break;
1027 /* configure TIMER_CH_3 */
1028 case TIMER_CH_3:
1029 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN);
1030 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1031 break;
1032 default:
1033 break;
1034 }
1035 }
1036
1051 void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
1052 {
1053 switch(channel){
1054 /* configure TIMER_CH_0 */
1055 case TIMER_CH_0:
1056 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
1057 TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
1058 break;
1059 /* configure TIMER_CH_1 */
1060 case TIMER_CH_1:
1061 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
1062 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1063 break;
1064 /* configure TIMER_CH_2 */
1065 case TIMER_CH_2:
1066 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
1067 TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
1068 break;
1069 /* configure TIMER_CH_3 */
1070 case TIMER_CH_3:
1071 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
1072 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1073 break;
1074 default:
1075 break;
1076 }
1077 }
1078
1093 void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
1094 {
1095 switch(channel){
1096 /* configure TIMER_CH_0 */
1097 case TIMER_CH_0:
1098 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
1099 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
1100 break;
1101 /* configure TIMER_CH_1 */
1102 case TIMER_CH_1:
1103 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
1104 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
1105 break;
1106 /* configure TIMER_CH_2 */
1107 case TIMER_CH_2:
1108 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
1109 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
1110 break;
1111 /* configure TIMER_CH_3 */
1112 case TIMER_CH_3:
1113 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
1114 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
1115 break;
1116 default:
1117 break;
1118 }
1119 }
1120
1135 void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
1136 {
1137 switch(channel){
1138 /* configure TIMER_CH_0 */
1139 case TIMER_CH_0:
1140 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
1141 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
1142 break;
1143 /* configure TIMER_CH_1 */
1144 case TIMER_CH_1:
1145 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
1146 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
1147 break;
1148 /* configure TIMER_CH_2 */
1149 case TIMER_CH_2:
1150 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
1151 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
1152 break;
1153 /* configure TIMER_CH_3 */
1154 case TIMER_CH_3:
1155 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3NP);
1156 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 12U);
1157 break;
1158 default:
1159 break;
1160 }
1161 }
1162
1177 void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
1178 {
1179 switch(channel){
1180 /* configure TIMER_CH_0 */
1181 case TIMER_CH_0:
1182 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1183 TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
1184 break;
1185 /* configure TIMER_CH_1 */
1186 case TIMER_CH_1:
1187 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1188 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
1189 break;
1190 /* configure TIMER_CH_2 */
1191 case TIMER_CH_2:
1192 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1193 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
1194 break;
1195 /* configure TIMER_CH_3 */
1196 case TIMER_CH_3:
1197 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1198 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
1199 break;
1200 default:
1201 break;
1202 }
1203 }
1204
1218 void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
1219 {
1220 switch(channel){
1221 /* configure TIMER_CH_0 */
1222 case TIMER_CH_0:
1223 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
1224 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
1225 break;
1226 /* configure TIMER_CH_1 */
1227 case TIMER_CH_1:
1228 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
1229 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
1230 break;
1231 /* configure TIMER_CH_2 */
1232 case TIMER_CH_2:
1233 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
1234 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
1235 break;
1236 default:
1237 break;
1238 }
1239 }
1240
1257 void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic_parameter_struct* icpara)
1258 {
1259 switch(channel){
1260 /* configure TIMER_CH_0 */
1261 case TIMER_CH_0:
1262 /* reset the CH0EN bit */
1263 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1264
1265 /* reset the CH0P and CH0NP bits */
1266 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1267 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
1268 /* reset the CH0MS bit */
1269 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1270 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
1271 /* reset the CH0CAPFLT bit */
1272 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1273 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1274
1275 /* set the CH0EN bit */
1276 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1277 break;
1278
1279 /* configure TIMER_CH_1 */
1280 case TIMER_CH_1:
1281 /* reset the CH1EN bit */
1282 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1283
1284 /* reset the CH1P and CH1NP bits */
1285 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1286 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U);
1287 /* reset the CH1MS bit */
1288 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1289 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1290 /* reset the CH1CAPFLT bit */
1291 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1292 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1293
1294 /* set the CH1EN bit */
1295 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1296 break;
1297 /* configure TIMER_CH_2 */
1298 case TIMER_CH_2:
1299 /* reset the CH2EN bit */
1300 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1301
1302 /* reset the CH2P and CH2NP bits */
1303 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP));
1304 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U);
1305
1306 /* reset the CH2MS bit */
1307 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
1308 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection));
1309
1310 /* reset the CH2CAPFLT bit */
1311 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
1312 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1313
1314 /* set the CH2EN bit */
1315 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
1316 break;
1317 /* configure TIMER_CH_3 */
1318 case TIMER_CH_3:
1319 /* reset the CH3EN bit */
1320 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1321
1322 /* reset the CH3P and CH3NP bits */
1323 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P|TIMER_CHCTL2_CH3NP));
1324 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U);
1325
1326 /* reset the CH3MS bit */
1327 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
1328 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1329
1330 /* reset the CH3CAPFLT bit */
1331 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
1332 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1333
1334 /* set the CH3EN bit */
1335 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
1336 break;
1337 default:
1338 break;
1339 }
1340 /* configure TIMER channel input capture prescaler value */
1341 timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler));
1342 }
1343
1360 void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
1361 {
1362 switch(channel){
1363 /* configure TIMER_CH_0 */
1364 case TIMER_CH_0:
1365 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
1366 TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
1367 break;
1368 /* configure TIMER_CH_1 */
1369 case TIMER_CH_1:
1370 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
1371 TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
1372 break;
1373 /* configure TIMER_CH_2 */
1374 case TIMER_CH_2:
1375 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
1376 TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
1377 break;
1378 /* configure TIMER_CH_3 */
1379 case TIMER_CH_3:
1380 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
1381 TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
1382 break;
1383 default:
1384 break;
1385 }
1386 }
1387
1399 uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
1400 {
1401 uint32_t count_value = 0U;
1402
1403 switch(channel){
1404 case TIMER_CH_0:
1405 count_value = TIMER_CH0CV(timer_periph);
1406 break;
1407 case TIMER_CH_1:
1408 count_value = TIMER_CH1CV(timer_periph);
1409 break;
1410 case TIMER_CH_2:
1411 count_value = TIMER_CH2CV(timer_periph);
1412 break;
1413 case TIMER_CH_3:
1414 count_value = TIMER_CH3CV(timer_periph);
1415 break;
1416 default:
1417 break;
1418 }
1419 return (count_value);
1420 }
1421
1436 void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm)
1437 {
1438 uint16_t icpolarity = 0x0U;
1439 uint16_t icselection = 0x0U;
1440
1441 if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
1442 icpolarity = TIMER_IC_POLARITY_FALLING;
1443 }else{
1444 icpolarity = TIMER_IC_POLARITY_RISING;
1445 }
1446
1447 if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
1448 icselection = TIMER_IC_SELECTION_INDIRECTTI;
1449 }else{
1450 icselection = TIMER_IC_SELECTION_DIRECTTI;
1451 }
1452
1453 if(TIMER_CH_0 == channel){
1454 /* reset the CH0EN bit */
1455 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1456 /* reset the CH0P and CH0NP bits */
1457 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1458 /* set the CH0P and CH0NP bits */
1459 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
1460 /* reset the CH0MS bit */
1461 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1462 /* set the CH0MS bit */
1463 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
1464 /* reset the CH0CAPFLT bit */
1465 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1466 /* set the CH0CAPFLT bit */
1467 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1468 /* set the CH0EN bit */
1469 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1470 /* configure TIMER channel input capture prescaler value */
1471 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler));
1472
1473 /* reset the CH1EN bit */
1474 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1475 /* reset the CH1P and CH1NP bits */
1476 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1477 /* set the CH1P and CH1NP bits */
1478 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U);
1479 /* reset the CH1MS bit */
1480 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1481 /* set the CH1MS bit */
1482 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U);
1483 /* reset the CH1CAPFLT bit */
1484 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1485 /* set the CH1CAPFLT bit */
1486 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1487 /* set the CH1EN bit */
1488 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1489 /* configure TIMER channel input capture prescaler value */
1490 timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler));
1491 }else{
1492 /* reset the CH1EN bit */
1493 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1494 /* reset the CH1P and CH1NP bits */
1495 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1496 /* set the CH1P and CH1NP bits */
1497 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U);
1498 /* reset the CH1MS bit */
1499 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1500 /* set the CH1MS bit */
1501 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U);
1502 /* reset the CH1CAPFLT bit */
1503 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1504 /* set the CH1CAPFLT bit */
1505 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1506 /* set the CH1EN bit */
1507 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1508 /* configure TIMER channel input capture prescaler value */
1509 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
1510
1511 /* reset the CH0EN bit */
1512 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1513 /* reset the CH0P and CH0NP bits */
1514 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1515 /* set the CH0P and CH0NP bits */
1516 TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
1517 /* reset the CH0MS bit */
1518 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1519 /* set the CH0MS bit */
1520 TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
1521 /* reset the CH0CAPFLT bit */
1522 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1523 /* set the CH0CAPFLT bit */
1524 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1525 /* set the CH0EN bit */
1526 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1527 /* configure TIMER channel input capture prescaler value */
1528 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
1529 }
1530 }
1531
1541 void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode)
1542 {
1543 if(TIMER_HALLINTERFACE_ENABLE == hallmode){
1544 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
1545 }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
1546 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
1547 }else{
1548 }
1549 }
1550
1565 void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
1566 {
1567 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
1568 TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
1569 }
1570
1586 void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
1587 {
1588 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
1589 TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
1590 }
1591
1608 void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
1609 {
1610 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1611
1612 TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
1613 }
1614
1624 void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave)
1625 {
1626 if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
1627 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
1628 }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
1629 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
1630 }else{
1631 }
1632 }
1633
1649 void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler,
1650 uint32_t expolarity, uint32_t extfilter)
1651 {
1652 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC));
1653 TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | expolarity);
1654 TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U);
1655 }
1656
1673 void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode,
1674 uint16_t ic0polarity, uint16_t ic1polarity)
1675 {
1676 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1677 TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
1678
1679 TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS)));
1680 TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U));
1681
1682 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1683 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1684 TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity << 4U));
1685 }
1686
1693 void timer_internal_clock_config(uint32_t timer_periph)
1694 {
1695 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1696 }
1697
1708 void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
1709 {
1710 timer_input_trigger_source_select(timer_periph, intrigger);
1711 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1712 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1713 }
1714
1729 void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger,
1730 uint16_t expolarity, uint32_t extfilter)
1731 {
1732 if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
1733 /* reset the CH1EN bit */
1734 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1735 /* reset the CH1NP bit */
1736 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
1737 /* set the CH1NP bit */
1738 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)expolarity << 4U);
1739 /* reset the CH1MS bit */
1740 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1741 /* set the CH1MS bit */
1742 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U);
1743 /* reset the CH1CAPFLT bit */
1744 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1745 /* set the CH1CAPFLT bit */
1746 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U);
1747 /* set the CH1EN bit */
1748 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1749 }else{
1750 /* reset the CH0EN bit */
1751 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1752 /* reset the CH0P and CH0NP bits */
1753 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
1754 /* set the CH0P and CH0NP bits */
1755 TIMER_CHCTL2(timer_periph) |= (uint32_t)expolarity;
1756 /* reset the CH0MS bit */
1757 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1758 /* set the CH0MS bit */
1759 TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
1760 /* reset the CH0CAPFLT bit */
1761 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1762 /* reset the CH0CAPFLT bit */
1763 TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter;
1764 /* set the CH0EN bit */
1765 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1766 }
1767 /* select TIMER input trigger source */
1768 timer_input_trigger_source_select(timer_periph,extrigger);
1769 /* reset the SMC bit */
1770 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1771 /* set the SMC bit */
1772 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1773 }
1774
1790 void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler,
1791 uint32_t expolarity, uint32_t extfilter)
1792 {
1793 /* configure TIMER external trigger input */
1794 timer_external_trigger_config(timer_periph, extprescaler, expolarity, extfilter);
1795
1796 /* reset the SMC bit,TRGS bit */
1797 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
1798 /* set the SMC bit,TRGS bit */
1799 TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
1800 }
1801
1817 void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler,
1818 uint32_t expolarity, uint32_t extfilter)
1819 {
1820 /* configure TIMER external trigger input */
1821 timer_external_trigger_config(timer_periph, extprescaler, expolarity, extfilter);
1822
1823 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
1824 }
1825
1832 void timer_external_clock_mode1_disable(uint32_t timer_periph)
1833 {
1834 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
1835 }
1836
1848 void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap)
1849 {
1850 TIMER_IRMP(timer_periph) = (uint32_t)remap;
1851 }
1852
1862 void timer_write_cc_register_config(uint32_t timer_periph, uint16_t ccsel)
1863 {
1864 if(TIMER_CCSEL_ENABLE == ccsel){
1865 TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL;
1866 }else if(TIMER_CCSEL_DISABLE == ccsel){
1867 TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL;
1868 }else{
1869 }
1870 }
1871
1881 void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel)
1882 {
1883 if(TIMER_OUTSEL_ENABLE == outsel){
1884 TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL;
1885 }else if(TIMER_OUTSEL_DISABLE == outsel){
1886 TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL;
1887 }else{
1888 }
1889 }
timer_counter_down_direction
void timer_counter_down_direction(uint32_t timer_periph)
set TIMER counter down direction
Definition: gd32f3x0_timer.c:214
TIMER_IC_POLARITY_RISING
#define TIMER_IC_POLARITY_RISING
Definition: gd32f3x0_timer.h:494
TIMER_SP_MODE_REPETITIVE
#define TIMER_SP_MODE_REPETITIVE
Definition: gd32f3x0_timer.h:404
timer_init
void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara)
initialize TIMER counter
Definition: gd32f3x0_timer.c:83
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#define TIMER_UPDATECTL_CCU
Definition: gd32f3x0_timer.h:490
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#define TIMER_CTL1_TI0S
Definition: gd32f3x0_timer.h:69
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#define TIMER_CNT(timerx)
Definition: gd32f3x0_timer.h:39
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#define TIMER_CHCTL0_CH0COMCEN
Definition: gd32f3x0_timer.h:135
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#define TIMER0
Definition: gd32f3x0_timer.h:18
timer_autoreload_value_config
void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload)
configure TIMER autoreload register value
Definition: gd32f3x0_timer.c:257
timer_channel_input_capture_prescaler_config
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value
Definition: gd32f3x0_timer.c:1360
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uint16_t deadtime
Definition: gd32f3x0_timer.h:253
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#define TIMER_CHCTL2_CH1P
Definition: gd32f3x0_timer.h:171
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void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
clear TIMER interrupt flag
Definition: gd32f3x0_timer.c:438
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#define TIMER_CTL1_DMAS
Definition: gd32f3x0_timer.h:67
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uint16_t icselection
Definition: gd32f3x0_timer.h:275
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#define TIMER_CFG_CHVSEL
Definition: gd32f3x0_timer.h:234
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void timer_enable(uint32_t timer_periph)
enable a TIMER
Definition: gd32f3x0_timer.c:120
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#define TIMER_CCHP_BRKEN
Definition: gd32f3x0_timer.h:217
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void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
enable the TIMER DMA
Definition: gd32f3x0_timer.c:509
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#define TIMER_CHCTL2_CH1NEN
Definition: gd32f3x0_timer.h:172
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uint16_t ocnidlestate
Definition: gd32f3x0_timer.h:268
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#define TIMER_CTL1_ISO1
Definition: gd32f3x0_timer.h:72
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void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara)
configure TIMER input capture parameter
Definition: gd32f3x0_timer.c:1257
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void timer_automatic_output_disable(uint32_t timer_periph)
disable TIMER output automatic function
Definition: gd32f3x0_timer.c:671
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#define TIMER_SP_MODE_SINGLE
Definition: gd32f3x0_timer.h:403
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void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
disable the TIMER DMA
Definition: gd32f3x0_timer.c:528
timer_channel_output_mode_config
void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
configure TIMER channel output compare mode
Definition: gd32f3x0_timer.c:893
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#define TIMER_CH_1
Definition: gd32f3x0_timer.h:439
TIMER_OUTSEL_ENABLE
#define TIMER_OUTSEL_ENABLE
Definition: gd32f3x0_timer.h:571
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#define TIMER_CHCTL1_CH3MS
Definition: gd32f3x0_timer.h:154
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#define TIMER_CHCTL0_CH1CAPPSC
Definition: gd32f3x0_timer.h:144
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#define TIMER_CH_2
Definition: gd32f3x0_timer.h:440
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void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm)
configure TIMER input pwm capture function
Definition: gd32f3x0_timer.c:1436
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#define TIMER_DMACFG(timerx)
Definition: gd32f3x0_timer.h:48
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void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
enable the TIMER interrupt
Definition: gd32f3x0_timer.c:372
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void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap)
configure TIMER channel remap function
Definition: gd32f3x0_timer.c:1848
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#define TIMER_CHCTL1_CH3COMCTL
Definition: gd32f3x0_timer.h:157
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#define TIMER_CTL1_CCUC
Definition: gd32f3x0_timer.h:66
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#define TIMER_CHCTL0_CH1COMCTL
Definition: gd32f3x0_timer.h:139
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void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
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void timer_internal_clock_config(uint32_t timer_periph)
configure TIMER internal clock mode
Definition: gd32f3x0_timer.c:1693
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#define TIMER16
Definition: gd32f3x0_timer.h:27
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uint32_t ideloffstate
Definition: gd32f3x0_timer.h:252
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#define TIMER_UPDATE_SRC_REGULAR
Definition: gd32f3x0_timer.h:407
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#define TIMER_CAR(timerx)
Definition: gd32f3x0_timer.h:41
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void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
set TIMER counter alignment mode
Definition: gd32f3x0_timer.c:191
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#define TIMER_DMACFG_DMATC
Definition: gd32f3x0_timer.h:224
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#define TIMER_CHCTL1_CH2CAPPSC
Definition: gd32f3x0_timer.h:160
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Definition: gd32f3x0_timer.h:56
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#define TIMER_CHCTL0_CH0CAPPSC
Definition: gd32f3x0_timer.h:142
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#define TIMER_CHCTL0_CH0COMCTL
Definition: gd32f3x0_timer.h:134
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void timer_auto_reload_shadow_enable(uint32_t timer_periph)
enable the auto reload shadow function
Definition: gd32f3x0_timer.c:142
TIMER_CHCTL2_CH2NEN
#define TIMER_CHCTL2_CH2NEN
Definition: gd32f3x0_timer.h:176
TIMER_SWEVG_UPG
#define TIMER_SWEVG_UPG
Definition: gd32f3x0_timer.h:120
timer_channel_output_state_config
void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
configure TIMER channel enable state
Definition: gd32f3x0_timer.c:1177
timer_channel_complementary_output_state_config
void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
configure TIMER channel complementary output enable state
Definition: gd32f3x0_timer.c:1218
TIMER_SMCFG_TRGS
#define TIMER_SMCFG_TRGS
Definition: gd32f3x0_timer.h:81
TIMER_CTL1_ISO3
#define TIMER_CTL1_ISO3
Definition: gd32f3x0_timer.h:76
TIMER_CHCTL2_CH3NP
#define TIMER_CHCTL2_CH3NP
Definition: gd32f3x0_timer.h:180
TIMER14
#define TIMER14
Definition: gd32f3x0_timer.h:25
TIMER_CTL1
#define TIMER_CTL1(timerx)
Definition: gd32f3x0_timer.h:31
timer_counter_value_config
void timer_counter_value_config(uint32_t timer_periph, uint32_t counter)
configure TIMER counter register value
Definition: gd32f3x0_timer.c:269
TIMER_SMCFG_ETPSC
#define TIMER_SMCFG_ETPSC
Definition: gd32f3x0_timer.h:84
TIMER_CHCTL1_CH3CAPFLT
#define TIMER_CHCTL1_CH3CAPFLT
Definition: gd32f3x0_timer.h:163
TIMER_SMCFG_OCRC
#define TIMER_SMCFG_OCRC
Definition: gd32f3x0_timer.h:80
TIMER_SMCFG
#define TIMER_SMCFG(timerx)
Definition: gd32f3x0_timer.h:32
TIMER_SMCFG_TRGSEL_ETIFP
#define TIMER_SMCFG_TRGSEL_ETIFP
Definition: gd32f3x0_timer.h:518
TIMER_MASTER_SLAVE_MODE_ENABLE
#define TIMER_MASTER_SLAVE_MODE_ENABLE
Definition: gd32f3x0_timer.h:547
TIMER_CTL0_CKDIV
#define TIMER_CTL0_CKDIV
Definition: gd32f3x0_timer.h:62
TIMER_CHCTL1
#define TIMER_CHCTL1(timerx)
Definition: gd32f3x0_timer.h:37
timer_oc_parameter_struct::ocpolarity
uint16_t ocpolarity
Definition: gd32f3x0_timer.h:265
TIMER_CHCTL2_CH1NP
#define TIMER_CHCTL2_CH1NP
Definition: gd32f3x0_timer.h:173
timer_channel_output_polarity_config
void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
configure TIMER channel output polarity
Definition: gd32f3x0_timer.c:1093
timer_dma_transfer_config
void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
configure the TIMER DMA transfer
Definition: gd32f3x0_timer.c:581
timer_external_clock_mode1_config
void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode1
Definition: gd32f3x0_timer.c:1817
timer_counter_up_direction
void timer_counter_up_direction(uint32_t timer_periph)
set TIMER counter up direction
Definition: gd32f3x0_timer.c:203
TIMER_CTL0_UPS
#define TIMER_CTL0_UPS
Definition: gd32f3x0_timer.h:57
TIMER_DMAREQUEST_CHANNELEVENT
#define TIMER_DMAREQUEST_CHANNELEVENT
Definition: gd32f3x0_timer.h:325
TIMER_CTL1_ISO1N
#define TIMER_CTL1_ISO1N
Definition: gd32f3x0_timer.h:73
TIMER2
#define TIMER2
Definition: gd32f3x0_timer.h:20
timer_channel_capture_value_register_read
uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
read TIMER channel capture compare register value
Definition: gd32f3x0_timer.c:1399
TIMER_CHCTL2_CH0NP
#define TIMER_CHCTL2_CH0NP
Definition: gd32f3x0_timer.h:169
TIMER_CHCTL1_CH2MS
#define TIMER_CHCTL1_CH2MS
Definition: gd32f3x0_timer.h:149
TIMER_CHCTL2_CH2EN
#define TIMER_CHCTL2_CH2EN
Definition: gd32f3x0_timer.h:174
TIMER_HALLINTERFACE_ENABLE
#define TIMER_HALLINTERFACE_ENABLE
Definition: gd32f3x0_timer.h:562
TIMER_CH0CV
#define TIMER_CH0CV(timerx)
Definition: gd32f3x0_timer.h:43
TIMER_CH3CV
#define TIMER_CH3CV(timerx)
Definition: gd32f3x0_timer.h:46
TIMER_CHCTL2_CH0EN
#define TIMER_CHCTL2_CH0EN
Definition: gd32f3x0_timer.h:166
gd32f3x0_timer.h
definitions for the TIMER
TIMER_SMCFG_ETP
#define TIMER_SMCFG_ETP
Definition: gd32f3x0_timer.h:86
TIMER_CHCTL1_CH2COMCTL
#define TIMER_CHCTL1_CH2COMCTL
Definition: gd32f3x0_timer.h:152
timer_auto_reload_shadow_disable
void timer_auto_reload_shadow_disable(uint32_t timer_periph)
disable the auto reload shadow function
Definition: gd32f3x0_timer.c:153
TIMER_PSC_RELOAD_NOW
#define TIMER_PSC_RELOAD_NOW
Definition: gd32f3x0_timer.h:389
timer_interrupt_disable
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
disable the TIMER interrupt
Definition: gd32f3x0_timer.c:392
TIMER_CHCTL1_CH2COMSEN
#define TIMER_CHCTL1_CH2COMSEN
Definition: gd32f3x0_timer.h:151
timer_event_software_generate
void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
software generate events
Definition: gd32f3x0_timer.c:602
timer_channel_output_fast_config
void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
configure TIMER channel output fast function
Definition: gd32f3x0_timer.c:1009
TIMER_MASTER_SLAVE_MODE_DISABLE
#define TIMER_MASTER_SLAVE_MODE_DISABLE
Definition: gd32f3x0_timer.h:548
TIMER_CHCTL0_CH0COMSEN
#define TIMER_CHCTL0_CH0COMSEN
Definition: gd32f3x0_timer.h:133
timer_ic_parameter_struct::icprescaler
uint16_t icprescaler
Definition: gd32f3x0_timer.h:276
RCU_TIMER1RST
Definition: gd32f3x0_rcu.h:344
TIMER_CH_3
#define TIMER_CH_3
Definition: gd32f3x0_timer.h:441
timer_master_slave_mode_config
void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave)
configure TIMER master slave mode
Definition: gd32f3x0_timer.c:1624
TIMER_CHCTL2_CH0P
#define TIMER_CHCTL2_CH0P
Definition: gd32f3x0_timer.h:167
timer_primary_output_config
void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
configure TIMER primary output function
Definition: gd32f3x0_timer.c:683
timer_disable
void timer_disable(uint32_t timer_periph)
disable a TIMER
Definition: gd32f3x0_timer.c:131
TIMER_CHCTL1_CH3COMFEN
#define TIMER_CHCTL1_CH3COMFEN
Definition: gd32f3x0_timer.h:155
TIMER_CTL1_CCSE
#define TIMER_CTL1_CCSE
Definition: gd32f3x0_timer.h:65
TIMER_CH1CV
#define TIMER_CH1CV(timerx)
Definition: gd32f3x0_timer.h:44
timer_repetition_value_config
void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
configure TIMER repetition register value
Definition: gd32f3x0_timer.c:245
TIMER_IRMP
#define TIMER_IRMP(timerx)
Definition: gd32f3x0_timer.h:50
TIMER_CCHP_POEN
#define TIMER_CCHP_POEN
Definition: gd32f3x0_timer.h:220
timer_channel_output_shadow_config
void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
configure TIMER channel output shadow function
Definition: gd32f3x0_timer.c:967
timer_channel_output_clear_config
void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
configure TIMER channel output clear function
Definition: gd32f3x0_timer.c:1051
TIMER_SMCFG_SMC1
#define TIMER_SMCFG_SMC1
Definition: gd32f3x0_timer.h:85
TIMER_SMCFG_ETFC
#define TIMER_SMCFG_ETFC
Definition: gd32f3x0_timer.h:83
timer_prescaler_config
void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
configure TIMER prescaler
Definition: gd32f3x0_timer.c:229
TIMER_PSC
#define TIMER_PSC(timerx)
Definition: gd32f3x0_timer.h:40
RCU_TIMER13RST
Definition: gd32f3x0_rcu.h:346
timer_channel_output_pulse_value_config
void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
configure TIMER channel output pulse value
Definition: gd32f3x0_timer.c:933
TIMER_CHCTL1_CH3CAPPSC
#define TIMER_CHCTL1_CH3CAPPSC
Definition: gd32f3x0_timer.h:162
timer_update_event_disable
void timer_update_event_disable(uint32_t timer_periph)
disable the update event
Definition: gd32f3x0_timer.c:175
TIMER_CTL0_SPM
#define TIMER_CTL0_SPM
Definition: gd32f3x0_timer.h:58
RCU_TIMER14RST
Definition: gd32f3x0_rcu.h:339
TIMER_CHCTL1_CH3COMCEN
#define TIMER_CHCTL1_CH3COMCEN
Definition: gd32f3x0_timer.h:158
TIMER_CREP
#define TIMER_CREP(timerx)
Definition: gd32f3x0_timer.h:42
timer_parameter_struct::clockdivision
uint16_t clockdivision
Definition: gd32f3x0_timer.h:244
TIMER_CCSEL_ENABLE
#define TIMER_CCSEL_ENABLE
Definition: gd32f3x0_timer.h:567
TIMER_DMAREQUEST_UPDATEEVENT
#define TIMER_DMAREQUEST_UPDATEEVENT
Definition: gd32f3x0_timer.h:324
TIMER_HALLINTERFACE_DISABLE
#define TIMER_HALLINTERFACE_DISABLE
Definition: gd32f3x0_timer.h:563
timer_break_parameter_struct::outputautostate
uint16_t outputautostate
Definition: gd32f3x0_timer.h:255
timer_channel_complementary_output_polarity_config
void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
configure TIMER channel complementary output polarity
Definition: gd32f3x0_timer.c:1135
TIMER_CHCTL0_CH0CAPFLT
#define TIMER_CHCTL0_CH0CAPFLT
Definition: gd32f3x0_timer.h:143
TIMER_CHCTL2_CH3EN
#define TIMER_CHCTL2_CH3EN
Definition: gd32f3x0_timer.h:178
timer_interrupt_flag_get
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
get timer interrupt flag
Definition: gd32f3x0_timer.c:412
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
TIMER_CHCTL2_CH2P
#define TIMER_CHCTL2_CH2P
Definition: gd32f3x0_timer.h:175
timer_update_source_config
void timer_update_source_config(uint32_t timer_periph, uint8_t update)
configure TIMER update source
Definition: gd32f3x0_timer.c:328
TIMER_UPDATE_SRC_GLOBAL
#define TIMER_UPDATE_SRC_GLOBAL
Definition: gd32f3x0_timer.h:408
TIMER_SMCFG_SMC
#define TIMER_SMCFG_SMC
Definition: gd32f3x0_timer.h:79
TIMER_CHCTL1_CH3COMSEN
#define TIMER_CHCTL1_CH3COMSEN
Definition: gd32f3x0_timer.h:156
TIMER_CH_0
#define TIMER_CH_0
Definition: gd32f3x0_timer.h:438
timer_flag_clear
void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
clear TIMER flags
Definition: gd32f3x0_timer.c:490
timer_prescaler_read
uint16_t timer_prescaler_read(uint32_t timer_periph)
read TIMER prescaler value
Definition: gd32f3x0_timer.c:293
timer_quadrature_decoder_mode_config
void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
configure TIMER quadrature decoder mode
Definition: gd32f3x0_timer.c:1673
TIMER_CHCTL0_CH1COMCEN
#define TIMER_CHCTL0_CH1COMCEN
Definition: gd32f3x0_timer.h:140
TIMER_INTF
#define TIMER_INTF(timerx)
Definition: gd32f3x0_timer.h:34
timer_ocpre_clear_source_config
void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear)
configure TIMER OCPRE clear source selection
Definition: gd32f3x0_timer.c:347
TIMER_IC_SELECTION_INDIRECTTI
#define TIMER_IC_SELECTION_INDIRECTTI
Definition: gd32f3x0_timer.h:500
TIMER_CHCTL0_CH1COMSEN
#define TIMER_CHCTL0_CH1COMSEN
Definition: gd32f3x0_timer.h:138
TIMER_CHCTL2
#define TIMER_CHCTL2(timerx)
Definition: gd32f3x0_timer.h:38
TIMER_CTL0_ARSE
#define TIMER_CTL0_ARSE
Definition: gd32f3x0_timer.h:61
TIMER15
#define TIMER15
Definition: gd32f3x0_timer.h:26
timer_external_trigger_as_external_clock_config
void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter)
configure TIMER the external trigger as external clock input
Definition: gd32f3x0_timer.c:1729
timer_master_output_trigger_source_select
void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
select TIMER master mode output trigger source
Definition: gd32f3x0_timer.c:1586
timer_ic_parameter_struct::icpolarity
uint16_t icpolarity
Definition: gd32f3x0_timer.h:274
timer_internal_trigger_as_external_clock_config
void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
configure TIMER the internal trigger as external clock input
Definition: gd32f3x0_timer.c:1708
timer_break_parameter_struct
Definition: gd32f3x0_timer.h:249
TIMER_SMCFG_MSM
#define TIMER_SMCFG_MSM
Definition: gd32f3x0_timer.h:82
timer_external_clock_mode0_config
void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode0
Definition: gd32f3x0_timer.c:1790
TIMER_CCHP
#define TIMER_CCHP(timerx)
Definition: gd32f3x0_timer.h:47
timer_deinit
void timer_deinit(uint32_t timer_periph)
deinit a TIMER
Definition: gd32f3x0_timer.c:20
TIMER_CTL0
#define TIMER_CTL0(timerx)
Definition: gd32f3x0_timer.h:30
TIMER1
#define TIMER1
Definition: gd32f3x0_timer.h:19
timer_write_cc_register_config
void timer_write_cc_register_config(uint32_t timer_periph, uint16_t ccsel)
configure TIMER write CHxVAL register selection
Definition: gd32f3x0_timer.c:1862
timer_break_parameter_struct::runoffstate
uint16_t runoffstate
Definition: gd32f3x0_timer.h:251
TIMER_OCPRE_CLEAR_SOURCE_ETIF
#define TIMER_OCPRE_CLEAR_SOURCE_ETIF
Definition: gd32f3x0_timer.h:544
TIMER_SWEVG
#define TIMER_SWEVG(timerx)
Definition: gd32f3x0_timer.h:35
TIMER13
#define TIMER13
Definition: gd32f3x0_timer.h:24
timer_input_trigger_source_select
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source
Definition: gd32f3x0_timer.c:1565
timer_oc_parameter_struct::outputstate
uint32_t outputstate
Definition: gd32f3x0_timer.h:263
TIMER_CTL0_CAM
#define TIMER_CTL0_CAM
Definition: gd32f3x0_timer.h:60
timer_oc_parameter_struct::ocidlestate
uint16_t ocidlestate
Definition: gd32f3x0_timer.h:267
timer_break_parameter_struct::breakpolarity
uint16_t breakpolarity
Definition: gd32f3x0_timer.h:254
timer_parameter_struct::repetitioncounter
uint8_t repetitioncounter
Definition: gd32f3x0_timer.h:245
timer_break_parameter_struct::breakstate
uint16_t breakstate
Definition: gd32f3x0_timer.h:257
TIMER_CHCTL1_CH2COMFEN
#define TIMER_CHCTL1_CH2COMFEN
Definition: gd32f3x0_timer.h:150
TIMER_CHCTL1_CH2COMCEN
#define TIMER_CHCTL1_CH2COMCEN
Definition: gd32f3x0_timer.h:153
timer_channel_dma_request_source_select
void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request)
channel DMA request source selection
Definition: gd32f3x0_timer.c:542
timer_hall_mode_config
void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode)
configure TIMER hall sensor mode
Definition: gd32f3x0_timer.c:1541
TIMER_CFG
#define TIMER_CFG(timerx)
Definition: gd32f3x0_timer.h:51
TIMER_CTL0_DIR
#define TIMER_CTL0_DIR
Definition: gd32f3x0_timer.h:59
TIMER_CHCTL0_CH0MS
#define TIMER_CHCTL0_CH0MS
Definition: gd32f3x0_timer.h:131
TIMER_CHCTL2_CH1EN
#define TIMER_CHCTL2_CH1EN
Definition: gd32f3x0_timer.h:170
TIMER_CHCTL2_CH3P
#define TIMER_CHCTL2_CH3P
Definition: gd32f3x0_timer.h:179
TIMER_CHCTL0_CH0COMFEN
#define TIMER_CHCTL0_CH0COMFEN
Definition: gd32f3x0_timer.h:132
timer_slave_mode_select
void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
select TIMER slave mode
Definition: gd32f3x0_timer.c:1608
TIMER_CTL0_CEN
#define TIMER_CTL0_CEN
Definition: gd32f3x0_timer.h:55
TIMER_CHCTL0_CH1CAPFLT
#define TIMER_CHCTL0_CH1CAPFLT
Definition: gd32f3x0_timer.h:145
TIMER_OCPRE_CLEAR_SOURCE_CLR
#define TIMER_OCPRE_CLEAR_SOURCE_CLR
Definition: gd32f3x0_timer.h:543
timer_channel_control_shadow_config
void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
channel capture/compare control shadow register enable
Definition: gd32f3x0_timer.c:699
TIMER_CTL1_ISO0
#define TIMER_CTL1_ISO0
Definition: gd32f3x0_timer.h:70
TIMER_CHCTL2_CH0NEN
#define TIMER_CHCTL2_CH0NEN
Definition: gd32f3x0_timer.h:168
TIMER_CTL1_ISO2N
#define TIMER_CTL1_ISO2N
Definition: gd32f3x0_timer.h:75
timer_update_event_enable
void timer_update_event_enable(uint32_t timer_periph)
enable the update event
Definition: gd32f3x0_timer.c:164
timer_external_clock_mode1_disable
void timer_external_clock_mode1_disable(uint32_t timer_periph)
disable TIMER the external clock mode1
Definition: gd32f3x0_timer.c:1832
TIMER_CTL1_ISO0N
#define TIMER_CTL1_ISO0N
Definition: gd32f3x0_timer.h:71
TIMER_SMCFG_TRGSEL_CI1FE1
#define TIMER_SMCFG_TRGSEL_CI1FE1
Definition: gd32f3x0_timer.h:517
TIMER_CH2CV
#define TIMER_CH2CV(timerx)
Definition: gd32f3x0_timer.h:45
TIMER_CHCTL2_CH2NP
#define TIMER_CHCTL2_CH2NP
Definition: gd32f3x0_timer.h:177
RCU_TIMER0RST
Definition: gd32f3x0_rcu.h:336
timer_break_config
void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara)
configure TIMER break function
Definition: gd32f3x0_timer.c:621
timer_parameter_struct::prescaler
uint16_t prescaler
Definition: gd32f3x0_timer.h:240
timer_oc_parameter_struct::ocnpolarity
uint16_t ocnpolarity
Definition: gd32f3x0_timer.h:266
TIMER_IC_SELECTION_DIRECTTI
#define TIMER_IC_SELECTION_DIRECTTI
Definition: gd32f3x0_timer.h:499
timer_break_enable
void timer_break_enable(uint32_t timer_periph)
enable TIMER break function
Definition: gd32f3x0_timer.c:638
timer_counter_read
uint32_t timer_counter_read(uint32_t timer_periph)
read TIMER counter value
Definition: gd32f3x0_timer.c:280
TIMER_IC_POLARITY_FALLING
#define TIMER_IC_POLARITY_FALLING
Definition: gd32f3x0_timer.h:495
TIMER_CHCTL0_CH1MS
#define TIMER_CHCTL0_CH1MS
Definition: gd32f3x0_timer.h:136
TIMER_CCHP_OAEN
#define TIMER_CCHP_OAEN
Definition: gd32f3x0_timer.h:219
timer_single_pulse_mode_config
void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode)
configure TIMER single pulse mode
Definition: gd32f3x0_timer.c:309
timer_parameter_struct
Definition: gd32f3x0_timer.h:238
TIMER_OUTSEL_DISABLE
#define TIMER_OUTSEL_DISABLE
Definition: gd32f3x0_timer.h:570
TIMER_CHCTL0_CH1COMFEN
#define TIMER_CHCTL0_CH1COMFEN
Definition: gd32f3x0_timer.h:137
timer_channel_output_config
void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara)
configure TIMER channel output function
Definition: gd32f3x0_timer.c:745
timer_flag_get
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
get TIMER flags
Definition: gd32f3x0_timer.c:462
TIMER_CTL1_ISO2
#define TIMER_CTL1_ISO2
Definition: gd32f3x0_timer.h:74
TIMER_CCSEL_DISABLE
#define TIMER_CCSEL_DISABLE
Definition: gd32f3x0_timer.h:566
TIMER_CTL1_MMC
#define TIMER_CTL1_MMC
Definition: gd32f3x0_timer.h:68
timer_external_trigger_config
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input
Definition: gd32f3x0_timer.c:1649
timer_parameter_struct::period
uint32_t period
Definition: gd32f3x0_timer.h:243
timer_channel_control_shadow_update_config
void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl)
configure TIMER channel control shadow register update control
Definition: gd32f3x0_timer.c:717
TIMER_CHCTL0
#define TIMER_CHCTL0(timerx)
Definition: gd32f3x0_timer.h:36
timer_automatic_output_enable
void timer_automatic_output_enable(uint32_t timer_periph)
enable TIMER output automatic function
Definition: gd32f3x0_timer.c:660
timer_oc_parameter_struct
Definition: gd32f3x0_timer.h:261
timer_break_parameter_struct::protectmode
uint16_t protectmode
Definition: gd32f3x0_timer.h:256
RCU_TIMER15RST
Definition: gd32f3x0_rcu.h:340
TIMER_DMACFG_DMATA
#define TIMER_DMACFG_DMATA
Definition: gd32f3x0_timer.h:223
TIMER_SLAVE_MODE_EXTERNAL0
#define TIMER_SLAVE_MODE_EXTERNAL0
Definition: gd32f3x0_timer.h:540
TIMER_DMAINTEN
#define TIMER_DMAINTEN(timerx)
Definition: gd32f3x0_timer.h:33
TIMER_CHCTL1_CH2CAPFLT
#define TIMER_CHCTL1_CH2CAPFLT
Definition: gd32f3x0_timer.h:161
timer_ic_parameter_struct::icfilter
uint16_t icfilter
Definition: gd32f3x0_timer.h:277
timer_break_disable
void timer_break_disable(uint32_t timer_periph)
disable TIMER break function
Definition: gd32f3x0_timer.c:649
RCU_TIMER16RST
Definition: gd32f3x0_rcu.h:341
timer_oc_parameter_struct::outputnstate
uint16_t outputnstate
Definition: gd32f3x0_timer.h:264
TIMER_CFG_OUTSEL
#define TIMER_CFG_OUTSEL
Definition: gd32f3x0_timer.h:233
timer_output_value_selection_config
void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel)
configure TIMER output value selection
Definition: gd32f3x0_timer.c:1881
timer_ic_parameter_struct
Definition: gd32f3x0_timer.h:272
TIMER_UPDATECTL_CCUTRI
#define TIMER_UPDATECTL_CCUTRI
Definition: gd32f3x0_timer.h:491
timer_parameter_struct::alignedmode
uint16_t alignedmode
Definition: gd32f3x0_timer.h:241
timer_parameter_struct::counterdirection
uint16_t counterdirection
Definition: gd32f3x0_timer.h:242
RCU_TIMER2RST
Definition: gd32f3x0_rcu.h:345
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_crc.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_crc.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_crc.h"
13
20 void crc_deinit(void)
21 {
22 CRC_IDATA = (uint32_t)0xFFFFFFFFU;
23 CRC_DATA = (uint32_t)0xFFFFFFFFU;
24 CRC_FDATA = (uint32_t)0x00000000U;
25 CRC_POLY = (uint32_t)0x04C11DB7U;
26 CRC_CTL = CRC_CTL_RST;
27 }
28
35 void crc_reverse_output_data_enable(void)
36 {
37 CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
38 CRC_CTL |= (uint32_t)CRC_CTL_REV_O;
39 }
40
47 void crc_reverse_output_data_disable(void)
48 {
49 CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
50 }
51
58 void crc_data_register_reset(void)
59 {
60 CRC_CTL |= (uint32_t)CRC_CTL_RST;
61 }
62
69 uint32_t crc_data_register_read(void)
70 {
71 uint32_t data;
72 data = CRC_DATA;
73 return (data);
74 }
75
82 uint8_t crc_free_data_register_read(void)
83 {
84 uint8_t fdata;
85 fdata = (uint8_t)CRC_FDATA;
86 return (fdata);
87 }
88
95 void crc_free_data_register_write(uint8_t free_data)
96 {
97 CRC_FDATA = (uint32_t)free_data;
98 }
99
106 void crc_init_data_register_write(uint32_t init_data)
107 {
108 CRC_IDATA = (uint32_t)init_data;
109 }
110
121 void crc_input_data_reverse_config(uint32_t data_reverse)
122 {
123 CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I);
124 CRC_CTL |= (uint32_t)data_reverse;
125 }
126
137 void crc_polynomial_size_set(uint32_t poly_size)
138 {
139 CRC_CTL &= (uint32_t)(~(CRC_CTL_PS));
140 CRC_CTL |= (uint32_t)poly_size;
141 }
142
149 void crc_polynomial_set(uint32_t poly)
150 {
151 CRC_POLY &= (uint32_t)(~CRC_POLY_POLY);
152 CRC_POLY = poly;
153 }
154
161 uint32_t crc_single_data_calculate(uint32_t sdata)
162 {
163 CRC_DATA = sdata;
164 return(CRC_DATA);
165 }
166
174 uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
175 {
176 uint32_t index;
177 for(index = 0U; index < size; index++){
178 CRC_DATA = array[index];
179 }
180 return (CRC_DATA);
181 }
crc_polynomial_set
void crc_polynomial_set(uint32_t poly)
configure the CRC polynomial value function
Definition: gd32f3x0_crc.c:149
CRC_IDATA
#define CRC_IDATA
Definition: gd32f3x0_crc.h:24
crc_reverse_output_data_enable
void crc_reverse_output_data_enable(void)
enable the reverse operation of output data
Definition: gd32f3x0_crc.c:35
CRC_DATA
#define CRC_DATA
Definition: gd32f3x0_crc.h:21
crc_deinit
void crc_deinit(void)
deinit CRC calculation unit
Definition: gd32f3x0_crc.c:20
CRC_FDATA
#define CRC_FDATA
Definition: gd32f3x0_crc.h:22
CRC_CTL_REV_I
#define CRC_CTL_REV_I
Definition: gd32f3x0_crc.h:37
crc_free_data_register_write
void crc_free_data_register_write(uint8_t free_data)
write the free data register
Definition: gd32f3x0_crc.c:95
crc_block_data_calculate
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
CRC calculate a 32-bit data array.
Definition: gd32f3x0_crc.c:174
CRC_POLY
#define CRC_POLY
Definition: gd32f3x0_crc.h:25
crc_init_data_register_write
void crc_init_data_register_write(uint32_t init_data)
write the initializaiton data register
Definition: gd32f3x0_crc.c:106
crc_polynomial_size_set
void crc_polynomial_size_set(uint32_t poly_size)
configure the CRC size of polynomial function
Definition: gd32f3x0_crc.c:137
CRC_CTL_RST
#define CRC_CTL_RST
Definition: gd32f3x0_crc.h:35
crc_input_data_reverse_config
void crc_input_data_reverse_config(uint32_t data_reverse)
configure the CRC input data function
Definition: gd32f3x0_crc.c:121
crc_free_data_register_read
uint8_t crc_free_data_register_read(void)
read the free data register
Definition: gd32f3x0_crc.c:82
CRC_CTL_REV_O
#define CRC_CTL_REV_O
Definition: gd32f3x0_crc.h:38
crc_single_data_calculate
uint32_t crc_single_data_calculate(uint32_t sdata)
CRC calculate a 32-bit data.
Definition: gd32f3x0_crc.c:161
crc_reverse_output_data_disable
void crc_reverse_output_data_disable(void)
disable the reverse operation of output data
Definition: gd32f3x0_crc.c:47
CRC_POLY_POLY
#define CRC_POLY_POLY
Definition: gd32f3x0_crc.h:44
gd32f3x0_crc.h
definitions for the CRC
crc_data_register_reset
void crc_data_register_reset(void)
reset data register to the value of initializaiton data register
Definition: gd32f3x0_crc.c:58
CRC_CTL
#define CRC_CTL
Definition: gd32f3x0_crc.h:23
CRC_CTL_PS
#define CRC_CTL_PS
Definition: gd32f3x0_crc.h:36
crc_data_register_read
uint32_t crc_data_register_read(void)
read the data register
Definition: gd32f3x0_crc.c:69
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_wwdgt.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_wwdgt.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_wwdgt.h"
13 #include "gd32f3x0_rcu.h"
14
21 void wwdgt_deinit(void)
22 {
23 rcu_periph_reset_enable(RCU_WWDGTRST);
24 rcu_periph_reset_disable(RCU_WWDGTRST);
25 }
26
33 void wwdgt_counter_update(uint16_t counter_value)
34 {
35 uint32_t reg = 0x0U;
36
37 reg = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT);
38 reg |= (uint32_t)(CTL_CNT(counter_value));
39
40 WWDGT_CTL = (uint32_t)reg;
41 }
42
49 void wwdgt_enable(void)
50 {
51 WWDGT_CTL |= WWDGT_CTL_WDGTEN;
52 }
53
66 void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
67 {
68 uint32_t reg_cfg = 0x0U, reg_ctl = 0x0U;
69
70 /* clear WIN and PSC bits, clear CNT bit */
71 reg_cfg = WWDGT_CFG &(~((uint32_t)WWDGT_CFG_WIN|(uint32_t)WWDGT_CFG_PSC));
72 reg_ctl = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT);
73
74 /* configure WIN and PSC bits, configure CNT bit */
75 reg_cfg |= (uint32_t)(CFG_WIN(window));
76 reg_cfg |= (uint32_t)(prescaler);
77 reg_ctl |= (uint32_t)(CTL_CNT(counter));
78
79 WWDGT_CFG = (uint32_t)reg_cfg;
80 WWDGT_CTL = (uint32_t)reg_ctl;
81 }
82
89 void wwdgt_interrupt_enable(void)
90 {
91 WWDGT_CFG |= WWDGT_CFG_EWIE;
92 }
93
100 FlagStatus wwdgt_flag_get(void)
101 {
102 if(WWDGT_STAT & WWDGT_STAT_EWIF){
103 return SET;
104 }
105 return RESET;
106 }
107
114 void wwdgt_flag_clear(void)
115 {
116 WWDGT_STAT &= (uint32_t)(~(uint32_t)WWDGT_STAT_EWIF);
117 }
WWDGT_CTL_WDGTEN
#define WWDGT_CTL_WDGTEN
Definition: gd32f3x0_wwdgt.h:28
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
wwdgt_counter_update
void wwdgt_counter_update(uint16_t counter_value)
configure the window watchdog timer counter value
Definition: gd32f3x0_wwdgt.c:33
CTL_CNT
#define CTL_CNT(regval)
Definition: gd32f3x0_wwdgt.h:40
gd32f3x0_rcu.h
definitions for the RCU
WWDGT_CFG_WIN
#define WWDGT_CFG_WIN
Definition: gd32f3x0_wwdgt.h:31
WWDGT_STAT_EWIF
#define WWDGT_STAT_EWIF
Definition: gd32f3x0_wwdgt.h:36
wwdgt_flag_get
FlagStatus wwdgt_flag_get(void)
check early wakeup interrupt state of WWDGT
Definition: gd32f3x0_wwdgt.c:100
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
WWDGT_CFG
#define WWDGT_CFG
Definition: gd32f3x0_wwdgt.h:22
WWDGT_CTL
#define WWDGT_CTL
Definition: gd32f3x0_wwdgt.h:21
CFG_WIN
#define CFG_WIN(regval)
Definition: gd32f3x0_wwdgt.h:43
WWDGT_CFG_EWIE
#define WWDGT_CFG_EWIE
Definition: gd32f3x0_wwdgt.h:33
wwdgt_interrupt_enable
void wwdgt_interrupt_enable(void)
enable early wakeup interrupt of WWDGT
Definition: gd32f3x0_wwdgt.c:89
WWDGT_CTL_CNT
#define WWDGT_CTL_CNT
Definition: gd32f3x0_wwdgt.h:27
WWDGT_STAT
#define WWDGT_STAT
Definition: gd32f3x0_wwdgt.h:23
RCU_WWDGTRST
Definition: gd32f3x0_rcu.h:347
WWDGT_CFG_PSC
#define WWDGT_CFG_PSC
Definition: gd32f3x0_wwdgt.h:32
wwdgt_enable
void wwdgt_enable(void)
start the window watchdog timer counter
Definition: gd32f3x0_wwdgt.c:49
wwdgt_config
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
configure counter value, window value, and prescaler divider value
Definition: gd32f3x0_wwdgt.c:66
gd32f3x0_wwdgt.h
definitions for the WWDGT
wwdgt_deinit
void wwdgt_deinit(void)
reset the window watchdog timer configuration
Definition: gd32f3x0_wwdgt.c:21
wwdgt_flag_clear
void wwdgt_flag_clear(void)
clear early wakeup interrupt state of WWDGT
Definition: gd32f3x0_wwdgt.c:114
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_fmc.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_fmc.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_FMC_H
13 #define GD32F3X0_FMC_H
14
15 #include "gd32f3x0.h"
16
17 /* FMC and option byte definition */
18 #define FMC FMC_BASE
19 #define OB OB_BASE
21 /* registers definitions */
22 #define FMC_WS REG32((FMC) + 0x00U)
23 #define FMC_KEY REG32((FMC) + 0x04U)
24 #define FMC_OBKEY REG32((FMC) + 0x08U)
25 #define FMC_STAT REG32((FMC) + 0x0CU)
26 #define FMC_CTL REG32((FMC) + 0x10U)
27 #define FMC_ADDR REG32((FMC) + 0x14U)
28 #define FMC_OBSTAT REG32((FMC) + 0x1CU)
29 #define FMC_WP REG32((FMC) + 0x20U)
30 #define FMC_WSEN REG32((FMC) + 0xFCU)
31 #define FMC_PID REG32((FMC) + 0x100U)
33 #define OB_SPC REG16((OB) + 0x00U)
34 #define OB_USER REG16((OB) + 0x02U)
35 #define OB_WP0 REG16((OB) + 0x08U)
36 #define OB_WP1 REG16((OB) + 0x0AU)
38 /* bits definitions */
39 /* FMC_WS */
40 #define FMC_WS_WSCNT BITS(0,2)
42 /* FMC_KEY */
43 #define FMC_KEY_KEY BITS(0,31)
45 /* FMC_OBKEY */
46 #define FMC_OBKEY_OBKEY BITS(0,31)
48 /* FMC_STAT */
49 #define FMC_STAT_BUSY BIT(0)
50 #define FMC_STAT_PGERR BIT(2)
51 #define FMC_STAT_WPERR BIT(4)
52 #define FMC_STAT_ENDF BIT(5)
54 /* FMC_CTL */
55 #define FMC_CTL_PG BIT(0)
56 #define FMC_CTL_PER BIT(1)
57 #define FMC_CTL_MER BIT(2)
58 #define FMC_CTL_OBPG BIT(4)
59 #define FMC_CTL_OBER BIT(5)
60 #define FMC_CTL_START BIT(6)
61 #define FMC_CTL_LK BIT(7)
62 #define FMC_CTL_OBWEN BIT(9)
63 #define FMC_CTL_ERRIE BIT(10)
64 #define FMC_CTL_ENDIE BIT(12)
65 #define FMC_CTL_OBRLD BIT(13)
67 /* FMC_ADDR */
68 #define FMC_ADDR_ADDR BITS(0,31)
70 /* FMC_OBSTAT */
71 #define FMC_OBSTAT_OBERR BIT(0)
72 #define FMC_OBSTAT_PLVL_BIT0 BIT(1)
73 #define FMC_OBSTAT_PLVL_BIT1 BIT(2)
74 #define FMC_OBSTAT_USER BITS(8,15)
75 #define FMC_OBSTAT_DATA BITS(16,31)
77 /* FMC_WSEN */
78 #define FMC_WSEN_WSEN BIT(0)
79 #define FMC_WSEN_BPEN BIT(1)
81 /* FMC_PID */
82 #define FMC_PID_PID BITS(0,31)
84 /* constants definitions */
85 /* fmc state */
86 typedef enum
87 {
88 FMC_READY,
89 FMC_BUSY,
90 FMC_PGERR,
91 FMC_WPERR,
92 FMC_TOERR,
93 FMC_OB_HSPC
94 }fmc_state_enum;
95
96 /* unlock key */
97 #define UNLOCK_KEY0 ((uint32_t)0x45670123U)
98 #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU)
100 /* wait state counter value */
101 #define WS_WSCNT_0 ((uint8_t)0x00U)
102 #define WS_WSCNT_1 ((uint8_t)0x01U)
103 #define WS_WSCNT_2 ((uint8_t)0x02U)
105 /* read protect configure */
106 #define FMC_NSPC ((uint8_t)0xA5U)
107 #define FMC_LSPC ((uint8_t)0xBBU)
108 #define FMC_HSPC ((uint8_t)0xCCU)
110 /* option byte write protection */
111 #define OB_LWP ((uint32_t)0x000000FFU)
112 #define OB_HWP ((uint32_t)0x0000FF00U)
114 /* option byte software/hardware free watchdog timer */
115 #define OBUSER_NWDG_HW(regval) (BIT(0) & ((uint32_t)(regval) << 0))
116 #define OB_FWDGT_HW OBUSER_NWDG_HW(0)
117 #define OB_FWDGT_SW OBUSER_NWDG_HW(1)
119 /* option byte reset or not entering deep sleep mode */
120 #define OBUSER_NRST_DPSLP(regval) (BIT(1) & ((uint32_t)(regval) << 1))
121 #define OB_DEEPSLEEP_RST OBUSER_NRST_DPSLP(0)
122 #define OB_DEEPSLEEP_NRST OBUSER_NRST_DPSLP(1)
124 /* option byte reset or not entering standby mode */
125 #define OBUSER_NRST_STDBY(regval) (BIT(2) & ((uint32_t)(regval) << 2))
126 #define OB_STDBY_RST OBUSER_NRST_STDBY(0)
127 #define OB_STDBY_NRST OBUSER_NRST_STDBY(1)
129 /* option byte OB_BOOT1_n set */
130 #define OBUSER_BOOT1_N(regval) (BIT(4) & ((uint32_t)(regval) << 4))
131 #define OB_BOOT1_SET_1 OBUSER_BOOT1_N(0)
132 #define OB_BOOT1_SET_0 OBUSER_BOOT1_N(1)
134 /* option byte VDDA monitor enable/disable */
135 #define OBUSER_VDDA_VISOR(regval) (BIT(5) & ((uint32_t)(regval) << 5))
136 #define OB_VDDA_DISABLE OBUSER_VDDA_VISOR(0)
137 #define OB_VDDA_ENABLE OBUSER_VDDA_VISOR(1)
139 /* option byte SRAM parity enable/disable */
140 #define OBUSER_SRAM_PARITY(regval) (BIT(6) & ((uint32_t)(regval) << 6))
141 #define OB_SRAM_PARITY_ENABLE OBUSER_SRAM_PARITY(0)
142 #define OB_SRAM_PARITY_DISABLE OBUSER_SRAM_PARITY(1)
144 /* option byte security protection level in FMC_OBSTAT register */
145 #define OB_OBSTAT_PLEVEL_NO ((uint32_t)0x00000000U)
146 #define OB_OBSTAT_PLEVEL_LOW ((uint32_t)0x00000002U)
147 #define OB_OBSTAT_PLEVEL_HIGH ((uint32_t)0x00000006U)
149 /* option byte user mask */
150 #define OB_USER_MASK ((uint8_t)0x88U)
152 /* option byte data address */
153 #define OB_DATA_ADDR0 ((uint32_t)0x1FFFF804U)
154 #define OB_DATA_ADDR1 ((uint32_t)0x1FFFF806U)
156 /* FMC flags */
157 #define FMC_FLAG_BUSY FMC_STAT_BUSY
158 #define FMC_FLAG_PGERR FMC_STAT_PGERR
159 #define FMC_FLAG_WPERR FMC_STAT_WPERR
160 #define FMC_FLAG_END FMC_STAT_ENDF
162 /* FMC interrupt enable */
163 #define FMC_INTEN_END FMC_CTL_ENDIE
164 #define FMC_INTEN_ERR FMC_CTL_ERRIE
166 /* FMC time out */
167 #define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U)
169 /* function declarations */
170 /* FMC main memory programming functions */
171 /* unlock the main FMC operation */
172 void fmc_unlock(void);
173 /* lock the main FMC operation */
174 void fmc_lock(void);
175 /* set the wait state counter value */
176 void fmc_wscnt_set(uint8_t wscnt);
177 /* fmc wait state enable */
178 void fmc_wait_state_enable(void);
179 /* fmc wait state disable */
180 void fmc_wait_state_disable(void);
181 /* FMC erase page */
182 fmc_state_enum fmc_page_erase(uint32_t page_address);
183 /* FMC erase whole chip */
184 fmc_state_enum fmc_mass_erase(void);
185 /* FMC program a word at the corresponding address */
186 fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
187 /* FMC program a half word at the corresponding address */
188 fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
189 /* FMC program a word at the corresponding address without erasing */
190 fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data);
191
192 /* FMC option bytes programming functions */
193 /* unlock the option byte operation */
194 void ob_unlock(void);
195 /* lock the option byte operation */
196 void ob_lock(void);
197 /* reload the option byte and generate a system reset */
198 void ob_reset(void);
199 /* erase option byte */
200 fmc_state_enum ob_erase(void);
201 /* enable option byte write protection (OB_WP) */
202 fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
203 /* configure read out protect */
204 fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
205 /* write the FMC option byte user */
206 fmc_state_enum ob_user_write(uint8_t ob_user);
207 /* write the FMC option byte data */
208 fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
209 /* get the FMC option byte OB_USER */
210 uint8_t ob_user_get(void);
211 /* get the FMC option byte OB_DATA */
212 uint16_t ob_data_get(void);
213 /* get the FMC option byte write protection */
214 uint16_t ob_write_protection_get(void);
215 /* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */
216 uint32_t ob_obstat_plevel_get(void);
217
218 /* FMC interrupts and flags management functions */
219 /* enable FMC interrupt */
220 void fmc_interrupt_enable(uint32_t interrupt);
221 /* disable FMC interrupt */
222 void fmc_interrupt_disable(uint32_t interrupt);
223 /* get flag set or reset */
224 FlagStatus fmc_flag_get(uint32_t flag);
225 /* clear the FMC pending flag */
226 void fmc_flag_clear(uint32_t flag);
227 /* return the FMC state */
228 fmc_state_enum fmc_state_get(void);
229 /* check FMC ready or not */
230 fmc_state_enum fmc_ready_wait(uint32_t timeout);
231
232 #endif /* GD32F3X0_FMC_H */
fmc_wait_state_enable
void fmc_wait_state_enable(void)
fmc wait state enable
Definition: gd32f3x0_fmc.c:70
ob_security_protection_config
fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
configure security protection
Definition: gd32f3x0_fmc.c:390
ob_data_program
fmc_state_enum ob_data_program(uint32_t address, uint8_t data)
program the FMC data option byte
Definition: gd32f3x0_fmc.c:484
ob_lock
void ob_lock(void)
lock the option byte operation it is better to used in pairs with ob_unlock after an operation ...
Definition: gd32f3x0_fmc.c:263
fmc_mass_erase
fmc_state_enum fmc_mass_erase(void)
erase whole chip
Definition: gd32f3x0_fmc.c:133
fmc_word_program
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
program a word at the corresponding address
Definition: gd32f3x0_fmc.c:160
fmc_unlock
void fmc_unlock(void)
unlock the main FMC operation it is better to used in pairs with fmc_lock
Definition: gd32f3x0_fmc.c:23
ob_write_protection_enable
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
enable option byte write protection (OB_WP)
Definition: gd32f3x0_fmc.c:346
fmc_flag_clear
void fmc_flag_clear(uint32_t flag)
clear the FMC pending flag by writing 1
Definition: gd32f3x0_fmc.c:606
FMC_READY
Definition: gd32f3x0_fmc.h:88
ob_data_get
uint16_t ob_data_get(void)
get OB_DATA in register FMC_OBSTAT
Definition: gd32f3x0_fmc.c:522
fmc_lock
void fmc_lock(void)
lock the main FMC operation it is better to used in pairs with fmc_unlock after an operation ...
Definition: gd32f3x0_fmc.c:39
ob_obstat_plevel_get
uint32_t ob_obstat_plevel_get(void)
get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register ...
Definition: gd32f3x0_fmc.c:544
fmc_flag_get
FlagStatus fmc_flag_get(uint32_t flag)
get flag set or reset
Definition: gd32f3x0_fmc.c:586
ob_write_protection_get
uint16_t ob_write_protection_get(void)
get the FMC option byte write protection (OB_WP) in register FMC_WP
Definition: gd32f3x0_fmc.c:533
FMC_OB_HSPC
Definition: gd32f3x0_fmc.h:93
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
fmc_state_get
fmc_state_enum fmc_state_get(void)
get the FMC state
Definition: gd32f3x0_fmc.c:618
ob_user_get
uint8_t ob_user_get(void)
get OB_USER in register FMC_OBSTAT
Definition: gd32f3x0_fmc.c:511
ob_unlock
void ob_unlock(void)
unlock the option byte operation it is better to used in pairs with ob_lock
Definition: gd32f3x0_fmc.c:247
fmc_wait_state_disable
void fmc_wait_state_disable(void)
fmc wait state disable
Definition: gd32f3x0_fmc.c:88
ob_user_write
fmc_state_enum ob_user_write(uint8_t ob_user)
program the FMC user option byte
Definition: gd32f3x0_fmc.c:453
FMC_PGERR
Definition: gd32f3x0_fmc.h:90
ob_erase
fmc_state_enum ob_erase(void)
erase the option byte programmer must ensure FMC & option byte are both unlocked before calling this ...
Definition: gd32f3x0_fmc.c:288
ob_reset
void ob_reset(void)
reload the option byte and generate a system reset
Definition: gd32f3x0_fmc.c:275
fmc_interrupt_disable
void fmc_interrupt_disable(uint32_t interrupt)
disable FMC interrupt
Definition: gd32f3x0_fmc.c:571
fmc_interrupt_enable
void fmc_interrupt_enable(uint32_t interrupt)
enable FMC interrupt
Definition: gd32f3x0_fmc.c:558
fmc_page_erase
fmc_state_enum fmc_page_erase(uint32_t page_address)
erase page
Definition: gd32f3x0_fmc.c:106
fmc_wscnt_set
void fmc_wscnt_set(uint8_t wscnt)
set the wait state counter value
Definition: gd32f3x0_fmc.c:54
fmc_word_reprogram
fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data)
program a word at the corresponding address without erasing
Definition: gd32f3x0_fmc.c:216
FMC_WPERR
Definition: gd32f3x0_fmc.h:91
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
fmc_halfword_program
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
program a half word at the corresponding address
Definition: gd32f3x0_fmc.c:188
FMC_BUSY
Definition: gd32f3x0_fmc.h:89
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_core.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
usbh_core.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef USBH_CORE_H
13 #define USBH_CORE_H
14
15 #include "usbh_conf.h"
16 #include "usb_std.h"
17 #include "usb_core.h"
18
19 #define MSC_CLASS 0x08
20 #define HID_CLASS 0x03
21 #define MSC_PROTOCOL 0x50
22 #define CBI_PROTOCOL 0x01
24 #define USBH_DEVICE_ADDRESS_DEFAULT 0U
25 #define USBH_DEVICE_ADDRESS 1U
26 #define USBH_MAX_ERROR_COUNT 2U
28 #define HOST_USER_SELECT_CONFIGURATION 1U
29 #define HOST_USER_CLASS_ACTIVE 2U
30 #define HOST_USER_CLASS_SELECTED 3U
31 #define HOST_USER_CONNECTION 4U
32 #define HOST_USER_DISCONNECTION 5U
33 #define HOST_USER_UNRECOVERED_ERROR 6U
35 #define MAX_USBH_STATE_STACK_DEEP 4
36 #define MAX_USBH_STATE_TABLE_NUM 10U
38 #define HOST_FSM_ID 0U
39 #define ENUM_FSM_ID 1U
40 #define CMD_FSM_ID 2U
41 #define CTRL_FSM_ID 3U
42 #define CLASS_REQ_FSM_ID 4U
43 #define CLASS_FSM_ID 5U
45 #define UP_STATE 100U
46 #define GO_TO_UP_STATE_EVENT 100U
48 #define HOST_HANDLE_TABLE_SIZE 9U
50 /* the enum of host state */
51 typedef enum
52 {
53 HOST_IDLE = 0, /* the host idle state definition */
54 HOST_DEV_ATTACHED, /* the host device attached state definition */
55 HOST_DEV_DETACHED, /* the host device detached state definition */
56 HOST_DETECT_DEV_SPEED, /* the host detect device speed state definition */
57 HOST_ENUMERATION, /* the host enumeration state definition */
58 HOST_CLASS_REQUEST, /* the host class request state definition */
59 HOST_CLASS, /* the host class state definition */
60 HOST_USER_INPUT, /* the host user input state definition */
61 HOST_SUSPENDED, /* the host suspended state definition */
62 HOST_ERROR /* the host error state definition */
63 }host_state_enum;
64
65 /* the enum of host event */
66 typedef enum
67 {
68 HOST_EVENT_ATTACHED = 0, /* the host attached event */
69 HOST_EVENT_ENUM, /* the host enum event */
70 HOST_EVENT_USER_INPUT, /* the host user input event */
71 HOST_EVENT_CLASS_REQ, /* the host class request event */
72 HOST_EVENT_CLASS, /* the host class event */
73 HOST_EVENT_ERROR, /* the host error event */
74 HOST_EVENT_DEV_DETACHED, /* the host device detached event */
75 HOST_EVENT_IDLE /* the host idle event */
76 }host_event_enum;
77
78 /* the enum of enum state */
79 typedef enum
80 {
81 ENUM_IDLE = 0, /* the enum idle state definition */
82 ENUM_SET_ADDR, /* the enum set address state definition */
83 ENUM_GET_FULL_DEV_DESC, /* the enum get full device descripter state definition */
84 ENUM_GET_CFG_DESC, /* the enum get configuration descripter state definition */
85 ENUM_GET_FULL_CFG_DESC, /* the enum get full configuration descripter state definition */
86 ENUM_GET_MFC_STRING_DESC, /* the enum get MFC string descripter state definition */
87 ENUM_GET_PRODUCT_STRING_DESC, /* the enum get product string descripter state definition */
88 ENUM_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string descripter state definition */
89 ENUM_SET_CONFIGURATION, /* the enum set congiguration state definition */
90 ENUM_DEV_CONFIGURED /* the enum device configuration state definition */
91 }enum_state_enum;
92
93 /* the enum of ctrl state */
94 typedef enum
95 {
96 CTRL_IDLE = 0, /* the ctrl idle state definition */
97 CTRL_SETUP, /* the ctrl setup state definition */
98 CTRL_DATA, /* the ctrl data state definition */
99 CTRL_STATUS, /* the ctrl status state definition */
100 CTRL_ERROR, /* the ctrl error state definition */
101 CTRL_STALLED, /* the ctrl stalled state definition */
102 CTRL_COMPLETE /* the ctrl complete state definition */
103 }ctrl_state_enum;
104
105 /* the enum of host status */
106 typedef enum
107 {
108 USBH_OK = 0, /* the usbh ok status definition */
109 USBH_BUSY, /* the usbh busy status definition */
110 USBH_FAIL, /* the usbh fail status definition */
111 USBH_NOT_SUPPORTED, /* the usbh not supported status definition */
112 USBH_UNRECOVERED_ERROR, /* the usbh unrecovered error status definition */
113 USBH_SPEED_UNKNOWN_ERROR, /* the usbh speed unknown error status definition */
114 USBH_APPLY_DEINIT /* the usbh apply deinit status definition */
115 }usbh_status_enum;
116
117 /* the state of user action */
118 typedef enum
119 {
120 USBH_USER_NO_RESP = 0, /* the user no response */
121 USBH_USER_RESP_OK = 1, /* the user response ok */
122 }usbh_user_status_enum;
123
124 /* control transfer information */
125 typedef struct
126 {
127 uint8_t hc_in_num; /* the host in channel number */
128 uint8_t hc_out_num; /* the host out channel number */
129 uint8_t ep0_size; /* the endpoint 0 max packet size */
130 uint8_t error_count; /* the error count */
131 uint16_t length; /* the length */
132 uint16_t timer; /* the timer */
133 uint8_t *buff; /* the buffer */
134 usb_setup_union setup; /* the setup packet */
135 }usbh_ctrl_struct;
136
137 /* device property */
138 typedef struct
139 {
140 uint8_t address; /* the device address */
141 uint8_t speed; /* the device speed */
142 usb_descriptor_device_struct dev_desc; /* the device descripter */
143 usb_descriptor_configuration_struct cfg_desc; /* the configuration descripter */
144 usb_descriptor_interface_struct itf_desc[USBH_MAX_INTERFACES_NUM]; /* the interface descripter */
145 usb_descriptor_endpoint_struct ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]; /* the endpoint descripter */
146 }usbh_device_struct;
147
148 /* user callbacks */
149 typedef struct
150 {
151 void (*init) (void); /* the user callback init function */
152 void (*deinit) (void); /* the user callback deinit function */
153 void (*device_connected) (void); /* the user callback device connected function */
154 void (*device_reset) (void); /* the user callback device reset function */
155 void (*device_disconnected) (void); /* the user callback device disconnected function */
156 void (*over_current_detected) (void); /* the user callback over current detected function */
157 void (*device_speed_detected) (uint8_t device_speed); /* the user callback device speed detected function */
158 void (*device_desc_available) (void *devDesc); /* the user callback device descrpiter available function */
159 void (*device_address_set) (void); /* the user callback set device address function */
160
161 void (*configuration_desc_available)(usb_descriptor_configuration_struct *cfg_desc,
162 usb_descriptor_interface_struct *itf_desc,
163 usb_descriptor_endpoint_struct *ep_desc);
164 /* the configuration descripter available function */
165
166 void (*manufacturer_string) (void *mfc_string); /* the user callback manufacturer string function */
167 void (*product_string) (void *prod_string); /* the user callback product string function */
168 void (*serial_num_string) (void *serial_string); /* the user callback serial number string function */
169 void (*enumeration_finish) (void); /* the user callback enumeration finish function */
170 usbh_user_status_enum (*user_input) (void); /* the user callback user input function */
171 int (*user_application) (usb_core_handle_struct *pudev, uint8_t id);
172 /* the user callback user appliction function */
173 void (*device_not_supported) (void); /* the user callback device not supported function */
174 void (*unrecovered_error) (void); /* the user callback unrecovered error function */
175 }usbh_user_callback_struct;
176
177 /* the backup state struct */
178 typedef struct
179 {
180 host_state_enum host_backup_state; /* the host backup state */
181 enum_state_enum enum_backup_state; /* the enum backup state */
182 ctrl_state_enum ctrl_backup_state; /* the ctrl backup state */
183 uint8_t class_req_backup_state;/* the class request backup state */
184 uint8_t class_backup_state; /* the class backup state */
185 } backup_state_struct;
186
187 /* host information */
188 typedef struct
189 {
190 backup_state_struct usbh_backup_state; /* the usbh backup state variable */
191 usbh_ctrl_struct control; /* the control struct variable */
192 usbh_device_struct device; /* the device struct variable */
193 usbh_user_callback_struct *usr_cb; /* the user callback function */
194 usbh_status_enum (*class_init) (usb_core_handle_struct *pudev, void *phost); /* the class init function */
195 void (*class_deinit) (usb_core_handle_struct *pudev, void *phost); /* the class deinit function */
196 }usbh_host_struct;
197
198 /* the action function definition */
199 typedef usbh_status_enum (*ACT_FUN) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void* pustate);
200
201 /* the state table struct */
202 typedef struct
203 {
204 uint8_t cur_state; /* the current state */
205 uint8_t cur_event; /* the current event */
206 uint8_t next_state; /* the next state */
207 ACT_FUN event_action_fun; /* the event action function entry */
208 } state_table_struct;
209
210 /* the state stack struct */
211 typedef struct
212 {
213 uint8_t state; /* the state in state stack */
214 state_table_struct* table; /* the table in state stack */
215 uint8_t table_size; /* the table size in state stack */
216 } usbh_state_stack_struct;
217
218 /* the state regist table struct */
219 typedef struct
220 {
221 uint8_t id; /* the id of the state table */
222 state_table_struct* table; /* the table entry to regist */
223 uint8_t table_size; /* the table size to regist */
224 } usbh_state_regist_table_struct;
225
226 /* the state handle struct */
227 typedef struct
228 {
229 uint8_t usbh_current_state; /* current state */
230 uint8_t usbh_current_state_table_size; /* current state table size */
231 state_table_struct* usbh_current_state_table; /* current state table */
232
233 usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]; /* the stack of state table */
234 int8_t usbh_current_state_stack_top; /* the current state top */
235
236 usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]; /* the array of regist state table */
237 uint8_t usbh_regist_state_table_num; /* the number of regist state table */
238 } usbh_state_handle_struct;
239
240 /* function declarations */
241 /* the host core driver function */
242 usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
243 /* initialize the host portion of the driver */
244 uint32_t hcd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id);
245 /* check if the device is connected */
246 uint32_t hcd_is_device_connected (usb_core_handle_struct *pudev);
247 /* this function returns the last URBstate */
248 urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num);
249 /* this function returns the last URBstate */
250 uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num);
251 /* de-initialize host */
252 usbh_status_enum usbh_deinit (usb_core_handle_struct *pudev,
253 usbh_host_struct *puhost,
254 usbh_state_handle_struct* pustate);
255
256 /* the state core driver function */
257 /* state core driver init */
258 void scd_init (usbh_state_handle_struct* pustate);
259 /* state core driver table regist */
260 void scd_table_regist (usbh_state_handle_struct* pustate,
261 state_table_struct* pstate_table,
262 uint8_t table_id,
263 uint8_t current_table_size);
264 /* state core driver begin */
265 void scd_begin (usbh_state_handle_struct* pustate, uint8_t table_id);
266 /* state core driver move state */
267 void scd_state_move (usbh_state_handle_struct* pustate, uint8_t state);
268 /* state core driver event handle */
269 usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev,
270 usbh_host_struct *puhost,
271 usbh_state_handle_struct* pustate,
272 uint8_t event,
273 uint8_t state);
274 /* state core driver table push */
275 void scd_table_push (usbh_state_handle_struct* pustate);
276 /* state core driver table pop */
277 void scd_table_pop (usbh_state_handle_struct* pustate);
278 /* the function is only used to state move */
279 usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
280 /* the function to the up state */
281 usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
282
283 #endif /* USBH_CORE_H */
ENUM_DEV_CONFIGURED
Definition: usbh_core.h:90
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
HOST_EVENT_IDLE
Definition: usbh_core.h:75
MAX_USBH_STATE_TABLE_NUM
#define MAX_USBH_STATE_TABLE_NUM
Definition: usbh_core.h:36
goto_up_state_fun
usbh_status_enum goto_up_state_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state
Definition: usbh_core.c:705
usbh_ctrl_struct
Definition: usbh_core.h:125
hcd_urb_state_get
urb_state_enum hcd_urb_state_get(usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate
Definition: usbh_core.c:429
usbh_deinit
usbh_status_enum usbh_deinit(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
de-initialize host
Definition: usbh_core.c:453
usbh_user_status_enum
usbh_user_status_enum
Definition: usbh_core.h:118
usbh_state_handle_struct
Definition: usbh_core.h:227
HOST_EVENT_CLASS_REQ
Definition: usbh_core.h:71
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:213
scd_init
void scd_init(usbh_state_handle_struct *pustate)
state core driver init
Definition: usbh_core.c:484
HOST_EVENT_CLASS
Definition: usbh_core.h:72
backup_state_struct::ctrl_backup_state
ctrl_state_enum ctrl_backup_state
Definition: usbh_core.h:182
state_table_struct::event_action_fun
ACT_FUN event_action_fun
Definition: usbh_core.h:207
CTRL_IDLE
Definition: usbh_core.h:96
urb_state_enum
urb_state_enum
Definition: usb_core.h:48
ENUM_IDLE
Definition: usbh_core.h:81
CTRL_ERROR
Definition: usbh_core.h:100
usbh_ctrl_struct::timer
uint16_t timer
Definition: usbh_core.h:132
HOST_SUSPENDED
Definition: usbh_core.h:61
HOST_EVENT_ENUM
Definition: usbh_core.h:69
usbh_ctrl_struct::hc_in_num
uint8_t hc_in_num
Definition: usbh_core.h:127
ENUM_GET_PRODUCT_STRING_DESC
Definition: usbh_core.h:87
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:133
usb_descriptor_interface_struct
Definition: usb_std.h:157
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:231
HOST_CLASS
Definition: usbh_core.h:59
HOST_ERROR
Definition: usbh_core.h:62
ctrl_state_enum
ctrl_state_enum
Definition: usbh_core.h:94
usb_descriptor_device_struct
Definition: usb_std.h:127
HOST_DEV_DETACHED
Definition: usbh_core.h:55
scd_table_pop
void scd_table_pop(usbh_state_handle_struct *pustate)
state core driver table pop
Definition: usbh_core.c:644
USBH_NOT_SUPPORTED
Definition: usbh_core.h:111
HOST_EVENT_ERROR
Definition: usbh_core.h:73
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:106
usb_setup_union
Definition: usb_std.h:107
ENUM_GET_CFG_DESC
Definition: usbh_core.h:84
usbh_host_struct
Definition: usbh_core.h:188
usbh_ctrl_struct::ep0_size
uint8_t ep0_size
Definition: usbh_core.h:129
hcd_is_device_connected
uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev)
check if the device is connected.
Definition: usbh_core.c:417
HOST_DEV_ATTACHED
Definition: usbh_core.h:54
usbh_host_struct::usr_cb
usbh_user_callback_struct * usr_cb
Definition: usbh_core.h:193
host_event_enum
host_event_enum
Definition: usbh_core.h:66
backup_state_struct
Definition: usbh_core.h:178
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:237
usbh_device_struct
Definition: usbh_core.h:138
backup_state_struct::enum_backup_state
enum_state_enum enum_backup_state
Definition: usbh_core.h:181
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:223
CTRL_STATUS
Definition: usbh_core.h:99
usbh_device_struct::speed
uint8_t speed
Definition: usbh_core.h:141
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:221
state_table_struct::next_state
uint8_t next_state
Definition: usbh_core.h:206
usbh_ctrl_struct::error_count
uint8_t error_count
Definition: usbh_core.h:130
CTRL_STALLED
Definition: usbh_core.h:101
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:561
USBH_APPLY_DEINIT
Definition: usbh_core.h:114
HOST_ENUMERATION
Definition: usbh_core.h:57
host_state_enum
host_state_enum
Definition: usbh_core.h:51
USBH_UNRECOVERED_ERROR
Definition: usbh_core.h:112
ENUM_SET_ADDR
Definition: usbh_core.h:82
USBH_USER_RESP_OK
Definition: usbh_core.h:121
usbh_state_stack_struct
Definition: usbh_core.h:211
usb_descriptor_endpoint_struct
Definition: usb_std.h:170
enum_state_enum
enum_state_enum
Definition: usbh_core.h:79
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:538
state_table_struct
Definition: usbh_core.h:202
HOST_DETECT_DEV_SPEED
Definition: usbh_core.h:56
scd_event_handle
usbh_status_enum scd_event_handle(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate, uint8_t event, uint8_t state)
state core driver event handle
Definition: usbh_core.c:576
usbh_user_callback_struct
Definition: usbh_core.h:149
usb_core.h
USB core driver header file.
usbh_host_struct::usbh_backup_state
backup_state_struct usbh_backup_state
Definition: usbh_core.h:190
state_table_struct::cur_state
uint8_t cur_state
Definition: usbh_core.h:204
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:214
host_state_polling_fun
usbh_status_enum host_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of HOST state
Definition: usbh_core.c:88
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:622
backup_state_struct::class_req_backup_state
uint8_t class_req_backup_state
Definition: usbh_core.h:183
ACT_FUN
usbh_status_enum(* ACT_FUN)(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
Definition: usbh_core.h:199
ENUM_SET_CONFIGURATION
Definition: usbh_core.h:89
usbh_device_struct::cfg_desc
usb_descriptor_configuration_struct cfg_desc
Definition: usbh_core.h:143
hcd_init
uint32_t hcd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize the host portion of the driver.
Definition: usbh_core.c:385
backup_state_struct::class_backup_state
uint8_t class_backup_state
Definition: usbh_core.h:184
HOST_EVENT_DEV_DETACHED
Definition: usbh_core.h:74
USBH_SPEED_UNKNOWN_ERROR
Definition: usbh_core.h:113
usbh_device_struct::address
uint8_t address
Definition: usbh_core.h:140
USBH_USER_NO_RESP
Definition: usbh_core.h:120
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:222
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:131
usb_core_handle_struct
Definition: usb_core.h:200
HOST_EVENT_ATTACHED
Definition: usbh_core.h:68
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:234
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:230
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:692
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:215
hcd_xfer_count_get
uint32_t hcd_xfer_count_get(usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate
Definition: usbh_core.c:441
usbh_host_struct::device
usbh_device_struct device
Definition: usbh_core.h:192
USBH_OK
Definition: usbh_core.h:108
ENUM_GET_FULL_CFG_DESC
Definition: usbh_core.h:85
ENUM_GET_FULL_DEV_DESC
Definition: usbh_core.h:83
CTRL_SETUP
Definition: usbh_core.h:97
HOST_CLASS_REQUEST
Definition: usbh_core.h:58
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:191
usb_std.h
USB 2.0 standard defines.
USBH_FAIL
Definition: usbh_core.h:110
ENUM_GET_MFC_STRING_DESC
Definition: usbh_core.h:86
MAX_USBH_STATE_STACK_DEEP
#define MAX_USBH_STATE_STACK_DEEP
Definition: usbh_core.h:35
ENUM_GET_SERIALNUM_STRING_DESC
Definition: usbh_core.h:88
HOST_USER_INPUT
Definition: usbh_core.h:60
usbh_device_struct::dev_desc
usb_descriptor_device_struct dev_desc
Definition: usbh_core.h:142
usbh_state_regist_table_struct
Definition: usbh_core.h:219
HOST_IDLE
Definition: usbh_core.h:53
scd_table_regist
void scd_table_regist(usbh_state_handle_struct *pustate, state_table_struct *pstate_table, uint8_t table_id, uint8_t current_table_size)
state core driver table regist
Definition: usbh_core.c:515
CTRL_COMPLETE
Definition: usbh_core.h:102
usbh_ctrl_struct::hc_out_num
uint8_t hc_out_num
Definition: usbh_core.h:128
USBH_BUSY
Definition: usbh_core.h:109
CTRL_DATA
Definition: usbh_core.h:98
state_table_struct::cur_event
uint8_t cur_event
Definition: usbh_core.h:205
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:86
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:134
usb_descriptor_configuration_struct
Definition: usb_std.h:145
backup_state_struct::host_backup_state
host_state_enum host_backup_state
Definition: usbh_core.h:180
HOST_EVENT_USER_INPUT
Definition: usbh_core.h:70
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_pmu.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_pmu.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_pmu.h"
13 #include "core_cm4.h"
14
21 void pmu_deinit(void)
22 {
23 /* reset PMU */
24 rcu_periph_reset_enable(RCU_PMURST);
25 rcu_periph_reset_disable(RCU_PMURST);
26 }
27
43 void pmu_lvd_select(uint32_t lvdt_n)
44 {
45 /* disable LVD */
46 PMU_CTL &= ~PMU_CTL_LVDEN;
47 /* clear LVDT bits */
48 PMU_CTL &= ~PMU_CTL_LVDT;
49 /* set LVDT bits according to lvdt_n */
50 PMU_CTL |= lvdt_n;
51 /* enable LVD */
52 PMU_CTL |= PMU_CTL_LVDEN;
53 }
54
66 void pmu_ldo_output_select(uint32_t ldo_output)
67 {
68 PMU_CTL &= ~PMU_CTL_LDOVS;
69 PMU_CTL |= ldo_output;
70 }
71
78 void pmu_lvd_disable(void)
79 {
80 /* disable LVD */
81 PMU_CTL &= ~PMU_CTL_LVDEN;
82 }
83
90 void pmu_lowdriver_mode_enable(void)
91 {
92 PMU_CTL &= ~PMU_CTL_LDEN;
93 PMU_CTL |= PMU_LOWDRIVER_ENABLE;
94 }
95
102 void pmu_lowdriver_mode_disable(void)
103 {
104 PMU_CTL &= ~PMU_CTL_LDEN;
105 PMU_CTL |= PMU_LOWDRIVER_DISABLE;
106 }
107
115 void pmu_highdriver_mode_enable(void)
116 {
117 PMU_CTL |= PMU_CTL_HDEN;
118 }
119
126 void pmu_highdriver_mode_disable(void)
127 {
128 PMU_CTL &= ~PMU_CTL_HDEN;
129 }
130
141 void pmu_highdriver_switch_select(uint32_t highdr_switch)
142 {
143 /* wait for HDRF flag to be set */
144 while(SET != pmu_flag_get(PMU_FLAG_HDR)){
145 }
146 PMU_CTL &= ~PMU_CTL_HDS;
147 PMU_CTL |= highdr_switch;
148 }
149
159 void pmu_lowpower_driver_config(uint32_t mode)
160 {
161 PMU_CTL &= ~PMU_CTL_LDLP;
162 PMU_CTL |= mode;
163 }
164
174 void pmu_normalpower_driver_config(uint32_t mode)
175 {
176 PMU_CTL &= ~PMU_CTL_LDNP;
177 PMU_CTL |= mode;
178 }
179
189 void pmu_to_sleepmode(uint8_t sleepmodecmd)
190 {
191 /* clear sleepdeep bit of Cortex-M4 system control register */
192 SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
193
194 /* select WFI or WFE command to enter sleep mode */
195 if(WFI_CMD == sleepmodecmd){
196 __WFI();
197 }else{
198 __WFE();
199 }
200 }
201
215 void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
216 {
217 /* clear stbmod and ldolp bits */
218 PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
219
220 /* set ldolp bit according to pmu_ldo */
221 PMU_CTL |= ldo;
222
223 /* set sleepdeep bit of Cortex-M4 system control register */
224 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
225
226 /* select WFI or WFE command to enter deepsleep mode */
227 if(WFI_CMD == deepsleepmodecmd){
228 __WFI();
229 }else{
230 __SEV();
231 __WFE();
232 __WFE();
233 }
234 /* reset sleepdeep bit of Cortex-M4 system control register */
235 SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
236 }
237
247 void pmu_to_standbymode(uint8_t standbymodecmd)
248 {
249 /* set sleepdeep bit of Cortex-M4 system control register */
250 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
251
252 /* set stbmod bit */
253 PMU_CTL |= PMU_CTL_STBMOD;
254
255 /* reset wakeup flag */
256 PMU_CTL |= PMU_CTL_WURST;
257
258 /* select WFI or WFE command to enter standby mode */
259 if(WFI_CMD == standbymodecmd){
260 __WFI();
261 }else{
262 __WFE();
263 }
264 }
265
278 void pmu_wakeup_pin_enable(uint32_t wakeup_pin)
279 {
280 PMU_CS |= wakeup_pin;
281 }
282
295 void pmu_wakeup_pin_disable(uint32_t wakeup_pin)
296 {
297 PMU_CS &= ~(wakeup_pin);
298 }
299
306 void pmu_backup_write_enable(void)
307 {
308 PMU_CTL |= PMU_CTL_BKPWEN;
309 }
310
317 void pmu_backup_write_disable(void)
318 {
319 PMU_CTL &= ~PMU_CTL_BKPWEN;
320 }
321
331 void pmu_flag_clear(uint32_t flag_clear)
332 {
333 if(RESET != (flag_clear & PMU_FLAG_RESET_WAKEUP)){
334 /* reset wakeup flag */
335 PMU_CTL |= PMU_CTL_WURST;
336 }
337 if(RESET != (flag_clear & PMU_FLAG_RESET_STANDBY)){
338 /* reset standby flag */
339 PMU_CTL |= PMU_CTL_STBRST;
340 }
341 }
342
357 FlagStatus pmu_flag_get(uint32_t flag)
358 {
359 FlagStatus ret_status = RESET;
360
361 if(PMU_CS & flag){
362 ret_status = SET;
363 }
364
365 return ret_status;
366 }
PMU_FLAG_RESET_STANDBY
#define PMU_FLAG_RESET_STANDBY
Definition: gd32f3x0_pmu.h:116
PMU_FLAG_RESET_WAKEUP
#define PMU_FLAG_RESET_WAKEUP
Definition: gd32f3x0_pmu.h:115
PMU_CTL_WURST
#define PMU_CTL_WURST
Definition: gd32f3x0_pmu.h:28
pmu_highdriver_mode_disable
void pmu_highdriver_mode_disable(void)
disable high-driver mode
Definition: gd32f3x0_pmu.c:126
pmu_highdriver_mode_enable
void pmu_highdriver_mode_enable(void)
enable high-driver mode this bit set by software only when IRC8M or HXTAL used as system clock ...
Definition: gd32f3x0_pmu.c:115
PMU_CTL_LDLP
#define PMU_CTL_LDLP
Definition: gd32f3x0_pmu.h:33
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
pmu_lvd_disable
void pmu_lvd_disable(void)
disable PMU lvd
Definition: gd32f3x0_pmu.c:78
pmu_normalpower_driver_config
void pmu_normalpower_driver_config(uint32_t mode)
low-driver mode when use normal power LDO
Definition: gd32f3x0_pmu.c:174
PMU_CTL_BKPWEN
#define PMU_CTL_BKPWEN
Definition: gd32f3x0_pmu.h:32
PMU_LOWDRIVER_ENABLE
#define PMU_LOWDRIVER_ENABLE
Definition: gd32f3x0_pmu.h:75
pmu_backup_write_disable
void pmu_backup_write_disable(void)
disable backup domain write
Definition: gd32f3x0_pmu.c:317
pmu_flag_get
FlagStatus pmu_flag_get(uint32_t flag)
get flag state
Definition: gd32f3x0_pmu.c:357
pmu_wakeup_pin_disable
void pmu_wakeup_pin_disable(uint32_t wakeup_pin)
disable wakeup pin
Definition: gd32f3x0_pmu.c:295
PMU_CTL_LVDT
#define PMU_CTL_LVDT
Definition: gd32f3x0_pmu.h:31
gd32f3x0_pmu.h
definitions for the PMU
pmu_lowdriver_mode_disable
void pmu_lowdriver_mode_disable(void)
enable low-driver mode in deep-sleep mode
Definition: gd32f3x0_pmu.c:102
pmu_flag_clear
void pmu_flag_clear(uint32_t flag_clear)
clear flag bit
Definition: gd32f3x0_pmu.c:331
PMU_CTL_LVDEN
#define PMU_CTL_LVDEN
Definition: gd32f3x0_pmu.h:30
PMU_CTL_HDS
#define PMU_CTL_HDS
Definition: gd32f3x0_pmu.h:37
PMU_LOWDRIVER_DISABLE
#define PMU_LOWDRIVER_DISABLE
Definition: gd32f3x0_pmu.h:74
pmu_to_deepsleepmode
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd)
PMU work at deepsleep mode.
Definition: gd32f3x0_pmu.c:215
PMU_CTL_HDEN
#define PMU_CTL_HDEN
Definition: gd32f3x0_pmu.h:36
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
PMU_CTL_LDOVS
#define PMU_CTL_LDOVS
Definition: gd32f3x0_pmu.h:35
pmu_lowdriver_mode_enable
void pmu_lowdriver_mode_enable(void)
enable low-driver mode in deep-sleep mode
Definition: gd32f3x0_pmu.c:90
WFI_CMD
#define WFI_CMD
Definition: gd32f3x0_pmu.h:119
pmu_deinit
void pmu_deinit(void)
reset PMU register
Definition: gd32f3x0_pmu.c:21
PMU_CTL
#define PMU_CTL
Definition: gd32f3x0_pmu.h:21
PMU_FLAG_HDR
#define PMU_FLAG_HDR
Definition: gd32f3x0_pmu.h:103
PMU_CTL_STBMOD
#define PMU_CTL_STBMOD
Definition: gd32f3x0_pmu.h:27
PMU_CTL_LDEN
#define PMU_CTL_LDEN
Definition: gd32f3x0_pmu.h:38
pmu_ldo_output_select
void pmu_ldo_output_select(uint32_t ldo_output)
select LDO output voltage these bits set by software when the main PLL closed
Definition: gd32f3x0_pmu.c:66
pmu_highdriver_switch_select
void pmu_highdriver_switch_select(uint32_t highdr_switch)
switch high-driver mode this bit set by software only when IRC8M or HXTAL used as system clock ...
Definition: gd32f3x0_pmu.c:141
pmu_lvd_select
void pmu_lvd_select(uint32_t lvdt_n)
select low voltage detector threshold
Definition: gd32f3x0_pmu.c:43
PMU_CS
#define PMU_CS
Definition: gd32f3x0_pmu.h:22
pmu_to_sleepmode
void pmu_to_sleepmode(uint8_t sleepmodecmd)
PMU work at sleep mode.
Definition: gd32f3x0_pmu.c:189
PMU_CTL_LDNP
#define PMU_CTL_LDNP
Definition: gd32f3x0_pmu.h:34
pmu_backup_write_enable
void pmu_backup_write_enable(void)
enable backup domain write
Definition: gd32f3x0_pmu.c:306
pmu_to_standbymode
void pmu_to_standbymode(uint8_t standbymodecmd)
pmu work at standby mode
Definition: gd32f3x0_pmu.c:247
pmu_wakeup_pin_enable
void pmu_wakeup_pin_enable(uint32_t wakeup_pin)
enable wakeup pin
Definition: gd32f3x0_pmu.c:278
PMU_CTL_STBRST
#define PMU_CTL_STBRST
Definition: gd32f3x0_pmu.h:29
pmu_lowpower_driver_config
void pmu_lowpower_driver_config(uint32_t mode)
low-driver mode when use low power LDO
Definition: gd32f3x0_pmu.c:159
RCU_PMURST
Definition: gd32f3x0_rcu.h:353
PMU_CTL_LDOLP
#define PMU_CTL_LDOLP
Definition: gd32f3x0_pmu.h:26
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_rtc.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_RTC_H
13 #define GD32F3X0_RTC_H
14
15 #include "gd32f3x0.h"
16
17 /* RTC definitions */
18 #define RTC RTC_BASE
19
20 /* registers definitions */
21 #define RTC_TIME REG32((RTC) + 0x00U)
22 #define RTC_DATE REG32((RTC) + 0x04U)
23 #define RTC_CTL REG32((RTC) + 0x08U)
24 #define RTC_STAT REG32((RTC) + 0x0CU)
25 #define RTC_PSC REG32((RTC) + 0x10U)
26 #define RTC_ALRM0TD REG32((RTC) + 0x1CU)
27 #define RTC_WPK REG32((RTC) + 0x24U)
28 #define RTC_SS REG32((RTC) + 0x28U)
29 #define RTC_SHIFTCTL REG32((RTC) + 0x2CU)
30 #define RTC_TTS REG32((RTC) + 0x30U)
31 #define RTC_DTS REG32((RTC) + 0x34U)
32 #define RTC_SSTS REG32((RTC) + 0x38U)
33 #define RTC_HRFC REG32((RTC) + 0x3CU)
34 #define RTC_TAMP REG32((RTC) + 0x40U)
35 #define RTC_ALRM0SS REG32((RTC) + 0x44U)
36 #define RTC_BKP0 REG32((RTC) + 0x50U)
37 #define RTC_BKP1 REG32((RTC) + 0x54U)
38 #define RTC_BKP2 REG32((RTC) + 0x58U)
39 #define RTC_BKP3 REG32((RTC) + 0x5CU)
40 #define RTC_BKP4 REG32((RTC) + 0x60U)
42 /* bits definitions */
43 /* RTC_TIME */
44 #define RTC_TIME_SCU BITS(0,3)
45 #define RTC_TIME_SCT BITS(4,6)
46 #define RTC_TIME_MNU BITS(8,11)
47 #define RTC_TIME_MNT BITS(12,14)
48 #define RTC_TIME_HRU BITS(16,19)
49 #define RTC_TIME_HRT BITS(20,21)
50 #define RTC_TIME_PM BIT(22)
52 /* RTC_DATE */
53 #define RTC_DATE_DAYU BITS(0,3)
54 #define RTC_DATE_DAYT BITS(4,5)
55 #define RTC_DATE_MONU BITS(8,11)
56 #define RTC_DATE_MONT BIT(12)
57 #define RTC_DATE_DOW BITS(13,15)
58 #define RTC_DATE_YRU BITS(16,19)
59 #define RTC_DATE_YRT BITS(20,23)
61 /* RTC_CTL */
62 #define RTC_CTL_TSEG BIT(3)
63 #define RTC_CTL_REFEN BIT(4)
64 #define RTC_CTL_BPSHAD BIT(5)
65 #define RTC_CTL_CS BIT(6)
66 #define RTC_CTL_ALRM0EN BIT(8)
67 #define RTC_CTL_TSEN BIT(11)
68 #define RTC_CTL_ALRM0IE BIT(12)
69 #define RTC_CTL_TSIE BIT(15)
70 #define RTC_CTL_A1H BIT(16)
71 #define RTC_CTL_S1H BIT(17)
72 #define RTC_CTL_DSM BIT(18)
73 #define RTC_CTL_COS BIT(19)
74 #define RTC_CTL_OPOL BIT(20)
75 #define RTC_CTL_OS BITS(21,22)
76 #define RTC_CTL_COEN BIT(23)
78 /* RTC_STAT */
79 #define RTC_STAT_ALRM0WF BIT(0)
80 #define RTC_STAT_SOPF BIT(3)
81 #define RTC_STAT_YCM BIT(4)
82 #define RTC_STAT_RSYNF BIT(5)
83 #define RTC_STAT_INITF BIT(6)
84 #define RTC_STAT_INITM BIT(7)
85 #define RTC_STAT_ALRM0F BIT(8)
86 #define RTC_STAT_TSF BIT(11)
87 #define RTC_STAT_TSOVRF BIT(12)
88 #define RTC_STAT_TP0F BIT(13)
89 #define RTC_STAT_TP1F BIT(14)
90 #define RTC_STAT_SCPF BIT(16)
92 /* RTC_PSC */
93 #define RTC_PSC_FACTOR_S BITS(0,14)
94 #define RTC_PSC_FACTOR_A BITS(16,22)
96 /* RTC_ALRM0TD */
97 #define RTC_ALRM0TD_SCU BITS(0,3)
98 #define RTC_ALRM0TD_SCT BITS(4,6)
99 #define RTC_ALRM0TD_MSKS BIT(7)
100 #define RTC_ALRM0TD_MNU BITS(8,11)
101 #define RTC_ALRM0TD_MNT BITS(12,14)
102 #define RTC_ALRM0TD_MSKM BIT(15)
103 #define RTC_ALRM0TD_HRU BITS(16,19)
104 #define RTC_ALRM0TD_HRT BITS(20,21)
105 #define RTC_ALRM0TD_PM BIT(22)
106 #define RTC_ALRM0TD_MSKH BIT(23)
107 #define RTC_ALRM0TD_DAYU BITS(24,27)
108 #define RTC_ALRM0TD_DAYT BITS(28,29)
109 #define RTC_ALRM0TD_DOWS BIT(30)
110 #define RTC_ALRM0TD_MSKD BIT(31)
112 /* RTC_WPK */
113 #define RTC_WPK_WPK BITS(0,7)
115 /* RTC_SS */
116 #define RTC_SS_SSC BITS(0,15)
118 /* RTC_SHIFTCTL */
119 #define RTC_SHIFTCTL_SFS BITS(0,14)
120 #define RTC_SHIFTCTL_A1S BIT(31)
122 /* RTC_TTS */
123 #define RTC_TTS_SCU BITS(0,3)
124 #define RTC_TTS_SCT BITS(4,6)
125 #define RTC_TTS_MNU BITS(8,11)
126 #define RTC_TTS_MNT BITS(12,14)
127 #define RTC_TTS_HRU BITS(16,19)
128 #define RTC_TTS_HRT BITS(20,21)
129 #define RTC_TTS_PM BIT(22)
131 /* RTC_DTS */
132 #define RTC_DTS_DAYU BITS(0,3)
133 #define RTC_DTS_DAYT BITS(4,5)
134 #define RTC_DTS_MONU BITS(8,11)
135 #define RTC_DTS_MONT BIT(12)
136 #define RTC_DTS_DOW BITS(13,15)
138 /* RTC_SSTS */
139 #define RTC_SSTS_SSC BITS(0,15)
141 /* RTC_HRFC */
142 #define RTC_HRFC_CMSK BITS(0,8)
143 #define RTC_HRFC_CWND16 BIT(13)
144 #define RTC_HRFC_CWND8 BIT(14)
145 #define RTC_HRFC_FREQI BIT(15)
147 /* RTC_TAMP */
148 #define RTC_TAMP_TP0EN BIT(0)
149 #define RTC_TAMP_TP0EG BIT(1)
150 #define RTC_TAMP_TPIE BIT(2)
151 #define RTC_TAMP_TP1EN BIT(3)
152 #define RTC_TAMP_TP1EG BIT(4)
153 #define RTC_TAMP_TPTS BIT(7)
154 #define RTC_TAMP_FREQ BITS(8,10)
155 #define RTC_TAMP_FLT BITS(11,12)
156 #define RTC_TAMP_PRCH BITS(13,14)
157 #define RTC_TAMP_DISPU BIT(15)
158 #define RTC_TAMP_PC13VAL BIT(18)
159 #define RTC_TAMP_PC13MDE BIT(19)
160 #define RTC_TAMP_PC14VAL BIT(20)
161 #define RTC_TAMP_PC14MDE BIT(21)
162 #define RTC_TAMP_PC15VAL BIT(22)
163 #define RTC_TAMP_PC15MDE BIT(23)
165 /* RTC_ALRM0SS */
166 #define RTC_ALRM0SS_SSC BITS(0,14)
167 #define RTC_ALRM0SS_MASKSSC BITS(24,27)
169 /* RTC_BKP0 */
170 #define RTC_BKP0_DATA BITS(0,31)
172 /* RTC_BKP1 */
173 #define RTC_BKP1_DATA BITS(0,31)
175 /* RTC_BKP2 */
176 #define RTC_BKP2_DATA BITS(0,31)
178 /* RTC_BKP3 */
179 #define RTC_BKP3_DATA BITS(0,31)
181 /* RTC_BKP4 */
182 #define RTC_BKP4_DATA BITS(0,31)
184 /* constants definitions */
185 /* structure for initialization of the RTC */
186 typedef struct
187 {
188 uint8_t rtc_year;
189 uint8_t rtc_month;
190 uint8_t rtc_date;
191 uint8_t rtc_day_of_week;
192 uint8_t rtc_hour;
193 uint8_t rtc_minute;
194 uint8_t rtc_second;
195 uint16_t rtc_factor_asyn;
196 uint16_t rtc_factor_syn;
197 uint32_t rtc_am_pm;
198 uint32_t rtc_display_format;
199 }rtc_parameter_struct;
200
201 /* structure for RTC alarm configuration */
202 typedef struct
203 {
204 uint32_t rtc_alarm_mask;
205 uint32_t rtc_weekday_or_date;
206 uint8_t rtc_alarm_day;
207 uint8_t rtc_alarm_hour;
208 uint8_t rtc_alarm_minute;
209 uint8_t rtc_alarm_second;
210 uint32_t rtc_am_pm;
211 }rtc_alarm_struct;
212
213 /* structure for RTC time-stamp configuration */
214 typedef struct
215 {
216 uint8_t rtc_timestamp_month;
217 uint8_t rtc_timestamp_date;
218 uint8_t rtc_timestamp_day;
219 uint8_t rtc_timestamp_hour;
220 uint8_t rtc_timestamp_minute;
221 uint8_t rtc_timestamp_second;
222 uint32_t rtc_am_pm;
223 }rtc_timestamp_struct;
224
225 /* structure for RTC tamper configuration */
226 typedef struct
227 {
228 uint32_t rtc_tamper_source;
229 uint32_t rtc_tamper_trigger;
230 uint32_t rtc_tamper_filter;
231 uint32_t rtc_tamper_sample_frequency;
232 ControlStatus rtc_tamper_precharge_enable;
233 uint32_t rtc_tamper_precharge_time;
234 ControlStatus rtc_tamper_with_timestamp;
235 }rtc_tamper_struct;
236
237 /* time register value */
238 #define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
239 #define GET_TIME_SC(regval) GET_BITS((regval),0,6)
241 #define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U))
242 #define GET_TIME_MN(regval) GET_BITS((regval),8,14)
244 #define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U))
245 #define GET_TIME_HR(regval) GET_BITS((regval),16,21)
247 #define RTC_AM ((uint32_t)0x00000000U)
248 #define RTC_PM RTC_TIME_PM
250 /* date register value */
251 #define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U))
252 #define GET_DATE_DAY(regval) GET_BITS((regval),0,5)
254 #define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U))
255 #define GET_DATE_MON(regval) GET_BITS((regval),8,12)
256 #define RTC_JAN ((uint8_t)0x01U)
257 #define RTC_FEB ((uint8_t)0x02U)
258 #define RTC_MAR ((uint8_t)0x03U)
259 #define RTC_APR ((uint8_t)0x04U)
260 #define RTC_MAY ((uint8_t)0x05U)
261 #define RTC_JUN ((uint8_t)0x06U)
262 #define RTC_JUL ((uint8_t)0x07U)
263 #define RTC_AUG ((uint8_t)0x08U)
264 #define RTC_SEP ((uint8_t)0x09U)
265 #define RTC_OCT ((uint8_t)0x10U)
266 #define RTC_NOV ((uint8_t)0x11U)
267 #define RTC_DEC ((uint8_t)0x12U)
269 #define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U))
270 #define GET_DATE_DOW(regval) GET_BITS((regval),13,15)
271 #define RTC_MONDAY ((uint8_t)0x01U)
272 #define RTC_TUESDAY ((uint8_t)0x02U)
273 #define RTC_WEDSDAY ((uint8_t)0x03U)
274 #define RTC_THURSDAY ((uint8_t)0x04U)
275 #define RTC_FRIDAY ((uint8_t)0x05U)
276 #define RTC_SATURDAY ((uint8_t)0x06U)
277 #define RTC_SUNDAY ((uint8_t)0x07U)
279 #define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16U))
280 #define GET_DATE_YR(regval) GET_BITS((regval),16,23)
282 /* ctl register value */
283 #define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21U))
284 #define RTC_OS_DISABLE CTL_OS(0)
285 #define RTC_OS_ENABLE CTL_OS(1)
287 #define RTC_CALIBRATION_512HZ RTC_CTL_COEN
288 #define RTC_CALIBRATION_1HZ RTC_CTL_COEN | RTC_CTL_COS
289 #define RTC_ALARM_HIGH RTC_CTL_OS_ENABLE
290 #define RTC_ALARM_LOW RTC_CTL_OS_ENABLE | RTC_CTL_OPOL
292 #define RTC_24HOUR ((uint32_t)0x00000000U)
293 #define RTC_12HOUR RTC_CTL_CS
295 #define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U)
296 #define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG
298 /* psc register value */
299 #define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U))
300 #define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14)
302 #define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16U))
303 #define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22)
305 /* alrm0td register value */
306 #define ALRM0TD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0U))
307 #define GET_ALRM0TD_SC(regval) GET_BITS((regval),0,6)
309 #define ALRM0TD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U))
310 #define GET_ALRM0TD_MN(regval) GET_BITS((regval),8,14)
312 #define ALRM0TD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U))
313 #define GET_ALRM0TD_HR(regval) GET_BITS((regval),16,21)
315 #define ALRM0TD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24U))
316 #define GET_ALRM0TD_DAY(regval) GET_BITS((regval),24,29)
318 #define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U)
319 #define RTC_ALARM_DATE_MASK RTC_ALRM0TD_MSKD
320 #define RTC_ALARM_HOUR_MASK RTC_ALRM0TD_MSKH
321 #define RTC_ALARM_MINUTE_MASK RTC_ALRM0TD_MSKM
322 #define RTC_ALARM_SECOND_MASK RTC_ALRM0TD_MSKS
323 #define RTC_ALARM_ALL_MASK (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS)
325 #define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U)
326 #define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRM0TD_DOWS
328 /* wpk register value */
329 #define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U))
331 /* ss register value */
332 #define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U))
334 /* shiftctl register value */
335 #define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U))
337 #define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U)
338 #define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S
340 /* tts register value */
341 #define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
342 #define GET_TTS_SC(regval) GET_BITS((regval),0,6)
344 #define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U))
345 #define GET_TTS_MN(regval) GET_BITS((regval),8,14)
347 #define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U))
348 #define GET_TTS_HR(regval) GET_BITS((regval),16,21)
350 /* dts register value */
351 #define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U))
352 #define GET_DTS_DAY(regval) GET_BITS((regval),0,5)
354 #define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U))
355 #define GET_DTS_MON(regval) GET_BITS((regval),8,11)
357 #define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U))
358 #define GET_DTS_DOW(regval) GET_BITS((regval),13,15)
360 /* ssts register value */
361 #define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U))
363 /* hrfc register value */
364 #define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0U))
366 #define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U)
367 #define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16
368 #define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8
370 #define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI
371 #define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U)
373 /* tamp register value */
374 #define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U))
375 #define RTC_FREQ_DIV32768 TAMP_FREQ(0)
376 #define RTC_FREQ_DIV16384 TAMP_FREQ(1)
377 #define RTC_FREQ_DIV8192 TAMP_FREQ(2)
378 #define RTC_FREQ_DIV4096 TAMP_FREQ(3)
379 #define RTC_FREQ_DIV2048 TAMP_FREQ(4)
380 #define RTC_FREQ_DIV1024 TAMP_FREQ(5)
381 #define RTC_FREQ_DIV512 TAMP_FREQ(6)
382 #define RTC_FREQ_DIV256 TAMP_FREQ(7)
384 #define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11U))
385 #define RTC_FLT_EDGE TAMP_FLT(0)
386 #define RTC_FLT_2S TAMP_FLT(1)
387 #define RTC_FLT_4S TAMP_FLT(2)
388 #define RTC_FLT_8S TAMP_FLT(3)
390 #define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13U))
391 #define RTC_PRCH_1C TAMP_PRCH(0)
392 #define RTC_PRCH_2C TAMP_PRCH(1)
393 #define RTC_PRCH_4C TAMP_PRCH(2)
394 #define RTC_PRCH_8C TAMP_PRCH(3)
396 #define RTC_TAMPER0 RTC_TAMP_TP0EN
397 #define RTC_TAMPER1 RTC_TAMP_TP1EN
399 #define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U)
400 #define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG
401 #define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U)
402 #define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG
404 #define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */
405
406 #define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U)
407 #define RTC_ALARM_OUTPUT_PP RTC_TAMP_PC13VAL
409 /* alrm0ss register value */
410 #define ALRM0SS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0U))
412 #define ALRM0SS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U))
413 #define RTC_MASKSSC_0_14 ALRM0SS_MASKSSC(0)
414 #define RTC_MASKSSC_1_14 ALRM0SS_MASKSSC(1)
415 #define RTC_MASKSSC_2_14 ALRM0SS_MASKSSC(2)
416 #define RTC_MASKSSC_3_14 ALRM0SS_MASKSSC(3)
417 #define RTC_MASKSSC_4_14 ALRM0SS_MASKSSC(4)
418 #define RTC_MASKSSC_5_14 ALRM0SS_MASKSSC(5)
419 #define RTC_MASKSSC_6_14 ALRM0SS_MASKSSC(6)
420 #define RTC_MASKSSC_7_14 ALRM0SS_MASKSSC(7)
421 #define RTC_MASKSSC_8_14 ALRM0SS_MASKSSC(8)
422 #define RTC_MASKSSC_9_14 ALRM0SS_MASKSSC(9)
423 #define RTC_MASKSSC_10_14 ALRM0SS_MASKSSC(10)
424 #define RTC_MASKSSC_11_14 ALRM0SS_MASKSSC(11)
425 #define RTC_MASKSSC_12_14 ALRM0SS_MASKSSC(12)
426 #define RTC_MASKSSC_13_14 ALRM0SS_MASKSSC(13)
427 #define RTC_MASKSSC_14 ALRM0SS_MASKSSC(14)
428 #define RTC_MASKSSC_NONE ALRM0SS_MASKSSC(15)
430 /* RTC interrupt source */
431 #define RTC_INT_TIMESTAMP RTC_CTL_TSIE
432 #define RTC_INT_ALARM RTC_CTL_ALRM0IE
433 #define RTC_INT_TAMP RTC_TAMP_TPIE
435 /* write protect key */
436 #define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU)
437 #define RTC_UNLOCK_KEY2 ((uint8_t)0x53U)
438 #define RTC_LOCK_KEY ((uint8_t)0xFFU)
440 /* registers reset value */
441 #define RTC_REGISTER_RESET ((uint32_t)0x00000000U)
442 #define RTC_DATE_RESET ((uint32_t)0x00002101U)
443 #define RTC_STAT_RESET ((uint32_t)0x00000007U)
444 #define RTC_PSC_RESET ((uint32_t)0x007F00FFU)
446 /* RTC timeout value */
447 #define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U)
448 #define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U)
449 #define RTC_HRFC_TIMEOUT ((uint32_t)0x00001000U)
450 #define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U)
451 #define RTC_ALRM0WF_TIMEOUT ((uint32_t)0x00008000U)
453 /* RTC flag */
454 #define RTC_FLAG_RECALIBRATION RTC_STAT_SCPF
455 #define RTC_FLAG_TAMP1 RTC_STAT_TP1F
456 #define RTC_FLAG_TAMP0 RTC_STAT_TP0F
457 #define RTC_FLAG_TIMESTAMP_OVERFLOW RTC_STAT_TSOVRF
458 #define RTC_FLAG_TIMESTAMP RTC_STAT_TSF
459 #define RTC_FLAG_ALARM0 RTC_STAT_ALRM0F
460 #define RTC_FLAG_INIT RTC_STAT_INITF
461 #define RTC_FLAG_RSYN RTC_STAT_RSYNF
462 #define RTC_FLAG_YCM RTC_STAT_YCM
463 #define RTC_FLAG_SHIFT RTC_STAT_SOPF
464 #define RTC_FLAG_ALARM0_WRITTEN RTC_STAT_ALRM0WF
466 /* function declarations */
467 /* reset most of the RTC registers */
468 ErrStatus rtc_deinit(void);
469 /* initialize RTC registers */
470 ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct);
471 /* enter RTC init mode */
472 ErrStatus rtc_init_mode_enter(void);
473 /* exit RTC init mode */
474 void rtc_init_mode_exit(void);
475 /* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */
476 ErrStatus rtc_register_sync_wait(void);
477
478 /* get current time and date */
479 void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct);
480 /* get current subsecond value */
481 uint32_t rtc_subsecond_get(void);
482
483 /* configure RTC alarm */
484 void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time);
485 /* configure subsecond of RTC alarm */
486 void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond);
487 /* get RTC alarm */
488 void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time);
489 /* get RTC alarm subsecond */
490 uint32_t rtc_alarm_subsecond_get(void);
491 /* enable RTC alarm */
492 void rtc_alarm_enable(void);
493 /* disable RTC alarm */
494 ErrStatus rtc_alarm_disable(void);
495
496 /* enable RTC time-stamp */
497 void rtc_timestamp_enable(uint32_t edge);
498 /* disable RTC time-stamp */
499 void rtc_timestamp_disable(void);
500 /* get RTC timestamp time and date */
501 void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp);
502 /* get RTC time-stamp subsecond */
503 uint32_t rtc_timestamp_subsecond_get(void);
504
505 /* enable RTC tamper */
506 void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper);
507 /* disable RTC tamper */
508 void rtc_tamper_disable(uint32_t source);
509
510 /* enable specified RTC interrupt */
511 void rtc_interrupt_enable(uint32_t interrupt);
512 /* disble specified RTC interrupt */
513 void rtc_interrupt_disable(uint32_t interrupt);
514 /* check specified flag */
515 FlagStatus rtc_flag_get(uint32_t flag);
516 /* clear specified flag */
517 void rtc_flag_clear(uint32_t flag);
518
519 /* configure RTC alternate output source */
520 void rtc_alter_output_config(uint32_t source, uint32_t mode);
521 /* configure RTC calibration register */
522 ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus);
523 /* ajust the daylight saving time by adding or substracting one hour from the current time */
524 void rtc_hour_adjust(uint32_t operation);
525 /* ajust RTC second or subsecond value of current time */
526 ErrStatus rtc_second_ajust(uint32_t add, uint32_t minus);
527 /* enable RTC bypass shadow registers function */
528 void rtc_bypass_shadow_enable(void);
529 /* disable RTC bypass shadow registers function */
530 void rtc_bypass_shadow_disable(void);
531 /* enable RTC reference clock detection function */
532 ErrStatus rtc_refclock_detection_enable(void);
533 /* disable RTC reference clock detection function */
534 ErrStatus rtc_refclock_detection_disable(void);
535
536 #endif /* GD32F3X0_RTC_H */
rtc_alarm_get
void rtc_alarm_get(rtc_alarm_struct *rtc_alarm_time)
get RTC alarm
Definition: gd32f3x0_rtc.c:418
rtc_flag_clear
void rtc_flag_clear(uint32_t flag)
clear specified flag
Definition: gd32f3x0_rtc.c:698
rtc_alarm_struct::rtc_alarm_hour
uint8_t rtc_alarm_hour
Definition: gd32f3x0_rtc.h:207
rtc_parameter_struct::rtc_minute
uint8_t rtc_minute
Definition: gd32f3x0_rtc.h:193
rtc_timestamp_disable
void rtc_timestamp_disable(void)
disable RTC time-stamp
Definition: gd32f3x0_rtc.c:480
rtc_alarm_struct::rtc_alarm_mask
uint32_t rtc_alarm_mask
Definition: gd32f3x0_rtc.h:204
rtc_bypass_shadow_enable
void rtc_bypass_shadow_enable(void)
enable RTC bypass shadow registers function
Definition: gd32f3x0_rtc.c:764
rtc_init_mode_exit
void rtc_init_mode_exit(void)
exit RTC init mode
Definition: gd32f3x0_rtc.c:168
rtc_parameter_struct::rtc_year
uint8_t rtc_year
Definition: gd32f3x0_rtc.h:188
rtc_alarm_subsecond_get
uint32_t rtc_alarm_subsecond_get(void)
get RTC alarm subsecond
Definition: gd32f3x0_rtc.c:441
rtc_timestamp_struct::rtc_timestamp_second
uint8_t rtc_timestamp_second
Definition: gd32f3x0_rtc.h:221
rtc_tamper_disable
void rtc_tamper_disable(uint32_t source)
disable RTC tamper
Definition: gd32f3x0_rtc.c:604
rtc_alter_output_config
void rtc_alter_output_config(uint32_t source, uint32_t mode)
configure rtc alternate output source
Definition: gd32f3x0_rtc.c:718
rtc_calibration_config
ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus)
configure RTC calibration register
Definition: gd32f3x0_rtc.c:903
rtc_timestamp_struct::rtc_timestamp_date
uint8_t rtc_timestamp_date
Definition: gd32f3x0_rtc.h:217
rtc_tamper_struct::rtc_tamper_sample_frequency
uint32_t rtc_tamper_sample_frequency
Definition: gd32f3x0_rtc.h:231
rtc_timestamp_subsecond_get
uint32_t rtc_timestamp_subsecond_get(void)
get RTC time-stamp subsecond
Definition: gd32f3x0_rtc.c:534
rtc_alarm_subsecond_config
void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond)
configure subsecond of RTC alarm
Definition: gd32f3x0_rtc.c:336
rtc_parameter_struct::rtc_am_pm
uint32_t rtc_am_pm
Definition: gd32f3x0_rtc.h:197
rtc_tamper_struct::rtc_tamper_with_timestamp
ControlStatus rtc_tamper_with_timestamp
Definition: gd32f3x0_rtc.h:234
rtc_deinit
ErrStatus rtc_deinit(void)
reset most of the RTC registers
Definition: gd32f3x0_rtc.c:20
rtc_interrupt_disable
void rtc_interrupt_disable(uint32_t interrupt)
disble specified RTC interrupt
Definition: gd32f3x0_rtc.c:644
rtc_parameter_struct::rtc_display_format
uint32_t rtc_display_format
Definition: gd32f3x0_rtc.h:198
rtc_refclock_detection_disable
ErrStatus rtc_refclock_detection_disable(void)
disable RTC reference clock detection function
Definition: gd32f3x0_rtc.c:829
rtc_timestamp_struct::rtc_am_pm
uint32_t rtc_am_pm
Definition: gd32f3x0_rtc.h:222
rtc_second_ajust
ErrStatus rtc_second_ajust(uint32_t add, uint32_t minus)
ajust RTC second or subsecond value of current time
Definition: gd32f3x0_rtc.c:861
rtc_timestamp_get
void rtc_timestamp_get(rtc_timestamp_struct *rtc_timestamp)
get RTC timestamp time and date
Definition: gd32f3x0_rtc.c:510
rtc_parameter_struct::rtc_date
uint8_t rtc_date
Definition: gd32f3x0_rtc.h:190
rtc_current_time_get
void rtc_current_time_get(rtc_parameter_struct *rtc_initpara_struct)
get current time and date
Definition: gd32f3x0_rtc.c:233
rtc_alarm_struct::rtc_alarm_day
uint8_t rtc_alarm_day
Definition: gd32f3x0_rtc.h:206
rtc_timestamp_struct::rtc_timestamp_day
uint8_t rtc_timestamp_day
Definition: gd32f3x0_rtc.h:218
rtc_parameter_struct::rtc_hour
uint8_t rtc_hour
Definition: gd32f3x0_rtc.h:192
rtc_init_mode_enter
ErrStatus rtc_init_mode_enter(void)
enter RTC init mode
Definition: gd32f3x0_rtc.c:138
rtc_parameter_struct::rtc_second
uint8_t rtc_second
Definition: gd32f3x0_rtc.h:194
rtc_parameter_struct::rtc_day_of_week
uint8_t rtc_day_of_week
Definition: gd32f3x0_rtc.h:191
rtc_hour_adjust
void rtc_hour_adjust(uint32_t operation)
ajust the daylight saving time by adding or substracting one hour from the current time ...
Definition: gd32f3x0_rtc.c:746
rtc_alarm_disable
ErrStatus rtc_alarm_disable(void)
disable RTC alarm
Definition: gd32f3x0_rtc.c:372
rtc_parameter_struct::rtc_factor_asyn
uint16_t rtc_factor_asyn
Definition: gd32f3x0_rtc.h:195
rtc_alarm_config
void rtc_alarm_config(rtc_alarm_struct *rtc_alarm_time)
configure RTC alarm
Definition: gd32f3x0_rtc.c:291
rtc_register_sync_wait
ErrStatus rtc_register_sync_wait(void)
wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers ...
Definition: gd32f3x0_rtc.c:180
rtc_parameter_struct
Definition: gd32f3x0_rtc.h:186
rtc_alarm_struct::rtc_alarm_minute
uint8_t rtc_alarm_minute
Definition: gd32f3x0_rtc.h:208
rtc_timestamp_enable
void rtc_timestamp_enable(uint32_t edge)
enable RTC time-stamp
Definition: gd32f3x0_rtc.c:454
rtc_flag_get
FlagStatus rtc_flag_get(uint32_t flag)
check specified flag
Definition: gd32f3x0_rtc.c:676
rtc_tamper_struct::rtc_tamper_trigger
uint32_t rtc_tamper_trigger
Definition: gd32f3x0_rtc.h:229
rtc_timestamp_struct
Definition: gd32f3x0_rtc.h:214
rtc_tamper_struct::rtc_tamper_source
uint32_t rtc_tamper_source
Definition: gd32f3x0_rtc.h:228
rtc_timestamp_struct::rtc_timestamp_minute
uint8_t rtc_timestamp_minute
Definition: gd32f3x0_rtc.h:220
rtc_alarm_struct::rtc_weekday_or_date
uint32_t rtc_weekday_or_date
Definition: gd32f3x0_rtc.h:205
rtc_alarm_enable
void rtc_alarm_enable(void)
enable RTC alarm
Definition: gd32f3x0_rtc.c:354
rtc_subsecond_get
uint32_t rtc_subsecond_get(void)
get current subsecond value
Definition: gd32f3x0_rtc.c:262
rtc_bypass_shadow_disable
void rtc_bypass_shadow_disable(void)
disable RTC bypass shadow registers function
Definition: gd32f3x0_rtc.c:782
rtc_tamper_struct::rtc_tamper_precharge_enable
ControlStatus rtc_tamper_precharge_enable
Definition: gd32f3x0_rtc.h:232
rtc_interrupt_enable
void rtc_interrupt_enable(uint32_t interrupt)
enable specified RTC interrupt
Definition: gd32f3x0_rtc.c:620
rtc_alarm_struct::rtc_alarm_second
uint8_t rtc_alarm_second
Definition: gd32f3x0_rtc.h:209
rtc_alarm_struct::rtc_am_pm
uint32_t rtc_am_pm
Definition: gd32f3x0_rtc.h:210
rtc_init
ErrStatus rtc_init(rtc_parameter_struct *rtc_initpara_struct)
initialize RTC registers
Definition: gd32f3x0_rtc.c:87
rtc_timestamp_struct::rtc_timestamp_month
uint8_t rtc_timestamp_month
Definition: gd32f3x0_rtc.h:216
rtc_tamper_struct::rtc_tamper_precharge_time
uint32_t rtc_tamper_precharge_time
Definition: gd32f3x0_rtc.h:233
rtc_alarm_struct
Definition: gd32f3x0_rtc.h:202
rtc_parameter_struct::rtc_factor_syn
uint16_t rtc_factor_syn
Definition: gd32f3x0_rtc.h:196
rtc_tamper_struct
Definition: gd32f3x0_rtc.h:226
rtc_parameter_struct::rtc_month
uint8_t rtc_month
Definition: gd32f3x0_rtc.h:189
rtc_timestamp_struct::rtc_timestamp_hour
uint8_t rtc_timestamp_hour
Definition: gd32f3x0_rtc.h:219
rtc_tamper_struct::rtc_tamper_filter
uint32_t rtc_tamper_filter
Definition: gd32f3x0_rtc.h:230
rtc_tamper_enable
void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper)
enable RTC tamper
Definition: gd32f3x0_rtc.c:557
rtc_refclock_detection_enable
ErrStatus rtc_refclock_detection_enable(void)
enable RTC reference clock detection function
Definition: gd32f3x0_rtc.c:800
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_core.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
usb_core.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef USB_CORE_H
13 #define USB_CORE_H
14
15 #include "usb_conf.h"
16 #include "usb_regs.h"
17 #include "usb_defines.h"
18
19 #define USB_MAX_EP0_SIZE 64U /* endpoint 0 max packet size */
20 #define RX_MAX_DATA_LENGTH 512U /* host rx buffer max data length */
21 #define HC_MAX_PACKET_COUNT 140U /* host channel max packet count */
22
23 #define USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT
24 #define USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U)
25
26 /* USB core status */
27 typedef enum
28 {
29 USB_OK = 0, /* USB core OK status */
30 USB_FAIL /* USB core fail status */
31 }usb_status_enum;
32
33 /* USB host channel status */
34 typedef enum
35 {
36 HC_IDLE = 0, /* USB host channel idle status */
37 HC_XF, /* USB host channel transfer status */
38 HC_HALTED, /* USB host channel halted status */
39 HC_NAK, /* USB host channel nak status */
40 HC_NYET, /* USB host channel nyet status */
41 HC_STALL, /* USB host channel stall status */
42 HC_TRACERR, /* USB host channel tracerr status */
43 HC_BBERR, /* USB host channel bberr status */
44 HC_DTGERR, /* USB host channel dtgerr status */
45 }hc_status_enum;
46
47 /* USB URB(USB request block) state */
48 typedef enum
49 {
50 URB_IDLE = 0, /* USB URB idle status */
51 URB_DONE, /* USB URB done status */
52 URB_NOTREADY, /* USB URB notready status */
53 URB_ERROR, /* USB URB error status */
54 URB_STALL, /* USB URB stall status */
55 URB_PING /* USB URB ping status */
56 }urb_state_enum;
57
58 /* USB core configuration */
59 typedef struct
60 {
61 uint8_t core_id; /* USB core id */
62 uint8_t core_speed; /* USB core speed */
63 uint8_t phy_interface; /* USB PHY interface */
64 uint8_t host_channel_num; /* USB host channel number */
65 uint8_t dev_endp_num; /* USB device endpoint number */
66 uint8_t sof_output; /* USB SOF output */
67 uint8_t low_power; /* USB low power */
68 uint16_t max_packet_size; /* USB max packet size */
69 uint16_t max_fifo_size; /* USB fifo size */
70 }usb_core_cfgs_struct;
71
72 typedef enum
73 {
74 USBD_OK = 0, /* USB device ok status */
75 USBD_BUSY, /* USB device busy status */
76 USBD_FAIL, /* USB device fail stauts */
77 }usbd_status_enum;
78
79 /* USB control transfer state */
80 typedef enum
81 {
82 USB_CTRL_IDLE = 0, /* USB control transfer idle state */
83 USB_CTRL_SETUP, /* USB control transfer setup state */
84 USB_CTRL_DATA_IN, /* USB control transfer data in state */
85 USB_CTRL_DATA_OUT, /* USB control transfer data out state */
86 USB_CTRL_STATUS_IN, /* USB control transfer status in state*/
87 USB_CTRL_STATUS_OUT, /* USB control transfer status out state */
88 USB_CTRL_STALL /* USB control transfer stall state */
89 }usbd_control_state_enum;
90
91 /* USB transfer direction */
92 typedef enum
93 {
94 USB_RX = 0, /* receive direction type value */
95 USB_TX /* transmit direction type value */
96 }usb_dir_enum;
97
98 /* USB endpoint in device mode */
99 typedef struct
100 {
101 uint8_t endp_type; /* USB endpoint type */
102 uint8_t endp_frame; /* USB endpoint frame */
103 uint32_t endp_mps; /* USB endpoint max packet size */
104
105 /* Transaction level variables */
106 uint8_t *xfer_buff; /* USB transfer buffer */
107 uint32_t xfer_len; /* USB transfer length */
108 uint32_t xfer_count; /* USB transfer count */
109
110 uint32_t dma_addr; /* USBHS can use DMA */
111 }usb_ep_struct;
112
113 /* USB device standard request */
114 typedef struct
115 {
116 uint8_t bmRequestType; /* USB device request type */
117 uint8_t bRequest; /* USB device request */
118 uint16_t wValue; /* USB device request value */
119 uint16_t wIndex; /* USB device request index */
120 uint16_t wLength; /* USB device request length */
121 }usb_device_req_struct;
122
123 /* USB core device driver */
124 typedef struct
125 {
126 uint8_t config_num; /* USB configuration number */
127 uint8_t status; /* USB status */
128 uint8_t ctl_status; /* USB control status */
129 uint8_t prev_status; /* USB previous status */
130 uint8_t connection_status; /* USB connection status */
131 uint32_t remote_wakeup; /* USB remote wakeup */
132
133 /* transfer level variables */
134 uint32_t remain_len; /* USB remain length */
135 uint32_t sum_len; /* USB sum length */
136 uint32_t ctl_len; /* USB control length */
137 uint8_t setup_packet[8 * 3]; /* USB setup packet */
138
139 usb_ep_struct in_ep[USB_MAX_DEV_EPCOUNT]; /* USB IN endpoint */
140 usb_ep_struct out_ep[USB_MAX_DEV_EPCOUNT]; /* USB OUT endpoint */
141
142 uint8_t *dev_desc; /* device descriptor */
143 uint8_t *config_desc; /* configuration descriptor */
144 uint8_t* *strings; /* configuration strings */
145
146 /* device class handler */
147 uint8_t (*class_init) (void *pudev, uint8_t config_index); /* device class initialize */
148 uint8_t (*class_deinit) (void *pudev, uint8_t config_index); /* device class deinitialize */
149 uint8_t (*class_req_handler) (void *pudev, usb_device_req_struct *req); /* device request handler */
150 uint8_t (*class_data_handler) (void *pudev, usb_dir_enum rx_tx, uint8_t ep_num); /* device data handler */
151 }dcd_dev_struct;
152
153 /* USB core host mode channel */
154 typedef struct
155 {
156 uint8_t dev_addr; /* device address */
157 uint8_t dev_speed; /* device speed */
158 uint8_t DPID; /* endpoint transfer data pid */
159 uint8_t endp_id; /* endpoint number */
160 uint8_t endp_in; /* endpoint in */
161 uint8_t endp_type; /* endpoint type */
162 uint16_t endp_mps; /* endpoint max pactet size */
163 uint16_t info; /* channel information */
164
165 uint8_t *xfer_buff; /* transfer buffer */
166 uint32_t xfer_len; /* transfer length */
167 uint32_t xfer_count; /* trasnfer count */
168
169 uint32_t err_count; /* USB transfer error count */
170
171 hc_status_enum status; /* channel status */
172 urb_state_enum urb_state; /* URB state */
173
174 uint8_t data_tg_in; /* data in toggle */
175 uint8_t data_tg_out; /* data out toggle */
176 }usb_hostchannel_struct;
177
178 /* USB core host driver */
179 typedef struct
180 {
181 uint8_t rx_buffer[RX_MAX_DATA_LENGTH]; /* rx buffer */
182 uint8_t connect_status; /* device connect status */
183 usb_hostchannel_struct host_channel[USB_MAX_FIFOS]; /* host channel */
184 void (*vbus_drive) (void *pudev, uint8_t state); /* the vbus driver function */
185 }hcd_dev_struct;
186
187 #ifdef USE_OTG_MODE
188
189 /* USB core OTG-mode driver */
190 typedef struct
191 {
192 uint8_t OTG_State; /* OTG state */
193 uint8_t OTG_PrevState; /* OTG previous state */
194 uint8_t OTG_Mode; /* OTG mode */
195 }otg_dev_struct;
196
197 #endif /* USE_OTG_MODE */
198
199 /* USB core driver */
200 typedef struct
201 {
202 usb_core_cfgs_struct cfg;
203
204 #ifdef USE_DEVICE_MODE
205 dcd_dev_struct dev;
206 #endif /* USE_DEVICE_MODE */
207
208 #ifdef USE_HOST_MODE
209 hcd_dev_struct host;
210 #endif /* USE_HOST_MODE */
211
212 #ifdef USE_OTG_MODE
213 otg_dev_struct otg;
214 #endif /* USE_OTG_MODE */
215
216 void (*udelay) (const uint32_t usec);
217 void (*mdelay) (const uint32_t msec);
218 }usb_core_handle_struct;
219
220 /* function declarations */
221
222 /* global APIs */
223 /* initializes the USB controller registers and prepares the core device mode or host mode operation */
224 usb_status_enum usb_core_init (usb_core_handle_struct *pudev);
225 /* initialize core parameters */
226 usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id);
227 /* read a packet from the Rx FIFO associated with the endpoint */
228 void* usb_fifo_read (uint8_t *dest, uint16_t len);
229 /* write a packet into the Tx FIFO associated with the endpoint */
230 usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len);
231 /* flush a Tx FIFO or all Tx FIFOs */
232 usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num);
233 /* flush the entire Rx FIFO */
234 usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev);
235 /* set operation mode (host or device) */
236 usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode);
237
238 /* host APIs */
239 #ifdef USE_HOST_MODE
240
241 /* initializes USB core for host mode */
242 usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev);
243 /* enables the host mode interrupts */
244 usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev);
245 /* initialize host channel */
246 usb_status_enum usb_hostchannel_init (usb_core_handle_struct *pudev, uint8_t hc_num);
247 /* halt channel */
248 usb_status_enum usb_hostchannel_halt (usb_core_handle_struct *pudev, uint8_t hc_num);
249 /* prepare host channel for transferring packets */
250 usb_status_enum usb_hostchannel_startxfer (usb_core_handle_struct *pudev, uint8_t hc_num);
251 /* reset host port */
252 uint32_t usb_port_reset (usb_core_handle_struct *pudev);
253 /* control the VBUS to power */
254 void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state);
255 /* stop the USB host and clean up fifos */
256 void usb_host_stop (usb_core_handle_struct *pudev);
257
258 #endif /* USE_HOST_MODE */
259
260 /* device APIs */
261 #ifdef USE_DEVICE_MODE
262
263 /* initialize USB core registers for device mode */
264 usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev);
265 /* configures endpoint 0 to receive SETUP packets */
266 void usb_ep0_startout (usb_core_handle_struct *pudev);
267 /* active remote wakeup signalling */
268 void usb_remotewakeup_active (usb_core_handle_struct *pudev);
269 /* active USB core clock */
270 void usb_clock_ungate (usb_core_handle_struct *pudev);
271 /* stop the device and clean up fifos */
272 void usb_device_stop (usb_core_handle_struct *pudev);
273
274 #endif /* USE_DEVICE_MODE */
275
276 #endif /* USB_CORE_H */
HC_NYET
Definition: usb_core.h:40
usb_txfifo_flush
usb_status_enum usb_txfifo_flush(usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs
Definition: usb_core.c:208
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:125
USB_CTRL_STATUS_OUT
Definition: usb_core.h:87
USB_MAX_DEV_EPCOUNT
#define USB_MAX_DEV_EPCOUNT
Definition: usb_core.h:23
HC_XF
Definition: usb_core.h:37
USB_TX
Definition: usb_core.h:95
dcd_dev_struct::config_num
uint8_t config_num
Definition: usb_core.h:126
usb_fifo_read
void * usb_fifo_read(uint8_t *dest, uint16_t len)
read a packet from the Rx FIFO associated with the endpoint
Definition: usb_core.c:102
usb_device_req_struct::wIndex
uint16_t wIndex
Definition: usb_core.h:119
URB_STALL
Definition: usb_core.h:54
usb_hostchannel_struct::info
uint16_t info
Definition: usb_core.h:163
USBD_OK
Definition: usb_core.h:74
USB_CTRL_STATUS_IN
Definition: usb_core.h:86
usb_device_req_struct::wLength
uint16_t wLength
Definition: usb_core.h:120
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:266
usb_hostchannel_struct::urb_state
urb_state_enum urb_state
Definition: usb_core.h:172
usb_rxfifo_flush
usb_status_enum usb_rxfifo_flush(usb_core_handle_struct *pudev)
flush the entire Rx FIFO
Definition: usb_core.c:236
usb_hostchannel_struct::status
hc_status_enum status
Definition: usb_core.h:171
usb_ep_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:108
urb_state_enum
urb_state_enum
Definition: usb_core.h:48
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:165
dcd_dev_struct::prev_status
uint8_t prev_status
Definition: usb_core.h:129
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:175
usb_core_cfgs_struct::dev_endp_num
uint8_t dev_endp_num
Definition: usb_core.h:65
dcd_dev_struct::remain_len
uint32_t remain_len
Definition: usb_core.h:134
usb_core_cfgs_struct::max_packet_size
uint16_t max_packet_size
Definition: usb_core.h:68
URB_PING
Definition: usb_core.h:55
hc_status_enum
hc_status_enum
Definition: usb_core.h:34
hcd_dev_struct
Definition: usb_core.h:179
usb_device_req_struct
Definition: usb_core.h:114
USB_CTRL_DATA_IN
Definition: usb_core.h:84
usb_fifo_write
usb_status_enum usb_fifo_write(uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint
Definition: usb_core.c:79
USB_CTRL_STALL
Definition: usb_core.h:88
USB_OK
Definition: usb_core.h:29
HC_BBERR
Definition: usb_core.h:43
USB_CTRL_DATA_OUT
Definition: usb_core.h:85
USB_MAX_FIFOS
#define USB_MAX_FIFOS
Definition: usb_core.h:24
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:160
dcd_dev_struct::ctl_len
uint32_t ctl_len
Definition: usb_core.h:136
dcd_dev_struct::status
uint8_t status
Definition: usb_core.h:127
dcd_dev_struct
Definition: usb_core.h:124
HC_IDLE
Definition: usb_core.h:36
usb_device_req_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_core.h:116
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:101
dcd_dev_struct::dev_desc
uint8_t * dev_desc
Definition: usb_core.h:142
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:103
URB_IDLE
Definition: usb_core.h:50
URB_NOTREADY
Definition: usb_core.h:52
usb_core_cfgs_struct::phy_interface
uint8_t phy_interface
Definition: usb_core.h:63
dcd_dev_struct::strings
uint8_t ** strings
Definition: usb_core.h:144
usb_ep_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:107
dcd_dev_struct::ctl_status
uint8_t ctl_status
Definition: usb_core.h:128
usb_ep_struct::endp_frame
uint8_t endp_frame
Definition: usb_core.h:102
usb_hostchannel_struct::err_count
uint32_t err_count
Definition: usb_core.h:169
dcd_dev_struct::config_desc
uint8_t * config_desc
Definition: usb_core.h:143
usb_regs.h
USB FS cell registers definition and handle macros.
usb_hostchannel_struct
Definition: usb_core.h:154
dcd_dev_struct::connection_status
uint8_t connection_status
Definition: usb_core.h:130
usb_core_cfgs_struct::sof_output
uint8_t sof_output
Definition: usb_core.h:66
USB_RX
Definition: usb_core.h:94
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:174
usb_hostchannel_struct::endp_mps
uint16_t endp_mps
Definition: usb_core.h:162
usb_ep_struct
Definition: usb_core.h:99
HC_TRACERR
Definition: usb_core.h:42
usb_core_cfgs_struct::core_speed
uint8_t core_speed
Definition: usb_core.h:62
usb_core_cfgs_struct::low_power
uint8_t low_power
Definition: usb_core.h:67
usb_core_cfgs_struct
Definition: usb_core.h:59
usb_hostchannel_struct::DPID
uint8_t DPID
Definition: usb_core.h:158
HC_NAK
Definition: usb_core.h:39
usb_dir_enum
usb_dir_enum
Definition: usb_core.h:92
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:166
usbd_status_enum
usbd_status_enum
Definition: usb_core.h:72
HC_STALL
Definition: usb_core.h:41
usb_status_enum
usb_status_enum
Definition: usb_core.h:27
usb_hostchannel_struct::dev_addr
uint8_t dev_addr
Definition: usb_core.h:156
HC_HALTED
Definition: usb_core.h:38
USB_FAIL
Definition: usb_core.h:30
usb_core_handle_struct
Definition: usb_core.h:200
usb_hostchannel_struct::dev_speed
uint8_t dev_speed
Definition: usb_core.h:157
URB_ERROR
Definition: usb_core.h:53
dcd_dev_struct::remote_wakeup
uint32_t remote_wakeup
Definition: usb_core.h:131
usb_defines.h
USB core defines.
USB_CTRL_SETUP
Definition: usb_core.h:83
usb_core_cfgs_struct::max_fifo_size
uint16_t max_fifo_size
Definition: usb_core.h:69
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:161
HC_DTGERR
Definition: usb_core.h:44
usb_core_cfgs_struct::core_id
uint8_t core_id
Definition: usb_core.h:61
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:167
usb_device_req_struct::bRequest
uint8_t bRequest
Definition: usb_core.h:117
USBD_FAIL
Definition: usb_core.h:76
usb_core_cfgs_struct::host_channel_num
uint8_t host_channel_num
Definition: usb_core.h:64
USBD_BUSY
Definition: usb_core.h:75
dcd_dev_struct::sum_len
uint32_t sum_len
Definition: usb_core.h:135
hcd_dev_struct::connect_status
uint8_t connect_status
Definition: usb_core.h:182
RX_MAX_DATA_LENGTH
#define RX_MAX_DATA_LENGTH
Definition: usb_core.h:20
URB_DONE
Definition: usb_core.h:51
usb_hostchannel_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:167
usb_device_req_struct::wValue
uint16_t wValue
Definition: usb_core.h:118
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:106
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:86
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:202
USB_CTRL_IDLE
Definition: usb_core.h:82
usb_hostchannel_struct::endp_id
uint8_t endp_id
Definition: usb_core.h:159
usbd_control_state_enum
usbd_control_state_enum
Definition: usb_core.h:80
usb_ep_struct::dma_addr
uint32_t dma_addr
Definition: usb_core.h:110
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbh_std.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
usbh_std.c
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1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "usbh_core.h"
13 #include "usbh_usr.h"
14 #include "usbh_std.h"
15 #include "usbh_ctrl.h"
16
17 uint8_t local_buffer[64];
18 uint8_t usbh_cfg_desc[512];
19 uint8_t enum_polling_handle_flag = 0U;
20
21 static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
22 static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
23 static void enum_set_addr_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
24 static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
25 static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
26 static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
27 static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
28 static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
29 static void enum_set_configuration_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
30 static void enum_dev_configured_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
31
32 /* the enumeration state handle function array */
33 void (*enum_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) =
34 {
35 enum_idle_handle,
36 enum_set_addr_handle,
37 enum_get_full_dev_desc_handle,
38 enum_get_cfg_desc_handle,
39 enum_get_full_cfg_desc_handle,
40 enum_get_mfc_string_desc_handle,
41 enum_get_product_string_desc_handle,
42 enum_get_serialnum_string_desc_handle,
43 enum_set_configuration_handle,
44 enum_dev_configured_handle,
45 };
46
47 /* the enumeration state handle table */
48 state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE] =
49 {
50 /* the current state the current event the next state the event function */
51 {ENUM_IDLE, ENUM_EVENT_SET_ADDR, ENUM_SET_ADDR, only_state_move },
52 {ENUM_SET_ADDR, ENUN_EVENT_GET_FULL_DEV_DESC, ENUM_GET_FULL_DEV_DESC, only_state_move },
53 {ENUM_GET_FULL_DEV_DESC, ENUN_EVENT_GET_CFG_DESC, ENUM_GET_CFG_DESC, only_state_move },
54 {ENUM_GET_CFG_DESC, ENUN_EVENT_GET_FULL_CFG_DESC, ENUM_GET_FULL_CFG_DESC, only_state_move },
55 {ENUM_GET_FULL_CFG_DESC, ENUN_EVENT_GET_MFC_STRING_DESC, ENUM_GET_MFC_STRING_DESC, only_state_move },
56 {ENUM_GET_MFC_STRING_DESC, ENUN_EVENT_GET_PRODUCT_STRING_DESC, ENUM_GET_PRODUCT_STRING_DESC, only_state_move },
57 {ENUM_GET_PRODUCT_STRING_DESC, ENUN_EVENT_GET_SERIALNUM_STRING_DESC, ENUM_GET_SERIALNUM_STRING_DESC, only_state_move },
58 {ENUM_GET_SERIALNUM_STRING_DESC, ENUN_EVENT_SET_CONFIGURATION, ENUM_SET_CONFIGURATION, only_state_move },
59 {ENUM_SET_CONFIGURATION, ENUN_EVENT_DEV_CONFIGURED, ENUM_DEV_CONFIGURED, only_state_move },
60 {ENUM_DEV_CONFIGURED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
61 };
62
71 usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
72 {
73 usbh_status_enum exe_state = USBH_BUSY;
74 usbh_state_handle_struct *p_state;
75 p_state = (usbh_state_handle_struct *)pustate;
76
77 if (0U == enum_polling_handle_flag) {
78 enum_polling_handle_flag = 1U;
79 scd_table_push(p_state);
80 scd_state_move(p_state, ENUM_IDLE);
81 }
82
83 /* start the enumeration state handle */
84 scd_begin(p_state,ENUM_FSM_ID);
85
86 if (0 == p_state->usbh_current_state_stack_top) {
87 enum_state_handle[p_state->usbh_current_state](pudev, puhost, p_state);
88 } else {
89 enum_state_handle[p_state->stack[1].state](pudev, puhost, p_state);
90 }
91
92 /* determine the enumeration whether to complete */
93 if (ENUM_DEV_CONFIGURED == puhost->usbh_backup_state.enum_backup_state) {
94 puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE;
95 enum_polling_handle_flag = 0U;
96 exe_state = USBH_OK;
97 }
98
99 return exe_state;
100 }
101
110 static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
111 {
112 puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE;
113
114 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
115 usbh_enum_desc_get(pudev,
116 puhost,
117 pudev->host.rx_buffer,
118 USB_REQTYPE_DEVICE | USB_STANDARD_REQ,
119 USB_DEVDESC,
120 8U);
121 if ((void *)0 != pudev->mdelay) {
122 pudev->mdelay(100U);
123 }
124 }
125
126 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) {
127 usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, 8U);
128 puhost->control.ep0_size = puhost->device.dev_desc.bMaxPacketSize0;
129
130 /* issue reset */
131 usb_port_reset(pudev);
132
133 /* modify control channels configuration for maxpacket size */
134 usbh_channel_modify (pudev,
135 puhost->control.hc_out_num,
136 0U,
137 0U,
138 0U,
139 (uint16_t)puhost->control.ep0_size);
140
141 usbh_channel_modify (pudev,
142 puhost->control.hc_in_num,
143 0U,
144 0U,
145 0U,
146 (uint16_t)puhost->control.ep0_size);
147
148 scd_event_handle(pudev,
149 puhost,
150 pustate,
151 ENUM_EVENT_SET_ADDR,
152 pustate->usbh_current_state);
153 }
154 }
155
164 static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev,
165 usbh_host_struct *puhost,
166 usbh_state_handle_struct *pustate)
167 {
168 puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_DEV_DESC;
169
170 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
171 usbh_enum_desc_get(pudev,
172 puhost,
173 pudev->host.rx_buffer,
174 USB_REQTYPE_DEVICE | USB_STANDARD_REQ,
175 USB_DEVDESC,
176 USB_DEVDESC_SIZE);
177 }
178
179 if(USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){
180 usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, USB_DEVDESC_SIZE);
181 puhost->usr_cb->device_desc_available(&puhost->device.dev_desc);
182
183 scd_event_handle(pudev,
184 puhost,
185 pustate,
186 ENUN_EVENT_GET_CFG_DESC,
187 pustate->usbh_current_state);
188 }
189 }
190
199 static void enum_set_addr_handle (usb_core_handle_struct *pudev,
200 usbh_host_struct *puhost,
201 usbh_state_handle_struct *pustate)
202 {
203 puhost->usbh_backup_state.enum_backup_state = ENUM_SET_ADDR;
204
205 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
206 usbh_enum_addr_set(pudev, puhost,USBH_DEVICE_ADDRESS);
207 if ((void *)0 != pudev->mdelay) {
208 pudev->mdelay(100U);
209 }
210 }
211
212 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) {
213 if ((void *)0 != pudev->mdelay) {
214 pudev->mdelay(2U);
215 }
216 puhost->device.address = USBH_DEVICE_ADDRESS;
217
218 /* user callback for device address assigned */
219 puhost->usr_cb->device_address_set();
220
221 /* modify control channels to update device address */
222 usbh_channel_modify (pudev,
223 puhost->control.hc_in_num,
224 puhost->device.address,
225 0U,
226 0U,
227 0U);
228
229 usbh_channel_modify (pudev,
230 puhost->control.hc_out_num,
231 puhost->device.address,
232 0U,
233 0U,
234 0U);
235
236 scd_event_handle(pudev,
237 puhost,
238 pustate,
239 ENUN_EVENT_GET_FULL_DEV_DESC,
240 pustate->usbh_current_state);
241 }
242 }
243
252 static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev,
253 usbh_host_struct *puhost,
254 usbh_state_handle_struct *pustate)
255 {
256 uint16_t index = 0U;
257
258 puhost->usbh_backup_state.enum_backup_state = ENUM_GET_CFG_DESC;
259
260 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
261 usbh_enum_desc_get(pudev,
262 puhost,
263 pudev->host.rx_buffer,
264 USB_REQTYPE_DEVICE | USB_STANDARD_REQ,
265 USB_CFGDESC,
266 USB_CFGDESC_SIZE);
267 }
268
269 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) {
270 /* save configuration descriptor for class parsing usage */
271 for (; index < USB_CFGDESC_SIZE; index ++) {
272 usbh_cfg_desc[index] = pudev->host.rx_buffer[index];
273 }
274
275 /* commands successfully sent and response received */
276 usbh_cfg_desc_parse (&puhost->device.cfg_desc,
277 puhost->device.itf_desc,
278 puhost->device.ep_desc,
279 pudev->host.rx_buffer,
280 USB_CFGDESC_SIZE);
281
282 scd_event_handle(pudev,
283 puhost,
284 pustate,
285 ENUN_EVENT_GET_FULL_CFG_DESC,
286 pustate->usbh_current_state);
287 }
288 }
289
298 static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev,
299 usbh_host_struct *puhost,
300 usbh_state_handle_struct *pustate)
301 {
302
303 uint16_t index = 0U;
304
305 puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_CFG_DESC;
306
307 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
308 usbh_enum_desc_get (pudev, puhost, pudev->host.rx_buffer,
309 USB_REQTYPE_DEVICE | USB_STANDARD_REQ,
310 USB_CFGDESC, puhost->device.cfg_desc.wTotalLength);
311 }
312
313
314 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) {
315 /* save configuration descriptor for class parsing usage */
316 for (; index < puhost->device.cfg_desc.wTotalLength; index ++) {
317 usbh_cfg_desc[index] = pudev->host.rx_buffer[index];
318 }
319
320 /* commands successfully sent and response received */
321 usbh_cfg_desc_parse (&puhost->device.cfg_desc,
322 puhost->device.itf_desc,
323 puhost->device.ep_desc,
324 pudev->host.rx_buffer,
325 puhost->device.cfg_desc.wTotalLength);
326
327 /* User callback for configuration descriptors available */
328 puhost->usr_cb->configuration_desc_available(&puhost->device.cfg_desc,
329 puhost->device.itf_desc,
330 puhost->device.ep_desc[0]);
331
332 scd_event_handle(pudev,
333 puhost,
334 pustate,
335 ENUN_EVENT_GET_MFC_STRING_DESC,
336 pustate->usbh_current_state);
337 }
338 }
339
348 static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev,
349 usbh_host_struct *puhost,
350 usbh_state_handle_struct *pustate)
351 {
352 puhost->usbh_backup_state.enum_backup_state = ENUM_GET_MFC_STRING_DESC;
353
354 if (0U != puhost->device.dev_desc.iManufacturer) {
355 if(CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
356 usbh_enum_desc_get(pudev,
357 puhost,
358 pudev->host.rx_buffer,
359 USB_REQTYPE_DEVICE | USB_STANDARD_REQ,
360 USB_STRDESC | puhost->device.dev_desc.iManufacturer,
361 0xffU);
362 }
363
364 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) {
365 usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU);
366 puhost->usr_cb->manufacturer_string(local_buffer);
367
368 scd_event_handle(pudev,
369 puhost,
370 pustate,
371 ENUN_EVENT_GET_PRODUCT_STRING_DESC,
372 pustate->usbh_current_state);
373 }
374 } else {
375 puhost->usr_cb->manufacturer_string("N/A");
376 scd_state_move((usbh_state_handle_struct *)pustate, ENUM_GET_PRODUCT_STRING_DESC);
377 }
378 }
379
388 static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev,
389 usbh_host_struct *puhost,
390 usbh_state_handle_struct *pustate)
391 {
392 puhost->usbh_backup_state.enum_backup_state = ENUM_GET_PRODUCT_STRING_DESC;
393
394 if (0U != puhost->device.dev_desc.iProduct) {
395 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
396 usbh_enum_desc_get(pudev,
397 puhost,
398 pudev->host.rx_buffer,
399 USB_REQTYPE_DEVICE | USB_STANDARD_REQ,
400 USB_STRDESC | puhost->device.dev_desc.iProduct,
401 0xffU);
402 }
403
404 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) {
405 usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU);
406
407 /* user callback for product string */
408 puhost->usr_cb->product_string(local_buffer);
409
410 scd_event_handle(pudev,
411 puhost,
412 pustate,
413 ENUN_EVENT_GET_SERIALNUM_STRING_DESC,
414 pustate->usbh_current_state);
415 }
416 } else {
417 puhost->usr_cb->product_string("N/A");
418 scd_event_handle(pudev,
419 puhost,
420 pustate,
421 ENUN_EVENT_GET_SERIALNUM_STRING_DESC,
422 pustate->usbh_current_state);
423 }
424 }
425
434 static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev,
435 usbh_host_struct *puhost,
436 usbh_state_handle_struct *pustate)
437 {
438 puhost->usbh_backup_state.enum_backup_state = ENUM_GET_SERIALNUM_STRING_DESC;
439
440 if (0U != puhost->device.dev_desc.iSerialNumber) {
441 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) {
442 usbh_enum_desc_get(pudev,
443 puhost,
444 pudev->host.rx_buffer,
445 USB_REQTYPE_DEVICE | USB_STANDARD_REQ,
446 USB_STRDESC | puhost->device.dev_desc.iSerialNumber,
447 0xffU);
448 }
449
450 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){
451 usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU);
452
453 /* user callback for product string */
454 puhost->usr_cb->serial_num_string(local_buffer);
455 scd_event_handle(pudev,
456 puhost,
457 pustate,
458 ENUN_EVENT_SET_CONFIGURATION,
459 pustate->usbh_current_state);
460 }
461 } else {
462 puhost->usr_cb->serial_num_string("N/A");
463 scd_event_handle(pudev,
464 puhost,
465 pustate,
466 ENUN_EVENT_SET_CONFIGURATION,
467 pustate->usbh_current_state);
468 }
469 }
470
479 static void enum_set_configuration_handle (usb_core_handle_struct *pudev,
480 usbh_host_struct *puhost,
481 usbh_state_handle_struct *pustate)
482 {
483 puhost->usbh_backup_state.enum_backup_state = ENUM_SET_CONFIGURATION;
484
485 if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state ) {
486 usbh_enum_cfg_set(pudev, puhost, (uint16_t)puhost->device.cfg_desc.bConfigurationValue);
487 }
488
489 if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) {
490 scd_event_handle(pudev,
491 puhost,
492 pustate,
493 ENUN_EVENT_DEV_CONFIGURED,
494 pustate->usbh_current_state);
495 }
496 }
497
506 static void enum_dev_configured_handle (usb_core_handle_struct *pudev,
507 usbh_host_struct *puhost,
508 usbh_state_handle_struct *pustate)
509 {
510 puhost->usbh_backup_state.enum_backup_state = ENUM_DEV_CONFIGURED;
511 scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state);
512 }
513
525 void usbh_enum_desc_get(usb_core_handle_struct *pudev,
526 usbh_host_struct *puhost,
527 uint8_t *buf,
528 uint8_t req_type,
529 uint16_t value_idx,
530 uint16_t len)
531 {
532 usb_setup_union *pSetup = &(puhost->control.setup);
533
534 pSetup->b.bmRequestType = USB_DIR_IN | req_type;
535 pSetup->b.bRequest = USBREQ_GET_DESCRIPTOR;
536 pSetup->b.wValue = value_idx;
537
538 if (USB_STRDESC == (value_idx & 0xff00U)){
539 pSetup->b.wIndex = 0x0409U;
540 } else {
541 pSetup->b.wIndex = 0U;
542 }
543
544 pSetup->b.wLength = len;
545
546 puhost->control.buff = buf;
547 puhost->control.length = len;
548
549 }
550
559 void usbh_enum_addr_set(usb_core_handle_struct *pudev,
560 usbh_host_struct *puhost,
561 uint8_t device_address)
562 {
563 usb_setup_union *p_setup = &(puhost->control.setup);
564
565 p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ;
566 p_setup->b.bRequest = USBREQ_SET_ADDRESS;
567 p_setup->b.wValue = (uint16_t)device_address;
568 p_setup->b.wIndex = 0U;
569 p_setup->b.wLength = 0U;
570 puhost->control.buff = 0U;
571 puhost->control.length = 0U;
572 }
573
582 void usbh_enum_cfg_set(usb_core_handle_struct *pudev,
583 usbh_host_struct *puhost,
584 uint16_t cfg_idx)
585 {
586 usb_setup_union *p_setup = &(puhost->control.setup);
587
588 p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ;
589 p_setup->b.bRequest = USBREQ_SET_CONFIGURATION;
590 p_setup->b.wValue = cfg_idx;
591 p_setup->b.wIndex = 0U;
592 p_setup->b.wLength = 0U;
593 puhost->control.buff = 0;
594 puhost->control.length = 0U;
595 }
596
605 void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len)
606 {
607 dev_desc->Header.bLength = *(uint8_t *)(buf + 0);
608 dev_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
609 dev_desc->bcdUSB = SWAPBYTE(buf + 2);
610 dev_desc->bDeviceClass = *(uint8_t *)(buf + 4);
611 dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5);
612 dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6);
613 dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7);
614
615 if (len > 8U){
616 /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */
617 dev_desc->idVendor = SWAPBYTE(buf + 8);
618 dev_desc->idProduct = SWAPBYTE(buf + 10);
619 dev_desc->bcdDevice = SWAPBYTE(buf + 12);
620 dev_desc->iManufacturer = *(uint8_t *)(buf + 14);
621 dev_desc->iProduct = *(uint8_t *)(buf + 15);
622 dev_desc->iSerialNumber = *(uint8_t *)(buf + 16);
623 dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17);
624 }
625 }
626
637 void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc,
638 usb_descriptor_interface_struct *itf_desc,
639 usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM],
640 uint8_t *buf,
641 uint16_t len)
642 {
643 usb_descriptor_interface_struct *pitf = NULL;
644 usb_descriptor_interface_struct temp_pitf;
645 usb_descriptor_endpoint_struct *pep = NULL;
646 usb_descriptor_header_struct *pdesc = (usb_descriptor_header_struct *)buf;
647
648 uint8_t itf_ix = 0U;
649 uint8_t ep_ix = 0U;
650 uint16_t ptr = 0U;
651 static uint8_t prev_itf = 0U;
652 static uint16_t prev_ep_size = 0U;
653
654 /* parse configuration descriptor */
655 cfg_desc->Header.bLength = *(uint8_t *)(buf + 0);
656 cfg_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
657 cfg_desc->wTotalLength = SWAPBYTE(buf + 2);
658 cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4);
659 cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5);
660 cfg_desc->iConfiguration = *(uint8_t *)(buf + 6);
661 cfg_desc->bmAttributes = *(uint8_t *)(buf + 7);
662 cfg_desc->bMaxPower = *(uint8_t *)(buf + 8);
663
664 if (len > USB_CFGDESC_SIZE) {
665 ptr = USB_CFG_DESC_LEN;
666
667 if (cfg_desc->bNumInterfaces <= USBH_MAX_INTERFACES_NUM) {
668 pitf = (usb_descriptor_interface_struct *)0;
669
670 for (; ptr < cfg_desc->wTotalLength; ) {
671 pdesc = usbh_next_desc_get((uint8_t *)pdesc, &ptr);
672
673 if (USB_DESCTYPE_INTERFACE == pdesc->bDescriptorType) {
674 itf_ix = *((uint8_t *)pdesc + 2U);
675 pitf = &itf_desc[itf_ix];
676
677 if (*((uint8_t *)pdesc + 3U) < 3U) {
678 usbh_interface_desc_parse (&temp_pitf, (uint8_t *)pdesc);
679
680 /* parse endpoint descriptors relative to the current interface */
681 if (temp_pitf.bNumEndpoints <= USBH_MAX_EP_NUM) {
682 for (ep_ix = 0U; ep_ix < temp_pitf.bNumEndpoints;) {
683 pdesc = usbh_next_desc_get((void* )pdesc, &ptr);
684
685 if (USB_DESCTYPE_ENDPOINT == pdesc->bDescriptorType) {
686 pep = &ep_desc[itf_ix][ep_ix];
687
688 if (prev_itf != itf_ix) {
689 prev_itf = itf_ix;
690 usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf);
691 } else {
692 if (prev_ep_size > SWAPBYTE((uint8_t *)pdesc + 4)) {
693 break;
694 } else {
695 usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf);
696 }
697 }
698
699 usbh_endpoint_desc_parse (pep, (uint8_t *)pdesc);
700 prev_ep_size = SWAPBYTE((uint8_t *)pdesc + 4);
701 ep_ix++;
702 }
703 }
704 }
705 }
706 }
707 }
708 }
709
710 prev_ep_size = 0U;
711 prev_itf = 0U;
712 }
713 }
714
722 void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf)
723 {
724 itf_desc->Header.bLength = *(uint8_t *)(buf + 0);
725 itf_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
726 itf_desc->bInterfaceNumber = *(uint8_t *)(buf + 2);
727 itf_desc->bAlternateSetting = *(uint8_t *)(buf + 3);
728 itf_desc->bNumEndpoints = *(uint8_t *)(buf + 4);
729 itf_desc->bInterfaceClass = *(uint8_t *)(buf + 5);
730 itf_desc->bInterfaceSubClass = *(uint8_t *)(buf + 6);
731 itf_desc->bInterfaceProtocol = *(uint8_t *)(buf + 7);
732 itf_desc->iInterface = *(uint8_t *)(buf + 8);
733 }
734
742 void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf)
743 {
744 ep_desc->Header.bLength = *(uint8_t *)(buf + 0);
745 ep_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1);
746 ep_desc->bEndpointAddress = *(uint8_t *)(buf + 2);
747 ep_desc->bmAttributes = *(uint8_t *)(buf + 3);
748 ep_desc->wMaxPacketSize = SWAPBYTE(buf + 4);
749 ep_desc->bInterval = *(uint8_t *)(buf + 6);
750 }
751
760 void usbh_string_desc_parse (uint8_t* psrc, uint8_t* pdest, uint16_t len)
761 {
762 uint16_t strlength;
763 uint16_t idx;
764
765 /* the unicode string descriptor is not null-terminated. the string length is
766 computed by substracting two from the value of the first byte of the descriptor.
767 */
768
769 /* check which is lower size, the size of string or the length of bytes read from the device */
770
771 if (USB_DESCTYPE_STRING == psrc[1]){
772 /* make sure the descriptor is string type */
773
774 /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */
775 strlength = ((((uint16_t)psrc[0] - 2U) <= len) ? ((uint16_t)psrc[0] - 2U) : len);
776 psrc += 2; /* adjust the offset ignoring the string len and descriptor type */
777
778 for (idx = 0U; idx < strlength; idx += 2U) {
779 /* copy only the string and ignore the unicode id, hence add the src */
780 *pdest = psrc[idx];
781 pdest++;
782 }
783
784 *pdest = 0U; /* mark end of string */
785 }
786 }
787
795 usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr)
796 {
797 uint8_t len = ((usb_descriptor_header_struct *)pbuf)->bLength;
798
799 usb_descriptor_header_struct *pnext;
800
801 *ptr += len;
802
803 pnext = (usb_descriptor_header_struct *)((uint8_t *)pbuf + len);
804
805 return(pnext);
806 }
807
ENUM_DEV_CONFIGURED
Definition: usbh_core.h:90
usb_descriptor_interface_struct::bInterfaceProtocol
uint8_t bInterfaceProtocol
Definition: usb_std.h:166
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
USB_STRDESC
#define USB_STRDESC
Definition: usb_std.h:76
goto_up_state_fun
usbh_status_enum goto_up_state_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state
Definition: usbh_core.c:705
usb_descriptor_configuration_struct::bmAttributes
uint8_t bmAttributes
Definition: usb_std.h:153
usbh_core.h
header file for usbh_core.c
usbh_std.h
header file for usbh_std.c
ENUN_EVENT_GET_SERIALNUM_STRING_DESC
Definition: usbh_std.h:38
usb_descriptor_endpoint_struct::bmAttributes
uint8_t bmAttributes
Definition: usb_std.h:175
enum_polling_handle_flag
uint8_t enum_polling_handle_flag
Definition: usbh_std.c:19
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:116
usb_descriptor_device_struct::idProduct
uint16_t idProduct
Definition: usb_std.h:137
ctrl_state_polling_fun
usbh_status_enum ctrl_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of CTRL state
Definition: usbh_ctrl.c:72
usb_descriptor_interface_struct::iInterface
uint8_t iInterface
Definition: usb_std.h:167
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usb_std.h:30
usb_descriptor_configuration_struct::wTotalLength
uint16_t wTotalLength
Definition: usb_std.h:149
enum_handle_table
state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]
Definition: usbh_std.c:48
usbh_state_handle_struct
Definition: usbh_core.h:227
usbh_user_callback_struct::serial_num_string
void(* serial_num_string)(void *serial_string)
Definition: usbh_core.h:168
usbh_enum_addr_set
void usbh_enum_addr_set(usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address)
set address in usb host enumeration stage
Definition: usbh_std.c:559
ENUM_FSM_ID
#define ENUM_FSM_ID
Definition: usbh_core.h:39
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:213
usb_descriptor_configuration_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:147
ENUN_EVENT_DEV_CONFIGURED
Definition: usbh_std.h:40
backup_state_struct::ctrl_backup_state
ctrl_state_enum ctrl_backup_state
Definition: usbh_core.h:182
usbh_endpoint_desc_parse
void usbh_endpoint_desc_parse(usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf)
parse the endpoint descriptor
Definition: usbh_std.c:742
CTRL_IDLE
Definition: usbh_core.h:96
ENUM_IDLE
Definition: usbh_core.h:81
usbh_cfg_desc
uint8_t usbh_cfg_desc[512]
Definition: usbh_std.c:18
usbh_device_struct::ep_desc
usb_descriptor_endpoint_struct ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]
Definition: usbh_core.h:145
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:113
ENUN_EVENT_SET_CONFIGURATION
Definition: usbh_std.h:39
usb_descriptor_interface_struct::bNumEndpoints
uint8_t bNumEndpoints
Definition: usb_std.h:163
usbh_ctrl_struct::hc_in_num
uint8_t hc_in_num
Definition: usbh_core.h:127
usbh_user_callback_struct::product_string
void(* product_string)(void *prod_string)
Definition: usbh_core.h:167
USB_CFG_DESC_LEN
#define USB_CFG_DESC_LEN
Definition: usb_std.h:19
ENUM_GET_PRODUCT_STRING_DESC
Definition: usbh_core.h:87
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usb_std.h:123
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:133
usb_descriptor_interface_struct
Definition: usb_std.h:157
usb_descriptor_header_struct
Definition: usb_std.h:121
usb_descriptor_endpoint_struct::bEndpointAddress
uint8_t bEndpointAddress
Definition: usb_std.h:174
usb_descriptor_device_struct
Definition: usb_std.h:127
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:106
USBREQ_GET_DESCRIPTOR
#define USBREQ_GET_DESCRIPTOR
Definition: usb_std.h:46
usb_setup_union
Definition: usb_std.h:107
ENUM_GET_CFG_DESC
Definition: usbh_core.h:84
usbh_host_struct
Definition: usbh_core.h:188
usb_descriptor_device_struct::bcdUSB
uint16_t bcdUSB
Definition: usb_std.h:131
ENUN_EVENT_GET_PRODUCT_STRING_DESC
Definition: usbh_std.h:37
usbh_ctrl_struct::ep0_size
uint8_t ep0_size
Definition: usbh_core.h:129
usbh_cfg_desc_parse
void usbh_cfg_desc_parse(usb_descriptor_configuration_struct *cfg_desc, usb_descriptor_interface_struct *itf_desc, usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], uint8_t *buf, uint16_t len)
parse the configuration descriptor
Definition: usbh_std.c:637
usb_descriptor_interface_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:159
usbh_device_desc_parse
void usbh_device_desc_parse(usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len)
parse the device descriptor
Definition: usbh_std.c:605
ENUN_EVENT_GET_CFG_DESC
Definition: usbh_std.h:34
ENUN_EVENT_GET_FULL_CFG_DESC
Definition: usbh_std.h:35
USB_CFGDESC
#define USB_CFGDESC
Definition: usb_std.h:75
enum_state_polling_fun
usbh_status_enum enum_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of enumeration state
Definition: usbh_std.c:71
ENUN_EVENT_GET_MFC_STRING_DESC
Definition: usbh_std.h:36
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:217
usbh_host_struct::usr_cb
usbh_user_callback_struct * usr_cb
Definition: usbh_core.h:193
USB_DESCTYPE_STRING
#define USB_DESCTYPE_STRING
Definition: usb_std.h:57
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:117
backup_state_struct::enum_backup_state
enum_state_enum enum_backup_state
Definition: usbh_core.h:181
local_buffer
uint8_t local_buffer[64]
Definition: usbh_std.c:17
UP_STATE
#define UP_STATE
Definition: usbh_core.h:45
GO_TO_UP_STATE_EVENT
#define GO_TO_UP_STATE_EVENT
Definition: usbh_core.h:46
USB_DIR_OUT
#define USB_DIR_OUT
Definition: usb_std.h:26
USB_DEVDESC_SIZE
#define USB_DEVDESC_SIZE
Definition: usb_std.h:67
usbh_user_callback_struct::device_address_set
void(* device_address_set)(void)
Definition: usbh_core.h:159
usb_descriptor_interface_struct::bInterfaceClass
uint8_t bInterfaceClass
Definition: usb_std.h:164
usbh_ctrl.h
header file for usbh_ctrl.c
usbh_channel_modify
uint8_t usbh_channel_modify(usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
modify a channel
Definition: usbh_hcs.c:63
ENUN_EVENT_GET_FULL_DEV_DESC
Definition: usbh_std.h:33
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usb_std.h:85
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:561
enum_state_handle
void(* enum_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_std.c:33
usb_descriptor_device_struct::bDeviceProtocol
uint8_t bDeviceProtocol
Definition: usb_std.h:134
ENUM_SET_ADDR
Definition: usbh_core.h:82
usbh_interface_desc_parse
void usbh_interface_desc_parse(usb_descriptor_interface_struct *itf_desc, uint8_t *buf)
parse the interface descriptor
Definition: usbh_std.c:722
usb_descriptor_device_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:129
usb_descriptor_configuration_struct::bConfigurationValue
uint8_t bConfigurationValue
Definition: usb_std.h:151
usb_descriptor_endpoint_struct
Definition: usb_std.h:170
usbh_user_callback_struct::configuration_desc_available
void(* configuration_desc_available)(usb_descriptor_configuration_struct *cfg_desc, usb_descriptor_interface_struct *itf_desc, usb_descriptor_endpoint_struct *ep_desc)
Definition: usbh_core.h:161
usb_descriptor_device_struct::bcdDevice
uint16_t bcdDevice
Definition: usb_std.h:138
USBREQ_SET_CONFIGURATION
#define USBREQ_SET_CONFIGURATION
Definition: usb_std.h:49
usb_descriptor_device_struct::bDeviceSubClass
uint8_t bDeviceSubClass
Definition: usb_std.h:133
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:538
state_table_struct
Definition: usbh_core.h:202
usbh_string_desc_parse
void usbh_string_desc_parse(uint8_t *psrc, uint8_t *pdest, uint16_t len)
parse the string descriptor
Definition: usbh_std.c:760
USBH_DEVICE_ADDRESS
#define USBH_DEVICE_ADDRESS
Definition: usbh_core.h:25
usb_descriptor_interface_struct::bInterfaceSubClass
uint8_t bInterfaceSubClass
Definition: usb_std.h:165
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:233
scd_event_handle
usbh_status_enum scd_event_handle(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate, uint8_t event, uint8_t state)
state core driver event handle
Definition: usbh_core.c:576
usbh_host_struct::usbh_backup_state
backup_state_struct usbh_backup_state
Definition: usbh_core.h:190
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:115
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:622
usb_descriptor_device_struct::bNumberConfigurations
uint8_t bNumberConfigurations
Definition: usb_std.h:142
ENUM_SET_CONFIGURATION
Definition: usbh_core.h:89
usbh_device_struct::cfg_desc
usb_descriptor_configuration_struct cfg_desc
Definition: usbh_core.h:143
USB_DIR_IN
#define USB_DIR_IN
Definition: usb_std.h:27
usb_descriptor_interface_struct::bAlternateSetting
uint8_t bAlternateSetting
Definition: usb_std.h:162
USB_DESCTYPE_INTERFACE
#define USB_DESCTYPE_INTERFACE
Definition: usb_std.h:58
usbh_device_struct::address
uint8_t address
Definition: usbh_core.h:140
usbh_user_callback_struct::manufacturer_string
void(* manufacturer_string)(void *mfc_string)
Definition: usbh_core.h:166
usbh_next_desc_get
usb_descriptor_header_struct * usbh_next_desc_get(uint8_t *pbuf, uint16_t *ptr)
get the next descriptor header
Definition: usbh_std.c:795
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:131
usb_core_handle_struct
Definition: usb_core.h:200
usb_descriptor_endpoint_struct::wMaxPacketSize
uint16_t wMaxPacketSize
Definition: usb_std.h:176
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:234
USB_DEVDESC
#define USB_DEVDESC
Definition: usb_std.h:74
usb_descriptor_configuration_struct::bNumInterfaces
uint8_t bNumInterfaces
Definition: usb_std.h:150
usb_descriptor_endpoint_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:172
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:692
USB_CFGDESC_SIZE
#define USB_CFGDESC_SIZE
Definition: usb_std.h:68
usbh_user_callback_struct::device_desc_available
void(* device_desc_available)(void *devDesc)
Definition: usbh_core.h:158
usbh_host_struct::device
usbh_device_struct device
Definition: usbh_core.h:192
USB_REQTYPE_DEVICE
#define USB_REQTYPE_DEVICE
Definition: usb_std.h:36
USBH_OK
Definition: usbh_core.h:108
NULL
#define NULL
Definition: usb_defines.h:18
USBREQ_SET_ADDRESS
#define USBREQ_SET_ADDRESS
Definition: usb_std.h:45
ENUM_GET_FULL_CFG_DESC
Definition: usbh_core.h:85
usb_descriptor_configuration_struct::iConfiguration
uint8_t iConfiguration
Definition: usb_std.h:152
ENUM_GET_FULL_DEV_DESC
Definition: usbh_core.h:83
usb_descriptor_device_struct::idVendor
uint16_t idVendor
Definition: usb_std.h:136
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:114
ENUM_EVENT_SET_ADDR
Definition: usbh_std.h:32
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:191
ENUM_HANDLE_TABLE_SIZE
#define ENUM_HANDLE_TABLE_SIZE
Definition: usbh_std.h:23
usb_descriptor_interface_struct::bInterfaceNumber
uint8_t bInterfaceNumber
Definition: usb_std.h:161
ENUM_GET_MFC_STRING_DESC
Definition: usbh_core.h:86
usb_descriptor_device_struct::iProduct
uint8_t iProduct
Definition: usb_std.h:140
ENUM_GET_SERIALNUM_STRING_DESC
Definition: usbh_core.h:88
usbh_device_struct::dev_desc
usb_descriptor_device_struct dev_desc
Definition: usbh_core.h:142
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usb_std.h:124
usb_descriptor_device_struct::bDeviceClass
uint8_t bDeviceClass
Definition: usb_std.h:132
usbh_ctrl_struct::hc_out_num
uint8_t hc_out_num
Definition: usbh_core.h:128
usb_descriptor_device_struct::bMaxPacketSize0
uint8_t bMaxPacketSize0
Definition: usb_std.h:135
usb_descriptor_configuration_struct::bMaxPower
uint8_t bMaxPower
Definition: usb_std.h:154
usb_descriptor_device_struct::iManufacturer
uint8_t iManufacturer
Definition: usb_std.h:139
usbh_enum_cfg_set
void usbh_enum_cfg_set(usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx)
set configuration in usb host enumeration stage
Definition: usbh_std.c:582
usbh_enum_desc_get
void usbh_enum_desc_get(usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t *buf, uint8_t req_type, uint16_t value_idx, uint16_t len)
get descriptor in usb host enumeration stage
Definition: usbh_std.c:525
USBH_BUSY
Definition: usbh_core.h:109
usb_descriptor_endpoint_struct::bInterval
uint8_t bInterval
Definition: usb_std.h:177
usb_descriptor_device_struct::iSerialNumber
uint8_t iSerialNumber
Definition: usb_std.h:141
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:134
usb_descriptor_configuration_struct
Definition: usb_std.h:145
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
USB_DESCTYPE_ENDPOINT
#define USB_DESCTYPE_ENDPOINT
Definition: usb_std.h:59
usbh_device_struct::itf_desc
usb_descriptor_interface_struct itf_desc[USBH_MAX_INTERFACES_NUM]
Definition: usbh_core.h:144
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbd_std.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
usbd_std.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef USBD_STD_H
13 #define USBD_STD_H
14
15 #include "usb_std.h"
16 #include "usbd_core.h"
17 #include "usbd_conf.h"
18 #include <wchar.h>
19
20 #define USBD_LANGID_STR_IDX 0x00U
21 #define USBD_MFC_STR_IDX 0x01U
22 #define USBD_PRODUCT_STR_IDX 0x02U
23 #define USBD_SERIAL_STR_IDX 0x03U
24 #define USBD_CONFIG_STR_IDX 0x04U
25 #define USBD_INTERFACE_STR_IDX 0x05U
27 #define USB_STATUS_REMOTE_WAKEUP 0x02U
28 #define USB_STATUS_SELF_POWERED 0x01U
30 #define USB_FEATURE_ENDP_HALT 0x00U
31 #define USB_FEATURE_REMOTE_WAKEUP 0x01U
32 #define USB_FEATURE_TEST_MODE 0x02U
34 #define ENG_LANGID 0x0409U
35 #define CHN_LANGID 0x0804U
37 #define USB_DEVICE_DESC_SIZE 0x12U
39 #define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU))
40 #define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U))
42 #define USB_MIN(a, b) (((a) < (b)) ? (a) : (b))
44 #define WIDE_STRING(string) _WIDE_STRING(string)
45 #define _WIDE_STRING(string) L##string
46
47 #define USBD_STRING_DESC(string) \
48 (uint8_t *)&(struct { \
49 uint8_t _len; \
50 uint8_t _type; \
51 wchar_t _data[sizeof(string)]; \
52 }) { \
53 sizeof(WIDE_STRING(string)) + 2U - 2U, \
54 USB_DESCTYPE_STRING, \
55 WIDE_STRING(string) \
56 }
57
58 #define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U))
59
60 /* function declarations */
61 /* USB device setup transaction*/
62 usbd_status_enum usbd_setup_transaction (usb_core_handle_struct *pudev);
63 /* USB device out transaction*/
64 usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num);
65 /* USB device in transaction*/
66 usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num);
67 /* USB device enum error handle*/
68 void usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req);
69
70 #endif /* USBD_STD_H */
usb_device_req_struct
Definition: usb_core.h:114
usbd_setup_transaction
usbd_status_enum usbd_setup_transaction(usb_core_handle_struct *pudev)
USB setup stage processing.
Definition: usbd_std.c:69
usbd_status_enum
usbd_status_enum
Definition: usb_core.h:72
usbd_out_transaction
usbd_status_enum usbd_out_transaction(usb_core_handle_struct *pudev, uint8_t endp_num)
data out stage processing
Definition: usbd_std.c:103
usb_core_handle_struct
Definition: usb_core.h:200
usbd_in_transaction
usbd_status_enum usbd_in_transaction(usb_core_handle_struct *pudev, uint8_t endp_num)
data in stage processing
Definition: usbd_std.c:142
usbd_enum_error
void usbd_enum_error(usb_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB low level error event
Definition: usbd_std.c:688
usb_std.h
USB 2.0 standard defines.
usbd_core.h
USB device mode core driver header file.
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_spi.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_spi.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_spi.h"
13
14 #define SPI_INIT_MASK ((uint32_t)0x00003040U)
15 #define I2S_INIT_MASK ((uint32_t)0x0000F047U)
17 #define SPI_I2SPSC_RESET ((uint32_t)0x00000002U)
25 void spi_i2s_deinit(uint32_t spi_periph)
26 {
27 switch(spi_periph){
28 case SPI0:
29 /* reset SPI0 and I2S0 */
30 rcu_periph_reset_enable(RCU_SPI0RST);
31 rcu_periph_reset_disable(RCU_SPI0RST);
32 break;
33 case SPI1:
34 /* reset SPI1 */
35 rcu_periph_reset_enable(RCU_SPI1RST);
36 rcu_periph_reset_disable(RCU_SPI1RST);
37 break;
38 case SPI2:
39 /* reset SPI2 and I2S2 */
40 rcu_periph_reset_enable(RCU_SPI2RST);
41 rcu_periph_reset_disable(RCU_SPI2RST);
42 break;
43 default :
44 break;
45 }
46 }
47
65 void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct)
66 {
67 uint32_t reg = 0U;
68 reg = SPI_CTL0(spi_periph);
69 reg &= SPI_INIT_MASK;
70
71 /* select SPI as master or slave */
72 reg |= spi_struct->device_mode;
73 /* select SPI transfer mode */
74 reg |= spi_struct->trans_mode;
75 /* select SPI frame size */
76 reg |= spi_struct->frame_size;
77 /* select SPI NSS use hardware or software */
78 reg |= spi_struct->nss;
79 /* select SPI LSB or MSB */
80 reg |= spi_struct->endian;
81 /* select SPI polarity and phase */
82 reg |= spi_struct->clock_polarity_phase;
83 /* select SPI prescale to adjust transmit speed */
84 reg |= spi_struct->prescale;
85
86 /* write to SPI_CTL0 register */
87 SPI_CTL0(spi_periph) = (uint32_t)reg;
88
89 /* select SPI mode */
90 SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL);
91 }
92
99 void spi_enable(uint32_t spi_periph)
100 {
101 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN;
102 }
103
110 void spi_disable(uint32_t spi_periph)
111 {
112 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN);
113 }
114
115
116 #ifdef GD32F350
117
141 void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout)
142 {
143 uint32_t i2sdiv = 2U, i2sof = 0U;
144 uint32_t clks = 0U;
145 uint32_t i2sclock = 0U;
146
147 /* deinit SPI_I2SPSC register */
148 SPI_I2SPSC(spi_periph) = SPI_I2SPSC_RESET;
149
150 /* get system clock */
151 i2sclock = rcu_clock_freq_get(CK_SYS);
152
153 /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
154 if(I2S_MCKOUT_ENABLE == mckout){
155 clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample);
156 }else{
157 if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){
158 clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample);
159 }else{
160 clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample);
161 }
162 }
163
164 /* remove the floating point */
165 clks = (clks + 5U) / 10U;
166 i2sof = (clks & 0x00000001U);
167 i2sdiv = ((clks - i2sof) / 2U);
168 i2sof = (i2sof << 8U);
169
170 /* set the default values */
171 if((i2sdiv < 2U) || (i2sdiv > 255U)){
172 i2sdiv = 2U;
173 i2sof = 0U;
174 }
175
176 /* configure SPI_I2SPSC */
177 SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout);
178
179 /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */
180 SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN));
181 /* configure data frame format */
182 SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat;
183 }
184
205 void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl)
206 {
207 uint32_t reg = 0U;
208 reg = SPI_I2SCTL(spi_periph);
209 reg &= I2S_INIT_MASK;
210
211 /* enable I2S mode */
212 reg |= (uint32_t)SPI_I2SCTL_I2SSEL;
213 /* select I2S mode */
214 reg |= (uint32_t)mode;
215 /* select I2S standard */
216 reg |= (uint32_t)standard;
217 /* select I2S polarity */
218 reg |= (uint32_t)ckpl;
219
220 /* write to SPI_I2SCTL register */
221 SPI_I2SCTL(spi_periph) = (uint32_t)reg;
222 }
223
230 void i2s_enable(uint32_t spi_periph)
231 {
232 SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN;
233 }
234
241 void i2s_disable(uint32_t spi_periph)
242 {
243 SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN);
244 }
245
246 #endif /* GD32F350 */
247
254 void spi_nss_output_enable(uint32_t spi_periph)
255 {
256 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
257 }
258
265 void spi_nss_output_disable(uint32_t spi_periph)
266 {
267 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
268 }
269
276 void spi_nss_internal_high(uint32_t spi_periph)
277 {
278 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS;
279 }
280
287 void spi_nss_internal_low(uint32_t spi_periph)
288 {
289 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS);
290 }
291
301 void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
302 {
303 if(SPI_DMA_TRANSMIT == dma){
304 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
305 }else{
306 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
307 }
308 }
309
319 void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
320 {
321 if(SPI_DMA_TRANSMIT == dma){
322 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
323 }else{
324 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
325 }
326 }
327
337 void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format)
338 {
339 /* clear SPI_CTL0_FF16 bit */
340 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
341 /* confige SPI_CTL0_FF16 bit */
342 SPI_CTL0(spi_periph) |= (uint32_t)frame_format;
343 }
344
352 void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
353 {
354 SPI_DATA(spi_periph) = (uint32_t)data;
355 }
356
363 uint16_t spi_i2s_data_receive(uint32_t spi_periph)
364 {
365 return ((uint16_t)SPI_DATA(spi_periph));
366 }
367
376 void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
377 {
378 if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){
379 /* set the transmit only mode */
380 SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
381 }else{
382 /* set the receive only mode */
383 SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
384 }
385 }
386
398 void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
399 {
400 switch(interrupt){
401 /* SPI/I2S transmit buffer empty interrupt */
402 case SPI_I2S_INT_TBE:
403 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
404 break;
405 /* SPI/I2S receive buffer not empty interrupt */
406 case SPI_I2S_INT_RBNE:
407 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE;
408 break;
409 /* SPI/I2S error */
410 case SPI_I2S_INT_ERR:
411 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE;
412 break;
413 default:
414 break;
415 }
416 }
417
429 void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
430 {
431 switch(interrupt){
432 /* SPI/I2S transmit buffer empty interrupt */
433 case SPI_I2S_INT_TBE:
434 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
435 break;
436 /* SPI/I2S receive buffer not empty interrupt */
437 case SPI_I2S_INT_RBNE:
438 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
439 break;
440 /* SPI/I2S error */
441 case SPI_I2S_INT_ERR:
442 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
443 break;
444 default :
445 break;
446 }
447 }
448
463 FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
464 {
465 uint32_t reg1 = SPI_STAT(spi_periph);
466 uint32_t reg2 = SPI_CTL1(spi_periph);
467
468 switch(interrupt){
469 /* SPI/I2S transmit buffer empty interrupt */
470 case SPI_I2S_INT_FLAG_TBE:
471 reg1 = reg1 & SPI_STAT_TBE;
472 reg2 = reg2 & SPI_CTL1_TBEIE;
473 break;
474 /* SPI/I2S receive buffer not empty interrupt */
475 case SPI_I2S_INT_FLAG_RBNE:
476 reg1 = reg1 & SPI_STAT_RBNE;
477 reg2 = reg2 & SPI_CTL1_RBNEIE;
478 break;
479 /* SPI/I2S overrun interrupt */
480 case SPI_I2S_INT_FLAG_RXORERR:
481 reg1 = reg1 & SPI_STAT_RXORERR;
482 reg2 = reg2 & SPI_CTL1_ERRIE;
483 break;
484 /* SPI config error interrupt */
485 case SPI_INT_FLAG_CONFERR:
486 reg1 = reg1 & SPI_STAT_CONFERR;
487 reg2 = reg2 & SPI_CTL1_ERRIE;
488 break;
489 /* SPI CRC error interrupt */
490 case SPI_INT_FLAG_CRCERR:
491 reg1 = reg1 & SPI_STAT_CRCERR;
492 reg2 = reg2 & SPI_CTL1_ERRIE;
493 break;
494 /* I2S underrun error interrupt */
495 case I2S_INT_FLAG_TXURERR:
496 reg1 = reg1 & SPI_STAT_TXURERR;
497 reg2 = reg2 & SPI_CTL1_ERRIE;
498 break;
499 /* SPI/I2S format error interrupt */
500 case SPI_I2S_INT_FLAG_FERR:
501 reg1 = reg1 & SPI_STAT_FERR;
502 reg2 = reg2 & SPI_CTL1_ERRIE;
503 break;
504 default :
505 break;
506 }
507 /*get SPI/I2S interrupt flag status */
508 if(reg1 && reg2){
509 return SET;
510 }else{
511 return RESET;
512 }
513 }
514
536 FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
537 {
538 if(SPI_STAT(spi_periph) & flag){
539 return SET;
540 }else{
541 return RESET;
542 }
543 }
544
551 void spi_crc_error_clear(uint32_t spi_periph)
552 {
553 SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR);
554 }
555
562 void spi_crc_on(uint32_t spi_periph)
563 {
564 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
565 }
566
573 void spi_crc_off(uint32_t spi_periph)
574 {
575 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
576 }
577
585 void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly)
586 {
587 /* set SPI CRC polynomial */
588 SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
589 }
590
597 uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
598 {
599 return ((uint16_t)SPI_CRCPOLY(spi_periph));
600 }
601
608 void spi_crc_next(uint32_t spi_periph)
609 {
610 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
611 }
612
622 uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
623 {
624 if(SPI_CRC_TX == crc){
625 return ((uint16_t)(SPI_TCRC(spi_periph)));
626 }else{
627 return ((uint16_t)(SPI_RCRC(spi_periph)));
628 }
629 }
630
637 void spi_ti_mode_enable(uint32_t spi_periph)
638 {
639 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD;
640 }
641
648 void spi_ti_mode_disable(uint32_t spi_periph)
649 {
650 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD);
651 }
652
659 void spi_nssp_mode_enable(uint32_t spi_periph)
660 {
661 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP;
662 }
663
670 void spi_nssp_mode_disable(uint32_t spi_periph)
671 {
672 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP);
673 }
674
681 void qspi_enable(uint32_t spi_periph)
682 {
683 SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD;
684 }
685
692 void qspi_disable(uint32_t spi_periph)
693 {
694 SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD);
695 }
696
703 void qspi_write_enable(uint32_t spi_periph)
704 {
705 SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD);
706 }
707
714 void qspi_read_enable(uint32_t spi_periph)
715 {
716 SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD;
717 }
718
725 void qspi_io23_output_enable(uint32_t spi_periph)
726 {
727 SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV;
728 }
729
736 void qspi_io23_output_disable(uint32_t spi_periph)
737 {
738 SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV);
739 }
SPI_I2S_INT_ERR
#define SPI_I2S_INT_ERR
Definition: gd32f3x0_spi.h:214
SPI_CTL1_NSSP
#define SPI_CTL1_NSSP
Definition: gd32f3x0_spi.h:55
spi_crc_off
void spi_crc_off(uint32_t spi_periph)
turn off CRC function
Definition: gd32f3x0_spi.c:573
spi_enable
void spi_enable(uint32_t spi_periph)
enable SPI
Definition: gd32f3x0_spi.c:99
SPI_FLAG_CRCERR
#define SPI_FLAG_CRCERR
Definition: gd32f3x0_spi.h:228
spi_nss_output_enable
void spi_nss_output_enable(uint32_t spi_periph)
enable SPI NSS output
Definition: gd32f3x0_spi.c:254
SPI_QCTL
#define SPI_QCTL(spix)
Definition: gd32f3x0_spi.h:32
spi_crc_on
void spi_crc_on(uint32_t spi_periph)
turn on CRC function
Definition: gd32f3x0_spi.c:562
spi_parameter_struct::nss
uint32_t nss
Definition: gd32f3x0_spi.h:111
qspi_io23_output_enable
void qspi_io23_output_enable(uint32_t spi_periph)
enable SPI_IO2 and SPI_IO3 pin output
Definition: gd32f3x0_spi.c:725
SPI1
#define SPI1
Definition: gd32f3x0_spi.h:19
spi_nss_internal_low
void spi_nss_internal_low(uint32_t spi_periph)
SPI NSS pin low level in software mode.
Definition: gd32f3x0_spi.c:287
spi_parameter_struct::device_mode
uint32_t device_mode
Definition: gd32f3x0_spi.h:108
spi_bidirectional_transfer_config
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
configure SPI bidirectional transfer direction
Definition: gd32f3x0_spi.c:376
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
SPI_CTL1_TMOD
#define SPI_CTL1_TMOD
Definition: gd32f3x0_spi.h:56
spi_i2s_data_receive
uint16_t spi_i2s_data_receive(uint32_t spi_periph)
SPI receive data.
Definition: gd32f3x0_spi.c:363
SPI_STAT_CONFERR
#define SPI_STAT_CONFERR
Definition: gd32f3x0_spi.h:67
SPI_CTL1_ERRIE
#define SPI_CTL1_ERRIE
Definition: gd32f3x0_spi.h:57
SPI_CTL1
#define SPI_CTL1(spix)
Definition: gd32f3x0_spi.h:24
SPI_STAT_TBE
#define SPI_STAT_TBE
Definition: gd32f3x0_spi.h:63
SPI_I2S_INT_RBNE
#define SPI_I2S_INT_RBNE
Definition: gd32f3x0_spi.h:213
SPI_RCRC
#define SPI_RCRC(spix)
Definition: gd32f3x0_spi.h:28
spi_i2s_data_frame_format_config
void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format)
configure SPI/I2S data frame format
Definition: gd32f3x0_spi.c:337
SPI_STAT
#define SPI_STAT(spix)
Definition: gd32f3x0_spi.h:25
spi_parameter_struct::frame_size
uint32_t frame_size
Definition: gd32f3x0_spi.h:110
SPI_QCTL_QMOD
#define SPI_QCTL_QMOD
Definition: gd32f3x0_spi.h:100
SPI_CTL0_CRCEN
#define SPI_CTL0_CRCEN
Definition: gd32f3x0_spi.h:47
CK_SYS
Definition: gd32f3x0_rcu.h:454
spi_crc_polynomial_get
uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
get SPI CRC polynomial
Definition: gd32f3x0_spi.c:597
SPI_CTL1_NSSDRV
#define SPI_CTL1_NSSDRV
Definition: gd32f3x0_spi.h:54
SPI_I2S_INT_FLAG_RBNE
#define SPI_I2S_INT_FLAG_RBNE
Definition: gd32f3x0_spi.h:218
SPI_INT_FLAG_CONFERR
#define SPI_INT_FLAG_CONFERR
Definition: gd32f3x0_spi.h:220
spi_i2s_interrupt_disable
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
disable SPI and I2S interrupt
Definition: gd32f3x0_spi.c:429
spi_parameter_struct::trans_mode
uint32_t trans_mode
Definition: gd32f3x0_spi.h:109
SPI_I2SPSC_RESET
#define SPI_I2SPSC_RESET
Definition: gd32f3x0_spi.c:17
SPI_CTL0_SWNSS
#define SPI_CTL0_SWNSS
Definition: gd32f3x0_spi.h:42
SPI_I2S_INT_FLAG_TBE
#define SPI_I2S_INT_FLAG_TBE
Definition: gd32f3x0_spi.h:217
RCU_SPI0RST
Definition: gd32f3x0_rcu.h:337
SPI_STAT_CRCERR
#define SPI_STAT_CRCERR
Definition: gd32f3x0_spi.h:66
SPI0
#define SPI0
Definition: gd32f3x0_spi.h:18
SPI_CTL1_TBEIE
#define SPI_CTL1_TBEIE
Definition: gd32f3x0_spi.h:59
spi_ti_mode_disable
void spi_ti_mode_disable(uint32_t spi_periph)
disable SPI TI mode
Definition: gd32f3x0_spi.c:648
SPI2
#define SPI2
Definition: gd32f3x0_spi.h:20
SPI_I2SCTL_CHLEN
#define SPI_I2SCTL_CHLEN
Definition: gd32f3x0_spi.h:85
SPI_STAT_RBNE
#define SPI_STAT_RBNE
Definition: gd32f3x0_spi.h:62
SPI_INIT_MASK
#define SPI_INIT_MASK
Definition: gd32f3x0_spi.c:14
spi_crc_next
void spi_crc_next(uint32_t spi_periph)
SPI next data is CRC value.
Definition: gd32f3x0_spi.c:608
spi_crc_polynomial_set
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly)
set CRC polynomial
Definition: gd32f3x0_spi.c:585
SPI_I2SCTL_I2SSEL
#define SPI_I2SCTL_I2SSEL
Definition: gd32f3x0_spi.h:92
spi_dma_disable
void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
disable SPI DMA send or receive
Definition: gd32f3x0_spi.c:319
SPI_DATA
#define SPI_DATA(spix)
Definition: gd32f3x0_spi.h:26
qspi_disable
void qspi_disable(uint32_t spi_periph)
disable quad wire SPI
Definition: gd32f3x0_spi.c:692
SPI_CTL0_SPIEN
#define SPI_CTL0_SPIEN
Definition: gd32f3x0_spi.h:40
spi_i2s_flag_get
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
get SPI and I2S flag status
Definition: gd32f3x0_spi.c:536
spi_i2s_interrupt_enable
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
enable SPI and I2S interrupt
Definition: gd32f3x0_spi.c:398
SPI_CTL1_DMATEN
#define SPI_CTL1_DMATEN
Definition: gd32f3x0_spi.h:53
spi_parameter_struct::endian
uint32_t endian
Definition: gd32f3x0_spi.h:112
qspi_io23_output_disable
void qspi_io23_output_disable(uint32_t spi_periph)
disable SPI_IO2 and SPI_IO3 pin output
Definition: gd32f3x0_spi.c:736
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
SPI_QCTL_QRD
#define SPI_QCTL_QRD
Definition: gd32f3x0_spi.h:101
spi_parameter_struct
Definition: gd32f3x0_spi.h:106
spi_ti_mode_enable
void spi_ti_mode_enable(uint32_t spi_periph)
enable SPI TI mode
Definition: gd32f3x0_spi.c:637
SPI_I2S_INT_FLAG_FERR
#define SPI_I2S_INT_FLAG_FERR
Definition: gd32f3x0_spi.h:223
SPI_CTL0_CRCNT
#define SPI_CTL0_CRCNT
Definition: gd32f3x0_spi.h:46
SPI_I2S_INT_FLAG_RXORERR
#define SPI_I2S_INT_FLAG_RXORERR
Definition: gd32f3x0_spi.h:219
SPI_INT_FLAG_CRCERR
#define SPI_INT_FLAG_CRCERR
Definition: gd32f3x0_spi.h:221
RCU_SPI1RST
Definition: gd32f3x0_rcu.h:348
spi_nss_internal_high
void spi_nss_internal_high(uint32_t spi_periph)
SPI NSS pin high level in software mode.
Definition: gd32f3x0_spi.c:276
SPI_CRCPOLY
#define SPI_CRCPOLY(spix)
Definition: gd32f3x0_spi.h:27
SPI_BIDIRECTIONAL_RECEIVE
#define SPI_BIDIRECTIONAL_RECEIVE
Definition: gd32f3x0_spi.h:158
gd32f3x0_spi.h
definitions for the SPI
spi_crc_error_clear
void spi_crc_error_clear(uint32_t spi_periph)
clear SPI CRC error flag status
Definition: gd32f3x0_spi.c:551
SPI_CTL0_FF16
#define SPI_CTL0_FF16
Definition: gd32f3x0_spi.h:45
I2S_INIT_MASK
#define I2S_INIT_MASK
Definition: gd32f3x0_spi.c:15
spi_i2s_data_transmit
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
SPI transmit data.
Definition: gd32f3x0_spi.c:352
SPI_I2SCTL_I2SEN
#define SPI_I2SCTL_I2SEN
Definition: gd32f3x0_spi.h:91
spi_i2s_interrupt_flag_get
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
get SPI and I2S interrupt flag status
Definition: gd32f3x0_spi.c:463
I2S_INT_FLAG_TXURERR
#define I2S_INT_FLAG_TXURERR
Definition: gd32f3x0_spi.h:222
spi_nss_output_disable
void spi_nss_output_disable(uint32_t spi_periph)
disable SPI NSS output
Definition: gd32f3x0_spi.c:265
SPI_I2SCTL_DTLEN
#define SPI_I2SCTL_DTLEN
Definition: gd32f3x0_spi.h:86
spi_parameter_struct::clock_polarity_phase
uint32_t clock_polarity_phase
Definition: gd32f3x0_spi.h:113
SPI_I2SPSC
#define SPI_I2SPSC(spix)
Definition: gd32f3x0_spi.h:31
SPI_DMA_TRANSMIT
#define SPI_DMA_TRANSMIT
Definition: gd32f3x0_spi.h:204
SPI_CTL0
#define SPI_CTL0(spix)
Definition: gd32f3x0_spi.h:23
SPI_I2S_INT_TBE
#define SPI_I2S_INT_TBE
Definition: gd32f3x0_spi.h:212
spi_init
void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct)
initialize SPI parameter
Definition: gd32f3x0_spi.c:65
spi_dma_enable
void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
enable SPI DMA send or receive
Definition: gd32f3x0_spi.c:301
spi_nssp_mode_enable
void spi_nssp_mode_enable(uint32_t spi_periph)
enable SPI NSS pulse mode
Definition: gd32f3x0_spi.c:659
SPI_CRC_TX
#define SPI_CRC_TX
Definition: gd32f3x0_spi.h:208
SPI_CTL1_DMAREN
#define SPI_CTL1_DMAREN
Definition: gd32f3x0_spi.h:52
SPI_STAT_TXURERR
#define SPI_STAT_TXURERR
Definition: gd32f3x0_spi.h:65
SPI_STAT_FERR
#define SPI_STAT_FERR
Definition: gd32f3x0_spi.h:70
qspi_read_enable
void qspi_read_enable(uint32_t spi_periph)
enable quad wire SPI read
Definition: gd32f3x0_spi.c:714
SPI_BIDIRECTIONAL_TRANSMIT
#define SPI_BIDIRECTIONAL_TRANSMIT
Definition: gd32f3x0_spi.h:157
RCU_SPI2RST
Definition: gd32f3x0_rcu.h:349
SPI_I2SCTL
#define SPI_I2SCTL(spix)
Definition: gd32f3x0_spi.h:30
spi_disable
void spi_disable(uint32_t spi_periph)
disable SPI
Definition: gd32f3x0_spi.c:110
spi_parameter_struct::prescale
uint32_t prescale
Definition: gd32f3x0_spi.h:114
SPI_QCTL_IO23_DRV
#define SPI_QCTL_IO23_DRV
Definition: gd32f3x0_spi.h:102
qspi_enable
void qspi_enable(uint32_t spi_periph)
enable quad wire SPI
Definition: gd32f3x0_spi.c:681
qspi_write_enable
void qspi_write_enable(uint32_t spi_periph)
enable quad wire SPI write
Definition: gd32f3x0_spi.c:703
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f3x0_rcu.c:964
SPI_TCRC
#define SPI_TCRC(spix)
Definition: gd32f3x0_spi.h:29
SPI_CTL1_RBNEIE
#define SPI_CTL1_RBNEIE
Definition: gd32f3x0_spi.h:58
spi_nssp_mode_disable
void spi_nssp_mode_disable(uint32_t spi_periph)
disable SPI NSS pulse mode
Definition: gd32f3x0_spi.c:670
SPI_STAT_RXORERR
#define SPI_STAT_RXORERR
Definition: gd32f3x0_spi.h:68
spi_crc_get
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
get SPI CRC send value or receive value
Definition: gd32f3x0_spi.c:622
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_misc.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_misc.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_MISC_H
13 #define GD32F3X0_MISC_H
14
15 #include "gd32f3x0.h"
16
17 /* constants definitions */
18 /* set the RAM and FLASH base address */
19 #define NVIC_VECTTAB_RAM ((uint32_t)0x20000000)
20 #define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000)
22 /* set the NVIC vector table offset mask */
23 #define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80)
25 /* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
26 #define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
28 /* priority group - define the pre-emption priority and the subpriority */
29 #define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700)
30 #define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600)
31 #define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500)
32 #define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400)
33 #define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300)
35 /* choose the method to enter or exit the lowpower mode */
36 #define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)
37 #define SCB_SCR_SLEEPDEEP ((uint8_t)0x04)
38 #define SCB_SCR_SEVONPEND ((uint8_t)0x10)
40 #define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT
41 #define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP
42 #define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND
44 /* choose the systick clock source */
45 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU)
46 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
48 /* function declarations */
49 /* set the priority group */
50 void nvic_priority_group_set(uint32_t nvic_prigroup);
51
52 /* enable NVIC request */
53 void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
54 /* disable NVIC request */
55 void nvic_irq_disable(uint8_t nvic_irq);
56
57 /* set the NVIC vector table base address */
58 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
59
60 /* set the state of the low power mode */
61 void system_lowpower_set(uint8_t lowpower_mode);
62 /* reset the state of the low power mode */
63 void system_lowpower_reset(uint8_t lowpower_mode);
64
65 /* set the systick clock source */
66 void systick_clksource_set(uint32_t systick_clksource);
67
68 #endif /* GD32F3X0_MISC_H */
nvic_irq_enable
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority)
enable NVIC request
Definition: gd32f3x0_misc.c:39
system_lowpower_reset
void system_lowpower_reset(uint8_t lowpower_mode)
reset the state of the low power mode
Definition: gd32f3x0_misc.c:134
system_lowpower_set
void system_lowpower_set(uint8_t lowpower_mode)
set the state of the low power mode
Definition: gd32f3x0_misc.c:118
nvic_vector_table_set
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
set the NVIC vector table base address
Definition: gd32f3x0_misc.c:102
nvic_irq_disable
void nvic_irq_disable(uint8_t nvic_irq)
disable NVIC request
Definition: gd32f3x0_misc.c:87
nvic_priority_group_set
void nvic_priority_group_set(uint32_t nvic_prigroup)
set the priority group
Definition: gd32f3x0_misc.c:25
systick_clksource_set
void systick_clksource_set(uint32_t systick_clksource)
set the systick clock source
Definition: gd32f3x0_misc.c:148
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_timer.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_TIMER_H
13 #define GD32F3X0_TIMER_H
14
15 #include "gd32f3x0.h"
16
17 /* TIMERx(x=0,1,2,5,13..16) definitions */
18 #define TIMER0 (TIMER_BASE + 0x00012C00U)
19 #define TIMER1 (TIMER_BASE + 0x00000000U)
20 #define TIMER2 (TIMER_BASE + 0x00000400U)
21 #ifdef GD32F350
22 #define TIMER5 (TIMER_BASE + 0x00001000U)
23 #endif
24 #define TIMER13 (TIMER_BASE + 0x00002000U)
25 #define TIMER14 (TIMER_BASE + 0x00014000U)
26 #define TIMER15 (TIMER_BASE + 0x00014400U)
27 #define TIMER16 (TIMER_BASE + 0x00014800U)
28
29 /* registers definitions */
30 #define TIMER_CTL0(timerx) REG32((timerx) + 0x00U)
31 #define TIMER_CTL1(timerx) REG32((timerx) + 0x04U)
32 #define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U)
33 #define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU)
34 #define TIMER_INTF(timerx) REG32((timerx) + 0x10U)
35 #define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U)
36 #define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U)
37 #define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU)
38 #define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U)
39 #define TIMER_CNT(timerx) REG32((timerx) + 0x24U)
40 #define TIMER_PSC(timerx) REG32((timerx) + 0x28U)
41 #define TIMER_CAR(timerx) REG32((timerx) + 0x2CU)
42 #define TIMER_CREP(timerx) REG32((timerx) + 0x30U)
43 #define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U)
44 #define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U)
45 #define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU)
46 #define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U)
47 #define TIMER_CCHP(timerx) REG32((timerx) + 0x44U)
48 #define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U)
49 #define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU)
50 #define TIMER_IRMP(timerx) REG32((timerx) + 0x50U)
51 #define TIMER_CFG(timerx) REG32((timerx) + 0xFCU)
53 /* bits definitions */
54 /* TIMER_CTL0 */
55 #define TIMER_CTL0_CEN BIT(0)
56 #define TIMER_CTL0_UPDIS BIT(1)
57 #define TIMER_CTL0_UPS BIT(2)
58 #define TIMER_CTL0_SPM BIT(3)
59 #define TIMER_CTL0_DIR BIT(4)
60 #define TIMER_CTL0_CAM BITS(5,6)
61 #define TIMER_CTL0_ARSE BIT(7)
62 #define TIMER_CTL0_CKDIV BITS(8,9)
64 /* TIMER_CTL1 */
65 #define TIMER_CTL1_CCSE BIT(0)
66 #define TIMER_CTL1_CCUC BIT(2)
67 #define TIMER_CTL1_DMAS BIT(3)
68 #define TIMER_CTL1_MMC BITS(4,6)
69 #define TIMER_CTL1_TI0S BIT(7)
70 #define TIMER_CTL1_ISO0 BIT(8)
71 #define TIMER_CTL1_ISO0N BIT(9)
72 #define TIMER_CTL1_ISO1 BIT(10)
73 #define TIMER_CTL1_ISO1N BIT(11)
74 #define TIMER_CTL1_ISO2 BIT(12)
75 #define TIMER_CTL1_ISO2N BIT(13)
76 #define TIMER_CTL1_ISO3 BIT(14)
78 /* TIMER_SMCFG */
79 #define TIMER_SMCFG_SMC BITS(0,2)
80 #define TIMER_SMCFG_OCRC BIT(3)
81 #define TIMER_SMCFG_TRGS BITS(4,6)
82 #define TIMER_SMCFG_MSM BIT(7)
83 #define TIMER_SMCFG_ETFC BITS(8,11)
84 #define TIMER_SMCFG_ETPSC BITS(12,13)
85 #define TIMER_SMCFG_SMC1 BIT(14)
86 #define TIMER_SMCFG_ETP BIT(15)
88 /* TIMER_DMAINTEN */
89 #define TIMER_DMAINTEN_UPIE BIT(0)
90 #define TIMER_DMAINTEN_CH0IE BIT(1)
91 #define TIMER_DMAINTEN_CH1IE BIT(2)
92 #define TIMER_DMAINTEN_CH2IE BIT(3)
93 #define TIMER_DMAINTEN_CH3IE BIT(4)
94 #define TIMER_DMAINTEN_CMTIE BIT(5)
95 #define TIMER_DMAINTEN_TRGIE BIT(6)
96 #define TIMER_DMAINTEN_BRKIE BIT(7)
97 #define TIMER_DMAINTEN_UPDEN BIT(8)
98 #define TIMER_DMAINTEN_CH0DEN BIT(9)
99 #define TIMER_DMAINTEN_CH1DEN BIT(10)
100 #define TIMER_DMAINTEN_CH2DEN BIT(11)
101 #define TIMER_DMAINTEN_CH3DEN BIT(12)
102 #define TIMER_DMAINTEN_CMTDEN BIT(13)
103 #define TIMER_DMAINTEN_TRGDEN BIT(14)
105 /* TIMER_INTF */
106 #define TIMER_INTF_UPIF BIT(0)
107 #define TIMER_INTF_CH0IF BIT(1)
108 #define TIMER_INTF_CH1IF BIT(2)
109 #define TIMER_INTF_CH2IF BIT(3)
110 #define TIMER_INTF_CH3IF BIT(4)
111 #define TIMER_INTF_CMTIF BIT(5)
112 #define TIMER_INTF_TRGIF BIT(6)
113 #define TIMER_INTF_BRKIF BIT(7)
114 #define TIMER_INTF_CH0OF BIT(9)
115 #define TIMER_INTF_CH1OF BIT(10)
116 #define TIMER_INTF_CH2OF BIT(11)
117 #define TIMER_INTF_CH3OF BIT(12)
119 /* TIMER_SWEVG */
120 #define TIMER_SWEVG_UPG BIT(0)
121 #define TIMER_SWEVG_CH0G BIT(1)
122 #define TIMER_SWEVG_CH1G BIT(2)
123 #define TIMER_SWEVG_CH2G BIT(3)
124 #define TIMER_SWEVG_CH3G BIT(4)
125 #define TIMER_SWEVG_CMTG BIT(5)
126 #define TIMER_SWEVG_TRGG BIT(6)
127 #define TIMER_SWEVG_BRKG BIT(7)
129 /* TIMER_CHCTL0 */
130 /* output compare mode */
131 #define TIMER_CHCTL0_CH0MS BITS(0,1)
132 #define TIMER_CHCTL0_CH0COMFEN BIT(2)
133 #define TIMER_CHCTL0_CH0COMSEN BIT(3)
134 #define TIMER_CHCTL0_CH0COMCTL BITS(4,6)
135 #define TIMER_CHCTL0_CH0COMCEN BIT(7)
136 #define TIMER_CHCTL0_CH1MS BITS(8,9)
137 #define TIMER_CHCTL0_CH1COMFEN BIT(10)
138 #define TIMER_CHCTL0_CH1COMSEN BIT(11)
139 #define TIMER_CHCTL0_CH1COMCTL BITS(12,14)
140 #define TIMER_CHCTL0_CH1COMCEN BIT(15)
141 /* input capture mode */
142 #define TIMER_CHCTL0_CH0CAPPSC BITS(2,3)
143 #define TIMER_CHCTL0_CH0CAPFLT BITS(4,7)
144 #define TIMER_CHCTL0_CH1CAPPSC BITS(10,11)
145 #define TIMER_CHCTL0_CH1CAPFLT BITS(12,15)
147 /* TIMER_CHCTL1 */
148 /* output compare mode */
149 #define TIMER_CHCTL1_CH2MS BITS(0,1)
150 #define TIMER_CHCTL1_CH2COMFEN BIT(2)
151 #define TIMER_CHCTL1_CH2COMSEN BIT(3)
152 #define TIMER_CHCTL1_CH2COMCTL BITS(4,6)
153 #define TIMER_CHCTL1_CH2COMCEN BIT(7)
154 #define TIMER_CHCTL1_CH3MS BITS(8,9)
155 #define TIMER_CHCTL1_CH3COMFEN BIT(10)
156 #define TIMER_CHCTL1_CH3COMSEN BIT(11)
157 #define TIMER_CHCTL1_CH3COMCTL BITS(12,14)
158 #define TIMER_CHCTL1_CH3COMCEN BIT(15)
159 /* input capture mode */
160 #define TIMER_CHCTL1_CH2CAPPSC BITS(2,3)
161 #define TIMER_CHCTL1_CH2CAPFLT BITS(4,7)
162 #define TIMER_CHCTL1_CH3CAPPSC BITS(10,11)
163 #define TIMER_CHCTL1_CH3CAPFLT BITS(12,15)
165 /* TIMER_CHCTL2 */
166 #define TIMER_CHCTL2_CH0EN BIT(0)
167 #define TIMER_CHCTL2_CH0P BIT(1)
168 #define TIMER_CHCTL2_CH0NEN BIT(2)
169 #define TIMER_CHCTL2_CH0NP BIT(3)
170 #define TIMER_CHCTL2_CH1EN BIT(4)
171 #define TIMER_CHCTL2_CH1P BIT(5)
172 #define TIMER_CHCTL2_CH1NEN BIT(6)
173 #define TIMER_CHCTL2_CH1NP BIT(7)
174 #define TIMER_CHCTL2_CH2EN BIT(8)
175 #define TIMER_CHCTL2_CH2P BIT(9)
176 #define TIMER_CHCTL2_CH2NEN BIT(10)
177 #define TIMER_CHCTL2_CH2NP BIT(11)
178 #define TIMER_CHCTL2_CH3EN BIT(12)
179 #define TIMER_CHCTL2_CH3P BIT(13)
180 #define TIMER_CHCTL2_CH3NP BIT(15)
182 /* TIMER_CNT */
183 #define TIMER_CNT_CNT16 BITS(0,15)
184 #define TIMER_CNT_CNT32 BITS(0,31)
186 /* TIMER_PSC */
187 #define TIMER_PSC_PSC BITS(0,15)
189 /* TIMER_CAR */
190 #define TIMER_CAR_CARL16 BITS(0,15)
191 #define TIMER_CAR_CARL32 BITS(0,31)
193 /* TIMER_CREP */
194 #define TIMER_CREP_CREP BITS(0,7)
196 /* TIMER_CH0CV */
197 #define TIMER_CH0CV_CH0VAL16 BITS(0,15)
198 #define TIMER_CH0CV_CH0VAL32 BITS(0,31)
200 /* TIMER_CH1CV */
201 #define TIMER_CH1CV_CH1VAL16 BITS(0,15)
202 #define TIMER_CH1CV_CH1VAL32 BITS(0,31)
204 /* TIMER_CH2CV */
205 #define TIMER_CH2CV_CH2VAL16 BITS(0,15)
206 #define TIMER_CH2CV_CH2VAL32 BITS(0,31)
208 /* TIMER_CH3CV */
209 #define TIMER_CH3CV_CH3VAL16 BITS(0,15)
210 #define TIMER_CH3CV_CH3VAL32 BITS(0,31)
212 /* TIMER_CCHP */
213 #define TIMER_CCHP_DTCFG BITS(0,7)
214 #define TIMER_CCHP_PROT BITS(8,9)
215 #define TIMER_CCHP_IOS BIT(10)
216 #define TIMER_CCHP_ROS BIT(11)
217 #define TIMER_CCHP_BRKEN BIT(12)
218 #define TIMER_CCHP_BRKP BIT(13)
219 #define TIMER_CCHP_OAEN BIT(14)
220 #define TIMER_CCHP_POEN BIT(15)
222 /* TIMER_DMACFG */
223 #define TIMER_DMACFG_DMATA BITS(0,4)
224 #define TIMER_DMACFG_DMATC BITS(8,12)
226 /* TIMER_DMATB */
227 #define TIMER_DMATB_DMATB BITS(0,15)
229 /* TIMER_IRMP */
230 #define TIMER13_IRMP_CI0_RMP BITS(0,1)
232 /* TIMER_CFG */
233 #define TIMER_CFG_OUTSEL BIT(0)
234 #define TIMER_CFG_CHVSEL BIT(1)
236 /* constants definitions */
237 /* TIMER init parameter struct definitions*/
238 typedef struct
239 {
240 uint16_t prescaler;
241 uint16_t alignedmode;
242 uint16_t counterdirection;
243 uint32_t period;
244 uint16_t clockdivision;
245 uint8_t repetitioncounter;
246 }timer_parameter_struct;
247
248 /* break parameter struct definitions*/
249 typedef struct
250 {
251 uint16_t runoffstate;
252 uint32_t ideloffstate;
253 uint16_t deadtime;
254 uint16_t breakpolarity;
255 uint16_t outputautostate;
256 uint16_t protectmode;
257 uint16_t breakstate;
258 }timer_break_parameter_struct;
259
260 /* channel output parameter struct definitions */
261 typedef struct
262 {
263 uint32_t outputstate;
264 uint16_t outputnstate;
265 uint16_t ocpolarity;
266 uint16_t ocnpolarity;
267 uint16_t ocidlestate;
268 uint16_t ocnidlestate;
269 }timer_oc_parameter_struct;
270
271 /* channel input parameter struct definitions */
272 typedef struct
273 {
274 uint16_t icpolarity;
275 uint16_t icselection;
276 uint16_t icprescaler;
277 uint16_t icfilter;
278 }timer_ic_parameter_struct;
279
280 /* TIMER interrupt enable or disable */
281 #define TIMER_INT_UP TIMER_DMAINTEN_UPIE
282 #define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE
283 #define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE
284 #define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE
285 #define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE
286 #define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE
287 #define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE
288 #define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE
290 /* TIMER flag */
291 #define TIMER_FLAG_UP TIMER_INTF_UPIF
292 #define TIMER_FLAG_CH0 TIMER_INTF_CH0IF
293 #define TIMER_FLAG_CH1 TIMER_INTF_CH1IF
294 #define TIMER_FLAG_CH2 TIMER_INTF_CH2IF
295 #define TIMER_FLAG_CH3 TIMER_INTF_CH3IF
296 #define TIMER_FLAG_CMT TIMER_INTF_CMTIF
297 #define TIMER_FLAG_TRG TIMER_INTF_TRGIF
298 #define TIMER_FLAG_BRK TIMER_INTF_BRKIF
299 #define TIMER_FLAG_CH0O TIMER_INTF_CH0OF
300 #define TIMER_FLAG_CH1O TIMER_INTF_CH1OF
301 #define TIMER_FLAG_CH2O TIMER_INTF_CH2OF
302 #define TIMER_FLAG_CH3O TIMER_INTF_CH3OF
304 /* TIMER interrupt flag */
305 #define TIMER_INT_FLAG_UP TIMER_INTF_UPIF
306 #define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF
307 #define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF
308 #define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF
309 #define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF
310 #define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF
311 #define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF
312 #define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF
313
314 /* TIMER DMA source enable */
315 #define TIMER_DMA_UPD ((uint16_t)0x0100U)
316 #define TIMER_DMA_CH0D ((uint16_t)0x0200U)
317 #define TIMER_DMA_CH1D ((uint16_t)0x0400U)
318 #define TIMER_DMA_CH2D ((uint16_t)0x0800U)
319 #define TIMER_DMA_CH3D ((uint16_t)0x1000U)
320 #define TIMER_DMA_CMTD ((uint16_t)0x2000U)
321 #define TIMER_DMA_TRGD ((uint16_t)0x4000U)
323 /* channel DMA request source selection */
324 #define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U)
325 #define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U)
327 /* DMA access base address */
328 #define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U))
329 #define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0)
330 #define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1)
331 #define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2)
332 #define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3)
333 #define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4)
334 #define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5)
335 #define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6)
336 #define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7)
337 #define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8)
338 #define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9)
339 #define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10)
340 #define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11)
341 #define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12)
342 #define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13)
343 #define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14)
344 #define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15)
345 #define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16)
346 #define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17)
347 #define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18)
348 #define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19)
350 /* DMA access burst length */
351 #define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U))
352 #define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0)
353 #define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1)
354 #define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2)
355 #define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3)
356 #define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4)
357 #define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5)
358 #define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6)
359 #define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7)
360 #define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8)
361 #define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9)
362 #define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10)
363 #define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11)
364 #define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12)
365 #define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13)
366 #define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14)
367 #define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15)
368 #define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16)
369 #define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17)
371 /* TIMER software event generation source */
372 #define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U)
373 #define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U)
374 #define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U)
375 #define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U)
376 #define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U)
377 #define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U)
378 #define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U)
379 #define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U)
381 /* center-aligned mode selection */
382 #define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))
383 #define TIMER_COUNTER_EDGE CTL0_CAM(0)
384 #define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1)
385 #define TIMER_COUNTER_CENTER_UP CTL0_CAM(2)
386 #define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3)
388 /* TIMER prescaler reload mode */
389 #define TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U)
390 #define TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U)
392 /* count direction */
393 #define TIMER_COUNTER_UP ((uint16_t)0x0000U)
394 #define TIMER_COUNTER_DOWN ((uint16_t)0x0010U)
396 /* specify division ratio between TIMER clock and dead-time and sampling clock */
397 #define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
398 #define TIMER_CKDIV_DIV1 CTL0_CKDIV(0)
399 #define TIMER_CKDIV_DIV2 CTL0_CKDIV(1)
400 #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2)
402 /* single pulse mode */
403 #define TIMER_SP_MODE_SINGLE ((uint8_t)0x00U)
404 #define TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U)
406 /* update source */
407 #define TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U)
408 #define TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U)
410 /* run mode off-state configure */
411 #define TIMER_ROS_STATE_ENABLE ((uint32_t)0x00000800U)
412 #define TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U)
414 /* idle mode off-state configure */
415 #define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U)
416 #define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U)
418 /* break input polarity */
419 #define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U)
420 #define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U)
422 /* output automatic enable */
423 #define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U)
424 #define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U)
426 /* complementary register protect control */
427 #define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
428 #define TIMER_CCHP_PROT_OFF CCHP_PROT(0)
429 #define TIMER_CCHP_PROT_0 CCHP_PROT(1)
430 #define TIMER_CCHP_PROT_1 CCHP_PROT(2)
431 #define TIMER_CCHP_PROT_2 CCHP_PROT(3)
433 /* break input enable */
434 #define TIMER_BREAK_ENABLE ((uint16_t)0x1000U)
435 #define TIMER_BREAK_DISABLE ((uint16_t)0x0000U)
437 /* TIMER channel y(y=0,1,2,3) */
438 #define TIMER_CH_0 ((uint16_t)0x0000U)
439 #define TIMER_CH_1 ((uint16_t)0x0001U)
440 #define TIMER_CH_2 ((uint16_t)0x0002U)
441 #define TIMER_CH_3 ((uint16_t)0x0003U)
443 /* channel enable state*/
444 #define TIMER_CCX_ENABLE ((uint32_t)0x00000001U)
445 #define TIMER_CCX_DISABLE ((uint32_t)0x00000000U)
447 /* channel complementary output enable state*/
448 #define TIMER_CCXN_ENABLE ((uint16_t)0x0004U)
449 #define TIMER_CCXN_DISABLE ((uint16_t)0x0000U)
451 /* channel output polarity */
452 #define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U)
453 #define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U)
455 /* channel complementary output polarity */
456 #define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U)
457 #define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U)
459 /* idle state of channel output */
460 #define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100)
461 #define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000)
463 /* idle state of channel complementary output */
464 #define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U)
465 #define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U)
467 /* channel output compare mode */
468 #define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U)
469 #define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U)
470 #define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U)
471 #define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U)
472 #define TIMER_OC_MODE_LOW ((uint16_t)0x0040U)
473 #define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U)
474 #define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U)
475 #define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U)
477 /* channel output compare shadow enable */
478 #define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U)
479 #define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U)
481 /* channel output compare fast enable */
482 #define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004)
483 #define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000)
485 /* channel output compare clear enable */
486 #define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U)
487 #define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U)
489 /* channel control shadow register update control */
490 #define TIMER_UPDATECTL_CCU ((uint8_t)0x00U)
491 #define TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U)
493 /* channel input capture polarity */
494 #define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U)
495 #define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U)
496 #define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU)
498 /* timer input capture selection */
499 #define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U)
500 #define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U)
501 #define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U)
503 /* channel input capture prescaler */
504 #define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U)
505 #define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U)
506 #define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U)
507 #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU)
509 /* trigger selection */
510 #define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
511 #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0)
512 #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1)
513 #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2)
514 #define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3)
515 #define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4)
516 #define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5)
517 #define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6)
518 #define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7)
520 /* master mode control */
521 #define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
522 #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0)
523 #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1)
524 #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2)
525 #define TIMER_TRI_OUT_SRC_CC0 CTL1_MMC(3)
526 #define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4)
527 #define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5)
528 #define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6)
529 #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7)
531 /* slave mode control */
532 #define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U))
533 #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0)
534 #define TIMER_ENCODER_MODE0 SMCFG_SMC(1)
535 #define TIMER_ENCODER_MODE1 SMCFG_SMC(2)
536 #define TIMER_ENCODER_MODE2 SMCFG_SMC(3)
537 #define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4)
538 #define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5)
539 #define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6)
540 #define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7)
542 /* OCPRE clear source selection */
543 #define TIMER_OCPRE_CLEAR_SOURCE_CLR ((uint8_t)0x00U)
544 #define TIMER_OCPRE_CLEAR_SOURCE_ETIF ((uint8_t)0x01U)
546 /* master slave mode selection */
547 #define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U)
548 #define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U)
550 /* external trigger prescaler */
551 #define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U))
552 #define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0)
553 #define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1)
554 #define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2)
555 #define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3)
557 /* external trigger polarity */
558 #define TIMER_ETP_FALLING TIMER_SMCFG_ETP
559 #define TIMER_ETP_RISING ((uint32_t)0x00000000U)
561 /* channel 0 trigger input selection */
562 #define TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U)
563 #define TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U)
565 /* timerx(x=0,1,2,13,14,15,16) write cc register selection */
566 #define TIMER_CCSEL_DISABLE ((uint16_t)0x0000U)
567 #define TIMER_CCSEL_ENABLE ((uint16_t)0x0002U)
569 /* the output value selection */
570 #define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U)
571 #define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U)
573 /* timer13 channel 0 input remap */
574 #define TIMER13_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U))
575 #define TIMER13_CI0_RMP_GPIO TIMER13_IRMP(0)
576 #define TIMER13_CI0_RMP_RTCCLK TIMER13_IRMP(1)
577 #define TIMER13_CI0_RMP_HXTAL_DIV32 TIMER13_IRMP(2)
578 #define TIMER13_CI0_RMP_CKOUTSEL TIMER13_IRMP(3)
580 /* function declarations */
581 /* TIMER timebase*/
582 /* deinit a TIMER */
583 void timer_deinit(uint32_t timer_periph);
584 /* initialize TIMER counter */
585 void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara);
586 /* enable a TIMER */
587 void timer_enable(uint32_t timer_periph);
588 /* disable a TIMER */
589 void timer_disable(uint32_t timer_periph);
590 /* enable the auto reload shadow function */
591 void timer_auto_reload_shadow_enable(uint32_t timer_periph);
592 /* disable the auto reload shadow function */
593 void timer_auto_reload_shadow_disable(uint32_t timer_periph);
594 /* enable the update event */
595 void timer_update_event_enable(uint32_t timer_periph);
596 /* disable the update event */
597 void timer_update_event_disable(uint32_t timer_periph);
598 /* set TIMER counter alignment mode */
599 void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned);
600 /* set TIMER counter up direction */
601 void timer_counter_up_direction(uint32_t timer_periph);
602 /* set TIMER counter down direction */
603 void timer_counter_down_direction(uint32_t timer_periph);
604 /* configure TIMER prescaler */
605 void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload);
606 /* configure TIMER repetition register value */
607 void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition);
608 /* configure TIMER autoreload register value */
609 void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload);
610 /* configure TIMER counter register value */
611 void timer_counter_value_config(uint32_t timer_periph , uint32_t counter);
612 /* read TIMER counter value */
613 uint32_t timer_counter_read(uint32_t timer_periph);
614 /* read TIMER prescaler value */
615 uint16_t timer_prescaler_read(uint32_t timer_periph);
616 /* configure TIMER single pulse mode */
617 void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode);
618 /* configure TIMER update source */
619 void timer_update_source_config(uint32_t timer_periph, uint8_t update);
620 /* OCPRE clear source selection */
621 void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear);
622
623 /* TIMER interrupt and flag*/
624 /* enable the TIMER interrupt */
625 void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt);
626 /* disable the TIMER interrupt */
627 void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt);
628 /* get timer interrupt flag */
629 FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt);
630 /* clear TIMER interrupt flag */
631 void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt);
632 /* get TIMER flags */
633 FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag);
634 /* clear TIMER flags */
635 void timer_flag_clear(uint32_t timer_periph, uint32_t flag);
636
637 /* timer DMA and event*/
638 /* enable the TIMER DMA */
639 void timer_dma_enable(uint32_t timer_periph, uint16_t dma);
640 /* disable the TIMER DMA */
641 void timer_dma_disable(uint32_t timer_periph, uint16_t dma);
642 /* channel DMA request source selection */
643 void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request);
644 /* configure the TIMER DMA transfer */
645 void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr, uint32_t dma_lenth);
646 /* software generate events */
647 void timer_event_software_generate(uint32_t timer_periph, uint16_t event);
648
649 /* timer channel complementary protection */
650 /* configure TIMER break function */
651 void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara);
652 /* enable TIMER break function */
653 void timer_break_enable(uint32_t timer_periph);
654 /* disable TIMER break function */
655 void timer_break_disable(uint32_t timer_periph);
656 /* enable TIMER output automatic function */
657 void timer_automatic_output_enable(uint32_t timer_periph);
658 /* disable TIMER output automatic function */
659 void timer_automatic_output_disable(uint32_t timer_periph);
660 /* configure TIMER primary output function */
661 void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue);
662 /* channel capture/compare control shadow register enable */
663 void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue);
664 /* configure TIMER channel control shadow register update control */
665 void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl);
666
667 /* TIMER channel output */
668 /* configure TIMER channel output function */
669 void timer_channel_output_config(uint32_t timer_periph,uint16_t channel, timer_oc_parameter_struct* ocpara);
670 /* configure TIMER channel output compare mode */
671 void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel,uint16_t ocmode);
672 /* configure TIMER channel output pulse value */
673 void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse);
674 /* configure TIMER channel output shadow function */
675 void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow);
676 /* configure TIMER channel output fast function */
677 void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast);
678 /* configure TIMER channel output clear function */
679 void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear);
680 /* configure TIMER channel output polarity */
681 void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity);
682 /* configure TIMER channel complementary output polarity */
683 void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity);
684 /* configure TIMER channel enable state */
685 void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state);
686 /* configure TIMER channel complementary output enable state */
687 void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate);
688
689 /* TIMER channel input */
690 /* configure TIMER input capture parameter */
691 void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara);
692 /* configure TIMER channel input capture prescaler value */
693 void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler);
694 /* read TIMER channel capture compare register value */
695 uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel);
696 /* configure TIMER input pwm capture function */
697 void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm);
698 /* configure TIMER hall sensor mode */
699 void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode);
700
701 /* TIMER master and slave */
702 /* select TIMER input trigger source */
703 void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger);
704 /* select TIMER master mode output trigger source */
705 void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger);
706 /* select TIMER slave mode */
707 void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode);
708 /* configure TIMER master slave mode */
709 void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave);
710 /* configure TIMER external trigger input */
711 void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter);
712 /* configure TIMER quadrature decoder mode */
713 void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity);
714 /* configure TIMER internal clock mode */
715 void timer_internal_clock_config(uint32_t timer_periph);
716 /* configure TIMER the internal trigger as external clock input */
717 void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger);
718 /* configure TIMER the external trigger as external clock input */
719 void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity,uint32_t extfilter);
720 /* configure TIMER the external clock mode 0 */
721 void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter);
722 /* configure TIMER the external clock mode 1 */
723 void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter);
724 /* disable TIMER the external clock mode 1 */
725 void timer_external_clock_mode1_disable(uint32_t timer_periph);
726 /* configure TIMER channel remap function */
727 void timer_channel_remap_config(uint32_t timer_periph,uint32_t remap);
728
729 /* TIMER configure */
730 /* configure TIMER write CHxVAL register selection */
731 void timer_write_cc_register_config(uint32_t timer_periph, uint16_t ccsel);
732 /* configure TIMER output value selection */
733 void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel);
734
735 #endif /* GD32F3X0_TIMER_H */
timer_single_pulse_mode_config
void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode)
configure TIMER single pulse mode
Definition: gd32f3x0_timer.c:309
timer_event_software_generate
void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
software generate events
Definition: gd32f3x0_timer.c:602
timer_slave_mode_select
void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
select TIMER slave mode
Definition: gd32f3x0_timer.c:1608
timer_break_disable
void timer_break_disable(uint32_t timer_periph)
disable TIMER break function
Definition: gd32f3x0_timer.c:649
timer_break_parameter_struct::deadtime
uint16_t deadtime
Definition: gd32f3x0_timer.h:253
timer_counter_value_config
void timer_counter_value_config(uint32_t timer_periph, uint32_t counter)
configure TIMER counter register value
Definition: gd32f3x0_timer.c:269
timer_disable
void timer_disable(uint32_t timer_periph)
disable a TIMER
Definition: gd32f3x0_timer.c:131
timer_ic_parameter_struct::icselection
uint16_t icselection
Definition: gd32f3x0_timer.h:275
timer_master_output_trigger_source_select
void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
select TIMER master mode output trigger source
Definition: gd32f3x0_timer.c:1586
timer_oc_parameter_struct::ocnidlestate
uint16_t ocnidlestate
Definition: gd32f3x0_timer.h:268
timer_channel_output_clear_config
void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
configure TIMER channel output clear function
Definition: gd32f3x0_timer.c:1051
timer_channel_remap_config
void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap)
configure TIMER channel remap function
Definition: gd32f3x0_timer.c:1848
timer_channel_capture_value_register_read
uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
read TIMER channel capture compare register value
Definition: gd32f3x0_timer.c:1399
timer_output_value_selection_config
void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel)
configure TIMER output value selection
Definition: gd32f3x0_timer.c:1881
timer_counter_alignment
void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
set TIMER counter alignment mode
Definition: gd32f3x0_timer.c:191
timer_auto_reload_shadow_disable
void timer_auto_reload_shadow_disable(uint32_t timer_periph)
disable the auto reload shadow function
Definition: gd32f3x0_timer.c:153
timer_break_parameter_struct::ideloffstate
uint32_t ideloffstate
Definition: gd32f3x0_timer.h:252
timer_channel_output_state_config
void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
configure TIMER channel enable state
Definition: gd32f3x0_timer.c:1177
timer_channel_complementary_output_state_config
void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
configure TIMER channel complementary output enable state
Definition: gd32f3x0_timer.c:1218
timer_channel_output_fast_config
void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
configure TIMER channel output fast function
Definition: gd32f3x0_timer.c:1009
timer_flag_clear
void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
clear TIMER flags
Definition: gd32f3x0_timer.c:490
timer_counter_down_direction
void timer_counter_down_direction(uint32_t timer_periph)
set TIMER counter down direction
Definition: gd32f3x0_timer.c:214
timer_init
void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara)
initialize TIMER counter
Definition: gd32f3x0_timer.c:83
timer_external_trigger_as_external_clock_config
void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter)
configure TIMER the external trigger as external clock input
Definition: gd32f3x0_timer.c:1729
timer_break_enable
void timer_break_enable(uint32_t timer_periph)
enable TIMER break function
Definition: gd32f3x0_timer.c:638
timer_external_clock_mode1_config
void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode1
Definition: gd32f3x0_timer.c:1817
timer_channel_output_pulse_value_config
void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
configure TIMER channel output pulse value
Definition: gd32f3x0_timer.c:933
timer_enable
void timer_enable(uint32_t timer_periph)
enable a TIMER
Definition: gd32f3x0_timer.c:120
timer_oc_parameter_struct::ocpolarity
uint16_t ocpolarity
Definition: gd32f3x0_timer.h:265
timer_input_trigger_source_select
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
select TIMER input trigger source
Definition: gd32f3x0_timer.c:1565
timer_automatic_output_disable
void timer_automatic_output_disable(uint32_t timer_periph)
disable TIMER output automatic function
Definition: gd32f3x0_timer.c:671
timer_channel_complementary_output_polarity_config
void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
configure TIMER channel complementary output polarity
Definition: gd32f3x0_timer.c:1135
timer_channel_dma_request_source_select
void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request)
channel DMA request source selection
Definition: gd32f3x0_timer.c:542
timer_dma_transfer_config
void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
configure the TIMER DMA transfer
Definition: gd32f3x0_timer.c:581
timer_update_event_disable
void timer_update_event_disable(uint32_t timer_periph)
disable the update event
Definition: gd32f3x0_timer.c:175
timer_ocpre_clear_source_config
void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear)
configure TIMER OCPRE clear source selection
Definition: gd32f3x0_timer.c:347
timer_master_slave_mode_config
void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave)
configure TIMER master slave mode
Definition: gd32f3x0_timer.c:1624
timer_update_event_enable
void timer_update_event_enable(uint32_t timer_periph)
enable the update event
Definition: gd32f3x0_timer.c:164
timer_interrupt_flag_get
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
get timer interrupt flag
Definition: gd32f3x0_timer.c:412
timer_ic_parameter_struct::icprescaler
uint16_t icprescaler
Definition: gd32f3x0_timer.h:276
timer_channel_output_polarity_config
void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
configure TIMER channel output polarity
Definition: gd32f3x0_timer.c:1093
timer_autoreload_value_config
void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload)
configure TIMER autoreload register value
Definition: gd32f3x0_timer.c:257
timer_interrupt_flag_clear
void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
clear TIMER interrupt flag
Definition: gd32f3x0_timer.c:438
timer_channel_output_config
void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara)
configure TIMER channel output function
Definition: gd32f3x0_timer.c:745
timer_external_trigger_config
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER external trigger input
Definition: gd32f3x0_timer.c:1649
timer_channel_output_shadow_config
void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
configure TIMER channel output shadow function
Definition: gd32f3x0_timer.c:967
timer_interrupt_disable
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
disable the TIMER interrupt
Definition: gd32f3x0_timer.c:392
timer_parameter_struct::clockdivision
uint16_t clockdivision
Definition: gd32f3x0_timer.h:244
timer_break_parameter_struct::outputautostate
uint16_t outputautostate
Definition: gd32f3x0_timer.h:255
timer_write_cc_register_config
void timer_write_cc_register_config(uint32_t timer_periph, uint16_t ccsel)
configure TIMER write CHxVAL register selection
Definition: gd32f3x0_timer.c:1862
timer_quadrature_decoder_mode_config
void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
configure TIMER quadrature decoder mode
Definition: gd32f3x0_timer.c:1673
timer_internal_clock_config
void timer_internal_clock_config(uint32_t timer_periph)
configure TIMER internal clock mode
Definition: gd32f3x0_timer.c:1693
timer_external_clock_mode0_config
void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
configure TIMER the external clock mode0
Definition: gd32f3x0_timer.c:1790
timer_deinit
void timer_deinit(uint32_t timer_periph)
deinit a TIMER
Definition: gd32f3x0_timer.c:20
timer_dma_enable
void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
enable the TIMER DMA
Definition: gd32f3x0_timer.c:509
timer_ic_parameter_struct::icpolarity
uint16_t icpolarity
Definition: gd32f3x0_timer.h:274
timer_break_parameter_struct
Definition: gd32f3x0_timer.h:249
timer_input_capture_config
void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara)
configure TIMER input capture parameter
Definition: gd32f3x0_timer.c:1257
timer_primary_output_config
void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
configure TIMER primary output function
Definition: gd32f3x0_timer.c:683
timer_channel_output_mode_config
void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
configure TIMER channel output compare mode
Definition: gd32f3x0_timer.c:893
timer_break_parameter_struct::runoffstate
uint16_t runoffstate
Definition: gd32f3x0_timer.h:251
timer_update_source_config
void timer_update_source_config(uint32_t timer_periph, uint8_t update)
configure TIMER update source
Definition: gd32f3x0_timer.c:328
timer_repetition_value_config
void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
configure TIMER repetition register value
Definition: gd32f3x0_timer.c:245
timer_prescaler_config
void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
configure TIMER prescaler
Definition: gd32f3x0_timer.c:229
timer_oc_parameter_struct::outputstate
uint32_t outputstate
Definition: gd32f3x0_timer.h:263
timer_interrupt_enable
void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
enable the TIMER interrupt
Definition: gd32f3x0_timer.c:372
timer_oc_parameter_struct::ocidlestate
uint16_t ocidlestate
Definition: gd32f3x0_timer.h:267
timer_break_parameter_struct::breakpolarity
uint16_t breakpolarity
Definition: gd32f3x0_timer.h:254
timer_parameter_struct::repetitioncounter
uint8_t repetitioncounter
Definition: gd32f3x0_timer.h:245
timer_break_parameter_struct::breakstate
uint16_t breakstate
Definition: gd32f3x0_timer.h:257
timer_prescaler_read
uint16_t timer_prescaler_read(uint32_t timer_periph)
read TIMER prescaler value
Definition: gd32f3x0_timer.c:293
timer_channel_control_shadow_config
void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
channel capture/compare control shadow register enable
Definition: gd32f3x0_timer.c:699
timer_hall_mode_config
void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode)
configure TIMER hall sensor mode
Definition: gd32f3x0_timer.c:1541
timer_internal_trigger_as_external_clock_config
void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
configure TIMER the internal trigger as external clock input
Definition: gd32f3x0_timer.c:1708
timer_channel_input_capture_prescaler_config
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
configure TIMER channel input capture prescaler value
Definition: gd32f3x0_timer.c:1360
timer_counter_read
uint32_t timer_counter_read(uint32_t timer_periph)
read TIMER counter value
Definition: gd32f3x0_timer.c:280
timer_auto_reload_shadow_enable
void timer_auto_reload_shadow_enable(uint32_t timer_periph)
enable the auto reload shadow function
Definition: gd32f3x0_timer.c:142
timer_parameter_struct::prescaler
uint16_t prescaler
Definition: gd32f3x0_timer.h:240
timer_flag_get
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
get TIMER flags
Definition: gd32f3x0_timer.c:462
timer_oc_parameter_struct::ocnpolarity
uint16_t ocnpolarity
Definition: gd32f3x0_timer.h:266
timer_parameter_struct
Definition: gd32f3x0_timer.h:238
timer_external_clock_mode1_disable
void timer_external_clock_mode1_disable(uint32_t timer_periph)
disable TIMER the external clock mode1
Definition: gd32f3x0_timer.c:1832
timer_break_config
void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara)
configure TIMER break function
Definition: gd32f3x0_timer.c:621
timer_input_pwm_capture_config
void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm)
configure TIMER input pwm capture function
Definition: gd32f3x0_timer.c:1436
timer_counter_up_direction
void timer_counter_up_direction(uint32_t timer_periph)
set TIMER counter up direction
Definition: gd32f3x0_timer.c:203
timer_parameter_struct::period
uint32_t period
Definition: gd32f3x0_timer.h:243
timer_oc_parameter_struct
Definition: gd32f3x0_timer.h:261
timer_break_parameter_struct::protectmode
uint16_t protectmode
Definition: gd32f3x0_timer.h:256
timer_ic_parameter_struct::icfilter
uint16_t icfilter
Definition: gd32f3x0_timer.h:277
timer_channel_control_shadow_update_config
void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl)
configure TIMER channel control shadow register update control
Definition: gd32f3x0_timer.c:717
timer_dma_disable
void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
disable the TIMER DMA
Definition: gd32f3x0_timer.c:528
timer_automatic_output_enable
void timer_automatic_output_enable(uint32_t timer_periph)
enable TIMER output automatic function
Definition: gd32f3x0_timer.c:660
timer_oc_parameter_struct::outputnstate
uint16_t outputnstate
Definition: gd32f3x0_timer.h:264
timer_ic_parameter_struct
Definition: gd32f3x0_timer.h:272
timer_parameter_struct::alignedmode
uint16_t alignedmode
Definition: gd32f3x0_timer.h:241
timer_parameter_struct::counterdirection
uint16_t counterdirection
Definition: gd32f3x0_timer.h:242
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_int.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
usbh_int.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef USBH_INT_H
13 #define USBH_INT_H
14
15 #include "usb_core.h"
16
17 typedef struct
18 {
19 uint8_t (*sof) (usb_core_handle_struct *pudev);
20 uint8_t (*device_connected) (usb_core_handle_struct *pudev);
21 uint8_t (*device_disconnected) (usb_core_handle_struct *pudev);
22 }usbh_hcd_int_cb_struct;
23
24 extern usbh_hcd_int_cb_struct *usbh_hcd_int_fops;
25
26 /* function declarations */
27 /* handle global host interrupt */
28 uint32_t usbh_isr (usb_core_handle_struct *pudev);
29
30 #endif /* USBH_INT_H */
usbh_hcd_int_fops
usbh_hcd_int_cb_struct * usbh_hcd_int_fops
Definition: usbh_core.c:33
usb_core.h
USB core driver header file.
usb_core_handle_struct
Definition: usb_core.h:200
usbh_isr
uint32_t usbh_isr(usb_core_handle_struct *pudev)
handle global host interrupt
Definition: usbh_int.c:33
usbh_hcd_int_cb_struct
Definition: usbh_int.h:17
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbd_core.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
usbd_core.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "usbd_core.h"
13 #include "usbd_std.h"
14
22 void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
23 {
24 /* select USB core */
25 usb_core_select (pudev, core_id);
26
27 pudev->dev.status = USB_STATUS_DEFAULT;
28
29 /* disable USB global interrupt */
30 USB_GLOBAL_INT_DISABLE();
31
32 /* init the core (common init.) */
33 usb_core_init(pudev);
34
35 /* force device mode*/
36 usb_mode_set(pudev, DEVICE_MODE);
37
38 /* set device disconnect */
39 USB_SOFT_DISCONNECT_ENABLE();
40
41 if ((void *)0 != pudev->mdelay) {
42 pudev->mdelay(3U);
43 }
44
45 /* init device */
46 usb_devcore_init(pudev);
47
48 /* set device Connect */
49 USB_SOFT_DISCONNECT_DISABLE();
50
51 if ((void *)0 != pudev->mdelay) {
52 pudev->mdelay(3U);
53 }
54
55 /* enable USB global interrupt */
56 USB_GLOBAL_INT_ENABLE();
57 }
58
66 void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc)
67 {
68 usb_ep_struct *ep;
69 usb_dir_enum ep_dir;
70
71 uint32_t devepinten = 0U;
72 uint32_t devepctl = 0U;
73
74 uint8_t ep_num = ep_desc->bEndpointAddress & 0x7FU;
75 uint8_t ep_type = ep_desc->bmAttributes & USB_EPTYPE_MASK;
76 uint16_t ep_mps = ep_desc->wMaxPacketSize;
77
78 if (ep_desc->bEndpointAddress >> 7) {
79 ep = &pudev->dev.in_ep[ep_num];
80
81 devepinten |= 1U << ep_num;
82 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
83
84 ep_dir = USB_TX;
85 } else {
86 ep = &pudev->dev.out_ep[ep_num];
87
88 devepinten |= (1U << ep_num) << 16;
89 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
90
91 ep_dir = USB_RX;
92 }
93
94 /* if the endpoint is not active, need change the endpoint control register */
95 if (!(devepctl & DEPCTL_EPACT)) {
96 devepctl &= ~DEPCTL_MPL;
97 devepctl |= ep_mps;
98
99 devepctl &= ~DEPCTL_EPTYPE;
100 devepctl |= (uint32_t)ep_type << 18;
101
102 if (USB_TX == ep_dir) {
103 devepctl &= ~DIEPCTL_TXFNUM;
104 devepctl |= (uint32_t)ep_num << 22;
105 }
106
107 devepctl |= DEPCTL_SD0PID;
108 devepctl |= DEPCTL_EPACT;
109 }
110
111 if (USB_TX == ep_dir) {
112 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
113 } else if (USB_RX == ep_dir) {
114 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
115 } else {
116 /* no operation */
117 }
118
119 ep->endp_mps = ep_mps;
120 ep->endp_type = ep_type;
121
122 /* enable the interrupts for this endpoint */
123 USB_DAEPINTEN |= devepinten;
124 }
125
133 void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr)
134 {
135 uint32_t devepinten = 0U;
136 uint8_t ep_num = ep_addr & 0x7FU;
137
138 if (ep_addr >> 7) {
139 devepinten |= 1U << ep_num;
140
141 USB_DIEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT;
142 } else {
143 devepinten |= (1U << ep_num) << 16U;
144
145 USB_DOEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT;
146 }
147
148 /* disable the interrupts for this endpoint */
149 USB_DAEPINTEN &= ~devepinten;
150 }
151
161 void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
162 {
163 usb_ep_struct *ep;
164 uint8_t ep_num = ep_addr & 0x7FU;
165 uint32_t devepctl = 0U, devepxlen = 0U;
166
167 ep = &pudev->dev.out_ep[ep_num];
168
169 /* setup and start the Xfer */
170 ep->xfer_buff = pbuf;
171 ep->xfer_len = buf_len;
172 ep->xfer_count = 0U;
173
174 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
175 devepxlen = USB_DOEPxLEN((uint16_t)ep_num);
176
177 devepxlen &= ~DEPLEN_TLEN;
178 devepxlen &= ~DEPLEN_PCNT;
179
180 /* zero length packet */
181 if (0U == ep->xfer_len) {
182 /* set the transfer length to max packet size */
183 devepxlen |= ep->endp_mps;
184
185 /* set the transfer packet count to 1 */
186 devepxlen |= 1U << 19U;
187 } else {
188
189 if (0U == ep_num) {
190 /* set the transfer length to max packet size */
191 devepxlen |= ep->endp_mps;
192
193 /* set the transfer packet count to 1 */
194 devepxlen |= 1U << 19U;
195 } else {
196 /* configure the transfer size and packet count as follows:
197 * pktcnt = N
198 * xfersize = N * maxpacket
199 */
200 devepxlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U;
201 devepxlen |= ((devepxlen & DEPLEN_PCNT) >> 19U) * ep->endp_mps;
202 }
203 }
204
205 USB_DOEPxLEN((uint16_t)ep_num) = devepxlen;
206
207 if (USB_EPTYPE_ISOC == ep->endp_type) {
208 if (ep->endp_frame) {
209 devepctl |= DEPCTL_SODDFRM;
210 } else {
211 devepctl |= DEPCTL_SEVNFRM;
212 }
213 }
214
215 /* enable the endpoint and clear the NAK */
216 devepctl |= DEPCTL_EPEN | DEPCTL_CNAK;
217
218 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
219 }
220
230 void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
231 {
232 usb_ep_struct *ep;
233 uint8_t ep_num = ep_addr & 0x7FU;
234 __IO uint32_t devepctl = 0U;
235 __IO uint32_t deveplen = 0U;
236
237 ep = &pudev->dev.in_ep[ep_num];
238
239 /* setup and start the transfer */
240 ep->xfer_buff = pbuf;
241 ep->xfer_len = buf_len;
242 ep->xfer_count = 0U;
243
244 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
245 deveplen = USB_DIEPxLEN((uint16_t)ep_num);
246
247 /* clear transfer length to 0 */
248 deveplen &= ~DEPLEN_TLEN;
249
250 /* clear transfer packet to 0 */
251 deveplen &= ~DEPLEN_PCNT;
252
253 /* zero length packet */
254 if (0U == ep->xfer_len) {
255 /* set transfer packet count to 1 */
256 deveplen |= 1U << 19U;
257 } else {
258 if (0U == ep_num) {
259 if (ep->xfer_len > ep->endp_mps) {
260 ep->xfer_len = ep->endp_mps;
261 }
262
263 deveplen |= 1U << 19U;
264 } else {
265 deveplen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U;
266 }
267
268 /* configure the transfer size and packet count as follows:
269 * xfersize = N * maxpacket + short_packet
270 * pktcnt = N + (short_packet exist ? 1 : 0)
271 */
272 deveplen |= ep->xfer_len;
273
274 if (USB_EPTYPE_ISOC == ep->endp_type) {
275 deveplen |= DIEPLEN_MCNT & (1U << 29U);
276 }
277 }
278
279 USB_DIEPxLEN((uint16_t)ep_num) = deveplen;
280
281 if (USB_EPTYPE_ISOC == ep->endp_type) {
282 if (0U == (((USB_DSTAT & DSTAT_FNRSOF) >> 8U) & 0x1U)) {
283 devepctl |= DEPCTL_SODDFRM;
284 } else {
285 devepctl |= DEPCTL_SEVNFRM;
286 }
287 }
288
289 /* enable the endpoint and clear the NAK */
290 devepctl |= DEPCTL_EPEN | DEPCTL_CNAK;
291
292 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
293
294 if (USB_EPTYPE_ISOC != ep->endp_type) {
295 /* enable the Tx FIFO empty interrupt for this endpoint */
296 if (ep->xfer_len > 0U) {
297 USB_DIEPFEINTEN |= 1U << ep_num;
298 }
299 } else {
300 usb_fifo_write(ep->xfer_buff, ep_num, (uint16_t)ep->xfer_len);
301 }
302 }
303
312 usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
313 {
314 usbd_status_enum ret = USBD_OK;
315
316 pudev->dev.sum_len = len;
317 pudev->dev.remain_len = len;
318 pudev->dev.ctl_status = USB_CTRL_DATA_IN;
319
320 usbd_ep_tx (pudev, 0U, pbuf, (uint32_t)len);
321
322 return ret;
323 }
324
333 usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
334 {
335 pudev->dev.sum_len = len;
336 pudev->dev.remain_len = len;
337 pudev->dev.ctl_status = USB_CTRL_DATA_OUT;
338
339 usbd_ep_rx (pudev, 0U, pbuf, len);
340
341 return USBD_OK;
342 }
343
350 usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev)
351 {
352 pudev->dev.ctl_status = USB_CTRL_STATUS_IN;
353
354 usbd_ep_tx (pudev, 0U, NULL, 0U);
355
356 usb_ep0_startout(pudev);
357
358 return USBD_OK;
359 }
360
367 usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev)
368 {
369 pudev->dev.ctl_status = USB_CTRL_STATUS_OUT;
370
371 usbd_ep_rx (pudev, 0U, NULL, 0U);
372
373 usb_ep0_startout(pudev);
374
375 return USBD_OK;
376 }
377
385 void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr)
386 {
387 uint8_t ep_num = ep_addr & 0x7FU;
388 __IO uint32_t devepctl = 0U;
389
390 if (ep_addr >> 7U) {
391 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
392
393 /* set the endpoint disable bit */
394 if (devepctl & DEPCTL_EPEN) {
395 devepctl |= DEPCTL_EPD;
396 }
397
398 /* set the endpoint stall bit */
399 devepctl |= DEPCTL_STALL;
400
401 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
402 } else {
403 /* set the endpoint stall bit */
404 USB_DOEPxCTL((uint16_t)ep_num) |= DEPCTL_STALL;
405 }
406 }
407
415 void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr)
416 {
417 usb_ep_struct *ep;
418 uint8_t ep_num = ep_addr & 0x7FU;
419 __IO uint32_t devepctl = 0U;
420
421 if(ep_addr >> 7){
422 ep = &pudev->dev.in_ep[ep_num];
423
424 devepctl = USB_DIEPxCTL((uint16_t)ep_num);
425
426 /* clear the IN endpoint stall bits */
427 devepctl &= ~DEPCTL_STALL;
428
429 if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) {
430 devepctl |= DEPCTL_SEVNFRM;
431 }
432
433 USB_DIEPxCTL((uint16_t)ep_num) = devepctl;
434 } else {
435 ep = &pudev->dev.out_ep[ep_num];
436
437 devepctl = USB_DOEPxCTL((uint16_t)ep_num);
438
439 /* clear the OUT endpoint stall bits */
440 devepctl &= ~DEPCTL_STALL;
441
442 if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) {
443 devepctl |= DEPCTL_SEVNFRM;
444 }
445
446 USB_DOEPxCTL((uint16_t)ep_num) = devepctl;
447 }
448 }
449
457 void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr)
458 {
459 if (ep_addr >> 7) {
460 usb_txfifo_flush(pudev, ep_addr & 0x7FU);
461 } else {
462 usb_rxfifo_flush(pudev);
463 }
464 }
465
473 uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num)
474 {
475 return (uint16_t)pudev->dev.out_ep[ep_num].xfer_count;
476 }
usb_txfifo_flush
usb_status_enum usb_txfifo_flush(usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs
Definition: usb_core.c:208
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:125
usbd_std.h
USB 2.0 standard defines.
USB_CTRL_STATUS_OUT
Definition: usb_core.h:87
usbd_ep_deinit
void usbd_ep_deinit(usb_core_handle_struct *pudev, uint8_t ep_addr)
endpoint deinitialize
Definition: usbd_core.c:133
usb_descriptor_endpoint_struct::bmAttributes
uint8_t bmAttributes
Definition: usb_std.h:175
USB_TX
Definition: usb_core.h:95
USBD_OK
Definition: usb_core.h:74
USB_CTRL_STATUS_IN
Definition: usb_core.h:86
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:266
DEPCTL_EPTYPE
#define DEPCTL_EPTYPE
Definition: usb_regs.h:442
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:52
usb_rxfifo_flush
usb_status_enum usb_rxfifo_flush(usb_core_handle_struct *pudev)
flush the entire Rx FIFO
Definition: usb_core.c:236
usb_ep_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:108
usbd_ep_fifo_flush
void usbd_ep_fifo_flush(usb_core_handle_struct *pudev, uint8_t ep_addr)
flushes the FIFOs
Definition: usbd_core.c:457
usbd_ep_init
void usbd_ep_init(usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc)
endpoint initialization
Definition: usbd_core.c:66
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:71
usbd_rxcount_get
uint16_t usbd_rxcount_get(usb_core_handle_struct *pudev, uint8_t ep_num)
get the received data length
Definition: usbd_core.c:473
usbd_ep_stall
void usbd_ep_stall(usb_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:385
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:431
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:54
USB_CTRL_DATA_IN
Definition: usb_core.h:84
usb_fifo_write
usb_status_enum usb_fifo_write(uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint
Definition: usb_core.c:79
usb_descriptor_endpoint_struct::bEndpointAddress
uint8_t bEndpointAddress
Definition: usb_std.h:174
USB_CTRL_DATA_OUT
Definition: usb_core.h:85
DIEPLEN_MCNT
#define DIEPLEN_MCNT
Definition: usb_regs.h:478
DEPCTL_EPD
#define DEPCTL_EPD
Definition: usb_regs.h:432
USB_DIEPxLEN
#define USB_DIEPxLEN(x)
Definition: usb_regs.h:87
USB_EPTYPE_MASK
#define USB_EPTYPE_MASK
Definition: usb_defines.h:55
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:101
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:103
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:217
usb_ep_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:107
usb_ep_struct::endp_frame
uint8_t endp_frame
Definition: usb_core.h:102
DEPLEN_TLEN
#define DEPLEN_TLEN
Definition: usb_regs.h:480
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:83
DEPCTL_EPACT
#define DEPCTL_EPACT
Definition: usb_regs.h:446
usbd_ep_clear_stall
void usbd_ep_clear_stall(usb_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status
Definition: usbd_core.c:415
USB_RX
Definition: usb_core.h:94
DEPLEN_PCNT
#define DEPLEN_PCNT
Definition: usb_regs.h:479
usbd_ctltx
usbd_status_enum usbd_ctltx(usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
transmit data on the control channel
Definition: usbd_core.c:312
usb_ep_struct
Definition: usb_core.h:99
USB_DSTAT
#define USB_DSTAT
Definition: usb_regs.h:67
usbd_ctlrx
usbd_status_enum usbd_ctlrx(usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
receive data on the control channel
Definition: usbd_core.c:333
usb_descriptor_endpoint_struct
Definition: usb_std.h:170
usb_dir_enum
usb_dir_enum
Definition: usb_core.h:92
DSTAT_FNRSOF
#define DSTAT_FNRSOF
Definition: usb_regs.h:355
USB_SOFT_DISCONNECT_DISABLE
#define USB_SOFT_DISCONNECT_DISABLE()
Definition: usb_regs.h:602
usbd_status_enum
usbd_status_enum
Definition: usb_core.h:72
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:84
DEPCTL_MPL
#define DEPCTL_MPL
Definition: usb_regs.h:447
USB_DIEPFEINTEN
#define USB_DIEPFEINTEN
Definition: usb_regs.h:74
USB_GLOBAL_INT_DISABLE
#define USB_GLOBAL_INT_DISABLE()
Definition: usb_regs.h:545
usb_core_handle_struct
Definition: usb_core.h:200
usb_descriptor_endpoint_struct::wMaxPacketSize
uint16_t wMaxPacketSize
Definition: usb_std.h:176
usbd_ctlstatus_rx
usbd_status_enum usbd_ctlstatus_rx(usb_core_handle_struct *pudev)
receive status on the control channel
Definition: usbd_core.c:367
DEPCTL_STALL
#define DEPCTL_STALL
Definition: usb_regs.h:440
usbd_ctlstatus_tx
usbd_status_enum usbd_ctlstatus_tx(usb_core_handle_struct *pudev)
transmit status on the control channel
Definition: usbd_core.c:350
usbd_init
void usbd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initailizes the USB device-mode handler stack
Definition: usbd_core.c:22
USB_DOEPxLEN
#define USB_DOEPxLEN(x)
Definition: usb_regs.h:88
NULL
#define NULL
Definition: usb_defines.h:18
USB_GLOBAL_INT_ENABLE
#define USB_GLOBAL_INT_ENABLE()
Definition: usb_regs.h:542
DEPCTL_CNAK
#define DEPCTL_CNAK
Definition: usb_regs.h:438
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:167
DEPCTL_SEVNFRM
#define DEPCTL_SEVNFRM
Definition: usb_regs.h:435
DIEPCTL_TXFNUM
#define DIEPCTL_TXFNUM
Definition: usb_regs.h:439
usbd_ep_rx
void usbd_ep_rx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:161
USB_SOFT_DISCONNECT_ENABLE
#define USB_SOFT_DISCONNECT_ENABLE()
Definition: usb_regs.h:599
usbd_ep_tx
void usbd_ep_tx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:230
USB_STATUS_DEFAULT
#define USB_STATUS_DEFAULT
Definition: usbd_core.h:20
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:47
usbd_core.h
USB device mode core driver header file.
DEPCTL_SD0PID
#define DEPCTL_SD0PID
Definition: usb_regs.h:436
DEPCTL_SODDFRM
#define DEPCTL_SODDFRM
Definition: usb_regs.h:433
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:106
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:86
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:53
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_dma.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_dma.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_dma.h"
13
21 void dma_deinit(dma_channel_enum channelx)
22 {
23 /* disable DMA a channel */
24 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
25 /* reset DMA channel registers */
26 DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE;
27 DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE;
28 DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE;
29 DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE;
30 DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
31 }
32
50 void dma_init(dma_channel_enum channelx, dma_parameter_struct init_struct)
51 {
52 uint32_t ctl;
53
54 dma_channel_disable(channelx);
55
56 /* configure peripheral base address */
57 DMA_CHPADDR(channelx) = init_struct.periph_addr;
58
59 /* configure memory base address */
60 DMA_CHMADDR(channelx) = init_struct.memory_addr;
61
62 /* configure the number of remaining data to be transferred */
63 DMA_CHCNT(channelx) = init_struct.number;
64
65 /* configure peripheral transfer width,memory transfer width,channel priotity */
66 ctl = DMA_CHCTL(channelx);
67 ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
68 ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority);
69 DMA_CHCTL(channelx) = ctl;
70
71 /* configure peripheral increasing mode */
72 if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){
73 DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
74 }else{
75 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
76 }
77
78 /* configure memory increasing mode */
79 if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){
80 DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
81 }else{
82 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
83 }
84
85 /* configure the direction of data transfer */
86 if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){
87 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
88 }else{
89 DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
90 }
91 }
92
100 void dma_circulation_enable(dma_channel_enum channelx)
101 {
102 DMA_CHCTL(channelx) |= DMA_CHXCTL_CMEN;
103 }
104
112 void dma_circulation_disable(dma_channel_enum channelx)
113 {
114 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CMEN;
115 }
116
124 void dma_memory_to_memory_enable(dma_channel_enum channelx)
125 {
126 DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M;
127 }
128
136 void dma_memory_to_memory_disable(dma_channel_enum channelx)
137 {
138 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M;
139 }
140
148 void dma_channel_enable(dma_channel_enum channelx)
149 {
150 DMA_CHCTL(channelx) |= DMA_CHXCTL_CHEN;
151 }
152
160 void dma_channel_disable(dma_channel_enum channelx)
161 {
162 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
163 }
164
173 void dma_periph_address_config(dma_channel_enum channelx, uint32_t address)
174 {
175 DMA_CHPADDR(channelx) = address;
176 }
177
186 void dma_memory_address_config(dma_channel_enum channelx, uint32_t address)
187 {
188 DMA_CHMADDR(channelx) = address;
189 }
190
199 void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number)
200 {
201 DMA_CHCNT(channelx) = (number & DMA_CHANNEL_CNT_MASK);
202 }
203
211 uint32_t dma_transfer_number_get(dma_channel_enum channelx)
212 {
213 return (uint32_t)DMA_CHCNT(channelx);
214 }
215
228 void dma_priority_config(dma_channel_enum channelx, uint32_t priority)
229 {
230 uint32_t ctl;
231
232 /* acquire DMA_CHxCTL register */
233 ctl = DMA_CHCTL(channelx);
234 /* assign regiser */
235 ctl &= ~DMA_CHXCTL_PRIO;
236 ctl |= priority;
237 DMA_CHCTL(channelx) = ctl;
238 }
239
251 void dma_memory_width_config(dma_channel_enum channelx, uint32_t mwidth)
252 {
253 uint32_t ctl;
254
255 /* acquire DMA_CHxCTL register */
256 ctl = DMA_CHCTL(channelx);
257 /* assign regiser */
258 ctl &= ~DMA_CHXCTL_MWIDTH;
259 ctl |= mwidth;
260 DMA_CHCTL(channelx) = ctl;
261 }
262
274 void dma_periph_width_config(dma_channel_enum channelx, uint32_t pwidth)
275 {
276 uint32_t ctl;
277
278 /* acquire DMA_CHxCTL register */
279 ctl = DMA_CHCTL(channelx);
280 /* assign regiser */
281 ctl &= ~DMA_CHXCTL_PWIDTH;
282 ctl |= pwidth;
283 DMA_CHCTL(channelx) = ctl;
284 }
285
293 void dma_memory_increase_enable(dma_channel_enum channelx)
294 {
295 DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
296 }
297
305 void dma_memory_increase_disable(dma_channel_enum channelx)
306 {
307 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
308 }
309
317 void dma_periph_increase_enable(dma_channel_enum channelx)
318 {
319 DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
320 }
321
329 void dma_periph_increase_disable(dma_channel_enum channelx)
330 {
331 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
332 }
333
344 void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction)
345 {
346 if(DMA_PERIPHERAL_TO_MEMORY == direction){
347 DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
348 } else {
349 DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
350 }
351 }
352
366 FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag)
367 {
368 FlagStatus reval;
369
370 if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))){
371 reval = SET;
372 }else{
373 reval = RESET;
374 }
375
376 return reval;
377 }
378
391 void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
392 {
393 DMA_INTC |= DMA_FLAG_ADD(flag, channelx);
394 }
395
408 FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag)
409 {
410 uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
411
412 switch(flag){
413 case DMA_INT_FLAG_FTF:
414 interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
415 interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE;
416 break;
417 case DMA_INT_FLAG_HTF:
418 interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
419 interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE;
420 break;
421 case DMA_INT_FLAG_ERR:
422 interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
423 interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_ERRIE;
424 break;
425 default:
426 break;
427 }
428
429 if(interrupt_flag && interrupt_enable){
430 return SET;
431 }else{
432 return RESET;
433 }
434 }
435
448 void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag)
449 {
450 DMA_INTC |= DMA_FLAG_ADD(flag,channelx);
451 }
452
464 void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source)
465 {
466 DMA_CHCTL(channelx) |= source;
467 }
468
480 void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source)
481 {
482 DMA_CHCTL(channelx) &= ~source;
483 }
DMA_INT_FLAG_FTF
#define DMA_INT_FLAG_FTF
Definition: gd32f3x0_dma.h:140
DMA_CHXCTL_ERRIE
#define DMA_CHXCTL_ERRIE
Definition: gd32f3x0_dma.h:69
DMA_CHXCTL_DIR
#define DMA_CHXCTL_DIR
Definition: gd32f3x0_dma.h:70
DMA_CHCNT_RESET_VALUE
#define DMA_CHCNT_RESET_VALUE
Definition: gd32f3x0_dma.h:117
dma_interrupt_flag_clear
void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag
Definition: gd32f3x0_dma.c:448
dma_periph_increase_disable
void dma_periph_increase_disable(dma_channel_enum channelx)
disable next address increasement algorithm of peripheral
Definition: gd32f3x0_dma.c:329
dma_transfer_direction_config
void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction)
configure the direction of data transfer on the channel
Definition: gd32f3x0_dma.c:344
dma_channel_disable
void dma_channel_disable(dma_channel_enum channelx)
disable DMA channel
Definition: gd32f3x0_dma.c:160
dma_channel_enable
void dma_channel_enable(dma_channel_enum channelx)
enable DMA channel
Definition: gd32f3x0_dma.c:148
dma_interrupt_flag_get
FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag)
check DMA flag and interrupt enable bit is set or not
Definition: gd32f3x0_dma.c:408
dma_deinit
void dma_deinit(dma_channel_enum channelx)
deinitialize DMA a channel registers
Definition: gd32f3x0_dma.c:21
DMA_CHINTF_RESET_VALUE
#define DMA_CHINTF_RESET_VALUE
Definition: gd32f3x0_dma.h:120
dma_transfer_number_get
uint32_t dma_transfer_number_get(dma_channel_enum channelx)
get the number of remaining data to be transferred by the DMA
Definition: gd32f3x0_dma.c:211
dma_parameter_struct::priority
uint32_t priority
Definition: gd32f3x0_dma.h:112
DMA_INT_FLAG_HTF
#define DMA_INT_FLAG_HTF
Definition: gd32f3x0_dma.h:141
dma_parameter_struct::memory_width
uint32_t memory_width
Definition: gd32f3x0_dma.h:108
dma_flag_get
FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag)
check DMA flag is set or not
Definition: gd32f3x0_dma.c:366
dma_transfer_number_config
void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number)
set the number of remaining data to be transferred by the DMA
Definition: gd32f3x0_dma.c:199
dma_parameter_struct::periph_inc
uint8_t periph_inc
Definition: gd32f3x0_dma.h:106
DMA_CHXCTL_PWIDTH
#define DMA_CHXCTL_PWIDTH
Definition: gd32f3x0_dma.h:74
DMA_CHXCTL_MNAGA
#define DMA_CHXCTL_MNAGA
Definition: gd32f3x0_dma.h:73
dma_channel_enum
dma_channel_enum
Definition: gd32f3x0_dma.h:90
dma_init
void dma_init(dma_channel_enum channelx, dma_parameter_struct init_struct)
initialize DMA channel
Definition: gd32f3x0_dma.c:50
dma_memory_to_memory_enable
void dma_memory_to_memory_enable(dma_channel_enum channelx)
enable memory to memory mode
Definition: gd32f3x0_dma.c:124
dma_memory_address_config
void dma_memory_address_config(dma_channel_enum channelx, uint32_t address)
set DMA memory base address
Definition: gd32f3x0_dma.c:186
dma_periph_width_config
void dma_periph_width_config(dma_channel_enum channelx, uint32_t pwidth)
configure transfer data size of peripheral
Definition: gd32f3x0_dma.c:274
DMA_CHCTL_RESET_VALUE
#define DMA_CHCTL_RESET_VALUE
Definition: gd32f3x0_dma.h:116
DMA_PERIPH_INCREASE_ENABLE
#define DMA_PERIPH_INCREASE_ENABLE
Definition: gd32f3x0_dma.h:162
dma_parameter_struct
Definition: gd32f3x0_dma.h:102
dma_parameter_struct::number
uint32_t number
Definition: gd32f3x0_dma.h:111
dma_memory_to_memory_disable
void dma_memory_to_memory_disable(dma_channel_enum channelx)
disable memory to memory mode
Definition: gd32f3x0_dma.c:136
dma_periph_increase_enable
void dma_periph_increase_enable(dma_channel_enum channelx)
enable next address increasement algorithm of peripheral
Definition: gd32f3x0_dma.c:317
DMA_CHPADDR_RESET_VALUE
#define DMA_CHPADDR_RESET_VALUE
Definition: gd32f3x0_dma.h:118
DMA_CHXCTL_PRIO
#define DMA_CHXCTL_PRIO
Definition: gd32f3x0_dma.h:76
DMA_MEMORY_INCREASE_ENABLE
#define DMA_MEMORY_INCREASE_ENABLE
Definition: gd32f3x0_dma.h:166
dma_memory_width_config
void dma_memory_width_config(dma_channel_enum channelx, uint32_t mwidth)
configure transfer data size of memory
Definition: gd32f3x0_dma.c:251
DMA_INTC
#define DMA_INTC
Definition: gd32f3x0_dma.h:22
dma_parameter_struct::periph_width
uint32_t periph_width
Definition: gd32f3x0_dma.h:105
dma_parameter_struct::memory_inc
uint8_t memory_inc
Definition: gd32f3x0_dma.h:109
dma_interrupt_disable
void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source)
disable DMA interrupt
Definition: gd32f3x0_dma.c:480
dma_circulation_enable
void dma_circulation_enable(dma_channel_enum channelx)
enable DMA circulation mode
Definition: gd32f3x0_dma.c:100
dma_parameter_struct::direction
uint8_t direction
Definition: gd32f3x0_dma.h:110
dma_memory_increase_enable
void dma_memory_increase_enable(dma_channel_enum channelx)
enable next address increasement algorithm of memory
Definition: gd32f3x0_dma.c:293
dma_periph_address_config
void dma_periph_address_config(dma_channel_enum channelx, uint32_t address)
set DMA peripheral base address
Definition: gd32f3x0_dma.c:173
dma_interrupt_enable
void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source)
enable DMA interrupt
Definition: gd32f3x0_dma.c:464
DMA_CHMADDR_RESET_VALUE
#define DMA_CHMADDR_RESET_VALUE
Definition: gd32f3x0_dma.h:119
DMA_CHXCTL_PNAGA
#define DMA_CHXCTL_PNAGA
Definition: gd32f3x0_dma.h:72
DMA_CHCNT
#define DMA_CHCNT(channel)
Definition: gd32f3x0_dma.h:133
DMA_CHXCTL_HTFIE
#define DMA_CHXCTL_HTFIE
Definition: gd32f3x0_dma.h:68
DMA_CHMADDR
#define DMA_CHMADDR(channel)
Definition: gd32f3x0_dma.h:135
DMA_CHXCTL_M2M
#define DMA_CHXCTL_M2M
Definition: gd32f3x0_dma.h:77
gd32f3x0_dma.h
definitions for the DMA
DMA_CHANNEL_CNT_MASK
#define DMA_CHANNEL_CNT_MASK
Definition: gd32f3x0_dma.h:189
dma_priority_config
void dma_priority_config(dma_channel_enum channelx, uint32_t priority)
configure priority level of DMA channel
Definition: gd32f3x0_dma.c:228
dma_flag_clear
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag
Definition: gd32f3x0_dma.c:391
DMA_CHXCTL_FTFIE
#define DMA_CHXCTL_FTFIE
Definition: gd32f3x0_dma.h:67
DMA_CHXCTL_CHEN
#define DMA_CHXCTL_CHEN
Definition: gd32f3x0_dma.h:66
dma_memory_increase_disable
void dma_memory_increase_disable(dma_channel_enum channelx)
disable next address increasement algorithm of memory
Definition: gd32f3x0_dma.c:305
DMA_CHXCTL_CMEN
#define DMA_CHXCTL_CMEN
Definition: gd32f3x0_dma.h:71
DMA_INT_FLAG_ERR
#define DMA_INT_FLAG_ERR
Definition: gd32f3x0_dma.h:142
DMA_FLAG_ADD
#define DMA_FLAG_ADD(flag, shift)
Definition: gd32f3x0_dma.h:123
DMA_INTF
#define DMA_INTF
Definition: gd32f3x0_dma.h:21
DMA_PERIPHERAL_TO_MEMORY
#define DMA_PERIPHERAL_TO_MEMORY
Definition: gd32f3x0_dma.h:157
DMA_CHCTL
#define DMA_CHCTL(channel)
Definition: gd32f3x0_dma.h:132
dma_circulation_disable
void dma_circulation_disable(dma_channel_enum channelx)
disable DMA circulation mode
Definition: gd32f3x0_dma.c:112
dma_parameter_struct::periph_addr
uint32_t periph_addr
Definition: gd32f3x0_dma.h:104
DMA_CHPADDR
#define DMA_CHPADDR(channel)
Definition: gd32f3x0_dma.h:134
DMA_CHXCTL_MWIDTH
#define DMA_CHXCTL_MWIDTH
Definition: gd32f3x0_dma.h:75
dma_parameter_struct::memory_addr
uint32_t memory_addr
Definition: gd32f3x0_dma.h:107
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_tsi.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_tsi.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_tsi.h"
13
20 void tsi_deinit(void)
21 {
22 rcu_periph_reset_enable(RCU_TSIRST);
23 rcu_periph_reset_disable(RCU_TSIRST);
24 }
25
60 void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number)
61 {
62 uint32_t ctl0,ctl1;
63 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
64 if(TSI_CTCDIV_DIV256 > prescaler){
65 /* config TSI_CTL0 */
66 ctl0 = TSI_CTL0;
67 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
68 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT|TSI_CTL0_MCN);
69 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration|max_number);
70 TSI_CTL0 = ctl0;
71
72 /* config TSI_CTL1 */
73 ctl1 = TSI_CTL1;
74 ctl1 &= ~TSI_CTL1_CTCDIV;
75 TSI_CTL1 = ctl1;
76 }else{
77 /* config TSI_CTL0 */
78 ctl0 = TSI_CTL0;
79 prescaler &= ~0x08U;
80 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
81 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT|TSI_CTL0_MCN);
82 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration|max_number);
83 TSI_CTL0 = ctl0;
84
85 /* config TSI_CTL1 */
86 ctl1 = TSI_CTL1;
87 ctl1 |= TSI_CTL1_CTCDIV;
88 TSI_CTL1 = ctl1;
89 }
90 }
91 }
92
100 void tsi_sample_pin_enable(uint32_t sample)
101 {
102 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
103 TSI_SAMPCFG |= sample;
104 }
105 }
106
114 void tsi_sample_pin_disable(uint32_t sample)
115 {
116 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
117 TSI_SAMPCFG &= ~sample;
118 }
119 }
120
128 void tsi_channel_pin_enable(uint32_t channel)
129 {
130 TSI_CHCFG |= channel;
131 }
132
140 void tsi_channel_pin_disable(uint32_t channel)
141 {
142 TSI_CHCFG &= ~channel;
143 }
144
171 void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration)
172 {
173 uint32_t ctl0,ctl1;
174 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
175 if(TSI_CTCDIV_DIV256 > prescaler){
176 /* config TSI_CTL0 */
177 ctl0 = TSI_CTL0;
178 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
179 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT);
180 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration);
181 TSI_CTL0 = ctl0;
182
183 /* config TSI_CTL1 */
184 ctl1 = TSI_CTL1;
185 ctl1 &= ~TSI_CTL1_CTCDIV;
186 TSI_CTL1 = ctl1;
187 }else{
188 /* config TSI_CTL */
189 ctl0 = TSI_CTL0;
190 prescaler &= ~0x08U;
191 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
192 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT);
193 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration);
194 TSI_CTL0 = ctl0;
195
196 /* config TSI_CTL2 */
197 ctl1 = TSI_CTL1;
198 ctl1 |= TSI_CTL1_CTCDIV;
199 TSI_CTL1 = ctl1;
200 }
201 }
202 }
203
210 void tsi_sofeware_mode_config(void)
211 {
212 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
213 TSI_CTL0 &= ~TSI_CTL0_TRGMOD;
214 }
215 }
216
225 void tsi_hardware_mode_config(uint8_t trigger_edge)
226 {
227 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
228 /*enable hardware mode*/
229 TSI_CTL0 |= TSI_CTL0_TRGMOD;
230 /*configure the edge type in hardware trigger mode*/
231 if(TSI_FALLING_TRIGGER == trigger_edge){
232 TSI_CTL0 &= ~TSI_CTL0_EGSEL;
233 }else{
234 TSI_CTL0 |= TSI_CTL0_EGSEL;
235 }
236 }
237 }
238
247 void tsi_pin_mode_config(uint8_t pin_mode)
248 {
249 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
250 if(TSI_OUTPUT_LOW == pin_mode){
251 TSI_CTL0 &= ~TSI_CTL0_PINMOD;
252 }else{
253 TSI_CTL0 |= TSI_CTL0_PINMOD;
254 }
255 }
256 }
257
271 void tsi_max_number_config(uint32_t max_number)
272 {
273 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
274 uint32_t maxnum;
275 maxnum = TSI_CTL0;
276 /*configure the max cycle number of a charge-transfer sequence*/
277 maxnum &= ~TSI_CTL0_MCN;
278 maxnum |= max_number;
279 TSI_CTL0 = maxnum;
280 }
281 }
282
289 void tsi_software_start(void)
290 {
291 TSI_CTL0 |= TSI_CTL0_TSIS;
292 }
293
300 void tsi_software_stop(void)
301 {
302 TSI_CTL0 &= ~TSI_CTL0_TSIS;
303 }
304
311 void tsi_enable(void)
312 {
313 TSI_CTL0 |= TSI_CTL0_TSIEN;
314 }
315
322 void tsi_disable(void)
323 {
324 TSI_CTL0 &= ~TSI_CTL0_TSIEN;
325 }
326
345 void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration)
346 {
347 uint32_t ctl0,ctl1;
348 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
349 if(DISABLE == extend){
350 /*disable extend charge state*/
351 TSI_CTL0 &= ~TSI_CTL0_ECEN;
352 }else{
353 if(TSI_EXTEND_DIV3 > prescaler){
354 /*configure extend charge state maximum duration time*/
355 ctl0 = TSI_CTL0;
356 ctl0 &= ~TSI_CTL0_ECDT;
357 ctl0 |= TSI_EXTENDMAX((max_duration-1U));
358 TSI_CTL0 = ctl0;
359 /*configure ECCLK clock division factor*/
360 ctl0 = TSI_CTL0;
361 ctl0 &= ~TSI_CTL0_ECDIV;
362 ctl0 |= (uint32_t)prescaler<<15U;
363 TSI_CTL0 = ctl0;
364 /*enable extend charge state*/
365 TSI_CTL0 |= TSI_CTL0_ECEN;
366 }else{
367 /*configure extend charge state maximum duration time*/
368 ctl0 = TSI_CTL0;
369 ctl0 &= ~TSI_CTL0_ECDT;
370 ctl0 |= TSI_EXTENDMAX((max_duration-1U));
371 TSI_CTL0 = ctl0;
372 /*configure ECCLK clock division factor*/
373 ctl0 = TSI_CTL0;
374 ctl0 &= ~TSI_CTL0_ECDIV;
375 ctl0 |= (prescaler & 0x01U)<<15U;
376 TSI_CTL0 = ctl0;
377 ctl1 = TSI_CTL1;
378 ctl1 &= ~TSI_CTL1_ECDIV;
379 ctl1 |= (prescaler & 0x06U)<<28U;
380 TSI_CTL1 = ctl1;
381 /*enable extend charge state*/
382 TSI_CTL0 |= TSI_CTL0_ECEN;
383 }
384 }
385 }
386 }
387
396 void tsi_interrupt_enable(uint32_t source)
397 {
398 TSI_INTEN |= source;
399 }
400
409 void tsi_interrupt_disable(uint32_t source)
410 {
411 TSI_INTEN &= ~source;
412 }
413
422 void tsi_interrupt_flag_clear(uint32_t flag)
423 {
424 TSI_INTC |= flag;
425 }
426
435 FlagStatus tsi_interrupt_flag_get(uint32_t flag)
436 {
437 FlagStatus flag_status;
438 uint32_t tsi_inten;
439 tsi_inten = TSI_INTEN;
440 if(TSI_INT_FLAG_CTCF == flag){
441 if(TSI_INT_CCTCF & tsi_inten){
442 if(TSI_INTF & flag){
443 flag_status = SET;
444 }else{
445 flag_status = RESET;
446 }
447 }else{
448 flag_status = RESET;
449 }
450 }else if(TSI_INT_FLAG_MNERR == flag){
451 if(TSI_INT_MNERR & tsi_inten){
452 if(TSI_INTF & flag){
453 flag_status = SET;
454 }else{
455 flag_status = RESET;
456 }
457 }else{
458 flag_status = RESET;
459 }
460 }else{
461 flag_status = RESET;
462 }
463 return flag_status;
464 }
465
474 void tsi_flag_clear(uint32_t flag)
475 {
476 TSI_INTC |= flag;
477 }
478
487 FlagStatus tsi_flag_get(uint32_t flag)
488 {
489 FlagStatus flag_status;
490 if(TSI_INTF & flag){
491 flag_status = SET;
492 }else{
493 flag_status = RESET;
494 }
495 return flag_status;
496 }
497
505 void tsi_hysteresis_on(uint32_t group_pin)
506 {
507 TSI_PHM |= group_pin;
508 }
509
517 void tsi_hysteresis_off(uint32_t group_pin)
518 {
519 TSI_PHM &= ~group_pin;
520 }
521
529 void tsi_analog_on(uint32_t group_pin)
530 {
531 TSI_ASW |= group_pin;
532 }
533
541 void tsi_analog_off(uint32_t group_pin)
542 {
543 TSI_ASW &= ~group_pin;
544 }
545
553 void tsi_group_enable(uint32_t group)
554 {
555 TSI_GCTL |= group;
556 }
557
565 void tsi_group_disable(uint32_t group)
566 {
567 TSI_GCTL &= ~group;
568 }
569
577 FlagStatus tsi_group_status_get(uint32_t group)
578 {
579 FlagStatus flag_status;
580 if(TSI_GCTL & group){
581 flag_status = SET;
582 }else{
583 flag_status = RESET;
584 }
585 return flag_status;
586 }
587
594 uint16_t tsi_group0_cycle_get(void)
595 {
596 return (uint16_t)TSI_G0CYCN;
597 }
598
605 uint16_t tsi_group1_cycle_get(void)
606 {
607 return (uint16_t)TSI_G1CYCN;
608 }
609
616 uint16_t tsi_group2_cycle_get(void)
617 {
618 return (uint16_t)TSI_G2CYCN;
619 }
620
627 uint16_t tsi_group3_cycle_get(void)
628 {
629 return (uint16_t)TSI_G3CYCN;
630 }
631
638 uint16_t tsi_group4_cycle_get(void)
639 {
640 return (uint16_t)TSI_G4CYCN;
641 }
642
649 uint16_t tsi_group5_cycle_get(void)
650 {
651 return (uint16_t)TSI_G5CYCN;
652 }
TSI_CTL0_ECDIV
#define TSI_CTL0_ECDIV
Definition: gd32f3x0_tsi.h:47
TSI_INTEN
#define TSI_INTEN
Definition: gd32f3x0_tsi.h:22
tsi_init
void tsi_init(uint32_t prescaler, uint32_t charge_duration, uint32_t transfer_duration, uint32_t max_number)
initialize TSI plus prescaler,charge plus,transfer plus,max cycle number
Definition: gd32f3x0_tsi.c:60
tsi_group4_cycle_get
uint16_t tsi_group4_cycle_get(void)
get the cycle number for group4 as soon as a charge-transfer sequence completes
Definition: gd32f3x0_tsi.c:638
TSI_CTL0_CTCDIV
#define TSI_CTL0_CTCDIV
Definition: gd32f3x0_tsi.h:46
TSI_G2CYCN
#define TSI_G2CYCN
Definition: gd32f3x0_tsi.h:32
TSI_CTL0_ECDT
#define TSI_CTL0_ECDT
Definition: gd32f3x0_tsi.h:49
tsi_pin_mode_config
void tsi_pin_mode_config(uint8_t pin_mode)
configure TSI pin mode when charge-transfer sequence is IDLE
Definition: gd32f3x0_tsi.c:247
TSI_CTL0_ECEN
#define TSI_CTL0_ECEN
Definition: gd32f3x0_tsi.h:48
TSI_G4CYCN
#define TSI_G4CYCN
Definition: gd32f3x0_tsi.h:34
tsi_sample_pin_disable
void tsi_sample_pin_disable(uint32_t sample)
disable sample pin
Definition: gd32f3x0_tsi.c:114
TSI_GCTL
#define TSI_GCTL
Definition: gd32f3x0_tsi.h:29
RCU_TSIRST
Definition: gd32f3x0_rcu.h:331
tsi_group_status_get
FlagStatus tsi_group_status_get(uint32_t group)
get group complete status
Definition: gd32f3x0_tsi.c:577
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
TSI_INT_MNERR
#define TSI_INT_MNERR
Definition: gd32f3x0_tsi.h:67
tsi_group_disable
void tsi_group_disable(uint32_t group)
disbale group
Definition: gd32f3x0_tsi.c:565
tsi_hardware_mode_config
void tsi_hardware_mode_config(uint8_t trigger_edge)
configure TSI triggering by hardware
Definition: gd32f3x0_tsi.c:225
TSI_CTL0_TSIEN
#define TSI_CTL0_TSIEN
Definition: gd32f3x0_tsi.h:40
TSI_CTL0_MCN
#define TSI_CTL0_MCN
Definition: gd32f3x0_tsi.h:45
TSI_INTF
#define TSI_INTF
Definition: gd32f3x0_tsi.h:24
TSI_OUTPUT_LOW
#define TSI_OUTPUT_LOW
Definition: gd32f3x0_tsi.h:292
tsi_interrupt_flag_clear
void tsi_interrupt_flag_clear(uint32_t flag)
clear TSI interrupt flag
Definition: gd32f3x0_tsi.c:422
TSI_CTL0_EGSEL
#define TSI_CTL0_EGSEL
Definition: gd32f3x0_tsi.h:43
TSI_INT_CCTCF
#define TSI_INT_CCTCF
Definition: gd32f3x0_tsi.h:66
TSI_CTL1_ECDIV
#define TSI_CTL1_ECDIV
Definition: gd32f3x0_tsi.h:205
TSI_PHM
#define TSI_PHM
Definition: gd32f3x0_tsi.h:25
gd32f3x0_tsi.h
definitions for the TSI
TSI_CTL0_TRGMOD
#define TSI_CTL0_TRGMOD
Definition: gd32f3x0_tsi.h:42
tsi_enable
void tsi_enable(void)
enable TSI module
Definition: gd32f3x0_tsi.c:311
tsi_interrupt_enable
void tsi_interrupt_enable(uint32_t source)
enable TSI interrupt
Definition: gd32f3x0_tsi.c:396
TSI_INTC
#define TSI_INTC
Definition: gd32f3x0_tsi.h:23
TSI_ASW
#define TSI_ASW
Definition: gd32f3x0_tsi.h:26
TSI_INT_FLAG_MNERR
#define TSI_INT_FLAG_MNERR
Definition: gd32f3x0_tsi.h:71
tsi_sofeware_mode_config
void tsi_sofeware_mode_config(void)
configure TSI triggering by software
Definition: gd32f3x0_tsi.c:210
TSI_CTL0
#define TSI_CTL0
Definition: gd32f3x0_tsi.h:21
tsi_group3_cycle_get
uint16_t tsi_group3_cycle_get(void)
get the cycle number for group3 as soon as a charge-transfer sequence completes
Definition: gd32f3x0_tsi.c:627
tsi_software_stop
void tsi_software_stop(void)
stop a charge-transfer sequence when TSI is in software trigger mode
Definition: gd32f3x0_tsi.c:300
TSI_INT_FLAG_CTCF
#define TSI_INT_FLAG_CTCF
Definition: gd32f3x0_tsi.h:70
TSI_CTL0_PINMOD
#define TSI_CTL0_PINMOD
Definition: gd32f3x0_tsi.h:44
tsi_sample_pin_enable
void tsi_sample_pin_enable(uint32_t sample)
enable sample pin
Definition: gd32f3x0_tsi.c:100
TSI_SAMPCFG
#define TSI_SAMPCFG
Definition: gd32f3x0_tsi.h:27
tsi_hysteresis_off
void tsi_hysteresis_off(uint32_t group_pin)
switch off hysteresis pin
Definition: gd32f3x0_tsi.c:517
tsi_group0_cycle_get
uint16_t tsi_group0_cycle_get(void)
get the cycle number for group0 as soon as a charge-transfer sequence completes
Definition: gd32f3x0_tsi.c:594
tsi_analog_off
void tsi_analog_off(uint32_t group_pin)
switch off analog pin
Definition: gd32f3x0_tsi.c:541
tsi_analog_on
void tsi_analog_on(uint32_t group_pin)
switch on analog pin
Definition: gd32f3x0_tsi.c:529
tsi_deinit
void tsi_deinit(void)
reset TSI peripheral
Definition: gd32f3x0_tsi.c:20
TSI_CTL0_CDT
#define TSI_CTL0_CDT
Definition: gd32f3x0_tsi.h:51
tsi_group1_cycle_get
uint16_t tsi_group1_cycle_get(void)
get the cycle number for group1 as soon as a charge-transfer sequence completes
Definition: gd32f3x0_tsi.c:605
tsi_flag_clear
void tsi_flag_clear(uint32_t flag)
clear flag
Definition: gd32f3x0_tsi.c:474
TSI_CTL0_TSIS
#define TSI_CTL0_TSIS
Definition: gd32f3x0_tsi.h:41
TSI_G3CYCN
#define TSI_G3CYCN
Definition: gd32f3x0_tsi.h:33
tsi_group2_cycle_get
uint16_t tsi_group2_cycle_get(void)
get the cycle number for group2 as soon as a charge-transfer sequence completes
Definition: gd32f3x0_tsi.c:616
tsi_extend_charge_config
void tsi_extend_charge_config(ControlStatus extend, uint8_t prescaler, uint32_t max_duration)
configure extend charge state
Definition: gd32f3x0_tsi.c:345
TSI_CTCDIV_DIV256
#define TSI_CTCDIV_DIV256
Definition: gd32f3x0_tsi.h:217
TSI_CHCFG
#define TSI_CHCFG
Definition: gd32f3x0_tsi.h:28
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
TSI_CTL1_CTCDIV
#define TSI_CTL1_CTCDIV
Definition: gd32f3x0_tsi.h:204
tsi_group5_cycle_get
uint16_t tsi_group5_cycle_get(void)
get the cycle number for group5 as soon as a charge-transfer sequence completes
Definition: gd32f3x0_tsi.c:649
tsi_max_number_config
void tsi_max_number_config(uint32_t max_number)
configure the max cycle number of a charge-transfer sequence
Definition: gd32f3x0_tsi.c:271
TSI_G1CYCN
#define TSI_G1CYCN
Definition: gd32f3x0_tsi.h:31
tsi_software_start
void tsi_software_start(void)
start a charge-transfer sequence when TSI is in software trigger mode
Definition: gd32f3x0_tsi.c:289
tsi_plus_config
void tsi_plus_config(uint32_t prescaler, uint32_t charge_duration, uint32_t transfer_duration)
configure charge plus and transfer plus
Definition: gd32f3x0_tsi.c:171
tsi_channel_pin_disable
void tsi_channel_pin_disable(uint32_t channel)
disable channel pin
Definition: gd32f3x0_tsi.c:140
tsi_hysteresis_on
void tsi_hysteresis_on(uint32_t group_pin)
switch on hysteresis pin
Definition: gd32f3x0_tsi.c:505
tsi_interrupt_flag_get
FlagStatus tsi_interrupt_flag_get(uint32_t flag)
get TSI interrupt flag
Definition: gd32f3x0_tsi.c:435
TSI_CTL0_CTDT
#define TSI_CTL0_CTDT
Definition: gd32f3x0_tsi.h:50
TSI_CTL1
#define TSI_CTL1
Definition: gd32f3x0_tsi.h:36
tsi_group_enable
void tsi_group_enable(uint32_t group)
enbale group
Definition: gd32f3x0_tsi.c:553
TSI_FALLING_TRIGGER
#define TSI_FALLING_TRIGGER
Definition: gd32f3x0_tsi.h:288
tsi_disable
void tsi_disable(void)
disable TSI module
Definition: gd32f3x0_tsi.c:322
TSI_G5CYCN
#define TSI_G5CYCN
Definition: gd32f3x0_tsi.h:35
TSI_G0CYCN
#define TSI_G0CYCN
Definition: gd32f3x0_tsi.h:30
tsi_interrupt_disable
void tsi_interrupt_disable(uint32_t source)
disable TSI interrupt
Definition: gd32f3x0_tsi.c:409
tsi_flag_get
FlagStatus tsi_flag_get(uint32_t flag)
get flag
Definition: gd32f3x0_tsi.c:487
tsi_channel_pin_enable
void tsi_channel_pin_enable(uint32_t channel)
enable channel pin
Definition: gd32f3x0_tsi.c:128
TSI_EXTENDMAX
#define TSI_EXTENDMAX(regval)
Definition: gd32f3x0_tsi.h:285
TSI_EXTEND_DIV3
#define TSI_EXTEND_DIV3
Definition: gd32f3x0_tsi.h:277
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_cmp.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_cmp.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_cmp.h"
13
20 void cmp_deinit(void)
21 {
22 CMP_CS = ((uint32_t)0x00000000U);
23 }
24
51 void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis)
52 {
53 if(CMP0 == cmp_periph){
54 /* initialize comparator 0 mode */
55 CMP_CS |= CS_CMP0M(operating_mode) | CS_CMP0MSEL(inverting_input) | CS_CMP0HST(output_hysteresis);
56 }else{
57 /* initialize comparator 1 mode */
58 CMP_CS |= CS_CMP1M(operating_mode) | CS_CMP1MSEL(inverting_input) | CS_CMP1HST(output_hysteresis);
59 }
60 }
61
82 void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity)
83 {
84 /* initialize comparator 0 output */
85 if(CMP0 == cmp_periph){
86 CMP_CS |= CS_CMP0OSEL(output_slection);
87 /* output polarity */
88 if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
89 CMP_CS |= CMP_CS_CMP0PL;
90 }else{
91 CMP_CS &= ~CMP_CS_CMP0PL;
92 }
93 }else{
94 CMP_CS |= CS_CMP1OSEL(output_slection);
95
96 if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
97 CMP_CS |= CMP_CS_CMP1PL;
98 }else{
99 CMP_CS &= ~CMP_CS_CMP1PL;
100 }
101 }
102 }
103
112 void cmp_enable(uint32_t cmp_periph)
113 {
114 if(CMP0 == cmp_periph){
115 CMP_CS |= CMP_CS_CMP0EN;
116 }else{
117 CMP_CS |= CMP_CS_CMP1EN;
118 }
119 }
120
129 void cmp_disable(uint32_t cmp_periph)
130 {
131 if(CMP0 == cmp_periph){
132 CMP_CS &= ~CMP_CS_CMP0EN;
133 }else{
134 CMP_CS &= ~CMP_CS_CMP1EN;
135 }
136 }
137
144 void cmp_switch_enable(void)
145 {
146 CMP_CS |= CMP_CS_CMP0SW;
147 }
148
155 void cmp_switch_disable(void)
156 {
157 CMP_CS &= ~CMP_CS_CMP0SW;
158 }
159
168 uint32_t cmp_output_level_get(uint32_t cmp_periph)
169 {
170 if(CMP0 == cmp_periph){
171 if(CMP_CS & CMP_CS_CMP0O){
172 return CMP_OUTPUTLEVEL_HIGH;
173 }else{
174 return CMP_OUTPUTLEVEL_LOW;
175 }
176 }else{
177 if(CMP_CS & CMP_CS_CMP1O){
178 return CMP_OUTPUTLEVEL_HIGH;
179 }else{
180 return CMP_OUTPUTLEVEL_LOW;
181 }
182 }
183 }
184
191 void cmp_window_enable(void)
192 {
193 CMP_CS |= CMP_CS_WNDEN;
194 }
195
202 void cmp_window_disable(void)
203 {
204 CMP_CS &= ~CMP_CS_WNDEN;
205 }
206
215 void cmp_lock_enable(uint32_t cmp_periph)
216 {
217 if(CMP0 == cmp_periph){
218 CMP_CS |= CMP_CS_CMP0LK;
219 }else{
220 CMP_CS |= CMP_CS_CMP1LK;
221 }
222 }
223
232 void cmp_lock_disable(uint32_t cmp_periph)
233 {
234 if(CMP0 == cmp_periph){
235 CMP_CS &= ~CMP_CS_CMP0LK;
236 }else{
237 CMP_CS &= ~CMP_CS_CMP1LK;
238 }
239 }
cmp_switch_disable
void cmp_switch_disable(void)
disable comparator switch
Definition: gd32f3x0_cmp.c:155
cmp_window_disable
void cmp_window_disable(void)
disable the window mode
Definition: gd32f3x0_cmp.c:202
cmp_output_init
void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity)
initialize comparator output
Definition: gd32f3x0_cmp.c:82
operating_mode_enum
operating_mode_enum
Definition: gd32f3x0_cmp.h:45
CS_CMP0MSEL
#define CS_CMP0MSEL(regval)
Definition: gd32f3x0_cmp.h:91
cmp_lock_disable
void cmp_lock_disable(uint32_t cmp_periph)
unlock the comparator
Definition: gd32f3x0_cmp.c:232
CMP_CS_CMP0O
#define CMP_CS_CMP0O
Definition: gd32f3x0_cmp.h:31
cmp_disable
void cmp_disable(uint32_t cmp_periph)
disable comparator
Definition: gd32f3x0_cmp.c:129
CMP_OUTPUTLEVEL_LOW
#define CMP_OUTPUTLEVEL_LOW
Definition: gd32f3x0_cmp.h:159
CMP_CS_CMP0EN
#define CMP_CS_CMP0EN
Definition: gd32f3x0_cmp.h:24
CMP0
#define CMP0
Definition: gd32f3x0_cmp.h:154
cmp_deinit
void cmp_deinit(void)
deinitialize comparator
Definition: gd32f3x0_cmp.c:20
CMP_CS_CMP0PL
#define CMP_CS_CMP0PL
Definition: gd32f3x0_cmp.h:29
CMP_CS_CMP1LK
#define CMP_CS_CMP1LK
Definition: gd32f3x0_cmp.h:41
CMP_CS_WNDEN
#define CMP_CS_WNDEN
Definition: gd32f3x0_cmp.h:36
gd32f3x0_cmp.h
definitions for the CMP
CMP_OUTPUTLEVEL_HIGH
#define CMP_OUTPUTLEVEL_HIGH
Definition: gd32f3x0_cmp.h:158
CMP_CS
#define CMP_CS
Definition: gd32f3x0_cmp.h:21
CS_CMP0OSEL
#define CS_CMP0OSEL(regval)
Definition: gd32f3x0_cmp.h:101
cmp_lock_enable
void cmp_lock_enable(uint32_t cmp_periph)
lock the comparator
Definition: gd32f3x0_cmp.c:215
CS_CMP1HST
#define CS_CMP1HST(regval)
Definition: gd32f3x0_cmp.h:147
cmp_output_level_get
uint32_t cmp_output_level_get(uint32_t cmp_periph)
get output level
Definition: gd32f3x0_cmp.c:168
CS_CMP0M
#define CS_CMP0M(regval)
Definition: gd32f3x0_cmp.h:84
CMP_OUTPUT_POLARITY_INVERTED
#define CMP_OUTPUT_POLARITY_INVERTED
Definition: gd32f3x0_cmp.h:162
CMP_CS_CMP1O
#define CMP_CS_CMP1O
Definition: gd32f3x0_cmp.h:40
cmp_switch_enable
void cmp_switch_enable(void)
enable comparator switch
Definition: gd32f3x0_cmp.c:144
CMP_CS_CMP1EN
#define CMP_CS_CMP1EN
Definition: gd32f3x0_cmp.h:33
cmp_mode_init
void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis)
initialize comparator mode
Definition: gd32f3x0_cmp.c:51
CS_CMP1M
#define CS_CMP1M(regval)
Definition: gd32f3x0_cmp.h:119
CS_CMP0HST
#define CS_CMP0HST(regval)
Definition: gd32f3x0_cmp.h:112
cmp_enable
void cmp_enable(uint32_t cmp_periph)
enable comparator
Definition: gd32f3x0_cmp.c:112
cmp_window_enable
void cmp_window_enable(void)
enable the window mode
Definition: gd32f3x0_cmp.c:191
CMP_CS_CMP0LK
#define CMP_CS_CMP0LK
Definition: gd32f3x0_cmp.h:32
cmp_hysteresis_enum
cmp_hysteresis_enum
Definition: gd32f3x0_cmp.h:64
inverting_input_enum
inverting_input_enum
Definition: gd32f3x0_cmp.h:53
cmp_output_enum
cmp_output_enum
Definition: gd32f3x0_cmp.h:72
CS_CMP1MSEL
#define CS_CMP1MSEL(regval)
Definition: gd32f3x0_cmp.h:126
CMP_CS_CMP1PL
#define CMP_CS_CMP1PL
Definition: gd32f3x0_cmp.h:38
CMP_CS_CMP0SW
#define CMP_CS_CMP0SW
Definition: gd32f3x0_cmp.h:25
CS_CMP1OSEL
#define CS_CMP1OSEL(regval)
Definition: gd32f3x0_cmp.h:136
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_exti.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_exti.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_EXTI_H
13 #define GD32F3X0_EXTI_H
14
15 #include "gd32f3x0.h"
16
17 /* EXTI definitions */
18 #define EXTI EXTI_BASE
19
20 /* registers definitions */
21 #define EXTI_INTEN REG32(EXTI + 0x00U)
22 #define EXTI_EVEN REG32(EXTI + 0x04U)
23 #define EXTI_RTEN REG32(EXTI + 0x08U)
24 #define EXTI_FTEN REG32(EXTI + 0x0CU)
25 #define EXTI_SWIEV REG32(EXTI + 0x10U)
26 #define EXTI_PD REG32(EXTI + 0x14U)
28 /* bits definitions */
29 /* EXTI_INTEN */
30 #define EXTI_INTEN_INTEN0 BIT(0)
31 #define EXTI_INTEN_INTEN1 BIT(1)
32 #define EXTI_INTEN_INTEN2 BIT(2)
33 #define EXTI_INTEN_INTEN3 BIT(3)
34 #define EXTI_INTEN_INTEN4 BIT(4)
35 #define EXTI_INTEN_INTEN5 BIT(5)
36 #define EXTI_INTEN_INTEN6 BIT(6)
37 #define EXTI_INTEN_INTEN7 BIT(7)
38 #define EXTI_INTEN_INTEN8 BIT(8)
39 #define EXTI_INTEN_INTEN9 BIT(9)
40 #define EXTI_INTEN_INTEN10 BIT(10)
41 #define EXTI_INTEN_INTEN11 BIT(11)
42 #define EXTI_INTEN_INTEN12 BIT(12)
43 #define EXTI_INTEN_INTEN13 BIT(13)
44 #define EXTI_INTEN_INTEN14 BIT(14)
45 #define EXTI_INTEN_INTEN15 BIT(15)
46 #define EXTI_INTEN_INTEN16 BIT(16)
47 #define EXTI_INTEN_INTEN17 BIT(17)
48 #define EXTI_INTEN_INTEN18 BIT(18)
49 #define EXTI_INTEN_INTEN19 BIT(19)
50 #define EXTI_INTEN_INTEN20 BIT(20)
51 #define EXTI_INTEN_INTEN21 BIT(21)
52 #define EXTI_INTEN_INTEN22 BIT(22)
53 #define EXTI_INTEN_INTEN23 BIT(23)
54 #define EXTI_INTEN_INTEN24 BIT(24)
55 #define EXTI_INTEN_INTEN25 BIT(25)
56 #define EXTI_INTEN_INTEN26 BIT(26)
57 #define EXTI_INTEN_INTEN27 BIT(27)
59 /* EXTI_EVEN */
60 #define EXTI_EVEN_EVEN0 BIT(0)
61 #define EXTI_EVEN_EVEN1 BIT(1)
62 #define EXTI_EVEN_EVEN2 BIT(2)
63 #define EXTI_EVEN_EVEN3 BIT(3)
64 #define EXTI_EVEN_EVEN4 BIT(4)
65 #define EXTI_EVEN_EVEN5 BIT(5)
66 #define EXTI_EVEN_EVEN6 BIT(6)
67 #define EXTI_EVEN_EVEN7 BIT(7)
68 #define EXTI_EVEN_EVEN8 BIT(8)
69 #define EXTI_EVEN_EVEN9 BIT(9)
70 #define EXTI_EVEN_EVEN10 BIT(10)
71 #define EXTI_EVEN_EVEN11 BIT(11)
72 #define EXTI_EVEN_EVEN12 BIT(12)
73 #define EXTI_EVEN_EVEN13 BIT(13)
74 #define EXTI_EVEN_EVEN14 BIT(14)
75 #define EXTI_EVEN_EVEN15 BIT(15)
76 #define EXTI_EVEN_EVEN16 BIT(16)
77 #define EXTI_EVEN_EVEN17 BIT(17)
78 #define EXTI_EVEN_EVEN18 BIT(18)
79 #define EXTI_EVEN_EVEN19 BIT(19)
80 #define EXTI_EVEN_EVEN20 BIT(20)
81 #define EXTI_EVEN_EVEN21 BIT(21)
82 #define EXTI_EVEN_EVEN22 BIT(22)
83 #define EXTI_EVEN_EVEN23 BIT(23)
84 #define EXTI_EVEN_EVEN24 BIT(24)
85 #define EXTI_EVEN_EVEN25 BIT(25)
86 #define EXTI_EVEN_EVEN26 BIT(26)
87 #define EXTI_EVEN_EVEN27 BIT(27)
89 /* EXTI_RTEN */
90 #define EXTI_RTEN_RTEN0 BIT(0)
91 #define EXTI_RTEN_RTEN1 BIT(1)
92 #define EXTI_RTEN_RTEN2 BIT(2)
93 #define EXTI_RTEN_RTEN3 BIT(3)
94 #define EXTI_RTEN_RTEN4 BIT(4)
95 #define EXTI_RTEN_RTEN5 BIT(5)
96 #define EXTI_RTEN_RTEN6 BIT(6)
97 #define EXTI_RTEN_RTEN7 BIT(7)
98 #define EXTI_RTEN_RTEN8 BIT(8)
99 #define EXTI_RTEN_RTEN9 BIT(9)
100 #define EXTI_RTEN_RTEN10 BIT(10)
101 #define EXTI_RTEN_RTEN11 BIT(11)
102 #define EXTI_RTEN_RTEN12 BIT(12)
103 #define EXTI_RTEN_RTEN13 BIT(13)
104 #define EXTI_RTEN_RTEN14 BIT(14)
105 #define EXTI_RTEN_RTEN15 BIT(15)
106 #define EXTI_RTEN_RTEN16 BIT(16)
107 #define EXTI_RTEN_RTEN17 BIT(17)
108 #define EXTI_RTEN_RTEN18 BIT(18)
109 #define EXTI_RTEN_RTEN19 BIT(19)
110 #define EXTI_RTEN_RTEN21 BIT(21)
111 #define EXTI_RTEN_RTEN22 BIT(22)
113 /* EXTI_FTEN */
114 #define EXTI_FTEN_FTEN0 BIT(0)
115 #define EXTI_FTEN_FTEN1 BIT(1)
116 #define EXTI_FTEN_FTEN2 BIT(2)
117 #define EXTI_FTEN_FTEN3 BIT(3)
118 #define EXTI_FTEN_FTEN4 BIT(4)
119 #define EXTI_FTEN_FTEN5 BIT(5)
120 #define EXTI_FTEN_FTEN6 BIT(6)
121 #define EXTI_FTEN_FTEN7 BIT(7)
122 #define EXTI_FTEN_FTEN8 BIT(8)
123 #define EXTI_FTEN_FTEN9 BIT(9)
124 #define EXTI_FTEN_FTEN10 BIT(10)
125 #define EXTI_FTEN_FTEN11 BIT(11)
126 #define EXTI_FTEN_FTEN12 BIT(12)
127 #define EXTI_FTEN_FTEN13 BIT(13)
128 #define EXTI_FTEN_FTEN14 BIT(14)
129 #define EXTI_FTEN_FTEN15 BIT(15)
130 #define EXTI_FTEN_FTEN16 BIT(16)
131 #define EXTI_FTEN_FTEN17 BIT(17)
132 #define EXTI_FTEN_FTEN18 BIT(18)
133 #define EXTI_FTEN_FTEN19 BIT(19)
134 #define EXTI_FTEN_FTEN21 BIT(21)
135 #define EXTI_FTEN_FTEN22 BIT(22)
137 /* EXTI_SWIEV */
138 #define EXTI_SWIEV_SWIEV0 BIT(0)
139 #define EXTI_SWIEV_SWIEV1 BIT(1)
140 #define EXTI_SWIEV_SWIEV2 BIT(2)
141 #define EXTI_SWIEV_SWIEV3 BIT(3)
142 #define EXTI_SWIEV_SWIEV4 BIT(4)
143 #define EXTI_SWIEV_SWIEV5 BIT(5)
144 #define EXTI_SWIEV_SWIEV6 BIT(6)
145 #define EXTI_SWIEV_SWIEV7 BIT(7)
146 #define EXTI_SWIEV_SWIEV8 BIT(8)
147 #define EXTI_SWIEV_SWIEV9 BIT(9)
148 #define EXTI_SWIEV_SWIEV10 BIT(10)
149 #define EXTI_SWIEV_SWIEV11 BIT(11)
150 #define EXTI_SWIEV_SWIEV12 BIT(12)
151 #define EXTI_SWIEV_SWIEV13 BIT(13)
152 #define EXTI_SWIEV_SWIEV14 BIT(14)
153 #define EXTI_SWIEV_SWIEV15 BIT(15)
154 #define EXTI_SWIEV_SWIEV16 BIT(16)
155 #define EXTI_SWIEV_SWIEV17 BIT(17)
156 #define EXTI_SWIEV_SWIEV18 BIT(18)
157 #define EXTI_SWIEV_SWIEV19 BIT(19)
158 #define EXTI_SWIEV_SWIEV21 BIT(21)
159 #define EXTI_SWIEV_SWIEV22 BIT(22)
161 /* EXTI_PD */
162 #define EXTI_PD_PD0 BIT(0)
163 #define EXTI_PD_PD1 BIT(1)
164 #define EXTI_PD_PD2 BIT(2)
165 #define EXTI_PD_PD3 BIT(3)
166 #define EXTI_PD_PD4 BIT(4)
167 #define EXTI_PD_PD5 BIT(5)
168 #define EXTI_PD_PD6 BIT(6)
169 #define EXTI_PD_PD7 BIT(7)
170 #define EXTI_PD_PD8 BIT(8)
171 #define EXTI_PD_PD9 BIT(9)
172 #define EXTI_PD_PD10 BIT(10)
173 #define EXTI_PD_PD11 BIT(11)
174 #define EXTI_PD_PD12 BIT(12)
175 #define EXTI_PD_PD13 BIT(13)
176 #define EXTI_PD_PD14 BIT(14)
177 #define EXTI_PD_PD15 BIT(15)
178 #define EXTI_PD_PD16 BIT(16)
179 #define EXTI_PD_PD17 BIT(17)
180 #define EXTI_PD_PD18 BIT(18)
181 #define EXTI_PD_PD19 BIT(19)
182 #define EXTI_PD_PD21 BIT(21)
183 #define EXTI_PD_PD22 BIT(22)
185 /* constants definitions */
186 /* EXTI line number */
187 typedef enum
188 {
189 EXTI_0 = BIT(0),
190 EXTI_1 = BIT(1),
191 EXTI_2 = BIT(2),
192 EXTI_3 = BIT(3),
193 EXTI_4 = BIT(4),
194 EXTI_5 = BIT(5),
195 EXTI_6 = BIT(6),
196 EXTI_7 = BIT(7),
197 EXTI_8 = BIT(8),
198 EXTI_9 = BIT(9),
199 EXTI_10 = BIT(10),
200 EXTI_11 = BIT(11),
201 EXTI_12 = BIT(12),
202 EXTI_13 = BIT(13),
203 EXTI_14 = BIT(14),
204 EXTI_15 = BIT(15),
205 EXTI_16 = BIT(16),
206 EXTI_17 = BIT(17),
207 EXTI_18 = BIT(18),
208 EXTI_19 = BIT(19),
209 EXTI_20 = BIT(20),
210 EXTI_21 = BIT(21),
211 EXTI_22 = BIT(22),
212 EXTI_23 = BIT(23),
213 EXTI_24 = BIT(24),
214 EXTI_25 = BIT(25),
215 EXTI_26 = BIT(26),
216 EXTI_27 = BIT(27),
217 }exti_line_enum;
218
219 /* external interrupt and event */
220 typedef enum
221 {
222 EXTI_INTERRUPT = 0,
223 EXTI_EVENT
224 }exti_mode_enum;
225
226 /* interrupt trigger mode */
227 typedef enum
228 {
229 EXTI_TRIG_RISING = 0,
230 EXTI_TRIG_FALLING,
231 EXTI_TRIG_BOTH
232 }exti_trig_type_enum;
233
234 /* function declarations */
235 /* deinitialize the EXTI */
236 void exti_deinit(void);
237 /* enable the configuration of EXTI initialize */
238 void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
239 /* enable the interrupts from EXTI line x */
240 void exti_interrupt_enable(exti_line_enum linex);
241 /* enable the events from EXTI line x */
242 void exti_event_enable(exti_line_enum linex);
243 /* disable the interrupts from EXTI line x */
244 void exti_interrupt_disable(exti_line_enum linex);
245 /* disable the events from EXTI line x */
246 void exti_event_disable(exti_line_enum linex);
247
248 /* get EXTI lines pending flag */
249 FlagStatus exti_flag_get(exti_line_enum linex);
250 /* clear EXTI lines pending flag */
251 void exti_flag_clear(exti_line_enum linex);
252 /* get EXTI lines flag when the interrupt flag is set */
253 FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
254 /* clear EXTI lines pending flag */
255 void exti_interrupt_flag_clear(exti_line_enum linex);
256 /* EXTI software interrupt event enable */
257 void exti_software_interrupt_enable(exti_line_enum linex);
258 /* EXTI software interrupt event disable */
259 void exti_software_interrupt_disable(exti_line_enum linex);
260
261 #endif /* GD32F3X0_EXTI_H */
EXTI_20
Definition: gd32f3x0_exti.h:209
EXTI_27
Definition: gd32f3x0_exti.h:216
EXTI_TRIG_FALLING
Definition: gd32f3x0_exti.h:230
EXTI_12
Definition: gd32f3x0_exti.h:201
exti_trig_type_enum
exti_trig_type_enum
Definition: gd32f3x0_exti.h:227
exti_interrupt_flag_get
FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
get EXTI lines flag when the interrupt flag is set
Definition: gd32f3x0_exti.c:178
EXTI_4
Definition: gd32f3x0_exti.h:193
EXTI_EVENT
Definition: gd32f3x0_exti.h:223
EXTI_23
Definition: gd32f3x0_exti.h:212
exti_event_disable
void exti_event_disable(exti_line_enum linex)
disable the events from EXTI line x
Definition: gd32f3x0_exti.c:135
EXTI_15
Definition: gd32f3x0_exti.h:204
exti_line_enum
exti_line_enum
Definition: gd32f3x0_exti.h:187
exti_deinit
void exti_deinit(void)
deinitialize the EXTI
Definition: gd32f3x0_exti.c:20
EXTI_2
Definition: gd32f3x0_exti.h:191
EXTI_8
Definition: gd32f3x0_exti.h:197
exti_software_interrupt_enable
void exti_software_interrupt_enable(exti_line_enum linex)
enable EXTI software interrupt event
Definition: gd32f3x0_exti.c:213
EXTI_13
Definition: gd32f3x0_exti.h:202
EXTI_1
Definition: gd32f3x0_exti.h:190
EXTI_17
Definition: gd32f3x0_exti.h:206
EXTI_22
Definition: gd32f3x0_exti.h:211
EXTI_14
Definition: gd32f3x0_exti.h:203
EXTI_6
Definition: gd32f3x0_exti.h:195
exti_software_interrupt_disable
void exti_software_interrupt_disable(exti_line_enum linex)
disable EXTI software interrupt event
Definition: gd32f3x0_exti.c:226
exti_init
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
initialize the EXTI
Definition: gd32f3x0_exti.c:47
exti_flag_get
FlagStatus exti_flag_get(exti_line_enum linex)
get EXTI lines flag
Definition: gd32f3x0_exti.c:148
exti_flag_clear
void exti_flag_clear(exti_line_enum linex)
clear EXTI lines pending flag
Definition: gd32f3x0_exti.c:165
EXTI_24
Definition: gd32f3x0_exti.h:213
EXTI_10
Definition: gd32f3x0_exti.h:199
EXTI_26
Definition: gd32f3x0_exti.h:215
EXTI_5
Definition: gd32f3x0_exti.h:194
exti_mode_enum
exti_mode_enum
Definition: gd32f3x0_exti.h:220
exti_interrupt_enable
void exti_interrupt_enable(exti_line_enum linex)
enable the interrupts from EXTI line x
Definition: gd32f3x0_exti.c:96
exti_interrupt_flag_clear
void exti_interrupt_flag_clear(exti_line_enum linex)
clear EXTI lines pending flag
Definition: gd32f3x0_exti.c:200
EXTI_7
Definition: gd32f3x0_exti.h:196
EXTI_19
Definition: gd32f3x0_exti.h:208
EXTI_9
Definition: gd32f3x0_exti.h:198
EXTI_11
Definition: gd32f3x0_exti.h:200
EXTI_18
Definition: gd32f3x0_exti.h:207
EXTI_25
Definition: gd32f3x0_exti.h:214
EXTI_16
Definition: gd32f3x0_exti.h:205
exti_interrupt_disable
void exti_interrupt_disable(exti_line_enum linex)
disable the interrupt from EXTI line x
Definition: gd32f3x0_exti.c:122
EXTI_0
Definition: gd32f3x0_exti.h:189
EXTI_21
Definition: gd32f3x0_exti.h:210
exti_event_enable
void exti_event_enable(exti_line_enum linex)
enable the events from EXTI line x
Definition: gd32f3x0_exti.c:109
EXTI_INTERRUPT
Definition: gd32f3x0_exti.h:222
EXTI_TRIG_BOTH
Definition: gd32f3x0_exti.h:231
EXTI_TRIG_RISING
Definition: gd32f3x0_exti.h:229
EXTI_3
Definition: gd32f3x0_exti.h:192
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_misc.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_misc.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_misc.h"
13
25 void nvic_priority_group_set(uint32_t nvic_prigroup)
26 {
27 /* set the priority group value */
28 SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
29 }
30
39 void nvic_irq_enable(uint8_t nvic_irq,
40 uint8_t nvic_irq_pre_priority,
41 uint8_t nvic_irq_sub_priority)
42 {
43 uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
44
45 /* use the priority group value to get the temp_pre and the temp_sub */
46 switch ((SCB->AIRCR) & (uint32_t)0x700U) {
47 case NVIC_PRIGROUP_PRE0_SUB4:
48 temp_pre = 0U;
49 temp_sub = 0x4U;
50 break;
51 case NVIC_PRIGROUP_PRE1_SUB3:
52 temp_pre = 1U;
53 temp_sub = 0x3U;
54 break;
55 case NVIC_PRIGROUP_PRE2_SUB2:
56 temp_pre = 2U;
57 temp_sub = 0x2U;
58 break;
59 case NVIC_PRIGROUP_PRE3_SUB1:
60 temp_pre = 3U;
61 temp_sub = 0x1U;
62 break;
63 case NVIC_PRIGROUP_PRE4_SUB0:
64 temp_pre = 4U;
65 temp_sub = 0x0U;
66 break;
67 default:
68 break;
69 }
70
71 /* get the temp_priority to fill the NVIC->IP register */
72 temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
73 temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
74 temp_priority = temp_priority << 0x04U;
75 NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
76
77 /* enable the selected IRQ */
78 NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
79 }
80
87 void nvic_irq_disable(uint8_t nvic_irq)
88 {
89 /* disable the selected IRQ.*/
90 NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F);
91 }
92
102 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
103 {
104 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
105 }
106
118 void system_lowpower_set(uint8_t lowpower_mode)
119 {
120 SCB->SCR |= (uint32_t)lowpower_mode;
121 }
122
134 void system_lowpower_reset(uint8_t lowpower_mode)
135 {
136 SCB->SCR &= (~(uint32_t)lowpower_mode);
137 }
138
148 void systick_clksource_set(uint32_t systick_clksource)
149 {
150 if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
151 /* set the systick clock source from HCLK */
152 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
153 }else{
154 /* set the systick clock source from HCLK/8 */
155 SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
156 }
157 }
nvic_irq_disable
void nvic_irq_disable(uint8_t nvic_irq)
disable NVIC request
Definition: gd32f3x0_misc.c:87
nvic_vector_table_set
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
set the NVIC vector table base address
Definition: gd32f3x0_misc.c:102
system_lowpower_set
void system_lowpower_set(uint8_t lowpower_mode)
set the state of the low power mode
Definition: gd32f3x0_misc.c:118
NVIC_PRIGROUP_PRE2_SUB2
#define NVIC_PRIGROUP_PRE2_SUB2
Definition: gd32f3x0_misc.h:31
nvic_priority_group_set
void nvic_priority_group_set(uint32_t nvic_prigroup)
set the priority group
Definition: gd32f3x0_misc.c:25
nvic_irq_enable
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority)
enable NVIC request
Definition: gd32f3x0_misc.c:39
systick_clksource_set
void systick_clksource_set(uint32_t systick_clksource)
set the systick clock source
Definition: gd32f3x0_misc.c:148
system_lowpower_reset
void system_lowpower_reset(uint8_t lowpower_mode)
reset the state of the low power mode
Definition: gd32f3x0_misc.c:134
NVIC_VECTTAB_OFFSET_MASK
#define NVIC_VECTTAB_OFFSET_MASK
Definition: gd32f3x0_misc.h:23
gd32f3x0_misc.h
definitions for the MISC
NVIC_PRIGROUP_PRE0_SUB4
#define NVIC_PRIGROUP_PRE0_SUB4
Definition: gd32f3x0_misc.h:29
NVIC_PRIGROUP_PRE4_SUB0
#define NVIC_PRIGROUP_PRE4_SUB0
Definition: gd32f3x0_misc.h:33
NVIC_PRIGROUP_PRE1_SUB3
#define NVIC_PRIGROUP_PRE1_SUB3
Definition: gd32f3x0_misc.h:30
NVIC_AIRCR_VECTKEY_MASK
#define NVIC_AIRCR_VECTKEY_MASK
Definition: gd32f3x0_misc.h:26
SYSTICK_CLKSOURCE_HCLK_DIV8
#define SYSTICK_CLKSOURCE_HCLK_DIV8
Definition: gd32f3x0_misc.h:45
NVIC_PRIGROUP_PRE3_SUB1
#define NVIC_PRIGROUP_PRE3_SUB1
Definition: gd32f3x0_misc.h:32
SYSTICK_CLKSOURCE_HCLK
#define SYSTICK_CLKSOURCE_HCLK
Definition: gd32f3x0_misc.h:46
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_regs.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
usb_regs.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef USB_REGS_H
13 #define USB_REGS_H
14
15 #include "usb_conf.h"
16
17 #define USBFS USBFS_BASE
19 /* registers location definitions */
20 #define LOCATE_DIEPTFLEN(x) (0x104U + 4U * ((x) - 1U))
21 #define LOCATE_HCHCTL(x) (0x500U + 0x20U * (x))
22 #define LOCATE_HCHINTF(x) (0x508U + 0x20U * (x))
23 #define LOCATE_HCHINTEN(x) (0x50CU + 0x20U * (x))
24 #define LOCATE_HCHLEN(x) (0x510U + 0x20U * (x))
25 #define LOCATE_DIEPCTL(x) (0x900U + 0x20U * (x))
26 #define LOCATE_DOEPCTL(x) (0xB00U + 0x20U * (x))
27 #define LOCATE_DIEPINTF(x) (0x908U + 0x20U * (x))
28 #define LOCATE_DOEPINTF(x) (0xB08U + 0x20U * (x))
29 #define LOCATE_DIEPLEN(x) (0x910U + 0x20U * (x))
30 #define LOCATE_DOEPLEN(x) (0xB10U + 0x20U * (x))
31 #define LOCATE_DIEPxTFSTAT(x) (0x918U + 0x20U * (x))
32 #define LOCATE_FIFO(x) (((x) + 1U) << 12U)
34 /* registers definitions */
35 #define USB_GOTGCS REG32(((USBFS) + 0x0000U))
36 #define USB_GOTGINTF REG32(((USBFS) + 0x0004U))
37 #define USB_GAHBCS REG32(((USBFS) + 0x0008U))
38 #define USB_GUSBCS REG32(((USBFS) + 0x000CU))
39 #define USB_GRSTCTL REG32(((USBFS) + 0x0010U))
40 #define USB_GINTF REG32(((USBFS) + 0x0014U))
41 #define USB_GINTEN REG32(((USBFS) + 0x0018U))
42 #define USB_GRSTATR REG32(((USBFS) + 0x001CU))
43 #define USB_GRSTATP REG32(((USBFS) + 0x0020U))
44 #define USB_GRFLEN REG32(((USBFS) + 0x0024U))
45 #define USB_HNPTFLEN REG32(((USBFS) + 0x0028U))
46 #define USB_DIEP0TFLEN REG32(((USBFS) + 0x0028U))
47 #define USB_HNPTFQSTAT REG32(((USBFS) + 0x002CU))
48 #define USB_GCCFG REG32(((USBFS) + 0x0038U))
49 #define USB_CID REG32(((USBFS) + 0x003CU))
50 #define USB_HPTFLEN REG32(((USBFS) + 0x0100U))
51 #define USB_DIEPxTFLEN(x) REG32(((USBFS) + LOCATE_DIEPTFLEN(x)))
53 #define USB_HCTL REG32(((USBFS) + 0x0400U))
54 #define USB_HFT REG32(((USBFS) + 0x0404U))
55 #define USB_HFINFR REG32(((USBFS) + 0x0408U))
56 #define USB_HPTFQSTAT REG32(((USBFS) + 0x0410U))
57 #define USB_HACHINT REG32(((USBFS) + 0x0414U))
58 #define USB_HACHINTEN REG32(((USBFS) + 0x0418U))
59 #define USB_HPCS REG32(((USBFS) + 0x0440U))
60 #define USB_HCHxCTL(x) REG32(((USBFS) + LOCATE_HCHCTL(x)))
61 #define USB_HCHxINTF(x) REG32(((USBFS) + LOCATE_HCHINTF(x)))
62 #define USB_HCHxINTEN(x) REG32(((USBFS) + LOCATE_HCHINTEN(x)))
63 #define USB_HCHxLEN(x) REG32(((USBFS) + LOCATE_HCHLEN(x)))
65 #define USB_DCFG REG32(((USBFS) + 0x0800U))
66 #define USB_DCTL REG32(((USBFS) + 0x0804U))
67 #define USB_DSTAT REG32(((USBFS) + 0x0808U))
68 #define USB_DIEPINTEN REG32(((USBFS) + 0x0810U))
69 #define USB_DOEPINTEN REG32(((USBFS) + 0x0814U))
70 #define USB_DAEPINT REG32(((USBFS) + 0x0818U))
71 #define USB_DAEPINTEN REG32(((USBFS) + 0x081CU))
72 #define USB_DVBUSDT REG32(((USBFS) + 0x0828U))
73 #define USB_DVBUSPT REG32(((USBFS) + 0x082CU))
74 #define USB_DIEPFEINTEN REG32(((USBFS) + 0x0834U))
75 #define USB_DEP1INT REG32(((USBFS) + 0x0838U))
76 #define USB_DEP1INTEN REG32(((USBFS) + 0x083CU))
77 #define USB_DIEP1INTEN REG32(((USBFS) + 0x0844U))
78 #define USB_DOEP1INTEN REG32(((USBFS) + 0x0884U))
79 #define USB_DIEP0CTL REG32(((USBFS) + 0x0900U))
80 #define USB_DIEP0LEN REG32(((USBFS) + 0x0910U))
81 #define USB_DOEP0CTL REG32(((USBFS) + 0x0B00U))
82 #define USB_DOEP0LEN REG32(((USBFS) + 0x0B10U))
83 #define USB_DIEPxCTL(x) REG32(((USBFS) + LOCATE_DIEPCTL(x)))
84 #define USB_DOEPxCTL(x) REG32(((USBFS) + LOCATE_DOEPCTL(x)))
85 #define USB_DIEPxINTF(x) REG32(((USBFS) + LOCATE_DIEPINTF(x)))
86 #define USB_DOEPxINTF(x) REG32(((USBFS) + LOCATE_DOEPINTF(x)))
87 #define USB_DIEPxLEN(x) REG32(((USBFS) + LOCATE_DIEPLEN(x)))
88 #define USB_DOEPxLEN(x) REG32(((USBFS) + LOCATE_DOEPLEN(x)))
89 #define USB_DIEPxTFSTAT(x) REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x)))
91 #define USB_PWRCLKCTL REG32(((USBFS) + 0x0E00U))
93 #define USB_FIFO(x) (&REG32(((USBFS) + LOCATE_FIFO(x))))
95 /* global OTG control and status register bits definitions */
96 #define GOTGCS_BSV BIT(19)
97 #define GOTGCS_ASV BIT(18)
98 #define GOTGCS_DI BIT(17)
99 #define GOTGCS_IDPS BIT(16)
100 #define GOTGCS_DHNPEN BIT(11)
101 #define GOTGCS_HHNPEN BIT(10)
102 #define GOTGCS_HNPREQ BIT(9)
103 #define GOTGCS_HNPS BIT(8)
104 #define GOTGCS_SRPREQ BIT(1)
105 #define GOTGCS_SRPS BIT(0)
107 /* global OTG interrupt flag register bits definitions */
108 #define GOTGINTF_DF BIT(19)
109 #define GOTGINTF_ADTO BIT(18)
110 #define GOTGINTF_HNPDET BIT(17)
111 #define GOTGINTF_HNPEND BIT(9)
112 #define GOTGINTF_SRPEND BIT(8)
113 #define GOTGINTF_SESEND BIT(2)
115 /* global AHB control and status register bits definitions */
116 #define GAHBCS_PTXFTH BIT(8)
117 #define GAHBCS_TXFTH BIT(7)
118 //#define GAHBCS_DMAEN BIT(5)
119 //#define GAHBCS_BURST BITS(1, 4)
120 #define GAHBCS_GINTEN BIT(0)
122 /* global USB control and status register bits definitions */
123 #define GUSBCS_FDM BIT(30)
124 #define GUSBCS_FHM BIT(29)
125 //#define GUSBCS_ULPIEOI BIT(21)
126 //#define GUSBCS_ULPIEVD BIT(20)
127 #define GUSBCS_UTT BITS(10, 13)
128 #define GUSBCS_HNPCEN BIT(9)
129 #define GUSBCS_SRPCEN BIT(8)
130 //#define GUSBCS_EMBPHY BIT(6)
131 #define GUSBCS_TOC BITS(0, 2)
133 /* global reset control register bits definitions */
134 //#define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */
135 //#define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */
136 #define GRSTCTL_TXFNUM BITS(6, 10)
137 #define GRSTCTL_TXFF BIT(5)
138 #define GRSTCTL_RXFF BIT(4)
139 #define GRSTCTL_HFCRST BIT(2)
140 #define GRSTCTL_HCSRST BIT(1)
141 #define GRSTCTL_CSRST BIT(0)
143 /* global interrupt flag register bits definitions */
144 #define GINTF_WKUPIF BIT(31)
145 #define GINTF_SESIF BIT(30)
146 #define GINTF_DISCIF BIT(29)
147 #define GINTF_IDPSC BIT(28)
148 #define GINTF_PTXFEIF BIT(26)
149 #define GINTF_HCIF BIT(25)
150 #define GINTF_HPIF BIT(24)
151 #define GINTF_PXNCIF BIT(21)
152 #define GINTF_ISOONCIF BIT(21)
153 #define GINTF_ISOINCIF BIT(20)
154 #define GINTF_OEPIF BIT(19)
155 #define GINTF_IEPIF BIT(18)
156 #define GINTF_EOPFIF BIT(15)
157 #define GINTF_ISOOPDIF BIT(14)
158 #define GINTF_ENUMF BIT(13)
159 #define GINTF_RST BIT(12)
160 #define GINTF_SP BIT(11)
161 #define GINTF_ESP BIT(10)
162 #define GINTF_GONAK BIT(7)
163 #define GINTF_GNPINAK BIT(6)
164 #define GINTF_NPTXFEIF BIT(5)
165 #define GINTF_RXFNEIF BIT(4)
166 #define GINTF_SOF BIT(3)
167 #define GINTF_OTGIF BIT(2)
168 #define GINTF_MFIF BIT(1)
169 #define GINTF_COPM BIT(0)
171 /* global interrupt enable register bits definitions */
172 #define GINTEN_WKUPIE BIT(31)
173 #define GINTEN_SESIE BIT(30)
174 #define GINTEN_DISCIE BIT(29)
175 #define GINTEN_IDPSCIE BIT(28)
176 #define GINTEN_PTXFEIE BIT(26)
177 #define GINTEN_HCIE BIT(25)
178 #define GINTEN_HPIE BIT(24)
179 #define GINTEN_PXNCIE BIT(21)
180 #define GINTEN_ISOONCIE BIT(21)
181 #define GINTEN_ISOINCIE BIT(20)
182 #define GINTEN_OEPIE BIT(19)
183 #define GINTEN_IEPIE BIT(18)
184 #define GINTEN_EOPFIE BIT(15)
185 #define GINTEN_ISOOPDIE BIT(14)
186 #define GINTEN_ENUMFIE BIT(13)
187 #define GINTEN_RSTIE BIT(12)
188 #define GINTEN_SPIE BIT(11)
189 #define GINTEN_ESPIE BIT(10)
190 #define GINTEN_GONAKIE BIT(7)
191 #define GINTEN_GNPINAKIE BIT(6)
192 #define GINTEN_NPTXFEIE BIT(5)
193 #define GINTEN_RXFNEIE BIT(4)
194 #define GINTEN_SOFIE BIT(3)
195 #define GINTEN_OTGIE BIT(2)
196 #define GINTEN_MFIE BIT(1)
198 /* global receive status read and pop register bits definitions */
199 #define GRSTATRP_RPCKST BITS(17, 20)
200 #define GRSTATRP_DPID BITS(15, 16)
201 #define GRSTATRP_BCOUNT BITS(4, 14)
202 #define GRSTATRP_CNUM BITS(0, 3)
203 #define GRSTATRP_EPNUM BITS(0, 3)
205 /* global receive FIFO length register bits definitions */
206 #define GRFLEN_RXFD BITS(0, 15)
208 /* host non-periodic transmit FIFO length register bits definitions */
209 #define HNPTFLEN_HNPTXFD BITS(16, 31)
210 #define HNPTFLEN_HNPTXRSAR BITS(0, 15)
212 /* IN endpoint 0 transmit FIFO length register bits definitions */
213 #define DIEP0TFLEN_IEP0TXFD BITS(16, 31)
214 #define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15)
216 /* host non-periodic transmit FIFO/queue status register bits definitions */
217 #define HNPTFQSTAT_NPTXRQTOP BITS(24, 30)
218 #define HNPTFQSTAT_NPTXRQS BITS(16, 23)
219 #define HNPTFQSTAT_NPTXFS BITS(0, 15)
220 #define HNPTFQSTAT_CNUM BITS(27, 30)
221 #define HNPTFQSTAT_EPNUM BITS(27, 30)
222 #define HNPTFQSTAT_TYPE BITS(25, 26)
223 #define HNPTFQSTAT_TMF BIT(24)
225 /* global core configuration register bits definitions */
226 #define GCCFG_VBUSIG BIT(21)
227 #define GCCFG_SOFOEN BIT(20)
228 #define GCCFG_VBUSBCEN BIT(19)
229 #define GCCFG_VBUSACEN BIT(18)
230 #define GCCFG_PWRON BIT(16)
232 /* core ID register bits definitions */
233 #define CID_CID BITS(0, 31)
235 /* host periodic transmit FIFO length register bits definitions */
236 #define HPTFLEN_HPTXFD BITS(16, 31)
237 #define HPTFLEN_HPTXFSAR BITS(0, 15)
239 /* device IN endpoint transmit FIFO length register bits definitions */
240 #define DIEPTFLEN_IEPTXFD BITS(16, 31)
241 #define DIEPTFLEN_IEPTXRSAR BITS(0, 15)
243 /* host control register bits definitions */
244 //#define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */
245 #define HCTL_CLKSEL BITS(0, 1)
247 /* host frame interval register bits definitions */
248 #define HFT_FRI BITS(0, 15)
250 /* host frame information remaining register bits definitions */
251 #define HFINFR_FRT BITS(16, 31)
252 #define HFINFR_FRNUM BITS(0, 15)
254 /* host periodic transmit FIFO/queue status register bits definitions */
255 #define HPTFQSTAT_PTXREQT BITS(24, 31)
256 #define HPTFQSTAT_PTXREQS BITS(16, 23)
257 #define HPTFQSTAT_PTXFS BITS(0, 15)
258 #define HPTFQSTAT_OEFRM BIT(31)
259 #define HPTFQSTAT_CNUM BITS(27, 30)
260 #define HPTFQSTAT_EPNUM BITS(27, 30)
261 #define HPTFQSTAT_TYPE BITS(25, 26)
262 #define HPTFQSTAT_TMF BIT(24)
264 /* host all channels interrupt register bits definitions */
265 #define HACHINT_HACHINT BITS(0, 7)
267 /* host all channels interrupt enable register bits definitions */
268 #define HACHINTEN_CINTEN BITS(0, 7)
270 /* host port control and status register bits definitions */
271 #define HPCS_PS BITS(17, 18)
272 #define HPCS_PP BIT(12)
273 #define HPCS_PLST BITS(10, 11)
274 #define HPCS_PRST BIT(8)
275 #define HPCS_PSP BIT(7)
276 #define HPCS_PREM BIT(6)
277 #define HPCS_PEDC BIT(3)
278 #define HPCS_PE BIT(2)
279 #define HPCS_PCD BIT(1)
280 #define HPCS_PCST BIT(0)
282 /* host channel-x control register bits definitions */
283 #define HCHCTL_CEN BIT(31)
284 #define HCHCTL_CDIS BIT(30)
285 #define HCHCTL_ODDFRM BIT(29)
286 #define HCHCTL_DAR BITS(22, 28)
287 #define HCHCTL_MPC BITS(20, 21)
288 #define HCHCTL_EPTYPE BITS(18, 19)
289 #define HCHCTL_LSD BIT(17)
290 #define HCHCTL_EPDIR BIT(15)
291 #define HCHCTL_EPNUM BITS(11, 14)
292 #define HCHCTL_MPL BITS(0, 10)
294 /* host channel-x split transaction register bits definitions */
295 //#define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */
296 //#define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */
297 //#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */
298 //#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */
299 //#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */
300
301 /* host channel-x interrupt flag register bits definitions */
302 #define HCHINTF_DTER BIT(10)
303 #define HCHINTF_REQOVR BIT(9)
304 #define HCHINTF_BBER BIT(8)
305 #define HCHINTF_USBER BIT(7)
306 #define HCHINTF_NYET BIT(6)
307 #define HCHINTF_ACK BIT(5)
308 #define HCHINTF_NAK BIT(4)
309 #define HCHINTF_STALL BIT(3)
310 //#define HCHINTF_DMAER BIT(2)
311 #define HCHINTF_CH BIT(1)
312 #define HCHINTF_TF BIT(0)
314 /* host channel-x interrupt enable register bits definitions */
315 #define HCHINTEN_DTERIE BIT(10)
316 #define HCHINTEN_REQOVRIE BIT(9)
317 #define HCHINTEN_BBERIE BIT(8)
318 #define HCHINTEN_USBERIE BIT(7)
319 #define HCHINTEN_NYETIE BIT(6)
320 #define HCHINTEN_ACKIE BIT(5)
321 #define HCHINTEN_NAKIE BIT(4)
322 #define HCHINTEN_STALLIE BIT(3)
323 //#define HCHINTEN_DMAERIE BIT(2)
324 #define HCHINTEN_CHIE BIT(1)
325 #define HCHINTEN_TFIE BIT(0)
327 /* host channel-x transfer length register bits definitions */
328 //#define HCHLEN_PING BIT(31) /*!< PING token request */
329 #define HCHLEN_DPID BITS(29, 30)
330 #define HCHLEN_PCNT BITS(19, 28)
331 #define HCHLEN_TLEN BITS(0, 18)
333 /* host channel-x DMA address register bits definitions */
334 //#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
335
336 /* device control and status registers */
337 /* device configuration registers bits definitions */
338 #define DCFG_EOPFT BITS(11, 12)
339 #define DCFG_DAR BITS(4, 10)
340 #define DCFG_NZLSOH BIT(2)
341 #define DCFG_DS BITS(0, 1)
343 /* device control registers bits definitions */
344 #define DCTL_POIF BIT(11)
345 #define DCTL_CGONAK BIT(10)
346 #define DCTL_SGONAK BIT(9)
347 #define DCTL_CGINAK BIT(8)
348 #define DCTL_SGINAK BIT(7)
349 #define DCTL_GONS BIT(3)
350 #define DCTL_GINS BIT(2)
351 #define DCTL_SD BIT(1)
352 #define DCTL_RWKUP BIT(0)
354 /* device status registers bits definitions */
355 #define DSTAT_FNRSOF BITS(8, 21)
356 #define DSTAT_ES BITS(1, 2)
357 #define DSTAT_SPST BIT(0)
359 /* device IN endpoint common interrupt enable registers bits definitions */
360 //#define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */
361 #define DIEPINTEN_TXFEEN BIT(7)
362 #define DIEPINTEN_IEPNEEN BIT(6)
363 #define DIEPINTEN_EPTXFUDEN BIT(4)
364 #define DIEPINTEN_CITOEN BIT(3)
365 #define DIEPINTEN_EPDISEN BIT(1)
366 #define DIEPINTEN_TFEN BIT(0)
368 /* device OUT endpoint common interrupt enable registers bits definitions */
369 //#define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */
370 #define DOEPINTEN_BTBSTPEN BIT(6)
371 #define DOEPINTEN_EPRXFOVREN BIT(4)
372 #define DOEPINTEN_STPFEN BIT(3)
373 #define DOEPINTEN_EPDISEN BIT(1)
374 #define DOEPINTEN_TFEN BIT(0)
376 /* device all endpoints interrupt registers bits definitions */
377 #define DAEPINT_OEPITB BITS(16, 21)
378 #define DAEPINT_IEPITB BITS(0, 5)
380 /* device all endpoints interrupt enable registers bits definitions */
381 #define DAEPINTEN_OEPIE BITS(16, 21)
382 #define DAEPINTEN_IEPIE BITS(0, 3)
384 /* device Vbus discharge time registers bits definitions */
385 #define DVBUSDT_DVBUSDT BITS(0, 15)
387 /* device Vbus pulsing time registers bits definitions */
388 #define DVBUSPT_DVBUSPT BITS(0, 11)
390 /* device IN endpoint FIFO empty interrupt enable register bits definitions */
391 #define DIEPFEINTEN_IEPTXFEIE BITS(0, 3)
393 //#define DEP1INT_OEP1INT BIT(17)
395 //#define DEP1INT_IEP1INT BIT(1)
397 //#define DEP1INTEN_OEP1INTEN BIT(17)
399 //#define DEP1INTEN_IEP1INTEN BIT(1)
401 //#define DIEP1INTEN_NAKEN BIT(13)
403 //#define DIEP1INTEN_IEPNEEN BIT(6)
404 //#define DIEP1INTEN_EPTXFUDEN BIT(4)
405 //#define DIEP1INTEN_CITOEN BIT(3)
406 //#define DIEP1INTEN_EPDISEN BIT(1)
407 //#define DIEP1INTEN_TFEN BIT(0)
409 //#define DOEP1INTEN_NYETEN BIT(14)
411 //#define DOEP1INTEN_BTBSTPEN BIT(6)
412 //#define DOEP1INTEN_EPRXOVREN BIT(4)
413 //#define DOEP1INTEN_STPFEN BIT(3)
414 //#define DOEP1INTEN_EPDISEN BIT(1)
415 //#define DOEP1INTEN_TFEN BIT(0)
417 /* device endpoint 0 control register bits definitions */
418 #define DEP0CTL_EPEN BIT(31)
419 #define DEP0CTL_EPD BIT(30)
420 #define DEP0CTL_SNAK BIT(27)
421 #define DEP0CTL_CNAK BIT(26)
422 #define DIEP0CTL_TXFNUM BITS(22, 25)
423 #define DEP0CTL_STALL BIT(21)
424 //#define DOEP0CTL_SNOOP BIT(20)
425 #define DEP0CTL_EPTYPE BITS(18, 19)
426 #define DEP0CTL_NAKS BIT(17)
427 #define DEP0CTL_EPACT BIT(15)
428 #define DEP0CTL_MPL BITS(0, 1)
430 /* device endpoint x control register bits definitions */
431 #define DEPCTL_EPEN BIT(31)
432 #define DEPCTL_EPD BIT(30)
433 #define DEPCTL_SODDFRM BIT(29)
434 #define DEPCTL_SD1PID BIT(29)
435 #define DEPCTL_SEVNFRM BIT(28)
436 #define DEPCTL_SD0PID BIT(28)
437 #define DEPCTL_SNAK BIT(27)
438 #define DEPCTL_CNAK BIT(26)
439 #define DIEPCTL_TXFNUM BITS(22, 25)
440 #define DEPCTL_STALL BIT(21)
441 //#define DOEPCTL_SNOOP BIT(20)
442 #define DEPCTL_EPTYPE BITS(18, 19)
443 #define DEPCTL_NAKS BIT(17)
444 #define DEPCTL_EOFRM BIT(16)
445 #define DEPCTL_DPID BIT(16)
446 #define DEPCTL_EPACT BIT(15)
447 #define DEPCTL_MPL BITS(0, 10)
449 /* device IN endpoint-x interrupt flag register bits definitions */
450 //#define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */
451 #define DIEPINTF_TXFE BIT(7)
452 #define DIEPINTF_IEPNE BIT(6)
453 #define DIEPINTF_EPTXFUD BIT(4)
454 #define DIEPINTF_CITO BIT(3)
455 #define DIEPINTF_EPDIS BIT(1)
456 #define DIEPINTF_TF BIT(0)
458 /* device OUT endpoint-x interrupt flag register bits definitions */
459 //#define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */
460 #define DOEPINTF_BTBSTP BIT(6)
461 #define DOEPINTF_EPRXFOVR BIT(4)
462 #define DOEPINTF_STPF BIT(3)
463 #define DOEPINTF_EPDIS BIT(1)
464 #define DOEPINTF_TF BIT(0)
466 /* device IN endpoint 0 transfer length register bits definitions */
467 #define DIEP0LEN_PCNT BITS(19, 20)
468 #define DIEP0LEN_TLEN BITS(0, 6)
470 /* device OUT endpoint 0 transfer length register bits definitions */
471 #define DOEP0LEN_STPCNT BITS(29, 30)
472 #define DOEP0LEN_PCNT BIT(19)
473 #define DOEP0LEN_TLEN BITS(0, 6)
475 /* device OUT endpoint-x transfer length register bits definitions */
476 #define DOEPLEN_RXDPID BITS(29, 30)
477 #define DOEPLEN_STPCNT BITS(29, 30)
478 #define DIEPLEN_MCNT BITS(29, 30)
479 #define DEPLEN_PCNT BITS(19, 28)
480 #define DEPLEN_TLEN BITS(0, 18)
482 /* device IN endpoint-x DMA address register bits definitions */
483 //#define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
484
485 /* device OUT endpoint-x DMA address register bits definitions */
486 //#define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
487
488 /* device IN endpoint-x transmit FIFO status register bits definitions */
489 #define DIEPTFSTAT_IEPTFS BITS(0, 15)
491 /* USB power and clock registers bits definition */
492 #define PWRCLKCTL_SHCLK BIT(1)
493 #define PWRCLKCTL_SUCLK BIT(0)
495 /* register options defines */
496 #define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U))
498 #define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U)
499 #define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U)
500 #define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U)
502 #define GAHBCS_TFEL(regval) (GAHBCS_TXFTH & ((regval) << 7U))
504 #define TXFIFO_EMPTY_HALF GAHBCS_TFEL(0U)
505 #define TXFIFO_EMPTY GAHBCS_TFEL(1U)
507 #define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U))
509 #define DMA_INCR0 GAHBCS_DMAINCR(0U)
510 #define DMA_INCR1 GAHBCS_DMAINCR(1U)
511 #define DMA_INCR4 GAHBCS_DMAINCR(3U)
512 #define DMA_INCR8 GAHBCS_DMAINCR(5U)
513 #define DMA_INCR16 GAHBCS_DMAINCR(7U)
515 #define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U))
517 #define FRAME_INTERVAL_80 DCFG_PFRI(0U)
518 #define FRAME_INTERVAL_85 DCFG_PFRI(1U)
519 #define FRAME_INTERVAL_90 DCFG_PFRI(2U)
520 #define FRAME_INTERVAL_95 DCFG_PFRI(3U)
522 #define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U))
524 #define EP0MPL_64 DEP0_MPL(0U)
525 #define EP0MPL_32 DEP0_MPL(1U)
526 #define EP0MPL_16 DEP0_MPL(2U)
527 #define EP0MPL_8 DEP0_MPL(3U)
529 /* endpoints address */
530
531 /* first bit is direction(0 for Rx and 1 for Tx) */
532 #define EP0_OUT ((uint8_t)0x00U)
533 #define EP0_IN ((uint8_t)0x80U)
534 #define EP1_OUT ((uint8_t)0x01U)
535 #define EP1_IN ((uint8_t)0x81U)
536 #define EP2_OUT ((uint8_t)0x02U)
537 #define EP2_IN ((uint8_t)0x82U)
538 #define EP3_OUT ((uint8_t)0x03U)
539 #define EP3_IN ((uint8_t)0x83U)
541 /* enable global interrupt */
542 #define USB_GLOBAL_INT_ENABLE() (USB_GAHBCS |= GAHBCS_GINTEN)
543
544 /* disable global interrupt */
545 #define USB_GLOBAL_INT_DISABLE() (USB_GAHBCS &= ~GAHBCS_GINTEN)
546
547 /* get current operation mode */
548 #define USB_CURRENT_MODE_GET() (USB_GINTF & GINTF_COPM)
549
550 /* read global interrupt flag */
551 #define USB_CORE_INTR_READ(x) \
552 do { \
553 uint32_t global_intf = USB_GINTF; \
554 (x) = global_intf & USB_GINTEN; \
555 } while(0)
556
557 /* read global interrupt flag */
558 #define USB_DAOEP_INTR_READ(x) \
559 do { \
560 uint32_t dev_all_ep_inten = USB_DAEPINTEN; \
561 uint32_t dev_all_ep_int = USB_DAEPINT; \
562 uint32_t out_ep_intb = DAEPINT_OEPITB; \
563 (x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \
564 } while(0)
565
566 /* read out endpoint-x interrupt flag */
567 #define USB_DOEP_INTR_READ(x, EpID) \
568 do { \
569 uint32_t out_epintf = USB_DOEPxINTF(EpID); \
570 (x) = out_epintf & USB_DOEPINTEN; \
571 } while(0)
572
573 /* read all in endpoint interrupt flag */
574 #define USB_DAIEP_INTR_READ(x) \
575 do { \
576 uint32_t dev_all_ep_inten = USB_DAEPINTEN; \
577 uint32_t dev_all_ep_int = USB_DAEPINT; \
578 uint32_t in_ep_intb = DAEPINT_IEPITB; \
579 (x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \
580 } while(0)
581
582
583 /* read in endpoint-x interrupt flag */
584 #define USB_DIEP_INTR_READ(x, EpID) \
585 do { \
586 uint32_t dev_ep_intf = USB_DIEPxINTF(EpID); \
587 uint32_t dev_ep_fifoempty_intf = (((USB_DIEPFEINTEN >> (EpID)) & 0x1U) << 7U); \
588 uint32_t dev_inep_inten = USB_DIEPINTEN; \
589 (x) = dev_ep_intf & (dev_ep_fifoempty_intf | dev_inep_inten); \
590 } while(0)
591
592 /* generate remote wakup signal */
593 #define USB_REMOTE_WAKEUP_SET() (USB_DCTL |= DCTL_RWKUP)
594
595 /* no remote wakup signal generate */
596 #define USB_REMOTE_WAKEUP_RESET() (USB_DCTL &= ~DCTL_RWKUP)
597
598 /* generate soft disconnect */
599 #define USB_SOFT_DISCONNECT_ENABLE() (USB_DCTL |= DCTL_SD)
600
601 /* no soft disconnect generate */
602 #define USB_SOFT_DISCONNECT_DISABLE() (USB_DCTL &= ~DCTL_SD)
603
604 /* set device address */
605 #define USB_SET_DEVADDR(DevAddr) (USB_DCFG |= (DevAddr) << 4U)
606
607 /* check whether frame is even */
608 #define USB_EVEN_FRAME() (!(USB_HFINFR & 0x01U))
609
610 /* read port status */
611 #define USB_PORT_READ() (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC))
612
613 /* usb clock initialize */
614 #define USB_FSLSCLOCK_INIT(ClockFreq) (USB_HCTL &= ~HCTL_CLKSEL | (ClockFreq))
615
616 /* get usb current speed */
617 #define USB_CURRENT_SPEED_GET() ((USB_HPCS & HPCS_PS) >> 17)
618
619 /* get usb current frame */
620 #define USB_CURRENT_FRAME_GET() (USB_HFINFR & 0xFFFFU)
621
622 #endif /* USB_REGS_H */
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_adc.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_adc.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_adc.h"
13
20 void adc_deinit(void)
21 {
22 rcu_periph_reset_enable(RCU_ADCRST);
23 rcu_periph_reset_disable(RCU_ADCRST);
24 }
25
32 void adc_enable(void)
33 {
34 if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)){
35 ADC_CTL1 |= (uint32_t)ADC_CTL1_ADCON;
36 }
37 }
38
45 void adc_disable(void)
46 {
47 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ADCON);
48 }
49
56 void adc_calibration_enable(void)
57 {
58 /* reset the selected ADC calibration register */
59 ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB;
60 /* check the RSTCLB bit state */
61 while((ADC_CTL1 & ADC_CTL1_RSTCLB)){
62 }
63
64 /* enable ADC calibration process */
65 ADC_CTL1 |= ADC_CTL1_CLB;
66 /* check the CLB bit state */
67 while((ADC_CTL1 & ADC_CTL1_CLB)){
68 }
69 }
70
77 void adc_dma_mode_enable(void)
78 {
79 ADC_CTL1 |= (uint32_t)(ADC_CTL1_DMA);
80 }
81
88 void adc_dma_mode_disable(void)
89 {
90 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DMA);
91 }
92
99 void adc_tempsensor_vrefint_enable(void)
100 {
101 /* enable the temperature sensor and Vrefint channel */
102 ADC_CTL1 |= ADC_CTL1_TSVREN;
103 }
104
111 void adc_tempsensor_vrefint_disable(void)
112 {
113 /* disable the temperature sensor and Vrefint channel */
114 ADC_CTL1 &= ~ADC_CTL1_TSVREN;
115 }
116
123 void adc_vbat_enable(void)
124 {
125 /* enable the vbat channel */
126 ADC_CTL1 |= ADC_CTL1_VBETEN;
127 }
128
135 void adc_vbat_disable(void)
136 {
137 /* disable the vbat channel */
138 ADC_CTL1 &= ~ADC_CTL1_VBETEN;
139 }
140
152 void adc_resolution_config(uint32_t resolution)
153 {
154 ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DRES);
155 ADC_CTL0 |= (uint32_t)resolution;
156 }
157
170 void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length)
171 {
172 ADC_CTL0 &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
173
174 switch(channel_group){
175 case ADC_REGULAR_CHANNEL:
176 /* configure the number of conversions in discontinuous mode */
177 ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DISNUM);
178 ADC_CTL0 |= CTL0_DISNUM(((uint32_t)length - 1U));
179 ADC_CTL0 |= (uint32_t)ADC_CTL0_DISRC;
180 break;
181 case ADC_INSERTED_CHANNEL:
182 ADC_CTL0 |= (uint32_t)ADC_CTL0_DISIC;
183 break;
184 case ADC_CHANNEL_DISCON_DISABLE:
185 default:
186 break;
187 }
188 }
189
201 void adc_special_function_config(uint32_t function, ControlStatus newvalue)
202 {
203 if(newvalue){
204 /* enable ADC scan mode */
205 if(RESET != (function & ADC_SCAN_MODE)){
206 ADC_CTL0 |= ADC_SCAN_MODE;
207 }
208 /* enable ADC inserted channel group convert automatically */
209 if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){
210 ADC_CTL0 |= ADC_INSERTED_CHANNEL_AUTO;
211 }
212 /* enable ADC continuous mode */
213 if(RESET != (function & ADC_CONTINUOUS_MODE)){
214 ADC_CTL1 |= ADC_CONTINUOUS_MODE;
215 }
216 }else{
217 /* disable ADC scan mode */
218 if(RESET != (function & ADC_SCAN_MODE)){
219 ADC_CTL0 &= ~ADC_SCAN_MODE;
220 }
221 /* disable ADC inserted channel group convert automatically */
222 if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){
223 ADC_CTL0 &= ~ADC_INSERTED_CHANNEL_AUTO;
224 }
225 /* disable ADC continuous mode */
226 if(RESET != (function & ADC_CONTINUOUS_MODE)){
227 ADC_CTL1 &= ~ADC_CONTINUOUS_MODE;
228 }
229 }
230 }
231
241 void adc_data_alignment_config(uint32_t data_alignment)
242 {
243 if(ADC_DATAALIGN_RIGHT != data_alignment){
244 ADC_CTL1 |= ADC_CTL1_DAL;
245 }else{
246 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DAL);
247 }
248 }
249
262 void adc_channel_length_config(uint8_t channel_group, uint32_t length)
263 {
264 switch(channel_group){
265 case ADC_REGULAR_CHANNEL:
266 /* configure the length of regular channel group */
267 ADC_RSQ0 &= ~((uint32_t)ADC_RSQ0_RL);
268 ADC_RSQ0 |= RSQ0_RL((uint32_t)(length-1U));
269 break;
270 case ADC_INSERTED_CHANNEL:
271 /* configure the length of inserted channel group */
272 ADC_ISQ &= ~((uint32_t)ADC_ISQ_IL);
273 ADC_ISQ |= ISQ_IL((uint32_t)(length-1U));
274 break;
275 default:
276 break;
277 }
278 }
279
299 void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time)
300 {
301 uint32_t rsq,sampt;
302
303 /* configure ADC regular sequence */
304 if(rank < 6U){
305 rsq = ADC_RSQ2;
306 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank)));
307 rsq |= ((uint32_t)channel << (5U*rank));
308 ADC_RSQ2 = rsq;
309 }else if(rank < 12U){
310 rsq = ADC_RSQ1;
311 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U))));
312 rsq |= ((uint32_t)channel << (5U*(rank-6U)));
313 ADC_RSQ1 = rsq;
314 }else if(rank < 16U){
315 rsq = ADC_RSQ0;
316 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U))));
317 rsq |= ((uint32_t)channel << (5U*(rank-12U)));
318 ADC_RSQ0 = rsq;
319 }else{
320 }
321
322 /* configure ADC sampling time */
323 if(channel < 10U){
324 sampt = ADC_SAMPT1;
325 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel)));
326 sampt |= (uint32_t)(sample_time << (3U*channel));
327 ADC_SAMPT1 = sampt;
328 }else if(channel < 19U){
329 sampt = ADC_SAMPT0;
330 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel-10U))));
331 sampt |= (uint32_t)(sample_time << (3U*(channel-10U)));
332 ADC_SAMPT0 = sampt;
333 }else{
334 /* illegal parameters */
335 }
336 }
337
357 void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time)
358 {
359 uint8_t inserted_length;
360 uint32_t isq,sampt;
361
362 inserted_length = (uint8_t)GET_BITS(ADC_ISQ , 20U , 21U);
363
364 isq = ADC_ISQ;
365 isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U - (inserted_length - rank)*5U)));
366 isq |= ((uint32_t)channel << (15U - (inserted_length - rank)*5U));
367 ADC_ISQ = isq;
368
369 /* configure ADC sampling time */
370 if(channel < 10U){
371 sampt = ADC_SAMPT1;
372 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel)));
373 sampt |= (uint32_t) sample_time << (3U*channel);
374 ADC_SAMPT1 = sampt;
375 }else if(channel < 19U){
376 sampt = ADC_SAMPT0;
377 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel - 10U))));
378 sampt |= ((uint32_t)sample_time << (3U*(channel - 10U)));
379 ADC_SAMPT0 = sampt;
380 }else{
381 /* illegal parameters */
382 }
383 }
384
397 void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset)
398 {
399 uint8_t inserted_length;
400 uint32_t num = 0U;
401
402 inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U);
403 num = 3U - (inserted_length - inserted_channel);
404
405 if(num <= 3U){
406 /* calculate the offset of the register */
407 num = num * 4U;
408 /* configure the offset of the selected channels */
409 REG32((ADC) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
410 }
411 }
412
423 void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue)
424 {
425 if(newvalue){
426 /* external trigger enable for regular channel */
427 if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
428 ADC_CTL1 |= ADC_CTL1_ETERC;
429 }
430 /* external trigger enable for inserted channel */
431 if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
432 ADC_CTL1 |= ADC_CTL1_ETEIC;
433 }
434 }else{
435 /* external trigger disable for regular channel */
436 if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
437 ADC_CTL1 &= ~ADC_CTL1_ETERC;
438 }
439 /* external trigger disable for inserted channel */
440 if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
441 ADC_CTL1 &= ~ADC_CTL1_ETEIC;
442 }
443 }
444 }
445
475 void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source)
476 {
477 switch(channel_group){
478 case ADC_REGULAR_CHANNEL:
479 /* external trigger select for regular channel */
480 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSRC);
481 ADC_CTL1 |= (uint32_t)external_trigger_source;
482 break;
483 case ADC_INSERTED_CHANNEL:
484 /* external trigger select for inserted channel */
485 ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSIC);
486 ADC_CTL1 |= (uint32_t)external_trigger_source;
487 break;
488 default:
489 break;
490 }
491 }
492
502 void adc_software_trigger_enable(uint8_t channel_group)
503 {
504 /* enable regular group channel software trigger */
505 if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
506 ADC_CTL1 |= ADC_CTL1_SWRCST;
507 }
508 /* enable inserted channel group software trigger */
509 if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
510 ADC_CTL1 |= ADC_CTL1_SWICST;
511 }
512 }
513
520 uint16_t adc_regular_data_read(void)
521 {
522 return ((uint16_t)ADC_RDATA);
523 }
524
536 uint16_t adc_inserted_data_read(uint8_t inserted_channel)
537 {
538 uint32_t idata;
539 /* read the data of the selected channel */
540 switch(inserted_channel){
541 case ADC_INSERTED_CHANNEL_0:
542 idata = ADC_IDATA0;
543 break;
544 case ADC_INSERTED_CHANNEL_1:
545 idata = ADC_IDATA1;
546 break;
547 case ADC_INSERTED_CHANNEL_2:
548 idata = ADC_IDATA2;
549 break;
550 case ADC_INSERTED_CHANNEL_3:
551 idata = ADC_IDATA3;
552 break;
553 default:
554 idata = 0U;
555 break;
556 }
557 return (uint16_t)idata;
558 }
559
572 FlagStatus adc_flag_get(uint32_t flag)
573 {
574 FlagStatus reval = RESET;
575
576 if(ADC_STAT & flag){
577 reval = SET;
578 }
579 return reval;
580 }
581
594 void adc_flag_clear(uint32_t flag)
595 {
596 ADC_STAT &= ~((uint32_t)flag);
597 }
598
609 FlagStatus adc_interrupt_flag_get(uint32_t flag)
610 {
611 FlagStatus interrupt_flag = RESET;
612 uint32_t state;
613
614 /* check the interrupt bits */
615 switch(flag){
616 case ADC_INT_FLAG_WDE:
617 state = ADC_STAT & ADC_STAT_WDE;
618 if((ADC_CTL0 & ADC_CTL0_WDEIE) && state){
619 interrupt_flag = SET;
620 }
621 break;
622 case ADC_INT_FLAG_EOC:
623 state = ADC_STAT & ADC_STAT_EOC;
624 if((ADC_CTL0 & ADC_CTL0_EOCIE) && state){
625 interrupt_flag = SET;
626 }
627 break;
628 case ADC_INT_FLAG_EOIC:
629 state = ADC_STAT & ADC_STAT_EOIC;
630 if((ADC_CTL0 & ADC_CTL0_EOICIE) && state){
631 interrupt_flag = SET;
632 }
633 break;
634 default:
635 break;
636 }
637 return interrupt_flag;
638 }
639
650 void adc_interrupt_flag_clear(uint32_t flag)
651 {
652 ADC_STAT &= ~((uint32_t)flag);
653 }
654
665 void adc_interrupt_enable(uint32_t interrupt)
666 {
667 /* enable analog watchdog interrupt */
668 if(RESET != (interrupt & ADC_INT_WDE)){
669 ADC_CTL0 |= (uint32_t)ADC_CTL0_WDEIE;
670 }
671
672 /* enable end of group conversion interrupt */
673 if(RESET != (interrupt & ADC_INT_EOC)){
674 ADC_CTL0 |= (uint32_t)ADC_CTL0_EOCIE;
675 }
676
677 /* enable end of inserted group conversion interrupt */
678 if(RESET != (interrupt & ADC_INT_EOIC)){
679 ADC_CTL0 |= (uint32_t)ADC_CTL0_EOICIE;
680 }
681 }
682
693 void adc_interrupt_disable(uint32_t interrupt)
694 {
695 /* disable analog watchdog interrupt */
696 if(RESET != (interrupt & ADC_INT_WDE)){
697 ADC_CTL0 &= ~(uint32_t)ADC_CTL0_WDEIE;
698 }
699
700 /* disable end of group conversion interrupt */
701 if(RESET != (interrupt & ADC_INT_EOC)){
702 ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOCIE;
703 }
704
705 /* disable end of inserted group conversion interrupt */
706 if(RESET != (interrupt & ADC_INT_EOIC)){
707 ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOICIE;
708 }
709 }
710
719 void adc_watchdog_single_channel_enable(uint8_t channel)
720 {
721 ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
722
723 ADC_CTL0 |= (uint32_t)channel;
724 ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
725 }
726
737 void adc_watchdog_group_channel_enable(uint8_t channel_group)
738 {
739 ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
740
741 /* select the group */
742 switch(channel_group){
743 case ADC_REGULAR_CHANNEL:
744 ADC_CTL0 |= (uint32_t)ADC_CTL0_RWDEN;
745 break;
746 case ADC_INSERTED_CHANNEL:
747 ADC_CTL0 |= (uint32_t)ADC_CTL0_IWDEN;
748 break;
749 case ADC_REGULAR_INSERTED_CHANNEL:
750 ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
751 break;
752 default:
753 break;
754 }
755 }
756
763 void adc_watchdog_disable(void)
764 {
765 ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
766 }
767
775 void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold)
776 {
777 ADC_WDLT = (uint32_t)WDLT_WDLT(low_threshold);
778 ADC_WDHT = (uint32_t)WDHT_WDHT(high_threshold);
779 }
780
811 void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio)
812 {
813 /* configure ADC oversampling mode */
814 if(ADC_OVERSAMPLING_ONE_CONVERT == mode){
815 ADC_OVSAMPCTL |= (uint32_t)ADC_OVSAMPCTL_TOVS;
816 }else{
817 ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_TOVS);
818 }
819
820 /* configure the shift and ratio */
821 ADC_OVSAMPCTL &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS));
822 ADC_OVSAMPCTL |= ((uint32_t)shift | (uint32_t)ratio);
823 }
824
831 void adc_oversample_mode_enable(void)
832 {
833 ADC_OVSAMPCTL |= ADC_OVSAMPCTL_OVSEN;
834 }
835
842 void adc_oversample_mode_disable(void)
843 {
844 ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN);
845 }
adc_tempsensor_vrefint_enable
void adc_tempsensor_vrefint_enable(void)
enable the temperature sensor and Vrefint channel
Definition: gd32f3x0_adc.c:99
adc_resolution_config
void adc_resolution_config(uint32_t resolution)
configure ADC resolution
Definition: gd32f3x0_adc.c:152
ADC_INT_EOC
#define ADC_INT_EOC
Definition: gd32f3x0_adc.h:251
ADC_STAT_WDE
#define ADC_STAT_WDE
Definition: gd32f3x0_adc.h:45
ADC_IDATA2
#define ADC_IDATA2
Definition: gd32f3x0_adc.h:38
ADC_OVSAMPCTL_TOVS
#define ADC_OVSAMPCTL_TOVS
Definition: gd32f3x0_adc.h:112
ADC_OVSAMPCTL_OVSR
#define ADC_OVSAMPCTL_OVSR
Definition: gd32f3x0_adc.h:110
ADC_IDATA0
#define ADC_IDATA0
Definition: gd32f3x0_adc.h:36
ADC_SAMPT0
#define ADC_SAMPT0
Definition: gd32f3x0_adc.h:24
ADC_CTL1_RSTCLB
#define ADC_CTL1_RSTCLB
Definition: gd32f3x0_adc.h:70
ADC_CTL0_IWDEN
#define ADC_CTL0_IWDEN
Definition: gd32f3x0_adc.h:62
ADC_WDLT
#define ADC_WDLT
Definition: gd32f3x0_adc.h:31
ADC_INT_FLAG_EOIC
#define ADC_INT_FLAG_EOIC
Definition: gd32f3x0_adc.h:257
ADC_CTL1_ETEIC
#define ADC_CTL1_ETEIC
Definition: gd32f3x0_adc.h:74
ADC_INT_FLAG_EOC
#define ADC_INT_FLAG_EOC
Definition: gd32f3x0_adc.h:256
adc_oversample_mode_config
void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio)
configure ADC oversample mode
Definition: gd32f3x0_adc.c:811
ADC_CTL1_DAL
#define ADC_CTL1_DAL
Definition: gd32f3x0_adc.h:72
ADC_CTL0_DRES
#define ADC_CTL0_DRES
Definition: gd32f3x0_adc.h:64
adc_regular_channel_config
void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time)
configure ADC regular channel
Definition: gd32f3x0_adc.c:299
ADC_CTL0_RWDEN
#define ADC_CTL0_RWDEN
Definition: gd32f3x0_adc.h:63
adc_watchdog_disable
void adc_watchdog_disable(void)
disable ADC analog watchdog
Definition: gd32f3x0_adc.c:763
ADC_RDATA
#define ADC_RDATA
Definition: gd32f3x0_adc.h:40
adc_inserted_channel_offset_config
void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset)
configure ADC inserted channel offset
Definition: gd32f3x0_adc.c:397
ADC_ISQ_ISQN
#define ADC_ISQ_ISQN
Definition: gd32f3x0_adc.h:99
ADC_ISQ_IL
#define ADC_ISQ_IL
Definition: gd32f3x0_adc.h:100
ADC_INT_FLAG_WDE
#define ADC_INT_FLAG_WDE
Definition: gd32f3x0_adc.h:255
ADC_CTL0_WDSC
#define ADC_CTL0_WDSC
Definition: gd32f3x0_adc.h:57
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
ADC_DATAALIGN_RIGHT
#define ADC_DATAALIGN_RIGHT
Definition: gd32f3x0_adc.h:131
ADC_CTL1_TSVREN
#define ADC_CTL1_TSVREN
Definition: gd32f3x0_adc.h:79
adc_watchdog_threshold_config
void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold)
configure ADC analog watchdog threshold
Definition: gd32f3x0_adc.c:775
adc_calibration_enable
void adc_calibration_enable(void)
ADC calibration and reset calibration.
Definition: gd32f3x0_adc.c:56
ADC_CTL0_WDCHSEL
#define ADC_CTL0_WDCHSEL
Definition: gd32f3x0_adc.h:52
ADC_CTL0_WDEIE
#define ADC_CTL0_WDEIE
Definition: gd32f3x0_adc.h:54
ADC_CTL1_ETSIC
#define ADC_CTL1_ETSIC
Definition: gd32f3x0_adc.h:73
ADC_RSQ2
#define ADC_RSQ2
Definition: gd32f3x0_adc.h:34
adc_interrupt_flag_get
FlagStatus adc_interrupt_flag_get(uint32_t flag)
get the ADC interrupt flag
Definition: gd32f3x0_adc.c:609
ADC_CTL1_DMA
#define ADC_CTL1_DMA
Definition: gd32f3x0_adc.h:71
ADC_INSERTED_CHANNEL_1
#define ADC_INSERTED_CHANNEL_1
Definition: gd32f3x0_adc.h:224
ADC_ISQ
#define ADC_ISQ
Definition: gd32f3x0_adc.h:35
CTL0_DISNUM
#define CTL0_DISNUM(regval)
Definition: gd32f3x0_adc.h:123
ADC_CTL1_ADCON
#define ADC_CTL1_ADCON
Definition: gd32f3x0_adc.h:67
adc_inserted_channel_config
void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time)
configure ADC inserted channel
Definition: gd32f3x0_adc.c:357
adc_external_trigger_source_config
void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source)
configure ADC external trigger source
Definition: gd32f3x0_adc.c:475
adc_software_trigger_enable
void adc_software_trigger_enable(uint8_t channel_group)
enable ADC software trigger
Definition: gd32f3x0_adc.c:502
adc_interrupt_flag_clear
void adc_interrupt_flag_clear(uint32_t flag)
clear ADC interrupt flag
Definition: gd32f3x0_adc.c:650
ADC_INSERTED_CHANNEL_AUTO
#define ADC_INSERTED_CHANNEL_AUTO
Definition: gd32f3x0_adc.h:127
ADC_CTL1_ETSRC
#define ADC_CTL1_ETSRC
Definition: gd32f3x0_adc.h:75
ADC_CTL0_DISRC
#define ADC_CTL0_DISRC
Definition: gd32f3x0_adc.h:59
adc_special_function_config
void adc_special_function_config(uint32_t function, ControlStatus newvalue)
configure ADC special function
Definition: gd32f3x0_adc.c:201
ADC_RSQ1
#define ADC_RSQ1
Definition: gd32f3x0_adc.h:33
ADC_REGULAR_CHANNEL
#define ADC_REGULAR_CHANNEL
Definition: gd32f3x0_adc.h:217
adc_channel_length_config
void adc_channel_length_config(uint8_t channel_group, uint32_t length)
configure the length of regular channel group or inserted channel group
Definition: gd32f3x0_adc.c:262
ADC_STAT_EOIC
#define ADC_STAT_EOIC
Definition: gd32f3x0_adc.h:47
ADC_CTL1_SWICST
#define ADC_CTL1_SWICST
Definition: gd32f3x0_adc.h:77
ADC_STAT
#define ADC_STAT
Definition: gd32f3x0_adc.h:21
adc_flag_get
FlagStatus adc_flag_get(uint32_t flag)
get the ADC flag bits
Definition: gd32f3x0_adc.c:572
adc_vbat_disable
void adc_vbat_disable(void)
disable the vbat channel
Definition: gd32f3x0_adc.c:135
ADC_CTL0_DISNUM
#define ADC_CTL0_DISNUM
Definition: gd32f3x0_adc.h:61
ADC_INSERTED_CHANNEL_3
#define ADC_INSERTED_CHANNEL_3
Definition: gd32f3x0_adc.h:226
ADC_INT_WDE
#define ADC_INT_WDE
Definition: gd32f3x0_adc.h:250
ADC_RSQX_RSQN
#define ADC_RSQX_RSQN
Definition: gd32f3x0_adc.h:95
ADC_CTL1_CLB
#define ADC_CTL1_CLB
Definition: gd32f3x0_adc.h:69
adc_regular_data_read
uint16_t adc_regular_data_read(void)
read ADC regular group data register
Definition: gd32f3x0_adc.c:520
adc_flag_clear
void adc_flag_clear(uint32_t flag)
clear the ADC flag
Definition: gd32f3x0_adc.c:594
ADC_CONTINUOUS_MODE
#define ADC_CONTINUOUS_MODE
Definition: gd32f3x0_adc.h:128
adc_deinit
void adc_deinit(void)
reset ADC
Definition: gd32f3x0_adc.c:20
adc_inserted_data_read
uint16_t adc_inserted_data_read(uint8_t inserted_channel)
read ADC inserted group data register
Definition: gd32f3x0_adc.c:536
ADC_CHANNEL_DISCON_DISABLE
#define ADC_CHANNEL_DISCON_DISABLE
Definition: gd32f3x0_adc.h:220
ADC
#define ADC
Definition: gd32f3x0_adc.h:18
ISQ_IL
#define ISQ_IL(regval)
Definition: gd32f3x0_adc.h:180
adc_tempsensor_vrefint_disable
void adc_tempsensor_vrefint_disable(void)
disable the temperature sensor and Vrefint channel
Definition: gd32f3x0_adc.c:111
ADC_CTL0_EOICIE
#define ADC_CTL0_EOICIE
Definition: gd32f3x0_adc.h:55
RCU_ADCRST
Definition: gd32f3x0_rcu.h:335
ADC_OVSAMPCTL_OVSS
#define ADC_OVSAMPCTL_OVSS
Definition: gd32f3x0_adc.h:111
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
ADC_OVERSAMPLING_ONE_CONVERT
#define ADC_OVERSAMPLING_ONE_CONVERT
Definition: gd32f3x0_adc.h:214
ADC_OVSAMPCTL_OVSEN
#define ADC_OVSAMPCTL_OVSEN
Definition: gd32f3x0_adc.h:109
ADC_IDATA3
#define ADC_IDATA3
Definition: gd32f3x0_adc.h:39
adc_data_alignment_config
void adc_data_alignment_config(uint32_t data_alignment)
configure ADC data alignment
Definition: gd32f3x0_adc.c:241
adc_disable
void adc_disable(void)
disable ADC interface
Definition: gd32f3x0_adc.c:45
adc_dma_mode_disable
void adc_dma_mode_disable(void)
disable DMA request
Definition: gd32f3x0_adc.c:88
adc_enable
void adc_enable(void)
enable ADC interface
Definition: gd32f3x0_adc.c:32
ADC_INSERTED_CHANNEL_0
#define ADC_INSERTED_CHANNEL_0
Definition: gd32f3x0_adc.h:223
ADC_IDATA1
#define ADC_IDATA1
Definition: gd32f3x0_adc.h:37
adc_watchdog_group_channel_enable
void adc_watchdog_group_channel_enable(uint8_t channel_group)
configure ADC analog watchdog group channel
Definition: gd32f3x0_adc.c:737
WDHT_WDHT
#define WDHT_WDHT(regval)
Definition: gd32f3x0_adc.h:171
ADC_REGULAR_INSERTED_CHANNEL
#define ADC_REGULAR_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:219
ADC_CTL1_ETERC
#define ADC_CTL1_ETERC
Definition: gd32f3x0_adc.h:76
adc_watchdog_single_channel_enable
void adc_watchdog_single_channel_enable(uint8_t channel)
configure ADC analog watchdog single channel
Definition: gd32f3x0_adc.c:719
WDLT_WDLT
#define WDLT_WDLT(regval)
Definition: gd32f3x0_adc.h:174
ADC_WDHT
#define ADC_WDHT
Definition: gd32f3x0_adc.h:30
ADC_RSQ0
#define ADC_RSQ0
Definition: gd32f3x0_adc.h:32
ADC_RSQ0_RL
#define ADC_RSQ0_RL
Definition: gd32f3x0_adc.h:96
ADC_CTL1_VBETEN
#define ADC_CTL1_VBETEN
Definition: gd32f3x0_adc.h:80
adc_vbat_enable
void adc_vbat_enable(void)
enable the vbat channel
Definition: gd32f3x0_adc.c:123
ADC_SCAN_MODE
#define ADC_SCAN_MODE
Definition: gd32f3x0_adc.h:126
ADC_CTL1
#define ADC_CTL1
Definition: gd32f3x0_adc.h:23
adc_interrupt_disable
void adc_interrupt_disable(uint32_t interrupt)
disable ADC interrupt
Definition: gd32f3x0_adc.c:693
ADC_INSERTED_CHANNEL
#define ADC_INSERTED_CHANNEL
Definition: gd32f3x0_adc.h:218
gd32f3x0_adc.h
definitions for the ADC
adc_interrupt_enable
void adc_interrupt_enable(uint32_t interrupt)
enable ADC interrupt
Definition: gd32f3x0_adc.c:665
RSQ0_RL
#define RSQ0_RL(regval)
Definition: gd32f3x0_adc.h:177
ADC_STAT_EOC
#define ADC_STAT_EOC
Definition: gd32f3x0_adc.h:46
ADC_CTL1_SWRCST
#define ADC_CTL1_SWRCST
Definition: gd32f3x0_adc.h:78
adc_dma_mode_enable
void adc_dma_mode_enable(void)
enable DMA request
Definition: gd32f3x0_adc.c:77
ADC_INT_EOIC
#define ADC_INT_EOIC
Definition: gd32f3x0_adc.h:252
IOFFX_IOFF
#define IOFFX_IOFF(regval)
Definition: gd32f3x0_adc.h:168
ADC_SAMPT1
#define ADC_SAMPT1
Definition: gd32f3x0_adc.h:25
ADC_CTL0_EOCIE
#define ADC_CTL0_EOCIE
Definition: gd32f3x0_adc.h:53
ADC_OVSAMPCTL
#define ADC_OVSAMPCTL
Definition: gd32f3x0_adc.h:41
ADC_SAMPTX_SPTN
#define ADC_SAMPTX_SPTN
Definition: gd32f3x0_adc.h:83
adc_external_trigger_config
void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue)
enable or disable ADC external trigger
Definition: gd32f3x0_adc.c:423
adc_oversample_mode_disable
void adc_oversample_mode_disable(void)
disable ADC oversample mode
Definition: gd32f3x0_adc.c:842
ADC_INSERTED_CHANNEL_2
#define ADC_INSERTED_CHANNEL_2
Definition: gd32f3x0_adc.h:225
ADC_CTL0_DISIC
#define ADC_CTL0_DISIC
Definition: gd32f3x0_adc.h:60
adc_oversample_mode_enable
void adc_oversample_mode_enable(void)
enable ADC oversample mode
Definition: gd32f3x0_adc.c:831
ADC_CTL0
#define ADC_CTL0
Definition: gd32f3x0_adc.h:22
adc_discontinuous_mode_config
void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length)
configure ADC discontinuous mode
Definition: gd32f3x0_adc.c:170
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_syscfg.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_syscfg.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_syscfg.h"
13
20 void syscfg_deinit(void)
21 {
22 rcu_periph_reset_enable(RCU_CFGCMPRST);
23 rcu_periph_reset_disable(RCU_CFGCMPRST);
24 }
25
37 void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap)
38 {
39 SYSCFG_CFG0 |= syscfg_dma_remap;
40 }
41
53 void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap)
54 {
55 SYSCFG_CFG0 &= ~syscfg_dma_remap;
56 }
57
64 void syscfg_high_current_enable(void)
65 {
66 SYSCFG_CFG0 |= SYSCFG_HIGH_CURRENT_ENABLE;
67 }
68
75 void syscfg_high_current_disable(void)
76 {
77 SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE;
78 }
79
89 void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin)
90 {
91 uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin)));
92 uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin));
93
94 switch(exti_pin / EXTI_SS_JSTEP){
95 case EXTISS0:
96 /* clear EXTI source line(0..3) */
97 SYSCFG_EXTISS0 &= clear_exti_mask;
98 /* configure EXTI soure line(0..3) */
99 SYSCFG_EXTISS0 |= config_exti_mask;
100 break;
101 case EXTISS1:
102 /* clear EXTI soure line(4..7) */
103 SYSCFG_EXTISS1 &= clear_exti_mask;
104 /* configure EXTI soure line(4..7) */
105 SYSCFG_EXTISS1 |= config_exti_mask;
106 break;
107 case EXTISS2:
108 /* clear EXTI soure line(8..11) */
109 SYSCFG_EXTISS2 &= clear_exti_mask;
110 /* configure EXTI soure line(8..11) */
111 SYSCFG_EXTISS2 |= config_exti_mask;
112 break;
113 case EXTISS3:
114 /* clear EXTI soure line(12..15) */
115 SYSCFG_EXTISS3 &= clear_exti_mask;
116 /* configure EXTI soure line(12..15) */
117 SYSCFG_EXTISS3 |= config_exti_mask;
118 break;
119 default:
120 break;
121 }
122 }
123
133 void syscfg_lock_config(uint32_t syscfg_lock)
134 {
135 SYSCFG_CFG2 |= syscfg_lock;
136 }
137
145 FlagStatus syscfg_flag_get(uint32_t syscfg_flag)
146 {
147 if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET){
148 return SET;
149 }else{
150 return RESET;
151 }
152 }
153
161 void syscfg_flag_clear(uint32_t syscfg_flag)
162 {
163 SYSCFG_CFG2 |= (uint32_t) syscfg_flag;
164 }
165
174 void syscfg_compensation_config(uint32_t syscfg_compensation)
175 {
176 uint32_t reg;
177
178 reg = SYSCFG_CPSCTL;
179 /* reset the SYSCFG_CPSCTL_CPS_EN bit and set according to syscfg_compensation */
180 reg &= ~SYSCFG_CPSCTL_CPS_EN;
181 SYSCFG_CPSCTL = (reg | syscfg_compensation);
182 }
183
190 FlagStatus syscfg_cps_rdy_flag_get(void)
191 {
192 if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)){
193 return SET;
194 }else{
195 return RESET;
196 }
197 }
syscfg_lock_config
void syscfg_lock_config(uint32_t syscfg_lock)
connect TIMER0/14/15/16 break input to the selected parameter
Definition: gd32f3x0_syscfg.c:133
syscfg_high_current_enable
void syscfg_high_current_enable(void)
enable PB9 high current capability
Definition: gd32f3x0_syscfg.c:64
SYSCFG_EXTISS1
#define SYSCFG_EXTISS1
Definition: gd32f3x0_syscfg.h:23
SYSCFG_EXTISS0
#define SYSCFG_EXTISS0
Definition: gd32f3x0_syscfg.h:22
SYSCFG_CPSCTL_CPS_EN
#define SYSCFG_CPSCTL_CPS_EN
Definition: gd32f3x0_syscfg.h:69
EXTI_SS_MASK
#define EXTI_SS_MASK
Definition: gd32f3x0_syscfg.h:91
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
syscfg_dma_remap_disable
void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap)
disable the DMA channels remapping
Definition: gd32f3x0_syscfg.c:53
EXTISS2
#define EXTISS2
Definition: gd32f3x0_syscfg.h:87
SYSCFG_CFG0
#define SYSCFG_CFG0
Definition: gd32f3x0_syscfg.h:21
SYSCFG_HIGH_CURRENT_ENABLE
#define SYSCFG_HIGH_CURRENT_ENABLE
Definition: gd32f3x0_syscfg.h:81
SYSCFG_CFG2
#define SYSCFG_CFG2
Definition: gd32f3x0_syscfg.h:26
syscfg_high_current_disable
void syscfg_high_current_disable(void)
disable PB9 high current capability
Definition: gd32f3x0_syscfg.c:75
SYSCFG_CPSCTL_CPS_RDY
#define SYSCFG_CPSCTL_CPS_RDY
Definition: gd32f3x0_syscfg.h:70
RCU_CFGCMPRST
Definition: gd32f3x0_rcu.h:334
SYSCFG_CPSCTL
#define SYSCFG_CPSCTL
Definition: gd32f3x0_syscfg.h:27
EXTI_SS_JSTEP
#define EXTI_SS_JSTEP
Definition: gd32f3x0_syscfg.h:94
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
syscfg_flag_clear
void syscfg_flag_clear(uint32_t syscfg_flag)
clear the flag in SYSCFG_CFG2 by writing 1.
Definition: gd32f3x0_syscfg.c:161
EXTI_SS_MSTEP
#define EXTI_SS_MSTEP(pin)
Definition: gd32f3x0_syscfg.h:97
syscfg_compensation_config
void syscfg_compensation_config(uint32_t syscfg_compensation)
configure the I/O compensation cell
Definition: gd32f3x0_syscfg.c:174
EXTISS1
#define EXTISS1
Definition: gd32f3x0_syscfg.h:86
SYSCFG_HIGH_CURRENT_DISABLE
#define SYSCFG_HIGH_CURRENT_DISABLE
Definition: gd32f3x0_syscfg.h:82
syscfg_deinit
void syscfg_deinit(void)
reset the SYSCFG registers
Definition: gd32f3x0_syscfg.c:20
syscfg_flag_get
FlagStatus syscfg_flag_get(uint32_t syscfg_flag)
check if the specified flag in SYSCFG_CFG2 is set or not.
Definition: gd32f3x0_syscfg.c:145
SYSCFG_EXTISS3
#define SYSCFG_EXTISS3
Definition: gd32f3x0_syscfg.h:25
EXTISS0
#define EXTISS0
Definition: gd32f3x0_syscfg.h:85
syscfg_dma_remap_enable
void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap)
enable the DMA channels remapping
Definition: gd32f3x0_syscfg.c:37
syscfg_exti_line_config
void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin)
configure the GPIO pin as EXTI Line
Definition: gd32f3x0_syscfg.c:89
syscfg_cps_rdy_flag_get
FlagStatus syscfg_cps_rdy_flag_get(void)
check if the I/O compensation cell ready flag is set or not
Definition: gd32f3x0_syscfg.c:190
gd32f3x0_syscfg.h
definitions for the SYSCFG
SYSCFG_EXTISS2
#define SYSCFG_EXTISS2
Definition: gd32f3x0_syscfg.h:24
EXTISS3
#define EXTISS3
Definition: gd32f3x0_syscfg.h:88
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_crc.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_crc.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_CRC_H
13 #define GD32F3X0_CRC_H
14
15 #include "gd32f3x0.h"
16
17 /* CRC definitions */
18 #define CRC CRC_BASE
19
20 /* registers definitions */
21 #define CRC_DATA REG32((CRC) + 0x00U)
22 #define CRC_FDATA REG32((CRC) + 0x04U)
23 #define CRC_CTL REG32((CRC) + 0x08U)
24 #define CRC_IDATA REG32((CRC) + 0x10U)
25 #define CRC_POLY REG32((CRC) + 0x14U)
27 /* bits definitions */
28 /* CRC_DATA */
29 #define CRC_DATA_DATA BITS(0,31)
31 /* CRC_FDATA */
32 #define CRC_FDATA_FDATA BITS(0,7)
34 /* CRC_CTL */
35 #define CRC_CTL_RST BIT(0)
36 #define CRC_CTL_PS BITS(3,4)
37 #define CRC_CTL_REV_I BITS(5,6)
38 #define CRC_CTL_REV_O BIT(7)
40 /* CRC_INIT */
41 #define CRC_IDATA_IDATA BITS(0,31)
43 /* CRC_POLY */
44 #define CRC_POLY_POLY BITS(0,31)
46 /* constants definitions */
47 /* size of polynomial function */
48 #define CTL_PS(regval) (BITS(3, 4) & ((regval) << 3))
49 #define CRC_CTL_PS_32 CTL_PS(0)
50 #define CRC_CTL_PS_16 CTL_PS(1)
51 #define CRC_CTL_PS_8 CTL_PS(2)
52 #define CRC_CTL_PS_7 CTL_PS(3)
54 /* input data reverse function */
55 #define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5))
56 #define CRC_INPUT_DATA_NOT CTL_REV_I(0)
57 #define CRC_INPUT_DATA_BYTE CTL_REV_I(1)
58 #define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2)
59 #define CRC_INPUT_DATA_WORD CTL_REV_I(3)
61 /* function declarations */
62 /* deinit CRC calculation unit */
63 void crc_deinit(void);
64
65 /* enable the reverse operation of output data */
66 void crc_reverse_output_data_enable(void);
67 /* disable the reverse operation of output data */
68 void crc_reverse_output_data_disable(void);
69
70 /* reset data register to the value of initializaiton data register */
71 void crc_data_register_reset(void);
72 /* read the data register */
73 uint32_t crc_data_register_read(void);
74
75 /* read the free data register */
76 uint8_t crc_free_data_register_read(void);
77 /* write the free data register */
78 void crc_free_data_register_write(uint8_t free_data);
79
80 /* write the initial value register */
81 void crc_init_data_register_write(uint32_t init_data);
82 /* configure the CRC input data function */
83 void crc_input_data_reverse_config(uint32_t data_reverse);
84
85 /* configure the CRC size of polynomial function */
86 void crc_polynomial_size_set(uint32_t poly_size);
87 /* configure the CRC polynomial value function */
88 void crc_polynomial_set(uint32_t poly);
89
90 /* CRC calculate a 32-bit data */
91 uint32_t crc_single_data_calculate(uint32_t sdata);
92 /* CRC calculate a 32-bit data array */
93 uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
94
95 #endif /* GD32F3X0_CRC_H */
crc_block_data_calculate
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
CRC calculate a 32-bit data array.
Definition: gd32f3x0_crc.c:174
crc_free_data_register_read
uint8_t crc_free_data_register_read(void)
read the free data register
Definition: gd32f3x0_crc.c:82
crc_free_data_register_write
void crc_free_data_register_write(uint8_t free_data)
write the free data register
Definition: gd32f3x0_crc.c:95
crc_input_data_reverse_config
void crc_input_data_reverse_config(uint32_t data_reverse)
configure the CRC input data function
Definition: gd32f3x0_crc.c:121
crc_polynomial_size_set
void crc_polynomial_size_set(uint32_t poly_size)
configure the CRC size of polynomial function
Definition: gd32f3x0_crc.c:137
crc_reverse_output_data_enable
void crc_reverse_output_data_enable(void)
enable the reverse operation of output data
Definition: gd32f3x0_crc.c:35
crc_single_data_calculate
uint32_t crc_single_data_calculate(uint32_t sdata)
CRC calculate a 32-bit data.
Definition: gd32f3x0_crc.c:161
crc_data_register_read
uint32_t crc_data_register_read(void)
read the data register
Definition: gd32f3x0_crc.c:69
crc_reverse_output_data_disable
void crc_reverse_output_data_disable(void)
disable the reverse operation of output data
Definition: gd32f3x0_crc.c:47
crc_data_register_reset
void crc_data_register_reset(void)
reset data register to the value of initializaiton data register
Definition: gd32f3x0_crc.c:58
crc_polynomial_set
void crc_polynomial_set(uint32_t poly)
configure the CRC polynomial value function
Definition: gd32f3x0_crc.c:149
crc_deinit
void crc_deinit(void)
deinit CRC calculation unit
Definition: gd32f3x0_crc.c:20
crc_init_data_register_write
void crc_init_data_register_write(uint32_t init_data)
write the initializaiton data register
Definition: gd32f3x0_crc.c:106
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_fwdgt.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_fwdgt.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_FWDGT_H
13 #define GD32F3X0_FWDGT_H
14
15 #include "gd32f3x0.h"
16
17 /* FWDGT definitions */
18 #define FWDGT FWDGT_BASE
19
20 /* registers definitions */
21 #define FWDGT_CTL REG32((FWDGT) + 0x00U)
22 #define FWDGT_PSC REG32((FWDGT) + 0x04U)
23 #define FWDGT_RLD REG32((FWDGT) + 0x08U)
24 #define FWDGT_STAT REG32((FWDGT) + 0x0CU)
25 #define FWDGT_WND REG32((FWDGT) + 0x10U)
27 /* bits definitions */
28 /* FWDGT_CTL */
29 #define FWDGT_CTL_CMD BITS(0,15)
31 /* FWDGT_PSC */
32 #define FWDGT_PSC_PSC BITS(0,2)
34 /* FWDGT_RLD */
35 #define FWDGT_RLD_RLD BITS(0,11)
37 /* FWDGT_STAT */
38 #define FWDGT_STAT_PUD BIT(0)
39 #define FWDGT_STAT_RUD BIT(1)
40 #define FWDGT_STAT_WUD BIT(2)
42 /* FWDGT_WND */
43 #define FWDGT_WND_WND BITS(0,11)
45 /* constants definitions */
46 /* FWDGT_CTL register value */
47 #define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U))
49 /* FWDGT_PSC register value */
50 #define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U))
51 #define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0))
52 #define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1))
53 #define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2))
54 #define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3))
55 #define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4))
56 #define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5))
57 #define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6))
59 /* FWDGT_RLD register value */
60 #define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U))
62 /* FWDGT_WND register value */
63 #define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U))
65 /* control value */
66 #define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U)
67 #define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U)
68 #define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU)
69 #define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU)
71 /* FWDGT timeout value */
72 #define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU)
73 #define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU)
74 #define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU)
76 /* FWDGT flag definitions */
77 #define FWDGT_FLAG_PUD FWDGT_STAT_PUD
78 #define FWDGT_FLAG_RUD FWDGT_STAT_RUD
79 #define FWDGT_FLAG_WUD FWDGT_STAT_WUD
81 /* function declarations */
82 /* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */
83 void fwdgt_write_disable(void);
84 /* start the free watchdog timer counter */
85 void fwdgt_enable(void);
86
87 /* configure the free watchdog timer counter window value */
88 ErrStatus fwdgt_window_value_config(uint16_t window_value);
89 /* reload the counter of FWDGT */
90 void fwdgt_counter_reload(void);
91 /* configure counter reload value, and prescaler divider value */
92 ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
93
94 /* get flag state of FWDGT */
95 FlagStatus fwdgt_flag_get(uint16_t flag);
96
97 #endif /* GD32F3X0_FWDGT_H */
fwdgt_write_disable
void fwdgt_write_disable(void)
disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND
Definition: gd32f3x0_fwdgt.c:20
fwdgt_enable
void fwdgt_enable(void)
start the free watchdog timer counter
Definition: gd32f3x0_fwdgt.c:42
fwdgt_counter_reload
void fwdgt_counter_reload(void)
reload the counter of FWDGT
Definition: gd32f3x0_fwdgt.c:31
fwdgt_window_value_config
ErrStatus fwdgt_window_value_config(uint16_t window_value)
configure the free watchdog timer counter window value
Definition: gd32f3x0_fwdgt.c:53
fwdgt_config
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
configure counter reload value, and prescaler divider value
Definition: gd32f3x0_fwdgt.c:89
fwdgt_flag_get
FlagStatus fwdgt_flag_get(uint16_t flag)
get flag state of FWDGT
Definition: gd32f3x0_fwdgt.c:136
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_cec.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_cec.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifdef GD32F350
13
14 #include "gd32f3x0_cec.h"
15 #include "gd32f3x0_rcu.h"
16
23 void cec_deinit(void)
24 {
25 rcu_periph_reset_enable(RCU_CECRST);
26 rcu_periph_reset_disable(RCU_CECRST);
27 }
28
49 void cec_init(uint32_t sftmopt, uint32_t sft, uint32_t address)
50 {
51 uint32_t cfg;
52 cfg = CEC_CFG;
53 /* clear SFTMOPT bit,SFT[2:0] */
54 cfg &= ~(CEC_CFG_SFTOPT | CEC_CFG_SFT);
55 /* assign SFTMOPT bit,SFT[2:0] */
56 cfg |= (sftmopt | sft);
57 CEC_CFG = cfg;
58 if(CEC_OWN_ADDRESS_CLEAR == address){
59 CEC_CFG &= ~CEC_CFG_OWN_ADDRESS;
60 }else{
61 CEC_CFG |= address;
62 }
63 }
64
83 void cec_error_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre, uint32_t rxbrestp)
84 {
85 uint32_t cfg;
86 cfg = CEC_CFG;
87 /* clear BCNG bit, BPLEG bit, BREG bit */
88 cfg &= ~(CEC_CFG_BCNG | CEC_CFG_BPLEG | CEC_CFG_BREG);
89 /* assign BCNG bit, BPLEG bit, BREG bit */
90 cfg |= (broadcast | singlecast_lbpe | singlecast_bre);
91 CEC_CFG = cfg;
92 if(CEC_STOP_RISING_ERROR_BIT_ON == rxbrestp){
93 CEC_CFG |= CEC_CFG_BRES;
94 }else{
95 CEC_CFG &= ~CEC_CFG_BRES;
96 }
97 }
98
105 void cec_enable(void)
106 {
107 CEC_CTL |= CEC_CTL_CECEN;
108 }
109
116 void cec_disable(void)
117 {
118 CEC_CTL &= ~CEC_CTL_CECEN;
119 }
120
127 void cec_transmission_start(void)
128 {
129 CEC_CTL |= CEC_CTL_STAOM;
130 }
131
138 void cec_transmission_end(void)
139 {
140 CEC_CTL |= CEC_CTL_ENDOM;
141 }
142
149 void cec_listen_mode_enable(void)
150 {
151 CEC_CFG |= CEC_CFG_LMEN;
152 }
153
160 void cec_listen_mode_disable(void)
161 {
162 CEC_CFG &= ~CEC_CFG_LMEN;
163 }
164
173 void cec_own_address_config(uint32_t address)
174 {
175 if(CEC_OWN_ADDRESS_CLEAR == address){
176 CEC_CFG &= ~CEC_CFG_OWN_ADDRESS;
177 } else {
178 CEC_CFG |= address;
179 }
180 }
181
199 void cec_sft_config(uint32_t sftmopt, uint32_t sft)
200 {
201 uint32_t cfg;
202 cfg = CEC_CFG;
203 /* clear SFTMOPT bit,SFT[2:0] */
204 cfg &= ~(CEC_CFG_SFTOPT | CEC_CFG_SFT);
205 /* assign SFTMOPT bit,SFT[2:0] */
206 cfg |= (sftmopt | sft);
207 CEC_CFG = cfg;
208 }
209
224 void cec_generate_errorbit_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre)
225 {
226 uint32_t cfg;
227 cfg = CEC_CFG;
228 /* clear BCNG bit, RLBPEGEN bit, RBREGEN bit */
229 cfg &= ~(CEC_CFG_BCNG | CEC_CFG_BPLEG | CEC_CFG_BREG);
230 /* assign BCNG bit, RLBPEGEN bit, RBREGEN bit */
231 cfg |= (broadcast | singlecast_lbpe | singlecast_bre);
232 CEC_CFG = cfg;
233 }
234
243 void cec_stop_receive_bre_config(uint32_t rxbrestp)
244 {
245 if(CEC_STOP_RISING_ERROR_BIT_ON == rxbrestp){
246 CEC_CFG |= CEC_CFG_BRES;
247 } else {
248 CEC_CFG &= ~CEC_CFG_BRES;
249 }
250 }
251
258 void cec_reception_tolerance_enable(void)
259 {
260 CEC_CFG |= CEC_CFG_RTOL;
261 }
262
269 void cec_reception_tolerance_disable(void)
270 {
271 CEC_CFG &= ~CEC_CFG_RTOL;
272 }
273
280 void cec_data_send(uint8_t data)
281 {
282 CEC_TDATA = (uint32_t)data;
283 }
284
291 uint8_t cec_data_receive(void)
292 {
293 return (uint8_t)CEC_RDATA;
294 }
295
315 FlagStatus cec_interrupt_flag_get(uint32_t flag)
316 {
317 uint32_t interrupt_enable = 0U,interrupt_flag = 0U;
318 interrupt_flag = (CEC_INTF & flag);
319 interrupt_enable = (CEC_INTEN & flag);
320 if(interrupt_flag && interrupt_enable){
321 return SET;
322 }else{
323 return RESET;
324 }
325 }
326
346 void cec_interrupt_flag_clear(uint32_t flag)
347 {
348 CEC_INTF = flag;
349 }
350
370 void cec_interrupt_enable(uint32_t flag)
371 {
372 CEC_INTEN |= flag;
373 }
374
395 void cec_interrupt_disable(uint32_t flag)
396 {
397 CEC_INTEN &= ~flag;
398 }
399
419 FlagStatus cec_flag_get(uint32_t flag)
420 {
421 if(CEC_INTF & flag){
422 return SET;
423 }else{
424 return RESET;
425 }
426 }
427
448 void cec_flag_clear(uint32_t flag)
449 {
450 CEC_INTF |= flag;
451 }
452
453 #endif
gd32f3x0_cec.h
definitions for the CEC
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
gd32f3x0_rcu.h
definitions for the RCU
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_ctc.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_ctc.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_ctc.h"
13
14 #define CTC_FLAG_MASK ((uint32_t)0x00000700U)
15
22 void ctc_deinit(void)
23 {
24 /* reset CTC */
25 rcu_periph_reset_enable(RCU_CTCRST);
26 rcu_periph_reset_disable(RCU_CTCRST);
27 }
28
35 void ctc_irc48m_trim_value_config(uint8_t trim_value)
36 {
37 /* clear TRIMVALUE bits */
38 CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE);
39 /* set TRIMVALUE bits */
40 CTC_CTL0 |= CTL0_TRIMVALUE(trim_value);
41 }
42
49 void ctc_software_refsource_pulse_generate(void)
50 {
51 CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL;
52 }
53
62 void ctc_hardware_trim_mode_config(uint32_t hardmode)
63 {
64 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM);
65 CTC_CTL0 |= (uint32_t)hardmode;
66 }
67
74 void ctc_counter_enable(void)
75 {
76 CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN;
77 }
78
85 void ctc_counter_disable(void)
86 {
87 CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN);
88 }
89
98 void ctc_refsource_polarity_config(uint32_t polarity)
99 {
100 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL);
101 CTC_CTL1 |= (uint32_t)polarity;
102 }
103
113 void ctc_refsource_signal_select(uint32_t refs)
114 {
115 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL);
116 CTC_CTL1 |= (uint32_t)refs;
117 }
118
133 void ctc_refsource_prescaler_config(uint32_t prescaler)
134 {
135 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC);
136 CTC_CTL1 |= (uint32_t)prescaler;
137 }
138
145 void ctc_clock_limit_value_config(uint8_t limit_value)
146 {
147 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM);
148 CTC_CTL1 |= CTL1_CKLIM(limit_value);
149 }
150
157 void ctc_counter_reload_value_config(uint16_t reload_value)
158 {
159 CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE);
160 CTC_CTL1 |= (uint32_t)reload_value;
161 }
162
169 uint16_t ctc_counter_capture_value_read(void)
170 {
171 uint16_t capture_value = 0U;
172 capture_value = (uint16_t)GET_STAT_REFCAP(CTC_STAT);
173 return (capture_value);
174 }
175
184 FlagStatus ctc_counter_direction_read(void)
185 {
186 FlagStatus ret_status = RESET;
187 if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){
188 ret_status = SET;
189 }
190 return ret_status;
191 }
192
199 uint16_t ctc_counter_reload_value_read(void)
200 {
201 uint16_t reload_value = 0U;
202 reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE);
203 return (reload_value);
204 }
205
212 uint8_t ctc_irc48m_trim_value_read(void)
213 {
214 uint8_t trim_value = 0U;
215 trim_value = (uint8_t)GET_CTL0_TRIMVALUE(CTC_CTL0);
216 return (trim_value);
217 }
218
229 void ctc_interrupt_enable(uint32_t interrupt)
230 {
231 CTC_CTL0 |= (uint32_t)interrupt;
232 }
233
244 void ctc_interrupt_disable(uint32_t interrupt)
245 {
246 CTC_CTL0 &= (uint32_t)(~interrupt);
247 }
248
262 FlagStatus ctc_interrupt_flag_get(uint32_t interrupt)
263 {
264 uint32_t ctc_int = 0U, intenable = 0U;
265 FlagStatus ret_status = RESET;
266
267 if(interrupt & CTC_FLAG_MASK){
268 intenable = CTC_CTL0 & CTC_INT_ERR;
269 }else{
270 intenable = CTC_CTL0 & interrupt;
271 }
272 ctc_int = CTC_STAT & interrupt;
273
274 if(ctc_int && intenable){
275 ret_status = SET;
276 }
277 return ret_status;
278 }
279
293 void ctc_interrupt_flag_clear(uint32_t interrupt)
294 {
295 if(interrupt & CTC_FLAG_MASK){
296 CTC_INTC |= CTC_INTC_ERRIC;
297 }else{
298 CTC_INTC |= interrupt;
299 }
300 }
301
315 FlagStatus ctc_flag_get(uint32_t flag)
316 {
317 FlagStatus ret_status = RESET;
318
319 if(RESET != (CTC_STAT & flag)){
320 ret_status = SET;
321 }
322 return ret_status;
323 }
324
338 void ctc_flag_clear(uint32_t flag)
339 {
340 if(flag & CTC_FLAG_MASK){
341 CTC_INTC |= CTC_INTC_ERRIC;
342 }else{
343 CTC_INTC |= flag;
344 }
345 }
CTC_CTL0_CNTEN
#define CTC_CTL0_CNTEN
Definition: gd32f3x0_ctc.h:32
CTC_CTL1_RLVALUE
#define CTC_CTL1_RLVALUE
Definition: gd32f3x0_ctc.h:38
CTC_CTL0_TRIMVALUE
#define CTC_CTL0_TRIMVALUE
Definition: gd32f3x0_ctc.h:35
gd32f3x0_ctc.h
definitions for the CTC
CTC_CTL1_CKLIM
#define CTC_CTL1_CKLIM
Definition: gd32f3x0_ctc.h:39
ctc_counter_reload_value_read
uint16_t ctc_counter_reload_value_read(void)
read CTC counter reload value
Definition: gd32f3x0_ctc.c:199
GET_STAT_REFCAP
#define GET_STAT_REFCAP(regval)
Definition: gd32f3x0_ctc.h:64
CTC_STAT
#define CTC_STAT
Definition: gd32f3x0_ctc.h:23
ctc_counter_capture_value_read
uint16_t ctc_counter_capture_value_read(void)
read CTC counter capture value when reference sync pulse occurred
Definition: gd32f3x0_ctc.c:169
CTC_CTL1_REFSEL
#define CTC_CTL1_REFSEL
Definition: gd32f3x0_ctc.h:41
ctc_interrupt_flag_get
FlagStatus ctc_interrupt_flag_get(uint32_t interrupt)
get CTC interrupt flag
Definition: gd32f3x0_ctc.c:262
ctc_interrupt_disable
void ctc_interrupt_disable(uint32_t interrupt)
disable the CTC interrupt
Definition: gd32f3x0_ctc.c:244
CTC_CTL1
#define CTC_CTL1
Definition: gd32f3x0_ctc.h:22
CTC_STAT_REFDIR
#define CTC_STAT_REFDIR
Definition: gd32f3x0_ctc.h:52
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
CTC_CTL0_AUTOTRIM
#define CTC_CTL0_AUTOTRIM
Definition: gd32f3x0_ctc.h:33
ctc_interrupt_flag_clear
void ctc_interrupt_flag_clear(uint32_t interrupt)
clear CTC interrupt flag
Definition: gd32f3x0_ctc.c:293
CTC_INTC
#define CTC_INTC
Definition: gd32f3x0_ctc.h:24
ctc_refsource_polarity_config
void ctc_refsource_polarity_config(uint32_t polarity)
configure reference signal source polarity
Definition: gd32f3x0_ctc.c:98
ctc_interrupt_enable
void ctc_interrupt_enable(uint32_t interrupt)
enable the CTC interrupt
Definition: gd32f3x0_ctc.c:229
ctc_clock_limit_value_config
void ctc_clock_limit_value_config(uint8_t limit_value)
configure clock trim base limit value
Definition: gd32f3x0_ctc.c:145
ctc_refsource_prescaler_config
void ctc_refsource_prescaler_config(uint32_t prescaler)
configure reference signal source prescaler
Definition: gd32f3x0_ctc.c:133
ctc_counter_disable
void ctc_counter_disable(void)
disable CTC trim counter
Definition: gd32f3x0_ctc.c:85
ctc_software_refsource_pulse_generate
void ctc_software_refsource_pulse_generate(void)
generate software reference source sync pulse
Definition: gd32f3x0_ctc.c:49
CTL1_CKLIM
#define CTL1_CKLIM(regval)
Definition: gd32f3x0_ctc.h:63
CTC_INTC_ERRIC
#define CTC_INTC_ERRIC
Definition: gd32f3x0_ctc.h:58
ctc_hardware_trim_mode_config
void ctc_hardware_trim_mode_config(uint32_t hardmode)
configure hardware automatically trim mode
Definition: gd32f3x0_ctc.c:62
CTC_FLAG_MASK
#define CTC_FLAG_MASK
Definition: gd32f3x0_ctc.c:14
RCU_CTCRST
Definition: gd32f3x0_rcu.h:362
ctc_counter_enable
void ctc_counter_enable(void)
enable CTC trim counter
Definition: gd32f3x0_ctc.c:74
ctc_flag_clear
void ctc_flag_clear(uint32_t flag)
clear CTC flag
Definition: gd32f3x0_ctc.c:338
ctc_refsource_signal_select
void ctc_refsource_signal_select(uint32_t refs)
select reference signal source
Definition: gd32f3x0_ctc.c:113
CTL0_TRIMVALUE
#define CTL0_TRIMVALUE(regval)
Definition: gd32f3x0_ctc.h:62
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
ctc_counter_reload_value_config
void ctc_counter_reload_value_config(uint16_t reload_value)
configure CTC counter reload value
Definition: gd32f3x0_ctc.c:157
ctc_irc48m_trim_value_config
void ctc_irc48m_trim_value_config(uint8_t trim_value)
configure the IRC48M trim value
Definition: gd32f3x0_ctc.c:35
CTC_CTL1_REFPSC
#define CTC_CTL1_REFPSC
Definition: gd32f3x0_ctc.h:40
ctc_deinit
void ctc_deinit(void)
reset CTC clock trim controller
Definition: gd32f3x0_ctc.c:22
CTC_CTL0_SWREFPUL
#define CTC_CTL0_SWREFPUL
Definition: gd32f3x0_ctc.h:34
CTC_INT_ERR
#define CTC_INT_ERR
Definition: gd32f3x0_ctc.h:95
ctc_irc48m_trim_value_read
uint8_t ctc_irc48m_trim_value_read(void)
read the IRC48M trim value
Definition: gd32f3x0_ctc.c:212
ctc_counter_direction_read
FlagStatus ctc_counter_direction_read(void)
read CTC trim counter direction when reference sync pulse occurred
Definition: gd32f3x0_ctc.c:184
CTC_CTL1_REFPOL
#define CTC_CTL1_REFPOL
Definition: gd32f3x0_ctc.h:42
GET_CTL0_TRIMVALUE
#define GET_CTL0_TRIMVALUE(regval)
Definition: gd32f3x0_ctc.h:65
CTC_CTL0
#define CTC_CTL0
Definition: gd32f3x0_ctc.h:21
ctc_flag_get
FlagStatus ctc_flag_get(uint32_t flag)
get CTC flag
Definition: gd32f3x0_ctc.c:315
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_usart.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_usart.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06 V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_usart.h"
13
20 void usart_deinit(uint32_t usart_periph)
21 {
22 switch(usart_periph){
23 case USART0:
24 rcu_periph_reset_enable(RCU_USART0RST);
25 rcu_periph_reset_disable(RCU_USART0RST);
26 break;
27 case USART1:
28 rcu_periph_reset_enable(RCU_USART1RST);
29 rcu_periph_reset_disable(RCU_USART1RST);
30 break;
31 default:
32 break;
33 }
34 }
35
43 void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
44 {
45 uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U;
46 switch(usart_periph){
47 case USART0:
48 uclk = rcu_clock_freq_get(CK_USART);
49 break;
50 case USART1:
51 uclk = rcu_clock_freq_get(CK_APB1);
52 break;
53 default:
54 break;
55 }
56 if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){
57 /* when oversampling by 8,configure the value of USART_BAUD */
58 udiv = ((2U*uclk)+baudval/2U)/baudval;
59 intdiv = udiv & 0xfff0U;
60 fradiv = udiv & 0x7U;
61 USART_BAUD(usart_periph) |= ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
62 }else{
63 /* when oversampling by 16,configure the value of USART_BAUD */
64 udiv = (uclk+baudval/2U)/baudval;
65 intdiv = udiv & 0xfff0U;
66 fradiv = udiv & 0xfU;
67 USART_BAUD(usart_periph) |= ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
68 }
69 }
70
81 void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg)
82 {
83 /* disable USART */
84 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
85 /* clear USART_CTL0 PM,PCEN bits */
86 USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN);
87 /* configure USART parity mode */
88 USART_CTL0(usart_periph) |= paritycfg;
89 }
90
100 void usart_word_length_set(uint32_t usart_periph, uint32_t wlen)
101 {
102 /* disable USART */
103 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
104 /* clear USART_CTL0 WL bit */
105 USART_CTL0(usart_periph) &= ~USART_CTL0_WL;
106 /* configure USART word length */
107 USART_CTL0(usart_periph) |= wlen;
108 }
109
121 void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen)
122 {
123 /* disable USART */
124 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
125 /* clear USART_CTL1 STB bits */
126 USART_CTL1(usart_periph) &= ~USART_CTL1_STB;
127 USART_CTL1(usart_periph) |= stblen;
128 }
129
136 void usart_enable(uint32_t usart_periph)
137 {
138 USART_CTL0(usart_periph) |= USART_CTL0_UEN;
139 }
140
147 void usart_disable(uint32_t usart_periph)
148 {
149 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
150 }
151
161 void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig)
162 {
163 USART_CTL0(usart_periph) &= ~USART_CTL0_TEN;
164 /* configure transfer mode */
165 USART_CTL0(usart_periph) |= txconfig;
166 }
167
177 void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig)
178 {
179 USART_CTL0(usart_periph) &= ~USART_CTL0_REN;
180 /* configure receiver mode */
181 USART_CTL0(usart_periph) |= rxconfig;
182 }
183
191 void usart_data_transmit(uint32_t usart_periph, uint32_t data)
192 {
193 USART_TDATA(usart_periph) = (USART_TDATA_TDATA & data);
194 }
195
202 uint16_t usart_data_receive(uint32_t usart_periph)
203 {
204 return (uint16_t)(GET_BITS(USART_RDATA(usart_periph), 0U, 8U));
205 }
206
216 void usart_data_first_config(uint32_t usart_periph, uint32_t msbf)
217 {
218 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
219 /* configure LSB or MSB first */
220 USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF);
221 USART_CTL1(usart_periph) |= (USART_CTL1_MSBF & msbf);
222 }
223
231 void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara)
232 {
233 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
234 /* inverted or not the specified signal */
235 switch(invertpara){
236 case USART_DINV_ENABLE:
237 USART_CTL1(usart_periph) |= USART_CTL1_DINV;
238 break;
239 case USART_DINV_DISABLE:
240 USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV);
241 break;
242 case USART_TXPIN_DISABLE:
243 USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV);
244 break;
245 case USART_RXPIN_DISABLE:
246 USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV);
247 break;
248 case USART_SWAP_DISABLE:
249 USART_CTL1(usart_periph) &= ~(USART_CTL1_STRP);
250 break;
251 case USART_TXPIN_ENABLE:
252 USART_CTL1(usart_periph) |= USART_CTL1_TINV;
253 break;
254 case USART_RXPIN_ENABLE:
255 USART_CTL1(usart_periph) |= USART_CTL1_RINV;
256 break;
257 case USART_SWAP_ENABLE:
258 USART_CTL1(usart_periph) |= USART_CTL1_STRP;
259 break;
260 default:
261 break;
262 }
263 }
264
271 void usart_overrun_enable(uint32_t usart_periph)
272 {
273 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
274 /* enable overrun function */
275 USART_CTL2(usart_periph) &= ~(USART_CTL2_OVRD);
276 }
277
284 void usart_overrun_disable(uint32_t usart_periph)
285 {
286 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
287 /* disable overrun function */
288 USART_CTL2(usart_periph) |= USART_CTL2_OVRD;
289 }
290
300 void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp)
301 {
302 /* disable USART */
303 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
304 /* clear OVSMOD bit */
305 USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD);
306 USART_CTL0(usart_periph) |= oversamp;
307 }
308
318 void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb)
319 {
320 /* disable USART */
321 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
322
323 USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB);
324 USART_CTL2(usart_periph) |= osb;
325 }
326
333 void usart_autobaud_detection_enable(uint32_t usart_periph)
334 {
335 USART_CTL1(usart_periph) |= USART_CTL1_ABDEN;
336 }
337
344 void usart_autobaud_detection_disable(uint32_t usart_periph)
345 {
346 USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDEN);
347 }
348
358 void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod)
359 {
360 /* reset ABDM bits */
361 USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDM);
362 USART_CTL1(usart_periph) |= abdmod;
363 }
364
371 void usart_mute_mode_enable(uint32_t usart_periph)
372 {
373 USART_CTL0(usart_periph) |= USART_CTL0_MEN;
374 }
375
382 void usart_mute_mode_disable(uint32_t usart_periph)
383 {
384 USART_CTL0(usart_periph) &= ~(USART_CTL0_MEN);
385 }
386
396 void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod)
397 {
398 /* disable USART */
399 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
400
401 USART_CTL0(usart_periph) &= ~(USART_CTL0_WM);
402 USART_CTL0(usart_periph) |= wmethod;
403 }
404
414 void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod)
415 {
416 /* disable USART */
417 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
418
419 USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDM);
420 USART_CTL1(usart_periph) |= USART_CTL1_ADDM & (addmod);
421 }
422
430 void usart_address_config(uint32_t usart_periph, uint8_t addr)
431 {
432 /* disable USART */
433 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
434
435 USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR);
436 USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (((uint32_t)addr) << 24));
437 }
438
445 void usart_receiver_timeout_enable(uint32_t usart_periph)
446 {
447 USART_CTL1(usart_periph) |= USART_CTL1_RTEN;
448 }
449
456 void usart_receiver_timeout_disable(uint32_t usart_periph)
457 {
458 USART_CTL1(usart_periph) &= ~(USART_CTL1_RTEN);
459 }
460
468 void usart_receiver_timeout_config(uint32_t usart_periph, uint32_t rtimeout)
469 {
470 USART_RT(usart_periph) &= ~(USART_RT_RT);
471 USART_RT(usart_periph) |= rtimeout;
472 }
473
480 void usart_lin_mode_enable(uint32_t usart_periph)
481 {
482 /* disable USART */
483 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
484
485 USART_CTL1(usart_periph) |= USART_CTL1_LMEN;
486 }
487
494 void usart_lin_mode_disable(uint32_t usart_periph)
495 {
496 /* disable USART */
497 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
498
499 USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN);
500 }
501
511 void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen)
512 {
513 /* disable USART */
514 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
515
516 USART_CTL1(usart_periph) |= USART_CTL1_LBLEN & (lblen);
517 }
518
525 void usart_halfduplex_enable(uint32_t usart_periph)
526 {
527 /* disable USART */
528 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
529
530 USART_CTL2(usart_periph) |= USART_CTL2_HDEN;
531 }
532
539 void usart_halfduplex_disable(uint32_t usart_periph)
540 {
541 /* disable USART */
542 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
543
544 USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN);
545 }
546
553 void usart_clock_enable(uint32_t usart_periph)
554 {
555 /* disable USART */
556 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
557
558 USART_CTL1(usart_periph) |= USART_CTL1_CKEN;
559 }
560
567 void usart_clock_disable(uint32_t usart_periph)
568 {
569 /* disable USART */
570 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
571
572 USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN);
573 }
574
590 void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
591 {
592 /* disable USART */
593 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
594 /* reset USART_CTL1 CLEN,CPH,CPL bits */
595 USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL);
596
597 USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen);
598 USART_CTL1(usart_periph) |= (USART_CTL1_CPH & cph);
599 USART_CTL1(usart_periph) |= (USART_CTL1_CPL & cpl);
600 }
601
608 void usart_smartcard_mode_enable(uint32_t usart_periph)
609 {
610 /* disable USART */
611 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
612
613 USART_CTL2(usart_periph) |= USART_CTL2_SCEN;
614 }
615
622 void usart_smartcard_mode_disable(uint32_t usart_periph)
623 {
624 /* disable USART */
625 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
626
627 USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN);
628 }
629
636 void usart_smartcard_mode_nack_enable(uint32_t usart_periph)
637 {
638 /* disable USART */
639 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
640
641 USART_CTL2(usart_periph) |= USART_CTL2_NKEN;
642 }
643
650 void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
651 {
652 /* disable USART */
653 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
654
655 USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN);
656 }
657
665 void usart_guard_time_config(uint32_t usart_periph, uint32_t guat)
666 {
667 /* disable USART */
668 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
669
670 USART_GP(usart_periph) &= ~(USART_GP_GUAT);
671 USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << 8));
672 }
673
681 void usart_block_length_config(uint32_t usart_periph, uint32_t bl)
682 {
683 USART_RT(usart_periph) &= ~(USART_RT_BL);
684 USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << 24));
685 }
686
694 void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum)
695 {
696 /* disable USART */
697 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
698 USART_CTL2(usart_periph) &= ~(USART_CTL2_SCRTNUM);
699 USART_CTL2(usart_periph) |= (USART_CTL2_SCRTNUM & (scrtnum << 17));
700 }
701
708 void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph)
709 {
710 USART_RFCS(usart_periph) |= USART_RFCS_ELNACK;
711 }
712
719 void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph)
720 {
721 USART_RFCS(usart_periph) &= ~USART_RFCS_ELNACK;
722 }
723
730 void usart_irda_mode_enable(uint32_t usart_periph)
731 {
732 /* disable USART */
733 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
734
735 USART_CTL2(usart_periph) |= USART_CTL2_IREN;
736 }
737
744 void usart_irda_mode_disable(uint32_t usart_periph)
745 {
746 /* disable USART */
747 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
748
749 USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN);
750 }
751
761 void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp)
762 {
763 /* disable USART */
764 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
765
766 USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp);
767 }
768
776 void usart_prescaler_config(uint32_t usart_periph, uint32_t psc)
777 {
778 /* disable USART */
779 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
780 USART_GP(usart_periph) &= ~(USART_GP_PSC);
781 USART_GP(usart_periph) |= psc;
782 }
783
793 void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
794 {
795 /* disable USART */
796 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
797
798 USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN);
799 USART_CTL2(usart_periph) |= rtsconfig;
800 }
801
811 void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
812 {
813 /* disable USART */
814 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
815
816 USART_CTL2(usart_periph) &= ~USART_CTL2_CTSEN;
817 USART_CTL2(usart_periph) |= ctsconfig;
818 }
819
826 void usart_rs485_driver_enable(uint32_t usart_periph)
827 {
828 /* disable USART */
829 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
830
831 USART_CTL2(usart_periph) |= USART_CTL2_DEM;
832 }
833
840 void usart_rs485_driver_disable(uint32_t usart_periph)
841 {
842 /* disable USART */
843 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
844
845 USART_CTL2(usart_periph) &= ~(USART_CTL2_DEM);
846 }
847
855 void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime)
856 {
857 /* disable USART */
858 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
859
860 USART_CTL0(usart_periph) &= ~(USART_CTL0_DEA);
861 USART_CTL0(usart_periph) |= (USART_CTL0_DEA & ((deatime) << 21));
862 }
863
871 void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime)
872 {
873 /* disable USART */
874 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
875
876 USART_CTL0(usart_periph) &= ~(USART_CTL0_DED);
877 USART_CTL0(usart_periph) |= (USART_CTL0_DED & ((dedtime) << 16));
878 }
879
889 void usart_depolarity_config(uint32_t usart_periph, uint32_t dep)
890 {
891 /* disable USART */
892 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
893 /* reset DEP bit */
894 USART_CTL2(usart_periph) &= ~(USART_CTL2_DEP);
895 USART_CTL2(usart_periph) |= (USART_CTL2_DEP & dep);
896 }
897
907 void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
908 {
909 USART_CTL2(usart_periph) &= ~USART_CTL2_DENR;
910 /* configure DMA reception */
911 USART_CTL2(usart_periph) |= dmacmd;
912 }
913
923 void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
924 {
925 USART_CTL2(usart_periph) &= ~USART_CTL2_DENT;
926 /* configure DMA transmission */
927 USART_CTL2(usart_periph) |= dmacmd;
928 }
929
936 void usart_reception_error_dma_disable(uint32_t usart_periph)
937 {
938 /* disable USART */
939 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
940
941 USART_CTL2(usart_periph) |= USART_CTL2_DDRE;
942 }
943
950 void usart_reception_error_dma_enable(uint32_t usart_periph)
951 {
952 /* disable USART */
953 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
954
955 USART_CTL2(usart_periph) &= ~(USART_CTL2_DDRE);
956 }
957
964 void usart_wakeup_enable(uint32_t usart_periph)
965 {
966 USART_CTL0(usart_periph) |= USART_CTL0_UESM;
967 }
968
975 void usart_wakeup_disable(uint32_t usart_periph)
976 {
977 USART_CTL0(usart_periph) &= ~(USART_CTL0_UESM);
978 }
979
990 void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum)
991 {
992 /* disable USART */
993 USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
994 /* reset WUM bit */
995 USART_CTL2(usart_periph) &= ~(USART_CTL2_WUM);
996 USART_CTL2(usart_periph) |= USART_CTL2_WUM & (wum);
997 }
998
1005 void usart_receive_fifo_enable(uint32_t usart_periph)
1006 {
1007 USART_RFCS(usart_periph) |= USART_RFCS_RFEN;
1008 }
1009
1016 void usart_receive_fifo_disable(uint32_t usart_periph)
1017 {
1018 USART_RFCS(usart_periph) &= ~(USART_RFCS_RFEN);
1019 }
1020
1027 uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph)
1028 {
1029 return (uint8_t)(GET_BITS(USART_RFCS(usart_periph), 12U, 14U));
1030 }
1031
1064 FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
1065 {
1066 if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){
1067 return SET;
1068 }else{
1069 return RESET;
1070 }
1071 }
1072
1092 void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
1093 {
1094 USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag));
1095 }
1096
1118 void usart_interrupt_enable(uint32_t usart_periph, uint32_t inttype)
1119 {
1120 USART_REG_VAL(usart_periph, inttype) |= BIT(USART_BIT_POS(inttype));
1121 }
1122
1144 void usart_interrupt_disable(uint32_t usart_periph, uint32_t inttype)
1145 {
1146 USART_REG_VAL(usart_periph, inttype) &= ~BIT(USART_BIT_POS(inttype));
1147 }
1148
1161 void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype)
1162 {
1163 USART_CMD(usart_periph) |= (cmdtype);
1164 }
1165
1189 FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
1190 {
1191 uint32_t intenable = 0U, flagstatus = 0U;
1192 /* get the interrupt enable bit status */
1193 intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)));
1194 /* get the corresponding flag bit status */
1195 flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
1196
1197 if(flagstatus && intenable){
1198 return SET;
1199 }else{
1200 return RESET;
1201 }
1202 }
1203
1223 void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag)
1224 {
1225 USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(flag));
1226 }
CK_APB1
Definition: gd32f3x0_rcu.h:456
USART_CTL2_DENR
#define USART_CTL2_DENR
Definition: gd32f3x0_usart.h:85
USART_CTL2_OSB
#define USART_CTL2_OSB
Definition: gd32f3x0_usart.h:90
usart_deinit
void usart_deinit(uint32_t usart_periph)
reset USART
Definition: gd32f3x0_usart.c:20
usart_interrupt_flag_get
FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
get USART interrupt and flag status
Definition: gd32f3x0_usart.c:1189
usart_hardware_flow_cts_config
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
configure hardware flow control CTS
Definition: gd32f3x0_usart.c:811
USART_DINV_DISABLE
Definition: gd32f3x0_usart.h:271
USART_CTL1_ADDM
#define USART_CTL1_ADDM
Definition: gd32f3x0_usart.h:59
usart_receive_config
void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig)
configure USART receiver
Definition: gd32f3x0_usart.c:177
USART_CTL1_TINV
#define USART_CTL1_TINV
Definition: gd32f3x0_usart.h:70
usart_mute_mode_enable
void usart_mute_mode_enable(uint32_t usart_periph)
mute mode enable
Definition: gd32f3x0_usart.c:371
usart_lin_mode_disable
void usart_lin_mode_disable(uint32_t usart_periph)
LIN mode disable.
Definition: gd32f3x0_usart.c:494
USART_BIT_POS2
#define USART_BIT_POS2(val)
Definition: gd32f3x0_usart.h:180
RCU_USART0RST
Definition: gd32f3x0_rcu.h:338
usart_mute_mode_disable
void usart_mute_mode_disable(uint32_t usart_periph)
mute mode disable
Definition: gd32f3x0_usart.c:382
usart_interrupt_flag_clear
void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag)
clear USART interrupt flag
Definition: gd32f3x0_usart.c:1223
USART_CTL0_PM
#define USART_CTL0_PM
Definition: gd32f3x0_usart.h:46
USART_RT_RT
#define USART_RT_RT
Definition: gd32f3x0_usart.h:108
usart_smartcard_mode_nack_enable
void usart_smartcard_mode_nack_enable(uint32_t usart_periph)
NACK enable in smartcard mode.
Definition: gd32f3x0_usart.c:636
USART_CTL1_LBLEN
#define USART_CTL1_LBLEN
Definition: gd32f3x0_usart.h:60
USART_CTL0_WM
#define USART_CTL0_WM
Definition: gd32f3x0_usart.h:48
usart_smartcard_mode_disable
void usart_smartcard_mode_disable(uint32_t usart_periph)
smartcard mode disable
Definition: gd32f3x0_usart.c:622
usart_data_first_config
void usart_data_first_config(uint32_t usart_periph, uint32_t msbf)
data is transmitted/received with the LSB/MSB first
Definition: gd32f3x0_usart.c:216
USART_RDATA
#define USART_RDATA(usartx)
Definition: gd32f3x0_usart.h:31
usart_interrupt_enable
void usart_interrupt_enable(uint32_t usart_periph, uint32_t inttype)
enable USART interrupt
Definition: gd32f3x0_usart.c:1118
USART_CTL1_RTEN
#define USART_CTL1_RTEN
Definition: gd32f3x0_usart.h:75
usart_wakeup_mode_config
void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum)
wakeup mode from deep-sleep mode
Definition: gd32f3x0_usart.c:990
usart_stop_bit_set
void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen)
configure USART stop bit length
Definition: gd32f3x0_usart.c:121
usart_driver_assertime_config
void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime)
driver enable assertion time configure
Definition: gd32f3x0_usart.c:855
USART_CTL1_RINV
#define USART_CTL1_RINV
Definition: gd32f3x0_usart.h:69
USART_CTL0
#define USART_CTL0(usartx)
Definition: gd32f3x0_usart.h:22
usart_autobaud_detection_disable
void usart_autobaud_detection_disable(uint32_t usart_periph)
auto baud rate detection disable
Definition: gd32f3x0_usart.c:344
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
USART_CTL2_OVRD
#define USART_CTL2_OVRD
Definition: gd32f3x0_usart.h:91
usart_baudrate_set
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
configure USART baud rate value
Definition: gd32f3x0_usart.c:43
USART_TDATA_TDATA
#define USART_TDATA_TDATA
Definition: gd32f3x0_usart.h:160
usart_invert_enum
usart_invert_enum
Definition: gd32f3x0_usart.h:268
USART_CTL1
#define USART_CTL1(usartx)
Definition: gd32f3x0_usart.h:23
USART_TXPIN_ENABLE
Definition: gd32f3x0_usart.h:273
USART_GP
#define USART_GP(usartx)
Definition: gd32f3x0_usart.h:26
usart_clock_enable
void usart_clock_enable(uint32_t usart_periph)
clock enable
Definition: gd32f3x0_usart.c:553
gd32f3x0_usart.h
definitions for the USART
usart_clock_disable
void usart_clock_disable(uint32_t usart_periph)
clock disable
Definition: gd32f3x0_usart.c:567
USART_CTL1_STRP
#define USART_CTL1_STRP
Definition: gd32f3x0_usart.h:68
USART_REG_VAL2
#define USART_REG_VAL2(usartx, offset)
Definition: gd32f3x0_usart.h:179
USART_CTL2_DEM
#define USART_CTL2_DEM
Definition: gd32f3x0_usart.h:93
USART_CTL1_DINV
#define USART_CTL1_DINV
Definition: gd32f3x0_usart.h:71
usart_depolarity_config
void usart_depolarity_config(uint32_t usart_periph, uint32_t dep)
configure driver enable polarity mode
Definition: gd32f3x0_usart.c:889
USART_CTL1_ABDEN
#define USART_CTL1_ABDEN
Definition: gd32f3x0_usart.h:73
CK_USART
Definition: gd32f3x0_rcu.h:460
usart_block_length_config
void usart_block_length_config(uint32_t usart_periph, uint32_t bl)
block length configure
Definition: gd32f3x0_usart.c:681
usart_halfduplex_disable
void usart_halfduplex_disable(uint32_t usart_periph)
half-duplex disable
Definition: gd32f3x0_usart.c:539
USART_CTL2_SCEN
#define USART_CTL2_SCEN
Definition: gd32f3x0_usart.h:84
RCU_USART1RST
Definition: gd32f3x0_rcu.h:350
usart_flag_get
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
get flag in STAT/RFCS register
Definition: gd32f3x0_usart.c:1064
usart_irda_lowpower_config
void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp)
IrDA low-power configure.
Definition: gd32f3x0_usart.c:761
USART_CTL0_TEN
#define USART_CTL0_TEN
Definition: gd32f3x0_usart.h:40
USART_CTL1_LMEN
#define USART_CTL1_LMEN
Definition: gd32f3x0_usart.h:67
usart_irda_mode_enable
void usart_irda_mode_enable(uint32_t usart_periph)
IrDA mode enable.
Definition: gd32f3x0_usart.c:730
USART_RFCS
#define USART_RFCS(usartx)
Definition: gd32f3x0_usart.h:33
usart_lin_break_dection_length_config
void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen)
LIN break detection length.
Definition: gd32f3x0_usart.c:511
usart_hardware_flow_rts_config
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
configure hardware flow control RTS
Definition: gd32f3x0_usart.c:793
usart_oversample_config
void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp)
configure the USART oversample mode
Definition: gd32f3x0_usart.c:300
USART_TXPIN_DISABLE
Definition: gd32f3x0_usart.h:274
usart_rs485_driver_disable
void usart_rs485_driver_disable(uint32_t usart_periph)
RS485 driver disable.
Definition: gd32f3x0_usart.c:840
USART_RXPIN_ENABLE
Definition: gd32f3x0_usart.h:276
USART_SWAP_DISABLE
Definition: gd32f3x0_usart.h:280
USART_CTL0_DEA
#define USART_CTL0_DEA
Definition: gd32f3x0_usart.h:54
usart_flag_enum
usart_flag_enum
Definition: gd32f3x0_usart.h:190
USART_DINV_ENABLE
Definition: gd32f3x0_usart.h:270
usart_smartcard_mode_nack_disable
void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
NACK disable in smartcard mode.
Definition: gd32f3x0_usart.c:650
usart_receiver_timeout_enable
void usart_receiver_timeout_enable(uint32_t usart_periph)
receiver timeout enable
Definition: gd32f3x0_usart.c:445
USART_CTL0_OVSMOD
#define USART_CTL0_OVSMOD
Definition: gd32f3x0_usart.h:52
usart_lin_mode_enable
void usart_lin_mode_enable(uint32_t usart_periph)
LIN mode enable.
Definition: gd32f3x0_usart.c:480
USART_CTL1_STB
#define USART_CTL1_STB
Definition: gd32f3x0_usart.h:66
usart_smartcard_mode_early_nack_enable
void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph)
early NACK enable in smartcard mode
Definition: gd32f3x0_usart.c:708
USART_CTL0_REN
#define USART_CTL0_REN
Definition: gd32f3x0_usart.h:39
usart_disable
void usart_disable(uint32_t usart_periph)
disable USART
Definition: gd32f3x0_usart.c:147
usart_data_transmit
void usart_data_transmit(uint32_t usart_periph, uint32_t data)
USART transmit data function.
Definition: gd32f3x0_usart.c:191
usart_halfduplex_enable
void usart_halfduplex_enable(uint32_t usart_periph)
half-duplex enable
Definition: gd32f3x0_usart.c:525
USART_CTL0_WL
#define USART_CTL0_WL
Definition: gd32f3x0_usart.h:49
USART_BIT_POS
#define USART_BIT_POS(val)
Definition: gd32f3x0_usart.h:176
usart_rs485_driver_enable
void usart_rs485_driver_enable(uint32_t usart_periph)
RS485 driver enable.
Definition: gd32f3x0_usart.c:826
usart_address_detection_mode_config
void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod)
address detection mode configure
Definition: gd32f3x0_usart.c:414
USART_CTL1_CLEN
#define USART_CTL1_CLEN
Definition: gd32f3x0_usart.h:62
USART_GP_GUAT
#define USART_GP_GUAT
Definition: gd32f3x0_usart.h:105
USART_RT
#define USART_RT(usartx)
Definition: gd32f3x0_usart.h:27
USART_CTL2_WUM
#define USART_CTL2_WUM
Definition: gd32f3x0_usart.h:96
USART_GP_PSC
#define USART_GP_PSC
Definition: gd32f3x0_usart.h:104
USART_CTL2_RTSEN
#define USART_CTL2_RTSEN
Definition: gd32f3x0_usart.h:87
USART_CTL2_CTSEN
#define USART_CTL2_CTSEN
Definition: gd32f3x0_usart.h:88
USART_CTL1_CKEN
#define USART_CTL1_CKEN
Definition: gd32f3x0_usart.h:65
USART_CTL2_SCRTNUM
#define USART_CTL2_SCRTNUM
Definition: gd32f3x0_usart.h:95
USART_CTL1_ADDR
#define USART_CTL1_ADDR
Definition: gd32f3x0_usart.h:76
USART_CTL2_IREN
#define USART_CTL2_IREN
Definition: gd32f3x0_usart.h:80
USART_CTL0_PCEN
#define USART_CTL0_PCEN
Definition: gd32f3x0_usart.h:47
usart_driver_deassertime_config
void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime)
driver enable de-assertion time configure
Definition: gd32f3x0_usart.c:871
USART_RT_BL
#define USART_RT_BL
Definition: gd32f3x0_usart.h:109
usart_smartcard_mode_early_nack_disable
void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph)
early NACK disable in smartcard mode
Definition: gd32f3x0_usart.c:719
usart_receive_fifo_enable
void usart_receive_fifo_enable(uint32_t usart_periph)
receive FIFO enable
Definition: gd32f3x0_usart.c:1005
usart_smartcard_autoretry_config
void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum)
smartcard auto-retry number configure
Definition: gd32f3x0_usart.c:694
usart_smartcard_mode_enable
void usart_smartcard_mode_enable(uint32_t usart_periph)
smartcard mode enable
Definition: gd32f3x0_usart.c:608
usart_irda_mode_disable
void usart_irda_mode_disable(uint32_t usart_periph)
IrDA mode disable.
Definition: gd32f3x0_usart.c:744
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
USART_CMD
#define USART_CMD(usartx)
Definition: gd32f3x0_usart.h:28
USART1
#define USART1
Definition: gd32f3x0_usart.h:19
USART0
#define USART0
Definition: gd32f3x0_usart.h:18
USART_SWAP_ENABLE
Definition: gd32f3x0_usart.h:279
USART_INTC
#define USART_INTC(usartx)
Definition: gd32f3x0_usart.h:30
USART_CTL2_IRLP
#define USART_CTL2_IRLP
Definition: gd32f3x0_usart.h:81
USART_CTL1_CPH
#define USART_CTL1_CPH
Definition: gd32f3x0_usart.h:63
USART_CTL2_NKEN
#define USART_CTL2_NKEN
Definition: gd32f3x0_usart.h:83
usart_autobaud_detection_mode_config
void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod)
auto baud rate detection mode configure
Definition: gd32f3x0_usart.c:358
USART_CTL2_DEP
#define USART_CTL2_DEP
Definition: gd32f3x0_usart.h:94
usart_command_enable
void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype)
enable USART command
Definition: gd32f3x0_usart.c:1161
usart_autobaud_detection_enable
void usart_autobaud_detection_enable(uint32_t usart_periph)
auto baud rate detection enable
Definition: gd32f3x0_usart.c:333
USART_CTL1_ABDM
#define USART_CTL1_ABDM
Definition: gd32f3x0_usart.h:74
USART_REG_VAL
#define USART_REG_VAL(usartx, offset)
Definition: gd32f3x0_usart.h:175
USART_CTL1_MSBF
#define USART_CTL1_MSBF
Definition: gd32f3x0_usart.h:72
usart_dma_receive_config
void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA reception
Definition: gd32f3x0_usart.c:907
usart_flag_clear
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
clear USART status
Definition: gd32f3x0_usart.c:1092
usart_wakeup_disable
void usart_wakeup_disable(uint32_t usart_periph)
USART be not able to wake up the MCU from deep-sleep mode.
Definition: gd32f3x0_usart.c:975
usart_wakeup_enable
void usart_wakeup_enable(uint32_t usart_periph)
USART be able to wake up the MCU from deep-sleep mode.
Definition: gd32f3x0_usart.c:964
usart_interrupt_disable
void usart_interrupt_disable(uint32_t usart_periph, uint32_t inttype)
disable USART interrupt
Definition: gd32f3x0_usart.c:1144
USART_CTL0_UEN
#define USART_CTL0_UEN
Definition: gd32f3x0_usart.h:37
USART_CTL0_DED
#define USART_CTL0_DED
Definition: gd32f3x0_usart.h:53
usart_transmit_config
void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig)
configure USART transmitter
Definition: gd32f3x0_usart.c:161
USART_RFCS_ELNACK
#define USART_RFCS_ELNACK
Definition: gd32f3x0_usart.h:163
usart_sample_bit_config
void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb)
sample bit method configure
Definition: gd32f3x0_usart.c:318
USART_CTL0_MEN
#define USART_CTL0_MEN
Definition: gd32f3x0_usart.h:50
usart_reception_error_dma_disable
void usart_reception_error_dma_disable(uint32_t usart_periph)
disable DMA on reception error
Definition: gd32f3x0_usart.c:936
USART_CTL1_CPL
#define USART_CTL1_CPL
Definition: gd32f3x0_usart.h:64
usart_receiver_timeout_config
void usart_receiver_timeout_config(uint32_t usart_periph, uint32_t rtimeout)
receiver timeout threshold configure
Definition: gd32f3x0_usart.c:468
USART_BAUD
#define USART_BAUD(usartx)
Definition: gd32f3x0_usart.h:25
USART_BAUD_INTDIV
#define USART_BAUD_INTDIV
Definition: gd32f3x0_usart.h:101
usart_overrun_enable
void usart_overrun_enable(uint32_t usart_periph)
overrun function is enabled
Definition: gd32f3x0_usart.c:271
usart_address_config
void usart_address_config(uint32_t usart_periph, uint8_t addr)
address of the USART terminal
Definition: gd32f3x0_usart.c:430
usart_receiver_timeout_disable
void usart_receiver_timeout_disable(uint32_t usart_periph)
receiver timeout disable
Definition: gd32f3x0_usart.c:456
usart_synchronous_clock_config
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
configure USART synchronous mode parameters
Definition: gd32f3x0_usart.c:590
USART_CTL2_DENT
#define USART_CTL2_DENT
Definition: gd32f3x0_usart.h:86
USART_RFCS_RFEN
#define USART_RFCS_RFEN
Definition: gd32f3x0_usart.h:164
usart_dma_transmit_config
void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
configure USART DMA transmission
Definition: gd32f3x0_usart.c:923
usart_invert_config
void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara)
USART inverted configure.
Definition: gd32f3x0_usart.c:231
USART_BAUD_FRADIV
#define USART_BAUD_FRADIV
Definition: gd32f3x0_usart.h:100
USART_TDATA
#define USART_TDATA(usartx)
Definition: gd32f3x0_usart.h:32
usart_overrun_disable
void usart_overrun_disable(uint32_t usart_periph)
overrun function is disabled
Definition: gd32f3x0_usart.c:284
USART_CTL2_DDRE
#define USART_CTL2_DDRE
Definition: gd32f3x0_usart.h:92
usart_reception_error_dma_enable
void usart_reception_error_dma_enable(uint32_t usart_periph)
enable DMA on reception error
Definition: gd32f3x0_usart.c:950
usart_data_receive
uint16_t usart_data_receive(uint32_t usart_periph)
USART receive data function.
Definition: gd32f3x0_usart.c:202
usart_word_length_set
void usart_word_length_set(uint32_t usart_periph, uint32_t wlen)
configure USART word length
Definition: gd32f3x0_usart.c:100
USART_RXPIN_DISABLE
Definition: gd32f3x0_usart.h:277
usart_mute_mode_wakeup_config
void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod)
wakeup method in mute mode configure
Definition: gd32f3x0_usart.c:396
usart_receive_fifo_disable
void usart_receive_fifo_disable(uint32_t usart_periph)
receive FIFO disable
Definition: gd32f3x0_usart.c:1016
usart_guard_time_config
void usart_guard_time_config(uint32_t usart_periph, uint32_t guat)
guard time value configure in smartcard mode
Definition: gd32f3x0_usart.c:665
usart_enable
void usart_enable(uint32_t usart_periph)
enable USART
Definition: gd32f3x0_usart.c:136
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f3x0_rcu.c:964
usart_parity_config
void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg)
configure USART parity
Definition: gd32f3x0_usart.c:81
USART_CTL2_HDEN
#define USART_CTL2_HDEN
Definition: gd32f3x0_usart.h:82
USART_CTL2
#define USART_CTL2(usartx)
Definition: gd32f3x0_usart.h:24
USART_CTL0_UESM
#define USART_CTL0_UESM
Definition: gd32f3x0_usart.h:38
usart_receive_fifo_counter_number
uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph)
read receive FIFO counter number
Definition: gd32f3x0_usart.c:1027
usart_prescaler_config
void usart_prescaler_config(uint32_t usart_periph, uint32_t psc)
configure the peripheral clock prescaler in USART IrDA low-power mode
Definition: gd32f3x0_usart.c:776
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_ctrl.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
usbh_ctrl.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef USBH_CTRL_H
13 #define USBH_CTRL_H
14
15 #include "usbh_core.h"
16 #include "usbh_usr.h"
17
18 #define CTRL_HANDLE_TABLE_SIZE 13U
20 extern state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE];
21 extern uint8_t ctrl_polling_handle_flag;
22
23 /* the enum of CTRL event */
24 typedef enum
25 {
26 CTRL_EVENT_IDLE = 0, /* the ctrl idle event */
27 CTRL_EVENT_SETUP, /* the ctrl setup event */
28 CTRL_EVENT_DATA, /* the ctrl data event */
29 CTRL_EVENT_STATUS, /* the ctrl status event */
30 CTRL_EVENT_COMPLETE, /* the ctrl complete event */
31 CTRL_EVENT_ERROR, /* the ctrl error event */
32 CTRL_EVENT_STALLED, /* the ctrl stalled event */
33 }ctrl_event_enum;
34
35 /* function declarations */
36 /* the polling function of control transfer state handle */
37 usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
38 /* send datas from the host channel */
39 usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len);
40 /* send the setup packet to the device */
41 usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num);
42 /* this function prepare a hc and start a transfer */
43 uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num);
44
45 #endif /* USBH_CTRL_H */
usbh_core.h
header file for usbh_core.c
ctrl_state_polling_fun
usbh_status_enum ctrl_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of CTRL state
Definition: usbh_ctrl.c:72
CTRL_EVENT_ERROR
Definition: usbh_ctrl.h:31
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:106
usbh_host_struct
Definition: usbh_core.h:188
CTRL_EVENT_SETUP
Definition: usbh_ctrl.h:27
hcd_submit_request
uint32_t hcd_submit_request(usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer
Definition: usbh_ctrl.c:604
CTRL_EVENT_DATA
Definition: usbh_ctrl.h:28
usbh_ctltx_setup
usbh_status_enum usbh_ctltx_setup(usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num)
send the setup packet to the device
Definition: usbh_ctrl.c:586
usbh_xfer
usbh_status_enum usbh_xfer(usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len)
send datas from the host channel
Definition: usbh_ctrl.c:493
ctrl_event_enum
ctrl_event_enum
Definition: usbh_ctrl.h:24
ctrl_polling_handle_flag
uint8_t ctrl_polling_handle_flag
Definition: usbh_ctrl.c:16
usb_core_handle_struct
Definition: usb_core.h:200
CTRL_EVENT_STALLED
Definition: usbh_ctrl.h:32
CTRL_EVENT_COMPLETE
Definition: usbh_ctrl.h:30
CTRL_EVENT_IDLE
Definition: usbh_ctrl.h:26
CTRL_EVENT_STATUS
Definition: usbh_ctrl.h:29
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_fmc.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_fmc.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_fmc.h"
13
14 /* FMC main memory programming functions */
15
23 void fmc_unlock(void)
24 {
25 if((RESET != (FMC_CTL & FMC_CTL_LK))){
26 /* write the FMC key */
27 FMC_KEY = UNLOCK_KEY0;
28 FMC_KEY = UNLOCK_KEY1;
29 }
30 }
31
39 void fmc_lock(void)
40 {
41 /* set the LK bit*/
42 FMC_CTL |= FMC_CTL_LK;
43 }
44
54 void fmc_wscnt_set(uint8_t wscnt)
55 {
56 uint32_t reg;
57
58 reg = FMC_WS;
59 /* set the wait state counter value */
60 reg &= ~FMC_WS_WSCNT;
61 FMC_WS = (reg | wscnt);
62 }
63
70 void fmc_wait_state_enable(void)
71 {
72 /* unlock the main flash */
73 fmc_unlock();
74
75 /* set the WSEN bit in register FMC_WSEN */
76 FMC_WSEN |= FMC_WSEN_WSEN;
77
78 /* lock the main flash after operation */
79 fmc_lock();
80 }
81
88 void fmc_wait_state_disable(void)
89 {
90 /* unlock the main flash */
91 fmc_unlock();
92
93 /* reset the WSEN bit in register FMC_WSEN */
94 FMC_WSEN &= ~FMC_WSEN_WSEN;
95
96 /* lock the main flash after operation */
97 fmc_lock();
98 }
99
106 fmc_state_enum fmc_page_erase(uint32_t page_address)
107 {
108 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
109
110 if(FMC_READY == fmc_state){
111 /* start page erase */
112 FMC_CTL |= FMC_CTL_PER;
113 FMC_ADDR = page_address;
114 FMC_CTL |= FMC_CTL_START;
115
116 /* wait for the FMC ready */
117 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
118
119 /* reset the PER bit */
120 FMC_CTL &= ~FMC_CTL_PER;
121 }
122
123 /* return the FMC state */
124 return fmc_state;
125 }
126
133 fmc_state_enum fmc_mass_erase(void)
134 {
135 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
136
137 if(FMC_READY == fmc_state){
138 /* start chip erase */
139 FMC_CTL |= FMC_CTL_MER;
140 FMC_CTL |= FMC_CTL_START;
141
142 /* wait for the FMC ready */
143 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
144
145 /* reset the MER bit */
146 FMC_CTL &= ~FMC_CTL_MER;
147 }
148
149 /* return the fmc state */
150 return fmc_state;
151 }
152
160 fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
161 {
162 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
163
164 if(FMC_READY == fmc_state){
165 /* set the PG bit to start program */
166 FMC_CTL |= FMC_CTL_PG;
167
168 REG32(address) = data;
169
170 /* wait for the FMC ready */
171 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
172
173 /* reset the PG bit */
174 FMC_CTL &= ~FMC_CTL_PG;
175 }
176
177 /* return the FMC state */
178 return fmc_state;
179 }
180
188 fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
189 {
190 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
191
192 if(FMC_READY == fmc_state){
193 /* set the PG bit to start program */
194 FMC_CTL |= FMC_CTL_PG;
195
196 REG16(address) = data;
197
198 /* wait for the FMC ready */
199 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
200
201 /* reset the PG bit */
202 FMC_CTL &= ~FMC_CTL_PG;
203 }
204
205 /* return the FMC state */
206 return fmc_state;
207 }
208
216 fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data)
217 {
218 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
219 FMC_WSEN |= FMC_WSEN_BPEN;
220
221 if(FMC_READY == fmc_state){
222 /* set the PG bit to start program */
223 FMC_CTL |= FMC_CTL_PG;
224
225 REG32(address) = data;
226
227 /* wait for the FMC ready */
228 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
229
230 /* reset the PG bit */
231 FMC_CTL &= ~FMC_CTL_PG;
232 }
233
234 /* return the FMC state */
235 return fmc_state;
236 }
237
238 /* FMC option bytes programming functions */
239
247 void ob_unlock(void)
248 {
249 if(RESET == (FMC_CTL & FMC_CTL_OBWEN)){
250 /* write the FMC key */
251 FMC_OBKEY = UNLOCK_KEY0;
252 FMC_OBKEY = UNLOCK_KEY1;
253 }
254 }
255
263 void ob_lock(void)
264 {
265 /* reset the OBWE bit */
266 FMC_CTL &= ~FMC_CTL_OBWEN;
267 }
268
275 void ob_reset(void)
276 {
277 /* set the OBRLD bit */
278 FMC_CTL |= FMC_CTL_OBRLD;
279 }
280
288 fmc_state_enum ob_erase(void)
289 {
290 uint16_t fmc_spc;
291 uint32_t fmc_plevel = ob_obstat_plevel_get();
292 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
293
294 /* get the original option byte security protection code */
295 if(OB_OBSTAT_PLEVEL_NO == fmc_plevel){
296 fmc_spc = FMC_NSPC;
297 }else if(OB_OBSTAT_PLEVEL_LOW == fmc_plevel){
298 fmc_spc = FMC_LSPC;
299 }else{
300 fmc_spc = FMC_HSPC;
301 fmc_state = FMC_OB_HSPC;
302 }
303
304 if(FMC_READY == fmc_state){
305 /* start erase the option byte */
306 FMC_CTL |= FMC_CTL_OBER;
307 FMC_CTL |= FMC_CTL_START;
308
309 /* wait for the FMC ready */
310 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
311
312 if(FMC_READY == fmc_state){
313 /* reset the OBER bit */
314 FMC_CTL &= ~FMC_CTL_OBER;
315
316 /* set the OBPG bit */
317 FMC_CTL |= FMC_CTL_OBPG;
318
319 /* restore the last get option byte security protection code */
320 OB_SPC = fmc_spc;
321
322 /* wait for the FMC ready */
323 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
324
325 if(FMC_TOERR != fmc_state){
326 /* reset the OBPG bit */
327 FMC_CTL &= ~FMC_CTL_OBPG;
328 }
329 }else{
330 if(FMC_TOERR != fmc_state){
331 /* reset the OBPG bit */
332 FMC_CTL &= ~FMC_CTL_OBPG;
333 }
334 }
335 }
336 /* return the FMC state */
337 return fmc_state;
338 }
339
346 fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
347 {
348 uint16_t ob_wrp0, ob_wrp1;
349
350 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
351
352 ob_wp = (uint32_t)(~ob_wp);
353 ob_wrp0 = (uint16_t)(ob_wp & OB_LWP);
354 ob_wrp1 = (uint16_t)((ob_wp & OB_HWP) >> 8);
355
356 if(FMC_READY == fmc_state){
357 /* set the OBPG bit*/
358 FMC_CTL |= FMC_CTL_OBPG;
359
360 if(0xFFU != ob_wrp0){
361 OB_WP0 = ob_wrp0;
362
363 /* wait for the FMC ready */
364 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
365 }
366 if((FMC_READY == fmc_state) && (0xFFU != ob_wrp1)){
367 OB_WP1 = ob_wrp1;
368
369 /* wait for the FMC ready */
370 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
371 }
372 if(FMC_TOERR != fmc_state){
373 /* reset the OBPG bit */
374 FMC_CTL &= ~FMC_CTL_OBPG;
375 }
376 }
377 /* return the FMC state */
378 return fmc_state;
379 }
380
390 fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
391 {
392 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
393
394 /* the OB_SPC byte cannot be reprogrammed if protection level is high */
395 if(OB_OBSTAT_PLEVEL_HIGH == ob_obstat_plevel_get()){
396 fmc_state = FMC_OB_HSPC;
397 }
398
399 if(FMC_READY == fmc_state){
400 /* start erase the option byte */
401 FMC_CTL |= FMC_CTL_OBER;
402 FMC_CTL |= FMC_CTL_START;
403
404 /* wait for the FMC ready */
405 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
406
407 if(FMC_READY == fmc_state){
408
409 /* reset the OBER bit */
410 FMC_CTL &= ~FMC_CTL_OBER;
411
412 /* enable the option bytes programming */
413 FMC_CTL |= FMC_CTL_OBPG;
414
415 OB_SPC = ob_spc;
416
417 /* wait for the FMC ready */
418 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
419
420 if(FMC_TOERR != fmc_state){
421 /* reset the OBPG bit */
422 FMC_CTL &= ~FMC_CTL_OBPG;
423 }
424 }else{
425 if(FMC_TOERR != fmc_state){
426 /* reset the OBER bit */
427 FMC_CTL &= ~FMC_CTL_OBER;
428 }
429 }
430 }
431 /* return the FMC state */
432 return fmc_state;
433 }
434
453 fmc_state_enum ob_user_write(uint8_t ob_user)
454 {
455 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
456
457 if(FMC_READY == fmc_state){
458 /* set the OBPG bit */
459 FMC_CTL |= FMC_CTL_OBPG;
460
461 OB_USER = (uint8_t)(ob_user | OB_USER_MASK);
462
463 /* wait for the FMC ready */
464 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
465
466 if(FMC_TOERR != fmc_state){
467 /* reset the OBPG bit */
468 FMC_CTL &= ~FMC_CTL_OBPG;
469 }
470 }
471 /* return the FMC state */
472 return fmc_state;
473 }
474
484 fmc_state_enum ob_data_program(uint32_t address, uint8_t data)
485 {
486 fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
487
488 if(FMC_READY == fmc_state){
489 /* set the OBPG bit */
490 FMC_CTL |= FMC_CTL_OBPG;
491 REG16(address) = data;
492
493 /* wait for the FMC ready */
494 fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
495
496 if(FMC_TOERR != fmc_state){
497 /* reset the OBPG bit */
498 FMC_CTL &= ~FMC_CTL_OBPG;
499 }
500 }
501 /* return the FMC state */
502 return fmc_state;
503 }
504
511 uint8_t ob_user_get(void)
512 {
513 return (uint8_t)(FMC_OBSTAT >> 8);
514 }
515
522 uint16_t ob_data_get(void)
523 {
524 return (uint16_t)(FMC_OBSTAT >> 16);
525 }
526
533 uint16_t ob_write_protection_get(void)
534 {
535 return (uint16_t)(FMC_WP);
536 }
537
544 uint32_t ob_obstat_plevel_get(void)
545 {
546 return (FMC_OBSTAT & (FMC_OBSTAT_PLVL_BIT0 | FMC_OBSTAT_PLVL_BIT1));
547 }
548
549 /* FMC interrupts and flags management functions */
558 void fmc_interrupt_enable(uint32_t interrupt)
559 {
560 FMC_CTL |= interrupt;
561 }
562
571 void fmc_interrupt_disable(uint32_t interrupt)
572 {
573 FMC_CTL &= ~(uint32_t)interrupt;
574 }
575
586 FlagStatus fmc_flag_get(uint32_t flag)
587 {
588 FlagStatus status = RESET;
589
590 if(FMC_STAT & flag){
591 status = SET;
592 }
593 /* return the state of corresponding FMC flag */
594 return status;
595 }
596
606 void fmc_flag_clear(uint32_t flag)
607 {
608 /* clear the flags */
609 FMC_STAT = flag;
610 }
611
618 fmc_state_enum fmc_state_get(void)
619 {
620 fmc_state_enum fmc_state = FMC_READY;
621
622 if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)){
623 fmc_state = FMC_BUSY;
624 }else{
625 if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)){
626 fmc_state = FMC_WPERR;
627 }else{
628 if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGERR)){
629 fmc_state = FMC_PGERR;
630 }
631 }
632 }
633 /* return the FMC state */
634 return fmc_state;
635 }
636
643 fmc_state_enum fmc_ready_wait(uint32_t timeout)
644 {
645 fmc_state_enum fmc_state = FMC_BUSY;
646
647 /* wait for FMC ready */
648 do{
649 /* get FMC state */
650 fmc_state = fmc_state_get();
651 timeout--;
652 }while((FMC_BUSY == fmc_state) && (0U != timeout));
653
654 if(FMC_BUSY == fmc_state){
655 fmc_state = FMC_TOERR;
656 }
657 /* return the FMC state */
658 return fmc_state;
659 }
OB_USER_MASK
#define OB_USER_MASK
Definition: gd32f3x0_fmc.h:150
fmc_page_erase
fmc_state_enum fmc_page_erase(uint32_t page_address)
erase page
Definition: gd32f3x0_fmc.c:106
fmc_halfword_program
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
program a half word at the corresponding address
Definition: gd32f3x0_fmc.c:188
FMC_CTL_START
#define FMC_CTL_START
Definition: gd32f3x0_fmc.h:60
OB_LWP
#define OB_LWP
Definition: gd32f3x0_fmc.h:111
fmc_wait_state_enable
void fmc_wait_state_enable(void)
fmc wait state enable
Definition: gd32f3x0_fmc.c:70
fmc_lock
void fmc_lock(void)
lock the main FMC operation it is better to used in pairs with fmc_unlock after an operation ...
Definition: gd32f3x0_fmc.c:39
FMC_CTL_OBWEN
#define FMC_CTL_OBWEN
Definition: gd32f3x0_fmc.h:62
fmc_flag_get
FlagStatus fmc_flag_get(uint32_t flag)
get flag set or reset
Definition: gd32f3x0_fmc.c:586
ob_lock
void ob_lock(void)
lock the option byte operation it is better to used in pairs with ob_unlock after an operation ...
Definition: gd32f3x0_fmc.c:263
ob_security_protection_config
fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
configure security protection
Definition: gd32f3x0_fmc.c:390
FMC_OBKEY
#define FMC_OBKEY
Definition: gd32f3x0_fmc.h:24
FMC_WSEN
#define FMC_WSEN
Definition: gd32f3x0_fmc.h:30
fmc_unlock
void fmc_unlock(void)
unlock the main FMC operation it is better to used in pairs with fmc_lock
Definition: gd32f3x0_fmc.c:23
OB_OBSTAT_PLEVEL_NO
#define OB_OBSTAT_PLEVEL_NO
Definition: gd32f3x0_fmc.h:145
UNLOCK_KEY1
#define UNLOCK_KEY1
Definition: gd32f3x0_fmc.h:98
ob_erase
fmc_state_enum ob_erase(void)
erase the option byte programmer must ensure FMC & option byte are both unlocked before calling this ...
Definition: gd32f3x0_fmc.c:288
FMC_WS_WSCNT
#define FMC_WS_WSCNT
Definition: gd32f3x0_fmc.h:40
FMC_WS
#define FMC_WS
Definition: gd32f3x0_fmc.h:22
fmc_ready_wait
fmc_state_enum fmc_ready_wait(uint32_t timeout)
check whether FMC is ready or not
Definition: gd32f3x0_fmc.c:643
FMC_READY
Definition: gd32f3x0_fmc.h:88
fmc_state_get
fmc_state_enum fmc_state_get(void)
get the FMC state
Definition: gd32f3x0_fmc.c:618
ob_write_protection_get
uint16_t ob_write_protection_get(void)
get the FMC option byte write protection (OB_WP) in register FMC_WP
Definition: gd32f3x0_fmc.c:533
FMC_OBSTAT_PLVL_BIT1
#define FMC_OBSTAT_PLVL_BIT1
Definition: gd32f3x0_fmc.h:73
FMC_STAT
#define FMC_STAT
Definition: gd32f3x0_fmc.h:25
OB_HWP
#define OB_HWP
Definition: gd32f3x0_fmc.h:112
FMC_LSPC
#define FMC_LSPC
Definition: gd32f3x0_fmc.h:107
ob_user_get
uint8_t ob_user_get(void)
get OB_USER in register FMC_OBSTAT
Definition: gd32f3x0_fmc.c:511
FMC_CTL_OBRLD
#define FMC_CTL_OBRLD
Definition: gd32f3x0_fmc.h:65
OB_SPC
#define OB_SPC
Definition: gd32f3x0_fmc.h:33
OB_WP0
#define OB_WP0
Definition: gd32f3x0_fmc.h:35
FMC_OB_HSPC
Definition: gd32f3x0_fmc.h:93
FMC_TOERR
Definition: gd32f3x0_fmc.h:92
OB_OBSTAT_PLEVEL_HIGH
#define OB_OBSTAT_PLEVEL_HIGH
Definition: gd32f3x0_fmc.h:147
ob_data_program
fmc_state_enum ob_data_program(uint32_t address, uint8_t data)
program the FMC data option byte
Definition: gd32f3x0_fmc.c:484
UNLOCK_KEY0
#define UNLOCK_KEY0
Definition: gd32f3x0_fmc.h:97
ob_user_write
fmc_state_enum ob_user_write(uint8_t ob_user)
program the FMC user option byte
Definition: gd32f3x0_fmc.c:453
ob_unlock
void ob_unlock(void)
unlock the option byte operation it is better to used in pairs with ob_lock
Definition: gd32f3x0_fmc.c:247
FMC_STAT_PGERR
#define FMC_STAT_PGERR
Definition: gd32f3x0_fmc.h:50
fmc_flag_clear
void fmc_flag_clear(uint32_t flag)
clear the FMC pending flag by writing 1
Definition: gd32f3x0_fmc.c:606
fmc_wait_state_disable
void fmc_wait_state_disable(void)
fmc wait state disable
Definition: gd32f3x0_fmc.c:88
fmc_interrupt_enable
void fmc_interrupt_enable(uint32_t interrupt)
enable FMC interrupt
Definition: gd32f3x0_fmc.c:558
FMC_KEY
#define FMC_KEY
Definition: gd32f3x0_fmc.h:23
OB_OBSTAT_PLEVEL_LOW
#define OB_OBSTAT_PLEVEL_LOW
Definition: gd32f3x0_fmc.h:146
FMC_OBSTAT
#define FMC_OBSTAT
Definition: gd32f3x0_fmc.h:28
fmc_mass_erase
fmc_state_enum fmc_mass_erase(void)
erase whole chip
Definition: gd32f3x0_fmc.c:133
FMC_OBSTAT_PLVL_BIT0
#define FMC_OBSTAT_PLVL_BIT0
Definition: gd32f3x0_fmc.h:72
FMC_CTL_LK
#define FMC_CTL_LK
Definition: gd32f3x0_fmc.h:61
FMC_PGERR
Definition: gd32f3x0_fmc.h:90
FMC_WSEN_BPEN
#define FMC_WSEN_BPEN
Definition: gd32f3x0_fmc.h:79
FMC_CTL_OBPG
#define FMC_CTL_OBPG
Definition: gd32f3x0_fmc.h:58
ob_write_protection_enable
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
enable option byte write protection (OB_WP)
Definition: gd32f3x0_fmc.c:346
fmc_wscnt_set
void fmc_wscnt_set(uint8_t wscnt)
set the wait state counter value
Definition: gd32f3x0_fmc.c:54
OB_USER
#define OB_USER
Definition: gd32f3x0_fmc.h:34
fmc_word_reprogram
fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data)
program a word at the corresponding address without erasing
Definition: gd32f3x0_fmc.c:216
FMC_WP
#define FMC_WP
Definition: gd32f3x0_fmc.h:29
gd32f3x0_fmc.h
definitions for the FMC
ob_obstat_plevel_get
uint32_t ob_obstat_plevel_get(void)
get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register ...
Definition: gd32f3x0_fmc.c:544
FMC_STAT_WPERR
#define FMC_STAT_WPERR
Definition: gd32f3x0_fmc.h:51
FMC_TIMEOUT_COUNT
#define FMC_TIMEOUT_COUNT
Definition: gd32f3x0_fmc.h:167
fmc_word_program
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
program a word at the corresponding address
Definition: gd32f3x0_fmc.c:160
FMC_WSEN_WSEN
#define FMC_WSEN_WSEN
Definition: gd32f3x0_fmc.h:78
fmc_interrupt_disable
void fmc_interrupt_disable(uint32_t interrupt)
disable FMC interrupt
Definition: gd32f3x0_fmc.c:571
FMC_CTL_PG
#define FMC_CTL_PG
Definition: gd32f3x0_fmc.h:55
FMC_ADDR
#define FMC_ADDR
Definition: gd32f3x0_fmc.h:27
ob_reset
void ob_reset(void)
reload the option byte and generate a system reset
Definition: gd32f3x0_fmc.c:275
FMC_STAT_BUSY
#define FMC_STAT_BUSY
Definition: gd32f3x0_fmc.h:49
FMC_CTL_MER
#define FMC_CTL_MER
Definition: gd32f3x0_fmc.h:57
FMC_WPERR
Definition: gd32f3x0_fmc.h:91
FMC_CTL
#define FMC_CTL
Definition: gd32f3x0_fmc.h:26
FMC_HSPC
#define FMC_HSPC
Definition: gd32f3x0_fmc.h:108
FMC_NSPC
#define FMC_NSPC
Definition: gd32f3x0_fmc.h:106
ob_data_get
uint16_t ob_data_get(void)
get OB_DATA in register FMC_OBSTAT
Definition: gd32f3x0_fmc.c:522
FMC_CTL_OBER
#define FMC_CTL_OBER
Definition: gd32f3x0_fmc.h:59
fmc_state_enum
fmc_state_enum
Definition: gd32f3x0_fmc.h:86
FMC_CTL_PER
#define FMC_CTL_PER
Definition: gd32f3x0_fmc.h:56
OB_WP1
#define OB_WP1
Definition: gd32f3x0_fmc.h:36
FMC_BUSY
Definition: gd32f3x0_fmc.h:89
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbd_core.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
usbd_core.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef USBD_CORE_H
13 #define USBD_CORE_H
14
15 #include "usbd_conf.h"
16 #include "usb_core.h"
17 #include "usbd_std.h"
18
19 /* device status */
20 #define USB_STATUS_DEFAULT 1U /* default status */
21 #define USB_STATUS_ADDRESSED 2U /* addressed status */
22 #define USB_STATUS_CONFIGURED 3U /* configured status */
23 #define USB_STATUS_SUSPENDED 4U /* suspended status */
24
25 /* function declarations */
26 /* initailizes the USB device-mode handler stack */
27 void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id);
28 /* endpoint initialization */
29 void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc);
30 /* endpoint deinitialize */
31 void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr);
32 /* endpoint prepare to receive data */
33 void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len);
34 /* endpoint prepare to transmit data */
35 void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len);
36 /* transmit data on the control channel */
37 usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len);
38 /* receive data on the control channel */
39 usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len);
40 /* transmit status on the control channel */
41 usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev);
42 /* receive status on the control channel */
43 usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev);
44 /* set an endpoint to STALL status */
45 void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr);
46 /* clear endpoint stalled status */
47 void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr);
48 /* flushes the FIFOs */
49 void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr);
50 /* get the received data length */
51 uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num);
52
53 #endif /* USBD_CORE_H */
usbd_std.h
USB 2.0 standard defines.
usbd_ctltx
usbd_status_enum usbd_ctltx(usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
transmit data on the control channel
Definition: usbd_core.c:312
usbd_ctlstatus_rx
usbd_status_enum usbd_ctlstatus_rx(usb_core_handle_struct *pudev)
receive status on the control channel
Definition: usbd_core.c:367
usbd_init
void usbd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initailizes the USB device-mode handler stack
Definition: usbd_core.c:22
usbd_ep_tx
void usbd_ep_tx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:230
usbd_ctlrx
usbd_status_enum usbd_ctlrx(usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
receive data on the control channel
Definition: usbd_core.c:333
usbd_ep_fifo_flush
void usbd_ep_fifo_flush(usb_core_handle_struct *pudev, uint8_t ep_addr)
flushes the FIFOs
Definition: usbd_core.c:457
usbd_rxcount_get
uint16_t usbd_rxcount_get(usb_core_handle_struct *pudev, uint8_t ep_num)
get the received data length
Definition: usbd_core.c:473
usbd_ep_stall
void usbd_ep_stall(usb_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:385
usbd_ep_rx
void usbd_ep_rx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:161
usbd_ctlstatus_tx
usbd_status_enum usbd_ctlstatus_tx(usb_core_handle_struct *pudev)
transmit status on the control channel
Definition: usbd_core.c:350
usb_descriptor_endpoint_struct
Definition: usb_std.h:170
usbd_ep_init
void usbd_ep_init(usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc)
endpoint initialization
Definition: usbd_core.c:66
usb_core.h
USB core driver header file.
usbd_status_enum
usbd_status_enum
Definition: usb_core.h:72
usbd_ep_clear_stall
void usbd_ep_clear_stall(usb_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status
Definition: usbd_core.c:415
usb_core_handle_struct
Definition: usb_core.h:200
usbd_ep_deinit
void usbd_ep_deinit(usb_core_handle_struct *pudev, uint8_t ep_addr)
endpoint deinitialize
Definition: usbd_core.c:133
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:86
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbh_hcs.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
usbh_hcs.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "usbh_hcs.h"
13
14 static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev);
15
27 uint8_t usbh_channel_open (usb_core_handle_struct *pudev,
28 uint8_t channel_num,
29 uint8_t dev_addr,
30 uint8_t dev_speed,
31 uint8_t ep_type,
32 uint16_t ep_mps)
33 {
34 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
35 uint16_t channel_info = puhc->info;
36
37 puhc->endp_id = (uint8_t)channel_info & 0x7FU;
38 puhc->endp_in = (uint8_t)(channel_info & 0x80U) >> 7;
39 puhc->endp_type = ep_type;
40 puhc->endp_mps = ep_mps;
41 puhc->dev_addr = dev_addr;
42 puhc->dev_speed = dev_speed;
43
44 puhc->data_tg_in = 0U;
45 puhc->data_tg_out = 0U;
46
47 usb_hostchannel_init(pudev, channel_num);
48
49 return (uint8_t)HC_OK;
50 }
51
63 uint8_t usbh_channel_modify (usb_core_handle_struct *pudev,
64 uint8_t channel_num,
65 uint8_t dev_addr,
66 uint8_t dev_speed,
67 uint8_t ep_type,
68 uint16_t ep_mps)
69 {
70 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
71
72 if (0U != dev_addr) {
73 puhc->dev_addr = dev_addr;
74 }
75
76 if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) {
77 puhc->endp_mps = ep_mps;
78 }
79
80 if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) {
81 puhc->dev_speed = dev_speed;
82 }
83
84 usb_hostchannel_init(pudev, channel_num);
85
86 return (uint8_t)HC_OK;
87 }
88
96 uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr)
97 {
98 uint16_t hc_num = usbh_freechannel_get(pudev);
99
100 if ((uint16_t)HC_ERROR != hc_num) {
101 pudev->host.host_channel[hc_num].info = HC_USED | ep_addr;
102 }
103
104 return (uint8_t)hc_num;
105 }
106
114 uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index)
115 {
116 if (index < HC_MAX) {
117 pudev->host.host_channel[index].info &= HC_USED_MASK;
118 }
119
120 return USBH_OK;
121 }
122
129 uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev)
130 {
131 uint8_t index;
132
133 for (index = 2U; index < HC_MAX; index ++) {
134 pudev->host.host_channel[index].info = 0U;
135 }
136
137 return USBH_OK;
138 }
139
146 static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev)
147 {
148 uint8_t index = 0U;
149
150 for (index = 0U; index < HC_MAX; index++) {
151 if (0U == (pudev->host.host_channel[index].info & HC_USED)) {
152 return (uint16_t)index;
153 }
154 }
155
156 return HC_ERROR;
157 }
158
HC_USED
#define HC_USED
Definition: usbh_hcs.h:20
usb_hostchannel_struct::info
uint16_t info
Definition: usb_core.h:163
usbh_channel_modify
uint8_t usbh_channel_modify(usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
modify a channel
Definition: usbh_hcs.c:63
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:175
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:160
HC_MAX
#define HC_MAX
Definition: usbh_hcs.h:17
usbh_channel_free
uint8_t usbh_channel_free(usb_core_handle_struct *pudev, uint8_t index)
free the usb host channel
Definition: usbh_hcs.c:114
usb_hostchannel_struct
Definition: usb_core.h:154
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:174
usbh_channel_open
uint8_t usbh_channel_open(usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
open a channel
Definition: usbh_hcs.c:27
usb_hostchannel_struct::endp_mps
uint16_t endp_mps
Definition: usb_core.h:162
usb_hostchannel_struct::dev_addr
uint8_t dev_addr
Definition: usb_core.h:156
usbh_hcs.h
header file for usbh_hcs.c
usb_core_handle_struct
Definition: usb_core.h:200
usb_hostchannel_struct::dev_speed
uint8_t dev_speed
Definition: usb_core.h:157
HC_ERROR
#define HC_ERROR
Definition: usbh_hcs.h:21
usbh_channel_alloc
uint8_t usbh_channel_alloc(usb_core_handle_struct *pudev, uint8_t ep_addr)
allocate a new channel for the pipe
Definition: usbh_hcs.c:96
HC_USED_MASK
#define HC_USED_MASK
Definition: usbh_hcs.h:22
USBH_OK
Definition: usbh_core.h:108
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:161
HC_OK
#define HC_OK
Definition: usbh_hcs.h:19
usbh_allchannel_dealloc
uint8_t usbh_allchannel_dealloc(usb_core_handle_struct *pudev)
free all usb host channel
Definition: usbh_hcs.c:129
usb_hostchannel_struct::endp_id
uint8_t endp_id
Definition: usb_core.h:159
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_dbg.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_dbg.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_dbg.h"
13
14 #define DBG_RESET_VAL 0x00000000U
15
22 void dbg_deinit(void)
23 {
24 DBG_CTL0 = DBG_RESET_VAL;
25 DBG_CTL1 = DBG_RESET_VAL;
26 }
27
34 uint32_t dbg_id_get(void)
35 {
36 return DBG_ID;
37 }
38
49 void dbg_low_power_enable(uint32_t dbg_low_power)
50 {
51 DBG_CTL0 |= dbg_low_power;
52 }
53
64 void dbg_low_power_disable(uint32_t dbg_low_power)
65 {
66 DBG_CTL0 &= ~dbg_low_power;
67 }
68
93 void dbg_periph_enable(dbg_periph_enum dbg_periph)
94 {
95 DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
96 }
97
122 void dbg_periph_disable(dbg_periph_enum dbg_periph)
123 {
124 DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
125 }
dbg_periph_enum
dbg_periph_enum
Definition: gd32f3x0_dbg.h:70
dbg_periph_disable
void dbg_periph_disable(dbg_periph_enum dbg_periph)
disable peripheral behavior when the mcu is in debug mode
Definition: gd32f3x0_dbg.c:122
dbg_id_get
uint32_t dbg_id_get(void)
read DBG_ID code register
Definition: gd32f3x0_dbg.c:34
DBG_RESET_VAL
#define DBG_RESET_VAL
Definition: gd32f3x0_dbg.c:14
dbg_periph_enable
void dbg_periph_enable(dbg_periph_enum dbg_periph)
enable peripheral behavior when the mcu is in debug mode
Definition: gd32f3x0_dbg.c:93
dbg_deinit
void dbg_deinit(void)
deinitialize the DBG
Definition: gd32f3x0_dbg.c:22
dbg_low_power_disable
void dbg_low_power_disable(uint32_t dbg_low_power)
disable low power behavior when the mcu is in debug mode
Definition: gd32f3x0_dbg.c:64
DBG_ID
#define DBG_ID
Definition: gd32f3x0_dbg.h:21
DBG_REG_VAL
#define DBG_REG_VAL(periph)
Definition: gd32f3x0_dbg.h:59
DBG_BIT_POS
#define DBG_BIT_POS(val)
Definition: gd32f3x0_dbg.h:60
dbg_low_power_enable
void dbg_low_power_enable(uint32_t dbg_low_power)
enable low power behavior when the mcu is in debug mode
Definition: gd32f3x0_dbg.c:49
gd32f3x0_dbg.h
definitions for the DBG
DBG_CTL1
#define DBG_CTL1
Definition: gd32f3x0_dbg.h:23
DBG_CTL0
#define DBG_CTL0
Definition: gd32f3x0_dbg.h:22
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbd_int.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
usbd_int.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "usbd_int.h"
13 #include "usbd_std.h"
14
15 /* interrupt handlers */
16 static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev);
17 static uint32_t usbd_intf_inep (usb_core_handle_struct *pudev);
18 static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev);
19 static uint32_t usbd_intf_suspend (usb_core_handle_struct *pudev);
20 static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev);
21 static uint32_t usbd_intf_sof (usb_core_handle_struct *pudev);
22 static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev);
23 static uint32_t usbd_intf_reset (usb_core_handle_struct *pudev);
24 static uint32_t usbd_intf_enumfinish (usb_core_handle_struct *pudev);
25 static uint32_t usbd_intf_isoinincomplete (usb_core_handle_struct *pudev);
26 static uint32_t usbd_intf_isooutincomplete (usb_core_handle_struct *pudev);
27
28 static uint32_t usbd_emptytxfifo_write (usb_core_handle_struct *pudev, uint8_t ep_num);
29
30 #ifdef VBUS_SENSING_ENABLED
31
32 static uint32_t usbd_intf_otg (usb_core_handle_struct *pudev);
33 static uint32_t usbd_intf_sessionrequest (usb_core_handle_struct *pudev);
34
35 #endif /* VBUS_SENSING_ENABLED */
36
37 static usb_speed_enum USB_SPEED[4] = {
38 [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_HIGH,
39 [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_FULL,
40 [DSTAT_ENUMSPD_FS_PHY_48MHZ] = USB_SPEED_FULL,
41 [DSTAT_ENUMSPD_LS_PHY_6MHZ] = USB_SPEED_LOW
42 };
43
44 static const uint8_t EP0_MAXLEN[4] = {
45 [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64,
46 [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64,
47 [DSTAT_ENUMSPD_FS_PHY_48MHZ] = EP0MPL_64,
48 [DSTAT_ENUMSPD_LS_PHY_6MHZ] = EP0MPL_8
49 };
50
57 uint32_t usbd_isr (usb_core_handle_struct *pudev)
58 {
59 uint32_t retval = 0U;
60 uint32_t int_status = 0U, gintf = USB_GINTF, ginten = USB_GINTEN;
61
62 /* ensure the core is in device mode */
63 if (DEVICE_MODE == USB_CURRENT_MODE_GET()) {
64 int_status = gintf & ginten;
65
66 /* there are no interrupts, avoid spurious interrupt */
67 if (!int_status) {
68 return 0U;
69 }
70
71 /* OUT endpoints interrupts */
72 if (int_status & GINTF_OEPIF) {
73 retval |= usbd_intf_outep(pudev);
74 }
75
76 /* IN endpoints interrupts */
77 if (int_status & GINTF_IEPIF) {
78 retval |= usbd_intf_inep(pudev);
79 }
80
81 /* mode mismatch interrupt */
82 if (int_status & GINTF_MFIF) {
83 /* clear interrupt */
84 USB_GINTF = GINTF_MFIF;
85 }
86
87 /* early suspend interrupt */
88 if (int_status & GINTF_ESP) {
89 retval |= usbd_intf_earlysuspend(pudev);
90 }
91
92 /* suspend interrupt */
93 if (int_status & GINTF_SP) {
94 retval |= usbd_intf_suspend(pudev);
95 }
96
97 /* wakeup interrupt */
98 if (int_status & GINTF_WKUPIF) {
99 retval |= usbd_intf_resume(pudev);
100 }
101
102 /* start of frame interrupt */
103 if (int_status & GINTF_SOF) {
104 retval |= usbd_intf_sof(pudev);
105 }
106
107 /* reveive fifo not empty interrupt */
108 if (int_status & GINTF_RXFNEIF) {
109 retval |= usbd_intf_rxfifo(pudev);
110 }
111
112 /* USB reset interrupt */
113 if (int_status & GINTF_RST) {
114 retval |= usbd_intf_reset(pudev);
115 }
116
117 /* enumeration has been finished interrupt */
118 if (int_status & GINTF_ENUMF) {
119 retval |= usbd_intf_enumfinish(pudev);
120 }
121
122 /* incomplete synchronization in transfer interrupt*/
123 if (int_status & GINTF_ISOINCIF) {
124 retval |= usbd_intf_isoinincomplete(pudev);
125 }
126
127 /* incomplete synchronization out transfer interrupt*/
128 if (int_status & GINTF_ISOONCIF) {
129 retval |= usbd_intf_isooutincomplete(pudev);
130 }
131
132 #ifdef VBUS_SENSING_ENABLED
133
134 /* session request interrupt */
135 if (int_status & GINTF_SESIF) {
136 retval |= usbd_intf_sessionrequest(pudev);
137 }
138
139 /* OTG mode interrupt */
140 if (int_status & GINTF_OTGIF) {
141 retval |= usbd_intf_otg(pudev);
142 }
143 #endif /* VBUS_SENSING_ENABLED */
144 }
145
146 return retval;
147 }
148
155 static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev)
156 {
157 uint8_t endp_num = 0U;
158 uint32_t endp_intr = 0U;
159
160 __IO uint32_t out_endp_intr = 0U;
161
162 /* read in the device interrupt bits */
163 USB_DAOEP_INTR_READ(endp_intr);
164
165 while (endp_intr) {
166 if (endp_intr & 0x1U) {
167 USB_DOEP_INTR_READ(out_endp_intr, (uint16_t)endp_num);
168
169 /* transfer complete interrupt */
170 if (out_endp_intr & DOEPINTF_TF) {
171 USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_TF;
172
173 /* data receive is completed */
174 usbd_out_transaction(pudev, endp_num);
175 }
176
177 /* endpoint disable interrupt */
178 if (out_endp_intr & DOEPINTF_EPDIS) {
179 USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_EPDIS;
180 }
181
182 /* setup phase finished interrupt (just for control endpoints) */
183 if (out_endp_intr & DOEPINTF_STPF) {
184 /* setup phase is completed */
185 usbd_setup_transaction(pudev);
186
187 USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_STPF;
188 }
189
190 /* back to back setup packets received */
191 if (out_endp_intr & DOEPINTF_BTBSTP) {
192 USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_BTBSTP;
193 }
194 }
195
196 endp_num ++;
197 endp_intr >>= 1;
198 }
199
200 return 1U;
201 }
202
209 static uint32_t usbd_intf_inep(usb_core_handle_struct *pudev)
210 {
211 uint8_t endp_num = 0U;
212 uint32_t endp_intr = 0U;
213
214 __IO uint32_t in_endp_intr = 0U;
215
216 /* get all in endpoints which have interrupts */
217 USB_DAIEP_INTR_READ(endp_intr);
218
219 while (endp_intr) {
220 if (endp_intr & 0x1U) {
221 USB_DIEP_INTR_READ(in_endp_intr, (uint16_t)endp_num);
222
223 if (in_endp_intr & DIEPINTF_TF) {
224 /* disable the fifo empty interrupt for the endpoint */
225 USB_DIEPFEINTEN &= ~(0x1U << endp_num);
226
227 USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TF;
228
229 /* data transmittion is completed */
230 usbd_in_transaction(pudev, endp_num);
231 }
232
233 if (in_endp_intr & DIEPINTF_CITO) {
234 USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_CITO;
235 }
236
237 if (in_endp_intr & DIEPINTF_IEPNE) {
238 USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_IEPNE;
239 }
240
241 if (in_endp_intr & DIEPINTF_EPDIS) {
242 USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_EPDIS;
243 }
244
245 if (in_endp_intr & DIEPINTF_TXFE) {
246 usbd_emptytxfifo_write(pudev, endp_num);
247 USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TXFE;
248 }
249 }
250
251 endp_num ++;
252 endp_intr >>= 1;
253 }
254
255 return 1U;
256 }
257
264 static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev)
265 {
266 USB_GINTEN &= ~GINTEN_ESPIE;
267 USB_GINTF = GINTF_ESP;
268
269 return 1U;
270 }
271
278 static uint32_t usbd_intf_suspend(usb_core_handle_struct *pudev)
279 {
280 __IO uint8_t low_power = pudev->cfg.low_power;
281 __IO uint8_t suspend = (uint8_t)(USB_DSTAT & DSTAT_SPST);
282 __IO uint8_t is_configured = (pudev->dev.status == USB_STATUS_CONFIGURED)? 1U : 0U;
283
284 pudev->dev.prev_status = pudev->dev.status;
285 pudev->dev.status = USB_STATUS_SUSPENDED;
286
287 if (low_power && suspend && is_configured) {
288 /* switch-off the otg clocks */
289 USB_PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK;
290
291 /* enter DEEP_SLEEP mode with LDO in low power mode */
292 pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD);
293 }
294
295 /* clear interrupt */
296 USB_GINTF = GINTF_SP;
297
298 return 1U;
299 }
300
307 static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev)
308 {
309 pudev->dev.status = pudev->dev.prev_status;
310 pudev->dev.status = USB_STATUS_CONFIGURED;
311
312 /* clear interrupt */
313 USB_GINTF = GINTF_WKUPIF;
314
315 return 1U;
316 }
317
324 static uint32_t usbd_intf_sof(usb_core_handle_struct *pudev)
325 {
326 if (NULL != usbd_int_fops) {
327 usbd_int_fops->SOF(pudev);
328 }
329
330 USB_GINTF = GINTF_SOF;
331
332 return 1U;
333 }
334
341 static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev)
342 {
343 usb_ep_struct *ep;
344 uint8_t data_pid = 0U, endp_num = 0U;
345 uint32_t bcount = 0U, packet_num = 0U;
346
347 /* get the status from the top of the fifo (must be read to a variable) */
348 __IO uint32_t rx_status = USB_GRSTATP;
349
350 /* disable the rx fifo non-empty interrupt */
351 USB_GINTEN &= ~GINTEN_RXFNEIE;
352
353 endp_num = (uint8_t)(rx_status & GRSTATRP_EPNUM);
354 bcount = (rx_status & GRSTATRP_BCOUNT) >> 4U;
355 data_pid = (uint8_t)((rx_status & GRSTATRP_DPID) >> 15U);
356
357 /* ensure no-DMA mode can work */
358 packet_num = USB_DOEPxLEN((uint16_t)endp_num) & DEPLEN_PCNT;
359 if ((1U == endp_num) && (0U == packet_num)) {
360 uint32_t devepctl = USB_DOEPxCTL((uint16_t)endp_num);
361
362 devepctl |= DEPCTL_SNAK;
363 devepctl &= ~DEPCTL_EPEN;
364 devepctl &= ~DEPCTL_EPD;
365
366 USB_DOEPxCTL((uint16_t)endp_num) = devepctl;
367 }
368
369 ep = &pudev->dev.out_ep[endp_num];
370
371 switch ((rx_status & GRSTATRP_RPCKST) >> 17U) {
372 case RXSTAT_GOUT_NAK:
373 if(0U != bcount) {
374 return 0U;
375 }
376 break;
377 case RXSTAT_DATA_UPDT:
378 if (bcount > 0U) {
379 usb_fifo_read(ep->xfer_buff, (uint16_t)bcount);
380 ep->xfer_buff += bcount;
381 ep->xfer_count += bcount;
382 }
383 break;
384 case RXSTAT_XFER_COMP:
385 if (0U != bcount) {
386 return 0U;
387 }
388 break;
389 case RXSTAT_SETUP_COMP:
390 if(0U != bcount) {
391 return 0U;
392 }
393 break;
394 case RXSTAT_SETUP_UPDT:
395 *(uint32_t *)0x5000081CU |= 0x00020000U;
396 if ((0U == endp_num) && (8U == bcount) && (DPID_DATA0 == data_pid)) {
397 /* copy the setup packet received in fifo into the setup buffer in ram */
398 usb_fifo_read(pudev->dev.setup_packet, 8U);
399
400 ep->xfer_count += bcount;
401 }
402 break;
403 default:
404 break;
405 }
406
407 /* enable the Rx fifo non-empty interrupt */
408 USB_GINTEN |= GINTEN_RXFNEIE;
409
410 return 1U;
411 }
412
419 static uint32_t usbd_intf_reset(usb_core_handle_struct *pudev)
420 {
421 uint8_t i = 0U;
422 usb_ep_struct *ep;
423
424 /* clear the remote wakeup signaling */
425 USB_DCTL &= ~DCTL_RWKUP;
426
427 /* flush the tx fifo */
428 usb_txfifo_flush(pudev, 0U);
429
430 for (i = 0U; i < pudev->cfg.dev_endp_num; i++) {
431 USB_DIEPxINTF((uint16_t)i) = 0xFFU;
432 USB_DOEPxINTF((uint16_t)i) = 0xFFU;
433 }
434
435 /* clear all pending device endpoint interrupts */
436 USB_DAEPINT = 0xFFFFFFFFU;
437
438 /* enable endpoint 0 interrupts */
439 USB_DAEPINTEN &= ~DAEPINTEN_OEPIE;
440 USB_DAEPINTEN &= ~DAEPINTEN_IEPIE;
441 USB_DAEPINTEN = (1U << 16) | 1U;
442
443 /* enable out endpoint interrupts */
444 USB_DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN | DOEPINTEN_EPDISEN;
445
446 /* enable in endpoint interrupts */
447 USB_DIEPINTEN = DIEPINTEN_TFEN | DIEPINTEN_CITOEN | DIEPINTEN_EPDISEN;
448
449 /* reset device address */
450 USB_DCFG &= ~DCFG_DAR;
451 USB_DCFG |= 0U << 4U;
452
453 /* configure endpoint 0 to receive setup packets */
454 usb_ep0_startout(pudev);
455
456 /* clear usb reset interrupt */
457 USB_GINTF = GINTF_RST;
458
459 /* open EP0 IN */
460 ep = &pudev->dev.in_ep[0];
461
462 USB_DIEPxCTL(0U) &= ~DEP0CTL_MPL;
463 USB_DIEPxCTL(0U) &= ~DEPCTL_EPTYPE;
464 USB_DIEPxCTL(0U) &= ~DIEPCTL_TXFNUM;
465
466 if (!(USB_DIEPxCTL(0U) & DEP0CTL_EPACT)) {
467 USB_DIEPxCTL(0U) |= USB_MAX_EP0_SIZE;
468 USB_DIEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U);
469 USB_DIEPxCTL(0U) |= DEP0CTL_EPACT;
470 }
471
472 ep->endp_mps = USB_MAX_EP0_SIZE;
473 ep->endp_type = USB_EPTYPE_CTRL;
474
475 /* open EP0 OUT */
476 ep = &pudev->dev.out_ep[0];
477
478 USB_DOEPxCTL(0U) &= ~DEP0CTL_MPL;
479 USB_DOEPxCTL(0U) &= ~DEPCTL_EPTYPE;
480
481 if (!(USB_DOEPxCTL(0U) & DEP0CTL_EPACT)) {
482 USB_DOEPxCTL(0U) |= USB_MAX_EP0_SIZE;
483 USB_DOEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U);
484 USB_DOEPxCTL(0U) |= DEP0CTL_EPACT;
485 }
486
487 ep->endp_mps = USB_MAX_EP0_SIZE;
488 ep->endp_type = USB_EPTYPE_CTRL;
489
490 pudev->dev.status = USB_STATUS_DEFAULT;
491
492 return 1U;
493 }
494
501 static uint32_t usbd_intf_enumfinish(usb_core_handle_struct *pudev)
502 {
503 uint8_t enum_speed = (uint8_t)((USB_DSTAT & DSTAT_ES) >> 1U);
504
505 /* set the max packet size of devie in endpoint based on the enumeration speed */
506 USB_DIEPxCTL(0U) |= EP0_MAXLEN[enum_speed];
507
508 /* clear global IN NAK */
509 USB_DCTL &= ~DCTL_CGINAK;
510 USB_DCTL |= DCTL_CGINAK;
511
512 /* set USB turn-around time based on device speed and PHY interface */
513 if (USB_SPEED_HIGH == USB_SPEED[enum_speed]) {
514 pudev->cfg.core_speed = USB_CORE_SPEED_HIGH;
515 pudev->cfg.max_packet_size = USBHS_MAX_PACKET_SIZE;
516
517 USB_GUSBCS &= ~GUSBCS_UTT;
518 USB_GUSBCS |= 0x09U << 10;
519 } else {
520 pudev->cfg.core_speed = USB_CORE_SPEED_FULL;
521 pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE;
522
523 USB_GUSBCS &= ~GUSBCS_UTT;
524 USB_GUSBCS |= 0x05U << 10;
525 }
526
527 /* clear interrupt */
528 USB_GINTF = GINTF_ENUMF;
529
530 return 1U;
531 }
532
539 static uint32_t usbd_intf_isoinincomplete(usb_core_handle_struct *pudev)
540 {
541 // USBD_DCD_INT_fops->IsoINIncomplete (pudev);
542
543 /* clear interrupt */
544 USB_GINTF = GINTF_ISOINCIF;
545
546 return 1U;
547 }
548
555 static uint32_t usbd_intf_isooutincomplete(usb_core_handle_struct *pudev)
556 {
557 // USBD_DCD_INT_fops->IsoOUTIncomplete (pudev);
558
559 /* clear interrupt */
560 USB_GINTF = GINTF_ISOONCIF;
561
562 return 1U;
563 }
564
572 static uint32_t usbd_emptytxfifo_write(usb_core_handle_struct *pudev, uint8_t ep_num)
573 {
574 uint32_t len = 0U, word_len = 0U, fifo_empty_mask = 0U;
575 usb_ep_struct *ep;
576
577 ep = &pudev->dev.in_ep[ep_num];
578 len = ep->xfer_len - ep->xfer_count;
579
580 if (len > ep->endp_mps) {
581 len = ep->endp_mps;
582 }
583
584 word_len = (len + 3U) / 4U;
585
586 while (((USB_DIEPxTFSTAT((uint16_t)ep_num) & DIEPTFSTAT_IEPTFS) > word_len) &&
587 (ep->xfer_count < ep->xfer_len)) {
588 /* write the FIFO */
589 len = ep->xfer_len - ep->xfer_count;
590
591 if (len > ep->endp_mps) {
592 len = ep->endp_mps;
593 }
594
595 word_len = (len + 3U) / 4U;
596
597 usb_fifo_write (ep->xfer_buff, ep_num, (uint16_t)len);
598
599 ep->xfer_buff += len;
600 ep->xfer_count += len;
601
602 if(ep->xfer_len == ep->xfer_count) {
603 fifo_empty_mask = 0x1U << ep_num;
604 USB_DIEPFEINTEN &= ~fifo_empty_mask;
605 }
606 }
607
608 return 1U;
609 }
610
611 #ifdef VBUS_SENSING_ENABLED
612
619 static uint32_t usbd_intf_sessionrequest(usb_core_handle_struct *pudev)
620 {
621 pudev->dev.connection_status = 1U;
622
623 /* clear the interrupt bit */
624 USB_GINTF = GINTF_SESIF;
625
626 return 1;
627 }
628
635 static uint32_t usbd_intf_otg(usb_core_handle_struct *pudev)
636 {
637 if (USB_GOTGINTF & GOTGINTF_SESEND) {
638 pudev->dev.class_deinit(pudev, 0);
639 pudev->dev.connection_status = 0;
640 }
641
642 /* clear OTG interrupt */
643 USB_GOTGINTF |= GOTGINTF_SESEND;
644
645 return 1;
646 }
647
648 #endif /* VBUS_SENSING_ENABLED */
GINTEN_ESPIE
#define GINTEN_ESPIE
Definition: usb_regs.h:189
USB_STATUS_SUSPENDED
#define USB_STATUS_SUSPENDED
Definition: usbd_core.h:23
DOEPINTEN_STPFEN
#define DOEPINTEN_STPFEN
Definition: usb_regs.h:372
USB_DIEPxTFSTAT
#define USB_DIEPxTFSTAT(x)
Definition: usb_regs.h:89
usbd_int_fops
usbd_int_cb_struct * usbd_int_fops
usb_txfifo_flush
usb_status_enum usb_txfifo_flush(usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs
Definition: usb_core.c:208
usbd_std.h
USB 2.0 standard defines.
DIEPINTF_IEPNE
#define DIEPINTF_IEPNE
Definition: usb_regs.h:452
GINTF_IEPIF
#define GINTF_IEPIF
Definition: usb_regs.h:155
usb_fifo_read
void * usb_fifo_read(uint8_t *dest, uint16_t len)
read a packet from the Rx FIFO associated with the endpoint
Definition: usb_core.c:102
USBFS_MAX_PACKET_SIZE
#define USBFS_MAX_PACKET_SIZE
Definition: usb_defines.h:24
DIEPINTEN_CITOEN
#define DIEPINTEN_CITOEN
Definition: usb_regs.h:364
DSTAT_ENUMSPD_LS_PHY_6MHZ
#define DSTAT_ENUMSPD_LS_PHY_6MHZ
Definition: usb_defines.h:39
USB_DOEPINTEN
#define USB_DOEPINTEN
Definition: usb_regs.h:69
USB_DIEPxINTF
#define USB_DIEPxINTF(x)
Definition: usb_regs.h:85
DEPCTL_EPTYPE
#define DEPCTL_EPTYPE
Definition: usb_regs.h:442
GINTF_RXFNEIF
#define GINTF_RXFNEIF
Definition: usb_regs.h:165
USB_STATUS_CONFIGURED
#define USB_STATUS_CONFIGURED
Definition: usbd_core.h:22
usb_ep_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:108
DOEPINTF_BTBSTP
#define DOEPINTF_BTBSTP
Definition: usb_regs.h:460
DIEPINTEN_EPDISEN
#define DIEPINTEN_EPDISEN
Definition: usb_regs.h:365
DIEPTFSTAT_IEPTFS
#define DIEPTFSTAT_IEPTFS
Definition: usb_regs.h:489
RXSTAT_DATA_UPDT
#define RXSTAT_DATA_UPDT
Definition: usb_defines.h:58
DEPCTL_SNAK
#define DEPCTL_SNAK
Definition: usb_regs.h:437
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:71
usb_core_cfgs_struct::dev_endp_num
uint8_t dev_endp_num
Definition: usb_core.h:65
GINTF_ISOINCIF
#define GINTF_ISOINCIF
Definition: usb_regs.h:153
USB_DIEPINTEN
#define USB_DIEPINTEN
Definition: usb_regs.h:68
usbd_int_cb_struct::SOF
uint8_t(* SOF)(usb_core_handle_struct *pudev)
Definition: usbd_int.h:19
usb_core_cfgs_struct::max_packet_size
uint16_t max_packet_size
Definition: usb_core.h:68
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:431
USB_GUSBCS
#define USB_GUSBCS
Definition: usb_regs.h:38
USB_GINTEN
#define USB_GINTEN
Definition: usb_regs.h:41
usbd_setup_transaction
usbd_status_enum usbd_setup_transaction(usb_core_handle_struct *pudev)
USB setup stage processing.
Definition: usbd_std.c:69
usb_fifo_write
usb_status_enum usb_fifo_write(uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint
Definition: usb_core.c:79
GINTF_SESIF
#define GINTF_SESIF
Definition: usb_regs.h:145
USB_SPEED_FULL
Definition: usb_defines.h:96
USB_GINTF
#define USB_GINTF
Definition: usb_regs.h:40
USB_EPTYPE_CTRL
#define USB_EPTYPE_CTRL
Definition: usb_defines.h:51
DEPCTL_EPD
#define DEPCTL_EPD
Definition: usb_regs.h:432
DOEPINTF_EPDIS
#define DOEPINTF_EPDIS
Definition: usb_regs.h:463
GRSTATRP_DPID
#define GRSTATRP_DPID
Definition: usb_regs.h:200
DCTL_RWKUP
#define DCTL_RWKUP
Definition: usb_regs.h:352
usb_speed_enum
usb_speed_enum
Definition: usb_defines.h:92
GRSTATRP_RPCKST
#define GRSTATRP_RPCKST
Definition: usb_regs.h:199
USB_PWRCLKCTL
#define USB_PWRCLKCTL
Definition: usb_regs.h:91
DCFG_DAR
#define DCFG_DAR
Definition: usb_regs.h:339
DCTL_CGINAK
#define DCTL_CGINAK
Definition: usb_regs.h:347
usb_ep_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:101
USB_DAIEP_INTR_READ
#define USB_DAIEP_INTR_READ(x)
Definition: usb_regs.h:574
USB_SPEED_HIGH
Definition: usb_defines.h:97
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:103
DIEPINTF_CITO
#define DIEPINTF_CITO
Definition: usb_regs.h:454
DIEPINTF_EPDIS
#define DIEPINTF_EPDIS
Definition: usb_regs.h:455
USB_DOEPxINTF
#define USB_DOEPxINTF(x)
Definition: usb_regs.h:86
DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ
#define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ
Definition: usb_defines.h:38
usb_ep_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:107
DOEPINTEN_TFEN
#define DOEPINTEN_TFEN
Definition: usb_regs.h:374
USB_SPEED_LOW
Definition: usb_defines.h:95
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:83
USB_CORE_SPEED_FULL
#define USB_CORE_SPEED_FULL
Definition: usb_defines.h:22
PMU_LDO_LOWPOWER
#define PMU_LDO_LOWPOWER
Definition: gd32f3x0_pmu.h:91
USB_CURRENT_MODE_GET
#define USB_CURRENT_MODE_GET()
Definition: usb_regs.h:548
DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ
#define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ
Definition: usb_defines.h:37
DEPLEN_PCNT
#define DEPLEN_PCNT
Definition: usb_regs.h:479
usbd_isr
uint32_t usbd_isr(usb_core_handle_struct *pudev)
USB device-mode interrupts global service routine handler.
Definition: usbd_int.c:57
DSTAT_ENUMSPD_FS_PHY_48MHZ
#define DSTAT_ENUMSPD_FS_PHY_48MHZ
Definition: usb_defines.h:40
DSTAT_ES
#define DSTAT_ES
Definition: usb_regs.h:356
GINTF_OEPIF
#define GINTF_OEPIF
Definition: usb_regs.h:154
DOEPINTF_STPF
#define DOEPINTF_STPF
Definition: usb_regs.h:462
USB_DAEPINT
#define USB_DAEPINT
Definition: usb_regs.h:70
usb_ep_struct
Definition: usb_core.h:99
USB_DSTAT
#define USB_DSTAT
Definition: usb_regs.h:67
usb_core_cfgs_struct::core_speed
uint8_t core_speed
Definition: usb_core.h:62
USB_GRSTATP
#define USB_GRSTATP
Definition: usb_regs.h:43
usb_core_cfgs_struct::low_power
uint8_t low_power
Definition: usb_core.h:67
GINTF_ESP
#define GINTF_ESP
Definition: usb_regs.h:161
GRSTATRP_EPNUM
#define GRSTATRP_EPNUM
Definition: usb_regs.h:203
EP0MPL_64
#define EP0MPL_64
Definition: usb_regs.h:524
USB_DOEP_INTR_READ
#define USB_DOEP_INTR_READ(x, EpID)
Definition: usb_regs.h:567
USB_CORE_SPEED_HIGH
#define USB_CORE_SPEED_HIGH
Definition: usb_defines.h:21
DIEPINTF_TF
#define DIEPINTF_TF
Definition: usb_regs.h:456
EP0MPL_8
#define EP0MPL_8
Definition: usb_regs.h:527
usbd_int.h
USB device mode interrupt handler header file.
DOEPINTEN_EPDISEN
#define DOEPINTEN_EPDISEN
Definition: usb_regs.h:373
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:84
USB_GOTGINTF
#define USB_GOTGINTF
Definition: usb_regs.h:36
DSTAT_SPST
#define DSTAT_SPST
Definition: usb_regs.h:357
WFI_CMD
#define WFI_CMD
Definition: gd32f3x0_pmu.h:119
GINTF_OTGIF
#define GINTF_OTGIF
Definition: usb_regs.h:167
GINTF_SP
#define GINTF_SP
Definition: usb_regs.h:160
usbd_out_transaction
usbd_status_enum usbd_out_transaction(usb_core_handle_struct *pudev, uint8_t endp_num)
data out stage processing
Definition: usbd_std.c:103
USB_DIEPFEINTEN
#define USB_DIEPFEINTEN
Definition: usb_regs.h:74
RXSTAT_SETUP_COMP
#define RXSTAT_SETUP_COMP
Definition: usb_defines.h:60
GUSBCS_UTT
#define GUSBCS_UTT
Definition: usb_regs.h:127
usb_core_handle_struct
Definition: usb_core.h:200
RXSTAT_XFER_COMP
#define RXSTAT_XFER_COMP
Definition: usb_defines.h:59
USB_DIEP_INTR_READ
#define USB_DIEP_INTR_READ(x, EpID)
Definition: usb_regs.h:584
DAEPINTEN_IEPIE
#define DAEPINTEN_IEPIE
Definition: usb_regs.h:382
USB_MAX_EP0_SIZE
#define USB_MAX_EP0_SIZE
Definition: usb_core.h:19
USB_DOEPxLEN
#define USB_DOEPxLEN(x)
Definition: usb_regs.h:88
NULL
#define NULL
Definition: usb_defines.h:18
GINTF_WKUPIF
#define GINTF_WKUPIF
Definition: usb_regs.h:144
USB_DAOEP_INTR_READ
#define USB_DAOEP_INTR_READ(x)
Definition: usb_regs.h:558
usbd_in_transaction
usbd_status_enum usbd_in_transaction(usb_core_handle_struct *pudev, uint8_t endp_num)
data in stage processing
Definition: usbd_std.c:142
GOTGINTF_SESEND
#define GOTGINTF_SESEND
Definition: usb_regs.h:113
GRSTATRP_BCOUNT
#define GRSTATRP_BCOUNT
Definition: usb_regs.h:201
PWRCLKCTL_SUCLK
#define PWRCLKCTL_SUCLK
Definition: usb_regs.h:493
GINTEN_RXFNEIE
#define GINTEN_RXFNEIE
Definition: usb_regs.h:193
GINTF_RST
#define GINTF_RST
Definition: usb_regs.h:159
GINTF_ISOONCIF
#define GINTF_ISOONCIF
Definition: usb_regs.h:152
DIEPINTEN_TFEN
#define DIEPINTEN_TFEN
Definition: usb_regs.h:366
pmu_to_deepsleepmode
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd)
PMU work at deepsleep mode.
Definition: gd32f3x0_pmu.c:215
USBHS_MAX_PACKET_SIZE
#define USBHS_MAX_PACKET_SIZE
Definition: usb_defines.h:29
DAEPINTEN_OEPIE
#define DAEPINTEN_OEPIE
Definition: usb_regs.h:381
DIEPCTL_TXFNUM
#define DIEPCTL_TXFNUM
Definition: usb_regs.h:439
USB_DCFG
#define USB_DCFG
Definition: usb_regs.h:65
DPID_DATA0
#define DPID_DATA0
Definition: usb_defines.h:63
GINTF_ENUMF
#define GINTF_ENUMF
Definition: usb_regs.h:158
USB_STATUS_DEFAULT
#define USB_STATUS_DEFAULT
Definition: usbd_core.h:20
RXSTAT_GOUT_NAK
#define RXSTAT_GOUT_NAK
Definition: usb_defines.h:57
GINTF_SOF
#define GINTF_SOF
Definition: usb_regs.h:166
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:47
DEP0CTL_MPL
#define DEP0CTL_MPL
Definition: usb_regs.h:428
USB_DCTL
#define USB_DCTL
Definition: usb_regs.h:66
DEP0CTL_EPACT
#define DEP0CTL_EPACT
Definition: usb_regs.h:427
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:106
GINTF_MFIF
#define GINTF_MFIF
Definition: usb_regs.h:168
RXSTAT_SETUP_UPDT
#define RXSTAT_SETUP_UPDT
Definition: usb_defines.h:61
DOEPINTF_TF
#define DOEPINTF_TF
Definition: usb_regs.h:464
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:202
PWRCLKCTL_SHCLK
#define PWRCLKCTL_SHCLK
Definition: usb_regs.h:492
DIEPINTF_TXFE
#define DIEPINTF_TXFE
Definition: usb_regs.h:451
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_rcu.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_rcu.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_rcu.h"
13
14 /* define clock source */
15 #define SEL_IRC8M 0x00U
16 #define SEL_HXTAL 0x01U
17 #define SEL_PLL 0x02U
18
19 /* define startup timeout count */
20 #define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU)
21 #define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU)
22
29 void rcu_deinit(void)
30 {
31 /* enable IRC8M */
32 RCU_CTL0 |= RCU_CTL0_IRC8MEN;
33 while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
34 }
35 /* reset RCU */
36 RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
37 RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
38 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
39 #if (defined(GD32F350))
40 RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC);
41 RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2);
42 #endif /* GD32F350 */
43 RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
44 RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL);
45 RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
46 RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
47 RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
48 RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
49 RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN;
50 RCU_INT = 0x00000000U;
51 RCU_ADDINT = 0x00000000U;
52 }
53
78 void rcu_periph_clock_enable(rcu_periph_enum periph)
79 {
80 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
81 }
82
107 void rcu_periph_clock_disable(rcu_periph_enum periph)
108 {
109 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
110 }
111
121 void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
122 {
123 RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
124 }
125
135 void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
136 {
137 RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
138 }
160 void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
161 {
162 RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
163 }
164
186 void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
187 {
188 RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset));
189 }
190
197 void rcu_bkp_reset_enable(void)
198 {
199 RCU_BDCTL |= RCU_BDCTL_BKPRST;
200 }
201
208 void rcu_bkp_reset_disable(void)
209 {
210 RCU_BDCTL &= ~RCU_BDCTL_BKPRST;
211 }
212
223 void rcu_system_clock_source_config(uint32_t ck_sys)
224 {
225 uint32_t cksys_source = 0U;
226 cksys_source = RCU_CFG0;
227 /* reset the SCS bits and set according to ck_sys */
228 cksys_source &= ~RCU_CFG0_SCS;
229 RCU_CFG0 = (ck_sys | cksys_source);
230 }
231
241 uint32_t rcu_system_clock_source_get(void)
242 {
243 return (RCU_CFG0 & RCU_CFG0_SCSS);
244 }
245
253 void rcu_ahb_clock_config(uint32_t ck_ahb)
254 {
255 uint32_t ahbpsc = 0U;
256 ahbpsc = RCU_CFG0;
257 /* reset the AHBPSC bits and set according to ck_ahb */
258 ahbpsc &= ~RCU_CFG0_AHBPSC;
259 RCU_CFG0 = (ck_ahb | ahbpsc);
260 }
261
273 void rcu_apb1_clock_config(uint32_t ck_apb1)
274 {
275 uint32_t apb1psc = 0U;
276 apb1psc = RCU_CFG0;
277 /* reset the APB1PSC and set according to ck_apb1 */
278 apb1psc &= ~RCU_CFG0_APB1PSC;
279 RCU_CFG0 = (ck_apb1 | apb1psc);
280 }
281
293 void rcu_apb2_clock_config(uint32_t ck_apb2)
294 {
295 uint32_t apb2psc = 0U;
296 apb2psc = RCU_CFG0;
297 /* reset the APB2PSC and set according to ck_apb2 */
298 apb2psc &= ~RCU_CFG0_APB2PSC;
299 RCU_CFG0 = (ck_apb2 | apb2psc);
300 }
301
318 void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc)
319 {
320 /* reset the ADCPSC, ADCSEL, IRC28MDIV bits */
321 RCU_CFG0 &= ~RCU_CFG0_ADCPSC;
322 RCU_CFG2 &= ~(RCU_CFG2_ADCSEL | RCU_CFG2_IRC28MDIV | RCU_CFG2_ADCPSC2);
323
324 /* set the ADC clock according to ck_adc */
325 switch(ck_adc){
326 case RCU_ADCCK_IRC28M_DIV2:
327 RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
328 RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
329 break;
330 case RCU_ADCCK_IRC28M:
331 RCU_CFG2 |= RCU_CFG2_IRC28MDIV;
332 RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
333 break;
334 case RCU_ADCCK_APB2_DIV2:
335 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2;
336 RCU_CFG2 |= RCU_CFG2_ADCSEL;
337 break;
338 case RCU_ADCCK_APB2_DIV3:
339 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2;
340 RCU_CFG2 |= RCU_CFG2_ADCPSC2;
341 RCU_CFG2 |= RCU_CFG2_ADCSEL;
342 break;
343 case RCU_ADCCK_APB2_DIV4:
344 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4;
345 RCU_CFG2 |= RCU_CFG2_ADCSEL;
346 break;
347 case RCU_ADCCK_APB2_DIV5:
348 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4;
349 RCU_CFG2 |= RCU_CFG2_ADCPSC2;
350 RCU_CFG2 |= RCU_CFG2_ADCSEL;
351 break;
352 case RCU_ADCCK_APB2_DIV6:
353 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6;
354 RCU_CFG2 |= RCU_CFG2_ADCSEL;
355 break;
356 case RCU_ADCCK_APB2_DIV7:
357 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6;
358 RCU_CFG2 |= RCU_CFG2_ADCPSC2;
359 RCU_CFG2 |= RCU_CFG2_ADCSEL;
360 break;
361 case RCU_ADCCK_APB2_DIV8:
362 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8;
363 RCU_CFG2 |= RCU_CFG2_ADCSEL;
364 break;
365 case RCU_ADCCK_APB2_DIV9:
366 RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8;
367 RCU_CFG2 |= RCU_CFG2_ADCPSC2;
368 RCU_CFG2 |= RCU_CFG2_ADCSEL;
369 break;
370 default:
371 break;
372 }
373 }
374
387 void rcu_usbfs_clock_config(uint32_t ck_usbfs)
388 {
389 /* reset the USBFSPSC bits and set according to ck_usbfs */
390 RCU_CFG0 &= ~RCU_CFG0_USBFSPSC;
391 RCU_CFG2 &= ~RCU_CFG2_USBFSPSC2;
392
393 RCU_CFG0 |= (ck_usbfs & (~RCU_CFG2_USBFSPSC2));
394 RCU_CFG2 |= (ck_usbfs & RCU_CFG2_USBFSPSC2);
395 }
396
414 void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div)
415 {
416 uint32_t ckout = 0U;
417 ckout = RCU_CFG0;
418 /* reset the CKOUTSEL, CKOUTDIV and PLLDV bits and set according to ckout_src and ckout_div */
419 ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
420 RCU_CFG0 = (ckout | ckout_src | ckout_div);
421 }
422
431 void rcu_pll_preselection_config(uint32_t pll_presel)
432 {
433 RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL);
434 RCU_CFG1 |= pll_presel;
435 }
436
447 void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
448 {
449 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
450 RCU_CFG1 &= ~(RCU_CFG1_PLLMF5);
451 RCU_CFG0 |= (pll_src | (pll_mul & (~RCU_CFG1_PLLMF5)));
452 RCU_CFG1 |= (pll_mul & RCU_CFG1_PLLMF5);
453 }
454
465 void rcu_usart_clock_config(uint32_t ck_usart)
466 {
467 /* reset the USART0SEL bits and set according to ck_usart */
468 RCU_CFG2 &= ~RCU_CFG2_USART0SEL;
469 RCU_CFG2 |= ck_usart;
470 }
471
480 void rcu_cec_clock_config(uint32_t ck_cec)
481 {
482 /* reset the CECSEL bit and set according to ck_cec */
483 RCU_CFG2 &= ~RCU_CFG2_CECSEL;
484 RCU_CFG2 |= ck_cec;
485 }
486
497 void rcu_rtc_clock_config(uint32_t rtc_clock_source)
498 {
499 /* reset the RTCSRC bits and set according to rtc_clock_source */
500 RCU_BDCTL &= ~RCU_BDCTL_RTCSRC;
501 RCU_BDCTL |= rtc_clock_source;
502 }
503
511 void rcu_hxtal_prediv_config(uint32_t hxtal_prediv)
512 {
513 uint32_t prediv = 0U;
514 prediv = RCU_CFG1;
515 /* reset the HXTALPREDV bits and set according to hxtal_prediv */
516 prediv &= ~RCU_CFG1_PREDV;
517 RCU_CFG1 = (prediv | hxtal_prediv);
518 }
519
530 void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap)
531 {
532 /* reset the LXTALDRI bits and set according to lxtal_dricap */
533 RCU_BDCTL &= ~RCU_BDCTL_LXTALDRI;
534 RCU_BDCTL |= lxtal_dricap;
535 }
536
559 FlagStatus rcu_flag_get(rcu_flag_enum flag)
560 {
561 if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){
562 return SET;
563 }else{
564 return RESET;
565 }
566 }
567
574 void rcu_all_reset_flag_clear(void)
575 {
576 RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
577 }
578
594 FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
595 {
596 if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){
597 return SET;
598 }else{
599 return RESET;
600 }
601 }
602
618 void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
619 {
620 RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear));
621 }
622
637 void rcu_interrupt_enable(rcu_int_enum stab_int)
638 {
639 RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int));
640 }
641
642
657 void rcu_interrupt_disable(rcu_int_enum stab_int)
658 {
659 RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int));
660 }
661
675 ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
676 {
677 uint32_t stb_cnt = 0U;
678 ErrStatus reval = ERROR;
679 FlagStatus osci_stat = RESET;
680 switch(osci){
681 case RCU_HXTAL:
682 /* wait until HXTAL is stabilization and osci_stat is not more than timeout */
683 while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){
684 osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
685 stb_cnt++;
686 }
687 if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){
688 reval = SUCCESS;
689 }
690 break;
691 /* wait LXTAL stable */
692 case RCU_LXTAL:
693 while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){
694 osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
695 stb_cnt++;
696 }
697
698 /* check whether flag is set or not */
699 if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){
700 reval = SUCCESS;
701 }
702 break;
703
704 /* wait IRC8M stable */
705 case RCU_IRC8M:
706 while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){
707 osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
708 stb_cnt++;
709 }
710
711 /* check whether flag is set or not */
712 if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){
713 reval = SUCCESS;
714 }
715 break;
716
717 /* wait IRC48M stable */
718 case RCU_IRC48M:
719 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
720 osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB);
721 stb_cnt++;
722 }
723
724 /* check whether flag is set or not */
725 if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)){
726 reval = SUCCESS;
727 }
728 break;
729
730 /* wait IRC40K stable */
731 case RCU_IRC40K:
732 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
733 osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
734 stb_cnt++;
735 }
736
737 /* check whether flag is set or not */
738 if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){
739 reval = SUCCESS;
740 }
741 break;
742
743 /* wait PLL stable */
744 case RCU_PLL_CK:
745 while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
746 osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
747 stb_cnt++;
748 }
749
750 /* check whether flag is set or not */
751 if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){
752 reval = SUCCESS;
753 }
754 break;
755
756 default:
757 break;
758 }
759 /* return value */
760 return reval;
761 }
762
776 void rcu_osci_on(rcu_osci_type_enum osci)
777 {
778 RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));
779 }
780
794 void rcu_osci_off(rcu_osci_type_enum osci)
795 {
796 RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci));
797 }
798
807 void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
808 {
809 uint32_t reg;
810 switch(osci){
811 case RCU_HXTAL:
812 /* HXTALEN must be reset before enable the oscillator bypass mode */
813 reg = RCU_CTL0;
814 RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
815 RCU_CTL0 = (reg | RCU_CTL0_HXTALBPS);
816 break;
817 case RCU_LXTAL:
818 /* LXTALEN must be reset before enable the oscillator bypass mode */
819 reg = RCU_BDCTL;
820 RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
821 RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
822 break;
823 case RCU_IRC8M:
824 case RCU_IRC28M:
825 case RCU_IRC48M:
826 case RCU_IRC40K:
827 case RCU_PLL_CK:
828 break;
829 default:
830 break;
831 }
832 }
833
842 void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
843 {
844 uint32_t reg;
845 switch(osci){
846 case RCU_HXTAL:
847 /* HXTALEN must be reset before disable the oscillator bypass mode */
848 reg = RCU_CTL0;
849 RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
850 RCU_CTL0 = (reg & (~RCU_CTL0_HXTALBPS));
851 break;
852 case RCU_LXTAL:
853 /* LXTALEN must be reset before disable the oscillator bypass mode */
854 reg = RCU_BDCTL;
855 RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
856 RCU_BDCTL = (reg & (~RCU_BDCTL_LXTALBPS));
857 break;
858 case RCU_IRC8M:
859 case RCU_IRC28M:
860 case RCU_IRC48M:
861 case RCU_IRC40K:
862 case RCU_PLL_CK:
863 break;
864 default:
865 break;
866 }
867 }
868
875 void rcu_hxtal_clock_monitor_enable(void)
876 {
877 RCU_CTL0 |= RCU_CTL0_CKMEN;
878 }
879
886 void rcu_hxtal_clock_monitor_disable(void)
887 {
888 RCU_CTL0 &= ~RCU_CTL0_CKMEN;
889 }
890
897 void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval)
898 {
899 uint32_t adjust = 0U;
900 adjust = RCU_CTL0;
901 /* reset the IRC8MADJ bits and set according to irc8m_adjval */
902 adjust &= ~RCU_CTL0_IRC8MADJ;
903 RCU_CTL0 = (adjust | (((uint32_t)irc8m_adjval)<<3));
904 }
905
912 void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval)
913 {
914 uint32_t adjust = 0U;
915 adjust = RCU_CTL1;
916 /* reset the IRC28MADJ bits and set according to irc28m_adjval */
917 adjust &= ~RCU_CTL1_IRC28MADJ;
918 RCU_CTL1 = (adjust | (((uint32_t)irc28m_adjval)<<3));
919 }
920
927 void rcu_voltage_key_unlock(void)
928 {
929 /* reset the KEY bits and set 0x1A2B3C4D */
930 RCU_VKEY &= ~RCU_VKEY_KEY;
931 RCU_VKEY |= RCU_VKEY_UNLOCK;
932 }
933
944 void rcu_deepsleep_voltage_set(uint32_t dsvol)
945 {
946 /* reset the DSLPVS bits and set according to dsvol */
947 RCU_DSV &= ~RCU_DSV_DSLPVS;
948 RCU_DSV |= dsvol;
949 }
950
964 uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
965 {
966 uint32_t sws = 0U, adcps = 0U, adcps2 = 0U, ck_freq = 0U;
967 uint32_t cksys_freq = 0U, ahb_freq = 0U, apb1_freq = 0U, apb2_freq = 0U;
968 uint32_t adc_freq = 0U, cec_freq = 0U, usart_freq = 0U;
969 uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
970 /* exponent of AHB, APB1 and APB2 clock divider */
971 const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
972 const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
973 const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
974
975 sws = GET_BITS(RCU_CFG0, 2, 3);
976 switch(sws){
977 /* IRC8M is selected as CK_SYS */
978 case SEL_IRC8M:
979 cksys_freq = IRC8M_VALUE;
980 break;
981 /* HXTAL is selected as CK_SYS */
982 case SEL_HXTAL:
983 cksys_freq = HXTAL_VALUE;
984 break;
985 /* PLL is selected as CK_SYS */
986 case SEL_PLL:
987 /* get the value of PLLMF[3:0] */
988 pllmf = GET_BITS(RCU_CFG0, 18, 21);
989 pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
990 pllmf5 = GET_BITS(RCU_CFG1, 31, 31);
991 /* high 16 bits */
992 if(1U == pllmf4){
993 pllmf += 17U;
994 }else{
995 pllmf += 2U;
996 }
997 if(1U == pllmf5){
998 pllmf += 31U;
999 }
1000
1001 /* PLL clock source selection, HXTAL or IRC8M/2 */
1002 pllsel = GET_BITS(RCU_CFG0, 16, 16);
1003 pllpresel = GET_BITS(RCU_CFG1, 30, 30);
1004 if(0U != pllsel){
1005 prediv = (GET_BITS(RCU_CFG1,0, 3) + 1U);
1006 if(0U == pllpresel){
1007 cksys_freq = (HXTAL_VALUE / prediv) * pllmf;
1008 }else{
1009 cksys_freq = (IRC48M_VALUE / prediv) * pllmf;
1010 }
1011 }else{
1012 cksys_freq = (IRC8M_VALUE >> 1) * pllmf;
1013 }
1014 break;
1015 /* IRC8M is selected as CK_SYS */
1016 default:
1017 cksys_freq = IRC8M_VALUE;
1018 break;
1019 }
1020 /* calculate AHB clock frequency */
1021 idx = GET_BITS(RCU_CFG0, 4, 7);
1022 clk_exp = ahb_exp[idx];
1023 ahb_freq = cksys_freq >> clk_exp;
1024
1025 /* calculate APB1 clock frequency */
1026 idx = GET_BITS(RCU_CFG0, 8, 10);
1027 clk_exp = apb1_exp[idx];
1028 apb1_freq = ahb_freq >> clk_exp;
1029
1030 /* calculate APB2 clock frequency */
1031 idx = GET_BITS(RCU_CFG0, 11, 13);
1032 clk_exp = apb2_exp[idx];
1033 apb2_freq = ahb_freq >> clk_exp;
1034
1035 /* return the clocks frequency */
1036 switch(clock){
1037 case CK_SYS:
1038 ck_freq = cksys_freq;
1039 break;
1040 case CK_AHB:
1041 ck_freq = ahb_freq;
1042 break;
1043 case CK_APB1:
1044 ck_freq = apb1_freq;
1045 break;
1046 case CK_APB2:
1047 ck_freq = apb2_freq;
1048 break;
1049 case CK_ADC:
1050 /* calculate ADC clock frequency */
1051 if(RCU_ADCSRC_APB2DIV != (RCU_CFG2 & RCU_CFG2_ADCSEL)){
1052 if(RCU_ADC_IRC28M_DIV1 != (RCU_CFG2 & RCU_CFG2_IRC28MDIV)){
1053 adc_freq = IRC28M_VALUE >> 1;
1054 }else{
1055 adc_freq = IRC28M_VALUE;
1056 }
1057 }else{
1058 /* ADC clock select CK_APB2 divided by 2/3/4/5/6/7/8/9 */
1059 adcps = GET_BITS(RCU_CFG0, 14, 15);
1060 adcps2 = GET_BITS(RCU_CFG2, 31, 31);
1061 switch(adcps){
1062 case 0:
1063 if(0U == adcps2){
1064 adc_freq = apb2_freq / 2U;
1065 }else{
1066 adc_freq = apb2_freq / 3U;
1067 }
1068 break;
1069 case 1:
1070 if(0U == adcps2){
1071 adc_freq = apb2_freq / 4U;
1072 }else{
1073 adc_freq = apb2_freq / 5U;
1074 }
1075 break;
1076 case 2:
1077 if(0U == adcps2){
1078 adc_freq = apb2_freq / 6U;
1079 }else{
1080 adc_freq = apb2_freq / 7U;
1081 }
1082 break;
1083 case 3:
1084 if(0U == adcps2){
1085 adc_freq = apb2_freq / 8U;
1086 }else{
1087 adc_freq = apb2_freq / 9U;
1088 }
1089 break;
1090 default:
1091 break;
1092 }
1093 }
1094 ck_freq = adc_freq;
1095 break;
1096 case CK_CEC:
1097 /* calculate CEC clock frequency */
1098 if(RCU_CECSRC_LXTAL != (RCU_CFG2 & RCU_CFG2_CECSEL)){
1099 cec_freq = IRC8M_VALUE / 244U;
1100 }else{
1101 cec_freq = LXTAL_VALUE;
1102 }
1103 ck_freq = cec_freq;
1104 break;
1105 case CK_USART:
1106 /* calculate USART clock frequency */
1107 if(RCU_USART0SRC_CKAPB2 == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
1108 usart_freq = apb2_freq;
1109 }else if(RCU_USART0SRC_CKSYS == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
1110 usart_freq = cksys_freq;
1111 }else if(RCU_USART0SRC_LXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
1112 usart_freq = LXTAL_VALUE;
1113 }else if(RCU_USART0SRC_IRC8M == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
1114 usart_freq = IRC8M_VALUE;
1115 }else{
1116 }
1117 ck_freq = usart_freq;
1118 break;
1119 default:
1120 break;
1121 }
1122 return ck_freq;
1123 }
CK_APB1
Definition: gd32f3x0_rcu.h:456
rcu_cec_clock_config
void rcu_cec_clock_config(uint32_t ck_cec)
configure the CEC clock source selection
Definition: gd32f3x0_rcu.c:480
RCU_REG_VAL
#define RCU_REG_VAL(periph)
Definition: gd32f3x0_rcu.h:234
SEL_HXTAL
#define SEL_HXTAL
Definition: gd32f3x0_rcu.c:16
rcu_clock_freq_enum
rcu_clock_freq_enum
Definition: gd32f3x0_rcu.h:452
rcu_interrupt_flag_clear
void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
clear the interrupt flags
Definition: gd32f3x0_rcu.c:618
RCU_CFG1_PLLMF5
#define RCU_CFG1_PLLMF5
Definition: gd32f3x0_rcu.h:190
rcu_apb2_clock_config
void rcu_apb2_clock_config(uint32_t ck_apb2)
configure the APB2 clock prescaler selection
Definition: gd32f3x0_rcu.c:293
RCU_ADCCK_APB2_DIV3
Definition: gd32f3x0_rcu.h:430
RCU_CFG2_ADCPSC2
#define RCU_CFG2_ADCPSC2
Definition: gd32f3x0_rcu.h:198
RCU_FLAG_HXTALSTB
Definition: gd32f3x0_rcu.h:371
RCU_INT
#define RCU_INT
Definition: gd32f3x0_rcu.h:23
rcu_bkp_reset_enable
void rcu_bkp_reset_enable(void)
reset the BKP
Definition: gd32f3x0_rcu.c:197
rcu_periph_clock_disable
void rcu_periph_clock_disable(rcu_periph_enum periph)
disable the peripherals clock
Definition: gd32f3x0_rcu.c:107
RCU_BDCTL_RTCSRC
#define RCU_BDCTL_RTCSRC
Definition: gd32f3x0_rcu.h:161
rcu_irc28m_adjust_value_set
void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval)
set the IRC28M adjust value
Definition: gd32f3x0_rcu.c:912
RCU_CFG1_PLLPRESEL
#define RCU_CFG1_PLLPRESEL
Definition: gd32f3x0_rcu.h:189
rcu_usart_clock_config
void rcu_usart_clock_config(uint32_t ck_usart)
configure the USART clock source selection
Definition: gd32f3x0_rcu.c:465
RCU_CFG2_USBFSPSC2
#define RCU_CFG2_USBFSPSC2
Definition: gd32f3x0_rcu.h:197
rcu_hxtal_clock_monitor_disable
void rcu_hxtal_clock_monitor_disable(void)
disable the HXTAL clock monitor
Definition: gd32f3x0_rcu.c:886
RCU_USART0SRC_LXTAL
#define RCU_USART0SRC_LXTAL
Definition: gd32f3x0_rcu.h:661
rcu_irc8m_adjust_value_set
void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval)
set the IRC8M adjust value
Definition: gd32f3x0_rcu.c:897
RCU_CTL1_IRC28MEN
#define RCU_CTL1_IRC28MEN
Definition: gd32f3x0_rcu.h:201
rcu_periph_clock_enable
void rcu_periph_clock_enable(rcu_periph_enum periph)
enable the peripherals clock
Definition: gd32f3x0_rcu.c:78
rcu_hxtal_clock_monitor_enable
void rcu_hxtal_clock_monitor_enable(void)
enable the HXTAL clock monitor
Definition: gd32f3x0_rcu.c:875
rcu_all_reset_flag_clear
void rcu_all_reset_flag_clear(void)
clear the reset flag
Definition: gd32f3x0_rcu.c:574
rcu_deepsleep_voltage_set
void rcu_deepsleep_voltage_set(uint32_t dsvol)
set voltage in deep sleep mode
Definition: gd32f3x0_rcu.c:944
CK_ADC
Definition: gd32f3x0_rcu.h:458
RCU_ADCCK_APB2_DIV6
Definition: gd32f3x0_rcu.h:433
RCU_ADC_CKAPB2_DIV8
#define RCU_ADC_CKAPB2_DIV8
Definition: gd32f3x0_rcu.h:508
RCU_ADCCK_IRC28M
Definition: gd32f3x0_rcu.h:428
RCU_BDCTL_BKPRST
#define RCU_BDCTL_BKPRST
Definition: gd32f3x0_rcu.h:163
RCU_CTL0_IRC8MADJ
#define RCU_CTL0_IRC8MADJ
Definition: gd32f3x0_rcu.h:46
RCU_FLAG_IRC40KSTB
Definition: gd32f3x0_rcu.h:368
RCU_IRC48M
Definition: gd32f3x0_rcu.h:446
RCU_ADCCK_APB2_DIV5
Definition: gd32f3x0_rcu.h:432
RCU_CFG2_USART0SEL
#define RCU_CFG2_USART0SEL
Definition: gd32f3x0_rcu.h:193
RCU_CFG0_ADCPSC
#define RCU_CFG0_ADCPSC
Definition: gd32f3x0_rcu.h:61
RCU_ADCCK_APB2_DIV9
Definition: gd32f3x0_rcu.h:436
RCU_CTL1_IRC28MADJ
#define RCU_CTL1_IRC28MADJ
Definition: gd32f3x0_rcu.h:203
RCU_USART0SRC_CKSYS
#define RCU_USART0SRC_CKSYS
Definition: gd32f3x0_rcu.h:660
RCU_CFG2_IRC28MDIV
#define RCU_CFG2_IRC28MDIV
Definition: gd32f3x0_rcu.h:196
RCU_CECSRC_LXTAL
#define RCU_CECSRC_LXTAL
Definition: gd32f3x0_rcu.h:666
CK_USART
Definition: gd32f3x0_rcu.h:460
rcu_lxtal_drive_capability_config
void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap)
configure the LXTAL drive capability
Definition: gd32f3x0_rcu.c:530
RCU_ADCCK_APB2_DIV7
Definition: gd32f3x0_rcu.h:434
rcu_interrupt_flag_get
FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
get the clock stabilization interrupt and ckm flags
Definition: gd32f3x0_rcu.c:594
rcu_hxtal_prediv_config
void rcu_hxtal_prediv_config(uint32_t hxtal_prediv)
configure the HXTAL divider used as input of PLL
Definition: gd32f3x0_rcu.c:511
CK_SYS
Definition: gd32f3x0_rcu.h:454
rcu_deinit
void rcu_deinit(void)
deinitialize the RCU
Definition: gd32f3x0_rcu.c:29
rcu_bkp_reset_disable
void rcu_bkp_reset_disable(void)
disable the BKP reset
Definition: gd32f3x0_rcu.c:208
RCU_CFG0_APB1PSC
#define RCU_CFG0_APB1PSC
Definition: gd32f3x0_rcu.h:59
RCU_BDCTL_LXTALEN
#define RCU_BDCTL_LXTALEN
Definition: gd32f3x0_rcu.h:157
gd32f3x0_rcu.h
definitions for the RCU
RCU_HXTAL
Definition: gd32f3x0_rcu.h:442
rcu_interrupt_enable
void rcu_interrupt_enable(rcu_int_enum stab_int)
enable the stabilization interrupt
Definition: gd32f3x0_rcu.c:637
CK_AHB
Definition: gd32f3x0_rcu.h:455
RCU_CFG0_PLLMF4
#define RCU_CFG0_PLLMF4
Definition: gd32f3x0_rcu.h:67
RCU_FLAG_LXTALSTB
Definition: gd32f3x0_rcu.h:369
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
RCU_FLAG_PLLSTB
Definition: gd32f3x0_rcu.h:372
RCU_CFG2_ADCSEL
#define RCU_CFG2_ADCSEL
Definition: gd32f3x0_rcu.h:195
rcu_osci_off
void rcu_osci_off(rcu_osci_type_enum osci)
turn off the oscillator
Definition: gd32f3x0_rcu.c:794
RCU_IRC28M
Definition: gd32f3x0_rcu.h:445
RCU_USART0SRC_CKAPB2
#define RCU_USART0SRC_CKAPB2
Definition: gd32f3x0_rcu.h:659
RCU_CTL1
#define RCU_CTL1
Definition: gd32f3x0_rcu.h:34
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
rcu_periph_enum
rcu_periph_enum
Definition: gd32f3x0_rcu.h:268
RCU_ADCSRC_APB2DIV
#define RCU_ADCSRC_APB2DIV
Definition: gd32f3x0_rcu.h:670
RCU_VKEY
#define RCU_VKEY
Definition: gd32f3x0_rcu.h:39
rcu_adc_clock_enum
rcu_adc_clock_enum
Definition: gd32f3x0_rcu.h:425
OSC_STARTUP_TIMEOUT
#define OSC_STARTUP_TIMEOUT
Definition: gd32f3x0_rcu.c:20
RCU_BDCTL_LXTALBPS
#define RCU_BDCTL_LXTALBPS
Definition: gd32f3x0_rcu.h:159
RCU_CFG1
#define RCU_CFG1
Definition: gd32f3x0_rcu.h:32
RCU_BDCTL_LXTALDRI
#define RCU_BDCTL_LXTALDRI
Definition: gd32f3x0_rcu.h:160
rcu_osci_stab_wait
ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
wait until oscillator stabilization flags is SET
Definition: gd32f3x0_rcu.c:675
RCU_BDCTL
#define RCU_BDCTL
Definition: gd32f3x0_rcu.h:29
RCU_CTL0_PLLEN
#define RCU_CTL0_PLLEN
Definition: gd32f3x0_rcu.h:52
RCU_ADC_CKAPB2_DIV4
#define RCU_ADC_CKAPB2_DIV4
Definition: gd32f3x0_rcu.h:506
RCU_CFG0_PLLMF
#define RCU_CFG0_PLLMF
Definition: gd32f3x0_rcu.h:64
RCU_RSTSCK
#define RCU_RSTSCK
Definition: gd32f3x0_rcu.h:30
RCU_CFG0_SCS
#define RCU_CFG0_SCS
Definition: gd32f3x0_rcu.h:56
rcu_osci_bypass_mode_disable
void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
Definition: gd32f3x0_rcu.c:842
CK_APB2
Definition: gd32f3x0_rcu.h:457
RCU_CTL0_IRC8MSTB
#define RCU_CTL0_IRC8MSTB
Definition: gd32f3x0_rcu.h:45
RCU_CTL0_IRC8MEN
#define RCU_CTL0_IRC8MEN
Definition: gd32f3x0_rcu.h:44
rcu_periph_reset_enum
rcu_periph_reset_enum
Definition: gd32f3x0_rcu.h:323
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f3x0_rcu.c:964
RCU_ADDCTL
#define RCU_ADDCTL
Definition: gd32f3x0_rcu.h:35
RCU_IRC8M
Definition: gd32f3x0_rcu.h:444
CK_CEC
Definition: gd32f3x0_rcu.h:459
RCU_ADC_IRC28M_DIV1
#define RCU_ADC_IRC28M_DIV1
Definition: gd32f3x0_rcu.h:674
rcu_flag_get
FlagStatus rcu_flag_get(rcu_flag_enum flag)
get the clock stabilization and periphral reset flags
Definition: gd32f3x0_rcu.c:559
rcu_system_clock_source_get
uint32_t rcu_system_clock_source_get(void)
get the system clock source
Definition: gd32f3x0_rcu.c:241
SEL_IRC8M
#define SEL_IRC8M
Definition: gd32f3x0_rcu.c:15
RCU_CFG0_CKOUTSEL
#define RCU_CFG0_CKOUTSEL
Definition: gd32f3x0_rcu.h:66
rcu_int_enum
rcu_int_enum
Definition: gd32f3x0_rcu.h:413
rcu_osci_on
void rcu_osci_on(rcu_osci_type_enum osci)
turn on the oscillator
Definition: gd32f3x0_rcu.c:776
RCU_CFG2_CECSEL
#define RCU_CFG2_CECSEL
Definition: gd32f3x0_rcu.h:194
RCU_CFG1_PREDV
#define RCU_CFG1_PREDV
Definition: gd32f3x0_rcu.h:188
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_ADC_CKAPB2_DIV6
#define RCU_ADC_CKAPB2_DIV6
Definition: gd32f3x0_rcu.h:507
rcu_pll_config
void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
configure the PLL clock source selection and PLL multiply factor
Definition: gd32f3x0_rcu.c:447
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
RCU_CFG0_USBFSPSC
#define RCU_CFG0_USBFSPSC
Definition: gd32f3x0_rcu.h:65
rcu_periph_clock_sleep_disable
void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
disable the peripherals clock when sleep mode
Definition: gd32f3x0_rcu.c:135
rcu_int_flag_clear_enum
rcu_int_flag_clear_enum
Definition: gd32f3x0_rcu.h:400
RCU_ADCCK_APB2_DIV8
Definition: gd32f3x0_rcu.h:435
rcu_voltage_key_unlock
void rcu_voltage_key_unlock(void)
unlock the voltage key
Definition: gd32f3x0_rcu.c:927
RCU_CFG0_SCSS
#define RCU_CFG0_SCSS
Definition: gd32f3x0_rcu.h:57
rcu_rtc_clock_config
void rcu_rtc_clock_config(uint32_t rtc_clock_source)
configure the RTC clock source selection
Definition: gd32f3x0_rcu.c:497
rcu_flag_enum
rcu_flag_enum
Definition: gd32f3x0_rcu.h:366
RCU_VKEY_UNLOCK
#define RCU_VKEY_UNLOCK
Definition: gd32f3x0_rcu.h:237
RCU_PLL_CK
Definition: gd32f3x0_rcu.h:448
RCU_DSV_DSLPVS
#define RCU_DSV_DSLPVS
Definition: gd32f3x0_rcu.h:229
rcu_usbfs_clock_config
void rcu_usbfs_clock_config(uint32_t ck_usbfs)
configure the USBFS clock prescaler selection
Definition: gd32f3x0_rcu.c:387
RCU_CTL0_CKMEN
#define RCU_CTL0_CKMEN
Definition: gd32f3x0_rcu.h:51
RCU_RSTSCK_RSTFC
#define RCU_RSTSCK_RSTFC
Definition: gd32f3x0_rcu.h:169
rcu_ckout_config
void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div)
configure the CK_OUT clock source and divider
Definition: gd32f3x0_rcu.c:414
RCU_CFG0_APB2PSC
#define RCU_CFG0_APB2PSC
Definition: gd32f3x0_rcu.h:60
RCU_BIT_POS
#define RCU_BIT_POS(val)
Definition: gd32f3x0_rcu.h:235
rcu_pll_preselection_config
void rcu_pll_preselection_config(uint32_t pll_presel)
configure the PLL clock source preselection
Definition: gd32f3x0_rcu.c:431
RCU_ADC_CKAPB2_DIV2
#define RCU_ADC_CKAPB2_DIV2
Definition: gd32f3x0_rcu.h:505
rcu_interrupt_disable
void rcu_interrupt_disable(rcu_int_enum stab_int)
disable the stabilization interrupt
Definition: gd32f3x0_rcu.c:657
RCU_USART0SRC_IRC8M
#define RCU_USART0SRC_IRC8M
Definition: gd32f3x0_rcu.h:662
RCU_FLAG_IRC8MSTB
Definition: gd32f3x0_rcu.h:370
rcu_system_clock_source_config
void rcu_system_clock_source_config(uint32_t ck_sys)
configure the system clock source
Definition: gd32f3x0_rcu.c:223
RCU_CTL0_HXTALEN
#define RCU_CTL0_HXTALEN
Definition: gd32f3x0_rcu.h:48
rcu_osci_bypass_mode_enable
void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
Definition: gd32f3x0_rcu.c:807
RCU_CFG0_PLLDV
#define RCU_CFG0_PLLDV
Definition: gd32f3x0_rcu.h:69
RCU_ADDCTL_IRC48MEN
#define RCU_ADDCTL_IRC48MEN
Definition: gd32f3x0_rcu.h:208
RCU_ADDINT
#define RCU_ADDINT
Definition: gd32f3x0_rcu.h:36
rcu_periph_sleep_enum
rcu_periph_sleep_enum
Definition: gd32f3x0_rcu.h:315
RCU_CTL0_HXTALBPS
#define RCU_CTL0_HXTALBPS
Definition: gd32f3x0_rcu.h:50
rcu_periph_clock_sleep_enable
void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
enable the peripherals clock when sleep mode
Definition: gd32f3x0_rcu.c:121
RCU_CFG0_CKOUTDIV
#define RCU_CFG0_CKOUTDIV
Definition: gd32f3x0_rcu.h:68
RCU_CFG0_PLLSEL
#define RCU_CFG0_PLLSEL
Definition: gd32f3x0_rcu.h:62
RCU_DSV
#define RCU_DSV
Definition: gd32f3x0_rcu.h:40
RCU_ADCCK_IRC28M_DIV2
Definition: gd32f3x0_rcu.h:427
RCU_ADCCK_APB2_DIV4
Definition: gd32f3x0_rcu.h:431
LXTAL_STARTUP_TIMEOUT
#define LXTAL_STARTUP_TIMEOUT
Definition: gd32f3x0_rcu.c:21
RCU_VKEY_KEY
#define RCU_VKEY_KEY
Definition: gd32f3x0_rcu.h:226
RCU_CFG0_AHBPSC
#define RCU_CFG0_AHBPSC
Definition: gd32f3x0_rcu.h:58
rcu_int_flag_enum
rcu_int_flag_enum
Definition: gd32f3x0_rcu.h:387
RCU_LXTAL
Definition: gd32f3x0_rcu.h:443
SEL_PLL
#define SEL_PLL
Definition: gd32f3x0_rcu.c:17
RCU_IRC40K
Definition: gd32f3x0_rcu.h:447
RCU_ADCCK_APB2_DIV2
Definition: gd32f3x0_rcu.h:429
rcu_adc_clock_config
void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc)
configure the ADC clock prescaler selection
Definition: gd32f3x0_rcu.c:318
rcu_osci_type_enum
rcu_osci_type_enum
Definition: gd32f3x0_rcu.h:440
rcu_apb1_clock_config
void rcu_apb1_clock_config(uint32_t ck_apb1)
configure the APB1 clock prescaler selection
Definition: gd32f3x0_rcu.c:273
rcu_ahb_clock_config
void rcu_ahb_clock_config(uint32_t ck_ahb)
configure the AHB clock prescaler selection
Definition: gd32f3x0_rcu.c:253
RCU_FLAG_IRC48MSTB
Definition: gd32f3x0_rcu.h:374
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_cec.h Source File

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  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_cec.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifdef GD32F350
13
14 #ifndef GD32F3X0_CEC_H
15 #define GD32F3X0_CEC_H
16
17 #include "gd32f3x0.h"
18
19 /* CEC definitions */
20 #define CEC CEC_BASE
22 /* registers definitions */
23 #define CEC_CTL REG32(CEC + 0x00U)
24 #define CEC_CFG REG32(CEC + 0x04U)
25 #define CEC_TDATA REG32(CEC + 0x08U)
26 #define CEC_RDATA REG32(CEC + 0x0CU)
27 #define CEC_INTF REG32(CEC + 0x10U)
28 #define CEC_INTEN REG32(CEC + 0x14U)
30 /* bits definitions */
31 /* CEC_CTL */
32 #define CEC_CTL_CECEN BIT(0)
33 #define CEC_CTL_STAOM BIT(1)
34 #define CEC_CTL_ENDOM BIT(2)
36 /* CEC_CFG */
37 #define CEC_CFG_SFT BITS(0,2)
38 #define CEC_CFG_RTOL BIT(3)
39 #define CEC_CFG_BRES BIT(4)
40 #define CEC_CFG_BREG BIT(5)
41 #define CEC_CFG_BPLEG BIT(6)
42 #define CEC_CFG_BCNG BIT(7)
43 #define CEC_CFG_SFTOPT BIT(8)
44 #define CEC_CFG_OWN_ADDRESS BITS(16,30)
45 #define CEC_CFG_LMEN BIT(31)
47 /* CEC_TDATA */
48 #define CEC_TDATA_TDATA BITS(0,7)
50 /* CEC_RDATA */
51 #define CEC_RDATA_RDATA BITS(0,7)
53 /* CEC_INTF */
54 #define CEC_INTF_BR BIT(0)
55 #define CEC_INTF_REND BIT(1)
56 #define CEC_INTF_RO BIT(2)
57 #define CEC_INTF_BRE BIT(3)
58 #define CEC_INTF_BPSE BIT(4)
59 #define CEC_INTF_BPLE BIT(5)
60 #define CEC_INTF_RAE BIT(6)
61 #define CEC_INTF_ARBF BIT(7)
62 #define CEC_INTF_TBR BIT(8)
63 #define CEC_INTF_TEND BIT(9)
64 #define CEC_INTF_TU BIT(10)
65 #define CEC_INTF_TERR BIT(11)
66 #define CEC_INTF_TAERR BIT(12)
68 /* CEC_INTEN */
69 #define CEC_INTEN_BRIE BIT(0)
70 #define CEC_INTEN_RENDIE BIT(1)
71 #define CEC_INTEN_ROIE BIT(2)
72 #define CEC_INTEN_BREIE BIT(3)
73 #define CEC_INTEN_BPSEIE BIT(4)
74 #define CEC_INTEN_BPLEIE BIT(5)
75 #define CEC_INTEN_RAEIE BIT(6)
76 #define CEC_INTEN_ARBFIE BIT(7)
77 #define CEC_INTEN_TBRIE BIT(8)
78 #define CEC_INTEN_TENDIE BIT(9)
79 #define CEC_INTEN_TUIE BIT(10)
80 #define CEC_INTEN_TERRIE BIT(11)
81 #define CEC_INTEN_TAERRIE BIT(12)
83 /* constants definitions */
84 /* signal free time */
85 #define CFG_SFT(regval) (BITS(0, 2) & ((regval) << 0U))
86 #define CEC_SFT_PROTOCOL_PERIOD CFG_SFT(0)
87 #define CEC_SFT_1POINT5_PERIOD CFG_SFT(1)
88 #define CEC_SFT_2POINT5_PERIOD CFG_SFT(2)
89 #define CEC_SFT_3POINT5_PERIOD CFG_SFT(3)
90 #define CEC_SFT_4POINT5_PERIOD CFG_SFT(4)
91 #define CEC_SFT_5POINT5_PERIOD CFG_SFT(5)
92 #define CEC_SFT_6POINT5_PERIOD CFG_SFT(6)
93 #define CEC_SFT_7POINT5_PERIOD CFG_SFT(7)
95 /* signal free time start option */
96 #define CEC_SFT_START_STAOM ((uint32_t)0x00000000U)
97 #define CEC_SFT_START_LAST CEC_CFG_SFTOPT
99 /* own address */
100 #define CEC_OWN_ADDRESS_CLEAR ((uint32_t)0x00000000U)
101 #define CEC_OWN_ADDRESS0 BIT(16)
102 #define CEC_OWN_ADDRESS1 BIT(17)
103 #define CEC_OWN_ADDRESS2 BIT(18)
104 #define CEC_OWN_ADDRESS3 BIT(19)
105 #define CEC_OWN_ADDRESS4 BIT(20)
106 #define CEC_OWN_ADDRESS5 BIT(21)
107 #define CEC_OWN_ADDRESS6 BIT(22)
108 #define CEC_OWN_ADDRESS7 BIT(23)
109 #define CEC_OWN_ADDRESS8 BIT(24)
110 #define CEC_OWN_ADDRESS9 BIT(25)
111 #define CEC_OWN_ADDRESS10 BIT(26)
112 #define CEC_OWN_ADDRESS11 BIT(27)
113 #define CEC_OWN_ADDRESS12 BIT(28)
114 #define CEC_OWN_ADDRESS13 BIT(29)
115 #define CEC_OWN_ADDRESS14 BIT(30)
117 /* error-bit generate */
118 #define CEC_BROADCAST_ERROR_BIT_ON ((uint32_t)0x00000000U)
119 #define CEC_BROADCAST_ERROR_BIT_OFF CEC_CFG_BCNG
120 #define CEC_LONG_PERIOD_ERROR_BIT_OFF ((uint32_t)0x00000000U)
121 #define CEC_LONG_PERIOD_ERROR_BIT_ON CEC_CFG_BPLEG
122 #define CEC_RISING_PERIOD_ERROR_BIT_OFF ((uint32_t)0x00000000U)
123 #define CEC_RISING_PERIOD_ERROR_BIT_ON CEC_CFG_BREG
125 /* whether stop receive message when detected bit rising error */
126 #define CEC_STOP_RISING_ERROR_BIT_ON ((uint32_t)0x00000000U)
127 #define CEC_STOP_RISING_ERROR_BIT_OFF ((uint32_t)0x00000001U)
129 /* flag bits */
130 #define CEC_FLAG_BR CEC_INTF_BR
131 #define CEC_FLAG_REND CEC_INTF_REND
132 #define CEC_FLAG_RO CEC_INTF_RO
133 #define CEC_FLAG_BRE CEC_INTF_BRE
134 #define CEC_FLAG_BPSE CEC_INTF_BPSE
135 #define CEC_FLAG_BPLE CEC_INTF_BPLE
136 #define CEC_FLAG_RAE CEC_INTF_RAE
137 #define CEC_FLAG_ARBF CEC_INTF_ARBF
138 #define CEC_FLAG_TBR CEC_INTF_TBR
139 #define CEC_FLAG_TEND CEC_INTF_TEND
140 #define CEC_FLAG_TU CEC_INTF_TU
141 #define CEC_FLAG_TERR CEC_INTF_TERR
142 #define CEC_FLAG_TAERR CEC_INTF_TAERR
144 /* interrupt flag bits */
145 #define CEC_INT_FLAG_BR CEC_INTF_BR
146 #define CEC_INT_FLAG_REND CEC_INTF_REND
147 #define CEC_INT_FLAG_RO CEC_INTF_RO
148 #define CEC_INT_FLAG_BRE CEC_INTF_BRE
149 #define CEC_INT_FLAG_BPSE CEC_INTF_BPSE
150 #define CEC_INT_FLAG_BPLE CEC_INTF_BPLE
151 #define CEC_INT_FLAG_RAE CEC_INTF_RAE
152 #define CEC_INT_FLAG_ARBF CEC_INTF_ARBF
153 #define CEC_INT_FLAG_TBR CEC_INTF_TBR
154 #define CEC_INT_FLAG_TEND CEC_INTF_TEND
155 #define CEC_INT_FLAG_TU CEC_INTF_TU
156 #define CEC_INT_FLAG_TERR CEC_INTF_TERR
157 #define CEC_INT_FLAG_TAERR CEC_INTF_TAERR
159 /* interrupt enable bits */
160 #define CEC_INT_BR CEC_INTEN_BRIE
161 #define CEC_INT_REND CEC_INTEN_RENDIE
162 #define CEC_INT_RO CEC_INTEN_ROIE
163 #define CEC_INT_BRE CEC_INTEN_BREIE
164 #define CEC_INT_BPSE CEC_INTEN_BPSEIE
165 #define CEC_INT_BPLE CEC_INTEN_BPLEIE
166 #define CEC_INT_RAE CEC_INTEN_RAEIE
167 #define CEC_INT_ARBF CEC_INTEN_ARBFIE
168 #define CEC_INT_TBR CEC_INTEN_TBRIE
169 #define CEC_INT_TEND CEC_INTEN_TENDIE
170 #define CEC_INT_TU CEC_INTEN_TUIE
171 #define CEC_INT_TERR CEC_INTEN_TERRIE
172 #define CEC_INT_TAERR CEC_INTEN_TAERRIE
174 /* function declarations */
175 /* reset HDMI-CEC controller */
176 void cec_deinit(void);
177 /* configure signal free time,the signal free time counter start option,own address */
178 void cec_init(uint32_t sftmopt, uint32_t sft, uint32_t address);
179 /* configure generate Error-bit, whether stop receive message when detected bit rising error */
180 void cec_error_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre, uint32_t rxbrestp);
181 /* enable HDMI-CEC controller */
182 void cec_enable(void);
183 /* disable HDMI-CEC controller */
184 void cec_disable(void);
185
186 /* start CEC message transmission */
187 void cec_transmission_start(void);
188 /* end CEC message transmission */
189 void cec_transmission_end(void);
190 /* enable CEC listen mode */
191 void cec_listen_mode_enable(void);
192 /* disable CEC listen mode */
193 void cec_listen_mode_disable(void);
194 /* configure and clear own address */
195 void cec_own_address_config(uint32_t address);
196 /* configure signal free time and the signal free time counter start option */
197 void cec_sft_config(uint32_t sftmopt,uint32_t sft);
198 /* configure generate Error-bit when detected some abnormal situation or not */
199 void cec_generate_errorbit_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre);
200 /* whether stop receive message when detected bit rising error */
201 void cec_stop_receive_bre_config(uint32_t rxbrestp);
202 /* enable reception bit timing tolerance */
203 void cec_reception_tolerance_enable(void);
204 /* disable reception bit timing tolerance */
205 void cec_reception_tolerance_disable(void);
206 /* send a data by the CEC peripheral */
207 void cec_data_send(uint8_t data);
208 /* receive a data by the CEC peripheral */
209 uint8_t cec_data_receive(void);
210
211 /* clear CEC int flag and status */
212 FlagStatus cec_interrupt_flag_get(uint32_t flag);
213 /* clear CEC flag */
214 void cec_interrupt_flag_clear(uint32_t flag);
215 /* enable interrupt */
216 void cec_interrupt_enable(uint32_t flag);
217 /* disable interrupt */
218 void cec_interrupt_disable(uint32_t flag);
219 /* get CEC status */
220 FlagStatus cec_flag_get(uint32_t flag);
221 /* clear CEC status */
222 void cec_flag_clear(uint32_t flag);
223
224 #endif /* GD32F3X0_CEC_H */
225
226 #endif /* GD32F350 */
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbh_int.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
usbh_int.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "usb_core.h"
13 #include "usb_defines.h"
14 #include "usbh_int.h"
15
16 static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev);
17 static uint32_t usbh_intf_port (usb_core_handle_struct *pudev);
18 static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev);
19 static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num);
20 static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num);
21 static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev);
22 static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev);
23 static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev);
24 static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev);
25 static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev);
26
33 uint32_t usbh_isr (usb_core_handle_struct *pudev)
34 {
35 uint32_t retval = 0U;
36 uint32_t int_flag = 0U;
37
38 /* check if host mode */
39 if (USB_CURRENT_MODE_GET() == HOST_MODE) {
40 USB_CORE_INTR_READ(int_flag);
41
42 if (!int_flag) {
43 return 0U;
44 }
45
46 /* start of frame interrupt handle */
47 if (int_flag & GINTF_SOF) {
48 retval |= usbh_intf_sof (pudev);
49 }
50
51 /* Rx FIFO non-empty interrupt handle */
52 if (int_flag & GINTF_RXFNEIF) {
53 retval |= usbh_intf_rxfifo_noempty (pudev);
54 }
55
56 /* Non-Periodic Tx FIFO empty interrupt hanlde */
57 if (int_flag & GINTF_NPTXFEIF) {
58 retval |= usbh_intf_nptxfifo_empty (pudev);
59 }
60
61 /* periodic Tx FIFO empty interrupt handle */
62 if (int_flag & GINTF_PTXFEIF) {
63 retval |= usbh_intf_ptxfifo_empty (pudev);
64 }
65
66 /* host channels interrupt handle */
67 if (int_flag & GINTF_HCIF) {
68 retval |= usbh_intf_hc (pudev);
69 }
70
71 /* host port interrupt handle */
72 if (int_flag & GINTF_HPIF) {
73 retval |= usbh_intf_port (pudev);
74 }
75
76 /* disconnect interrupt handle */
77 if (int_flag & GINTF_DISCIF) {
78 retval |= usbh_intf_disconnect (pudev);
79 }
80
81 /* isochronous IN transfer not complete interrupt handle */
82 if (int_flag & GINTF_ISOONCIF) {
83 retval |= usbh_intf_iso_incomplete_xfer (pudev);
84 }
85 }
86
87 return retval;
88 }
89
96 static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev)
97 {
98 usbh_hcd_int_fops->sof(pudev);
99
100 /* clear interrupt */
101 USB_GINTF = GINTF_SOF;
102
103 return 1U;
104 }
105
112 static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev)
113 {
114 uint8_t i = 0U;
115 uint32_t retval = 0U;
116
117 for (i = 0U; i < pudev->cfg.host_channel_num; i++) {
118 if ((USB_HACHINT & HACHINT_HACHINT) & ((uint32_t)1U << i)) {
119 if ((USB_HCHxCTL((uint16_t)i) & HCHCTL_EPDIR) >> 15U) {
120 retval |= usbh_intf_hc_in (pudev, i);
121 } else {
122 retval |= usbh_intf_hc_out (pudev, i);
123 }
124 }
125 }
126
127 return retval;
128 }
129
136 static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev)
137 {
138 usbh_hcd_int_fops->device_disconnected(pudev);
139
140 /* clear interrupt */
141 USB_GINTF = GINTF_DISCIF;
142
143 return 1U;
144 }
145
152 static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev)
153 {
154 uint8_t channel_num = 0U;
155 uint32_t dword_len = 0U, len = 0U;
156 usb_hostchannel_struct *puhc;
157
158 channel_num = (uint8_t)((USB_HNPTFQSTAT & HNPTFQSTAT_CNUM) >> 27U);
159 puhc = &pudev->host.host_channel[channel_num];
160 dword_len = (puhc->xfer_len + 3U) / 4U;
161
162 while (((USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) > dword_len) && (0U != puhc->xfer_len)) {
163 len = (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) * 4U;
164
165 if (len > puhc->xfer_len) {
166 /* last packet */
167 len = (uint16_t)puhc->xfer_len;
168
169 USB_GINTEN &= ~GINTF_NPTXFEIF;
170
171 }
172
173 dword_len = (puhc->xfer_len + 3U) / 4U;
174 usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len);
175
176 puhc->xfer_buff += len;
177 puhc->xfer_len -= len;
178 puhc->xfer_count += len;
179 }
180
181 return 1U;
182 }
183
190 static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev)
191 {
192 uint8_t channel_num = 0U;
193 uint32_t dword_len = 0U, len = 0U;
194 usb_hostchannel_struct *puhc;
195
196 channel_num = (uint8_t)((USB_HPTFQSTAT & HPTFQSTAT_CNUM) >> 27U);
197 puhc = &pudev->host.host_channel[channel_num];
198 dword_len = (puhc->xfer_len + 3U) / 4U;
199
200 while (((USB_HPTFQSTAT & HPTFQSTAT_PTXFS) > dword_len) && (0U != puhc->xfer_len)) {
201 len = (USB_HPTFQSTAT & HPTFQSTAT_PTXFS) * 4U;
202
203 if (len > puhc->xfer_len) {
204 len = puhc->xfer_len;
205
206 /* last packet */
207 USB_GINTEN &= ~GINTF_PTXFEIF;
208 }
209
210 dword_len = (puhc->xfer_len + 3U) / 4U;
211 usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len);
212
213 puhc->xfer_buff += len;
214 puhc->xfer_len -= len;
215 puhc->xfer_count += len;
216 }
217
218 return 1U;
219 }
220
227 static uint32_t usbh_intf_port (usb_core_handle_struct *pudev)
228 {
229 uint8_t port_speed = 0U;
230 uint8_t port_reset = 0U;
231 uint32_t retval = 0U;
232 __IO uint32_t hostportdup = USB_HPCS;
233
234 /* clear the interrupt bits in gintsts */
235 hostportdup &= ~HPCS_PE;
236 hostportdup &= ~HPCS_PCD;
237 hostportdup &= ~HPCS_PEDC;
238
239 /* port connect detected */
240 if (USB_HPCS & HPCS_PCD) {
241 hostportdup |= HPCS_PCD;
242 usbh_hcd_int_fops->device_connected(pudev);
243 retval |= 1U;
244 }
245
246 /* port enable changed */
247 if (USB_HPCS & HPCS_PEDC) {
248 hostportdup |= HPCS_PEDC;
249
250 if (USB_HPCS & HPCS_PE) {
251 port_speed = (uint8_t)((USB_HPCS & HPCS_PS) >> 17U);
252
253 if (HPRT_PRTSPD_LOW_SPEED == port_speed) {
254 USB_HFT = 6000U;
255
256 if (HCTLR_6_MHZ != (USB_HCTL & HCTL_CLKSEL)) {
257 if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) {
258 USB_FSLSCLOCK_INIT(HCTLR_6_MHZ);
259 }
260 port_reset = 1U;
261 }
262 } else if(HPRT_PRTSPD_FULL_SPEED == port_speed) {
263 USB_HFT = 48000U;
264
265 if (HCTLR_48_MHZ != (USB_HCTL & HCTL_CLKSEL)) {
266 if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) {
267 USB_FSLSCLOCK_INIT(HCTLR_48_MHZ);
268 }
269 port_reset = 1U;
270 }
271 } else {
272 /* for high speed device and others */
273 port_reset = 1U;
274 }
275 }
276 }
277
278 if (port_reset) {
279 usb_port_reset(pudev);
280 }
281
282 /* clear port interrupts */
283 USB_HPCS = hostportdup;
284
285 return retval;
286 }
287
295 static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num)
296 {
297 uint32_t channel_intr = USB_HCHxINTF((uint16_t)channel_num);
298 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
299
300 channel_intr &= USB_HCHxINTEN((uint16_t)channel_num);
301
302 if (channel_intr & HCHINTF_ACK) {
303 if (URB_PING == puhc->urb_state) {
304 puhc->err_count = 0U;
305 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
306 usb_hostchannel_halt(pudev, channel_num);
307 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF;
308 puhc->status = HC_XF;
309 }
310
311 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK;
312 } else if (channel_intr & HCHINTF_REQOVR) {
313 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
314 usb_hostchannel_halt(pudev, channel_num);
315 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR;
316 } else if (channel_intr & HCHINTF_TF) {
317 puhc->err_count = 0U;
318 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
319 usb_hostchannel_halt(pudev, channel_num);
320 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF;
321 puhc->status = HC_XF;
322 } else if (channel_intr & HCHINTF_STALL) {
323 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
324 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL;
325 usb_hostchannel_halt(pudev, channel_num);
326 puhc->status = HC_STALL;
327 } else if (channel_intr & HCHINTF_NAK) {
328 puhc->err_count = 0U;
329 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
330 usb_hostchannel_halt(pudev, channel_num);
331 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK;
332 puhc->status = HC_NAK;
333 } else if (channel_intr & HCHINTF_USBER) {
334 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
335 usb_hostchannel_halt(pudev, channel_num);
336 puhc->err_count ++;
337 puhc->status = HC_TRACERR;
338 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER;
339 } else if (channel_intr & HCHINTF_NYET) {
340 puhc->err_count = 0U;
341 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
342 puhc->status = HC_NYET;
343 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NYET;
344 } else if (channel_intr & HCHINTF_DTER) {
345 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
346 usb_hostchannel_halt(pudev, channel_num);
347 puhc->status= HC_DTGERR;
348 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER;
349 } else if (channel_intr & HCHINTF_CH) {
350 USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE;
351
352 switch (puhc->status) {
353 case HC_XF:
354 puhc->urb_state = URB_DONE;
355
356 if (USB_EPTYPE_BULK == ((USB_HCHxCTL((uint16_t)channel_num) & HCHCTL_EPTYPE) >> 18)) {
357 puhc->data_tg_out ^= 1U;
358 }
359 break;
360 case HC_NAK:
361 puhc->urb_state = URB_NOTREADY;
362 break;
363 case HC_NYET:
364 break;
365 case HC_STALL:
366 puhc->urb_state = URB_STALL;
367 break;
368 case HC_TRACERR:
369 if (3U == puhc->err_count) {
370 puhc->urb_state = URB_ERROR;
371 puhc->err_count = 0U;
372 }
373 break;
374 default:
375 break;
376 }
377
378 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH;
379 } else {
380 /* no operation */
381 }
382
383 return 1U;
384 }
385
393 static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num)
394 {
395 uint8_t endp_type = 0U;
396 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
397
398 uint32_t channle_intf = USB_HCHxINTF((uint16_t)channel_num);
399 __IO uint32_t channel_ctrl = USB_HCHxCTL((uint16_t)channel_num);
400
401 channle_intf &= USB_HCHxINTEN((uint16_t)channel_num);
402
403 endp_type = (uint8_t)((channel_ctrl & HCHCTL_EPTYPE) >> 18U);
404
405 if (channle_intf & HCHINTF_ACK) {
406 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK;
407 } else if (channle_intf & HCHINTF_STALL) {
408 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
409 puhc->status = HC_STALL;
410 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK;
411 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL;
412
413 /* NOTE: When there is a 'stall', reset also nak,
414 else, the pudev->host.status = HC_STALL
415 will be overwritten by 'nak' in code below */
416 channle_intf &= ~HCHINTF_NAK;
417
418 usb_hostchannel_halt(pudev, channel_num);
419 } else if (channle_intf & HCHINTF_DTER) {
420 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
421 usb_hostchannel_halt(pudev, channel_num);
422 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK;
423 puhc->status = HC_DTGERR;
424 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER;
425 } else {
426 /* no operation */
427 }
428
429 if (channle_intf & HCHINTF_REQOVR) {
430 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
431 usb_hostchannel_halt(pudev, channel_num);
432 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR;
433 } else if (channle_intf & HCHINTF_TF) {
434 puhc->status = HC_XF;
435 puhc->err_count = 0U;
436 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF;
437
438 if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) {
439 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
440 usb_hostchannel_halt(pudev, channel_num);
441 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK;
442 puhc->data_tg_in ^= 1U;
443 } else if (USB_EPTYPE_INTR == endp_type) {
444 channel_ctrl |= HCHCTL_ODDFRM;
445 USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl;
446 puhc->urb_state = URB_DONE;
447 } else {
448 /* no operation */
449 }
450 } else if (channle_intf & HCHINTF_CH) {
451 USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE;
452
453 switch (puhc->status) {
454 case HC_XF:
455 puhc->urb_state = URB_DONE;
456 break;
457 case HC_TRACERR:
458 case HC_DTGERR:
459 puhc->err_count = 0U;
460 puhc->urb_state = URB_ERROR;
461 break;
462 case HC_STALL:
463 puhc->urb_state = URB_STALL;
464 break;
465 default:
466 if (USB_EPTYPE_INTR == endp_type) {
467 puhc->data_tg_in ^= 1U;
468 }
469 break;
470 }
471
472 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH;
473 } else if (channle_intf & HCHINTF_USBER) {
474 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
475 (puhc->err_count)++;
476 puhc->status = HC_TRACERR;
477 usb_hostchannel_halt(pudev, channel_num);
478 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER;
479 } else if (channle_intf & HCHINTF_NAK) {
480 if (USB_EPTYPE_INTR == endp_type) {
481 USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE;
482 usb_hostchannel_halt(pudev, channel_num);
483 } else if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) {
484 /* re-activate the channel */
485 channel_ctrl |= HCHCTL_CEN;
486 channel_ctrl &= ~HCHCTL_CDIS;
487 USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl;
488 } else {
489 /* no operation */
490 }
491
492 puhc->status = HC_NAK;
493 USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK;
494 } else {
495 /* no operation */
496 }
497
498 return 1U;
499 }
500
507 static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev)
508 {
509 uint32_t count = 0U;
510 __IO uint8_t channel_num = 0U;
511 __IO uint32_t rx_status = 0U;
512 uint32_t usbh_ch_ctl_reg = 0U;
513 usb_hostchannel_struct *puhc;
514
515 /* disable the Rx status queue level interrupt */
516 USB_GINTEN &= ~GINTF_RXFNEIF;
517
518 rx_status = USB_GRSTATP;
519 channel_num = (uint8_t)(rx_status & GRSTATRP_CNUM);
520 puhc = &pudev->host.host_channel[channel_num];
521
522 switch ((rx_status & GRSTATRP_RPCKST) >> 17) {
523 case GRSTATR_RPCKST_IN:
524 count = (rx_status & GRSTATRP_BCOUNT) >> 4;
525
526 /* read the data into the host buffer. */
527 if ((count > 0U) && (puhc->xfer_buff != (void *)0)) {
528 usb_fifo_read(puhc->xfer_buff, (uint16_t)count);
529
530 /* manage multiple Xfer */
531 puhc->xfer_buff += count;
532 puhc->xfer_count += count;
533
534 if (USB_HCHxLEN((uint16_t)channel_num) & HCHLEN_PCNT) {
535 /* re-activate the channel when more packets are expected */
536 usbh_ch_ctl_reg = USB_HCHxCTL((uint16_t)channel_num);
537 usbh_ch_ctl_reg |= HCHCTL_CEN;
538 usbh_ch_ctl_reg &= ~HCHCTL_CDIS;
539 USB_HCHxCTL((uint16_t)channel_num) = usbh_ch_ctl_reg;
540 }
541 }
542 break;
543 case GRSTATR_RPCKST_IN_XFER_COMP:
544 case GRSTATR_RPCKST_DATA_TOGGLE_ERR:
545 case GRSTATR_RPCKST_CH_HALTED:
546 default:
547 break;
548 }
549
550 /* enable the Rx status queue level interrupt */
551 USB_GINTEN |= GINTF_RXFNEIF;
552
553 return 1U;
554 }
555
562 static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev)
563 {
564 __IO uint32_t gint_flag = 0U;
565
566 gint_flag = USB_HCHxCTL(0U);
567 USB_HCHxCTL(0U) = 0U;
568
569 gint_flag = 0U;
570
571 /* clear interrupt */
572 gint_flag |= GINTF_ISOONCIF;
573 USB_GINTF = gint_flag;
574
575 return 1U;
576 }
USB_CORE_INTR_READ
#define USB_CORE_INTR_READ(x)
Definition: usb_regs.h:551
HC_NYET
Definition: usb_core.h:40
HPCS_PS
#define HPCS_PS
Definition: usb_regs.h:271
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:48
HC_XF
Definition: usb_core.h:37
usb_fifo_read
void * usb_fifo_read(uint8_t *dest, uint16_t len)
read a packet from the Rx FIFO associated with the endpoint
Definition: usb_core.c:102
URB_STALL
Definition: usb_core.h:54
HCHINTF_ACK
#define HCHINTF_ACK
Definition: usb_regs.h:307
USB_FSLSCLOCK_INIT
#define USB_FSLSCLOCK_INIT(ClockFreq)
Definition: usb_regs.h:614
usb_hostchannel_struct::urb_state
urb_state_enum urb_state
Definition: usb_core.h:172
GINTF_RXFNEIF
#define GINTF_RXFNEIF
Definition: usb_regs.h:165
HPRT_PRTSPD_LOW_SPEED
#define HPRT_PRTSPD_LOW_SPEED
Definition: usb_defines.h:75
HCHINTF_CH
#define HCHINTF_CH
Definition: usb_regs.h:311
HPCS_PE
#define HPCS_PE
Definition: usb_regs.h:278
usb_hostchannel_struct::status
hc_status_enum status
Definition: usb_core.h:171
HCHINTF_NAK
#define HCHINTF_NAK
Definition: usb_regs.h:308
HCHCTL_CDIS
#define HCHCTL_CDIS
Definition: usb_regs.h:284
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:165
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:175
HPTFQSTAT_CNUM
#define HPTFQSTAT_CNUM
Definition: usb_regs.h:259
URB_PING
Definition: usb_core.h:55
HNPTFQSTAT_NPTXFS
#define HNPTFQSTAT_NPTXFS
Definition: usb_regs.h:219
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:54
usbh_isr
uint32_t usbh_isr(usb_core_handle_struct *pudev)
handle global host interrupt
Definition: usbh_int.c:33
USB_GINTEN
#define USB_GINTEN
Definition: usb_regs.h:41
USB_HFT
#define USB_HFT
Definition: usb_regs.h:54
HCHINTF_USBER
#define HCHINTF_USBER
Definition: usb_regs.h:305
usb_fifo_write
usb_status_enum usb_fifo_write(uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint
Definition: usb_core.c:79
HPCS_PEDC
#define HPCS_PEDC
Definition: usb_regs.h:277
USB_HNPTFQSTAT
#define USB_HNPTFQSTAT
Definition: usb_regs.h:47
USB_GINTF
#define USB_GINTF
Definition: usb_regs.h:40
USB_EPTYPE_CTRL
#define USB_EPTYPE_CTRL
Definition: usb_defines.h:51
USB_HCHxLEN
#define USB_HCHxLEN(x)
Definition: usb_regs.h:63
HNPTFQSTAT_CNUM
#define HNPTFQSTAT_CNUM
Definition: usb_regs.h:220
GRSTATRP_RPCKST
#define GRSTATRP_RPCKST
Definition: usb_regs.h:199
HCHCTL_EPTYPE
#define HCHCTL_EPTYPE
Definition: usb_regs.h:288
usbh_hcd_int_fops
usbh_hcd_int_cb_struct * usbh_hcd_int_fops
Definition: usbh_core.c:33
USB_HACHINT
#define USB_HACHINT
Definition: usb_regs.h:57
URB_NOTREADY
Definition: usb_core.h:52
usb_core_cfgs_struct::phy_interface
uint8_t phy_interface
Definition: usb_core.h:63
HCHINTF_DTER
#define HCHINTF_DTER
Definition: usb_regs.h:302
usb_hostchannel_struct::err_count
uint32_t err_count
Definition: usb_core.h:169
usb_hostchannel_struct
Definition: usb_core.h:154
USB_CURRENT_MODE_GET
#define USB_CURRENT_MODE_GET()
Definition: usb_regs.h:548
USB_HCHxINTF
#define USB_HCHxINTF(x)
Definition: usb_regs.h:61
HPCS_PCD
#define HPCS_PCD
Definition: usb_regs.h:279
HCHINTEN_CHIE
#define HCHINTEN_CHIE
Definition: usb_regs.h:324
USB_CORE_EMBEDDED_PHY
#define USB_CORE_EMBEDDED_PHY
Definition: usb_defines.h:35
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:174
GRSTATR_RPCKST_IN
#define GRSTATR_RPCKST_IN
Definition: usb_defines.h:42
HC_TRACERR
Definition: usb_core.h:42
USB_GRSTATP
#define USB_GRSTATP
Definition: usb_regs.h:43
GRSTATR_RPCKST_DATA_TOGGLE_ERR
#define GRSTATR_RPCKST_DATA_TOGGLE_ERR
Definition: usb_defines.h:44
HC_NAK
Definition: usb_core.h:39
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:166
GINTF_HCIF
#define GINTF_HCIF
Definition: usb_regs.h:149
usbh_int.h
USB host mode interrupt handler header file.
usb_core.h
USB core driver header file.
USB_HCHxINTEN
#define USB_HCHxINTEN(x)
Definition: usb_regs.h:62
HC_STALL
Definition: usb_core.h:41
USB_HPTFQSTAT
#define USB_HPTFQSTAT
Definition: usb_regs.h:56
HCHCTL_ODDFRM
#define HCHCTL_ODDFRM
Definition: usb_regs.h:285
HCHCTL_EPDIR
#define HCHCTL_EPDIR
Definition: usb_regs.h:290
HACHINT_HACHINT
#define HACHINT_HACHINT
Definition: usb_regs.h:265
HCHCTL_CEN
#define HCHCTL_CEN
Definition: usb_regs.h:283
usbh_hcd_int_cb_struct::device_connected
uint8_t(* device_connected)(usb_core_handle_struct *pudev)
Definition: usbh_int.h:20
USB_HCHxCTL
#define USB_HCHxCTL(x)
Definition: usb_regs.h:60
HCHINTF_TF
#define HCHINTF_TF
Definition: usb_regs.h:312
usb_core_handle_struct
Definition: usb_core.h:200
URB_ERROR
Definition: usb_core.h:53
usb_defines.h
USB core defines.
HPRT_PRTSPD_FULL_SPEED
#define HPRT_PRTSPD_FULL_SPEED
Definition: usb_defines.h:74
GINTF_HPIF
#define GINTF_HPIF
Definition: usb_regs.h:150
USB_HCTL
#define USB_HCTL
Definition: usb_regs.h:53
HCHINTF_REQOVR
#define HCHINTF_REQOVR
Definition: usb_regs.h:303
HCHLEN_PCNT
#define HCHLEN_PCNT
Definition: usb_regs.h:330
HCHINTF_STALL
#define HCHINTF_STALL
Definition: usb_regs.h:309
HC_DTGERR
Definition: usb_core.h:44
GRSTATRP_BCOUNT
#define GRSTATRP_BCOUNT
Definition: usb_regs.h:201
GRSTATR_RPCKST_CH_HALTED
#define GRSTATR_RPCKST_CH_HALTED
Definition: usb_defines.h:45
USB_HPCS
#define USB_HPCS
Definition: usb_regs.h:59
GINTF_NPTXFEIF
#define GINTF_NPTXFEIF
Definition: usb_regs.h:164
GINTF_ISOONCIF
#define GINTF_ISOONCIF
Definition: usb_regs.h:152
HPTFQSTAT_PTXFS
#define HPTFQSTAT_PTXFS
Definition: usb_regs.h:257
HCTL_CLKSEL
#define HCTL_CLKSEL
Definition: usb_regs.h:245
usb_core_cfgs_struct::host_channel_num
uint8_t host_channel_num
Definition: usb_core.h:64
usbh_hcd_int_cb_struct::sof
uint8_t(* sof)(usb_core_handle_struct *pudev)
Definition: usbh_int.h:19
usbh_hcd_int_cb_struct::device_disconnected
uint8_t(* device_disconnected)(usb_core_handle_struct *pudev)
Definition: usbh_int.h:21
GINTF_PTXFEIF
#define GINTF_PTXFEIF
Definition: usb_regs.h:148
GINTF_SOF
#define GINTF_SOF
Definition: usb_regs.h:166
GRSTATR_RPCKST_IN_XFER_COMP
#define GRSTATR_RPCKST_IN_XFER_COMP
Definition: usb_defines.h:43
URB_DONE
Definition: usb_core.h:51
usb_hostchannel_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:167
HCTLR_48_MHZ
#define HCTLR_48_MHZ
Definition: usb_defines.h:78
GINTF_DISCIF
#define GINTF_DISCIF
Definition: usb_regs.h:146
GRSTATRP_CNUM
#define GRSTATRP_CNUM
Definition: usb_regs.h:202
HCHINTF_NYET
#define HCHINTF_NYET
Definition: usb_regs.h:306
HCTLR_6_MHZ
#define HCTLR_6_MHZ
Definition: usb_defines.h:79
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:202
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:53
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_gpio.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_gpio.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_gpio.h"
13
20 void gpio_deinit(uint32_t gpio_periph)
21 {
22 switch(gpio_periph){
23 case GPIOA:
24 /* reset GPIOA */
25 rcu_periph_reset_enable(RCU_GPIOARST);
26 rcu_periph_reset_disable(RCU_GPIOARST);
27 break;
28 case GPIOB:
29 /* reset GPIOB */
30 rcu_periph_reset_enable(RCU_GPIOBRST);
31 rcu_periph_reset_disable(RCU_GPIOBRST);
32 break;
33 case GPIOC:
34 /* reset GPIOC */
35 rcu_periph_reset_enable(RCU_GPIOCRST);
36 rcu_periph_reset_disable(RCU_GPIOCRST);
37 break;
38 case GPIOD:
39 /* reset GPIOD */
40 rcu_periph_reset_enable(RCU_GPIODRST);
41 rcu_periph_reset_disable(RCU_GPIODRST);
42 break;
43 case GPIOF:
44 /* reset GPIOF */
45 rcu_periph_reset_enable(RCU_GPIOFRST);
46 rcu_periph_reset_disable(RCU_GPIOFRST);
47 break;
48 default:
49 break;
50 }
51 }
52
69 void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin)
70 {
71 uint16_t i;
72 uint32_t ctl, pupd;
73
74 ctl = GPIO_CTL(gpio_periph);
75 pupd = GPIO_PUD(gpio_periph);
76
77 for(i = 0U;i < 16U;i++){
78 if((1U << i) & pin){
79 /* clear the specified pin mode bits */
80 ctl &= ~GPIO_MODE_MASK(i);
81 /* set the specified pin mode bits */
82 ctl |= GPIO_MODE_SET(i, mode);
83
84 /* clear the specified pin pupd bits */
85 pupd &= ~GPIO_PUPD_MASK(i);
86 /* set the specified pin pupd bits */
87 pupd |= GPIO_PUPD_SET(i, pull_up_down);
88 }
89 }
90
91 GPIO_CTL(gpio_periph) = ctl;
92 GPIO_PUD(gpio_periph) = pupd;
93 }
94
110 void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin)
111 {
112 uint16_t i;
113 uint32_t ospeed0,ospeed1;
114
115 if(GPIO_OTYPE_OD == otype){
116 GPIO_OMODE(gpio_periph) |= (uint32_t)pin;
117 }else{
118 GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin);
119 }
120
121 /* get the specified pin output speed bits value */
122 ospeed0 = GPIO_OSPD0(gpio_periph);
123
124 if(GPIO_OSPEED_MAX == speed){
125 ospeed1 = GPIO_OSPD1(gpio_periph);
126
127 for(i = 0U;i < 16U;i++){
128 if((1U << i) & pin){
129 /* enable very high output speed function of the pin when the corresponding OSPDy(y=0..15)
130 is "11" (output max speed 50MHz) */
131 ospeed0 |= GPIO_OSPEED_SET(i,0x03);
132 ospeed1 |= (1U << i);
133 }
134 }
135 GPIO_OSPD0(gpio_periph) = ospeed0;
136 GPIO_OSPD1(gpio_periph) = ospeed1;
137 }else{
138 for(i = 0U;i < 16U;i++){
139 if((1U << i) & pin){
140 /* clear the specified pin output speed bits */
141 ospeed0 &= ~GPIO_OSPEED_MASK(i);
142 /* set the specified pin output speed bits */
143 ospeed0 |= GPIO_OSPEED_SET(i,speed);
144 }
145 }
146 GPIO_OSPD0(gpio_periph) = ospeed0;
147 }
148 }
149
157 void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
158 {
159 GPIO_BOP(gpio_periph) = (uint32_t)pin;
160 }
161
169 void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
170 {
171 GPIO_BC(gpio_periph) = (uint32_t)pin;
172 }
173
184 void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
185 {
186 if(RESET != bit_value){
187 GPIO_BOP(gpio_periph) = (uint32_t)pin;
188 }else{
189 GPIO_BC(gpio_periph) = (uint32_t)pin;
190 }
191 }
192
200 void gpio_port_write(uint32_t gpio_periph, uint16_t data)
201 {
202 GPIO_OCTL(gpio_periph) = (uint32_t)data;
203 }
204
212 FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
213 {
214 if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){
215 return SET;
216 }else{
217 return RESET;
218 }
219 }
220
227 uint16_t gpio_input_port_get(uint32_t gpio_periph)
228 {
229 return (uint16_t)GPIO_ISTAT(gpio_periph);
230 }
231
239 FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
240 {
241 if((uint32_t)RESET != (GPIO_OCTL(gpio_periph)&(pin))){
242 return SET;
243 }else{
244 return RESET;
245 }
246 }
247
254 uint16_t gpio_output_port_get(uint32_t gpio_periph)
255 {
256 return (uint16_t)GPIO_OCTL(gpio_periph);
257 }
258
276 void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin)
277 {
278 uint16_t i;
279 uint32_t afrl, afrh;
280
281 afrl = GPIO_AFSEL0(gpio_periph);
282 afrh = GPIO_AFSEL1(gpio_periph);
283
284 for(i = 0U;i < 8U;i++){
285 if((1U << i) & pin){
286 /* clear the specified pin alternate function bits */
287 afrl &= ~GPIO_AFR_MASK(i);
288 afrl |= GPIO_AFR_SET(i,alt_func_num);
289 }
290 }
291
292 for(i = 8U;i < 16U;i++){
293 if((1U << i) & pin){
294 /* clear the specified pin alternate function bits */
295 afrh &= ~GPIO_AFR_MASK(i - 8U);
296 afrh |= GPIO_AFR_SET(i - 8U,alt_func_num);
297 }
298 }
299
300 GPIO_AFSEL0(gpio_periph) = afrl;
301 GPIO_AFSEL1(gpio_periph) = afrh;
302 }
303
311 void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
312 {
313 uint32_t lock = 0x00010000U;
314 lock |= pin;
315
316 /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */
317 GPIO_LOCK(gpio_periph) = (uint32_t)lock;
318 GPIO_LOCK(gpio_periph) = (uint32_t)pin;
319 GPIO_LOCK(gpio_periph) = (uint32_t)lock;
320 lock = GPIO_LOCK(gpio_periph);
321 lock = GPIO_LOCK(gpio_periph);
322 }
323
331 void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin)
332 {
333 GPIO_TG(gpio_periph) = (uint32_t)pin;
334 }
335
342 void gpio_port_toggle(uint32_t gpio_periph)
343 {
344 GPIO_TG(gpio_periph) = 0x0000FFFFU;
345 }
RCU_GPIOCRST
Definition: gd32f3x0_rcu.h:328
gpio_pin_lock
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
lock GPIO pin bit
Definition: gd32f3x0_gpio.c:311
GPIOB
#define GPIOB
Definition: gd32f3x0_gpio.h:19
GPIO_OSPEED_MAX
#define GPIO_OSPEED_MAX
Definition: gd32f3x0_gpio.h:331
RCU_GPIOBRST
Definition: gd32f3x0_rcu.h:327
GPIO_PUD
#define GPIO_PUD(gpiox)
Definition: gd32f3x0_gpio.h:28
gpio_mode_set
void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin)
set GPIO output mode
Definition: gd32f3x0_gpio.c:69
GPIOF
#define GPIOF
Definition: gd32f3x0_gpio.h:22
GPIO_OSPEED_SET
#define GPIO_OSPEED_SET(n, speed)
Definition: gd32f3x0_gpio.h:319
gpio_bit_reset
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
reset GPIO pin bit
Definition: gd32f3x0_gpio.c:169
GPIO_OSPEED_MASK
#define GPIO_OSPEED_MASK(n)
Definition: gd32f3x0_gpio.h:320
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
GPIO_TG
#define GPIO_TG(gpiox)
Definition: gd32f3x0_gpio.h:36
gpio_output_bit_get
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
get GPIO pin output status
Definition: gd32f3x0_gpio.c:239
GPIO_BC
#define GPIO_BC(gpiox)
Definition: gd32f3x0_gpio.h:35
gpio_bit_write
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
write data to the specified GPIO pin
Definition: gd32f3x0_gpio.c:184
GPIO_PUPD_SET
#define GPIO_PUPD_SET(n, pupd)
Definition: gd32f3x0_gpio.h:315
GPIO_OMODE
#define GPIO_OMODE(gpiox)
Definition: gd32f3x0_gpio.h:26
GPIO_PUPD_MASK
#define GPIO_PUPD_MASK(n)
Definition: gd32f3x0_gpio.h:316
GPIO_OCTL
#define GPIO_OCTL(gpiox)
Definition: gd32f3x0_gpio.h:30
gpio_af_set
void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin)
set GPIO alternate function
Definition: gd32f3x0_gpio.c:276
GPIO_CTL
#define GPIO_CTL(gpiox)
Definition: gd32f3x0_gpio.h:25
GPIOA
#define GPIOA
Definition: gd32f3x0_gpio.h:18
GPIO_ISTAT
#define GPIO_ISTAT(gpiox)
Definition: gd32f3x0_gpio.h:29
GPIO_AFR_MASK
#define GPIO_AFR_MASK(n)
Definition: gd32f3x0_gpio.h:335
GPIO_BOP
#define GPIO_BOP(gpiox)
Definition: gd32f3x0_gpio.h:31
GPIO_OTYPE_OD
#define GPIO_OTYPE_OD
Definition: gd32f3x0_gpio.h:324
gpio_output_options_set
void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin)
set GPIO output type and speed
Definition: gd32f3x0_gpio.c:110
GPIO_MODE_MASK
#define GPIO_MODE_MASK(n)
Definition: gd32f3x0_gpio.h:312
GPIO_OSPD0
#define GPIO_OSPD0(gpiox)
Definition: gd32f3x0_gpio.h:27
gpio_port_toggle
void gpio_port_toggle(uint32_t gpio_periph)
toggle GPIO port status
Definition: gd32f3x0_gpio.c:342
GPIOC
#define GPIOC
Definition: gd32f3x0_gpio.h:20
GPIO_AFR_SET
#define GPIO_AFR_SET(n, af)
Definition: gd32f3x0_gpio.h:334
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
GPIOD
#define GPIOD
Definition: gd32f3x0_gpio.h:21
RCU_GPIOARST
Definition: gd32f3x0_rcu.h:326
gd32f3x0_gpio.h
definitions for the GPIO
GPIO_MODE_SET
#define GPIO_MODE_SET(n, mode)
Definition: gd32f3x0_gpio.h:311
gpio_bit_set
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
set GPIO pin bit
Definition: gd32f3x0_gpio.c:157
gpio_port_write
void gpio_port_write(uint32_t gpio_periph, uint16_t data)
write data to the specified GPIO port
Definition: gd32f3x0_gpio.c:200
gpio_output_port_get
uint16_t gpio_output_port_get(uint32_t gpio_periph)
get GPIO all pins output status
Definition: gd32f3x0_gpio.c:254
GPIO_AFSEL0
#define GPIO_AFSEL0(gpiox)
Definition: gd32f3x0_gpio.h:33
gpio_input_port_get
uint16_t gpio_input_port_get(uint32_t gpio_periph)
get GPIO all pins input status
Definition: gd32f3x0_gpio.c:227
RCU_GPIODRST
Definition: gd32f3x0_rcu.h:329
gpio_bit_toggle
void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin)
toggle GPIO pin status
Definition: gd32f3x0_gpio.c:331
gpio_deinit
void gpio_deinit(uint32_t gpio_periph)
reset GPIO port
Definition: gd32f3x0_gpio.c:20
GPIO_OSPD1
#define GPIO_OSPD1(gpiox)
Definition: gd32f3x0_gpio.h:37
GPIO_AFSEL1
#define GPIO_AFSEL1(gpiox)
Definition: gd32f3x0_gpio.h:34
gpio_input_bit_get
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
get GPIO pin input status
Definition: gd32f3x0_gpio.c:212
GPIO_LOCK
#define GPIO_LOCK(gpiox)
Definition: gd32f3x0_gpio.h:32
bit_status
FlagStatus bit_status
Definition: gd32f3x0_gpio.h:276
RCU_GPIOFRST
Definition: gd32f3x0_rcu.h:330
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_syscfg.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_syscfg.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_SYSCFG_H
13 #define GD32F3X0_SYSCFG_H
14
15 #include "gd32f3x0.h"
16
17 /* SYSCFG definitions */
18 #define SYSCFG SYSCFG_BASE
19
20 /* registers definitions */
21 #define SYSCFG_CFG0 REG32(SYSCFG + 0x00U)
22 #define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U)
23 #define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU)
24 #define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U)
25 #define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U)
26 #define SYSCFG_CFG2 REG32(SYSCFG + 0x18U)
27 #define SYSCFG_CPSCTL REG32(SYSCFG + 0x20U)
29 /* SYSCFG_CFG0 bits definitions */
30 #define SYSCFG_CFG0_BOOT_MODE BITS(0,1)
31 #define SYSCFG_CFG0_ADC_DMA_RMP BIT(8)
32 #define SYSCFG_CFG0_USART0_TX_DMA_RMP BIT(9)
33 #define SYSCFG_CFG0_USART0_RX_DMA_RMP BIT(10)
34 #define SYSCFG_CFG0_TIMER15_DMA_RMP BIT(11)
35 #define SYSCFG_CFG0_TIMER16_DMA_RMP BIT(12)
36 #define SYSCFG_CFG0_PB9_HCCE BIT(19)
38 /* SYSCFG_EXTISS0 bits definitions */
39 #define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3)
40 #define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7)
41 #define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11)
42 #define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15)
44 /* SYSCFG_EXTISS1 bits definitions */
45 #define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3)
46 #define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7)
47 #define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11)
48 #define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15)
50 /* SYSCFG_EXTISS2 bits definitions */
51 #define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3)
52 #define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7)
53 #define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11)
54 #define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15)
56 /* SYSCFG_EXTISS3 bits definitions */
57 #define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3)
58 #define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7)
59 #define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11)
60 #define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15)
62 /* SYSCFG_CFG2 bits definitions */
63 #define SYSCFG_CFG2_LOCKUP_LOCK BIT(0)
64 #define SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK BIT(1)
65 #define SYSCFG_CFG2_LVD_LOCK BIT(2)
66 #define SYSCFG_CFG2_SRAM_PCEF BIT(8)
68 /* SYSCFG_CPSCTL bits definitions */
69 #define SYSCFG_CPSCTL_CPS_EN BIT(0)
70 #define SYSCFG_CPSCTL_CPS_RDY BIT(8)
72 /* constants definitions */
73 /* DMA remap definitions */
74 #define SYSCFG_DMA_REMAP_ADC SYSCFG_CFG0_ADC_DMA_RMP
75 #define SYSCFG_DMA_REMAP_USART0TX SYSCFG_CFG0_USART0_TX_DMA_RMP
76 #define SYSCFG_DMA_REMAP_USART0RX SYSCFG_CFG0_USART0_RX_DMA_RMP
77 #define SYSCFG_DMA_REMAP_TIMER15 SYSCFG_CFG0_TIMER15_DMA_RMP
78 #define SYSCFG_DMA_REMAP_TIMER16 SYSCFG_CFG0_TIMER16_DMA_RMP
80 /* high current definitions */
81 #define SYSCFG_HIGH_CURRENT_ENABLE SYSCFG_CFG0_PB9_HCCE
82 #define SYSCFG_HIGH_CURRENT_DISABLE (~SYSCFG_CFG0_PB9_HCCE)
84 /* EXTI source select definition */
85 #define EXTISS0 ((uint8_t)0x00U)
86 #define EXTISS1 ((uint8_t)0x01U)
87 #define EXTISS2 ((uint8_t)0x02U)
88 #define EXTISS3 ((uint8_t)0x03U)
90 /* EXTI source select mask bits definition */
91 #define EXTI_SS_MASK BITS(0,3)
93 /* EXTI source select jumping step definition */
94 #define EXTI_SS_JSTEP ((uint8_t)(0x04U))
96 /* EXTI source select moving step definition */
97 #define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP))
99 /* EXTI source port definitions */
100 #define EXTI_SOURCE_GPIOA ((uint8_t)0x00U)
101 #define EXTI_SOURCE_GPIOB ((uint8_t)0x01U)
102 #define EXTI_SOURCE_GPIOC ((uint8_t)0x02U)
103 #define EXTI_SOURCE_GPIOD ((uint8_t)0x03U)
104 #define EXTI_SOURCE_GPIOF ((uint8_t)0x05U)
106 /* EXTI source pin definitions */
107 #define EXTI_SOURCE_PIN0 ((uint8_t)0x00U)
108 #define EXTI_SOURCE_PIN1 ((uint8_t)0x01U)
109 #define EXTI_SOURCE_PIN2 ((uint8_t)0x02U)
110 #define EXTI_SOURCE_PIN3 ((uint8_t)0x03U)
111 #define EXTI_SOURCE_PIN4 ((uint8_t)0x04U)
112 #define EXTI_SOURCE_PIN5 ((uint8_t)0x05U)
113 #define EXTI_SOURCE_PIN6 ((uint8_t)0x06U)
114 #define EXTI_SOURCE_PIN7 ((uint8_t)0x07U)
115 #define EXTI_SOURCE_PIN8 ((uint8_t)0x08U)
116 #define EXTI_SOURCE_PIN9 ((uint8_t)0x09U)
117 #define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU)
118 #define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU)
119 #define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU)
120 #define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU)
121 #define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU)
122 #define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU)
124 /* lock definitions */
125 #define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK
126 #define SYSCFG_LOCK_SRAM_PARITY_ERROR SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK
127 #define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK
129 /* SRAM parity check error flag definitions */
130 #define SYSCFG_SRAM_PCEF SYSCFG_CFG2_SRAM_PCEF
132 /* I/O compensation cell enable/disable */
133 #define SYSCFG_COMPENSATION(regval) (BIT(0) & ((uint32_t)(regval) << 0))
134 #define SYSCFG_COMPENSATION_DISABLE SYSCFG_COMPENSATION(0)
135 #define SYSCFG_COMPENSATION_ENABLE SYSCFG_COMPENSATION(1)
137 /* function declarations */
138 /* deinit syscfg module */
139 void syscfg_deinit(void);
140
141 /* enable the DMA channels remapping */
142 void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap);
143 /* disable the DMA channels remapping */
144 void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap);
145
146 /* enable PB9 high current capability */
147 void syscfg_high_current_enable(void);
148 /* disable PB9 high current capability */
149 void syscfg_high_current_disable(void);
150
151 /* configure the GPIO pin as EXTI Line */
152 void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin);
153 /* connect TIMER0/14/15/16 break input to the selected parameter */
154 void syscfg_lock_config(uint32_t syscfg_lock);
155
156 /* check if the specified flag in SYSCFG_CFG2 is set or not */
157 FlagStatus syscfg_flag_get(uint32_t syscfg_flag);
158 /* clear the flag in SYSCFG_CFG2 by writing 1 */
159 void syscfg_flag_clear(uint32_t syscfg_flag);
160
161 /* configure the I/O compensation cell */
162 void syscfg_compensation_config(uint32_t syscfg_compensation);
163 /* check if the I/O compensation cell ready flag is set or not */
164 FlagStatus syscfg_cps_rdy_flag_get(void);
165
166 #endif /* GD32F3X0_SYSCFG_H */
syscfg_deinit
void syscfg_deinit(void)
reset the SYSCFG registers
Definition: gd32f3x0_syscfg.c:20
syscfg_flag_clear
void syscfg_flag_clear(uint32_t syscfg_flag)
clear the flag in SYSCFG_CFG2 by writing 1.
Definition: gd32f3x0_syscfg.c:161
syscfg_high_current_enable
void syscfg_high_current_enable(void)
enable PB9 high current capability
Definition: gd32f3x0_syscfg.c:64
syscfg_exti_line_config
void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin)
configure the GPIO pin as EXTI Line
Definition: gd32f3x0_syscfg.c:89
syscfg_cps_rdy_flag_get
FlagStatus syscfg_cps_rdy_flag_get(void)
check if the I/O compensation cell ready flag is set or not
Definition: gd32f3x0_syscfg.c:190
syscfg_dma_remap_enable
void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap)
enable the DMA channels remapping
Definition: gd32f3x0_syscfg.c:37
syscfg_compensation_config
void syscfg_compensation_config(uint32_t syscfg_compensation)
configure the I/O compensation cell
Definition: gd32f3x0_syscfg.c:174
syscfg_dma_remap_disable
void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap)
disable the DMA channels remapping
Definition: gd32f3x0_syscfg.c:53
syscfg_flag_get
FlagStatus syscfg_flag_get(uint32_t syscfg_flag)
check if the specified flag in SYSCFG_CFG2 is set or not.
Definition: gd32f3x0_syscfg.c:145
syscfg_high_current_disable
void syscfg_high_current_disable(void)
disable PB9 high current capability
Definition: gd32f3x0_syscfg.c:75
syscfg_lock_config
void syscfg_lock_config(uint32_t syscfg_lock)
connect TIMER0/14/15/16 break input to the selected parameter
Definition: gd32f3x0_syscfg.c:133
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_spi.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_spi.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_SPI_H
13 #define GD32F3X0_SPI_H
14
15 #include "gd32f3x0.h"
16
17 /* SPIx(x=0,1,2) definitions */
18 #define SPI0 (SPI_BASE + 0x0000F800U)
19 #define SPI1 SPI_BASE
20 #define SPI2 (SPI_BASE + 0x00000400U)
21
22 /* SPI registers definitions */
23 #define SPI_CTL0(spix) REG32((spix) + 0x00U)
24 #define SPI_CTL1(spix) REG32((spix) + 0x04U)
25 #define SPI_STAT(spix) REG32((spix) + 0x08U)
26 #define SPI_DATA(spix) REG32((spix) + 0x0CU)
27 #define SPI_CRCPOLY(spix) REG32((spix) + 0x10U)
28 #define SPI_RCRC(spix) REG32((spix) + 0x14U)
29 #define SPI_TCRC(spix) REG32((spix) + 0x18U)
30 #define SPI_I2SCTL(spix) REG32((spix) + 0x1CU)
31 #define SPI_I2SPSC(spix) REG32((spix) + 0x20U)
32 #define SPI_QCTL(spix) REG32((spix) + 0x80U)
34 /* bits definitions */
35 /* SPI_CTL0 */
36 #define SPI_CTL0_CKPH BIT(0)
37 #define SPI_CTL0_CKPL BIT(1)
38 #define SPI_CTL0_MSTMOD BIT(2)
39 #define SPI_CTL0_PSC BITS(3,5)
40 #define SPI_CTL0_SPIEN BIT(6)
41 #define SPI_CTL0_LF BIT(7)
42 #define SPI_CTL0_SWNSS BIT(8)
43 #define SPI_CTL0_SWNSSEN BIT(9)
44 #define SPI_CTL0_RO BIT(10)
45 #define SPI_CTL0_FF16 BIT(11)
46 #define SPI_CTL0_CRCNT BIT(12)
47 #define SPI_CTL0_CRCEN BIT(13)
48 #define SPI_CTL0_BDOEN BIT(14)
49 #define SPI_CTL0_BDEN BIT(15)
51 /* SPI_CTL1 */
52 #define SPI_CTL1_DMAREN BIT(0)
53 #define SPI_CTL1_DMATEN BIT(1)
54 #define SPI_CTL1_NSSDRV BIT(2)
55 #define SPI_CTL1_NSSP BIT(3)
56 #define SPI_CTL1_TMOD BIT(4)
57 #define SPI_CTL1_ERRIE BIT(5)
58 #define SPI_CTL1_RBNEIE BIT(6)
59 #define SPI_CTL1_TBEIE BIT(7)
61 /* SPI_STAT */
62 #define SPI_STAT_RBNE BIT(0)
63 #define SPI_STAT_TBE BIT(1)
64 #define SPI_STAT_I2SCH BIT(2)
65 #define SPI_STAT_TXURERR BIT(3)
66 #define SPI_STAT_CRCERR BIT(4)
67 #define SPI_STAT_CONFERR BIT(5)
68 #define SPI_STAT_RXORERR BIT(6)
69 #define SPI_STAT_TRANS BIT(7)
70 #define SPI_STAT_FERR BIT(8)
72 /* SPI_DATA */
73 #define SPI_DATA_DATA BITS(0,15)
75 /* SPI_CRCPOLY */
76 #define SPI_CRCPOLY_CPR BITS(0,15)
78 /* SPI_RCRC */
79 #define SPI_RCRC_RCR BITS(0,15)
81 /* SPI_TCRC */
82 #define SPI_TCRC_TCR BITS(0,15)
84 /* SPI_I2SCTL */
85 #define SPI_I2SCTL_CHLEN BIT(0)
86 #define SPI_I2SCTL_DTLEN BITS(1,2)
87 #define SPI_I2SCTL_CKPL BIT(3)
88 #define SPI_I2SCTL_I2SSTD BITS(4,5)
89 #define SPI_I2SCTL_PCMSMOD BIT(7)
90 #define SPI_I2SCTL_I2SOPMOD BITS(8,9)
91 #define SPI_I2SCTL_I2SEN BIT(10)
92 #define SPI_I2SCTL_I2SSEL BIT(11)
94 /* SPI_I2SPSC */
95 #define SPI_I2SPSC_DIV BITS(0,7)
96 #define SPI_I2SPSC_OF BIT(8)
97 #define SPI_I2SPSC_MCKOEN BIT(9)
99 /* SPI_QCTL(only for SPI1) */
100 #define SPI_QCTL_QMOD BIT(0)
101 #define SPI_QCTL_QRD BIT(1)
102 #define SPI_QCTL_IO23_DRV BIT(2)
104 /* constants definitions */
105 /* SPI and I2S parameter struct definitions */
106 typedef struct
107 {
108 uint32_t device_mode;
109 uint32_t trans_mode;
110 uint32_t frame_size;
111 uint32_t nss;
112 uint32_t endian;
113 uint32_t clock_polarity_phase;
114 uint32_t prescale;
115 }spi_parameter_struct;
116
117 /* SPI mode definitions */
118 #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS)
119 #define SPI_SLAVE ((uint32_t)0x00000000U)
121 /* SPI transmit type */
122 #define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U)
123 #define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO
124 #define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN
125 #define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN)
127 /* SPI frame size */
128 #define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16
129 #define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U)
131 /* SPI NSS control mode */
132 #define SPI_NSS_SOFT SPI_CTL0_SWNSSEN
133 #define SPI_NSS_HARD ((uint32_t)0x00000000U)
135 /* SPI transmit way */
136 #define SPI_ENDIAN_MSB ((uint32_t)0x00000000U)
137 #define SPI_ENDIAN_LSB SPI_CTL0_LF
139 /* SPI clock phase and polarity */
140 #define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U)
141 #define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL
142 #define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH
143 #define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH)
145 /* SPI clock prescale factor */
146 #define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
147 #define SPI_PSC_2 CTL0_PSC(0)
148 #define SPI_PSC_4 CTL0_PSC(1)
149 #define SPI_PSC_8 CTL0_PSC(2)
150 #define SPI_PSC_16 CTL0_PSC(3)
151 #define SPI_PSC_32 CTL0_PSC(4)
152 #define SPI_PSC_64 CTL0_PSC(5)
153 #define SPI_PSC_128 CTL0_PSC(6)
154 #define SPI_PSC_256 CTL0_PSC(7)
156 /* SPI bidirectional transfer direction */
157 #define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN
158 #define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN)
160 #ifdef GD32F350
161 /* I2S audio sample rate */
162 #define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U)
163 #define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U)
164 #define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U)
165 #define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U)
166 #define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U)
167 #define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U)
168 #define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U)
169 #define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U)
170 #define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U)
172 /* I2S frame format */
173 #define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1))
174 #define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0)
175 #define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN)
176 #define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN)
177 #define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN)
179 /* I2S master clock output */
180 #define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U)
181 #define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN
183 /* I2S operation mode */
184 #define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
185 #define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0)
186 #define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1)
187 #define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2)
188 #define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3)
190 /* I2S standard */
191 #define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
192 #define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0)
193 #define I2S_STD_MSB I2SCTL_I2SSTD(1)
194 #define I2S_STD_LSB I2SCTL_I2SSTD(2)
195 #define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3)
196 #define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD)
198 /* I2S clock polarity */
199 #define I2S_CKPL_LOW ((uint32_t)0x00000000U)
200 #define I2S_CKPL_HIGH SPI_I2SCTL_CKPL
201 #endif /* GD32F350 */
202
203 /* SPI DMA constants definitions */
204 #define SPI_DMA_TRANSMIT ((uint8_t)0x00U)
205 #define SPI_DMA_RECEIVE ((uint8_t)0x01U)
207 /* SPI CRC constants definitions */
208 #define SPI_CRC_TX ((uint8_t)0x00U)
209 #define SPI_CRC_RX ((uint8_t)0x01U)
211 /* SPI/I2S interrupt enable/disable constants definitions */
212 #define SPI_I2S_INT_TBE ((uint8_t)0x00U)
213 #define SPI_I2S_INT_RBNE ((uint8_t)0x01U)
214 #define SPI_I2S_INT_ERR ((uint8_t)0x02U)
216 /* SPI/I2S interrupt flag constants definitions */
217 #define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U)
218 #define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U)
219 #define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U)
220 #define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U)
221 #define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U)
222 #define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U)
223 #define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U)
225 /* SPI flag definitions */
226 #define SPI_FLAG_RBNE SPI_STAT_RBNE
227 #define SPI_FLAG_TBE SPI_STAT_TBE
228 #define SPI_FLAG_CRCERR SPI_STAT_CRCERR
229 #define SPI_FLAG_CONFERR SPI_STAT_CONFERR
230 #define SPI_FLAG_RXORERR SPI_STAT_RXORERR
231 #define SPI_FLAG_TRANS SPI_STAT_TRANS
232 #define SPI_FLAG_FERR SPI_STAT_FERR
234 #ifdef GD32F350
235 /* I2S flag definitions */
236 #define I2S_FLAG_RBNE SPI_STAT_RBNE
237 #define I2S_FLAG_TBE SPI_STAT_TBE
238 #define I2S_FLAG_CH SPI_STAT_I2SCH
239 #define I2S_FLAG_TXURERR SPI_STAT_TXURERR
240 #define I2S_FLAG_RXORERR SPI_STAT_RXORERR
241 #define I2S_FLAG_TRANS SPI_STAT_TRANS
242 #define I2S_FLAG_FERR SPI_STAT_FERR
243 #endif /* GD32F350 */
244
245 /* function declarations */
246 /* reset SPI and I2S */
247 void spi_i2s_deinit(uint32_t spi_periph);
248 /* initialize SPI parameter */
249 void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct);
250 /* enable SPI */
251 void spi_enable(uint32_t spi_periph);
252 /* disable SPI */
253 void spi_disable(uint32_t spi_periph);
254
255 #ifdef GD32F350
256 /* initialize I2S parameter */
257 void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl);
258 /* configure I2S prescaler */
259 void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout);
260 /* enable I2S */
261 void i2s_enable(uint32_t spi_periph);
262 /* disable I2S */
263 void i2s_disable(uint32_t spi_periph);
264 #endif /* GD32F350 */
265
266 /* enable SPI NSS output */
267 void spi_nss_output_enable(uint32_t spi_periph);
268 /* disable SPI NSS output */
269 void spi_nss_output_disable(uint32_t spi_periph);
270 /* SPI NSS pin high level in software mode */
271 void spi_nss_internal_high(uint32_t spi_periph);
272 /* SPI NSS pin low level in software mode */
273 void spi_nss_internal_low(uint32_t spi_periph);
274
275 /* enable SPI DMA */
276 void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
277 /* disable SPI DMA */
278 void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
279
280 /* configure SPI/I2S data frame format */
281 void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
282 /* SPI transmit data */
283 void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
284 /* SPI receive data */
285 uint16_t spi_i2s_data_receive(uint32_t spi_periph);
286 /* configure SPI bidirectional transfer direction */
287 void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
288
289 /* enable SPI and I2S interrupt */
290 void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
291 /* disable SPI and I2S interrupt */
292 void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
293 /* get SPI and I2S interrupt status */
294 FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
295 /* get SPI and I2S flag status */
296 FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
297 /* clear SPI CRC error flag status */
298 void spi_crc_error_clear(uint32_t spi_periph);
299
300 /* set SPI CRC polynomial */
301 void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
302 /* get SPI CRC polynomial */
303 uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
304 /* turn on SPI CRC function */
305 void spi_crc_on(uint32_t spi_periph);
306 /* turn off SPI CRC function */
307 void spi_crc_off(uint32_t spi_periph);
308 /* SPI next data is CRC value */
309 void spi_crc_next(uint32_t spi_periph);
310 /* get SPI CRC send value or receive value */
311 uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
312
313 /* enable SPI TI mode */
314 void spi_ti_mode_enable(uint32_t spi_periph);
315 /* disable SPI TI mode */
316 void spi_ti_mode_disable(uint32_t spi_periph);
317
318 /* enable SPI NSS pulse mode */
319 void spi_nssp_mode_enable(uint32_t spi_periph);
320 /* disable SPI NSS pulse mode */
321 void spi_nssp_mode_disable(uint32_t spi_periph);
322
323 /* enable quad wire SPI */
324 void qspi_enable(uint32_t spi_periph);
325 /* disable quad wire SPI */
326 void qspi_disable(uint32_t spi_periph);
327 /* enable quad wire SPI write */
328 void qspi_write_enable(uint32_t spi_periph);
329 /* enable quad wire SPI read */
330 void qspi_read_enable(uint32_t spi_periph);
331 /* enable quad wire SPI_IO2 and SPI_IO3 pin output */
332 void qspi_io23_output_enable(uint32_t spi_periph);
333 /* disable quad wire SPI_IO2 and SPI_IO3 pin output */
334 void qspi_io23_output_disable(uint32_t spi_periph);
335
336 #endif /* GD32F3X0_SPI_H */
spi_nss_output_disable
void spi_nss_output_disable(uint32_t spi_periph)
disable SPI NSS output
Definition: gd32f3x0_spi.c:265
spi_ti_mode_disable
void spi_ti_mode_disable(uint32_t spi_periph)
disable SPI TI mode
Definition: gd32f3x0_spi.c:648
spi_crc_next
void spi_crc_next(uint32_t spi_periph)
SPI next data is CRC value.
Definition: gd32f3x0_spi.c:608
spi_parameter_struct::nss
uint32_t nss
Definition: gd32f3x0_spi.h:111
spi_disable
void spi_disable(uint32_t spi_periph)
disable SPI
Definition: gd32f3x0_spi.c:110
spi_parameter_struct::device_mode
uint32_t device_mode
Definition: gd32f3x0_spi.h:108
spi_i2s_data_transmit
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
SPI transmit data.
Definition: gd32f3x0_spi.c:352
spi_i2s_interrupt_flag_get
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
get SPI and I2S interrupt flag status
Definition: gd32f3x0_spi.c:463
spi_crc_get
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
get SPI CRC send value or receive value
Definition: gd32f3x0_spi.c:622
spi_nssp_mode_enable
void spi_nssp_mode_enable(uint32_t spi_periph)
enable SPI NSS pulse mode
Definition: gd32f3x0_spi.c:659
spi_crc_polynomial_set
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly)
set CRC polynomial
Definition: gd32f3x0_spi.c:585
spi_crc_off
void spi_crc_off(uint32_t spi_periph)
turn off CRC function
Definition: gd32f3x0_spi.c:573
qspi_disable
void qspi_disable(uint32_t spi_periph)
disable quad wire SPI
Definition: gd32f3x0_spi.c:692
spi_parameter_struct::frame_size
uint32_t frame_size
Definition: gd32f3x0_spi.h:110
spi_enable
void spi_enable(uint32_t spi_periph)
enable SPI
Definition: gd32f3x0_spi.c:99
spi_i2s_interrupt_enable
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
enable SPI and I2S interrupt
Definition: gd32f3x0_spi.c:398
qspi_io23_output_disable
void qspi_io23_output_disable(uint32_t spi_periph)
disable SPI_IO2 and SPI_IO3 pin output
Definition: gd32f3x0_spi.c:736
spi_nss_internal_low
void spi_nss_internal_low(uint32_t spi_periph)
SPI NSS pin low level in software mode.
Definition: gd32f3x0_spi.c:287
spi_parameter_struct::trans_mode
uint32_t trans_mode
Definition: gd32f3x0_spi.h:109
spi_init
void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct)
initialize SPI parameter
Definition: gd32f3x0_spi.c:65
spi_dma_enable
void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
enable SPI DMA send or receive
Definition: gd32f3x0_spi.c:301
spi_i2s_deinit
void spi_i2s_deinit(uint32_t spi_periph)
reset SPI and I2S
Definition: gd32f3x0_spi.c:25
qspi_read_enable
void qspi_read_enable(uint32_t spi_periph)
enable quad wire SPI read
Definition: gd32f3x0_spi.c:714
spi_nss_internal_high
void spi_nss_internal_high(uint32_t spi_periph)
SPI NSS pin high level in software mode.
Definition: gd32f3x0_spi.c:276
qspi_enable
void qspi_enable(uint32_t spi_periph)
enable quad wire SPI
Definition: gd32f3x0_spi.c:681
spi_crc_on
void spi_crc_on(uint32_t spi_periph)
turn on CRC function
Definition: gd32f3x0_spi.c:562
spi_parameter_struct::endian
uint32_t endian
Definition: gd32f3x0_spi.h:112
spi_parameter_struct
Definition: gd32f3x0_spi.h:106
spi_nss_output_enable
void spi_nss_output_enable(uint32_t spi_periph)
enable SPI NSS output
Definition: gd32f3x0_spi.c:254
qspi_write_enable
void qspi_write_enable(uint32_t spi_periph)
enable quad wire SPI write
Definition: gd32f3x0_spi.c:703
spi_crc_polynomial_get
uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
get SPI CRC polynomial
Definition: gd32f3x0_spi.c:597
spi_dma_disable
void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
disable SPI DMA send or receive
Definition: gd32f3x0_spi.c:319
spi_nssp_mode_disable
void spi_nssp_mode_disable(uint32_t spi_periph)
disable SPI NSS pulse mode
Definition: gd32f3x0_spi.c:670
spi_bidirectional_transfer_config
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
configure SPI bidirectional transfer direction
Definition: gd32f3x0_spi.c:376
spi_i2s_data_receive
uint16_t spi_i2s_data_receive(uint32_t spi_periph)
SPI receive data.
Definition: gd32f3x0_spi.c:363
spi_parameter_struct::clock_polarity_phase
uint32_t clock_polarity_phase
Definition: gd32f3x0_spi.h:113
spi_ti_mode_enable
void spi_ti_mode_enable(uint32_t spi_periph)
enable SPI TI mode
Definition: gd32f3x0_spi.c:637
spi_i2s_data_frame_format_config
void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format)
configure SPI/I2S data frame format
Definition: gd32f3x0_spi.c:337
qspi_io23_output_enable
void qspi_io23_output_enable(uint32_t spi_periph)
enable SPI_IO2 and SPI_IO3 pin output
Definition: gd32f3x0_spi.c:725
spi_parameter_struct::prescale
uint32_t prescale
Definition: gd32f3x0_spi.h:114
spi_crc_error_clear
void spi_crc_error_clear(uint32_t spi_periph)
clear SPI CRC error flag status
Definition: gd32f3x0_spi.c:551
spi_i2s_flag_get
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
get SPI and I2S flag status
Definition: gd32f3x0_spi.c:536
spi_i2s_interrupt_disable
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
disable SPI and I2S interrupt
Definition: gd32f3x0_spi.c:429
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_dma.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_dma.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_DMA_H
13 #define GD32F3X0_DMA_H
14
15 #include "gd32f3x0.h"
16
17 /* DMA definitions */
18 #define DMA DMA_BASE
20 /* registers definitions */
21 #define DMA_INTF REG32(DMA + 0x00U)
22 #define DMA_INTC REG32(DMA + 0x04U)
23 #define DMA_CH0CTL REG32(DMA + 0x08U)
24 #define DMA_CH0CNT REG32(DMA + 0x0CU)
25 #define DMA_CH0PADDR REG32(DMA + 0x10U)
26 #define DMA_CH0MADDR REG32(DMA + 0x14U)
27 #define DMA_CH1CTL REG32(DMA + 0x1CU)
28 #define DMA_CH1CNT REG32(DMA + 0x20U)
29 #define DMA_CH1PADDR REG32(DMA + 0x24U)
30 #define DMA_CH1MADDR REG32(DMA + 0x28U)
31 #define DMA_CH2CTL REG32(DMA + 0x30U)
32 #define DMA_CH2CNT REG32(DMA + 0x34U)
33 #define DMA_CH2PADDR REG32(DMA + 0x38U)
34 #define DMA_CH2MADDR REG32(DMA + 0x3CU)
35 #define DMA_CH3CTL REG32(DMA + 0x44U)
36 #define DMA_CH3CNT REG32(DMA + 0x48U)
37 #define DMA_CH3PADDR REG32(DMA + 0x4CU)
38 #define DMA_CH3MADDR REG32(DMA + 0x50U)
39 #define DMA_CH4CTL REG32(DMA + 0x58U)
40 #define DMA_CH4CNT REG32(DMA + 0x5CU)
41 #define DMA_CH4PADDR REG32(DMA + 0x60U)
42 #define DMA_CH4MADDR REG32(DMA + 0x64U)
43 #define DMA_CH5CTL REG32(DMA + 0x6CU)
44 #define DMA_CH5CNT REG32(DMA + 0x70U)
45 #define DMA_CH5PADDR REG32(DMA + 0x74U)
46 #define DMA_CH5MADDR REG32(DMA + 0x78U)
47 #define DMA_CH6CTL REG32(DMA + 0x80U)
48 #define DMA_CH6CNT REG32(DMA + 0x84U)
49 #define DMA_CH6PADDR REG32(DMA + 0x88U)
50 #define DMA_CH6MADDR REG32(DMA + 0x8CU)
52 /* bits definitions */
53 /* DMA_INTF */
54 #define DMA_INTF_GIF BIT(0)
55 #define DMA_INTF_FTFIF BIT(1)
56 #define DMA_INTF_HTFIF BIT(2)
57 #define DMA_INTF_ERRIF BIT(3)
59 /* DMA_INTC */
60 #define DMA_INTC_GIFC BIT(0)
61 #define DMA_INTC_FTFIFC BIT(1)
62 #define DMA_INTC_HTFIFC BIT(2)
63 #define DMA_INTC_ERRIFC BIT(3)
65 /* DMA_CHxCTL,x=0..6 */
66 #define DMA_CHXCTL_CHEN BIT(0)
67 #define DMA_CHXCTL_FTFIE BIT(1)
68 #define DMA_CHXCTL_HTFIE BIT(2)
69 #define DMA_CHXCTL_ERRIE BIT(3)
70 #define DMA_CHXCTL_DIR BIT(4)
71 #define DMA_CHXCTL_CMEN BIT(5)
72 #define DMA_CHXCTL_PNAGA BIT(6)
73 #define DMA_CHXCTL_MNAGA BIT(7)
74 #define DMA_CHXCTL_PWIDTH BITS(8,9)
75 #define DMA_CHXCTL_MWIDTH BITS(10,11)
76 #define DMA_CHXCTL_PRIO BITS(12,13)
77 #define DMA_CHXCTL_M2M BIT(14)
79 /* DMA_CHxCNT,x=0..6 */
80 #define DMA_CHXCNT_CNT BITS(0,15)
82 /* DMA_CHxPADDR,x=0..6 */
83 #define DMA_CHXPADDR_PADDR BITS(0,31)
85 /* DMA_CHxMADDR,x=0..6 */
86 #define DMA_CHXMADDR_MADDR BITS(0,31)
88 /* constants definitions */
89 /* DMA channel select */
90 typedef enum
91 {
92 DMA_CH0 = 0,
93 DMA_CH1,
94 DMA_CH2,
95 DMA_CH3,
96 DMA_CH4,
97 DMA_CH5,
98 DMA_CH6
99 } dma_channel_enum;
100
101 /* DMA initialize struct */
102 typedef struct
103 {
104 uint32_t periph_addr;
105 uint32_t periph_width;
106 uint8_t periph_inc;
107 uint32_t memory_addr;
108 uint32_t memory_width;
109 uint8_t memory_inc;
110 uint8_t direction;
111 uint32_t number;
112 uint32_t priority;
113 } dma_parameter_struct;
114
115 /* DMA reset value */
116 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U)
117 #define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U)
118 #define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U)
119 #define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U)
120 #define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
121 DMA_INTF_HTFIF | DMA_INTF_ERRIF)
122
123 #define DMA_FLAG_ADD(flag,shift) ((flag) << ((uint32_t)(shift) * 4U))
125 /* DMA_CHCTL base address */
126 #define DMA_CHXCTL_BASE (DMA + 0x08U)
127 #define DMA_CHXCNT_BASE (DMA + 0x0CU)
128 #define DMA_CHXPADDR_BASE (DMA + 0x10U)
129 #define DMA_CHXMADDR_BASE (DMA + 0x14U)
131 /* DMA channel shift bit */
132 #define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + 0x14U * (uint32_t)(channel))
133 #define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + 0x14U * (uint32_t)(channel))
134 #define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + 0x14U * (uint32_t)(channel))
135 #define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + 0x14U * (uint32_t)(channel))
137 /* DMA_INTF register */
138 /* interrupt flag bits */
139 #define DMA_INT_FLAG_G DMA_INTF_GIF
140 #define DMA_INT_FLAG_FTF DMA_INTF_FTFIF
141 #define DMA_INT_FLAG_HTF DMA_INTF_HTFIF
142 #define DMA_INT_FLAG_ERR DMA_INTF_ERRIF
144 /* flag bits */
145 #define DMA_FLAG_G DMA_INTF_GIF
146 #define DMA_FLAG_FTF DMA_INTF_FTFIF
147 #define DMA_FLAG_HTF DMA_INTF_HTFIF
148 #define DMA_FLAG_ERR DMA_INTF_ERRIF
150 /* DMA_CHxCTL register */
151 /* interrupt enable bits */
152 #define DMA_INT_FTF DMA_CHXCTL_FTFIE
153 #define DMA_INT_HTF DMA_CHXCTL_HTFIE
154 #define DMA_INT_ERR DMA_CHXCTL_ERRIE
156 /* transfer direction */
157 #define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U)
158 #define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U)
160 /* peripheral increasing mode */
161 #define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U)
162 #define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U)
164 /* memory increasing mode */
165 #define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U)
166 #define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U)
168 /* transfer data size of peripheral */
169 #define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8))
170 #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0)
171 #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1)
172 #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2)
174 /* transfer data size of memory */
175 #define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10))
176 #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0)
177 #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1)
178 #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2)
180 /* channel priority level */
181 #define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12))
182 #define DMA_PRIORITY_LOW CHCTL_PRIO(0)
183 #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1)
184 #define DMA_PRIORITY_HIGH CHCTL_PRIO(2)
185 #define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3)
187 /* DMA_CHxCNT register */
188 /* transfer counter */
189 #define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT
190
191 /* function declarations */
192 /* deinitialize DMA a channel registers */
193 void dma_deinit(dma_channel_enum channelx);
194 /* initialize DMA channel */
195 void dma_init(dma_channel_enum channelx, dma_parameter_struct init_struct);
196 /* enable DMA circulation mode */
197 void dma_circulation_enable(dma_channel_enum channelx);
198 /* disable DMA circulation mode */
199 void dma_circulation_disable(dma_channel_enum channelx);
200 /* enable memory to memory mode */
201 void dma_memory_to_memory_enable(dma_channel_enum channelx);
202 /* disable memory to memory mode */
203 void dma_memory_to_memory_disable(dma_channel_enum channelx);
204 /* enable DMA channel */
205 void dma_channel_enable(dma_channel_enum channelx);
206 /* disable DMA channel */
207 void dma_channel_disable(dma_channel_enum channelx);
208
209 /* set DMA peripheral base address */
210 void dma_periph_address_config(dma_channel_enum channelx, uint32_t address);
211 /* set DMA memory base address */
212 void dma_memory_address_config(dma_channel_enum channelx, uint32_t address);
213 /* set the number of remaining data to be transferred by the DMA */
214 void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number);
215 /* get the number of remaining data to be transferred by the DMA */
216 uint32_t dma_transfer_number_get(dma_channel_enum channelx);
217 /* configure priority level of DMA channel */
218 void dma_priority_config(dma_channel_enum channelx, uint32_t priority);
219 /* configure transfer data size of memory */
220 void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth);
221 /* configure transfer data size of peripheral */
222 void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth);
223 /* enable next address increasement algorithm of memory */
224 void dma_memory_increase_enable(dma_channel_enum channelx);
225 /* disable next address increasement algorithm of memory */
226 void dma_memory_increase_disable(dma_channel_enum channelx);
227 /* enable next address increasement algorithm of peripheral */
228 void dma_periph_increase_enable(dma_channel_enum channelx);
229 /* disable next address increasement algorithm of peripheral */
230 void dma_periph_increase_disable(dma_channel_enum channelx);
231 /* configure the direction of data transfer on the channel */
232 void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction);
233
234 /* check DMA flag is set or not */
235 FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag);
236 /* clear DMA a channel flag */
237 void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
238 /* check DMA flag and interrupt enable bit is set or not */
239 FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag);
240 /* clear DMA a channel flag */
241 void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag);
242 /* enable DMA interrupt */
243 void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source);
244 /* disable DMA interrupt */
245 void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source);
246
247 #endif /* GD32F3X0_DMA_H */
dma_memory_increase_disable
void dma_memory_increase_disable(dma_channel_enum channelx)
disable next address increasement algorithm of memory
Definition: gd32f3x0_dma.c:305
dma_parameter_struct::priority
uint32_t priority
Definition: gd32f3x0_dma.h:112
dma_parameter_struct::memory_width
uint32_t memory_width
Definition: gd32f3x0_dma.h:108
dma_parameter_struct::periph_inc
uint8_t periph_inc
Definition: gd32f3x0_dma.h:106
dma_memory_address_config
void dma_memory_address_config(dma_channel_enum channelx, uint32_t address)
set DMA memory base address
Definition: gd32f3x0_dma.c:186
dma_interrupt_flag_clear
void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag
Definition: gd32f3x0_dma.c:448
dma_transfer_direction_config
void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction)
configure the direction of data transfer on the channel
Definition: gd32f3x0_dma.c:344
dma_channel_enable
void dma_channel_enable(dma_channel_enum channelx)
enable DMA channel
Definition: gd32f3x0_dma.c:148
dma_memory_increase_enable
void dma_memory_increase_enable(dma_channel_enum channelx)
enable next address increasement algorithm of memory
Definition: gd32f3x0_dma.c:293
dma_channel_enum
dma_channel_enum
Definition: gd32f3x0_dma.h:90
dma_memory_to_memory_enable
void dma_memory_to_memory_enable(dma_channel_enum channelx)
enable memory to memory mode
Definition: gd32f3x0_dma.c:124
DMA_CH0
Definition: gd32f3x0_dma.h:92
dma_channel_disable
void dma_channel_disable(dma_channel_enum channelx)
disable DMA channel
Definition: gd32f3x0_dma.c:160
dma_interrupt_flag_get
FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag)
check DMA flag and interrupt enable bit is set or not
Definition: gd32f3x0_dma.c:408
dma_deinit
void dma_deinit(dma_channel_enum channelx)
deinitialize DMA a channel registers
Definition: gd32f3x0_dma.c:21
dma_memory_to_memory_disable
void dma_memory_to_memory_disable(dma_channel_enum channelx)
disable memory to memory mode
Definition: gd32f3x0_dma.c:136
dma_transfer_number_get
uint32_t dma_transfer_number_get(dma_channel_enum channelx)
get the number of remaining data to be transferred by the DMA
Definition: gd32f3x0_dma.c:211
dma_circulation_enable
void dma_circulation_enable(dma_channel_enum channelx)
enable DMA circulation mode
Definition: gd32f3x0_dma.c:100
dma_parameter_struct
Definition: gd32f3x0_dma.h:102
dma_parameter_struct::number
uint32_t number
Definition: gd32f3x0_dma.h:111
DMA_CH5
Definition: gd32f3x0_dma.h:97
dma_priority_config
void dma_priority_config(dma_channel_enum channelx, uint32_t priority)
configure priority level of DMA channel
Definition: gd32f3x0_dma.c:228
dma_periph_width_config
void dma_periph_width_config(dma_channel_enum channelx, uint32_t pwidth)
configure transfer data size of peripheral
Definition: gd32f3x0_dma.c:274
dma_interrupt_enable
void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source)
enable DMA interrupt
Definition: gd32f3x0_dma.c:464
DMA_CH6
Definition: gd32f3x0_dma.h:98
dma_parameter_struct::periph_width
uint32_t periph_width
Definition: gd32f3x0_dma.h:105
dma_circulation_disable
void dma_circulation_disable(dma_channel_enum channelx)
disable DMA circulation mode
Definition: gd32f3x0_dma.c:112
dma_parameter_struct::memory_inc
uint8_t memory_inc
Definition: gd32f3x0_dma.h:109
dma_periph_address_config
void dma_periph_address_config(dma_channel_enum channelx, uint32_t address)
set DMA peripheral base address
Definition: gd32f3x0_dma.c:173
dma_parameter_struct::direction
uint8_t direction
Definition: gd32f3x0_dma.h:110
DMA_CH3
Definition: gd32f3x0_dma.h:95
dma_init
void dma_init(dma_channel_enum channelx, dma_parameter_struct init_struct)
initialize DMA channel
Definition: gd32f3x0_dma.c:50
dma_periph_increase_enable
void dma_periph_increase_enable(dma_channel_enum channelx)
enable next address increasement algorithm of peripheral
Definition: gd32f3x0_dma.c:317
dma_flag_get
FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag)
check DMA flag is set or not
Definition: gd32f3x0_dma.c:366
dma_memory_width_config
void dma_memory_width_config(dma_channel_enum channelx, uint32_t mwidth)
configure transfer data size of memory
Definition: gd32f3x0_dma.c:251
dma_interrupt_disable
void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source)
disable DMA interrupt
Definition: gd32f3x0_dma.c:480
DMA_CH4
Definition: gd32f3x0_dma.h:96
DMA_CH1
Definition: gd32f3x0_dma.h:93
dma_periph_increase_disable
void dma_periph_increase_disable(dma_channel_enum channelx)
disable next address increasement algorithm of peripheral
Definition: gd32f3x0_dma.c:329
DMA_CH2
Definition: gd32f3x0_dma.h:94
dma_parameter_struct::periph_addr
uint32_t periph_addr
Definition: gd32f3x0_dma.h:104
dma_flag_clear
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
clear DMA a channel flag
Definition: gd32f3x0_dma.c:391
dma_parameter_struct::memory_addr
uint32_t memory_addr
Definition: gd32f3x0_dma.h:107
dma_transfer_number_config
void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number)
set the number of remaining data to be transferred by the DMA
Definition: gd32f3x0_dma.c:199
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_dac.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_dac.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifdef GD32F350
13 #ifndef GD32F3X0_DAC_H
14 #define GD32F3X0_DAC_H
15
16 #include "gd32f3x0.h"
17
18 /* DAC definitions */
19 #define DAC DAC_BASE
20
21 /* registers definitions */
22 #define DAC_CTL REG32(DAC + 0x00U)
23 #define DAC_SWT REG32(DAC + 0x04U)
24 #define DAC_R12DH REG32(DAC + 0x08U)
25 #define DAC_L12DH REG32(DAC + 0x0CU)
26 #define DAC_R8DH REG32(DAC + 0x10U)
27 #define DAC_DO REG32(DAC + 0x2CU)
28 #define DAC_STAT REG32(DAC + 0x34U)
30 /* bits definitions */
31 /* DAC_CTL */
32 #define DAC_CTL_DEN BIT(0)
33 #define DAC_CTL_DBOFF BIT(1)
34 #define DAC_CTL_DTEN BIT(2)
35 #define DAC_CTL_DTSEL BITS(3,5)
36 #define DAC_CTL_DWM BITS(6,7)
37 #define DAC_CTL_DWBW BITS(8,11)
38 #define DAC_CTL_DDMAEN BIT(12)
39 #define DAC_CTL_DDUDRIE BIT(13)
41 /* DAC_SWT */
42 #define DAC_SWT_SWTR BIT(0)
44 /* DAC_R12DH */
45 #define DAC_R12DH_DAC_DH BITS(0,11)
47 /* DAC_L12DH */
48 #define DAC_L12DH_DAC_DH BITS(4,15)
50 /* DAC_R8DH */
51 #define DAC_R8DH_DAC_DH BITS(0,7)
53 /* DAC_DO */
54 #define DAC_DO_DAC_DO BITS(0,11)
56 /* DAC_STAT */
57 #define DAC_STAT_DDUDR BIT(13)
59 /* constants definitions */
60 /* DAC trigger source */
61 #define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
62 #define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0)
63 #define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1)
64 #define DAC_TRIGGER_T14_TRGO CTL_DTSEL(3)
65 #define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4)
66 #define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6)
67 #define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7)
69 /* DAC noise wave mode */
70 #define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
71 #define DAC_WAVE_DISABLE CTL_DWM(0)
72 #define DAC_WAVE_MODE_LFSR CTL_DWM(1)
73 #define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2)
75 /* DAC noise wave bit width */
76 #define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
77 #define DAC_WAVE_BIT_WIDTH_1 DWBW(0)
78 #define DAC_WAVE_BIT_WIDTH_2 DWBW(1)
79 #define DAC_WAVE_BIT_WIDTH_3 DWBW(2)
80 #define DAC_WAVE_BIT_WIDTH_4 DWBW(3)
81 #define DAC_WAVE_BIT_WIDTH_5 DWBW(4)
82 #define DAC_WAVE_BIT_WIDTH_6 DWBW(5)
83 #define DAC_WAVE_BIT_WIDTH_7 DWBW(6)
84 #define DAC_WAVE_BIT_WIDTH_8 DWBW(7)
85 #define DAC_WAVE_BIT_WIDTH_9 DWBW(8)
86 #define DAC_WAVE_BIT_WIDTH_10 DWBW(9)
87 #define DAC_WAVE_BIT_WIDTH_11 DWBW(10)
88 #define DAC_WAVE_BIT_WIDTH_12 DWBW(11)
90 /* unmask LFSR bits in DAC LFSR noise mode */
91 #define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1
92 #define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2
93 #define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3
94 #define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4
95 #define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5
96 #define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6
97 #define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7
98 #define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8
99 #define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9
100 #define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10
101 #define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11
102 #define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12
104 /* triangle amplitude in DAC triangle noise mode */
105 #define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1
106 #define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2
107 #define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3
108 #define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4
109 #define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5
110 #define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6
111 #define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7
112 #define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8
113 #define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9
114 #define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10
115 #define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11
116 #define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12
118 /* DAC data alignment */
119 #define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
120 #define DAC_ALIGN_12B_R DATA_ALIGN(0)
121 #define DAC_ALIGN_12B_L DATA_ALIGN(1)
122 #define DAC_ALIGN_8B_R DATA_ALIGN(2)
124 /* function declarations */
125 /* deinitialize DAC */
126 void dac_deinit(void);
127
128 /* enable DAC */
129 void dac_enable(void);
130 /* disable DAC */
131 void dac_disable(void);
132 /* enable DAC DMA */
133 void dac_dma_enable(void);
134 /* disable DAC DMA */
135 void dac_dma_disable(void);
136 /* enable DAC output buffer */
137 void dac_output_buffer_enable(void);
138 /* disable DAC output buffer */
139 void dac_output_buffer_disable(void);
140 /* enable DAC trigger */
141 void dac_trigger_enable(void);
142 /* disable DAC trigger */
143 void dac_trigger_disable(void);
144 /* enable DAC software trigger */
145 void dac_software_trigger_enable(void);
146 /* disable DAC software trigger */
147 void dac_software_trigger_disable(void);
148 /* enable DAC interrupt(DAC DMA underrun interrupt) */
149 void dac_interrupt_enable(void);
150 /* disable DAC interrupt(DAC DMA underrun interrupt) */
151 void dac_interrupt_disable(void);
152
153 /* configure DAC trigger source */
154 void dac_trigger_source_config(uint32_t triggersource);
155 /* configure DAC wave mode */
156 void dac_wave_mode_config(uint32_t wave_mode);
157 /* configure DAC wave bit width */
158 void dac_wave_bit_width_config(uint32_t bit_width);
159 /* configure DAC LFSR noise mode */
160 void dac_lfsr_noise_config(uint32_t unmask_bits);
161 /* configure DAC triangle noise mode */
162 void dac_triangle_noise_config(uint32_t amplitude);
163 /* get the last data output value */
164 uint16_t dac_output_value_get(void);
165
166 /* get the specified DAC flag(DAC DMA underrun flag) */
167 FlagStatus dac_flag_get(void);
168 /* clear the specified DAC flag(DAC DMA underrun flag) */
169 void dac_flag_clear(void);
170 /* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
171 FlagStatus dac_interrupt_flag_get(void);
172 /* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
173 void dac_interrupt_flag_clear(void);
174
175 /* set DAC data holding register value */
176 void dac_data_set(uint32_t dac_align, uint16_t data);
177
178 #endif /* GD32F3X0_DAC_H */
179
180 #endif /* GD32F350 */
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_pmu.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_pmu.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_PMU_H
13 #define GD32F3X0_PMU_H
14
15 #include "gd32f3x0.h"
16
17 /* PMU definitions */
18 #define PMU PMU_BASE
20 /* registers definitions */
21 #define PMU_CTL REG32((PMU) + 0x00U)
22 #define PMU_CS REG32((PMU) + 0x04U)
24 /* bits definitions */
25 /* PMU_CTL */
26 #define PMU_CTL_LDOLP BIT(0)
27 #define PMU_CTL_STBMOD BIT(1)
28 #define PMU_CTL_WURST BIT(2)
29 #define PMU_CTL_STBRST BIT(3)
30 #define PMU_CTL_LVDEN BIT(4)
31 #define PMU_CTL_LVDT BITS(5,7)
32 #define PMU_CTL_BKPWEN BIT(8)
33 #define PMU_CTL_LDLP BIT(10)
34 #define PMU_CTL_LDNP BIT(11)
35 #define PMU_CTL_LDOVS BITS(14,15)
36 #define PMU_CTL_HDEN BIT(16)
37 #define PMU_CTL_HDS BIT(17)
38 #define PMU_CTL_LDEN BITS(18,19)
40 /* PMU_CS */
41 #define PMU_CS_WUF BIT(0)
42 #define PMU_CS_STBF BIT(1)
43 #define PMU_CS_LVDF BIT(2)
44 #define PMU_CS_WUPEN0 BIT(8)
45 #define PMU_CS_WUPEN1 BIT(9)
46 #define PMU_CS_WUPEN4 BIT(12)
47 #define PMU_CS_WUPEN5 BIT(13)
48 #define PMU_CS_WUPEN6 BIT(14)
49 #define PMU_CS_LDOVSRF BIT(15)
50 #define PMU_CS_HDRF BIT(16)
51 #define PMU_CS_HDSRF BIT(17)
52 #define PMU_CS_LDRF BITS(18,19)
54 /* constants definitions */
55 /* PMU low voltage detector threshold definitions */
56 #define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
57 #define PMU_LVDT_0 CTL_LVDT(0)
58 #define PMU_LVDT_1 CTL_LVDT(1)
59 #define PMU_LVDT_2 CTL_LVDT(2)
60 #define PMU_LVDT_3 CTL_LVDT(3)
61 #define PMU_LVDT_4 CTL_LVDT(4)
62 #define PMU_LVDT_5 CTL_LVDT(5)
63 #define PMU_LVDT_6 CTL_LVDT(6)
64 #define PMU_LVDT_7 CTL_LVDT(7)
66 /* PMU LDO output voltage select definitions */
67 #define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14))
68 #define PMU_LDOVS_LOW CTL_LDOVS(1)
69 #define PMU_LDOVS_MID CTL_LDOVS(2)
70 #define PMU_LDOVS_HIGH CTL_LDOVS(3)
72 /* PMU low-driver mode enable in deep-sleep mode */
73 #define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
74 #define PMU_LOWDRIVER_DISABLE CTL_LDEN(0)
75 #define PMU_LOWDRIVER_ENABLE CTL_LDEN(3)
77 /* PMU high-driver mode switch */
78 #define PMU_HIGHDR_SWITCH_NONE ((uint32_t)0x00000000U)
79 #define PMU_HIGHDR_SWITCH_EN PMU_CTL_HDS
81 /* PMU low-driver mode when use normal power LDO */
82 #define PMU_NORMALDR_NORMALPWR ((uint32_t)0x00000000U)
83 #define PMU_LOWDR_NORMALPWR PMU_CTL_LDNP
85 /* PMU low-driver mode when use low power LDO */
86 #define PMU_NORMALDR_LOWPWR ((uint32_t)0x00000000U)
87 #define PMU_LOWDR_LOWPWR PMU_CTL_LDLP
89 /* PMU ldo definitions */
90 #define PMU_LDO_NORMAL ((uint32_t)0x00000000U)
91 #define PMU_LDO_LOWPOWER PMU_CTL_LDOLP
93 /* PMU low power mode ready flag definitions */
94 #define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
95 #define PMU_LDRF_NORMAL CS_LDRF(0)
96 #define PMU_LDRF_LOWDRIVER CS_LDRF(3)
98 /* PMU flag definitions */
99 #define PMU_FLAG_WAKEUP PMU_CS_WUF
100 #define PMU_FLAG_STANDBY PMU_CS_STBF
101 #define PMU_FLAG_LVD PMU_CS_LVDF
102 #define PMU_FLAG_LDOVSR PMU_CS_LDOVSRF
103 #define PMU_FLAG_HDR PMU_CS_HDRF
104 #define PMU_FLAG_HDSR PMU_CS_HDSRF
105 #define PMU_FLAG_LDR PMU_CS_LDRF
107 /* PMU WKUP pin definitions */
108 #define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0
109 #define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1
110 #define PMU_WAKEUP_PIN4 PMU_CS_WUPEN4
111 #define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5
112 #define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6
114 /* PMU flag reset definitions */
115 #define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST
116 #define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST
118 /* PMU command constants definitions */
119 #define WFI_CMD ((uint8_t)0x00U)
120 #define WFE_CMD ((uint8_t)0x01U)
122 /* function declarations */
123 /* reset PMU registers */
124 void pmu_deinit(void);
125
126 /* select low voltage detector threshold */
127 void pmu_lvd_select(uint32_t lvdt_n);
128 /* select LDO output voltage */
129 void pmu_ldo_output_select(uint32_t ldo_output);
130 /* disable PMU lvd */
131 void pmu_lvd_disable(void);
132
133 /* functions of low-driver mode and high-driver mode in deep-sleep mode */
134 /* enable low-driver mode in deep-sleep mode */
135 void pmu_lowdriver_mode_enable(void);
136 /* disable low-driver mode in deep-sleep mode */
137 void pmu_lowdriver_mode_disable(void);
138 /* enable high-driver mode */
139 void pmu_highdriver_mode_enable(void);
140 /* disable high-driver mode */
141 void pmu_highdriver_mode_disable(void);
142 /* switch high-driver mode */
143 void pmu_highdriver_switch_select(uint32_t highdr_switch);
144 /* in deep-sleep mode, low-driver mode when use low power LDO */
145 void pmu_lowpower_driver_config(uint32_t mode);
146 /* in deep-sleep mode, low-driver mode when use normal power LDO */
147 void pmu_normalpower_driver_config(uint32_t mode);
148
149 /* set PMU mode */
150 /* PMU work in sleep mode */
151 void pmu_to_sleepmode(uint8_t sleepmodecmd);
152 /* PMU work in deepsleep mode */
153 void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
154 /* PMU work in standby mode */
155 void pmu_to_standbymode(uint8_t standbymodecmd);
156 /* enable PMU wakeup pin */
157 void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
158 /* disable PMU wakeup pin */
159 void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
160
161 /* backup related functions */
162 /* enable backup domain write */
163 void pmu_backup_write_enable(void);
164 /* disable backup domain write */
165 void pmu_backup_write_disable(void);
166
167 /* flag functions */
168 /* clear flag bit */
169 void pmu_flag_clear(uint32_t flag_clear);
170 /* get flag state */
171 FlagStatus pmu_flag_get(uint32_t flag);
172
173 #endif /* GD32F3X0_PMU_H */
pmu_lowpower_driver_config
void pmu_lowpower_driver_config(uint32_t mode)
low-driver mode when use low power LDO
Definition: gd32f3x0_pmu.c:159
pmu_deinit
void pmu_deinit(void)
reset PMU register
Definition: gd32f3x0_pmu.c:21
pmu_wakeup_pin_disable
void pmu_wakeup_pin_disable(uint32_t wakeup_pin)
disable wakeup pin
Definition: gd32f3x0_pmu.c:295
pmu_highdriver_mode_enable
void pmu_highdriver_mode_enable(void)
enable high-driver mode this bit set by software only when IRC8M or HXTAL used as system clock ...
Definition: gd32f3x0_pmu.c:115
pmu_to_standbymode
void pmu_to_standbymode(uint8_t standbymodecmd)
pmu work at standby mode
Definition: gd32f3x0_pmu.c:247
pmu_ldo_output_select
void pmu_ldo_output_select(uint32_t ldo_output)
select LDO output voltage these bits set by software when the main PLL closed
Definition: gd32f3x0_pmu.c:66
pmu_lvd_disable
void pmu_lvd_disable(void)
disable PMU lvd
Definition: gd32f3x0_pmu.c:78
pmu_to_sleepmode
void pmu_to_sleepmode(uint8_t sleepmodecmd)
PMU work at sleep mode.
Definition: gd32f3x0_pmu.c:189
pmu_flag_clear
void pmu_flag_clear(uint32_t flag_clear)
clear flag bit
Definition: gd32f3x0_pmu.c:331
pmu_backup_write_enable
void pmu_backup_write_enable(void)
enable backup domain write
Definition: gd32f3x0_pmu.c:306
pmu_lvd_select
void pmu_lvd_select(uint32_t lvdt_n)
select low voltage detector threshold
Definition: gd32f3x0_pmu.c:43
pmu_backup_write_disable
void pmu_backup_write_disable(void)
disable backup domain write
Definition: gd32f3x0_pmu.c:317
pmu_flag_get
FlagStatus pmu_flag_get(uint32_t flag)
get flag state
Definition: gd32f3x0_pmu.c:357
pmu_highdriver_mode_disable
void pmu_highdriver_mode_disable(void)
disable high-driver mode
Definition: gd32f3x0_pmu.c:126
pmu_normalpower_driver_config
void pmu_normalpower_driver_config(uint32_t mode)
low-driver mode when use normal power LDO
Definition: gd32f3x0_pmu.c:174
pmu_lowdriver_mode_enable
void pmu_lowdriver_mode_enable(void)
enable low-driver mode in deep-sleep mode
Definition: gd32f3x0_pmu.c:90
pmu_highdriver_switch_select
void pmu_highdriver_switch_select(uint32_t highdr_switch)
switch high-driver mode this bit set by software only when IRC8M or HXTAL used as system clock ...
Definition: gd32f3x0_pmu.c:141
pmu_to_deepsleepmode
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd)
PMU work at deepsleep mode.
Definition: gd32f3x0_pmu.c:215
pmu_lowdriver_mode_disable
void pmu_lowdriver_mode_disable(void)
enable low-driver mode in deep-sleep mode
Definition: gd32f3x0_pmu.c:102
pmu_wakeup_pin_enable
void pmu_wakeup_pin_enable(uint32_t wakeup_pin)
enable wakeup pin
Definition: gd32f3x0_pmu.c:278
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbd_std.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
usbd_std.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "usbd_std.h"
13 #include "usb_core.h"
14
15 static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req);
16 static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req);
17 static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req);
18
19 static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req);
20
21 static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req);
22 static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req);
23 static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req);
24 static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req);
25 static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req);
26 static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req);
27 static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req);
28 static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req);
29 static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req);
30 static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req);
31 static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req);
32 static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req);
33
34 static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen);
35 static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen);
36 static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen);
37
38 static void (*StandardDeviceRequest[])(usb_core_handle_struct *pudev, usb_device_req_struct *req) =
39 {
40 usbd_getstatus,
41 usbd_clrfeature,
42 usbd_reserved,
43 usbd_setfeature,
44 usbd_reserved,
45 usbd_setaddress,
46 usbd_getdescriptor,
47 usbd_setdescriptor,
48 usbd_getconfig,
49 usbd_setconfig,
50 usbd_getinterface,
51 usbd_setinterface,
52 usbd_synchframe,
53 };
54
55 /* get standard descriptor handler */
56 static uint8_t* (*standard_descriptor_get[])(usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) =
57 {
58 usbd_device_descriptor_get,
59 usbd_configuration_descriptor_get,
60 usbd_string_descriptor_get
61 };
62
69 usbd_status_enum usbd_setup_transaction(usb_core_handle_struct *pudev)
70 {
71 usb_device_req_struct req;
72
73 usbd_setup_request_parse(pudev, &req);
74
75 switch (req.bmRequestType & USB_REQ_MASK) {
76 /* standard device request */
77 case USB_STANDARD_REQ:
78 usbd_standard_request(pudev, &req);
79 break;
80 /* device class request */
81 case USB_CLASS_REQ:
82 usbd_device_class_request(pudev, &req);
83 break;
84 /* vendor defined request */
85 case USB_VENDOR_REQ:
86 usbd_vendor_request(pudev, &req);
87 break;
88 default:
89 usbd_ep_stall(pudev, req.bmRequestType & 0x80U);
90 break;
91 }
92
93 return USBD_OK;
94 }
95
103 usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num)
104 {
105 usb_ep_struct *ep;
106
107 if (0U == endp_num) {
108 ep = &pudev->dev.out_ep[0];
109
110 if (USB_CTRL_DATA_OUT == pudev->dev.ctl_status) {
111 if (pudev->dev.remain_len > ep->endp_mps) {
112 pudev->dev.remain_len -= ep->endp_mps;
113
114 usbd_ep_rx (pudev,
115 0U,
116 ep->xfer_buff,
117 (uint16_t)USB_MIN(pudev->dev.remain_len, ep->endp_mps));
118 } else {
119 if (USB_STATUS_CONFIGURED == pudev->dev.status) {
120 pudev->dev.class_data_handler(pudev, USB_RX, 0U);
121 }
122
123 usbd_ctlstatus_tx(pudev);
124 }
125 }
126 } else if (USB_STATUS_CONFIGURED == pudev->dev.status) {
127 pudev->dev.class_data_handler(pudev, USB_RX, endp_num);
128 } else {
129 /* no operation */
130 }
131
132 return USBD_OK;
133 }
134
142 usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num)
143 {
144 usb_ep_struct *ep;
145
146 if (0U == endp_num) {
147 ep = &pudev->dev.in_ep[0];
148
149 if (USB_CTRL_DATA_IN == pudev->dev.ctl_status) {
150 if (pudev->dev.remain_len > ep->endp_mps) {
151 pudev->dev.remain_len -= ep->endp_mps;
152
153 usbd_ep_tx (pudev, 0U, ep->xfer_buff, pudev->dev.remain_len);
154
155 usbd_ep_rx (pudev, 0U, NULL, 0U);
156 } else {
157 /* last packet is MPS multiple, so send ZLP packet */
158 if ((pudev->dev.sum_len % ep->endp_mps == 0U) &&
159 (pudev->dev.sum_len >= ep->endp_mps) &&
160 (pudev->dev.sum_len < pudev->dev.ctl_len)) {
161 usbd_ep_tx (pudev, 0U, NULL, 0U);
162 pudev->dev.ctl_len = 0U;
163
164 usbd_ep_rx (pudev, 0U, NULL, 0U);
165 } else {
166 if (USB_STATUS_CONFIGURED == pudev->dev.status) {
167 pudev->dev.class_data_handler(pudev, USB_TX, 0U);
168 }
169
170 usbd_ctlstatus_rx(pudev);
171 }
172 }
173 }
174 } else if (USB_STATUS_CONFIGURED == pudev->dev.status) {
175 pudev->dev.class_data_handler(pudev, USB_TX, endp_num);
176 } else {
177 /* no operation */
178 }
179
180 return USBD_OK;
181 }
182
190 static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req)
191 {
192 /* call device request handle function */
193 (*StandardDeviceRequest[req->bRequest])(pudev, req);
194
195 return USBD_OK;
196 }
197
205 static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req)
206 {
207 usbd_status_enum ret = USBD_OK;
208
209 switch (pudev->dev.status) {
210 case USB_STATUS_CONFIGURED:
211 if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
212 ret = (usbd_status_enum)(pudev->dev.class_req_handler(pudev, req));
213
214 if ((0U == req->wLength) && (USBD_OK == ret)) {
215 /* no data stage */
216 usbd_ctlstatus_tx(pudev);
217 }
218 } else {
219 usbd_enum_error(pudev, req);
220 }
221 break;
222
223 default:
224 usbd_enum_error(pudev, req);
225 break;
226 }
227
228 return ret;
229 }
230
238 static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req)
239 {
240 /* added by user... */
241
242 return USBD_OK;
243 }
244
252 static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req)
253 {
254 /* no operation... */
255 }
256
264 static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen)
265 {
266 *pLen = pudev->dev.dev_desc[0];
267
268 return pudev->dev.dev_desc;
269 }
270
278 static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen)
279 {
280 *pLen = pudev->dev.config_desc[2];
281
282 return pudev->dev.config_desc;
283 }
284
292 static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen)
293 {
294 uint8_t *desc = pudev->dev.strings[index];
295
296 *pLen = desc[0];
297
298 return desc;
299 }
300
308 static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req)
309 {
310 }
311
319 static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req)
320 {
321 uint8_t ep_addr = 0U;
322
323 switch (req->bmRequestType & USB_REQTYPE_MASK) {
324 case USB_REQTYPE_DEVICE:
325 switch (pudev->dev.status) {
326 case USB_STATUS_ADDRESSED:
327 case USB_STATUS_CONFIGURED:
328 if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) {
329 pudev->dev.remote_wakeup = 0U;
330 pudev->dev.class_req_handler(pudev, req);
331
332 usbd_ctlstatus_tx(pudev);
333 }
334 break;
335
336 default:
337 usbd_enum_error(pudev, req);
338 break;
339 }
340 break;
341 case USB_REQTYPE_INTERFACE:
342 switch (pudev->dev.status) {
343 case USB_STATUS_ADDRESSED:
344 usbd_enum_error(pudev, req);
345 break;
346 case USB_STATUS_CONFIGURED:
347 if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
348 /* no operation */
349 } else {
350 usbd_enum_error(pudev, req);
351 }
352 break;
353 default:
354 break;
355 }
356 break;
357 case USB_REQTYPE_ENDPOINT:
358 ep_addr = LOWBYTE(req->wIndex);
359
360 switch (pudev->dev.status) {
361 case USB_STATUS_ADDRESSED:
362 if (IS_NOT_EP0(ep_addr)) {
363 usbd_ep_stall(pudev, ep_addr);
364 }
365 break;
366 case USB_STATUS_CONFIGURED:
367 if (USB_FEATURE_ENDP_HALT == req->wValue) {
368 if (IS_NOT_EP0(ep_addr)) {
369 usbd_ep_clear_stall(pudev, ep_addr);
370
371 pudev->dev.class_req_handler(pudev, req);
372 }
373 }
374 usbd_ctlstatus_tx(pudev);
375 break;
376 default:
377 break;
378 }
379 break;
380 default:
381 usbd_enum_error(pudev, req);
382 break;
383 }
384 }
385
393 static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req)
394 {
395 uint8_t ep_addr = 0U;
396 __IO uint32_t DctlrStatus;
397
398 switch (req->bmRequestType & USB_REQ_MASK) {
399 case USB_REQTYPE_DEVICE:
400 switch (pudev->dev.status) {
401 case USB_STATUS_ADDRESSED:
402 case USB_STATUS_CONFIGURED:
403 if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) {
404 pudev->dev.remote_wakeup = 1U;
405 pudev->dev.class_req_handler(pudev, req);
406
407 usbd_ctlstatus_tx(pudev);
408 } else if ((req->wValue == USB_FEATURE_TEST_MODE) &&
409 (0U == (req->wIndex & 0xFFU))) {
410 DctlrStatus = USB_DCTL;
411
412 usbd_ctlstatus_tx(pudev);
413 } else {
414 /* no operation */
415 }
416 break;
417 default:
418 break;
419 }
420 break;
421 case USB_REQTYPE_INTERFACE:
422 switch (pudev->dev.status) {
423 case USB_STATUS_ADDRESSED:
424 usbd_enum_error(pudev, req);
425 break;
426 case USB_STATUS_CONFIGURED:
427 if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
428 /* no operation */
429 } else {
430 usbd_enum_error(pudev, req);
431 }
432 break;
433 default:
434 break;
435 }
436 break;
437 case USB_REQTYPE_ENDPOINT:
438 switch (pudev->dev.status) {
439 case USB_STATUS_ADDRESSED:
440 if (IS_NOT_EP0(ep_addr)) {
441 usbd_ep_stall(pudev, ep_addr);
442 }
443 break;
444 case USB_STATUS_CONFIGURED:
445 if (USB_FEATURE_ENDP_HALT == req->wValue) {
446 if (IS_NOT_EP0(ep_addr)) {
447 usbd_ep_stall(pudev, ep_addr);
448 }
449 }
450 pudev->dev.class_req_handler(pudev, req);
451
452 usbd_ctlstatus_tx(pudev);
453 break;
454 default:
455 break;
456 }
457 break;
458 default:
459 usbd_enum_error(pudev, req);
460 break;
461 }
462 }
463
471 static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req)
472 {
473 uint8_t DevAddr;
474
475 if ((0U == req->wIndex) && (0U == req->wLength)) {
476 DevAddr = (uint8_t)(req->wValue) & 0x7FU;
477
478 if (USB_STATUS_CONFIGURED == pudev->dev.status) {
479 usbd_enum_error(pudev, req);
480 } else {
481 USB_SET_DEVADDR((uint32_t)DevAddr);
482
483 usbd_ctlstatus_tx(pudev);
484
485 if (0U != DevAddr) {
486 pudev->dev.status = USB_STATUS_ADDRESSED;
487 } else {
488 pudev->dev.status = USB_STATUS_DEFAULT;
489 }
490 }
491 } else {
492 usbd_enum_error(pudev, req);
493 }
494 }
495
503 static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req)
504 {
505 if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQTYPE_MASK)) {
506 uint8_t desc_index = (uint8_t)(req->wValue >> 8U);
507
508 if (desc_index <= 0x03U) {
509 uint16_t len;
510 uint8_t *pbuf;
511
512 /* call corresponding descriptor get function */
513 pbuf = standard_descriptor_get[desc_index - 1U](pudev, (uint8_t)(req->wValue) & 0xFFU, &len);
514
515 if ((0U != len) && (0U != req->wLength)) {
516 len = USB_MIN(len, req->wLength);
517
518 if ((1U == desc_index) && (64U == req->wLength)) {
519 len = 8U;
520 }
521
522 usbd_ctltx(pudev, pbuf, len);
523 }
524 } else {
525 usbd_enum_error(pudev, req);
526 }
527 } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQTYPE_MASK)) {
528 pudev->dev.class_req_handler(pudev, req);
529 } else {
530 /* no operation */
531 }
532 }
533
541 static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req)
542 {
543 /* no handle... */
544 }
545
553 static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req)
554 {
555 uint32_t USBD_default_config = 0U;
556
557 if (1U != req->wLength) {
558 usbd_enum_error(pudev, req);
559 } else {
560 switch (pudev->dev.status) {
561 case USB_STATUS_ADDRESSED:
562 usbd_ctltx(pudev, (uint8_t *)&USBD_default_config, 1U);
563 break;
564 case USB_STATUS_CONFIGURED:
565 usbd_ctltx(pudev, &pudev->dev.config_num, 1U);
566 break;
567 default:
568 usbd_enum_error(pudev, req);
569 break;
570 }
571 }
572 }
573
581 static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req)
582 {
583 static uint8_t cfgidx;
584
585 cfgidx = (uint8_t)(req->wValue);
586
587 if (cfgidx > USBD_CFG_MAX_NUM) {
588 usbd_enum_error(pudev, req);
589 } else {
590 switch (pudev->dev.status) {
591 case USB_STATUS_ADDRESSED:
592 if (cfgidx) {
593 pudev->dev.config_num = cfgidx;
594 pudev->dev.status = USB_STATUS_CONFIGURED;
595 pudev->dev.class_init(pudev, cfgidx);
596 }
597
598 usbd_ctlstatus_tx(pudev);
599 break;
600 case USB_STATUS_CONFIGURED:
601 if (0U == cfgidx) {
602 pudev->dev.status = USB_STATUS_ADDRESSED;
603 pudev->dev.config_num = cfgidx;
604 pudev->dev.class_deinit(pudev, cfgidx);
605 } else if (cfgidx != pudev->dev.config_num) {
606 /* clear old configuration */
607 pudev->dev.class_deinit(pudev, pudev->dev.config_num);
608
609 /* set new configuration */
610 pudev->dev.config_num = cfgidx;
611 pudev->dev.class_init(pudev, cfgidx);
612 } else {
613 /* no operation */
614 }
615
616 usbd_ctlstatus_tx(pudev);
617 break;
618 default:
619 usbd_enum_error(pudev, req);
620 break;
621 }
622 }
623 }
624
632 static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req)
633 {
634 pudev->dev.class_req_handler(pudev, req);
635 }
636
644 static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req)
645 {
646 pudev->dev.class_req_handler(pudev, req);
647 }
648
656 static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req)
657 {
658 /* no handle... */
659 }
660
668 static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req)
669 {
670 uint8_t *psetup = pudev->dev.setup_packet;
671
672 req->bmRequestType = *psetup;
673 req->bRequest = *(uint8_t *)(psetup + 1U);
674 req->wValue = SWAPBYTE (psetup + 2U);
675 req->wIndex = SWAPBYTE (psetup + 4U);
676 req->wLength = SWAPBYTE (psetup + 6U);
677
678 pudev->dev.ctl_len = req->wLength;
679 }
680
688 void usbd_enum_error(usb_core_handle_struct *pudev, usb_device_req_struct *req)
689 {
690 usbd_ep_stall(pudev, 0x80U);
691 usbd_ep_stall(pudev, 0x00U);
692 usb_ep0_startout(pudev);
693 }
USB_CLASS_REQ
#define USB_CLASS_REQ
Definition: usb_std.h:31
usbd_std.h
USB 2.0 standard defines.
USB_TX
Definition: usb_core.h:95
usb_device_req_struct::wIndex
uint16_t wIndex
Definition: usb_core.h:119
usbd_out_transaction
usbd_status_enum usbd_out_transaction(usb_core_handle_struct *pudev, uint8_t endp_num)
data out stage processing
Definition: usbd_std.c:103
USBD_OK
Definition: usb_core.h:74
usb_device_req_struct::wLength
uint16_t wLength
Definition: usb_core.h:120
usbd_ctltx
usbd_status_enum usbd_ctltx(usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len)
transmit data on the control channel
Definition: usbd_core.c:312
USB_STANDARD_REQ
#define USB_STANDARD_REQ
Definition: usb_std.h:30
USB_REQTYPE_INTERFACE
#define USB_REQTYPE_INTERFACE
Definition: usb_std.h:37
USB_STATUS_CONFIGURED
#define USB_STATUS_CONFIGURED
Definition: usbd_core.h:22
usbd_ctlstatus_rx
usbd_status_enum usbd_ctlstatus_rx(usb_core_handle_struct *pudev)
receive status on the control channel
Definition: usbd_core.c:367
IS_NOT_EP0
#define IS_NOT_EP0(ep_addr)
Definition: usbd_std.h:58
usb_device_req_struct
Definition: usb_core.h:114
USB_CTRL_DATA_IN
Definition: usb_core.h:84
USB_CTRL_DATA_OUT
Definition: usb_core.h:85
USB_FEATURE_ENDP_HALT
#define USB_FEATURE_ENDP_HALT
Definition: usbd_std.h:30
USB_REQTYPE_MASK
#define USB_REQTYPE_MASK
Definition: usb_std.h:39
usbd_ep_tx
void usbd_ep_tx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
endpoint prepare to transmit data
Definition: usbd_core.c:230
USB_SET_DEVADDR
#define USB_SET_DEVADDR(DevAddr)
Definition: usb_regs.h:605
usb_device_req_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_core.h:116
usb_ep_struct::endp_mps
uint32_t endp_mps
Definition: usb_core.h:103
usbd_ep_stall
void usbd_ep_stall(usb_core_handle_struct *pudev, uint8_t ep_addr)
set an endpoint to STALL status
Definition: usbd_core.c:385
USB_REQ_MASK
#define USB_REQ_MASK
Definition: usb_std.h:33
usbd_setup_transaction
usbd_status_enum usbd_setup_transaction(usb_core_handle_struct *pudev)
USB setup stage processing.
Definition: usbd_std.c:69
USB_RX
Definition: usb_core.h:94
usbd_ep_rx
void usbd_ep_rx(usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
endpoint prepare to receive data
Definition: usbd_core.c:161
SWAPBYTE
#define SWAPBYTE(addr)
Definition: usb_std.h:85
usb_ep_struct
Definition: usb_core.h:99
usbd_ctlstatus_tx
usbd_status_enum usbd_ctlstatus_tx(usb_core_handle_struct *pudev)
transmit status on the control channel
Definition: usbd_core.c:350
USB_FEATURE_REMOTE_WAKEUP
#define USB_FEATURE_REMOTE_WAKEUP
Definition: usbd_std.h:31
LOWBYTE
#define LOWBYTE(x)
Definition: usbd_std.h:39
usb_core.h
USB core driver header file.
usbd_status_enum
usbd_status_enum
Definition: usb_core.h:72
USB_MIN
#define USB_MIN(a, b)
Definition: usbd_std.h:42
usbd_ep_clear_stall
void usbd_ep_clear_stall(usb_core_handle_struct *pudev, uint8_t ep_addr)
clear endpoint stalled status
Definition: usbd_core.c:415
usb_core_handle_struct
Definition: usb_core.h:200
USB_REQTYPE_DEVICE
#define USB_REQTYPE_DEVICE
Definition: usb_std.h:36
NULL
#define NULL
Definition: usb_defines.h:18
usbd_enum_error
void usbd_enum_error(usb_core_handle_struct *pudev, usb_device_req_struct *req)
handle USB low level error event
Definition: usbd_std.c:688
usb_device_req_struct::bRequest
uint8_t bRequest
Definition: usb_core.h:117
USB_STATUS_DEFAULT
#define USB_STATUS_DEFAULT
Definition: usbd_core.h:20
USB_REQTYPE_ENDPOINT
#define USB_REQTYPE_ENDPOINT
Definition: usb_std.h:38
usbd_in_transaction
usbd_status_enum usbd_in_transaction(usb_core_handle_struct *pudev, uint8_t endp_num)
data in stage processing
Definition: usbd_std.c:142
usb_device_req_struct::wValue
uint16_t wValue
Definition: usb_core.h:118
USB_STATUS_ADDRESSED
#define USB_STATUS_ADDRESSED
Definition: usbd_core.h:21
USB_DCTL
#define USB_DCTL
Definition: usb_regs.h:66
usb_ep_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:106
USB_FEATURE_TEST_MODE
#define USB_FEATURE_TEST_MODE
Definition: usbd_std.h:32
USB_VENDOR_REQ
#define USB_VENDOR_REQ
Definition: usb_std.h:32
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_wwdgt.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_wwdgt.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_WWDGT_H
13 #define GD32F3X0_WWDGT_H
14
15 #include "gd32f3x0.h"
16
17 /* WWDGT definitions */
18 #define WWDGT WWDGT_BASE
19
20 /* registers definitions */
21 #define WWDGT_CTL REG32((WWDGT) + 0x00U)
22 #define WWDGT_CFG REG32((WWDGT) + 0x04U)
23 #define WWDGT_STAT REG32((WWDGT) + 0x08U)
25 /* bits definitions */
26 /* WWDGT_CTL */
27 #define WWDGT_CTL_CNT BITS(0,6)
28 #define WWDGT_CTL_WDGTEN BIT(7)
30 /* WWDGT_CFG */
31 #define WWDGT_CFG_WIN BITS(0,6)
32 #define WWDGT_CFG_PSC BITS(7,8)
33 #define WWDGT_CFG_EWIE BIT(9)
35 /* WWDGT_STAT */
36 #define WWDGT_STAT_EWIF BIT(0)
38 /* constants definitions */
39 /* WWDGT_CTL register value */
40 #define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
42 /* WWDGT_CFG register value */
43 #define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
45 #define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U))
46 #define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0))
47 #define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1))
48 #define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2))
49 #define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3))
51 /* function declarations */
52 /* reset the window watchdog timer configuration */
53 void wwdgt_deinit(void);
54 /* start the window watchdog timer counter */
55 void wwdgt_enable(void);
56
57 /* configure the window watchdog timer counter value */
58 void wwdgt_counter_update(uint16_t counter_value);
59 /* configure counter value, window value, and prescaler divider value */
60 void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
61
62 /* enable early wakeup interrupt of WWDGT */
63 void wwdgt_interrupt_enable(void);
64 /* check early wakeup interrupt state of WWDGT */
65 FlagStatus wwdgt_flag_get(void);
66 /* clear early wakeup interrupt state of WWDGT */
67 void wwdgt_flag_clear(void);
68
69 #endif /* GD32F3X0_WWDGT_H */
wwdgt_deinit
void wwdgt_deinit(void)
reset the window watchdog timer configuration
Definition: gd32f3x0_wwdgt.c:21
wwdgt_enable
void wwdgt_enable(void)
start the window watchdog timer counter
Definition: gd32f3x0_wwdgt.c:49
wwdgt_counter_update
void wwdgt_counter_update(uint16_t counter_value)
configure the window watchdog timer counter value
Definition: gd32f3x0_wwdgt.c:33
wwdgt_flag_clear
void wwdgt_flag_clear(void)
clear early wakeup interrupt state of WWDGT
Definition: gd32f3x0_wwdgt.c:114
wwdgt_config
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
configure counter value, window value, and prescaler divider value
Definition: gd32f3x0_wwdgt.c:66
wwdgt_interrupt_enable
void wwdgt_interrupt_enable(void)
enable early wakeup interrupt of WWDGT
Definition: gd32f3x0_wwdgt.c:89
wwdgt_flag_get
FlagStatus wwdgt_flag_get(void)
check early wakeup interrupt state of WWDGT
Definition: gd32f3x0_wwdgt.c:100
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbh_ctrl.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
usbh_ctrl.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "usbh_core.h"
13 #include "usbh_std.h"
14 #include "usbh_ctrl.h"
15
16 uint8_t ctrl_polling_handle_flag = 0U;
17 uint8_t ctrl_setup_wait_flag = 0U;
18 uint8_t ctrl_data_wait_flag = 0U;
19 uint8_t ctrl_status_wait_flag = 0U;
20
21 static uint16_t timeout = 0U;
22
23 static void ctrl_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
24 static void ctrl_setup_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
25 static void ctrl_data_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
26 static void ctrl_status_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
27 static void ctrl_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
28 static void ctrl_stalled_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
29 static void ctrl_complete_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
30
31 /* the ctrl state handle function array */
32 void (*ctrl_state_handle[]) (usb_core_handle_struct *pudev,
33 usbh_host_struct *puhost,
34 usbh_state_handle_struct *pustate) =
35 {
36 ctrl_idle_handle,
37 ctrl_setup_handle,
38 ctrl_data_handle,
39 ctrl_status_handle,
40 ctrl_error_handle,
41 ctrl_stalled_handle,
42 ctrl_complete_handle,
43 };
44
45 /* the ctrl state handle table */
46 state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE] =
47 {
48 /* the current state the current event the next state the event function */
49 {CTRL_IDLE, CTRL_EVENT_SETUP, CTRL_SETUP, only_state_move },
50 {CTRL_SETUP, CTRL_EVENT_DATA, CTRL_DATA, only_state_move },
51 {CTRL_SETUP, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move },
52 {CTRL_SETUP, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move },
53 {CTRL_DATA, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move },
54 {CTRL_DATA, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move },
55 {CTRL_DATA, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move },
56 {CTRL_STATUS, CTRL_EVENT_COMPLETE, CTRL_COMPLETE, only_state_move },
57 {CTRL_STATUS, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move },
58 {CTRL_STATUS, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move },
59 {CTRL_ERROR, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
60 {CTRL_STALLED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
61 {CTRL_COMPLETE, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun },
62 };
63
72 usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev,
73 usbh_host_struct *puhost,
74 void *pustate)
75 {
76 usbh_status_enum exe_state = USBH_BUSY;
77 usbh_state_handle_struct *p_state;
78
79 p_state = (usbh_state_handle_struct *)pustate;
80
81 /* if first enter this function, begin the ctrl state */
82 if (0U == ctrl_polling_handle_flag) {
83 ctrl_polling_handle_flag = 1U;
84 scd_table_push(p_state);
85 scd_state_move(p_state, CTRL_IDLE);
86 }
87
88 /* base on the current state to handle the ctrl state */
89 scd_begin(p_state, CTRL_FSM_ID);
90 ctrl_state_handle[p_state->usbh_current_state](pudev, puhost, p_state);
91
92 /* determine the control transfer whether to complete */
93 switch (puhost->usbh_backup_state.ctrl_backup_state) {
94 case CTRL_COMPLETE:
95 ctrl_polling_handle_flag = 0U;
96 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
97 exe_state = USBH_OK;
98 break;
99 case CTRL_STALLED:
100 ctrl_polling_handle_flag = 0U;
101 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
102 exe_state = USBH_NOT_SUPPORTED;
103 break;
104 case CTRL_ERROR:
105 ctrl_polling_handle_flag = 0U;
106 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
107 exe_state = USBH_FAIL;
108 break;
109 default:
110 exe_state = USBH_BUSY;
111 break;
112 }
113
114 return exe_state;
115 }
116
125 static void ctrl_idle_handle (usb_core_handle_struct *pudev,
126 usbh_host_struct *puhost,
127 usbh_state_handle_struct *pustate)
128 {
129 puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE;
130 scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state);
131 }
132
141 static void ctrl_setup_handle (usb_core_handle_struct *pudev,
142 usbh_host_struct *puhost,
143 usbh_state_handle_struct *pustate)
144 {
145 urb_state_enum urb_status = URB_IDLE;
146 puhost->usbh_backup_state.ctrl_backup_state = CTRL_SETUP;
147
148 if (0U == ctrl_setup_wait_flag) {
149 ctrl_setup_wait_flag = 1U;
150
151 /* send a setup packet */
152 usbh_ctltx_setup (pudev,
153 puhost->control.setup.data,
154 puhost->control.hc_out_num);
155 } else {
156 urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num);
157
158 /* case setup packet sent successfully */
159 if (URB_DONE == urb_status) {
160 /* check if there is a data stage */
161 if (0U != puhost->control.setup.b.wLength) {
162 ctrl_setup_wait_flag = 0U;
163 timeout = DATA_STAGE_TIMEOUT;
164 scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_DATA, pustate->usbh_current_state);
165 /* no data stage */
166 } else {
167 timeout = NODATA_STAGE_TIMEOUT;
168 ctrl_setup_wait_flag = 0U;
169 scd_event_handle(pudev,
170 puhost,
171 pustate,
172 CTRL_EVENT_STATUS,
173 pustate->usbh_current_state);
174 }
175
176 /* set the delay timer to enable timeout for data stage completion */
177 puhost->control.timer = (uint16_t)USB_CURRENT_FRAME_GET();
178 } else if (URB_ERROR == urb_status) {
179 ctrl_setup_wait_flag = 0U;
180 scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_ERROR, pustate->usbh_current_state);
181 } else {
182 /* no operation */
183 }
184 }
185 }
186
195 static void ctrl_data_handle (usb_core_handle_struct *pudev,
196 usbh_host_struct *puhost,
197 usbh_state_handle_struct *pustate)
198 {
199 uint8_t direction;
200 urb_state_enum urb_status = URB_IDLE;
201 puhost->usbh_backup_state.ctrl_backup_state = CTRL_DATA;
202
203 direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK);
204
205 if (USB_DIR_IN == direction) {
206 if (0U == ctrl_data_wait_flag) {
207 ctrl_data_wait_flag = 1U;
208
209 /* issue an IN token */
210 usbh_xfer(pudev,
211 puhost->control.buff,
212 puhost->control.hc_in_num,
213 puhost->control.length);
214 } else {
215 urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num);
216
217 /* check is data packet transfered successfully */
218 switch (urb_status) {
219 case URB_DONE:
220 ctrl_data_wait_flag = 0U;
221
222 scd_event_handle(pudev,
223 puhost,
224 pustate,
225 CTRL_EVENT_STATUS,
226 pustate->usbh_current_state);
227 break;
228 case URB_STALL:
229 ctrl_data_wait_flag = 0U;
230
231 scd_event_handle(pudev,
232 puhost,
233 pustate,
234 CTRL_EVENT_STALLED,
235 pustate->usbh_current_state);
236 break;
237 case URB_ERROR:
238 ctrl_data_wait_flag = 0U;
239
240 /* device error */
241 scd_event_handle(pudev,
242 puhost,
243 pustate,
244 CTRL_EVENT_ERROR,
245 pustate->usbh_current_state);
246 break;
247 default:
248 if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) {
249 ctrl_data_wait_flag = 0U;
250
251 /* timeout for IN transfer */
252 scd_event_handle(pudev,
253 puhost,
254 pustate,
255 CTRL_EVENT_ERROR,
256 pustate->usbh_current_state);
257 }
258 break;
259 }
260 }
261 } else {
262 if (0U == ctrl_data_wait_flag) {
263 ctrl_data_wait_flag = 1U;
264
265 /* start DATA out transfer (only one DATA packet)*/
266 pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out = 1U;
267
268 usbh_xfer(pudev,
269 puhost->control.buff,
270 puhost->control.hc_out_num,
271 puhost->control.length);
272 } else {
273 urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num);
274
275 switch (urb_status) {
276 case URB_DONE:
277 ctrl_data_wait_flag = 0U;
278
279 /* if the setup pkt is sent successful, then change the state */
280 scd_event_handle(pudev,
281 puhost,
282 pustate,
283 CTRL_EVENT_STATUS,
284 pustate->usbh_current_state);
285 break;
286 case URB_STALL:
287 ctrl_data_wait_flag = 0U;
288
289 scd_event_handle(pudev,
290 puhost,
291 pustate,
292 CTRL_EVENT_STALLED,
293 pustate->usbh_current_state);
294 break;
295 case URB_NOTREADY:
296 /* nack received from device */
297 ctrl_data_wait_flag = 0U;
298 break;
299 case URB_ERROR:
300 ctrl_data_wait_flag = 0U;
301
302 /* device error */
303 scd_event_handle(pudev,
304 puhost,
305 pustate,
306 CTRL_EVENT_ERROR,
307 pustate->usbh_current_state);
308 break;
309 default:
310 break;
311 }
312 }
313 }
314 }
315
324 static void ctrl_status_handle (usb_core_handle_struct *pudev,
325 usbh_host_struct *puhost,
326 usbh_state_handle_struct *pustate)
327 {
328 uint8_t direction;
329 urb_state_enum urb_status = URB_IDLE;
330
331 puhost->usbh_backup_state.ctrl_backup_state = CTRL_STATUS;
332
333 /* get the transfer direction in the data state, but the transfer direction in the status state is opposite */
334 direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK);
335
336 if (USB_DIR_OUT == direction) {
337 /* handle status in */
338 if (0U == ctrl_status_wait_flag) {
339 ctrl_status_wait_flag = 1U;
340 usbh_xfer (pudev, 0U, puhost->control.hc_in_num, 0U);
341 } else {
342 urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num);
343
344 switch (urb_status) {
345 case URB_DONE:
346 ctrl_status_wait_flag = 0U;
347
348 /* handle URB_DONE status */
349 scd_event_handle(pudev,
350 puhost,
351 pustate,
352 CTRL_EVENT_COMPLETE,
353 pustate->usbh_current_state);
354 break;
355 case URB_ERROR:
356 ctrl_status_wait_flag = 0U;
357
358 /* handle URB_STALL status*/
359 scd_event_handle(pudev,
360 puhost,
361 pustate,
362 CTRL_EVENT_ERROR,
363 pustate->usbh_current_state);
364 break;
365 case URB_STALL:
366 ctrl_status_wait_flag = 0U;
367
368 /* handle URB_STALL status */
369 scd_event_handle(pudev,
370 puhost,
371 pustate,
372 CTRL_EVENT_STALLED,
373 pustate->usbh_current_state);
374 break;
375 default:
376 if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) {
377 ctrl_status_wait_flag = 0U;
378
379 /* handle timeout */
380 scd_event_handle(pudev,
381 puhost,
382 pustate,
383 CTRL_EVENT_ERROR,
384 pustate->usbh_current_state);
385 }
386 break;
387 }
388 }
389 } else {
390 /* handle status out */
391 if (0U == ctrl_status_wait_flag) {
392 ctrl_status_wait_flag = 1U;
393 pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out ^= 1U;
394 usbh_xfer (pudev, 0U, puhost->control.hc_out_num, 0U);
395 } else {
396 urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num);
397
398 switch (urb_status) {
399 case URB_DONE:
400 ctrl_status_wait_flag = 0U;
401
402 /* handle URB_DONE status */
403 scd_event_handle(pudev,
404 puhost,
405 pustate,
406 CTRL_EVENT_COMPLETE,
407 pustate->usbh_current_state);
408 break;
409 case URB_NOTREADY:
410 /* handle URB_NOTREADY status */
411 ctrl_status_wait_flag = 0U;
412 break;
413 case URB_ERROR:
414 ctrl_status_wait_flag = 0U;
415
416 /* handle URB_ERROR status */
417 scd_event_handle(pudev,
418 puhost,
419 pustate,
420 CTRL_EVENT_ERROR,
421 pustate->usbh_current_state);
422 break;
423 default:
424 break;
425 }
426 }
427 }
428 }
429
438 static void ctrl_error_handle (usb_core_handle_struct *pudev,
439 usbh_host_struct *puhost,
440 usbh_state_handle_struct *pustate)
441 {
442 puhost->usbh_backup_state.ctrl_backup_state = CTRL_ERROR;
443
444 if (++puhost->control.error_count <= USBH_MAX_ERROR_COUNT) {
445 /* do the transmission again, starting from SETUP Packet */
446 scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state);
447 } else {
448 scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state);
449 }
450 }
451
460 static void ctrl_stalled_handle (usb_core_handle_struct *pudev,
461 usbh_host_struct *puhost,
462 usbh_state_handle_struct *pustate)
463 {
464 puhost->usbh_backup_state.ctrl_backup_state = CTRL_STALLED;
465 scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state);
466 }
467
476 static void ctrl_complete_handle (usb_core_handle_struct *pudev,
477 usbh_host_struct *puhost,
478 usbh_state_handle_struct *pustate)
479 {
480 puhost->usbh_backup_state.ctrl_backup_state = CTRL_COMPLETE;
481 scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state);
482 }
483
493 usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev,
494 uint8_t *buf,
495 uint8_t hc_num,
496 uint16_t len)
497 {
498 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
499
500 puhc->xfer_buff = buf;
501 puhc->xfer_len = len;
502
503 switch (puhc->endp_type) {
504 case USB_EPTYPE_CTRL:
505 if (0U == puhc->endp_in) {
506 if (0U == len) {
507 /* for status out stage, length = 0, status out pid = 1 */
508 puhc->data_tg_out = 1U;
509 }
510
511 /* set the data toggle bit as per the flag */
512 if (0U == puhc->data_tg_out) {
513 /* put the pid 0 */
514 puhc->DPID = HC_PID_DATA0;
515 } else {
516 /* put the pid 1 */
517 puhc->DPID = HC_PID_DATA1;
518 }
519 } else {
520 puhc->DPID = HC_PID_DATA1;
521 }
522 break;
523
524 case USB_EPTYPE_ISOC:
525 puhc->DPID = HC_PID_DATA0;
526 break;
527
528 case USB_EPTYPE_BULK:
529 if (0U == puhc->endp_in) {
530 /* set the data toggle bit as per the flag */
531 if (0U == puhc->data_tg_out) {
532 /* put the pid 0 */
533 puhc->DPID = HC_PID_DATA0;
534 } else {
535 /* put the pid 1 */
536 puhc->DPID = HC_PID_DATA1;
537 }
538 } else {
539 if (0U == puhc->data_tg_in) {
540 puhc->DPID = HC_PID_DATA0;
541 } else {
542 puhc->DPID = HC_PID_DATA1;
543 }
544 }
545 break;
546
547 case USB_EPTYPE_INTR:
548 if (0U == puhc->endp_in) {
549 if (0U == puhc->data_tg_out) {
550 puhc->DPID = HC_PID_DATA0;
551 } else {
552 puhc->DPID = HC_PID_DATA1;
553 }
554
555 /* toggle data pid */
556 puhc->data_tg_out ^= 1U;
557 } else {
558 if (0U == puhc->data_tg_in) {
559 puhc->DPID = HC_PID_DATA0;
560 } else {
561 puhc->DPID = HC_PID_DATA1;
562 }
563
564 /* toggle data pid */
565 puhc->data_tg_in ^= 1U;
566 }
567 break;
568
569 default:
570 break;
571 }
572
573 hcd_submit_request (pudev, hc_num);
574
575 return USBH_OK;
576 }
577
586 usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num)
587 {
588 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
589
590 puhc->DPID = HC_PID_SETUP;
591 puhc->xfer_buff = buf;
592 puhc->xfer_len = USBH_SETUP_PACKET_SIZE;
593
594 return (usbh_status_enum)hcd_submit_request (pudev, hc_num);
595 }
596
604 uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num)
605 {
606 usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num];
607
608 puhc->urb_state = URB_IDLE;
609 puhc->xfer_count = 0U;
610
611 return (uint32_t)usb_hostchannel_startxfer(pudev, channel_num);
612 }
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
goto_up_state_fun
usbh_status_enum goto_up_state_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state
Definition: usbh_core.c:705
hcd_urb_state_get
urb_state_enum hcd_urb_state_get(usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate
Definition: usbh_core.c:429
usbh_core.h
header file for usbh_core.c
usbh_std.h
header file for usbh_std.c
URB_STALL
Definition: usb_core.h:54
usbh_xfer
usbh_status_enum usbh_xfer(usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len)
send datas from the host channel
Definition: usbh_ctrl.c:493
usb_hostchannel_struct::urb_state
urb_state_enum urb_state
Definition: usb_core.h:172
usbh_state_handle_struct
Definition: usbh_core.h:227
hcd_submit_request
uint32_t hcd_submit_request(usb_core_handle_struct *pudev, uint8_t channel_num)
this function prepare a hc and start a transfer
Definition: usbh_ctrl.c:604
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:52
ctrl_state_handle
void(* ctrl_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_ctrl.c:32
CTRL_EVENT_ERROR
Definition: usbh_ctrl.h:31
backup_state_struct::ctrl_backup_state
ctrl_state_enum ctrl_backup_state
Definition: usbh_core.h:182
CTRL_IDLE
Definition: usbh_core.h:96
urb_state_enum
urb_state_enum
Definition: usb_core.h:48
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:165
usb_hostchannel_struct::data_tg_out
uint8_t data_tg_out
Definition: usb_core.h:175
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:113
CTRL_ERROR
Definition: usbh_core.h:100
usbh_ctrl_struct::timer
uint16_t timer
Definition: usbh_core.h:132
ctrl_status_wait_flag
uint8_t ctrl_status_wait_flag
Definition: usbh_ctrl.c:19
CTRL_FSM_ID
#define CTRL_FSM_ID
Definition: usbh_core.h:41
usbh_ctrl_struct::hc_in_num
uint8_t hc_in_num
Definition: usbh_core.h:127
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:54
usbh_ctrl_struct::buff
uint8_t * buff
Definition: usbh_core.h:133
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:160
ctrl_polling_handle_flag
uint8_t ctrl_polling_handle_flag
Definition: usbh_ctrl.c:16
USB_EPTYPE_CTRL
#define USB_EPTYPE_CTRL
Definition: usb_defines.h:51
USBH_NOT_SUPPORTED
Definition: usbh_core.h:111
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:106
usbh_host_struct
Definition: usbh_core.h:188
HC_PID_DATA1
#define HC_PID_DATA1
Definition: usb_defines.h:70
CTRL_HANDLE_TABLE_SIZE
#define CTRL_HANDLE_TABLE_SIZE
Definition: usbh_ctrl.h:18
URB_IDLE
Definition: usb_core.h:50
NODATA_STAGE_TIMEOUT
#define NODATA_STAGE_TIMEOUT
Definition: usb_std.h:100
URB_NOTREADY
Definition: usb_core.h:52
usb_setup_union::data
uint8_t data[8]
Definition: usb_std.h:109
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:117
UP_STATE
#define UP_STATE
Definition: usbh_core.h:45
CTRL_EVENT_SETUP
Definition: usbh_ctrl.h:27
GO_TO_UP_STATE_EVENT
#define GO_TO_UP_STATE_EVENT
Definition: usbh_core.h:46
usbh_ctltx_setup
usbh_status_enum usbh_ctltx_setup(usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num)
send the setup packet to the device
Definition: usbh_ctrl.c:586
USB_DIR_OUT
#define USB_DIR_OUT
Definition: usb_std.h:26
USBH_MAX_ERROR_COUNT
#define USBH_MAX_ERROR_COUNT
Definition: usbh_core.h:26
CTRL_STATUS
Definition: usbh_core.h:99
usb_hostchannel_struct
Definition: usb_core.h:154
USBH_SETUP_PACKET_SIZE
#define USBH_SETUP_PACKET_SIZE
Definition: usbh_std.h:22
usbh_ctrl.h
header file for usbh_ctrl.c
DATA_STAGE_TIMEOUT
#define DATA_STAGE_TIMEOUT
Definition: usb_std.h:99
usbh_ctrl_struct::error_count
uint8_t error_count
Definition: usbh_core.h:130
CTRL_STALLED
Definition: usbh_core.h:101
usb_hostchannel_struct::data_tg_in
uint8_t data_tg_in
Definition: usb_core.h:174
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:561
HC_PID_DATA0
#define HC_PID_DATA0
Definition: usb_defines.h:68
ctrl_data_wait_flag
uint8_t ctrl_data_wait_flag
Definition: usbh_ctrl.c:18
ctrl_state_polling_fun
usbh_status_enum ctrl_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of CTRL state
Definition: usbh_ctrl.c:72
USB_CURRENT_FRAME_GET
#define USB_CURRENT_FRAME_GET()
Definition: usb_regs.h:620
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:538
state_table_struct
Definition: usbh_core.h:202
usb_hostchannel_struct::DPID
uint8_t DPID
Definition: usb_core.h:158
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:166
scd_event_handle
usbh_status_enum scd_event_handle(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate, uint8_t event, uint8_t state)
state core driver event handle
Definition: usbh_core.c:576
usbh_host_struct::usbh_backup_state
backup_state_struct usbh_backup_state
Definition: usbh_core.h:190
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:622
CTRL_EVENT_DATA
Definition: usbh_ctrl.h:28
USB_DIR_IN
#define USB_DIR_IN
Definition: usb_std.h:27
usbh_ctrl_struct::length
uint16_t length
Definition: usbh_core.h:131
usb_core_handle_struct
Definition: usb_core.h:200
URB_ERROR
Definition: usb_core.h:53
CTRL_EVENT_STALLED
Definition: usbh_ctrl.h:32
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:692
ctrl_setup_wait_flag
uint8_t ctrl_setup_wait_flag
Definition: usbh_ctrl.c:17
USBH_OK
Definition: usbh_core.h:108
CTRL_SETUP
Definition: usbh_core.h:97
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:161
CTRL_EVENT_COMPLETE
Definition: usbh_ctrl.h:30
USB_DIR_MASK
#define USB_DIR_MASK
Definition: usb_std.h:25
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:191
USBH_FAIL
Definition: usbh_core.h:110
URB_DONE
Definition: usb_core.h:51
CTRL_COMPLETE
Definition: usbh_core.h:102
usb_hostchannel_struct::xfer_count
uint32_t xfer_count
Definition: usb_core.h:167
usbh_ctrl_struct::hc_out_num
uint8_t hc_out_num
Definition: usbh_core.h:128
USBH_BUSY
Definition: usbh_core.h:109
ctrl_handle_table
state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]
Definition: usbh_ctrl.c:46
CTRL_DATA
Definition: usbh_core.h:98
HC_PID_SETUP
#define HC_PID_SETUP
Definition: usb_defines.h:71
usbh_ctrl_struct::setup
usb_setup_union setup
Definition: usbh_core.h:134
CTRL_EVENT_STATUS
Definition: usbh_ctrl.h:29
usb_setup_union::b
struct usb_setup_union::_setup_packet_struct b
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:53
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_gpio.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_gpio.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_GPIO_H
13 #define GD32F3X0_GPIO_H
14
15 #include "gd32f3x0.h"
16
17 /* GPIOx(x=A,B,C,D,F) definitions */
18 #define GPIOA (GPIO_BASE + 0x00000000U)
19 #define GPIOB (GPIO_BASE + 0x00000400U)
20 #define GPIOC (GPIO_BASE + 0x00000800U)
21 #define GPIOD (GPIO_BASE + 0x00000C00U)
22 #define GPIOF (GPIO_BASE + 0x00001400U)
23
24 /* registers definitions */
25 #define GPIO_CTL(gpiox) REG32((gpiox) + 0x00U)
26 #define GPIO_OMODE(gpiox) REG32((gpiox) + 0x04U)
27 #define GPIO_OSPD0(gpiox) REG32((gpiox) + 0x08U)
28 #define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU)
29 #define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U)
30 #define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U)
31 #define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U)
32 #define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU)
33 #define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U)
34 #define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U)
35 #define GPIO_BC(gpiox) REG32((gpiox) + 0x28U)
36 #define GPIO_TG(gpiox) REG32((gpiox) + 0x2CU)
37 #define GPIO_OSPD1(gpiox) REG32((gpiox) + 0x3CU)
39 /* bits definitions */
40 /* GPIO_CTL */
41 #define GPIO_CTL_CTL0 BITS(0,1)
42 #define GPIO_CTL_CTL1 BITS(2,3)
43 #define GPIO_CTL_CTL2 BITS(4,5)
44 #define GPIO_CTL_CTL3 BITS(6,7)
45 #define GPIO_CTL_CTL4 BITS(8,9)
46 #define GPIO_CTL_CTL5 BITS(10,11)
47 #define GPIO_CTL_CTL6 BITS(12,13)
48 #define GPIO_CTL_CTL7 BITS(14,15)
49 #define GPIO_CTL_CTL8 BITS(16,17)
50 #define GPIO_CTL_CTL9 BITS(18,19)
51 #define GPIO_CTL_CTL10 BITS(20,21)
52 #define GPIO_CTL_CTL11 BITS(22,23)
53 #define GPIO_CTL_CTL12 BITS(24,25)
54 #define GPIO_CTL_CTL13 BITS(26,27)
55 #define GPIO_CTL_CTL14 BITS(28,29)
56 #define GPIO_CTL_CTL15 BITS(30,31)
58 /* GPIO_OMODE */
59 #define GPIO_OMODE_OM0 BIT(0)
60 #define GPIO_OMODE_OM1 BIT(1)
61 #define GPIO_OMODE_OM2 BIT(2)
62 #define GPIO_OMODE_OM3 BIT(3)
63 #define GPIO_OMODE_OM4 BIT(4)
64 #define GPIO_OMODE_OM5 BIT(5)
65 #define GPIO_OMODE_OM6 BIT(6)
66 #define GPIO_OMODE_OM7 BIT(7)
67 #define GPIO_OMODE_OM8 BIT(8)
68 #define GPIO_OMODE_OM9 BIT(9)
69 #define GPIO_OMODE_OM10 BIT(10)
70 #define GPIO_OMODE_OM11 BIT(11)
71 #define GPIO_OMODE_OM12 BIT(12)
72 #define GPIO_OMODE_OM13 BIT(13)
73 #define GPIO_OMODE_OM14 BIT(14)
74 #define GPIO_OMODE_OM15 BIT(15)
76 /* GPIO_OSPD0 */
77 #define GPIO_OSPD0_OSPD0 BITS(0,1)
78 #define GPIO_OSPD0_OSPD1 BITS(2,3)
79 #define GPIO_OSPD0_OSPD2 BITS(4,5)
80 #define GPIO_OSPD0_OSPD3 BITS(6,7)
81 #define GPIO_OSPD0_OSPD4 BITS(8,9)
82 #define GPIO_OSPD0_OSPD5 BITS(10,11)
83 #define GPIO_OSPD0_OSPD6 BITS(12,13)
84 #define GPIO_OSPD0_OSPD7 BITS(14,15)
85 #define GPIO_OSPD0_OSPD8 BITS(16,17)
86 #define GPIO_OSPD0_OSPD9 BITS(18,19)
87 #define GPIO_OSPD0_OSPD10 BITS(20,21)
88 #define GPIO_OSPD0_OSPD11 BITS(22,23)
89 #define GPIO_OSPD0_OSPD12 BITS(24,25)
90 #define GPIO_OSPD0_OSPD13 BITS(26,27)
91 #define GPIO_OSPD0_OSPD14 BITS(28,29)
92 #define GPIO_OSPD0_OSPD15 BITS(30,31)
94 /* GPIO_PUD */
95 #define GPIO_PUD_PUD0 BITS(0,1)
96 #define GPIO_PUD_PUD1 BITS(2,3)
97 #define GPIO_PUD_PUD2 BITS(4,5)
98 #define GPIO_PUD_PUD3 BITS(6,7)
99 #define GPIO_PUD_PUD4 BITS(8,9)
100 #define GPIO_PUD_PUD5 BITS(10,11)
101 #define GPIO_PUD_PUD6 BITS(12,13)
102 #define GPIO_PUD_PUD7 BITS(14,15)
103 #define GPIO_PUD_PUD8 BITS(16,17)
104 #define GPIO_PUD_PUD9 BITS(18,19)
105 #define GPIO_PUD_PUD10 BITS(20,21)
106 #define GPIO_PUD_PUD11 BITS(22,23)
107 #define GPIO_PUD_PUD12 BITS(24,25)
108 #define GPIO_PUD_PUD13 BITS(26,27)
109 #define GPIO_PUD_PUD14 BITS(28,29)
110 #define GPIO_PUD_PUD15 BITS(30,31)
112 /* GPIO_ISTAT */
113 #define GPIO_ISTAT_ISTAT0 BIT(0)
114 #define GPIO_ISTAT_ISTAT1 BIT(1)
115 #define GPIO_ISTAT_ISTAT2 BIT(2)
116 #define GPIO_ISTAT_ISTAT3 BIT(3)
117 #define GPIO_ISTAT_ISTAT4 BIT(4)
118 #define GPIO_ISTAT_ISTAT5 BIT(5)
119 #define GPIO_ISTAT_ISTAT6 BIT(6)
120 #define GPIO_ISTAT_ISTAT7 BIT(7)
121 #define GPIO_ISTAT_ISTAT8 BIT(8)
122 #define GPIO_ISTAT_ISTAT9 BIT(9)
123 #define GPIO_ISTAT_ISTAT10 BIT(10)
124 #define GPIO_ISTAT_ISTAT11 BIT(11)
125 #define GPIO_ISTAT_ISTAT12 BIT(12)
126 #define GPIO_ISTAT_ISTAT13 BIT(13)
127 #define GPIO_ISTAT_ISTAT14 BIT(14)
128 #define GPIO_ISTAT_ISTAT15 BIT(15)
130 /* GPIO_OCTL */
131 #define GPIO_OCTL_OCTL0 BIT(0)
132 #define GPIO_OCTL_OCTL1 BIT(1)
133 #define GPIO_OCTL_OCTL2 BIT(2)
134 #define GPIO_OCTL_OCTL3 BIT(3)
135 #define GPIO_OCTL_OCTL4 BIT(4)
136 #define GPIO_OCTL_OCTL5 BIT(5)
137 #define GPIO_OCTL_OCTL6 BIT(6)
138 #define GPIO_OCTL_OCTL7 BIT(7)
139 #define GPIO_OCTL_OCTL8 BIT(8)
140 #define GPIO_OCTL_OCTL9 BIT(9)
141 #define GPIO_OCTL_OCTL10 BIT(10)
142 #define GPIO_OCTL_OCTL11 BIT(11)
143 #define GPIO_OCTL_OCTL12 BIT(12)
144 #define GPIO_OCTL_OCTL13 BIT(13)
145 #define GPIO_OCTL_OCTL14 BIT(14)
146 #define GPIO_OCTL_OCTL15 BIT(15)
148 /* GPIO_BOP */
149 #define GPIO_BOP_BOP0 BIT(0)
150 #define GPIO_BOP_BOP1 BIT(1)
151 #define GPIO_BOP_BOP2 BIT(2)
152 #define GPIO_BOP_BOP3 BIT(3)
153 #define GPIO_BOP_BOP4 BIT(4)
154 #define GPIO_BOP_BOP5 BIT(5)
155 #define GPIO_BOP_BOP6 BIT(6)
156 #define GPIO_BOP_BOP7 BIT(7)
157 #define GPIO_BOP_BOP8 BIT(8)
158 #define GPIO_BOP_BOP9 BIT(9)
159 #define GPIO_BOP_BOP10 BIT(10)
160 #define GPIO_BOP_BOP11 BIT(11)
161 #define GPIO_BOP_BOP12 BIT(12)
162 #define GPIO_BOP_BOP13 BIT(13)
163 #define GPIO_BOP_BOP14 BIT(14)
164 #define GPIO_BOP_BOP15 BIT(15)
165 #define GPIO_BOP_CR0 BIT(16)
166 #define GPIO_BOP_CR1 BIT(17)
167 #define GPIO_BOP_CR2 BIT(18)
168 #define GPIO_BOP_CR3 BIT(19)
169 #define GPIO_BOP_CR4 BIT(20)
170 #define GPIO_BOP_CR5 BIT(21)
171 #define GPIO_BOP_CR6 BIT(22)
172 #define GPIO_BOP_CR7 BIT(23)
173 #define GPIO_BOP_CR8 BIT(24)
174 #define GPIO_BOP_CR9 BIT(25)
175 #define GPIO_BOP_CR10 BIT(26)
176 #define GPIO_BOP_CR11 BIT(27)
177 #define GPIO_BOP_CR12 BIT(28)
178 #define GPIO_BOP_CR13 BIT(29)
179 #define GPIO_BOP_CR14 BIT(30)
180 #define GPIO_BOP_CR15 BIT(31)
182 /* GPIO_LOCK */
183 #define GPIO_LOCK_LK0 BIT(0)
184 #define GPIO_LOCK_LK1 BIT(1)
185 #define GPIO_LOCK_LK2 BIT(2)
186 #define GPIO_LOCK_LK3 BIT(3)
187 #define GPIO_LOCK_LK4 BIT(4)
188 #define GPIO_LOCK_LK5 BIT(5)
189 #define GPIO_LOCK_LK6 BIT(6)
190 #define GPIO_LOCK_LK7 BIT(7)
191 #define GPIO_LOCK_LK8 BIT(8)
192 #define GPIO_LOCK_LK9 BIT(9)
193 #define GPIO_LOCK_LK10 BIT(10)
194 #define GPIO_LOCK_LK11 BIT(11)
195 #define GPIO_LOCK_LK12 BIT(12)
196 #define GPIO_LOCK_LK13 BIT(13)
197 #define GPIO_LOCK_LK14 BIT(14)
198 #define GPIO_LOCK_LK15 BIT(15)
199 #define GPIO_LOCK_LKK BIT(16)
201 /* GPIO_AFSEL0 */
202 #define GPIO_AFSEL0_SEL0 BITS(0,3)
203 #define GPIO_AFSEL0_SEL1 BITS(4,7)
204 #define GPIO_AFSEL0_SEL2 BITS(8,11)
205 #define GPIO_AFSEL0_SEL3 BITS(12,15)
206 #define GPIO_AFSEL0_SEL4 BITS(16,19)
207 #define GPIO_AFSEL0_SEL5 BITS(20,23)
208 #define GPIO_AFSEL0_SEL6 BITS(24,27)
209 #define GPIO_AFSEL0_SEL7 BITS(28,31)
211 /* GPIO_AFSEL1 */
212 #define GPIO_AFSEL1_SEL8 BITS(0,3)
213 #define GPIO_AFSEL1_SEL9 BITS(4,7)
214 #define GPIO_AFSEL1_SEL10 BITS(8,11)
215 #define GPIO_AFSEL1_SEL11 BITS(12,15)
216 #define GPIO_AFSEL1_SEL12 BITS(16,19)
217 #define GPIO_AFSEL1_SEL13 BITS(20,23)
218 #define GPIO_AFSEL1_SEL14 BITS(24,27)
219 #define GPIO_AFSEL1_SEL15 BITS(28,31)
221 /* GPIO_BC */
222 #define GPIO_BC_CR0 BIT(0)
223 #define GPIO_BC_CR1 BIT(1)
224 #define GPIO_BC_CR2 BIT(2)
225 #define GPIO_BC_CR3 BIT(3)
226 #define GPIO_BC_CR4 BIT(4)
227 #define GPIO_BC_CR5 BIT(5)
228 #define GPIO_BC_CR6 BIT(6)
229 #define GPIO_BC_CR7 BIT(7)
230 #define GPIO_BC_CR8 BIT(8)
231 #define GPIO_BC_CR9 BIT(9)
232 #define GPIO_BC_CR10 BIT(10)
233 #define GPIO_BC_CR11 BIT(11)
234 #define GPIO_BC_CR12 BIT(12)
235 #define GPIO_BC_CR13 BIT(13)
236 #define GPIO_BC_CR14 BIT(14)
237 #define GPIO_BC_CR15 BIT(15)
239 /* GPIO_TG */
240 #define GPIO_TG_TG0 BIT(0)
241 #define GPIO_TG_TG1 BIT(1)
242 #define GPIO_TG_TG2 BIT(2)
243 #define GPIO_TG_TG3 BIT(3)
244 #define GPIO_TG_TG4 BIT(4)
245 #define GPIO_TG_TG5 BIT(5)
246 #define GPIO_TG_TG6 BIT(6)
247 #define GPIO_TG_TG7 BIT(7)
248 #define GPIO_TG_TG8 BIT(8)
249 #define GPIO_TG_TG9 BIT(9)
250 #define GPIO_TG_TG10 BIT(10)
251 #define GPIO_TG_TG11 BIT(11)
252 #define GPIO_TG_TG12 BIT(12)
253 #define GPIO_TG_TG13 BIT(13)
254 #define GPIO_TG_TG14 BIT(14)
255 #define GPIO_TG_TG15 BIT(15)
257 /* GPIO_OSPD1 */
258 #define GPIO_OSPD1_SPD0 BIT(0)
259 #define GPIO_OSPD1_SPD1 BIT(1)
260 #define GPIO_OSPD1_SPD2 BIT(2)
261 #define GPIO_OSPD1_SPD3 BIT(3)
262 #define GPIO_OSPD1_SPD4 BIT(4)
263 #define GPIO_OSPD1_SPD5 BIT(5)
264 #define GPIO_OSPD1_SPD6 BIT(6)
265 #define GPIO_OSPD1_SPD7 BIT(7)
266 #define GPIO_OSPD1_SPD8 BIT(8)
267 #define GPIO_OSPD1_SPD9 BIT(9)
268 #define GPIO_OSPD1_SPD10 BIT(10)
269 #define GPIO_OSPD1_SPD11 BIT(11)
270 #define GPIO_OSPD1_SPD12 BIT(12)
271 #define GPIO_OSPD1_SPD13 BIT(13)
272 #define GPIO_OSPD1_SPD14 BIT(14)
273 #define GPIO_OSPD1_SPD15 BIT(15)
275 /* constants definitions */
276 typedef FlagStatus bit_status;
277
278 /* output mode definitions */
279 #define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
280 #define GPIO_MODE_INPUT CTL_CLTR(0)
281 #define GPIO_MODE_OUTPUT CTL_CLTR(1)
282 #define GPIO_MODE_AF CTL_CLTR(2)
283 #define GPIO_MODE_ANALOG CTL_CLTR(3)
285 /* pull-up/pull-down definitions */
286 #define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
287 #define GPIO_PUPD_NONE PUD_PUPD(0)
288 #define GPIO_PUPD_PULLUP PUD_PUPD(1)
289 #define GPIO_PUPD_PULLDOWN PUD_PUPD(2)
291 /* GPIO pin definitions */
292 #define GPIO_PIN_0 BIT(0)
293 #define GPIO_PIN_1 BIT(1)
294 #define GPIO_PIN_2 BIT(2)
295 #define GPIO_PIN_3 BIT(3)
296 #define GPIO_PIN_4 BIT(4)
297 #define GPIO_PIN_5 BIT(5)
298 #define GPIO_PIN_6 BIT(6)
299 #define GPIO_PIN_7 BIT(7)
300 #define GPIO_PIN_8 BIT(8)
301 #define GPIO_PIN_9 BIT(9)
302 #define GPIO_PIN_10 BIT(10)
303 #define GPIO_PIN_11 BIT(11)
304 #define GPIO_PIN_12 BIT(12)
305 #define GPIO_PIN_13 BIT(13)
306 #define GPIO_PIN_14 BIT(14)
307 #define GPIO_PIN_15 BIT(15)
308 #define GPIO_PIN_ALL BITS(0,15)
310 /* GPIO mode configuration values */
311 #define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n))))
312 #define GPIO_MODE_MASK(n) (0x3U << (2U * (n)))
313
314 /* GPIO pull-up/pull-down values */
315 #define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n))))
316 #define GPIO_PUPD_MASK(n) (0x3U << (2U * (n)))
317
318 /* GPIO output speed values */
319 #define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n))))
320 #define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n)))
321
322 /* GPIO output type */
323 #define GPIO_OTYPE_PP ((uint8_t)(0x00U))
324 #define GPIO_OTYPE_OD ((uint8_t)(0x01U))
326 /* GPIO output max speed value */
327 #define OSPD_OSPD0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
328 #define GPIO_OSPEED_2MHZ OSPD_OSPD0(0)
329 #define GPIO_OSPEED_10MHZ OSPD_OSPD0(1)
330 #define GPIO_OSPEED_50MHZ OSPD_OSPD0(3)
331 #define GPIO_OSPEED_MAX 0x0000FFFFU
333 /* GPIO alternate function values */
334 #define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
335 #define GPIO_AFR_MASK(n) (0xFU << (4U * (n)))
336
337 /* GPIO alternate function */
338 #define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
339 #define GPIO_AF_0 AF(0)
340 #define GPIO_AF_1 AF(1)
341 #define GPIO_AF_2 AF(2)
342 #define GPIO_AF_3 AF(3)
343 #define GPIO_AF_4 AF(4)
344 #define GPIO_AF_5 AF(5)
345 #define GPIO_AF_6 AF(6)
346 #define GPIO_AF_7 AF(7)
348 /* function declarations */
349 /* reset GPIO port */
350 void gpio_deinit(uint32_t gpio_periph);
351 /* set GPIO mode */
352 void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin);
353 /* set GPIO output type and speed */
354 void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin);
355
356 /* set GPIO pin bit */
357 void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
358 /* reset GPIO pin bit */
359 void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
360 /* write data to the specified GPIO pin */
361 void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
362 /* write data to the specified GPIO port */
363 void gpio_port_write(uint32_t gpio_periph, uint16_t data);
364
365 /* get GPIO pin input status */
366 FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
367 /* get GPIO port input status */
368 uint16_t gpio_input_port_get(uint32_t gpio_periph);
369 /* get GPIO pin output status */
370 FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
371 /* get GPIO port output status */
372 uint16_t gpio_output_port_get(uint32_t gpio_periph);
373
374 /* set GPIO alternate function */
375 void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num, uint32_t pin);
376 /* lock GPIO pin bit */
377 void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
378
379 /* toggle GPIO pin status */
380 void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin);
381 /* toggle GPIO port status */
382 void gpio_port_toggle(uint32_t gpio_periph);
383
384 #endif /* GD32F3X0_GPIO_H */
gpio_bit_set
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
set GPIO pin bit
Definition: gd32f3x0_gpio.c:157
gpio_af_set
void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin)
set GPIO alternate function
Definition: gd32f3x0_gpio.c:276
gpio_input_bit_get
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
get GPIO pin input status
Definition: gd32f3x0_gpio.c:212
gpio_port_toggle
void gpio_port_toggle(uint32_t gpio_periph)
toggle GPIO port status
Definition: gd32f3x0_gpio.c:342
gpio_deinit
void gpio_deinit(uint32_t gpio_periph)
reset GPIO port
Definition: gd32f3x0_gpio.c:20
gpio_input_port_get
uint16_t gpio_input_port_get(uint32_t gpio_periph)
get GPIO all pins input status
Definition: gd32f3x0_gpio.c:227
gpio_output_options_set
void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin)
set GPIO output type and speed
Definition: gd32f3x0_gpio.c:110
gpio_bit_write
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
write data to the specified GPIO pin
Definition: gd32f3x0_gpio.c:184
gpio_mode_set
void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin)
set GPIO output mode
Definition: gd32f3x0_gpio.c:69
gpio_bit_toggle
void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin)
toggle GPIO pin status
Definition: gd32f3x0_gpio.c:331
gpio_port_write
void gpio_port_write(uint32_t gpio_periph, uint16_t data)
write data to the specified GPIO port
Definition: gd32f3x0_gpio.c:200
gpio_output_port_get
uint16_t gpio_output_port_get(uint32_t gpio_periph)
get GPIO all pins output status
Definition: gd32f3x0_gpio.c:254
gpio_output_bit_get
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
get GPIO pin output status
Definition: gd32f3x0_gpio.c:239
gpio_bit_reset
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
reset GPIO pin bit
Definition: gd32f3x0_gpio.c:169
bit_status
FlagStatus bit_status
Definition: gd32f3x0_gpio.h:276
gpio_pin_lock
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
lock GPIO pin bit
Definition: gd32f3x0_gpio.c:311
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_std.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
usb_std.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef USB_STD_H
13 #define USB_STD_H
14
15 #include "usb_conf.h"
16
17 #define USB_DEV_QUALIFIER_DESC_LEN 0x0AU
18 #define USB_DEV_DESC_LEN 0x12U
19 #define USB_CFG_DESC_LEN 0x09U
20 #define USB_IF_DESC_LEN 0x09U
21 #define USB_EP_DESC_LEN 0x07U
22 #define USB_OTG_DESC_LEN 0x03U
24 /* bit 7 of bmRequestType: data phase transfer direction */
25 #define USB_DIR_MASK 0x80U
26 #define USB_DIR_OUT 0x00U
27 #define USB_DIR_IN 0x80U
29 /* bit 6..5 of bmRequestType: request type */
30 #define USB_STANDARD_REQ 0x00U
31 #define USB_CLASS_REQ 0x20U
32 #define USB_VENDOR_REQ 0x40U
33 #define USB_REQ_MASK 0x60U
35 /* bit 4..0 of bmRequestType: recipient type */
36 #define USB_REQTYPE_DEVICE 0x00U
37 #define USB_REQTYPE_INTERFACE 0x01U
38 #define USB_REQTYPE_ENDPOINT 0x02U
39 #define USB_REQTYPE_MASK 0x03U
41 /* bRequest value */
42 #define USBREQ_GET_STATUS 0x00U
43 #define USBREQ_CLEAR_FEATURE 0x01U
44 #define USBREQ_SET_FEATURE 0x03U
45 #define USBREQ_SET_ADDRESS 0x05U
46 #define USBREQ_GET_DESCRIPTOR 0x06U
47 #define USBREQ_SET_DESCRIPTOR 0x07U
48 #define USBREQ_GET_CONFIGURATION 0x08U
49 #define USBREQ_SET_CONFIGURATION 0x09U
50 #define USBREQ_GET_INTERFACE 0x0AU
51 #define USBREQ_SET_INTERFACE 0x0BU
52 #define USBREQ_SYNCH_FRAME 0x0CU
54 /* descriptor types of usb specifications */
55 #define USB_DESCTYPE_DEVICE 0x01U
56 #define USB_DESCTYPE_CONFIGURATION 0x02U
57 #define USB_DESCTYPE_STRING 0x03U
58 #define USB_DESCTYPE_INTERFACE 0x04U
59 #define USB_DESCTYPE_ENDPOINT 0x05U
60 #define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U
61 #define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U
62 #define USB_DESCTYPE_INTERFACE_POWER 0x08U
64 #define USB_DESCTYPE_HID 0x21U
65 #define USB_DESCTYPE_HID_REPORT 0x22U
67 #define USB_DEVDESC_SIZE 18U
68 #define USB_CFGDESC_SIZE 9U
69 #define USB_INTDESC_SIZE 9U
70 #define USB_EPDESC_SIZE 7U
72 /* descriptor type and descriptor index */
73 /* use the following values when USB host need to get descriptor */
74 #define USB_DEVDESC ((USB_DESCTYPE_DEVICE << 8U) & 0xFF00U)
75 #define USB_CFGDESC ((USB_DESCTYPE_CONFIGURATION << 8U) & 0xFF00U)
76 #define USB_STRDESC ((USB_DESCTYPE_STRING << 8U) & 0xFF00U)
77 #define USB_INTDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U)
78 #define USB_EPDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U)
79 #define USB_DEVQUADESC ((USB_DESCTYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U)
80 #define USB_OSPCFGDESC ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U)
81 #define USB_INTPWRDESC ((USB_DESCTYPE_INTERFACE_POWER << 8U) & 0xFF00U)
82 #define USB_HIDREPDESC ((USB_DESCTYPE_HID_REPORT << 8U) & 0xFF00U)
83 #define USB_HIDDESC ((USB_DESCTYPE_HID << 8U) & 0xFF00U)
85 #define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \
86 (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
87
88 /* supported classes */
89 #define USB_MSC_CLASS 0x08U
90 #define USB_HID_CLASS 0x03U
92 /* interface descriptor field values for hid boot protocol */
93 #define HID_BOOT_CODE 0x01U
94 #define HID_KEYBRD_BOOT_CODE 0x01U
95 #define HID_MOUSE_BOOT_CODE 0x02U
97 /* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec
98 standard request with no data stage timeout : 50ms */
99 #define DATA_STAGE_TIMEOUT 5000U
100 #define NODATA_STAGE_TIMEOUT 50U
102 #define USBH_CFG_DESC_SET_SIZE (USB_CFGDESC_SIZE + USB_INTDESC_SIZE \
103 + (USBH_MAX_EP_NUM * USB_EPDESC_SIZE))
105 #pragma pack(1)
106
107 typedef union
108 {
109 uint8_t data[8];
110
111 struct _setup_packet_struct
112 {
113 uint8_t bmRequestType;
114 uint8_t bRequest;
115 uint16_t wValue;
116 uint16_t wIndex;
117 uint16_t wLength;
118 } b;
119 }usb_setup_union;
120
121 typedef struct
122 {
123 uint8_t bLength;
124 uint8_t bDescriptorType;
125 } usb_descriptor_header_struct;
126
127 typedef struct
128 {
129 usb_descriptor_header_struct Header;
131 uint16_t bcdUSB;
132 uint8_t bDeviceClass;
133 uint8_t bDeviceSubClass;
134 uint8_t bDeviceProtocol;
135 uint8_t bMaxPacketSize0;
136 uint16_t idVendor;
137 uint16_t idProduct;
138 uint16_t bcdDevice;
139 uint8_t iManufacturer;
140 uint8_t iProduct;
141 uint8_t iSerialNumber;
142 uint8_t bNumberConfigurations;
143 } usb_descriptor_device_struct;
144
145 typedef struct
146 {
147 usb_descriptor_header_struct Header;
149 uint16_t wTotalLength;
150 uint8_t bNumInterfaces;
151 uint8_t bConfigurationValue;
152 uint8_t iConfiguration;
153 uint8_t bmAttributes;
154 uint8_t bMaxPower;
155 } usb_descriptor_configuration_struct;
156
157 typedef struct
158 {
159 usb_descriptor_header_struct Header;
161 uint8_t bInterfaceNumber;
162 uint8_t bAlternateSetting;
163 uint8_t bNumEndpoints;
164 uint8_t bInterfaceClass;
165 uint8_t bInterfaceSubClass;
166 uint8_t bInterfaceProtocol;
167 uint8_t iInterface;
168 } usb_descriptor_interface_struct;
169
170 typedef struct
171 {
172 usb_descriptor_header_struct Header;
174 uint8_t bEndpointAddress;
175 uint8_t bmAttributes;
176 uint16_t wMaxPacketSize;
177 uint8_t bInterval;
178 } usb_descriptor_endpoint_struct;
179
180 typedef struct
181 {
182 usb_descriptor_header_struct Header;
183 uint16_t wLANGID;
184 }usb_descriptor_language_id_struct;
185
186 #pragma pack()
187
188 #endif /* USB_STD_H */
usb_descriptor_interface_struct::bInterfaceProtocol
uint8_t bInterfaceProtocol
Definition: usb_std.h:166
usb_descriptor_configuration_struct::bmAttributes
uint8_t bmAttributes
Definition: usb_std.h:153
usb_descriptor_endpoint_struct::bmAttributes
uint8_t bmAttributes
Definition: usb_std.h:175
usb_setup_union::_setup_packet_struct::wIndex
uint16_t wIndex
Definition: usb_std.h:116
usb_descriptor_device_struct::idProduct
uint16_t idProduct
Definition: usb_std.h:137
usb_descriptor_interface_struct::iInterface
uint8_t iInterface
Definition: usb_std.h:167
usb_descriptor_configuration_struct::wTotalLength
uint16_t wTotalLength
Definition: usb_std.h:149
usb_descriptor_language_id_struct::wLANGID
uint16_t wLANGID
Definition: usb_std.h:183
usb_descriptor_configuration_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:147
usb_setup_union::_setup_packet_struct::bmRequestType
uint8_t bmRequestType
Definition: usb_std.h:113
usb_descriptor_interface_struct::bNumEndpoints
uint8_t bNumEndpoints
Definition: usb_std.h:163
usb_descriptor_header_struct::bLength
uint8_t bLength
Definition: usb_std.h:123
usb_descriptor_interface_struct
Definition: usb_std.h:157
usb_descriptor_header_struct
Definition: usb_std.h:121
usb_descriptor_endpoint_struct::bEndpointAddress
uint8_t bEndpointAddress
Definition: usb_std.h:174
usb_descriptor_device_struct
Definition: usb_std.h:127
usb_descriptor_language_id_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:182
usb_setup_union
Definition: usb_std.h:107
usb_descriptor_device_struct::bcdUSB
uint16_t bcdUSB
Definition: usb_std.h:131
usb_descriptor_interface_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:159
usb_setup_union::_setup_packet_struct::wLength
uint16_t wLength
Definition: usb_std.h:117
usb_descriptor_interface_struct::bInterfaceClass
uint8_t bInterfaceClass
Definition: usb_std.h:164
usb_descriptor_device_struct::bDeviceProtocol
uint8_t bDeviceProtocol
Definition: usb_std.h:134
usb_descriptor_device_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:129
usb_descriptor_configuration_struct::bConfigurationValue
uint8_t bConfigurationValue
Definition: usb_std.h:151
usb_descriptor_endpoint_struct
Definition: usb_std.h:170
usb_descriptor_device_struct::bcdDevice
uint16_t bcdDevice
Definition: usb_std.h:138
usb_descriptor_device_struct::bDeviceSubClass
uint8_t bDeviceSubClass
Definition: usb_std.h:133
usb_descriptor_interface_struct::bInterfaceSubClass
uint8_t bInterfaceSubClass
Definition: usb_std.h:165
usb_setup_union::_setup_packet_struct::wValue
uint16_t wValue
Definition: usb_std.h:115
usb_descriptor_device_struct::bNumberConfigurations
uint8_t bNumberConfigurations
Definition: usb_std.h:142
usb_descriptor_interface_struct::bAlternateSetting
uint8_t bAlternateSetting
Definition: usb_std.h:162
usb_descriptor_endpoint_struct::wMaxPacketSize
uint16_t wMaxPacketSize
Definition: usb_std.h:176
usb_descriptor_configuration_struct::bNumInterfaces
uint8_t bNumInterfaces
Definition: usb_std.h:150
usb_descriptor_endpoint_struct::Header
usb_descriptor_header_struct Header
Definition: usb_std.h:172
usb_descriptor_configuration_struct::iConfiguration
uint8_t iConfiguration
Definition: usb_std.h:152
usb_descriptor_device_struct::idVendor
uint16_t idVendor
Definition: usb_std.h:136
usb_setup_union::_setup_packet_struct::bRequest
uint8_t bRequest
Definition: usb_std.h:114
usb_setup_union::_setup_packet_struct
Definition: usb_std.h:111
usb_descriptor_interface_struct::bInterfaceNumber
uint8_t bInterfaceNumber
Definition: usb_std.h:161
usb_descriptor_device_struct::iProduct
uint8_t iProduct
Definition: usb_std.h:140
usb_descriptor_header_struct::bDescriptorType
uint8_t bDescriptorType
Definition: usb_std.h:124
usb_descriptor_device_struct::bDeviceClass
uint8_t bDeviceClass
Definition: usb_std.h:132
usb_descriptor_language_id_struct
Definition: usb_std.h:180
usb_descriptor_device_struct::bMaxPacketSize0
uint8_t bMaxPacketSize0
Definition: usb_std.h:135
usb_descriptor_configuration_struct::bMaxPower
uint8_t bMaxPower
Definition: usb_std.h:154
usb_descriptor_device_struct::iManufacturer
uint8_t iManufacturer
Definition: usb_std.h:139
usb_descriptor_endpoint_struct::bInterval
uint8_t bInterval
Definition: usb_std.h:177
usb_descriptor_device_struct::iSerialNumber
uint8_t iSerialNumber
Definition: usb_std.h:141
usb_descriptor_configuration_struct
Definition: usb_std.h:145
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbh_std.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
usbh_std.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef USBH_STD_H
13 #define USBH_STD_H
14
15 #include "usbh_core.h"
16 #include "usbh_usr.h"
17
18 /* standard feature selector for clear feature command */
19 #define FEATURE_SELECTOR_ENDPOINT 0x00U
20 #define FEATURE_SELECTOR_DEVICE 0x01U
21
22 #define USBH_SETUP_PACKET_SIZE 8U /* setup packet size */
23 #define ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */
24
25 extern uint8_t usbh_cfg_desc[512];
26 extern uint8_t enum_polling_handle_flag;
27 extern state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE];
28
29 typedef enum
30 {
31 ENUN_EVENT_IDLE = 0, /* the enum idle event */
32 ENUM_EVENT_SET_ADDR, /* the enum set address event */
33 ENUN_EVENT_GET_FULL_DEV_DESC, /* the enum get full device descripter event */
34 ENUN_EVENT_GET_CFG_DESC, /* the enum get congiguration descripter event */
35 ENUN_EVENT_GET_FULL_CFG_DESC, /* the enum get full configuration descripter event */
36 ENUN_EVENT_GET_MFC_STRING_DESC, /* the enum get MFC string descripter event */
37 ENUN_EVENT_GET_PRODUCT_STRING_DESC, /* the enum get product string event */
38 ENUN_EVENT_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string event */
39 ENUN_EVENT_SET_CONFIGURATION, /* the enum set configuration event */
40 ENUN_EVENT_DEV_CONFIGURED /* the enum device configured event */
41 }enum_event_enum;
42
43 /* function declarations */
44 /* the polling function of enumeration state */
45 usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
46 /* get descriptor in usb host enumeration stage */
47 void usbh_enum_desc_get (usb_core_handle_struct *pudev,
48 usbh_host_struct *puhost,
49 uint8_t *buf,
50 uint8_t req_type,
51 uint16_t value_idx,
52 uint16_t len);
53 /* set address in usb host enumeration stage */
54 void usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address);
55 /* set configuration in usb host enumeration stage */
56 void usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx);
57 /* parse the device descriptor */
58 void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len);
59 /* parse the configuration descriptor */
60 void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc,
61 usb_descriptor_interface_struct *itf_desc,
62 usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM],
63 uint8_t *buf,
64 uint16_t len);
65 /* parse the interface descriptor */
66 void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf);
67 /* parse the endpoint descriptor */
68 void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf);
69 /* parse the string descriptor */
70 void usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len);
71 /* get the next descriptor header */
72 usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr);
73
74 #endif /* USBH_STD_H */
usbh_core.h
header file for usbh_core.c
ENUN_EVENT_GET_SERIALNUM_STRING_DESC
Definition: usbh_std.h:38
usbh_enum_addr_set
void usbh_enum_addr_set(usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address)
set address in usb host enumeration stage
Definition: usbh_std.c:559
enum_event_enum
enum_event_enum
Definition: usbh_std.h:29
usbh_enum_cfg_set
void usbh_enum_cfg_set(usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx)
set configuration in usb host enumeration stage
Definition: usbh_std.c:582
enum_polling_handle_flag
uint8_t enum_polling_handle_flag
Definition: usbh_std.c:19
usbh_cfg_desc
uint8_t usbh_cfg_desc[512]
Definition: usbh_std.c:18
ENUN_EVENT_DEV_CONFIGURED
Definition: usbh_std.h:40
ENUN_EVENT_SET_CONFIGURATION
Definition: usbh_std.h:39
usbh_device_desc_parse
void usbh_device_desc_parse(usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len)
parse the device descriptor
Definition: usbh_std.c:605
usb_descriptor_interface_struct
Definition: usb_std.h:157
usb_descriptor_header_struct
Definition: usb_std.h:121
usb_descriptor_device_struct
Definition: usb_std.h:127
usbh_next_desc_get
usb_descriptor_header_struct * usbh_next_desc_get(uint8_t *pbuf, uint16_t *ptr)
get the next descriptor header
Definition: usbh_std.c:795
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:106
usbh_host_struct
Definition: usbh_core.h:188
ENUN_EVENT_GET_PRODUCT_STRING_DESC
Definition: usbh_std.h:37
ENUN_EVENT_GET_CFG_DESC
Definition: usbh_std.h:34
ENUN_EVENT_GET_FULL_CFG_DESC
Definition: usbh_std.h:35
ENUN_EVENT_GET_MFC_STRING_DESC
Definition: usbh_std.h:36
usbh_endpoint_desc_parse
void usbh_endpoint_desc_parse(usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf)
parse the endpoint descriptor
Definition: usbh_std.c:742
ENUN_EVENT_GET_FULL_DEV_DESC
Definition: usbh_std.h:33
usb_descriptor_endpoint_struct
Definition: usb_std.h:170
usbh_interface_desc_parse
void usbh_interface_desc_parse(usb_descriptor_interface_struct *itf_desc, uint8_t *buf)
parse the interface descriptor
Definition: usbh_std.c:722
state_table_struct
Definition: usbh_core.h:202
ENUN_EVENT_IDLE
Definition: usbh_std.h:31
usb_core_handle_struct
Definition: usb_core.h:200
ENUM_EVENT_SET_ADDR
Definition: usbh_std.h:32
usbh_enum_desc_get
void usbh_enum_desc_get(usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t *buf, uint8_t req_type, uint16_t value_idx, uint16_t len)
get descriptor in usb host enumeration stage
Definition: usbh_std.c:525
usbh_string_desc_parse
void usbh_string_desc_parse(uint8_t *psrc, uint8_t *pdest, uint16_t len)
parse the string descriptor
Definition: usbh_std.c:760
ENUM_HANDLE_TABLE_SIZE
#define ENUM_HANDLE_TABLE_SIZE
Definition: usbh_std.h:23
enum_handle_table
state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]
Definition: usbh_std.c:48
usbh_cfg_desc_parse
void usbh_cfg_desc_parse(usb_descriptor_configuration_struct *cfg_desc, usb_descriptor_interface_struct *itf_desc, usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], uint8_t *buf, uint16_t len)
parse the configuration descriptor
Definition: usbh_std.c:637
enum_state_polling_fun
usbh_status_enum enum_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of enumeration state
Definition: usbh_std.c:71
usb_descriptor_configuration_struct
Definition: usb_std.h:145
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_i2c.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_i2c.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12
13 #ifndef GD32F3X0_I2C_H
14 #define GD32F3X0_I2C_H
15
16 #include "gd32f3x0.h"
17
18 /* I2Cx(x=0,1,2) definitions */
19 #define I2C0 I2C_BASE
20 #define I2C1 (I2C_BASE+0x400U)
21 #define I2C2 (I2C_BASE+0x6C00U)
23 /* registers definitions */
24 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U)
25 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U)
26 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U)
27 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU)
28 #define I2C_DATA(i2cx) REG32((i2cx) + 0x10U)
29 #define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U)
30 #define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U)
31 #define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU)
32 #define I2C_RT(i2cx) REG32((i2cx) + 0x20U)
33 #define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U)
35 /* bits definitions */
36 /* I2Cx_CTL0 */
37 #define I2C_CTL0_I2CEN BIT(0)
38 #define I2C_CTL0_SMBEN BIT(1)
39 #define I2C_CTL0_SMBSEL BIT(3)
40 #define I2C_CTL0_ARPEN BIT(4)
41 #define I2C_CTL0_PECEN BIT(5)
42 #define I2C_CTL0_GCEN BIT(6)
43 #define I2C_CTL0_DISSTRC BIT(7)
44 #define I2C_CTL0_START BIT(8)
45 #define I2C_CTL0_STOP BIT(9)
46 #define I2C_CTL0_ACKEN BIT(10)
47 #define I2C_CTL0_POAP BIT(11)
48 #define I2C_CTL0_PECTRANS BIT(12)
49 #define I2C_CTL0_SALT BIT(13)
50 #define I2C_CTL0_SRESET BIT(15)
52 /* I2Cx_CTL1 */
53 #define I2C_CTL1_I2CCLK BITS(0,6)
54 #define I2C_CTL1_ERRIE BIT(8)
55 #define I2C_CTL1_EVIE BIT(9)
56 #define I2C_CTL1_BUFIE BIT(10)
57 #define I2C_CTL1_DMAON BIT(11)
58 #define I2C_CTL1_DMALST BIT(12)
60 /* I2Cx_SADDR0 */
61 #define I2C_SADDR0_ADDRESS0 BIT(0)
62 #define I2C_SADDR0_ADDRESS BITS(1,7)
63 #define I2C_SADDR0_ADDRESS_H BITS(8,9)
64 #define I2C_SADDR0_ADDFORMAT BIT(15)
66 /* I2Cx_SADDR1 */
67 #define I2C_SADDR1_DUADEN BIT(0)
68 #define I2C_SADDR1_ADDRESS2 BITS(1,7)
70 /* I2Cx_DATA */
71 #define I2C_DATA_TRB BITS(0,7)
73 /* I2Cx_STAT0 */
74 #define I2C_STAT0_SBSEND BIT(0)
75 #define I2C_STAT0_ADDSEND BIT(1)
76 #define I2C_STAT0_BTC BIT(2)
77 #define I2C_STAT0_ADD10SEND BIT(3)
78 #define I2C_STAT0_STPDET BIT(4)
79 #define I2C_STAT0_RBNE BIT(6)
80 #define I2C_STAT0_TBE BIT(7)
81 #define I2C_STAT0_BERR BIT(8)
82 #define I2C_STAT0_LOSTARB BIT(9)
83 #define I2C_STAT0_AERR BIT(10)
84 #define I2C_STAT0_OUERR BIT(11)
85 #define I2C_STAT0_PECERR BIT(12)
86 #define I2C_STAT0_SMBTO BIT(14)
87 #define I2C_STAT0_SMBALT BIT(15)
89 /* I2Cx_STAT1 */
90 #define I2C_STAT1_MASTER BIT(0)
91 #define I2C_STAT1_I2CBSY BIT(1)
92 #define I2C_STAT1_TRS BIT(2)
93 #define I2C_STAT1_RXGC BIT(4)
94 #define I2C_STAT1_DEFSMB BIT(5)
95 #define I2C_STAT1_HSTSMB BIT(6)
96 #define I2C_STAT1_DUMODF BIT(7)
97 #define I2C_STAT1_ECV BITS(8,15)
99 /* I2Cx_CKCFG */
100 #define I2C_CKCFG_CLKC BITS(0,11)
101 #define I2C_CKCFG_DTCY BIT(14)
102 #define I2C_CKCFG_FAST BIT(15)
104 /* I2Cx_RT */
105 #define I2C_RT_RISETIME BITS(0,6)
107 /* I2Cx_FMPCFG */
108 #define I2C_FMPCFG_FMPEN BIT(0)
110 /* constants definitions */
111 /* SMBus/I2C mode switch and SMBus type selection */
112 #define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U)
113 #define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN
115 /* SMBus/I2C mode switch and SMBus type selection */
116 #define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U)
117 #define I2C_SMBUS_HOST I2C_CTL0_SMBSEL
119 /* I2C transfer direction */
120 #define I2C_RECEIVER ((uint32_t)0x00000001U)
121 #define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU)
123 /* whether or not to send an ACK */
124 #define I2C_ACK_DISABLE ((uint32_t)0x00000000U)
125 #define I2C_ACK_ENABLE ((uint32_t)0x00000001U)
127 /* I2C POAP position*/
128 #define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U)
129 #define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U)
131 /* I2C dual-address mode switch */
132 #define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U)
133 #define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U)
135 /* whether or not to stretch SCL low */
136 #define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U)
137 #define I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC
139 /* whether or not to response to a general call */
140 #define I2C_GCEN_ENABLE I2C_CTL0_GCEN
141 #define I2C_GCEN_DISABLE ((uint32_t)0x00000000U)
143 /* software reset I2C */
144 #define I2C_SRESET_SET I2C_CTL0_SRESET
145 #define I2C_SRESET_RESET ((uint32_t)0x00000000U)
147 /* I2C DMA mode configure */
148 /* DMA mode switch */
149 #define I2C_DMA_ON I2C_CTL1_DMAON
150 #define I2C_DMA_OFF ((uint32_t)0x00000000U)
152 /* flag indicating DMA last transfer */
153 #define I2C_DMALST_ON I2C_CTL1_DMALST
154 #define I2C_DMALST_OFF ((uint32_t)0x00000000U)
156 /* I2C PEC configure */
157 /* PEC enable */
158 #define I2C_PEC_ENABLE I2C_CTL0_PECEN
159 #define I2C_PEC_DISABLE ((uint32_t)0x00000000U)
161 /* PEC transfer */
162 #define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS
163 #define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U)
165 /* I2C SMBus configure */
166 /* issue or not alert through SMBA pin */
167 #define I2C_SALTSEND_ENABLE I2C_CTL0_SALT
168 #define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U)
170 /* ARP protocol in SMBus switch */
171 #define I2C_ARP_ENABLE I2C_CTL0_ARPEN
172 #define I2C_ARP_DISABLE ((uint32_t)0x00000000U)
174 /* fast mode plus enable */
175 #define I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN
176 #define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U)
178 /* transmit I2C data */
179 #define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
180
181 /* receive I2C data */
182 #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
183
184 /* I2C flag definitions */
185 #define I2C_FLAG_SBSEND BIT(0)
186 #define I2C_FLAG_ADDSEND BIT(1)
187 #define I2C_FLAG_BTC BIT(2)
188 #define I2C_FLAG_ADD10SEND BIT(3)
189 #define I2C_FLAG_STPDET BIT(4)
190 #define I2C_FLAG_RBNE BIT(6)
191 #define I2C_FLAG_TBE BIT(7)
192 #define I2C_FLAG_BERR BIT(8)
193 #define I2C_FLAG_LOSTARB BIT(9)
194 #define I2C_FLAG_AERR BIT(10)
195 #define I2C_FLAG_OUERR BIT(11)
196 #define I2C_FLAG_PECERR BIT(12)
197 #define I2C_FLAG_SMBTO BIT(14)
198 #define I2C_FLAG_SMBALT BIT(15)
199 #define I2C_FLAG_MASTER (BIT(0)|BIT(31))
200 #define I2C_FLAG_I2CBSY (BIT(1)|BIT(31))
201 #define I2C_FLAG_TRS (BIT(2)|BIT(31))
202 #define I2C_FLAG_RXGC (BIT(4)|BIT(31))
203 #define I2C_FLAG_DEFSMB (BIT(5)|BIT(31))
204 #define I2C_FLAG_HSTSMB (BIT(6)|BIT(31))
205 #define I2C_FLAG_DUMOD (BIT(7)|BIT(31))
207 /* I2C interrupt flags */
208 #define I2C_INT_FLAG_SBSEND I2C_FLAG_SBSEND
209 #define I2C_INT_FLAG_ADDSEND I2C_FLAG_ADDSEND
210 #define I2C_INT_FLAG_BTC I2C_FLAG_BTC
211 #define I2C_INT_FLAG_ADD10SEND I2C_FLAG_ADD10SEND
212 #define I2C_INT_FLAG_STPDET I2C_FLAG_STPDET
213 #define I2C_INT_FLAG_RBNE I2C_FLAG_RBNE
214 #define I2C_INT_FLAG_TBE I2C_FLAG_TBE
215 #define I2C_INT_FLAG_BERR I2C_FLAG_BERR
216 #define I2C_INT_FLAG_LOSTARB I2C_FLAG_LOSTARB
217 #define I2C_INT_FLAG_AERR I2C_FLAG_AERR
218 #define I2C_INT_FLAG_OUERR I2C_FLAG_OUERR
219 #define I2C_INT_FLAG_PECERR I2C_FLAG_PECERR
220 #define I2C_INT_FLAG_SMBTO I2C_FLAG_SMBTO
221 #define I2C_INT_FLAG_SMBALT I2C_FLAG_SMBALT
223 /* I2C interrupt enable bit */
224 #define I2C_INT_ERR I2C_CTL1_ERRIE
225 #define I2C_INT_EV I2C_CTL1_EVIE
226 #define I2C_INT_BUF I2C_CTL1_BUFIE
228 /* I2C duty cycle in fast mode or fast mode plus */
229 #define CKCFG_DTCY(regval) (BIT(14) & ((uint32_t)(regval) << 14))
230 #define I2C_DTCY_2 CKCFG_DTCY(0)
231 #define I2C_DTCY_16_9 CKCFG_DTCY(1)
233 /* address mode for the I2C slave */
234 #define SADDR0_ADDFORMAT(regval) (BIT(15) & ((uint32_t)(regval) << 15))
235 #define I2C_ADDFORMAT_7BITS SADDR0_ADDFORMAT(0)
236 #define I2C_ADDFORMAT_10BITS SADDR0_ADDFORMAT(1)
238 /* function declarations */
239 /* reset I2C */
240 void i2c_deinit(uint32_t i2c_periph);
241 /* configure I2C clock */
242 void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
243 /* configure I2C address */
244 void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
245 /* SMBus type selection */
246 void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
247 /* whether or not to send an ACK */
248 void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
249 /* configure I2C POAP position */
250 void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
251 /* master send slave address */
252 void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
253 /* dual-address mode switch */
254 void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr);
255
256 /* enable I2C */
257 void i2c_enable(uint32_t i2c_periph);
258 /* disable I2C */
259 void i2c_disable(uint32_t i2c_periph);
260 /* generate a START condition on I2C bus */
261 void i2c_start_on_bus(uint32_t i2c_periph);
262 /* generate a STOP condition on I2C bus */
263 void i2c_stop_on_bus(uint32_t i2c_periph);
264 /* I2C transmit data function */
265 void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
266 /* I2C receive data function */
267 uint8_t i2c_data_receive(uint32_t i2c_periph);
268 /* I2C DMA mode enable */
269 void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate);
270 /* flag indicating DMA last transfer */
271 void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast);
272 /* whether to stretch SCL low when data is not ready in slave mode */
273 void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara );
274 /* whether or not to response to a general call */
275 void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
276 /* software reset I2C */
277 void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
278
279 /* check I2C flag is set or not */
280 FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag);
281 /* clear I2C flag */
282 void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag);
283 /* enable I2C interrupt */
284 void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype);
285 /* disable I2C interrupt */
286 void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype);
287 /* check I2C interrupt flag */
288 FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,uint32_t intflag);
289 /* clear I2C interrupt flag */
290 void i2c_interrupt_flag_clear(uint32_t i2c_periph,uint32_t intflag);
291
292 /* I2C PEC calculation on or off */
293 void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate);
294 /* I2C whether to transfer PEC value */
295 void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara);
296 /* packet error checking value */
297 uint8_t i2c_pec_value_get(uint32_t i2c_periph);
298 /* I2C issue alert through SMBA pin */
299 void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara);
300 /* I2C ARP protocol in SMBus switch */
301 void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate);
302
303 #endif /* GD32F3X0_I2C_H */
i2c_disable
void i2c_disable(uint32_t i2c_periph)
disable I2C
Definition: gd32f3x0_i2c.c:263
i2c_deinit
void i2c_deinit(uint32_t i2c_periph)
reset I2C
Definition: gd32f3x0_i2c.c:24
i2c_ackpos_config
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
I2C POAP position configure.
Definition: gd32f3x0_i2c.c:198
i2c_interrupt_enable
void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype)
enable I2C interrupt
Definition: gd32f3x0_i2c.c:495
i2c_flag_clear
void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag)
clear I2C flag
Definition: gd32f3x0_i2c.c:474
i2c_dma_last_transfer_enable
void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast)
flag indicating DMA last transfer
Definition: gd32f3x0_i2c.c:341
i2c_clock_config
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
configure I2C clock
Definition: gd32f3x0_i2c.c:58
i2c_interrupt_disable
void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype)
disable I2C interrupt
Definition: gd32f3x0_i2c.c:510
i2c_enable
void i2c_enable(uint32_t i2c_periph)
enable I2C
Definition: gd32f3x0_i2c.c:252
i2c_flag_get
FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag)
check I2C flag is set or not
Definition: gd32f3x0_i2c.c:436
i2c_ack_config
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
whether or not to send an ACK
Definition: gd32f3x0_i2c.c:180
i2c_master_addressing
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
master send slave address
Definition: gd32f3x0_i2c.c:218
i2c_dualaddr_enable
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr)
dual-address mode switch
Definition: gd32f3x0_i2c.c:237
i2c_interrupt_flag_clear
void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag)
clear I2C interrupt flag
Definition: gd32f3x0_i2c.c:592
i2c_mode_addr_config
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
configure I2C address
Definition: gd32f3x0_i2c.c:141
i2c_software_reset_config
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
software reset I2C
Definition: gd32f3x0_i2c.c:398
i2c_smbus_arp_enable
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
enable or disable I2C ARP protocol in SMBus switch
Definition: gd32f3x0_i2c.c:680
i2c_data_receive
uint8_t i2c_data_receive(uint32_t i2c_periph)
I2C receive data function.
Definition: gd32f3x0_i2c.c:308
i2c_data_transmit
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data)
I2C transmit data function.
Definition: gd32f3x0_i2c.c:297
i2c_pec_transfer_enable
void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
I2C whether to transfer PEC value.
Definition: gd32f3x0_i2c.c:631
i2c_stretch_scl_low_config
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
whether to stretch SCL low when data is not ready in slave mode
Definition: gd32f3x0_i2c.c:360
i2c_smbus_type_config
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
SMBus type selection.
Definition: gd32f3x0_i2c.c:162
i2c_pec_enable
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
I2C PEC calculation on or off.
Definition: gd32f3x0_i2c.c:612
i2c_dma_enable
void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate)
enable I2C DMA mode
Definition: gd32f3x0_i2c.c:322
i2c_start_on_bus
void i2c_start_on_bus(uint32_t i2c_periph)
generate a START condition on I2C bus
Definition: gd32f3x0_i2c.c:274
i2c_pec_value_get
uint8_t i2c_pec_value_get(uint32_t i2c_periph)
get packet error checking value
Definition: gd32f3x0_i2c.c:647
i2c_stop_on_bus
void i2c_stop_on_bus(uint32_t i2c_periph)
generate a STOP condition on I2C bus
Definition: gd32f3x0_i2c.c:285
i2c_smbus_issue_alert
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
I2C issue alert through SMBA pin.
Definition: gd32f3x0_i2c.c:661
i2c_slave_response_to_gcall_config
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
whether or not to response to a general call
Definition: gd32f3x0_i2c.c:379
i2c_interrupt_flag_get
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag)
check I2C interrupt flag
Definition: gd32f3x0_i2c.c:536
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_tsi.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_tsi.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_TSI_H
13 #define GD32F3X0_TSI_H
14
15 #include "gd32f3x0.h"
16
17 /* TSI definitions */
18 #define TSI TSI_BASE
20 /* registers definitions */
21 #define TSI_CTL0 REG32(TSI + 0x00U)
22 #define TSI_INTEN REG32(TSI + 0x04U)
23 #define TSI_INTC REG32(TSI + 0x08U)
24 #define TSI_INTF REG32(TSI + 0x0CU)
25 #define TSI_PHM REG32(TSI + 0x10U)
26 #define TSI_ASW REG32(TSI + 0x18U)
27 #define TSI_SAMPCFG REG32(TSI + 0x20U)
28 #define TSI_CHCFG REG32(TSI + 0x28U)
29 #define TSI_GCTL REG32(TSI + 0x30U)
30 #define TSI_G0CYCN REG32(TSI + 0x34U)
31 #define TSI_G1CYCN REG32(TSI + 0x38U)
32 #define TSI_G2CYCN REG32(TSI + 0x3CU)
33 #define TSI_G3CYCN REG32(TSI + 0x40U)
34 #define TSI_G4CYCN REG32(TSI + 0x44U)
35 #define TSI_G5CYCN REG32(TSI + 0x48U)
36 #define TSI_CTL1 REG32(TSI + 0x300U)
38 /* bits definitions */
39 /* TSI_CTL0 */
40 #define TSI_CTL0_TSIEN BIT(0)
41 #define TSI_CTL0_TSIS BIT(1)
42 #define TSI_CTL0_TRGMOD BIT(2)
43 #define TSI_CTL0_EGSEL BIT(3)
44 #define TSI_CTL0_PINMOD BIT(4)
45 #define TSI_CTL0_MCN BITS(5,7)
46 #define TSI_CTL0_CTCDIV BITS(12,14)
47 #define TSI_CTL0_ECDIV BIT(15)
48 #define TSI_CTL0_ECEN BIT(16)
49 #define TSI_CTL0_ECDT BITS(17,23)
50 #define TSI_CTL0_CTDT BITS(24,27)
51 #define TSI_CTL0_CDT BITS(28,31)
53 /* TSI_INTEN */
54 #define TSI_INTEN_CTCFIE BIT(0)
55 #define TSI_INTEN_MNERRIE BIT(1)
57 /* TSI_INTC */
58 #define TSI_INTC_CCTCF BIT(0)
59 #define TSI_INTC_CMNERR BIT(1)
61 /* TSI_INTF */
62 #define TSI_INTF_CTCF BIT(0)
63 #define TSI_INTF_MNERR BIT(1)
65 /* TSI interrupt enable bit */
66 #define TSI_INT_CCTCF TSI_INTEN_CTCFIE
67 #define TSI_INT_MNERR TSI_INTEN_MNERRIE
69 /* I2C interrupt flags */
70 #define TSI_INT_FLAG_CTCF TSI_INTF_CTCF
71 #define TSI_INT_FLAG_MNERR TSI_INTF_MNERR
73 /* I2C interrupt clear flags */
74 #define TSI_INT_FLAG_CTCF_CLR TSI_INTC_CCTCF
75 #define TSI_INT_FLAG_MNERR_CLR TSI_INTC_CMNERR
77 /* I2C flags */
78 #define TSI_FLAG_CTCF TSI_INTF_CTCF
79 #define TSI_FLAG_MNERR TSI_INTF_MNERR
81 /* I2C clear flags */
82 #define TSI_FLAG_CTCF_CLR TSI_INTC_CCTCF
83 #define TSI_FLAG_MNERR_CLR TSI_INTC_CMNERR
85 /* TSI_PHM */
86 #define TSI_PHM_G0P0 BIT(0)
87 #define TSI_PHM_G0P1 BIT(1)
88 #define TSI_PHM_G0P2 BIT(2)
89 #define TSI_PHM_G0P3 BIT(3)
90 #define TSI_PHM_G1P0 BIT(4)
91 #define TSI_PHM_G1P1 BIT(5)
92 #define TSI_PHM_G1P2 BIT(6)
93 #define TSI_PHM_G1P3 BIT(7)
94 #define TSI_PHM_G2P0 BIT(8)
95 #define TSI_PHM_G2P1 BIT(9)
96 #define TSI_PHM_G2P2 BIT(10)
97 #define TSI_PHM_G2P3 BIT(11)
98 #define TSI_PHM_G3P0 BIT(12)
99 #define TSI_PHM_G3P1 BIT(13)
100 #define TSI_PHM_G3P2 BIT(14)
101 #define TSI_PHM_G3P3 BIT(15)
102 #define TSI_PHM_G4P0 BIT(16)
103 #define TSI_PHM_G4P1 BIT(17)
104 #define TSI_PHM_G4P2 BIT(18)
105 #define TSI_PHM_G4P3 BIT(19)
106 #define TSI_PHM_G5P0 BIT(20)
107 #define TSI_PHM_G5P1 BIT(21)
108 #define TSI_PHM_G5P2 BIT(22)
109 #define TSI_PHM_G5P3 BIT(23)
111 /* TSI_ASW */
112 #define TSI_ASW_G0P0 BIT(0)
113 #define TSI_ASW_G0P1 BIT(1)
114 #define TSI_ASW_G0P2 BIT(2)
115 #define TSI_ASW_G0P3 BIT(3)
116 #define TSI_ASW_G1P0 BIT(4)
117 #define TSI_ASW_G1P1 BIT(5)
118 #define TSI_ASW_G1P2 BIT(6)
119 #define TSI_ASW_G1P3 BIT(7)
120 #define TSI_ASW_G2P0 BIT(8)
121 #define TSI_ASW_G2P1 BIT(9)
122 #define TSI_ASW_G2P2 BIT(10)
123 #define TSI_ASW_G2P3 BIT(11)
124 #define TSI_ASW_G3P0 BIT(12)
125 #define TSI_ASW_G3P1 BIT(13)
126 #define TSI_ASW_G3P2 BIT(14)
127 #define TSI_ASW_G3P3 BIT(15)
128 #define TSI_ASW_G4P0 BIT(16)
129 #define TSI_ASW_G4P1 BIT(17)
130 #define TSI_ASW_G4P2 BIT(18)
131 #define TSI_ASW_G4P3 BIT(19)
132 #define TSI_ASW_G5P0 BIT(20)
133 #define TSI_ASW_G5P1 BIT(21)
134 #define TSI_ASW_G5P2 BIT(22)
135 #define TSI_ASW_G5P3 BIT(23)
137 /* TSI_SAMPCFG */
138 #define TSI_SAMPCFG_G0P0 BIT(0)
139 #define TSI_SAMPCFG_G0P1 BIT(1)
140 #define TSI_SAMPCFG_G0P2 BIT(2)
141 #define TSI_SAMPCFG_G0P3 BIT(3)
142 #define TSI_SAMPCFG_G1P0 BIT(4)
143 #define TSI_SAMPCFG_G1P1 BIT(5)
144 #define TSI_SAMPCFG_G1P2 BIT(6)
145 #define TSI_SAMPCFG_G1P3 BIT(7)
146 #define TSI_SAMPCFG_G2P0 BIT(8)
147 #define TSI_SAMPCFG_G2P1 BIT(9)
148 #define TSI_SAMPCFG_G2P2 BIT(10)
149 #define TSI_SAMPCFG_G2P3 BIT(11)
150 #define TSI_SAMPCFG_G3P0 BIT(12)
151 #define TSI_SAMPCFG_G3P1 BIT(13)
152 #define TSI_SAMPCFG_G3P2 BIT(14)
153 #define TSI_SAMPCFG_G3P3 BIT(15)
154 #define TSI_SAMPCFG_G4P0 BIT(16)
155 #define TSI_SAMPCFG_G4P1 BIT(17)
156 #define TSI_SAMPCFG_G4P2 BIT(18)
157 #define TSI_SAMPCFG_G4P3 BIT(19)
158 #define TSI_SAMPCFG_G5P0 BIT(20)
159 #define TSI_SAMPCFG_G5P1 BIT(21)
160 #define TSI_SAMPCFG_G5P2 BIT(22)
161 #define TSI_SAMPCFG_G5P3 BIT(23)
163 /* TSI_CHCFG */
164 #define TSI_CHCFG_G0P0 BIT(0)
165 #define TSI_CHCFG_G0P1 BIT(1)
166 #define TSI_CHCFG_G0P2 BIT(2)
167 #define TSI_CHCFG_G0P3 BIT(3)
168 #define TSI_CHCFG_G1P0 BIT(4)
169 #define TSI_CHCFG_G1P1 BIT(5)
170 #define TSI_CHCFG_G1P2 BIT(6)
171 #define TSI_CHCFG_G1P3 BIT(7)
172 #define TSI_CHCFG_G2P0 BIT(8)
173 #define TSI_CHCFG_G2P1 BIT(9)
174 #define TSI_CHCFG_G2P2 BIT(10)
175 #define TSI_CHCFG_G2P3 BIT(11)
176 #define TSI_CHCFG_G3P0 BIT(12)
177 #define TSI_CHCFG_G3P1 BIT(13)
178 #define TSI_CHCFG_G3P2 BIT(14)
179 #define TSI_CHCFG_G3P3 BIT(15)
180 #define TSI_CHCFG_G4P0 BIT(16)
181 #define TSI_CHCFG_G4P1 BIT(17)
182 #define TSI_CHCFG_G4P2 BIT(18)
183 #define TSI_CHCFG_G4P3 BIT(19)
184 #define TSI_CHCFG_G5P0 BIT(20)
185 #define TSI_CHCFG_G5P1 BIT(21)
186 #define TSI_CHCFG_G5P2 BIT(22)
187 #define TSI_CHCFG_G5P3 BIT(23)
189 /* TSI_GCTL */
190 #define TSI_GCTL_GE0 BIT(0)
191 #define TSI_GCTL_GE1 BIT(1)
192 #define TSI_GCTL_GE2 BIT(2)
193 #define TSI_GCTL_GE3 BIT(3)
194 #define TSI_GCTL_GE4 BIT(4)
195 #define TSI_GCTL_GE5 BIT(5)
196 #define TSI_GCTL_GC0 BIT(16)
197 #define TSI_GCTL_GC1 BIT(17)
198 #define TSI_GCTL_GC2 BIT(18)
199 #define TSI_GCTL_GC3 BIT(19)
200 #define TSI_GCTL_GC4 BIT(20)
201 #define TSI_GCTL_GC5 BIT(21)
203 /* TSI_CTL1 */
204 #define TSI_CTL1_CTCDIV BIT(24)
205 #define TSI_CTL1_ECDIV BITS(28,29)
207 /* constants definitions */
208 /* CTCLK clock division factor */
209 #define TSI_CTCDIV_DIV1 ((uint32_t)0x00000000U)
210 #define TSI_CTCDIV_DIV2 ((uint32_t)0x00000001U)
211 #define TSI_CTCDIV_DIV4 ((uint32_t)0x00000002U)
212 #define TSI_CTCDIV_DIV8 ((uint32_t)0x00000003U)
213 #define TSI_CTCDIV_DIV16 ((uint32_t)0x00000004U)
214 #define TSI_CTCDIV_DIV32 ((uint32_t)0x00000005U)
215 #define TSI_CTCDIV_DIV64 ((uint32_t)0x00000006U)
216 #define TSI_CTCDIV_DIV128 ((uint32_t)0x00000007U)
217 #define TSI_CTCDIV_DIV256 ((uint32_t)0x00000008U)
218 #define TSI_CTCDIV_DIV512 ((uint32_t)0x00000009U)
219 #define TSI_CTCDIV_DIV1024 ((uint32_t)0x0000000AU)
220 #define TSI_CTCDIV_DIV2048 ((uint32_t)0x0000000BU)
221 #define TSI_CTCDIV_DIV4096 ((uint32_t)0x0000000CU)
222 #define TSI_CTCDIV_DIV8192 ((uint32_t)0x0000000DU)
223 #define TSI_CTCDIV_DIV16384 ((uint32_t)0x0000000EU)
224 #define TSI_CTCDIV_DIV32768 ((uint32_t)0x0000000FU)
226 /* charge transfer state duration Time */
227 #define CTL_CTDT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U))
228 #define TSI_TRANSFER_1CTCLK CTL_CTDT(0)
229 #define TSI_TRANSFER_2CTCLK CTL_CTDT(1)
230 #define TSI_TRANSFER_3CTCLK CTL_CTDT(2)
231 #define TSI_TRANSFER_4CTCLK CTL_CTDT(3)
232 #define TSI_TRANSFER_5CTCLK CTL_CTDT(4)
233 #define TSI_TRANSFER_6CTCLK CTL_CTDT(5)
234 #define TSI_TRANSFER_7CTCLK CTL_CTDT(6)
235 #define TSI_TRANSFER_8CTCLK CTL_CTDT(7)
236 #define TSI_TRANSFER_9CTCLK CTL_CTDT(8)
237 #define TSI_TRANSFER_10CTCLK CTL_CTDT(9)
238 #define TSI_TRANSFER_11CTCLK CTL_CTDT(10)
239 #define TSI_TRANSFER_12CTCLK CTL_CTDT(11)
240 #define TSI_TRANSFER_13CTCLK CTL_CTDT(12)
241 #define TSI_TRANSFER_14CTCLK CTL_CTDT(13)
242 #define TSI_TRANSFER_15CTCLK CTL_CTDT(14)
243 #define TSI_TRANSFER_16CTCLK CTL_CTDT(15)
245 /* charge state duration time */
246 #define CTL_CDT(regval) (BITS(28,31) & ((uint32_t)(regval) << 28U))
247 #define TSI_CHARGE_1CTCLK CTL_CDT(0)
248 #define TSI_CHARGE_2CTCLK CTL_CDT(1)
249 #define TSI_CHARGE_3CTCLK CTL_CDT(2)
250 #define TSI_CHARGE_4CTCLK CTL_CDT(3)
251 #define TSI_CHARGE_5CTCLK CTL_CDT(4)
252 #define TSI_CHARGE_6CTCLK CTL_CDT(5)
253 #define TSI_CHARGE_7CTCLK CTL_CDT(6)
254 #define TSI_CHARGE_8CTCLK CTL_CDT(7)
255 #define TSI_CHARGE_9CTCLK CTL_CDT(8)
256 #define TSI_CHARGE_10CTCLK CTL_CDT(9)
257 #define TSI_CHARGE_11CTCLK CTL_CDT(10)
258 #define TSI_CHARGE_12CTCLK CTL_CDT(11)
259 #define TSI_CHARGE_13CTCLK CTL_CDT(12)
260 #define TSI_CHARGE_14CTCLK CTL_CDT(13)
261 #define TSI_CHARGE_15CTCLK CTL_CDT(14)
262 #define TSI_CHARGE_16CTCLK CTL_CDT(15)
264 /* max cycle number of a sequence */
265 #define CTL_MCN(regval) (BITS(5,7) & ((uint32_t)(regval) << 5U))
266 #define TSI_MAXNUM255 CTL_MCN(0)
267 #define TSI_MAXNUM511 CTL_MCN(1)
268 #define TSI_MAXNUM1023 CTL_MCN(2)
269 #define TSI_MAXNUM2047 CTL_MCN(3)
270 #define TSI_MAXNUM4095 CTL_MCN(4)
271 #define TSI_MAXNUM8191 CTL_MCN(5)
272 #define TSI_MAXNUM16383 CTL_MCN(6)
274 /* ECCLK clock division factor */
275 #define TSI_EXTEND_DIV1 ((uint32_t)0x00000000U)
276 #define TSI_EXTEND_DIV2 ((uint32_t)0x00000001U)
277 #define TSI_EXTEND_DIV3 ((uint32_t)0x00000002U)
278 #define TSI_EXTEND_DIV4 ((uint32_t)0x00000003U)
279 #define TSI_EXTEND_DIV5 ((uint32_t)0x00000004U)
280 #define TSI_EXTEND_DIV6 ((uint32_t)0x00000005U)
281 #define TSI_EXTEND_DIV7 ((uint32_t)0x00000006U)
282 #define TSI_EXTEND_DIV8 ((uint32_t)0x00000007U)
284 /* extend charge state maximum duration time */
285 #define TSI_EXTENDMAX(regval) (BITS(17,23) & ((uint32_t)(regval) << 17U)) /* value range 1..128,extend charge state maximum duration time */
286
287 /* hardware trigger mode */
288 #define TSI_FALLING_TRIGGER 0x00U
289 #define TSI_RISING_TRIGGER 0x01U
291 /* pin mode */
292 #define TSI_OUTPUT_LOW 0x00U
293 #define TSI_INPUT_FLOATING 0x01U
295 /* function declarations */
296 /* reset TSI peripheral */
297 void tsi_deinit(void);
298 /* initialize TSI plus prescaler,charge plus,transfer plus,max cycle number */
299 void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number);
300 /* enable TSI module */
301 void tsi_enable(void);
302 /* disable TSI module */
303 void tsi_disable(void);
304 /* enable sample pin */
305 void tsi_sample_pin_enable(uint32_t sample);
306 /* disable sample pin */
307 void tsi_sample_pin_disable(uint32_t sample);
308 /* enable channel pin */
309 void tsi_channel_pin_enable(uint32_t channel);
310 /* disable channel pin */
311 void tsi_channel_pin_disable(uint32_t channel);
312
313 /* configure TSI triggering by software */
314 void tsi_sofeware_mode_config(void);
315 /* start a charge-transfer sequence when TSI is in software trigger mode */
316 void tsi_software_start(void);
317 /* stop a charge-transfer sequence when TSI is in software trigger mode */
318 void tsi_software_stop(void);
319 /* configure TSI triggering by hardware */
320 void tsi_hardware_mode_config(uint8_t trigger_edge);
321 /* configure TSI pin mode when charge-transfer sequence is IDLE */
322 void tsi_pin_mode_config(uint8_t pin_mode);
323 /* configure extend charge state */
324 void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration);
325
326 /* configure charge plus and transfer plus */
327 void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration);
328 /* configure the max cycle number of a charge-transfer sequence */
329 void tsi_max_number_config(uint32_t max_number);
330 /* switch on hysteresis pin */
331 void tsi_hysteresis_on(uint32_t group_pin);
332 /* switch off hysteresis pin */
333 void tsi_hysteresis_off(uint32_t group_pin);
334 /* switch on analog pin */
335 void tsi_analog_on(uint32_t group_pin);
336 /* switch off analog pin */
337 void tsi_analog_off(uint32_t group_pin);
338
339 /* enable TSI interrupt */
340 void tsi_interrupt_enable(uint32_t source);
341 /* disable TSI interrupt */
342 void tsi_interrupt_disable(uint32_t source);
343 /* clear interrupt flag */
344 void tsi_interrupt_flag_clear(uint32_t flag);
345 /* get TSI interrupt flag */
346 FlagStatus tsi_interrupt_flag_get(uint32_t flag);
347
348 /* clear flag */
349 void tsi_flag_clear(uint32_t flag);
350 /* get flag */
351 FlagStatus tsi_flag_get(uint32_t flag);
352
353 /* enbale group */
354 void tsi_group_enable(uint32_t group);
355 /* disbale group */
356 void tsi_group_disable(uint32_t group);
357 /* get group complete status */
358 FlagStatus tsi_group_status_get(uint32_t group);
359 /* get the cycle number for group0 as soon as a charge-transfer sequence completes */
360 uint16_t tsi_group0_cycle_get(void);
361 /* get the cycle number for group1 as soon as a charge-transfer sequence completes */
362 uint16_t tsi_group1_cycle_get(void);
363 /* get the cycle number for group2 as soon as a charge-transfer sequence completes */
364 uint16_t tsi_group2_cycle_get(void);
365 /* get the cycle number for group3 as soon as a charge-transfer sequence completes */
366 uint16_t tsi_group3_cycle_get(void);
367 /* get the cycle number for group4 as soon as a charge-transfer sequence completes */
368 uint16_t tsi_group4_cycle_get(void);
369 /* get the cycle number for group5 as soon as a charge-transfer sequence completes */
370 uint16_t tsi_group5_cycle_get(void);
371
372 #endif /* GD32F3X0_TSI_H */
tsi_group5_cycle_get
uint16_t tsi_group5_cycle_get(void)
get the cycle number for group5 as soon as a charge-transfer sequence completes
Definition: gd32f3x0_tsi.c:649
tsi_interrupt_flag_clear
void tsi_interrupt_flag_clear(uint32_t flag)
clear TSI interrupt flag
Definition: gd32f3x0_tsi.c:422
tsi_deinit
void tsi_deinit(void)
reset TSI peripheral
Definition: gd32f3x0_tsi.c:20
tsi_group_enable
void tsi_group_enable(uint32_t group)
enbale group
Definition: gd32f3x0_tsi.c:553
tsi_plus_config
void tsi_plus_config(uint32_t prescaler, uint32_t charge_duration, uint32_t transfer_duration)
configure charge plus and transfer plus
Definition: gd32f3x0_tsi.c:171
tsi_flag_get
FlagStatus tsi_flag_get(uint32_t flag)
get flag
Definition: gd32f3x0_tsi.c:487
tsi_sofeware_mode_config
void tsi_sofeware_mode_config(void)
configure TSI triggering by software
Definition: gd32f3x0_tsi.c:210
tsi_extend_charge_config
void tsi_extend_charge_config(ControlStatus extend, uint8_t prescaler, uint32_t max_duration)
configure extend charge state
Definition: gd32f3x0_tsi.c:345
tsi_sample_pin_enable
void tsi_sample_pin_enable(uint32_t sample)
enable sample pin
Definition: gd32f3x0_tsi.c:100
tsi_analog_off
void tsi_analog_off(uint32_t group_pin)
switch off analog pin
Definition: gd32f3x0_tsi.c:541
tsi_max_number_config
void tsi_max_number_config(uint32_t max_number)
configure the max cycle number of a charge-transfer sequence
Definition: gd32f3x0_tsi.c:271
tsi_group1_cycle_get
uint16_t tsi_group1_cycle_get(void)
get the cycle number for group1 as soon as a charge-transfer sequence completes
Definition: gd32f3x0_tsi.c:605
tsi_interrupt_flag_get
FlagStatus tsi_interrupt_flag_get(uint32_t flag)
get TSI interrupt flag
Definition: gd32f3x0_tsi.c:435
tsi_group_disable
void tsi_group_disable(uint32_t group)
disbale group
Definition: gd32f3x0_tsi.c:565
tsi_init
void tsi_init(uint32_t prescaler, uint32_t charge_duration, uint32_t transfer_duration, uint32_t max_number)
initialize TSI plus prescaler,charge plus,transfer plus,max cycle number
Definition: gd32f3x0_tsi.c:60
tsi_group4_cycle_get
uint16_t tsi_group4_cycle_get(void)
get the cycle number for group4 as soon as a charge-transfer sequence completes
Definition: gd32f3x0_tsi.c:638
tsi_interrupt_disable
void tsi_interrupt_disable(uint32_t source)
disable TSI interrupt
Definition: gd32f3x0_tsi.c:409
tsi_channel_pin_disable
void tsi_channel_pin_disable(uint32_t channel)
disable channel pin
Definition: gd32f3x0_tsi.c:140
tsi_channel_pin_enable
void tsi_channel_pin_enable(uint32_t channel)
enable channel pin
Definition: gd32f3x0_tsi.c:128
tsi_interrupt_enable
void tsi_interrupt_enable(uint32_t source)
enable TSI interrupt
Definition: gd32f3x0_tsi.c:396
tsi_group_status_get
FlagStatus tsi_group_status_get(uint32_t group)
get group complete status
Definition: gd32f3x0_tsi.c:577
tsi_software_stop
void tsi_software_stop(void)
stop a charge-transfer sequence when TSI is in software trigger mode
Definition: gd32f3x0_tsi.c:300
tsi_disable
void tsi_disable(void)
disable TSI module
Definition: gd32f3x0_tsi.c:322
tsi_pin_mode_config
void tsi_pin_mode_config(uint8_t pin_mode)
configure TSI pin mode when charge-transfer sequence is IDLE
Definition: gd32f3x0_tsi.c:247
tsi_group0_cycle_get
uint16_t tsi_group0_cycle_get(void)
get the cycle number for group0 as soon as a charge-transfer sequence completes
Definition: gd32f3x0_tsi.c:594
tsi_analog_on
void tsi_analog_on(uint32_t group_pin)
switch on analog pin
Definition: gd32f3x0_tsi.c:529
tsi_flag_clear
void tsi_flag_clear(uint32_t flag)
clear flag
Definition: gd32f3x0_tsi.c:474
tsi_enable
void tsi_enable(void)
enable TSI module
Definition: gd32f3x0_tsi.c:311
tsi_hysteresis_off
void tsi_hysteresis_off(uint32_t group_pin)
switch off hysteresis pin
Definition: gd32f3x0_tsi.c:517
tsi_sample_pin_disable
void tsi_sample_pin_disable(uint32_t sample)
disable sample pin
Definition: gd32f3x0_tsi.c:114
tsi_software_start
void tsi_software_start(void)
start a charge-transfer sequence when TSI is in software trigger mode
Definition: gd32f3x0_tsi.c:289
tsi_group2_cycle_get
uint16_t tsi_group2_cycle_get(void)
get the cycle number for group2 as soon as a charge-transfer sequence completes
Definition: gd32f3x0_tsi.c:616
tsi_hardware_mode_config
void tsi_hardware_mode_config(uint8_t trigger_edge)
configure TSI triggering by hardware
Definition: gd32f3x0_tsi.c:225
tsi_hysteresis_on
void tsi_hysteresis_on(uint32_t group_pin)
switch on hysteresis pin
Definition: gd32f3x0_tsi.c:505
tsi_group3_cycle_get
uint16_t tsi_group3_cycle_get(void)
get the cycle number for group3 as soon as a charge-transfer sequence completes
Definition: gd32f3x0_tsi.c:627
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_ctc.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_ctc.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_CTC_H
13 #define GD32F3X0_CTC_H
14
15 #include "gd32f3x0.h"
16
17 /* CTC definitions */
18 #define CTC CTC_BASE
19
20 /* registers definitions */
21 #define CTC_CTL0 REG32((CTC) + 0x00U)
22 #define CTC_CTL1 REG32((CTC) + 0x04U)
23 #define CTC_STAT REG32((CTC) + 0x08U)
24 #define CTC_INTC REG32((CTC) + 0x0CU)
26 /* bits definitions */
27 /* CTC_CTL0 */
28 #define CTC_CTL0_CKOKIE BIT(0)
29 #define CTC_CTL0_CKWARNIE BIT(1)
30 #define CTC_CTL0_ERRIE BIT(2)
31 #define CTC_CTL0_EREFIE BIT(3)
32 #define CTC_CTL0_CNTEN BIT(5)
33 #define CTC_CTL0_AUTOTRIM BIT(6)
34 #define CTC_CTL0_SWREFPUL BIT(7)
35 #define CTC_CTL0_TRIMVALUE BITS(8,13)
37 /* CTC_CTL1 */
38 #define CTC_CTL1_RLVALUE BITS(0,15)
39 #define CTC_CTL1_CKLIM BITS(16,23)
40 #define CTC_CTL1_REFPSC BITS(24,26)
41 #define CTC_CTL1_REFSEL BITS(28,29)
42 #define CTC_CTL1_REFPOL BIT(31)
44 /* CTC_STAT */
45 #define CTC_STAT_CKOKIF BIT(0)
46 #define CTC_STAT_CKWARNIF BIT(1)
47 #define CTC_STAT_ERRIF BIT(2)
48 #define CTC_STAT_EREFIF BIT(3)
49 #define CTC_STAT_CKERR BIT(8)
50 #define CTC_STAT_REFMISS BIT(9)
51 #define CTC_STAT_TRIMERR BIT(10)
52 #define CTC_STAT_REFDIR BIT(15)
53 #define CTC_STAT_REFCAP BITS(16,31)
55 /* CTC_INTC */
56 #define CTC_INTC_CKOKIC BIT(0)
57 #define CTC_INTC_CKWARNIC BIT(1)
58 #define CTC_INTC_ERRIC BIT(2)
59 #define CTC_INTC_EREFIC BIT(3)
61 /* constants definitions */
62 #define CTL0_TRIMVALUE(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
63 #define CTL1_CKLIM(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
64 #define GET_STAT_REFCAP(regval) GET_BITS((regval),16,31)
65 #define GET_CTL0_TRIMVALUE(regval) GET_BITS((regval),8,13)
66
67 /* hardware automatically trim mode definitions */
68 #define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM
69 #define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U)
71 /* reference signal source polarity definitions */
72 #define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL
73 #define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U)
75 /* reference signal source selection definitions */
76 #define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
77 #define CTC_REFSOURCE_GPIO CTL1_REFSEL(0)
78 #define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1)
79 #define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2)
81 /* reference signal source prescaler definitions */
82 #define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
83 #define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0)
84 #define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1)
85 #define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2)
86 #define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3)
87 #define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4)
88 #define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5)
89 #define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6)
90 #define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7)
92 /* CTC interrupt enable definitions */
93 #define CTC_INT_CKOK CTC_CTL0_CKOKIE
94 #define CTC_INT_CKWARN CTC_CTL0_CKWARNIE
95 #define CTC_INT_ERR CTC_CTL0_ERRIE
96 #define CTC_INT_EREF CTC_CTL0_EREFIE
98 /* CTC interrupt source definitions */
99 #define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF
100 #define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF
101 #define CTC_INT_FLAG_ERR CTC_STAT_ERRIF
102 #define CTC_INT_FLAG_EREF CTC_STAT_EREFIF
103 #define CTC_INT_FLAG_CKERR CTC_STAT_CKERR
104 #define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS
105 #define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR
107 /* CTC flag definitions */
108 #define CTC_FLAG_CKOK CTC_STAT_CKOKIF
109 #define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF
110 #define CTC_FLAG_ERR CTC_STAT_ERRIF
111 #define CTC_FLAG_EREF CTC_STAT_EREFIF
112 #define CTC_FLAG_CKERR CTC_STAT_CKERR
113 #define CTC_FLAG_REFMISS CTC_STAT_REFMISS
114 #define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR
116 /* function declarations */
117 /* reset ctc clock trim controller */
118 void ctc_deinit(void);
119
120 /* enable the CTC interrupt */
121 void ctc_interrupt_enable(uint32_t interrupt);
122 /* disable the CTC interrupt */
123 void ctc_interrupt_disable(uint32_t interrupt);
124 /* get CTC interrupt flag */
125 FlagStatus ctc_interrupt_flag_get(uint32_t interrupt);
126 /* clear CTC interrupt flag */
127 void ctc_interrupt_flag_clear(uint32_t interrupt);
128
129 /* get CTC flag */
130 FlagStatus ctc_flag_get(uint32_t flag);
131 /* clear CTC flag */
132 void ctc_flag_clear(uint32_t flag);
133
134 /* configure the IRC48M trim value */
135 void ctc_irc48m_trim_value_config(uint8_t trim_value);
136 /* generate software reference source sync pulse */
137 void ctc_software_refsource_pulse_generate(void);
138 /* configure hardware automatically trim mode */
139 void ctc_hardware_trim_mode_config(uint32_t hardmode);
140
141 /* enable CTC trim counter */
142 void ctc_counter_enable(void);
143 /* disable CTC trim counter */
144 void ctc_counter_disable(void);
145
146 /* configure reference signal source polarity */
147 void ctc_refsource_polarity_config(uint32_t polarity);
148 /* select reference signal source */
149 void ctc_refsource_signal_select(uint32_t refs);
150 /* configure reference signal source prescaler */
151 void ctc_refsource_prescaler_config(uint32_t prescaler);
152 /* configure clock trim base limit value */
153 void ctc_clock_limit_value_config(uint8_t limit_value);
154 /* configure CTC counter reload value */
155 void ctc_counter_reload_value_config(uint16_t reload_value);
156
157 /* read CTC counter capture value when reference sync pulse occurred */
158 uint16_t ctc_counter_capture_value_read(void);
159 /* read CTC trim counter direction when reference sync pulse occurred */
160 FlagStatus ctc_counter_direction_read(void);
161 /* read CTC counter reload value */
162 uint16_t ctc_counter_reload_value_read(void);
163 /* read the IRC48M trim value */
164 uint8_t ctc_irc48m_trim_value_read(void);
165
166 #endif /* GD32F3X0_CTC_H */
ctc_flag_get
FlagStatus ctc_flag_get(uint32_t flag)
get CTC flag
Definition: gd32f3x0_ctc.c:315
ctc_interrupt_flag_get
FlagStatus ctc_interrupt_flag_get(uint32_t interrupt)
get CTC interrupt flag
Definition: gd32f3x0_ctc.c:262
ctc_flag_clear
void ctc_flag_clear(uint32_t flag)
clear CTC flag
Definition: gd32f3x0_ctc.c:338
ctc_interrupt_enable
void ctc_interrupt_enable(uint32_t interrupt)
enable the CTC interrupt
Definition: gd32f3x0_ctc.c:229
ctc_counter_reload_value_read
uint16_t ctc_counter_reload_value_read(void)
read CTC counter reload value
Definition: gd32f3x0_ctc.c:199
ctc_software_refsource_pulse_generate
void ctc_software_refsource_pulse_generate(void)
generate software reference source sync pulse
Definition: gd32f3x0_ctc.c:49
ctc_hardware_trim_mode_config
void ctc_hardware_trim_mode_config(uint32_t hardmode)
configure hardware automatically trim mode
Definition: gd32f3x0_ctc.c:62
ctc_irc48m_trim_value_read
uint8_t ctc_irc48m_trim_value_read(void)
read the IRC48M trim value
Definition: gd32f3x0_ctc.c:212
ctc_refsource_polarity_config
void ctc_refsource_polarity_config(uint32_t polarity)
configure reference signal source polarity
Definition: gd32f3x0_ctc.c:98
ctc_refsource_signal_select
void ctc_refsource_signal_select(uint32_t refs)
select reference signal source
Definition: gd32f3x0_ctc.c:113
ctc_interrupt_disable
void ctc_interrupt_disable(uint32_t interrupt)
disable the CTC interrupt
Definition: gd32f3x0_ctc.c:244
ctc_refsource_prescaler_config
void ctc_refsource_prescaler_config(uint32_t prescaler)
configure reference signal source prescaler
Definition: gd32f3x0_ctc.c:133
ctc_counter_enable
void ctc_counter_enable(void)
enable CTC trim counter
Definition: gd32f3x0_ctc.c:74
ctc_counter_capture_value_read
uint16_t ctc_counter_capture_value_read(void)
read CTC counter capture value when reference sync pulse occurred
Definition: gd32f3x0_ctc.c:169
ctc_irc48m_trim_value_config
void ctc_irc48m_trim_value_config(uint8_t trim_value)
configure the IRC48M trim value
Definition: gd32f3x0_ctc.c:35
ctc_counter_disable
void ctc_counter_disable(void)
disable CTC trim counter
Definition: gd32f3x0_ctc.c:85
ctc_interrupt_flag_clear
void ctc_interrupt_flag_clear(uint32_t interrupt)
clear CTC interrupt flag
Definition: gd32f3x0_ctc.c:293
ctc_clock_limit_value_config
void ctc_clock_limit_value_config(uint8_t limit_value)
configure clock trim base limit value
Definition: gd32f3x0_ctc.c:145
ctc_deinit
void ctc_deinit(void)
reset CTC clock trim controller
Definition: gd32f3x0_ctc.c:22
ctc_counter_reload_value_config
void ctc_counter_reload_value_config(uint16_t reload_value)
configure CTC counter reload value
Definition: gd32f3x0_ctc.c:157
ctc_counter_direction_read
FlagStatus ctc_counter_direction_read(void)
read CTC trim counter direction when reference sync pulse occurred
Definition: gd32f3x0_ctc.c:184
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_exti.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_exti.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_exti.h"
13
20 void exti_deinit(void)
21 {
22 /* reset the value of all the EXTI registers */
23 EXTI_INTEN = (uint32_t)0x0F940000U;
24 EXTI_EVEN = (uint32_t)0x00000000U;
25 EXTI_RTEN = (uint32_t)0x00000000U;
26 EXTI_FTEN = (uint32_t)0x00000000U;
27 EXTI_SWIEV = (uint32_t)0x00000000U;
28 }
29
47 void exti_init(exti_line_enum linex, \
48 exti_mode_enum mode, \
49 exti_trig_type_enum trig_type)
50 {
51 /* reset the EXTI line x */
52 EXTI_INTEN &= ~(uint32_t)linex;
53 EXTI_EVEN &= ~(uint32_t)linex;
54 EXTI_RTEN &= ~(uint32_t)linex;
55 EXTI_FTEN &= ~(uint32_t)linex;
56
57 /* set the EXTI mode and enable the interrupts or events from EXTI line x */
58 switch(mode){
59 case EXTI_INTERRUPT:
60 EXTI_INTEN |= (uint32_t)linex;
61 break;
62 case EXTI_EVENT:
63 EXTI_EVEN |= (uint32_t)linex;
64 break;
65 default:
66 break;
67 }
68
69 /* set the EXTI trigger type */
70 switch(trig_type){
71 case EXTI_TRIG_RISING:
72 EXTI_RTEN |= (uint32_t)linex;
73 EXTI_FTEN &= ~(uint32_t)linex;
74 break;
75 case EXTI_TRIG_FALLING:
76 EXTI_RTEN &= ~(uint32_t)linex;
77 EXTI_FTEN |= (uint32_t)linex;
78 break;
79 case EXTI_TRIG_BOTH:
80 EXTI_RTEN |= (uint32_t)linex;
81 EXTI_FTEN |= (uint32_t)linex;
82 break;
83 default:
84 break;
85 }
86 }
87
96 void exti_interrupt_enable(exti_line_enum linex)
97 {
98 EXTI_INTEN |= (uint32_t)linex;
99 }
100
109 void exti_event_enable(exti_line_enum linex)
110 {
111 EXTI_EVEN |= (uint32_t)linex;
112 }
113
122 void exti_interrupt_disable(exti_line_enum linex)
123 {
124 EXTI_INTEN &= ~(uint32_t)linex;
125 }
126
135 void exti_event_disable(exti_line_enum linex)
136 {
137 EXTI_EVEN &= ~(uint32_t)linex;
138 }
139
148 FlagStatus exti_flag_get(exti_line_enum linex)
149 {
150 if(RESET != (EXTI_PD & (uint32_t)linex)){
151 return SET;
152 }else{
153 return RESET;
154 }
155 }
156
165 void exti_flag_clear(exti_line_enum linex)
166 {
167 EXTI_PD = (uint32_t)linex;
168 }
169
178 FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
179 {
180 uint32_t flag_left, flag_right;
181
182 flag_left = EXTI_PD & (uint32_t)linex;
183 flag_right = EXTI_INTEN & (uint32_t)linex;
184
185 if((RESET != flag_left) && (RESET != flag_right)){
186 return SET;
187 }else{
188 return RESET;
189 }
190 }
191
200 void exti_interrupt_flag_clear(exti_line_enum linex)
201 {
202 EXTI_PD = (uint32_t)linex;
203 }
204
213 void exti_software_interrupt_enable(exti_line_enum linex)
214 {
215 EXTI_SWIEV |= (uint32_t)linex;
216 }
217
226 void exti_software_interrupt_disable(exti_line_enum linex)
227 {
228 EXTI_SWIEV &= ~(uint32_t)linex;
229 }
EXTI_TRIG_FALLING
Definition: gd32f3x0_exti.h:230
exti_trig_type_enum
exti_trig_type_enum
Definition: gd32f3x0_exti.h:227
exti_flag_clear
void exti_flag_clear(exti_line_enum linex)
clear EXTI lines pending flag
Definition: gd32f3x0_exti.c:165
EXTI_EVENT
Definition: gd32f3x0_exti.h:223
EXTI_PD
#define EXTI_PD
Definition: gd32f3x0_exti.h:26
EXTI_SWIEV
#define EXTI_SWIEV
Definition: gd32f3x0_exti.h:25
EXTI_EVEN
#define EXTI_EVEN
Definition: gd32f3x0_exti.h:22
exti_line_enum
exti_line_enum
Definition: gd32f3x0_exti.h:187
exti_interrupt_disable
void exti_interrupt_disable(exti_line_enum linex)
disable the interrupt from EXTI line x
Definition: gd32f3x0_exti.c:122
exti_interrupt_flag_get
FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
get EXTI lines flag when the interrupt flag is set
Definition: gd32f3x0_exti.c:178
exti_init
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
initialize the EXTI
Definition: gd32f3x0_exti.c:47
gd32f3x0_exti.h
definitions for the EXTI
EXTI_FTEN
#define EXTI_FTEN
Definition: gd32f3x0_exti.h:24
exti_deinit
void exti_deinit(void)
deinitialize the EXTI
Definition: gd32f3x0_exti.c:20
exti_flag_get
FlagStatus exti_flag_get(exti_line_enum linex)
get EXTI lines flag
Definition: gd32f3x0_exti.c:148
exti_interrupt_flag_clear
void exti_interrupt_flag_clear(exti_line_enum linex)
clear EXTI lines pending flag
Definition: gd32f3x0_exti.c:200
EXTI_RTEN
#define EXTI_RTEN
Definition: gd32f3x0_exti.h:23
exti_software_interrupt_disable
void exti_software_interrupt_disable(exti_line_enum linex)
disable EXTI software interrupt event
Definition: gd32f3x0_exti.c:226
EXTI_INTEN
#define EXTI_INTEN
Definition: gd32f3x0_exti.h:21
exti_mode_enum
exti_mode_enum
Definition: gd32f3x0_exti.h:220
exti_event_disable
void exti_event_disable(exti_line_enum linex)
disable the events from EXTI line x
Definition: gd32f3x0_exti.c:135
exti_software_interrupt_enable
void exti_software_interrupt_enable(exti_line_enum linex)
enable EXTI software interrupt event
Definition: gd32f3x0_exti.c:213
exti_interrupt_enable
void exti_interrupt_enable(exti_line_enum linex)
enable the interrupts from EXTI line x
Definition: gd32f3x0_exti.c:96
EXTI_INTERRUPT
Definition: gd32f3x0_exti.h:222
EXTI_TRIG_BOTH
Definition: gd32f3x0_exti.h:231
EXTI_TRIG_RISING
Definition: gd32f3x0_exti.h:229
exti_event_enable
void exti_event_enable(exti_line_enum linex)
enable the events from EXTI line x
Definition: gd32f3x0_exti.c:109
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_rcu.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_rcu.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_RCU_H
13 #define GD32F3X0_RCU_H
14
15 #include "gd32f3x0.h"
16
17 /* RCU definitions */
18 #define RCU RCU_BASE
19
20 /* registers definitions */
21 #define RCU_CTL0 REG32(RCU + 0x00U)
22 #define RCU_CFG0 REG32(RCU + 0x04U)
23 #define RCU_INT REG32(RCU + 0x08U)
24 #define RCU_APB2RST REG32(RCU + 0x0CU)
25 #define RCU_APB1RST REG32(RCU + 0x10U)
26 #define RCU_AHBEN REG32(RCU + 0x14U)
27 #define RCU_APB2EN REG32(RCU + 0x18U)
28 #define RCU_APB1EN REG32(RCU + 0x1CU)
29 #define RCU_BDCTL REG32(RCU + 0x20U)
30 #define RCU_RSTSCK REG32(RCU + 0x24U)
31 #define RCU_AHBRST REG32(RCU + 0x28U)
32 #define RCU_CFG1 REG32(RCU + 0x2CU)
33 #define RCU_CFG2 REG32(RCU + 0x30U)
34 #define RCU_CTL1 REG32(RCU + 0x34U)
35 #define RCU_ADDCTL REG32(RCU + 0xC0U)
36 #define RCU_ADDINT REG32(RCU + 0xCCU)
37 #define RCU_ADDAPB1EN REG32(RCU + 0xF8U)
38 #define RCU_ADDAPB1RST REG32(RCU + 0xFCU)
39 #define RCU_VKEY REG32(RCU + 0x100U)
40 #define RCU_DSV REG32(RCU + 0x134U)
42 /* bits definitions */
43 /* RCU_CTL0 */
44 #define RCU_CTL0_IRC8MEN BIT(0)
45 #define RCU_CTL0_IRC8MSTB BIT(1)
46 #define RCU_CTL0_IRC8MADJ BITS(3,7)
47 #define RCU_CTL0_IRC8MCALIB BITS(8,15)
48 #define RCU_CTL0_HXTALEN BIT(16)
49 #define RCU_CTL0_HXTALSTB BIT(17)
50 #define RCU_CTL0_HXTALBPS BIT(18)
51 #define RCU_CTL0_CKMEN BIT(19)
52 #define RCU_CTL0_PLLEN BIT(24)
53 #define RCU_CTL0_PLLSTB BIT(25)
55 /* RCU_CFG0 */
56 #define RCU_CFG0_SCS BITS(0,1)
57 #define RCU_CFG0_SCSS BITS(2,3)
58 #define RCU_CFG0_AHBPSC BITS(4,7)
59 #define RCU_CFG0_APB1PSC BITS(8,10)
60 #define RCU_CFG0_APB2PSC BITS(11,13)
61 #define RCU_CFG0_ADCPSC BITS(14,15)
62 #define RCU_CFG0_PLLSEL BIT(16)
63 #define RCU_CFG0_PLLPREDV BIT(17)
64 #define RCU_CFG0_PLLMF (BIT(27) | BITS(18,21))
65 #define RCU_CFG0_USBFSPSC BITS(22,23)
66 #define RCU_CFG0_CKOUTSEL BITS(24,26)
67 #define RCU_CFG0_PLLMF4 BIT(27)
68 #define RCU_CFG0_CKOUTDIV BITS(28,30)
69 #define RCU_CFG0_PLLDV BIT(31)
71 /* RCU_INT */
72 #define RCU_INT_IRC40KSTBIF BIT(0)
73 #define RCU_INT_LXTALSTBIF BIT(1)
74 #define RCU_INT_IRC8MSTBIF BIT(2)
75 #define RCU_INT_HXTALSTBIF BIT(3)
76 #define RCU_INT_PLLSTBIF BIT(4)
77 #define RCU_INT_IRC28MSTBIF BIT(5)
78 #define RCU_INT_CKMIF BIT(7)
79 #define RCU_INT_IRC40KSTBIE BIT(8)
80 #define RCU_INT_LXTALSTBIE BIT(9)
81 #define RCU_INT_IRC8MSTBIE BIT(10)
82 #define RCU_INT_HXTALSTBIE BIT(11)
83 #define RCU_INT_PLLSTBIE BIT(12)
84 #define RCU_INT_IRC28MSTBIE BIT(13)
85 #define RCU_INT_IRC40KSTBIC BIT(16)
86 #define RCU_INT_LXTALSTBIC BIT(17)
87 #define RCU_INT_IRC8MSTBIC BIT(18)
88 #define RCU_INT_HXTALSTBIC BIT(19)
89 #define RCU_INT_PLLSTBIC BIT(20)
90 #define RCU_INT_IRC28MSTBIC BIT(21)
91 #define RCU_INT_CKMIC BIT(23)
93 /* RCU_APB2RST */
94 #define RCU_APB2RST_CFGRST BIT(0)
95 #define RCU_APB2RST_ADCRST BIT(9)
96 #define RCU_APB2RST_TIMER0RST BIT(11)
97 #define RCU_APB2RST_SPI0RST BIT(12)
98 #define RCU_APB2RST_USART0RST BIT(14)
99 #define RCU_APB2RST_TIMER14RST BIT(16)
100 #define RCU_APB2RST_TIMER15RST BIT(17)
101 #define RCU_APB2RST_TIMER16RST BIT(18)
103 /* RCU_APB1RST */
104 #define RCU_APB1RST_TIMER1RST BIT(0)
105 #define RCU_APB1RST_TIMER2RST BIT(1)
106 #define RCU_APB1RST_TIMER5RST BIT(4)
107 #define RCU_APB1RST_TIMER13RST BIT(8)
108 #define RCU_APB1RST_WWDGTRST BIT(11)
109 #define RCU_APB1RST_SPI1RST BIT(14)
110 #define RCU_APB1RST_SPI2RST BIT(15)
111 #define RCU_APB1RST_USART1RST BIT(17)
112 #define RCU_APB1RST_I2C0RST BIT(21)
113 #define RCU_APB1RST_I2C1RST BIT(22)
114 #define RCU_APB1RST_PMURST BIT(28)
115 #define RCU_APB1RST_DACRST BIT(29)
116 #define RCU_APB1RST_CECRST BIT(30)
118 /* RCU_AHBEN */
119 #define RCU_AHBEN_DMAEN BIT(0)
120 #define RCU_AHBEN_SRAMSPEN BIT(2)
121 #define RCU_AHBEN_FMCSPEN BIT(4)
122 #define RCU_AHBEN_CRCEN BIT(6)
123 #define RCU_AHBEN_USBFS BIT(12)
124 #define RCU_AHBEN_PAEN BIT(17)
125 #define RCU_AHBEN_PBEN BIT(18)
126 #define RCU_AHBEN_PCEN BIT(19)
127 #define RCU_AHBEN_PDEN BIT(20)
128 #define RCU_AHBEN_PFEN BIT(22)
129 #define RCU_AHBEN_TSIEN BIT(24)
131 /* RCU_APB2EN */
132 #define RCU_APB2EN_CFGCMPEN BIT(0)
133 #define RCU_APB2EN_ADCEN BIT(9)
134 #define RCU_APB2EN_TIMER0EN BIT(11)
135 #define RCU_APB2EN_SPI0EN BIT(12)
136 #define RCU_APB2EN_USART0EN BIT(14)
137 #define RCU_APB2EN_TIMER14EN BIT(16)
138 #define RCU_APB2EN_TIMER15EN BIT(17)
139 #define RCU_APB2EN_TIMER16EN BIT(18)
141 /* RCU_APB1EN */
142 #define RCU_APB1EN_TIMER1EN BIT(0)
143 #define RCU_APB1EN_TIMER2EN BIT(1)
144 #define RCU_APB1EN_TIMER5EN BIT(4)
145 #define RCU_APB1EN_TIMER13EN BIT(8)
146 #define RCU_APB1EN_WWDGTEN BIT(11)
147 #define RCU_APB1EN_SPI1EN BIT(14)
148 #define RCU_APB1EN_SPI2EN BIT(15)
149 #define RCU_APB1EN_USART1EN BIT(17)
150 #define RCU_APB1EN_I2C0EN BIT(21)
151 #define RCU_APB1EN_I2C1EN BIT(22)
152 #define RCU_APB1EN_PMUEN BIT(28)
153 #define RCU_APB1EN_DACEN BIT(29)
154 #define RCU_APB1EN_CECEN BIT(30)
156 /* RCU_BDCTL */
157 #define RCU_BDCTL_LXTALEN BIT(0)
158 #define RCU_BDCTL_LXTALSTB BIT(1)
159 #define RCU_BDCTL_LXTALBPS BIT(2)
160 #define RCU_BDCTL_LXTALDRI BITS(3,4)
161 #define RCU_BDCTL_RTCSRC BITS(8,9)
162 #define RCU_BDCTL_RTCEN BIT(15)
163 #define RCU_BDCTL_BKPRST BIT(16)
165 /* RCU_RSTSCK */
166 #define RCU_RSTSCK_IRC40KEN BIT(0)
167 #define RCU_RSTSCK_IRC40KSTB BIT(1)
168 #define RCU_RSTSCK_V12RSTF BIT(23)
169 #define RCU_RSTSCK_RSTFC BIT(24)
170 #define RCU_RSTSCK_OBLRSTF BIT(25)
171 #define RCU_RSTSCK_EPRSTF BIT(26)
172 #define RCU_RSTSCK_PORRSTF BIT(27)
173 #define RCU_RSTSCK_SWRSTF BIT(28)
174 #define RCU_RSTSCK_FWDGTRSTF BIT(29)
175 #define RCU_RSTSCK_WWDGTRSTF BIT(30)
176 #define RCU_RSTSCK_LPRSTF BIT(31)
178 /* RCU_AHBRST */
179 #define RCU_AHBRST_USBFSRST BIT(12)
180 #define RCU_AHBRST_PARST BIT(17)
181 #define RCU_AHBRST_PBRST BIT(18)
182 #define RCU_AHBRST_PCRST BIT(19)
183 #define RCU_AHBRST_PDRST BIT(20)
184 #define RCU_AHBRST_PFRST BIT(22)
185 #define RCU_AHBRST_TSIRST BIT(24)
187 /* RCU_CFG1 */
188 #define RCU_CFG1_PREDV BITS(0,3)
189 #define RCU_CFG1_PLLPRESEL BIT(30)
190 #define RCU_CFG1_PLLMF5 BIT(31)
192 /* RCU_CFG2 */
193 #define RCU_CFG2_USART0SEL BITS(0,1)
194 #define RCU_CFG2_CECSEL BIT(6)
195 #define RCU_CFG2_ADCSEL BIT(8)
196 #define RCU_CFG2_IRC28MDIV BIT(16)
197 #define RCU_CFG2_USBFSPSC2 BIT(30)
198 #define RCU_CFG2_ADCPSC2 BIT(31)
200 /* RCU_CTL1 */
201 #define RCU_CTL1_IRC28MEN BIT(0)
202 #define RCU_CTL1_IRC28MSTB BIT(1)
203 #define RCU_CTL1_IRC28MADJ BITS(3,7)
204 #define RCU_CTL1_IRC28MCALIB BITS(8,15)
206 /* RCU_ADDCTL */
207 #define RCU_ADDCTL_CK48MSEL BIT(0)
208 #define RCU_ADDCTL_IRC48MEN BIT(16)
209 #define RCU_ADDCTL_IRC48MSTB BIT(17)
210 #define RCU_ADDCTL_IRC48MCALIB BITS(24,31)
212 /* RCU_ADDINT */
213 #define RCU_ADDINT_IRC48MSTBIF BIT(6)
214 #define RCU_ADDINT_IRC48MSTBIE BIT(14)
215 #define RCU_ADDINT_IRC48MSTBIC BIT(22)
217 /* RCU_ADDAPB1EN */
218 #define RCU_ADDAPB1EN_I2C2EN BIT(0)
219 #define RCU_ADDAPB1EN_CTCEN BIT(27)
221 /* RCU_ADDAPB1RST */
222 #define RCU_ADDAPB1RST_I2C2RST BIT(0)
223 #define RCU_ADDAPB1RST_CTCRST BIT(27)
225 /* RCU_VKEY */
226 #define RCU_VKEY_KEY BITS(0,31)
228 /* RCU_DSV */
229 #define RCU_DSV_DSLPVS BITS(0,1)
231 /* constants definitions */
232 /* define the peripheral clock enable bit position and its register index offset */
233 #define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx)<<6) | (uint32_t)(bitpos))
234 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph)>>6)))
235 #define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
236 /* define the voltage key unlock value */
237 #define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4D)
238
239 /* register index */
240 typedef enum
241 {
242 /* peripherals enable */
243 IDX_AHBEN = 0x14U,
244 IDX_APB2EN = 0x18U,
245 IDX_APB1EN = 0x1CU,
246 IDX_ADDAPB1EN = 0xF8U,
247 /* peripherals reset */
248 IDX_AHBRST = 0x28U,
249 IDX_APB2RST = 0x0CU,
250 IDX_APB1RST = 0x10U,
251 IDX_ADDAPB1RST = 0xFCU,
252 /* clock stabilization */
253 IDX_CTL0 = 0x00U,
254 IDX_BDCTL = 0x20U,
255 IDX_CTL1 = 0x34U,
256 IDX_ADDCTL = 0xC0U,
257 /* peripheral reset */
258 IDX_RSTSCK = 0x24U,
259 /* clock stabilization and stuck interrupt */
260 IDX_INT = 0x08U,
261 IDX_ADDINT = 0xCCU,
262 /* configuration register */
263 IDX_CFG0 = 0x04U,
264 IDX_CFG2 = 0x30U
265 }reg_idx;
266
267 /* peripheral clock enable */
268 typedef enum
269 {
270 /* AHB peripherals */
271 RCU_DMA = RCU_REGIDX_BIT(IDX_AHBEN, 0U),
272 RCU_CRC = RCU_REGIDX_BIT(IDX_AHBEN, 6U),
273 RCU_GPIOA = RCU_REGIDX_BIT(IDX_AHBEN, 17U),
274 RCU_GPIOB = RCU_REGIDX_BIT(IDX_AHBEN, 18U),
275 RCU_GPIOC = RCU_REGIDX_BIT(IDX_AHBEN, 19U),
276 RCU_GPIOD = RCU_REGIDX_BIT(IDX_AHBEN, 20U),
277 RCU_GPIOF = RCU_REGIDX_BIT(IDX_AHBEN, 22U),
278 RCU_TSI = RCU_REGIDX_BIT(IDX_AHBEN, 24U),
280 /* APB2 peripherals */
281 RCU_CFGCMP = RCU_REGIDX_BIT(IDX_APB2EN, 0U),
282 RCU_ADC = RCU_REGIDX_BIT(IDX_APB2EN, 9U),
283 RCU_TIMER0 = RCU_REGIDX_BIT(IDX_APB2EN, 11U),
284 RCU_SPI0 = RCU_REGIDX_BIT(IDX_APB2EN, 12U),
285 RCU_USART0 = RCU_REGIDX_BIT(IDX_APB2EN, 14U),
286 RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U),
287 RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U),
288 RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U),
290 /* APB1 peripherals */
291 RCU_TIMER1 = RCU_REGIDX_BIT(IDX_APB1EN, 0U),
292 RCU_TIMER2 = RCU_REGIDX_BIT(IDX_APB1EN, 1U),
293 RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U),
294 RCU_WWDGT = RCU_REGIDX_BIT(IDX_APB1EN, 11U),
295 RCU_SPI1 = RCU_REGIDX_BIT(IDX_APB1EN, 14U),
296 RCU_SPI2 = RCU_REGIDX_BIT(IDX_APB1EN, 15U),
297 RCU_USART1 = RCU_REGIDX_BIT(IDX_APB1EN, 17U),
298 RCU_I2C0 = RCU_REGIDX_BIT(IDX_APB1EN, 21U),
299 RCU_I2C1 = RCU_REGIDX_BIT(IDX_APB1EN, 22U),
300 RCU_PMU = RCU_REGIDX_BIT(IDX_APB1EN, 28U),
301 #if defined(GD32F350)
302 RCU_DAC = RCU_REGIDX_BIT(IDX_APB1EN, 29U),
303 RCU_CEC = RCU_REGIDX_BIT(IDX_APB1EN, 30U),
304 RCU_TIMER5 = RCU_REGIDX_BIT(IDX_APB1EN, 4U),
305 RCU_USBFS = RCU_REGIDX_BIT(IDX_AHBEN, 12U),
306 #endif /* GD32F350 */
307 RCU_RTC = RCU_REGIDX_BIT(IDX_BDCTL, 15U),
309 /* RCU_ADDAPB1EN */
310 RCU_I2C2 = RCU_REGIDX_BIT(IDX_ADDAPB1EN, 0U),
311 RCU_CTC = RCU_REGIDX_BIT(IDX_ADDAPB1EN, 27U)
312 }rcu_periph_enum;
313
314 /* peripheral clock enable when sleep mode*/
315 typedef enum
316 {
317 /* AHB peripherals */
318 RCU_SRAM_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 2U),
319 RCU_FMC_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 4U),
320 }rcu_periph_sleep_enum;
321
322 /* peripherals reset */
323 typedef enum
324 {
325 /* AHB peripherals reset */
326 RCU_GPIOARST = RCU_REGIDX_BIT(IDX_AHBRST, 17U),
327 RCU_GPIOBRST = RCU_REGIDX_BIT(IDX_AHBRST, 18U),
328 RCU_GPIOCRST = RCU_REGIDX_BIT(IDX_AHBRST, 19U),
329 RCU_GPIODRST = RCU_REGIDX_BIT(IDX_AHBRST, 20U),
330 RCU_GPIOFRST = RCU_REGIDX_BIT(IDX_AHBRST, 22U),
331 RCU_TSIRST = RCU_REGIDX_BIT(IDX_AHBRST, 24U),
333 /* APB2 peripherals reset */
334 RCU_CFGCMPRST = RCU_REGIDX_BIT(IDX_APB2RST, 0U),
335 RCU_ADCRST = RCU_REGIDX_BIT(IDX_APB2RST, 9U),
336 RCU_TIMER0RST = RCU_REGIDX_BIT(IDX_APB2RST, 11U),
337 RCU_SPI0RST = RCU_REGIDX_BIT(IDX_APB2RST, 12U),
338 RCU_USART0RST = RCU_REGIDX_BIT(IDX_APB2RST, 14U),
339 RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U),
340 RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U),
341 RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U),
343 /* APB1 peripherals reset */
344 RCU_TIMER1RST = RCU_REGIDX_BIT(IDX_APB1RST, 0U),
345 RCU_TIMER2RST = RCU_REGIDX_BIT(IDX_APB1RST, 1U),
346 RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U),
347 RCU_WWDGTRST = RCU_REGIDX_BIT(IDX_APB1RST, 11U),
348 RCU_SPI1RST = RCU_REGIDX_BIT(IDX_APB1RST, 14U),
349 RCU_SPI2RST = RCU_REGIDX_BIT(IDX_APB1RST, 15U),
350 RCU_USART1RST = RCU_REGIDX_BIT(IDX_APB1RST, 17U),
351 RCU_I2C0RST = RCU_REGIDX_BIT(IDX_APB1RST, 21U),
352 RCU_I2C1RST = RCU_REGIDX_BIT(IDX_APB1RST, 22U),
353 RCU_PMURST = RCU_REGIDX_BIT(IDX_APB1RST, 28U),
354 #if defined(GD32F350)
355 RCU_DACRST = RCU_REGIDX_BIT(IDX_APB1RST, 29U),
356 RCU_CECRST = RCU_REGIDX_BIT(IDX_APB1RST, 30U),
357 RCU_TIMER5RST = RCU_REGIDX_BIT(IDX_APB1RST, 4U),
358 RCU_USBFSRST = RCU_REGIDX_BIT(IDX_AHBRST, 12U),
359 #endif /* GD32F350 */
360 /* RCU_ADDAPB1RST */
361 RCU_I2C2RST = RCU_REGIDX_BIT(IDX_ADDAPB1RST, 0U),
362 RCU_CTCRST = RCU_REGIDX_BIT(IDX_ADDAPB1RST, 27U),
363 }rcu_periph_reset_enum;
364
365 /* clock stabilization and peripheral reset flags */
366 typedef enum
367 {
368 RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_RSTSCK, 1U),
369 RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_BDCTL, 1U),
370 RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_CTL0, 1U),
371 RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_CTL0, 17U),
372 RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_CTL0, 25U),
373 RCU_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_CTL1, 1U),
374 RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDCTL, 17U),
376 RCU_FLAG_V12RST = RCU_REGIDX_BIT(IDX_RSTSCK, 23U),
377 RCU_FLAG_OBLRST = RCU_REGIDX_BIT(IDX_RSTSCK, 25U),
378 RCU_FLAG_EPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 26U),
379 RCU_FLAG_PORRST = RCU_REGIDX_BIT(IDX_RSTSCK, 27U),
380 RCU_FLAG_SWRST = RCU_REGIDX_BIT(IDX_RSTSCK, 28U),
381 RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 29U),
382 RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 30U),
383 RCU_FLAG_LPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 31U)
384 }rcu_flag_enum;
385
386 /* clock stabilization and ckm interrupt flags */
387 typedef enum
388 {
389 RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 0U),
390 RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 1U),
391 RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 2U),
392 RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 3U),
393 RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 4U),
394 RCU_INT_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 5U),
395 RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(IDX_INT, 7U),
396 RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDCTL, 6U)
397 }rcu_int_flag_enum;
398
399 /* clock stabilization and stuck interrupt flags clear */
400 typedef enum
401 {
402 RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 16U),
403 RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 17U),
404 RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 18U),
405 RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 19U),
406 RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 20U),
407 RCU_INT_FLAG_IRC28MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 21U),
408 RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(IDX_INT, 23U),
409 RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(IDX_ADDCTL, 22U)
410 }rcu_int_flag_clear_enum;
411
412 /* clock stabilization interrupt enable or disable */
413 typedef enum
414 {
415 RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 8U),
416 RCU_INT_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 9U),
417 RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 10U),
418 RCU_INT_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 11U),
419 RCU_INT_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 12U),
420 RCU_INT_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 13U),
421 RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDINT, 14U)
422 }rcu_int_enum;
423
424 /* ADC clock source */
425 typedef enum
426 {
427 RCU_ADCCK_IRC28M_DIV2 = 0U,
428 RCU_ADCCK_IRC28M,
429 RCU_ADCCK_APB2_DIV2,
430 RCU_ADCCK_APB2_DIV3,
431 RCU_ADCCK_APB2_DIV4,
432 RCU_ADCCK_APB2_DIV5,
433 RCU_ADCCK_APB2_DIV6,
434 RCU_ADCCK_APB2_DIV7,
435 RCU_ADCCK_APB2_DIV8,
436 RCU_ADCCK_APB2_DIV9
437 }rcu_adc_clock_enum;
438
439 /* oscillator types */
440 typedef enum
441 {
442 RCU_HXTAL = RCU_REGIDX_BIT(IDX_CTL0, 16U),
443 RCU_LXTAL = RCU_REGIDX_BIT(IDX_BDCTL, 0U),
444 RCU_IRC8M = RCU_REGIDX_BIT(IDX_CTL0, 0U),
445 RCU_IRC28M = RCU_REGIDX_BIT(IDX_CTL1, 0U),
446 RCU_IRC48M = RCU_REGIDX_BIT(IDX_ADDCTL, 16U),
447 RCU_IRC40K = RCU_REGIDX_BIT(IDX_RSTSCK, 0U),
448 RCU_PLL_CK = RCU_REGIDX_BIT(IDX_CTL0, 24U)
449 }rcu_osci_type_enum;
450
451 /* rcu clock frequency */
452 typedef enum
453 {
454 CK_SYS = 0U,
455 CK_AHB,
456 CK_APB1,
457 CK_APB2,
458 CK_ADC,
459 CK_CEC,
460 CK_USART
461 }rcu_clock_freq_enum;
462
463 /* system clock source select */
464 #define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
465 #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0)
466 #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1)
467 #define RCU_CKSYSSRC_PLL CFG0_SCS(2)
469 /* system clock source select status */
470 #define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
471 #define RCU_SCSS_IRC8M CFG0_SCSS(0)
472 #define RCU_SCSS_HXTAL CFG0_SCSS(1)
473 #define RCU_SCSS_PLL CFG0_SCSS(2)
475 /* AHB prescaler selection */
476 #define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
477 #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0)
478 #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8)
479 #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9)
480 #define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10)
481 #define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11)
482 #define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12)
483 #define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13)
484 #define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14)
485 #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15)
487 /* APB1 prescaler selection */
488 #define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
489 #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0)
490 #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4)
491 #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5)
492 #define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6)
493 #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7)
495 /* APB2 prescaler selection */
496 #define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11))
497 #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0)
498 #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4)
499 #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5)
500 #define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6)
501 #define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7)
503 /* ADC clock prescaler selection */
504 #define CFG0_ADCPSC(regval) (BITS(14,15) & ((uint32_t)(regval) << 14))
505 #define RCU_ADC_CKAPB2_DIV2 CFG0_ADCPSC(0)
506 #define RCU_ADC_CKAPB2_DIV4 CFG0_ADCPSC(1)
507 #define RCU_ADC_CKAPB2_DIV6 CFG0_ADCPSC(2)
508 #define RCU_ADC_CKAPB2_DIV8 CFG0_ADCPSC(3)
510 /* PLL clock source selection */
511 #define RCU_PLLSRC_IRC8M_DIV2 (uint32_t)0x00000000U
512 #define RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL
514 /* PLL clock source preselection */
515 #define RCU_PLLPRESEL_HXTAL (uint32_t)0x00000000U
516 #define RCU_PLLPRESEL_IRC48M RCU_CFG1_PLLPRESEL
518 /* HXTAL or IRC48M divider for PLL source clock selection */
519 #define RCU_PLLPREDV (uint32_t)0x00000000U
520 #define RCU_PLLPREDV_DIV2 RCU_CFG0_PLLPREDV
522 /* PLL multiply factor */
523 #define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18))
524 #define RCU_PLL_MUL2 CFG0_PLLMF(0)
525 #define RCU_PLL_MUL3 CFG0_PLLMF(1)
526 #define RCU_PLL_MUL4 CFG0_PLLMF(2)
527 #define RCU_PLL_MUL5 CFG0_PLLMF(3)
528 #define RCU_PLL_MUL6 CFG0_PLLMF(4)
529 #define RCU_PLL_MUL7 CFG0_PLLMF(5)
530 #define RCU_PLL_MUL8 CFG0_PLLMF(6)
531 #define RCU_PLL_MUL9 CFG0_PLLMF(7)
532 #define RCU_PLL_MUL10 CFG0_PLLMF(8)
533 #define RCU_PLL_MUL11 CFG0_PLLMF(9)
534 #define RCU_PLL_MUL12 CFG0_PLLMF(10)
535 #define RCU_PLL_MUL13 CFG0_PLLMF(11)
536 #define RCU_PLL_MUL14 CFG0_PLLMF(12)
537 #define RCU_PLL_MUL15 CFG0_PLLMF(13)
538 #define RCU_PLL_MUL16 CFG0_PLLMF(14)
539 #define RCU_PLL_MUL17 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0))
540 #define RCU_PLL_MUL18 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1))
541 #define RCU_PLL_MUL19 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2))
542 #define RCU_PLL_MUL20 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3))
543 #define RCU_PLL_MUL21 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4))
544 #define RCU_PLL_MUL22 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5))
545 #define RCU_PLL_MUL23 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6))
546 #define RCU_PLL_MUL24 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7))
547 #define RCU_PLL_MUL25 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8))
548 #define RCU_PLL_MUL26 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9))
549 #define RCU_PLL_MUL27 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10))
550 #define RCU_PLL_MUL28 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11))
551 #define RCU_PLL_MUL29 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12))
552 #define RCU_PLL_MUL30 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13))
553 #define RCU_PLL_MUL31 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14))
554 #define RCU_PLL_MUL32 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15))
555 #define RCU_PLL_MUL33 (CFG0_PLLMF(0) | RCU_CFG1_PLLMF5)
556 #define RCU_PLL_MUL34 (CFG0_PLLMF(1) | RCU_CFG1_PLLMF5)
557 #define RCU_PLL_MUL35 (CFG0_PLLMF(2) | RCU_CFG1_PLLMF5)
558 #define RCU_PLL_MUL36 (CFG0_PLLMF(3) | RCU_CFG1_PLLMF5)
559 #define RCU_PLL_MUL37 (CFG0_PLLMF(4) | RCU_CFG1_PLLMF5)
560 #define RCU_PLL_MUL38 (CFG0_PLLMF(5) | RCU_CFG1_PLLMF5)
561 #define RCU_PLL_MUL39 (CFG0_PLLMF(6) | RCU_CFG1_PLLMF5)
562 #define RCU_PLL_MUL40 (CFG0_PLLMF(7) | RCU_CFG1_PLLMF5)
563 #define RCU_PLL_MUL41 (CFG0_PLLMF(8) | RCU_CFG1_PLLMF5)
564 #define RCU_PLL_MUL42 (CFG0_PLLMF(9) | RCU_CFG1_PLLMF5)
565 #define RCU_PLL_MUL43 (CFG0_PLLMF(10) | RCU_CFG1_PLLMF5)
566 #define RCU_PLL_MUL44 (CFG0_PLLMF(11) | RCU_CFG1_PLLMF5)
567 #define RCU_PLL_MUL45 (CFG0_PLLMF(12) | RCU_CFG1_PLLMF5)
568 #define RCU_PLL_MUL46 (CFG0_PLLMF(13) | RCU_CFG1_PLLMF5)
569 #define RCU_PLL_MUL47 (CFG0_PLLMF(14) | RCU_CFG1_PLLMF5)
570 #define RCU_PLL_MUL48 (CFG0_PLLMF(15) | RCU_CFG1_PLLMF5)
571 #define RCU_PLL_MUL49 (RCU_CFG0_PLLMF4 | RCU_CFG1_PLLMF5)
572 #define RCU_PLL_MUL50 (RCU_PLL_MUL18 | RCU_CFG1_PLLMF5)
573 #define RCU_PLL_MUL51 (RCU_PLL_MUL19 | RCU_CFG1_PLLMF5)
574 #define RCU_PLL_MUL52 (RCU_PLL_MUL20 | RCU_CFG1_PLLMF5)
575 #define RCU_PLL_MUL53 (RCU_PLL_MUL21 | RCU_CFG1_PLLMF5)
576 #define RCU_PLL_MUL54 (RCU_PLL_MUL22 | RCU_CFG1_PLLMF5)
577 #define RCU_PLL_MUL55 (RCU_PLL_MUL23 | RCU_CFG1_PLLMF5)
578 #define RCU_PLL_MUL56 (RCU_PLL_MUL24 | RCU_CFG1_PLLMF5)
579 #define RCU_PLL_MUL57 (RCU_PLL_MUL25 | RCU_CFG1_PLLMF5)
580 #define RCU_PLL_MUL58 (RCU_PLL_MUL26 | RCU_CFG1_PLLMF5)
581 #define RCU_PLL_MUL59 (RCU_PLL_MUL27 | RCU_CFG1_PLLMF5)
582 #define RCU_PLL_MUL60 (RCU_PLL_MUL28 | RCU_CFG1_PLLMF5)
583 #define RCU_PLL_MUL61 (RCU_PLL_MUL29 | RCU_CFG1_PLLMF5)
584 #define RCU_PLL_MUL62 (RCU_PLL_MUL30 | RCU_CFG1_PLLMF5)
585 #define RCU_PLL_MUL63 (RCU_PLL_MUL31 | RCU_CFG1_PLLMF5)
586 #define RCU_PLL_MUL64 (RCU_PLL_MUL32 | RCU_CFG1_PLLMF5)
588 /* USBFS clock prescaler selection */
589 #define CFG0_USBFSPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22))
590 #define RCU_USBFS_CKPLL_DIV1_5 CFG0_USBFSPSC(0)
591 #define RCU_USBFS_CKPLL_DIV1 CFG0_USBFSPSC(1)
592 #define RCU_USBFS_CKPLL_DIV2_5 CFG0_USBFSPSC(2)
593 #define RCU_USBFS_CKPLL_DIV2 CFG0_USBFSPSC(3)
594 #define RCU_USBFS_CKPLL_DIV3 RCU_CFG2_USBFSPSC2
595 #define RCU_USBFS_CKPLL_DIV3_5 (CFG0_USBFSPSC(1)|RCU_CFG2_USBFSPSC2)
597 /* CK_OUT clock source selection */
598 #define CFG0_CKOUTSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
599 #define RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0)
600 #define RCU_CKOUTSRC_IRC28M CFG0_CKOUTSEL(1)
601 #define RCU_CKOUTSRC_IRC40K CFG0_CKOUTSEL(2)
602 #define RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3)
603 #define RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4)
604 #define RCU_CKOUTSRC_IRC8M CFG0_CKOUTSEL(5)
605 #define RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6)
606 #define RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7))
607 #define RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7)
609 /* CK_OUT divider */
610 #define CFG0_CKOUTDIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28))
611 #define RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0)
612 #define RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1)
613 #define RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2)
614 #define RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3)
615 #define RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4)
616 #define RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5)
617 #define RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6)
618 #define RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7)
620 /* CK_PLL divide by 1 or 2 for CK_OUT */
621 #define RCU_PLLDV_CKPLL_DIV2 (uint32_t)0x00000000U
622 #define RCU_PLLDV_CKPLL RCU_CFG0_PLLDV
624 /* LXTAL drive capability */
625 #define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3))
626 #define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0)
627 #define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1)
628 #define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2)
629 #define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3)
631 /* RTC clock entry selection */
632 #define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
633 #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0)
634 #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1)
635 #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2)
636 #define RCU_RTCSRC_HXTAL_DIV32 BDCTL_RTCSRC(3)
638 /* CK_HXTAL divider previous PLL */
639 #define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
640 #define RCU_PLL_PREDV1 CFG1_PREDV(0)
641 #define RCU_PLL_PREDV2 CFG1_PREDV(1)
642 #define RCU_PLL_PREDV3 CFG1_PREDV(2)
643 #define RCU_PLL_PREDV4 CFG1_PREDV(3)
644 #define RCU_PLL_PREDV5 CFG1_PREDV(4)
645 #define RCU_PLL_PREDV6 CFG1_PREDV(5)
646 #define RCU_PLL_PREDV7 CFG1_PREDV(6)
647 #define RCU_PLL_PREDV8 CFG1_PREDV(7)
648 #define RCU_PLL_PREDV9 CFG1_PREDV(8)
649 #define RCU_PLL_PREDV10 CFG1_PREDV(9)
650 #define RCU_PLL_PREDV11 CFG1_PREDV(10)
651 #define RCU_PLL_PREDV12 CFG1_PREDV(11)
652 #define RCU_PLL_PREDV13 CFG1_PREDV(12)
653 #define RCU_PLL_PREDV14 CFG1_PREDV(13)
654 #define RCU_PLL_PREDV15 CFG1_PREDV(14)
655 #define RCU_PLL_PREDV16 CFG1_PREDV(15)
657 /* USART0 clock source selection */
658 #define CFG2_USART0SEL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
659 #define RCU_USART0SRC_CKAPB2 CFG2_USART0SEL(0)
660 #define RCU_USART0SRC_CKSYS CFG2_USART0SEL(1)
661 #define RCU_USART0SRC_LXTAL CFG2_USART0SEL(2)
662 #define RCU_USART0SRC_IRC8M CFG2_USART0SEL(3)
664 /* CEC clock source selection */
665 #define RCU_CECSRC_IRC8M_DIV244 (uint32_t)0x00000000U
666 #define RCU_CECSRC_LXTAL RCU_CFG2_CECSEL
668 /* ADC clock source selection */
669 #define RCU_ADCSRC_IRC28M (uint32_t)0x00000000U
670 #define RCU_ADCSRC_APB2DIV RCU_CFG2_ADCSEL
672 /* IRC28M clock divider for ADC */
673 #define RCU_ADC_IRC28M_DIV2 (uint32_t)0x00000000U
674 #define RCU_ADC_IRC28M_DIV1 RCU_CFG2_IRC28MDIV
676 /* Deep-sleep mode voltage */
677 #define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
678 #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0)
679 #define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1)
680 #define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2)
681 #define RCU_DEEPSLEEP_V_0_7 DSV_DSLPVS(3)
683 /* function declarations */
684 /* deinitialize the RCU */
685 void rcu_deinit(void);
686 /* enable the peripherals clock */
687 void rcu_periph_clock_enable(rcu_periph_enum periph);
688 /* disable the peripherals clock */
689 void rcu_periph_clock_disable(rcu_periph_enum periph);
690 /* enable the peripherals clock when sleep mode */
691 void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph);
692 /* disable the peripherals clock when sleep mode */
693 void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph);
694 /* reset the peripherals */
695 void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset);
696 /* disable reset the peripheral */
697 void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset);
698 /* reset the BKP */
699 void rcu_bkp_reset_enable(void);
700 /* disable the BKP reset */
701 void rcu_bkp_reset_disable(void);
702
703 /* configure the system clock source */
704 void rcu_system_clock_source_config(uint32_t ck_sys);
705 /* get the system clock source */
706 uint32_t rcu_system_clock_source_get(void);
707 /* configure the AHB prescaler selection */
708 void rcu_ahb_clock_config(uint32_t ck_ahb);
709 /* configure the APB1 prescaler selection */
710 void rcu_apb1_clock_config(uint32_t ck_apb1);
711 /* configure the APB2 prescaler selection */
712 void rcu_apb2_clock_config(uint32_t ck_apb2);
713 /* configure the ADC clock source and prescaler selection */
714 void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc);
715 /* configure the USBFS prescaler selection */
716 void rcu_usbfs_clock_config(uint32_t ck_usbfs);
717 /* configure the CK_OUT clock source and divider */
718 void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div);
719
720 /* configure the PLL clock source preselection */
721 void rcu_pll_preselection_config(uint32_t pll_presel);
722 /* configure the PLL clock source selection and PLL multiply factor */
723 void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul);
724 /* configure the USART clock source selection */
725 void rcu_usart_clock_config(uint32_t ck_usart);
726 /* configure the CEC clock source selection */
727 void rcu_cec_clock_config(uint32_t ck_cec);
728 /* configure the RTC clock source selection */
729 void rcu_rtc_clock_config(uint32_t rtc_clock_source);
730 /* configure the HXTAL divider used as input of PLL */
731 void rcu_hxtal_prediv_config(uint32_t hxtal_prediv);
732 /* configure the LXTAL drive capability */
733 void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap);
734
735 /* get the clock stabilization and periphral reset flags */
736 FlagStatus rcu_flag_get(rcu_flag_enum flag);
737 /* clear the reset flag */
738 void rcu_all_reset_flag_clear(void);
739 /* get the clock stabilization interrupt and ckm flags */
740 FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag);
741 /* clear the interrupt flags */
742 void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear);
743 /* enable the stabilization interrupt */
744 void rcu_interrupt_enable(rcu_int_enum stab_int);
745 /* disable the stabilization interrupt */
746 void rcu_interrupt_disable(rcu_int_enum stab_int);
747
748 /* wait until oscillator stabilization flags is SET */
749 ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci);
750 /* turn on the oscillator */
751 void rcu_osci_on(rcu_osci_type_enum osci);
752 /* turn off the oscillator */
753 void rcu_osci_off(rcu_osci_type_enum osci);
754 /* enable the oscillator bypass mode */
755 void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci);
756 /* disable the oscillator bypass mode */
757 void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci);
758 /* enable the HXTAL clock monitor */
759 void rcu_hxtal_clock_monitor_enable(void);
760 /* disable the HXTAL clock monitor */
761 void rcu_hxtal_clock_monitor_disable(void);
762
763 /* set the IRC8M adjust value */
764 void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval);
765 /* set the IRC28M adjust value */
766 void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval);
767 /* unlock the voltage key */
768 void rcu_voltage_key_unlock(void);
769 /* set the deep sleep mode voltage */
770 void rcu_deepsleep_voltage_set(uint32_t dsvol);
771
772 /* get the system clock, bus and peripheral clock frequency */
773 uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock);
774
775 #endif /* GD32F3X0_RCU_H */
RCU_I2C1RST
Definition: gd32f3x0_rcu.h:352
RCU_INT_FLAG_IRC48MSTB_CLR
Definition: gd32f3x0_rcu.h:409
RCU_GPIOCRST
Definition: gd32f3x0_rcu.h:328
RCU_TIMER0
Definition: gd32f3x0_rcu.h:283
CK_APB1
Definition: gd32f3x0_rcu.h:456
IDX_RSTSCK
Definition: gd32f3x0_rcu.h:258
rcu_clock_freq_enum
rcu_clock_freq_enum
Definition: gd32f3x0_rcu.h:452
RCU_USART0RST
Definition: gd32f3x0_rcu.h:338
rcu_periph_clock_sleep_enable
void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
enable the peripherals clock when sleep mode
Definition: gd32f3x0_rcu.c:121
RCU_GPIOBRST
Definition: gd32f3x0_rcu.h:327
RCU_ADCCK_APB2_DIV3
Definition: gd32f3x0_rcu.h:430
RCU_DMA
Definition: gd32f3x0_rcu.h:271
RCU_FLAG_HXTALSTB
Definition: gd32f3x0_rcu.h:371
RCU_GPIOF
Definition: gd32f3x0_rcu.h:277
IDX_CFG2
Definition: gd32f3x0_rcu.h:264
RCU_INT_FLAG_HXTALSTB
Definition: gd32f3x0_rcu.h:392
rcu_interrupt_flag_get
FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
get the clock stabilization interrupt and ckm flags
Definition: gd32f3x0_rcu.c:594
RCU_CFGCMP
Definition: gd32f3x0_rcu.h:281
RCU_INT_IRC48MSTB
Definition: gd32f3x0_rcu.h:421
RCU_INT_FLAG_IRC28MSTB
Definition: gd32f3x0_rcu.h:394
RCU_FLAG_PORRST
Definition: gd32f3x0_rcu.h:379
RCU_I2C2
Definition: gd32f3x0_rcu.h:310
RCU_TIMER2
Definition: gd32f3x0_rcu.h:292
rcu_interrupt_enable
void rcu_interrupt_enable(rcu_int_enum stab_int)
enable the stabilization interrupt
Definition: gd32f3x0_rcu.c:637
rcu_usbfs_clock_config
void rcu_usbfs_clock_config(uint32_t ck_usbfs)
configure the USBFS clock prescaler selection
Definition: gd32f3x0_rcu.c:387
RCU_INT_FLAG_PLLSTB
Definition: gd32f3x0_rcu.h:393
RCU_TSIRST
Definition: gd32f3x0_rcu.h:331
rcu_osci_off
void rcu_osci_off(rcu_osci_type_enum osci)
turn off the oscillator
Definition: gd32f3x0_rcu.c:794
rcu_flag_get
FlagStatus rcu_flag_get(rcu_flag_enum flag)
get the clock stabilization and periphral reset flags
Definition: gd32f3x0_rcu.c:559
RCU_TIMER16
Definition: gd32f3x0_rcu.h:288
IDX_ADDCTL
Definition: gd32f3x0_rcu.h:256
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
rcu_system_clock_source_get
uint32_t rcu_system_clock_source_get(void)
get the system clock source
Definition: gd32f3x0_rcu.c:241
rcu_osci_on
void rcu_osci_on(rcu_osci_type_enum osci)
turn on the oscillator
Definition: gd32f3x0_rcu.c:776
RCU_INT_FLAG_HXTALSTB_CLR
Definition: gd32f3x0_rcu.h:405
CK_ADC
Definition: gd32f3x0_rcu.h:458
RCU_ADCCK_APB2_DIV6
Definition: gd32f3x0_rcu.h:433
rcu_pll_config
void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
configure the PLL clock source selection and PLL multiply factor
Definition: gd32f3x0_rcu.c:447
IDX_CFG0
Definition: gd32f3x0_rcu.h:263
RCU_SPI0
Definition: gd32f3x0_rcu.h:284
RCU_INT_FLAG_IRC40KSTB
Definition: gd32f3x0_rcu.h:389
RCU_ADCCK_IRC28M
Definition: gd32f3x0_rcu.h:428
RCU_TIMER15
Definition: gd32f3x0_rcu.h:287
RCU_FLAG_WWDGTRST
Definition: gd32f3x0_rcu.h:382
RCU_GPIOB
Definition: gd32f3x0_rcu.h:274
IDX_ADDAPB1EN
Definition: gd32f3x0_rcu.h:246
RCU_FLAG_IRC40KSTB
Definition: gd32f3x0_rcu.h:368
RCU_IRC48M
Definition: gd32f3x0_rcu.h:446
RCU_ADCCK_APB2_DIV5
Definition: gd32f3x0_rcu.h:432
RCU_INT_LXTALSTB
Definition: gd32f3x0_rcu.h:416
RCU_INT_FLAG_CKM
Definition: gd32f3x0_rcu.h:395
RCU_ADCCK_APB2_DIV9
Definition: gd32f3x0_rcu.h:436
rcu_osci_bypass_mode_disable
void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
Definition: gd32f3x0_rcu.c:842
rcu_rtc_clock_config
void rcu_rtc_clock_config(uint32_t rtc_clock_source)
configure the RTC clock source selection
Definition: gd32f3x0_rcu.c:497
IDX_APB2RST
Definition: gd32f3x0_rcu.h:249
IDX_CTL1
Definition: gd32f3x0_rcu.h:255
RCU_FLAG_IRC28MSTB
Definition: gd32f3x0_rcu.h:373
rcu_interrupt_flag_clear
void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
clear the interrupt flags
Definition: gd32f3x0_rcu.c:618
CK_USART
Definition: gd32f3x0_rcu.h:460
RCU_ADCCK_APB2_DIV7
Definition: gd32f3x0_rcu.h:434
RCU_USART1RST
Definition: gd32f3x0_rcu.h:350
RCU_FLAG_OBLRST
Definition: gd32f3x0_rcu.h:377
rcu_adc_clock_config
void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc)
configure the ADC clock prescaler selection
Definition: gd32f3x0_rcu.c:318
CK_SYS
Definition: gd32f3x0_rcu.h:454
RCU_CRC
Definition: gd32f3x0_rcu.h:272
RCU_TIMER14
Definition: gd32f3x0_rcu.h:286
RCU_I2C1
Definition: gd32f3x0_rcu.h:299
RCU_SRAM_SLP
Definition: gd32f3x0_rcu.h:318
RCU_WWDGT
Definition: gd32f3x0_rcu.h:294
RCU_INT_FLAG_IRC8MSTB_CLR
Definition: gd32f3x0_rcu.h:404
IDX_APB2EN
Definition: gd32f3x0_rcu.h:244
RCU_HXTAL
Definition: gd32f3x0_rcu.h:442
CK_AHB
Definition: gd32f3x0_rcu.h:455
IDX_APB1EN
Definition: gd32f3x0_rcu.h:245
rcu_system_clock_source_config
void rcu_system_clock_source_config(uint32_t ck_sys)
configure the system clock source
Definition: gd32f3x0_rcu.c:223
RCU_FLAG_LXTALSTB
Definition: gd32f3x0_rcu.h:369
RCU_FLAG_SWRST
Definition: gd32f3x0_rcu.h:380
RCU_FLAG_PLLSTB
Definition: gd32f3x0_rcu.h:372
rcu_osci_bypass_mode_enable
void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
Definition: gd32f3x0_rcu.c:807
RCU_SPI2
Definition: gd32f3x0_rcu.h:296
RCU_IRC28M
Definition: gd32f3x0_rcu.h:445
RCU_I2C0RST
Definition: gd32f3x0_rcu.h:351
RCU_I2C0
Definition: gd32f3x0_rcu.h:298
rcu_periph_enum
rcu_periph_enum
Definition: gd32f3x0_rcu.h:268
rcu_cec_clock_config
void rcu_cec_clock_config(uint32_t ck_cec)
configure the CEC clock source selection
Definition: gd32f3x0_rcu.c:480
rcu_periph_clock_enable
void rcu_periph_clock_enable(rcu_periph_enum periph)
enable the peripherals clock
Definition: gd32f3x0_rcu.c:78
rcu_adc_clock_enum
rcu_adc_clock_enum
Definition: gd32f3x0_rcu.h:425
rcu_periph_clock_sleep_disable
void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
disable the peripherals clock when sleep mode
Definition: gd32f3x0_rcu.c:135
RCU_FLAG_LPRST
Definition: gd32f3x0_rcu.h:383
RCU_SPI0RST
Definition: gd32f3x0_rcu.h:337
rcu_voltage_key_unlock
void rcu_voltage_key_unlock(void)
unlock the voltage key
Definition: gd32f3x0_rcu.c:927
RCU_FMC_SLP
Definition: gd32f3x0_rcu.h:319
RCU_TIMER1RST
Definition: gd32f3x0_rcu.h:344
RCU_INT_FLAG_IRC40KSTB_CLR
Definition: gd32f3x0_rcu.h:402
reg_idx
reg_idx
Definition: gd32f3x0_rcu.h:240
rcu_apb2_clock_config
void rcu_apb2_clock_config(uint32_t ck_apb2)
configure the APB2 clock prescaler selection
Definition: gd32f3x0_rcu.c:293
RCU_FLAG_V12RST
Definition: gd32f3x0_rcu.h:376
RCU_INT_IRC28MSTB
Definition: gd32f3x0_rcu.h:420
RCU_FLAG_FWDGTRST
Definition: gd32f3x0_rcu.h:381
IDX_AHBEN
Definition: gd32f3x0_rcu.h:243
RCU_USART0
Definition: gd32f3x0_rcu.h:285
RCU_INT_FLAG_PLLSTB_CLR
Definition: gd32f3x0_rcu.h:406
RCU_TIMER13RST
Definition: gd32f3x0_rcu.h:346
CK_APB2
Definition: gd32f3x0_rcu.h:457
rcu_bkp_reset_enable
void rcu_bkp_reset_enable(void)
reset the BKP
Definition: gd32f3x0_rcu.c:197
RCU_CTCRST
Definition: gd32f3x0_rcu.h:362
rcu_periph_reset_enum
rcu_periph_reset_enum
Definition: gd32f3x0_rcu.h:323
rcu_interrupt_disable
void rcu_interrupt_disable(rcu_int_enum stab_int)
disable the stabilization interrupt
Definition: gd32f3x0_rcu.c:657
RCU_INT_IRC40KSTB
Definition: gd32f3x0_rcu.h:415
rcu_ahb_clock_config
void rcu_ahb_clock_config(uint32_t ck_ahb)
configure the AHB clock prescaler selection
Definition: gd32f3x0_rcu.c:253
RCU_TIMER14RST
Definition: gd32f3x0_rcu.h:339
RCU_PMU
Definition: gd32f3x0_rcu.h:300
RCU_INT_FLAG_CKM_CLR
Definition: gd32f3x0_rcu.h:408
RCU_INT_FLAG_IRC28MSTB_CLR
Definition: gd32f3x0_rcu.h:407
RCU_IRC8M
Definition: gd32f3x0_rcu.h:444
CK_CEC
Definition: gd32f3x0_rcu.h:459
rcu_hxtal_clock_monitor_disable
void rcu_hxtal_clock_monitor_disable(void)
disable the HXTAL clock monitor
Definition: gd32f3x0_rcu.c:886
RCU_CFGCMPRST
Definition: gd32f3x0_rcu.h:334
RCU_ADCRST
Definition: gd32f3x0_rcu.h:335
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
RCU_I2C2RST
Definition: gd32f3x0_rcu.h:361
RCU_TIMER1
Definition: gd32f3x0_rcu.h:291
rcu_int_enum
rcu_int_enum
Definition: gd32f3x0_rcu.h:413
rcu_all_reset_flag_clear
void rcu_all_reset_flag_clear(void)
clear the reset flag
Definition: gd32f3x0_rcu.c:574
rcu_deepsleep_voltage_set
void rcu_deepsleep_voltage_set(uint32_t dsvol)
set voltage in deep sleep mode
Definition: gd32f3x0_rcu.c:944
RCU_INT_FLAG_IRC48MSTB
Definition: gd32f3x0_rcu.h:396
RCU_GPIOARST
Definition: gd32f3x0_rcu.h:326
RCU_INT_IRC8MSTB
Definition: gd32f3x0_rcu.h:417
IDX_ADDINT
Definition: gd32f3x0_rcu.h:261
rcu_int_flag_clear_enum
rcu_int_flag_clear_enum
Definition: gd32f3x0_rcu.h:400
RCU_RTC
Definition: gd32f3x0_rcu.h:307
RCU_ADCCK_APB2_DIV8
Definition: gd32f3x0_rcu.h:435
RCU_SPI1RST
Definition: gd32f3x0_rcu.h:348
rcu_flag_enum
rcu_flag_enum
Definition: gd32f3x0_rcu.h:366
rcu_periph_clock_disable
void rcu_periph_clock_disable(rcu_periph_enum periph)
disable the peripherals clock
Definition: gd32f3x0_rcu.c:107
IDX_ADDAPB1RST
Definition: gd32f3x0_rcu.h:251
RCU_USART1
Definition: gd32f3x0_rcu.h:297
RCU_INT_FLAG_LXTALSTB_CLR
Definition: gd32f3x0_rcu.h:403
rcu_apb1_clock_config
void rcu_apb1_clock_config(uint32_t ck_apb1)
configure the APB1 clock prescaler selection
Definition: gd32f3x0_rcu.c:273
RCU_PLL_CK
Definition: gd32f3x0_rcu.h:448
rcu_irc28m_adjust_value_set
void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval)
set the IRC28M adjust value
Definition: gd32f3x0_rcu.c:912
RCU_REGIDX_BIT
#define RCU_REGIDX_BIT(regidx, bitpos)
Definition: gd32f3x0_rcu.h:233
rcu_hxtal_prediv_config
void rcu_hxtal_prediv_config(uint32_t hxtal_prediv)
configure the HXTAL divider used as input of PLL
Definition: gd32f3x0_rcu.c:511
rcu_usart_clock_config
void rcu_usart_clock_config(uint32_t ck_usart)
configure the USART clock source selection
Definition: gd32f3x0_rcu.c:465
rcu_deinit
void rcu_deinit(void)
deinitialize the RCU
Definition: gd32f3x0_rcu.c:29
RCU_INT_HXTALSTB
Definition: gd32f3x0_rcu.h:418
RCU_FLAG_IRC8MSTB
Definition: gd32f3x0_rcu.h:370
IDX_APB1RST
Definition: gd32f3x0_rcu.h:250
RCU_ADC
Definition: gd32f3x0_rcu.h:282
rcu_periph_sleep_enum
rcu_periph_sleep_enum
Definition: gd32f3x0_rcu.h:315
RCU_GPIOC
Definition: gd32f3x0_rcu.h:275
RCU_TIMER13
Definition: gd32f3x0_rcu.h:293
RCU_TIMER0RST
Definition: gd32f3x0_rcu.h:336
IDX_AHBRST
Definition: gd32f3x0_rcu.h:248
rcu_osci_stab_wait
ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
wait until oscillator stabilization flags is SET
Definition: gd32f3x0_rcu.c:675
RCU_ADCCK_IRC28M_DIV2
Definition: gd32f3x0_rcu.h:427
RCU_GPIODRST
Definition: gd32f3x0_rcu.h:329
RCU_ADCCK_APB2_DIV4
Definition: gd32f3x0_rcu.h:431
RCU_WWDGTRST
Definition: gd32f3x0_rcu.h:347
RCU_SPI2RST
Definition: gd32f3x0_rcu.h:349
rcu_int_flag_enum
rcu_int_flag_enum
Definition: gd32f3x0_rcu.h:387
RCU_CTC
Definition: gd32f3x0_rcu.h:311
RCU_LXTAL
Definition: gd32f3x0_rcu.h:443
RCU_IRC40K
Definition: gd32f3x0_rcu.h:447
rcu_lxtal_drive_capability_config
void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap)
configure the LXTAL drive capability
Definition: gd32f3x0_rcu.c:530
RCU_ADCCK_APB2_DIV2
Definition: gd32f3x0_rcu.h:429
RCU_TSI
Definition: gd32f3x0_rcu.h:278
RCU_SPI1
Definition: gd32f3x0_rcu.h:295
RCU_INT_FLAG_IRC8MSTB
Definition: gd32f3x0_rcu.h:391
rcu_osci_type_enum
rcu_osci_type_enum
Definition: gd32f3x0_rcu.h:440
RCU_FLAG_EPRST
Definition: gd32f3x0_rcu.h:378
rcu_bkp_reset_disable
void rcu_bkp_reset_disable(void)
disable the BKP reset
Definition: gd32f3x0_rcu.c:208
RCU_TIMER15RST
Definition: gd32f3x0_rcu.h:340
RCU_GPIOA
Definition: gd32f3x0_rcu.h:273
rcu_irc8m_adjust_value_set
void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval)
set the IRC8M adjust value
Definition: gd32f3x0_rcu.c:897
IDX_CTL0
Definition: gd32f3x0_rcu.h:253
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f3x0_rcu.c:964
rcu_ckout_config
void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div)
configure the CK_OUT clock source and divider
Definition: gd32f3x0_rcu.c:414
IDX_INT
Definition: gd32f3x0_rcu.h:260
RCU_GPIOD
Definition: gd32f3x0_rcu.h:276
rcu_pll_preselection_config
void rcu_pll_preselection_config(uint32_t pll_presel)
configure the PLL clock source preselection
Definition: gd32f3x0_rcu.c:431
IDX_BDCTL
Definition: gd32f3x0_rcu.h:254
rcu_hxtal_clock_monitor_enable
void rcu_hxtal_clock_monitor_enable(void)
enable the HXTAL clock monitor
Definition: gd32f3x0_rcu.c:875
RCU_PMURST
Definition: gd32f3x0_rcu.h:353
RCU_FLAG_IRC48MSTB
Definition: gd32f3x0_rcu.h:374
RCU_TIMER16RST
Definition: gd32f3x0_rcu.h:341
RCU_GPIOFRST
Definition: gd32f3x0_rcu.h:330
RCU_INT_PLLSTB
Definition: gd32f3x0_rcu.h:419
RCU_INT_FLAG_LXTALSTB
Definition: gd32f3x0_rcu.h:390
RCU_TIMER2RST
Definition: gd32f3x0_rcu.h:345
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usb_defines.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
usb_defines.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef USB_DEFINES_H
13 #define USB_DEFINES_H
14
15 #include "usb_conf.h"
16
17 #ifndef NULL
18 #define NULL (void *)0
19 #endif /* NULL */
20
21 #define USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */
22 #define USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */
23
24 #define USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */
25 #define USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */
26 #define USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */
27 #define USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */
28
29 #define USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */
30 #define USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */
31 #define USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */
32 #define USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */
33
34 #define USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */
35 #define USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */
36
37 #define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */
38 #define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */
39 #define DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */
40 #define DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */
41
42 #define GRSTATR_RPCKST_IN 2U /* IN data packet received */
43 #define GRSTATR_RPCKST_IN_XFER_COMP 3U /* IN transfer completed (generates an interrupt if poped) */
44 #define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* data toggle error (generates an interrupt if poped) */
45 #define GRSTATR_RPCKST_CH_HALTED 7U /* channel halted (generates an interrupt if poped) */
46
47 #define DEVICE_MODE 0U /* USB core in device mode */
48 #define HOST_MODE 1U /* USB core in host mode */
49 #define OTG_MODE 2U /* USB core in OTG mode */
50
51 #define USB_EPTYPE_CTRL 0U /* USB control endpoint type */
52 #define USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */
53 #define USB_EPTYPE_BULK 2U /* USB bulk endpoint type */
54 #define USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */
55 #define USB_EPTYPE_MASK 3U /* USB endpoint type mask */
56
57 #define RXSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */
58 #define RXSTAT_DATA_UPDT 2U /* OUT data packet received */
59 #define RXSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */
60 #define RXSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */
61 #define RXSTAT_SETUP_UPDT 6U /* SETUP data packet received */
62
63 #define DPID_DATA0 0U /* device endpoint data PID is DATA0 */
64 #define DPID_DATA1 2U /* device endpoint data PID is DATA1 */
65 #define DPID_DATA2 1U /* device endpoint data PID is DATA2 */
66 #define DPID_MDATA 3U /* device endpoint data PID is MDATA */
67
68 #define HC_PID_DATA0 0U /* host channel data PID is DATA0 */
69 #define HC_PID_DATA2 1U /* host channel data PID is DATA2 */
70 #define HC_PID_DATA1 2U /* host channel data PID is DATA1 */
71 #define HC_PID_SETUP 3U /* host channel data PID is SETUP */
72
73 #define HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */
74 #define HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */
75 #define HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */
76
77 #define HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */
78 #define HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */
79 #define HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */
80
81 #define HCCHAR_CTRL 0U /* control channel type */
82 #define HCCHAR_ISOC 1U /* synchronous channel type */
83 #define HCCHAR_BULK 2U /* bulk channel type */
84 #define HCCHAR_INTR 3U /* interrupt channel type */
85
86 typedef enum
87 {
88 USB_HS_CORE_ID = 0,
89 USB_FS_CORE_ID = 1
90 }usb_core_id_enum;
91
92 typedef enum
93 {
94 USB_SPEED_UNKNOWN = 0,
95 USB_SPEED_LOW,
96 USB_SPEED_FULL,
97 USB_SPEED_HIGH
98 }usb_speed_enum;
99
100 #endif /* USB_DEFINES_H */
USB_HS_CORE_ID
Definition: usb_defines.h:88
USB_SPEED_FULL
Definition: usb_defines.h:96
usb_speed_enum
usb_speed_enum
Definition: usb_defines.h:92
USB_SPEED_UNKNOWN
Definition: usb_defines.h:94
USB_SPEED_HIGH
Definition: usb_defines.h:97
USB_SPEED_LOW
Definition: usb_defines.h:95
USB_FS_CORE_ID
Definition: usb_defines.h:89
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:86
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/system_gd32f3x0.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
system_gd32f3x0.c
Go to the documentation of this file.
1
7 /* Copyright (c) 2012 ARM LIMITED
8
9 All rights reserved.
10 Redistribution and use in source and binary forms, with or without
11 modification, are permitted provided that the following conditions are met:
12 - Redistributions of source code must retain the above copyright
13 notice, this list of conditions and the following disclaimer.
14 - Redistributions in binary form must reproduce the above copyright
15 notice, this list of conditions and the following disclaimer in the
16 documentation and/or other materials provided with the distribution.
17 - Neither the name of ARM nor the names of its contributors may be used
18 to endorse or promote products derived from this software without
19 specific prior written permission.
20 *
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 ---------------------------------------------------------------------------*/
33
34 /* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
35
36 #include "gd32f3x0.h"
37
38 /* system frequency define */
39 #define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
40 #define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
41 #define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
42
43 /* select a system clock by uncommenting the following line */
44 #if defined (GD32F330)
45 //#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL)
46 //#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M)
47 //#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
48 //#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000)
49 #define __SYSTEM_CLOCK_84M_PLL_HXTAL (uint32_t)(84000000)
50 //#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2 (uint32_t)(84000000)
51 #endif /* GD32F330 */
52
53 #if defined (GD32F350)
54 //#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL)
55 //#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M)
56 //#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
57 //#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000)
58 //#define __SYSTEM_CLOCK_84M_PLL_HXTAL (uint32_t)(84000000)
59 //#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2 (uint32_t)(84000000)
60 #define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000)
61 //#define __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2 (uint32_t)(96000000)
62 //#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000)
63 //#define __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2 (uint32_t)(108000000)
64 #endif /* GD32F350 */
65
66 #define SEL_IRC8M 0x00
67 #define SEL_HXTAL 0x01
68 #define SEL_PLL 0x02
69
70 /* set the system clock frequency and declare the system clock configuration function */
71 #ifdef __SYSTEM_CLOCK_8M_HXTAL
72 uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL;
73 static void system_clock_8m_hxtal(void);
74
75 #elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
76 uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
77 static void system_clock_72m_hxtal(void);
78
79 #elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
80 uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2;
81 static void system_clock_72m_irc8m(void);
82
83 #elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL)
84 uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_HXTAL;
85 static void system_clock_84m_hxtal(void);
86
87 #elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2)
88 uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2;
89 static void system_clock_84m_irc8m(void);
90
91 #elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
92 uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL;
93 static void system_clock_96m_hxtal(void);
94
95 #elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2)
96 uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2;
97 static void system_clock_96m_irc8m(void);
98
99 #elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
100 uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL;
101 static void system_clock_108m_hxtal(void);
102
103 #elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2)
104 uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2;
105 static void system_clock_108m_irc8m(void);
106
107 #else
108 uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M;
109 static void system_clock_8m_irc8m(void);
110 #endif /* __SYSTEM_CLOCK_8M_HXTAL */
111
112 /* configure the system clock */
113 static void system_clock_config(void);
114
121 void SystemInit (void)
122 {
123 /* enable IRC8M */
124 RCU_CTL0 |= RCU_CTL0_IRC8MEN;
125 while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
126 }
127 /* reset RCU */
128 RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
129 RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
130 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
131 #if (defined(GD32F350))
132 RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC);
133 RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2);
134 #endif /* GD32F350 */
135 RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
136 RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL);
137 RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
138 RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
139 RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
140 RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
141 RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN;
142 RCU_INT = 0x00000000U;
143 RCU_ADDINT = 0x00000000U;
144 /* configure system clock */
145 system_clock_config();
146 }
147
154 static void system_clock_config(void)
155 {
156 #ifdef __SYSTEM_CLOCK_8M_HXTAL
157 system_clock_8m_hxtal();
158 #elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
159 system_clock_72m_hxtal();
160 #elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
161 system_clock_72m_irc8m();
162 #elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL)
163 system_clock_84m_hxtal();
164 #elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2)
165 system_clock_84m_irc8m();
166 #elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
167 system_clock_96m_hxtal();
168 #elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2)
169 system_clock_96m_irc8m();
170 #elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
171 system_clock_108m_hxtal();
172 #elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2)
173 system_clock_108m_irc8m();
174 #else
175 system_clock_8m_irc8m();
176 #endif /* __SYSTEM_CLOCK_8M_HXTAL */
177 }
178
179 #ifdef __SYSTEM_CLOCK_8M_HXTAL
180
186 static void system_clock_8m_hxtal(void)
187 {
188 uint32_t timeout = 0U;
189 uint32_t stab_flag = 0U;
190
191 /* enable HXTAL */
192 RCU_CTL0 |= RCU_CTL0_HXTALEN;
193
194 /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
195 do{
196 timeout++;
197 stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
198 }
199 while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
200 /* if fail */
201 if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
202 return;
203 }
204
205 /* HXTAL is stable */
206 /* AHB = SYSCLK */
207 RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
208 /* APB2 = AHB */
209 RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
210 /* APB1 = AHB */
211 RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
212
213 /* select HXTAL as system clock */
214 RCU_CFG0 &= ~RCU_CFG0_SCS;
215 RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
216
217 /* wait until HXTAL is selected as system clock */
218 while(0U == (RCU_CFG0 & RCU_SCSS_HXTAL)){
219 }
220 }
221
222 #elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
223
229 static void system_clock_72m_hxtal(void)
230 {
231 uint32_t timeout = 0U;
232 uint32_t stab_flag = 0U;
233
234 /* enable HXTAL */
235 RCU_CTL0 |= RCU_CTL0_HXTALEN;
236
237 /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
238 do{
239 timeout++;
240 stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
241 }
242 while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
243 /* if fail */
244 if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
245 return;
246 }
247 /* HXTAL is stable */
248 /* AHB = SYSCLK */
249 RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
250 /* APB2 = AHB/2 */
251 RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
252 /* APB1 = AHB/2 */
253 RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
254
255 /* PLL = HXTAL * 9 = 72 MHz */
256 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
257 RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL9);
258
259 /* enable PLL */
260 RCU_CTL0 |= RCU_CTL0_PLLEN;
261
262 /* wait until PLL is stable */
263 while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
264 }
265
266 /* select PLL as system clock */
267 RCU_CFG0 &= ~RCU_CFG0_SCS;
268 RCU_CFG0 |= RCU_CKSYSSRC_PLL;
269
270 /* wait until PLL is selected as system clock */
271 while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
272 }
273 }
274
275
276 #elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
277
283 static void system_clock_72m_irc8m(void)
284 {
285 /* AHB = SYSCLK */
286 RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
287 /* APB2 = AHB/2 */
288 RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
289 /* APB1 = AHB/2 */
290 RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
291 /* PLL = (IRC8M/2) * 18 = 72 MHz */
292 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
293 RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);
294
295 /* enable PLL */
296 RCU_CTL0 |= RCU_CTL0_PLLEN;
297
298 /* wait until PLL is stable */
299 while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
300 }
301
302 /* select PLL as system clock */
303 RCU_CFG0 &= ~RCU_CFG0_SCS;
304 RCU_CFG0 |= RCU_CKSYSSRC_PLL;
305
306 /* wait until PLL is selected as system clock */
307 while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
308 }
309 }
310
311 #elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL)
312
318 static void system_clock_84m_hxtal(void)
319 {
320 uint32_t timeout = 0U;
321 uint32_t stab_flag = 0U;
322 /* enable HXTAL */
323 RCU_CTL0 |= RCU_CTL0_HXTALEN;
324
325 /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
326 do{
327 timeout++;
328 stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
329 }
330 while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
331 /* if fail */
332 if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
333 return;
334 }
335 /* HXTAL is stable */
336 /* AHB = SYSCLK */
337 RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
338 /* APB2 = AHB/2 */
339 RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
340 /* APB1 = AHB/2 */
341 RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
342
343 /* PLL = HXTAL /2 * 21 = 84 MHz */
344 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
345 RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5);
346 RCU_CFG1 |= RCU_PLL_PREDV2;
347 RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL21);
348
349 /* enable PLL */
350 RCU_CTL0 |= RCU_CTL0_PLLEN;
351
352 /* wait until PLL is stable */
353 while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
354 }
355
356 /* select PLL as system clock */
357 RCU_CFG0 &= ~RCU_CFG0_SCS;
358 RCU_CFG0 |= RCU_CKSYSSRC_PLL;
359
360 /* wait until PLL is selected as system clock */
361 while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
362 }
363 }
364
365 #elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2)
366
372 static void system_clock_84m_irc8m(void)
373 {
374 /* AHB = SYSCLK */
375 RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
376 /* APB2 = AHB/2 */
377 RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
378 /* APB1 = AHB/2 */
379 RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
380 /* PLL = (IRC8M/2) * 21 = 84 MHz */
381 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
382 RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL21);
383
384 /* enable PLL */
385 RCU_CTL0 |= RCU_CTL0_PLLEN;
386
387 /* wait until PLL is stable */
388 while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
389 }
390
391 /* select PLL as system clock */
392 RCU_CFG0 &= ~RCU_CFG0_SCS;
393 RCU_CFG0 |= RCU_CKSYSSRC_PLL;
394
395 /* wait until PLL is selected as system clock */
396 while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
397 }
398 }
399
400 #elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
401
407 static void system_clock_96m_hxtal(void)
408 {
409 uint32_t timeout = 0U;
410 uint32_t stab_flag = 0U;
411 /* enable HXTAL */
412 RCU_CTL0 |= RCU_CTL0_HXTALEN;
413
414 /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
415 do{
416 timeout++;
417 stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
418 }
419 while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
420 /* if fail */
421 if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
422 return;
423 }
424 /* HXTAL is stable */
425 /* AHB = SYSCLK */
426 RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
427 /* APB2 = AHB/2 */
428 RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
429 /* APB1 = AHB/2 */
430 RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
431
432 /* PLL = HXTAL /2 * 24 = 96 MHz */
433 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
434 RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5);
435 RCU_CFG1 |= RCU_PLL_PREDV2;
436 RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL24);
437
438 /* enable PLL */
439 RCU_CTL0 |= RCU_CTL0_PLLEN;
440
441 /* wait until PLL is stable */
442 while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
443 }
444
445 /* select PLL as system clock */
446 RCU_CFG0 &= ~RCU_CFG0_SCS;
447 RCU_CFG0 |= RCU_CKSYSSRC_PLL;
448
449 /* wait until PLL is selected as system clock */
450 while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
451 }
452 }
453
454 #elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2)
455
461 static void system_clock_96m_irc8m(void)
462 {
463 /* AHB = SYSCLK */
464 RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
465 /* APB2 = AHB/2 */
466 RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
467 /* APB1 = AHB/2 */
468 RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
469 /* PLL = (IRC8M/2) * 24 = 96 MHz */
470 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
471 RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL24);
472
473 /* enable PLL */
474 RCU_CTL0 |= RCU_CTL0_PLLEN;
475
476 /* wait until PLL is stable */
477 while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
478 }
479
480 /* select PLL as system clock */
481 RCU_CFG0 &= ~RCU_CFG0_SCS;
482 RCU_CFG0 |= RCU_CKSYSSRC_PLL;
483
484 /* wait until PLL is selected as system clock */
485 while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
486 }
487 }
488
489 #elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
490
496 static void system_clock_108m_hxtal(void)
497 {
498 uint32_t timeout = 0U;
499 uint32_t stab_flag = 0U;
500
501 /* enable HXTAL */
502 RCU_CTL0 |= RCU_CTL0_HXTALEN;
503
504 /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
505 do{
506 timeout++;
507 stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
508 }
509 while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
510 /* if fail */
511 if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
512 return;
513 }
514 /* HXTAL is stable */
515 /* AHB = SYSCLK */
516 RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
517 /* APB2 = AHB/2 */
518 RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
519 /* APB1 = AHB/2 */
520 RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
521
522 /* PLL = HXTAL /2 * 27 = 108 MHz */
523 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
524 RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5);
525 RCU_CFG1 |= RCU_PLL_PREDV2;
526 RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL27);
527
528 /* enable PLL */
529 RCU_CTL0 |= RCU_CTL0_PLLEN;
530
531 /* wait until PLL is stable */
532 while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
533 }
534
535 /* select PLL as system clock */
536 RCU_CFG0 &= ~RCU_CFG0_SCS;
537 RCU_CFG0 |= RCU_CKSYSSRC_PLL;
538
539 /* wait until PLL is selected as system clock */
540 while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
541 }
542 }
543
544 #elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2)
545
551 static void system_clock_108m_irc8m(void)
552 {
553 /* AHB = SYSCLK */
554 RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
555 /* APB2 = AHB/2 */
556 RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
557 /* APB1 = AHB/2 */
558 RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
559 /* PLL = (IRC8M/2) * 27 = 108 MHz */
560 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
561 RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL27);
562
563 /* enable PLL */
564 RCU_CTL0 |= RCU_CTL0_PLLEN;
565
566 /* wait until PLL is stable */
567 while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
568 }
569
570 /* select PLL as system clock */
571 RCU_CFG0 &= ~RCU_CFG0_SCS;
572 RCU_CFG0 |= RCU_CKSYSSRC_PLL;
573
574 /* wait until PLL is selected as system clock */
575 while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
576 }
577 }
578
579 #else
580
586 static void system_clock_8m_irc8m(void)
587 {
588 /* AHB = SYSCLK */
589 RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
590 /* APB2 = AHB */
591 RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
592 /* APB1 = AHB */
593 RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
594
595 /* select IRC8M as system clock */
596 RCU_CFG0 &= ~RCU_CFG0_SCS;
597 RCU_CFG0 |= RCU_CKSYSSRC_IRC8M;
598
599 /* wait until IRC8M is selected as system clock */
600 while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){
601 }
602 }
603 #endif /* __SYSTEM_CLOCK_8M_HXTAL */
604
611 void SystemCoreClockUpdate (void)
612 {
613 uint32_t sws = 0U;
614 uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
615 /* exponent of AHB clock divider */
616 const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
617
618 sws = GET_BITS(RCU_CFG0, 2, 3);
619 switch(sws){
620 /* IRC8M is selected as CK_SYS */
621 case SEL_IRC8M:
622 SystemCoreClock = IRC8M_VALUE;
623 break;
624 /* HXTAL is selected as CK_SYS */
625 case SEL_HXTAL:
626 SystemCoreClock = HXTAL_VALUE;
627 break;
628 /* PLL is selected as CK_SYS */
629 case SEL_PLL:
630 /* get the value of PLLMF[3:0] */
631 pllmf = GET_BITS(RCU_CFG0, 18, 21);
632 pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
633 pllmf5 = GET_BITS(RCU_CFG1, 31, 31);
634 /* high 16 bits */
635 if(1U == pllmf4){
636 pllmf += 17U;
637 }else{
638 pllmf += 2U;
639 }
640 if(1U == pllmf5){
641 pllmf += 31U;
642 }
643 /* PLL clock source selection, HXTAL or IRC8M/2 */
644 pllsel = GET_BITS(RCU_CFG0, 16, 16);
645 if(0U != pllsel){
646 prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U);
647 if(0U == pllpresel){
648 SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf;
649 }else{
650 SystemCoreClock = (IRC48M_VALUE / prediv) * pllmf;
651 }
652 }else{
653 SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf;
654 }
655 break;
656 /* IRC8M is selected as CK_SYS */
657 default:
658 SystemCoreClock = IRC8M_VALUE;
659 break;
660 }
661 /* calculate AHB clock frequency */
662 idx = GET_BITS(RCU_CFG0, 4, 7);
663 clk_exp = ahb_exp[idx];
664 SystemCoreClock >>= clk_exp;
665 }
RCU_APB2_CKAHB_DIV1
#define RCU_APB2_CKAHB_DIV1
Definition: gd32f3x0_rcu.h:497
RCU_APB1_CKAHB_DIV2
#define RCU_APB1_CKAHB_DIV2
Definition: gd32f3x0_rcu.h:490
RCU_PLL_MUL9
#define RCU_PLL_MUL9
Definition: gd32f3x0_rcu.h:531
RCU_SCSS_HXTAL
#define RCU_SCSS_HXTAL
Definition: gd32f3x0_rcu.h:472
RCU_CFG1_PLLMF5
#define RCU_CFG1_PLLMF5
Definition: gd32f3x0_rcu.h:190
RCU_CTL0_PLLSTB
#define RCU_CTL0_PLLSTB
Definition: gd32f3x0_rcu.h:53
RCU_CFG2_ADCPSC2
#define RCU_CFG2_ADCPSC2
Definition: gd32f3x0_rcu.h:198
RCU_INT
#define RCU_INT
Definition: gd32f3x0_rcu.h:23
RCU_SCSS_IRC8M
#define RCU_SCSS_IRC8M
Definition: gd32f3x0_rcu.h:471
RCU_CFG1_PLLPRESEL
#define RCU_CFG1_PLLPRESEL
Definition: gd32f3x0_rcu.h:189
RCU_CFG2_USBFSPSC2
#define RCU_CFG2_USBFSPSC2
Definition: gd32f3x0_rcu.h:197
RCU_PLL_MUL21
#define RCU_PLL_MUL21
Definition: gd32f3x0_rcu.h:543
RCU_CTL1_IRC28MEN
#define RCU_CTL1_IRC28MEN
Definition: gd32f3x0_rcu.h:201
RCU_PLL_MUL27
#define RCU_PLL_MUL27
Definition: gd32f3x0_rcu.h:549
SystemInit
void SystemInit(void)
setup the microcontroller system, initialize the system
Definition: system_gd32f3x0.c:121
RCU_CFG2_USART0SEL
#define RCU_CFG2_USART0SEL
Definition: gd32f3x0_rcu.h:193
RCU_CFG0_ADCPSC
#define RCU_CFG0_ADCPSC
Definition: gd32f3x0_rcu.h:61
RCU_CFG2_IRC28MDIV
#define RCU_CFG2_IRC28MDIV
Definition: gd32f3x0_rcu.h:196
SystemCoreClock
uint32_t SystemCoreClock
Definition: system_gd32f3x0.c:108
RCU_PLLSRC_IRC8M_DIV2
#define RCU_PLLSRC_IRC8M_DIV2
Definition: gd32f3x0_rcu.h:511
RCU_CFG0_APB1PSC
#define RCU_CFG0_APB1PSC
Definition: gd32f3x0_rcu.h:59
RCU_SCSS_PLL
#define RCU_SCSS_PLL
Definition: gd32f3x0_rcu.h:473
RCU_CFG0_PLLMF4
#define RCU_CFG0_PLLMF4
Definition: gd32f3x0_rcu.h:67
RCU_CTL0
#define RCU_CTL0
Definition: gd32f3x0_rcu.h:21
RCU_CFG2_ADCSEL
#define RCU_CFG2_ADCSEL
Definition: gd32f3x0_rcu.h:195
RCU_CTL1
#define RCU_CTL1
Definition: gd32f3x0_rcu.h:34
SEL_HXTAL
#define SEL_HXTAL
Definition: system_gd32f3x0.c:67
RCU_CFG1
#define RCU_CFG1
Definition: gd32f3x0_rcu.h:32
RCU_CTL0_PLLEN
#define RCU_CTL0_PLLEN
Definition: gd32f3x0_rcu.h:52
RCU_CFG0_PLLMF
#define RCU_CFG0_PLLMF
Definition: gd32f3x0_rcu.h:64
RCU_CTL0_HXTALSTB
#define RCU_CTL0_HXTALSTB
Definition: gd32f3x0_rcu.h:49
SEL_IRC8M
#define SEL_IRC8M
Definition: system_gd32f3x0.c:66
RCU_CFG0_SCS
#define RCU_CFG0_SCS
Definition: gd32f3x0_rcu.h:56
RCU_PLL_MUL18
#define RCU_PLL_MUL18
Definition: gd32f3x0_rcu.h:540
RCU_CTL0_IRC8MSTB
#define RCU_CTL0_IRC8MSTB
Definition: gd32f3x0_rcu.h:45
RCU_CTL0_IRC8MEN
#define RCU_CTL0_IRC8MEN
Definition: gd32f3x0_rcu.h:44
RCU_PLL_MUL24
#define RCU_PLL_MUL24
Definition: gd32f3x0_rcu.h:546
RCU_ADDCTL
#define RCU_ADDCTL
Definition: gd32f3x0_rcu.h:35
RCU_CKSYSSRC_IRC8M
#define RCU_CKSYSSRC_IRC8M
Definition: gd32f3x0_rcu.h:465
RCU_PLL_PREDV2
#define RCU_PLL_PREDV2
Definition: gd32f3x0_rcu.h:641
RCU_CFG0_CKOUTSEL
#define RCU_CFG0_CKOUTSEL
Definition: gd32f3x0_rcu.h:66
SEL_PLL
#define SEL_PLL
Definition: system_gd32f3x0.c:68
RCU_CFG2_CECSEL
#define RCU_CFG2_CECSEL
Definition: gd32f3x0_rcu.h:194
RCU_CFG1_PREDV
#define RCU_CFG1_PREDV
Definition: gd32f3x0_rcu.h:188
RCU_CFG0
#define RCU_CFG0
Definition: gd32f3x0_rcu.h:22
RCU_AHB_CKSYS_DIV1
#define RCU_AHB_CKSYS_DIV1
Definition: gd32f3x0_rcu.h:477
RCU_CFG2
#define RCU_CFG2
Definition: gd32f3x0_rcu.h:33
SystemCoreClockUpdate
void SystemCoreClockUpdate(void)
update the SystemCoreClock with current core clock retrieved from cpu registers
Definition: system_gd32f3x0.c:611
RCU_CFG0_USBFSPSC
#define RCU_CFG0_USBFSPSC
Definition: gd32f3x0_rcu.h:65
RCU_CTL0_CKMEN
#define RCU_CTL0_CKMEN
Definition: gd32f3x0_rcu.h:51
RCU_CFG0_APB2PSC
#define RCU_CFG0_APB2PSC
Definition: gd32f3x0_rcu.h:60
RCU_APB1_CKAHB_DIV1
#define RCU_APB1_CKAHB_DIV1
Definition: gd32f3x0_rcu.h:489
RCU_PLLSRC_HXTAL_IRC48M
#define RCU_PLLSRC_HXTAL_IRC48M
Definition: gd32f3x0_rcu.h:512
RCU_CTL0_HXTALEN
#define RCU_CTL0_HXTALEN
Definition: gd32f3x0_rcu.h:48
RCU_CFG0_PLLDV
#define RCU_CFG0_PLLDV
Definition: gd32f3x0_rcu.h:69
RCU_ADDCTL_IRC48MEN
#define RCU_ADDCTL_IRC48MEN
Definition: gd32f3x0_rcu.h:208
RCU_ADDINT
#define RCU_ADDINT
Definition: gd32f3x0_rcu.h:36
RCU_APB2_CKAHB_DIV2
#define RCU_APB2_CKAHB_DIV2
Definition: gd32f3x0_rcu.h:498
RCU_CTL0_HXTALBPS
#define RCU_CTL0_HXTALBPS
Definition: gd32f3x0_rcu.h:50
RCU_CFG0_CKOUTDIV
#define RCU_CFG0_CKOUTDIV
Definition: gd32f3x0_rcu.h:68
RCU_CFG0_PLLSEL
#define RCU_CFG0_PLLSEL
Definition: gd32f3x0_rcu.h:62
RCU_CFG0_AHBPSC
#define RCU_CFG0_AHBPSC
Definition: gd32f3x0_rcu.h:58
RCU_CKSYSSRC_HXTAL
#define RCU_CKSYSSRC_HXTAL
Definition: gd32f3x0_rcu.h:466
RCU_CKSYSSRC_PLL
#define RCU_CKSYSSRC_PLL
Definition: gd32f3x0_rcu.h:467
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_i2c.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_i2c.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12
13 #include "gd32f3x0_i2c.h"
14
15 #define I2CCLK_MAX 0x7fU
16 #define I2C_FLAG_MASK 0x0000FFFFU
24 void i2c_deinit(uint32_t i2c_periph)
25 {
26 switch(i2c_periph){
27 case I2C0:
28 /* reset I2C0 */
29 rcu_periph_reset_enable(RCU_I2C0RST);
30 rcu_periph_reset_disable(RCU_I2C0RST);
31 break;
32 case I2C1:
33 /* reset I2C1 */
34 rcu_periph_reset_enable(RCU_I2C1RST);
35 rcu_periph_reset_disable(RCU_I2C1RST);
36 break;
37 case I2C2:
38 /* reset I2C2 */
39 rcu_periph_reset_enable(RCU_I2C2RST);
40 rcu_periph_reset_disable(RCU_I2C2RST);
41 break;
42 default:
43 break;
44 }
45 }
46
58 void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
59 {
60 uint32_t pclk1,clkc,freq,risetime;
61 uint32_t temp;
62
63 pclk1 = rcu_clock_freq_get(CK_APB1);
64 /* I2C peripheral clock frequency */
65 freq = (uint32_t)(pclk1/1000000U);
66 if(freq >= I2CCLK_MAX){
67 freq = I2CCLK_MAX;
68 }
69 temp = I2C_CTL1(i2c_periph);
70 temp &= ~I2C_CTL1_I2CCLK;
71 temp |= freq;
72
73 I2C_CTL1(i2c_periph) = temp;
74
75 if(100000U >= clkspeed){
76 /* the maximum SCL rise time is 1000ns in standard mode */
77 risetime = (uint32_t)((pclk1/1000000U)+1U);
78 if(risetime >= I2CCLK_MAX){
79 I2C_RT(i2c_periph) = I2CCLK_MAX;
80 }else{
81 I2C_RT(i2c_periph) = risetime;
82 }
83 clkc = (uint32_t)(pclk1/(clkspeed*2U));
84 if(clkc < 0x04U){
85 /* the CLKC in standard mode minmum value is 4 */
86 clkc = 0x04U;
87 }
88 I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc);
89
90 }else if(400000U >= clkspeed){
91 /* the maximum SCL rise time is 300ns in fast mode */
92 I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U);
93 if(I2C_DTCY_2 == dutycyc){
94 /* I2C duty cycle is 2 */
95 clkc = (uint32_t)(pclk1/(clkspeed*3U));
96 I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
97 }else{
98 /* I2C duty cycle is 16/9 */
99 clkc = (uint32_t)(pclk1/(clkspeed*25U));
100 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
101 }
102 if(0U == (clkc & I2C_CKCFG_CLKC)){
103 /* the CLKC in fast mode minmum value is 1 */
104 clkc |= 0x0001U;
105 }
106 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
107 I2C_CKCFG(i2c_periph) |= clkc;
108 }else{
109 /* fast mode plus, the maximum SCL rise time is 120ns */
110 I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)120U)/(uint32_t)1000U)+(uint32_t)1U);
111 if(I2C_DTCY_2 == dutycyc){
112 /* I2C duty cycle is 2 */
113 clkc = (uint32_t)(pclk1/(clkspeed*3U));
114 I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
115 }else{
116 /* I2C duty cycle is 16/9 */
117 clkc = (uint32_t)(pclk1/(clkspeed*25U));
118 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
119 }
120 /* enable fast mode */
121 I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
122 I2C_CKCFG(i2c_periph) |= clkc;
123 /* enable I2C fast mode plus */
124 I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN;
125 }
126 }
127
141 void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
142 {
143 /* SMBus/I2C mode selected */
144 uint32_t ctl = 0U;
145 ctl = I2C_CTL0(i2c_periph);
146 ctl &= ~(I2C_CTL0_SMBEN);
147 ctl |= mode;
148 I2C_CTL0(i2c_periph) = ctl;
149 /* configure address */
150 I2C_SADDR0(i2c_periph) = (addformat | addr);
151 }
152
162 void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
163 {
164 if(I2C_SMBUS_HOST == type){
165 I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
166 }else{
167 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL);
168 }
169 }
170
180 void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
181 {
182 if(I2C_ACK_ENABLE == ack){
183 I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
184 }else{
185 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN);
186 }
187 }
188
198 void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
199 {
200 /* configure I2C POAP position */
201 if(I2C_ACKPOS_NEXT == pos){
202 I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
203 }else{
204 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP);
205 }
206 }
207
218 void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
219 {
220 if(I2C_TRANSMITTER == trandirection){
221 addr = addr & I2C_TRANSMITTER;
222 }else{
223 addr = addr | I2C_RECEIVER;
224 }
225 I2C_DATA(i2c_periph) = addr;
226 }
227
237 void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr)
238 {
239 if(I2C_DUADEN_ENABLE == dualaddr){
240 I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN;
241 }else{
242 I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
243 }
244 }
245
252 void i2c_enable(uint32_t i2c_periph)
253 {
254 I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN;
255 }
256
263 void i2c_disable(uint32_t i2c_periph)
264 {
265 I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN);
266 }
267
274 void i2c_start_on_bus(uint32_t i2c_periph)
275 {
276 I2C_CTL0(i2c_periph) |= I2C_CTL0_START;
277 }
278
285 void i2c_stop_on_bus(uint32_t i2c_periph)
286 {
287 I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP;
288 }
289
297 void i2c_data_transmit(uint32_t i2c_periph, uint8_t data)
298 {
299 I2C_DATA(i2c_periph) = DATA_TRANS(data);
300 }
301
308 uint8_t i2c_data_receive(uint32_t i2c_periph)
309 {
310 return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph));
311 }
312
322 void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate)
323 {
324 /* configure I2C DMA function */
325 uint32_t ctl = 0U;
326 ctl = I2C_CTL1(i2c_periph);
327 ctl &= ~(I2C_CTL1_DMAON);
328 ctl |= dmastate;
329 I2C_CTL1(i2c_periph) = ctl;
330 }
331
341 void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast)
342 {
343 /* configure DMA last transfer */
344 uint32_t ctl = 0U;
345 ctl = I2C_CTL1(i2c_periph);
346 ctl &= ~(I2C_CTL1_DMALST);
347 ctl |= dmalast;
348 I2C_CTL1(i2c_periph) = ctl;
349 }
350
360 void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
361 {
362 /* configure I2C SCL strerching enable or disable */
363 uint32_t ctl = 0U;
364 ctl = I2C_CTL0(i2c_periph);
365 ctl &= ~(I2C_CTL0_DISSTRC);
366 ctl |= stretchpara;
367 I2C_CTL0(i2c_periph) = ctl;
368 }
369
379 void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
380 {
381 /* configure slave response to a general call enable or disable */
382 uint32_t ctl = 0U;
383 ctl = I2C_CTL0(i2c_periph);
384 ctl &= ~(I2C_CTL0_GCEN);
385 ctl |= gcallpara;
386 I2C_CTL0(i2c_periph) = ctl;
387 }
388
398 void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
399 {
400 /* modify CTL0 and configure software reset I2C state */
401 uint32_t ctl = 0U;
402 ctl = I2C_CTL0(i2c_periph);
403 ctl &= ~(I2C_CTL0_SRESET);
404 ctl |= sreset;
405 I2C_CTL0(i2c_periph) = ctl;
406 }
407
436 FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag)
437 {
438 uint32_t reg = 0U;
439 FlagStatus reval = RESET;
440 /* get the flag in which register */
441 reg = (BIT(31) & flag);
442 if((BIT(31) == reg)){
443 if((I2C_STAT1(i2c_periph)&(flag & I2C_FLAG_MASK))){
444 reval = SET;
445 }else{
446 reval = RESET;
447 }
448 }else{
449 if((I2C_STAT0(i2c_periph)&(flag & I2C_FLAG_MASK))){
450 reval = SET;
451 }else{
452 reval = RESET;
453 }
454 }
455 /* return the flag status */
456 return reval;
457 }
458
474 void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag)
475 {
476 if(I2C_FLAG_ADDSEND == flag){
477 /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
478 I2C_STAT0(i2c_periph);
479 I2C_STAT1(i2c_periph);
480 }else{
481 I2C_STAT0(i2c_periph) &= ~(flag);
482 }
483 }
484
495 void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype)
496 {
497 I2C_CTL1(i2c_periph) |= (inttype);
498 }
499
510 void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype)
511 {
512 I2C_CTL1(i2c_periph) &= ~(inttype);
513 }
514
536 FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag)
537 {
538 uint32_t evie, errie, bufie;
539
540 evie = I2C_CTL1(i2c_periph)&I2C_CTL1_EVIE;
541 errie = I2C_CTL1(i2c_periph)&I2C_CTL1_ERRIE;
542 /* check I2C event interrupt enable bit */
543 if((intflag&0x00ffU) && evie){
544 if(intflag&0x001fU){
545 /* check I2C event flags except TBE and RBNE */
546 if(intflag & I2C_STAT0(i2c_periph)){
547 return SET;
548 }else{
549 return RESET;
550 }
551 }else{
552 /* check I2C event flags TBE and RBNE */
553 bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;
554 if(bufie){
555 if(intflag & I2C_STAT0(i2c_periph)){
556 return SET;
557 }else{
558 return RESET;
559 }
560 }else{
561 return RESET;
562 }
563 }
564 /* check I2C error interrupt enable bit */
565 }else if((intflag&0xff00U) && errie){
566 /* check I2C error flags */
567 if(intflag & I2C_STAT0(i2c_periph)){
568 return SET;
569 }else{
570 return RESET;
571 }
572 }else{
573 return RESET;
574 }
575 }
576
592 void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag)
593 {
594 if(I2C_INT_FLAG_ADDSEND == intflag){
595 /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
596 I2C_STAT0(i2c_periph);
597 I2C_STAT1(i2c_periph);
598 }else{
599 I2C_STAT0(i2c_periph) &= ~(intflag);
600 }
601 }
602
612 void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
613 {
614 /* on/off PEC calculation */
615 uint32_t ctl = 0U;
616 ctl = I2C_CTL0(i2c_periph);
617 ctl &= ~(I2C_CTL0_PECEN);
618 ctl |= pecstate;
619 I2C_CTL0(i2c_periph) = ctl;
620 }
621
631 void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
632 {
633 /* whether to transfer PEC */
634 uint32_t ctl = 0U;
635 ctl = I2C_CTL0(i2c_periph);
636 ctl &= ~(I2C_CTL0_PECTRANS);
637 ctl |= pecpara;
638 I2C_CTL0(i2c_periph) = ctl;
639 }
640
647 uint8_t i2c_pec_value_get(uint32_t i2c_periph)
648 {
649 return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_ECV)>>8);
650 }
651
661 void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
662 {
663 /* issue alert through SMBA pin configure*/
664 uint32_t ctl = 0U;
665 ctl = I2C_CTL0(i2c_periph);
666 ctl &= ~(I2C_CTL0_SALT);
667 ctl |= smbuspara;
668 I2C_CTL0(i2c_periph) = ctl;
669 }
670
680 void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
681 {
682 /* enable or disable I2C ARP protocol*/
683 uint32_t ctl = 0U;
684 ctl = I2C_CTL0(i2c_periph);
685 ctl &= ~(I2C_CTL0_ARPEN);
686 ctl |= arpstate;
687 I2C_CTL0(i2c_periph) = ctl;
688 }
689
RCU_I2C1RST
Definition: gd32f3x0_rcu.h:352
i2c_interrupt_flag_get
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag)
check I2C interrupt flag
Definition: gd32f3x0_i2c.c:536
CK_APB1
Definition: gd32f3x0_rcu.h:456
i2c_pec_transfer_enable
void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
I2C whether to transfer PEC value.
Definition: gd32f3x0_i2c.c:631
i2c_dualaddr_enable
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr)
dual-address mode switch
Definition: gd32f3x0_i2c.c:237
I2C_CTL0_POAP
#define I2C_CTL0_POAP
Definition: gd32f3x0_i2c.h:47
I2C_FMPCFG
#define I2C_FMPCFG(i2cx)
Definition: gd32f3x0_i2c.h:33
i2c_flag_clear
void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag)
clear I2C flag
Definition: gd32f3x0_i2c.c:474
I2C_CTL1_DMAON
#define I2C_CTL1_DMAON
Definition: gd32f3x0_i2c.h:57
I2C_CTL0_SRESET
#define I2C_CTL0_SRESET
Definition: gd32f3x0_i2c.h:50
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
I2C_SMBUS_HOST
#define I2C_SMBUS_HOST
Definition: gd32f3x0_i2c.h:117
I2C_FMPCFG_FMPEN
#define I2C_FMPCFG_FMPEN
Definition: gd32f3x0_i2c.h:108
i2c_interrupt_flag_clear
void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag)
clear I2C interrupt flag
Definition: gd32f3x0_i2c.c:592
i2c_interrupt_disable
void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype)
disable I2C interrupt
Definition: gd32f3x0_i2c.c:510
i2c_flag_get
FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag)
check I2C flag is set or not
Definition: gd32f3x0_i2c.c:436
i2c_ack_config
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
whether or not to send an ACK
Definition: gd32f3x0_i2c.c:180
i2c_ackpos_config
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
I2C POAP position configure.
Definition: gd32f3x0_i2c.c:198
I2C_SADDR1
#define I2C_SADDR1(i2cx)
Definition: gd32f3x0_i2c.h:27
I2C_CKCFG_CLKC
#define I2C_CKCFG_CLKC
Definition: gd32f3x0_i2c.h:100
I2C_CTL0_SALT
#define I2C_CTL0_SALT
Definition: gd32f3x0_i2c.h:49
I2C_CTL0_I2CEN
#define I2C_CTL0_I2CEN
Definition: gd32f3x0_i2c.h:37
I2C1
#define I2C1
Definition: gd32f3x0_i2c.h:20
I2C_CTL0_PECTRANS
#define I2C_CTL0_PECTRANS
Definition: gd32f3x0_i2c.h:48
i2c_master_addressing
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
master send slave address
Definition: gd32f3x0_i2c.c:218
i2c_data_transmit
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data)
I2C transmit data function.
Definition: gd32f3x0_i2c.c:297
I2C_CKCFG_FAST
#define I2C_CKCFG_FAST
Definition: gd32f3x0_i2c.h:102
I2C_CTL0_SMBSEL
#define I2C_CTL0_SMBSEL
Definition: gd32f3x0_i2c.h:39
I2C_DUADEN_ENABLE
#define I2C_DUADEN_ENABLE
Definition: gd32f3x0_i2c.h:133
I2C_STAT1_ECV
#define I2C_STAT1_ECV
Definition: gd32f3x0_i2c.h:97
I2C_CTL0_START
#define I2C_CTL0_START
Definition: gd32f3x0_i2c.h:44
RCU_I2C0RST
Definition: gd32f3x0_rcu.h:351
I2C_CTL0_PECEN
#define I2C_CTL0_PECEN
Definition: gd32f3x0_i2c.h:41
i2c_data_receive
uint8_t i2c_data_receive(uint32_t i2c_periph)
I2C receive data function.
Definition: gd32f3x0_i2c.c:308
i2c_enable
void i2c_enable(uint32_t i2c_periph)
enable I2C
Definition: gd32f3x0_i2c.c:252
I2C_CTL0_STOP
#define I2C_CTL0_STOP
Definition: gd32f3x0_i2c.h:45
DATA_RECV
#define DATA_RECV(regval)
Definition: gd32f3x0_i2c.h:182
i2c_software_reset_config
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
software reset I2C
Definition: gd32f3x0_i2c.c:398
I2C_ACK_ENABLE
#define I2C_ACK_ENABLE
Definition: gd32f3x0_i2c.h:125
i2c_mode_addr_config
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
configure I2C address
Definition: gd32f3x0_i2c.c:141
i2c_slave_response_to_gcall_config
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
whether or not to response to a general call
Definition: gd32f3x0_i2c.c:379
I2C_CKCFG
#define I2C_CKCFG(i2cx)
Definition: gd32f3x0_i2c.h:31
I2C_CTL0
#define I2C_CTL0(i2cx)
Definition: gd32f3x0_i2c.h:24
I2CCLK_MAX
#define I2CCLK_MAX
Definition: gd32f3x0_i2c.c:15
i2c_dma_last_transfer_enable
void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast)
flag indicating DMA last transfer
Definition: gd32f3x0_i2c.c:341
gd32f3x0_i2c.h
definitions for the I2C
I2C_CKCFG_DTCY
#define I2C_CKCFG_DTCY
Definition: gd32f3x0_i2c.h:101
I2C2
#define I2C2
Definition: gd32f3x0_i2c.h:21
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
i2c_clock_config
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
configure I2C clock
Definition: gd32f3x0_i2c.c:58
RCU_I2C2RST
Definition: gd32f3x0_rcu.h:361
I2C_RECEIVER
#define I2C_RECEIVER
Definition: gd32f3x0_i2c.h:120
I2C_CTL1_ERRIE
#define I2C_CTL1_ERRIE
Definition: gd32f3x0_i2c.h:54
I2C_CTL1_BUFIE
#define I2C_CTL1_BUFIE
Definition: gd32f3x0_i2c.h:56
i2c_dma_enable
void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate)
enable I2C DMA mode
Definition: gd32f3x0_i2c.c:322
I2C_CTL1
#define I2C_CTL1(i2cx)
Definition: gd32f3x0_i2c.h:25
I2C_INT_FLAG_ADDSEND
#define I2C_INT_FLAG_ADDSEND
Definition: gd32f3x0_i2c.h:209
I2C_CTL0_SMBEN
#define I2C_CTL0_SMBEN
Definition: gd32f3x0_i2c.h:38
i2c_smbus_type_config
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
SMBus type selection.
Definition: gd32f3x0_i2c.c:162
i2c_disable
void i2c_disable(uint32_t i2c_periph)
disable I2C
Definition: gd32f3x0_i2c.c:263
i2c_smbus_arp_enable
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
enable or disable I2C ARP protocol in SMBus switch
Definition: gd32f3x0_i2c.c:680
I2C_TRANSMITTER
#define I2C_TRANSMITTER
Definition: gd32f3x0_i2c.h:121
I2C_CTL1_EVIE
#define I2C_CTL1_EVIE
Definition: gd32f3x0_i2c.h:55
I2C_RT
#define I2C_RT(i2cx)
Definition: gd32f3x0_i2c.h:32
i2c_stretch_scl_low_config
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
whether to stretch SCL low when data is not ready in slave mode
Definition: gd32f3x0_i2c.c:360
I2C_FLAG_MASK
#define I2C_FLAG_MASK
Definition: gd32f3x0_i2c.c:16
I2C_ACKPOS_NEXT
#define I2C_ACKPOS_NEXT
Definition: gd32f3x0_i2c.h:128
I2C_STAT0
#define I2C_STAT0(i2cx)
Definition: gd32f3x0_i2c.h:29
I2C_SADDR0
#define I2C_SADDR0(i2cx)
Definition: gd32f3x0_i2c.h:26
i2c_smbus_issue_alert
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
I2C issue alert through SMBA pin.
Definition: gd32f3x0_i2c.c:661
DATA_TRANS
#define DATA_TRANS(regval)
Definition: gd32f3x0_i2c.h:179
I2C_CTL0_GCEN
#define I2C_CTL0_GCEN
Definition: gd32f3x0_i2c.h:42
I2C_SADDR1_DUADEN
#define I2C_SADDR1_DUADEN
Definition: gd32f3x0_i2c.h:67
I2C0
#define I2C0
Definition: gd32f3x0_i2c.h:19
I2C_CTL0_ACKEN
#define I2C_CTL0_ACKEN
Definition: gd32f3x0_i2c.h:46
I2C_CTL0_ARPEN
#define I2C_CTL0_ARPEN
Definition: gd32f3x0_i2c.h:40
i2c_pec_value_get
uint8_t i2c_pec_value_get(uint32_t i2c_periph)
get packet error checking value
Definition: gd32f3x0_i2c.c:647
i2c_pec_enable
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
I2C PEC calculation on or off.
Definition: gd32f3x0_i2c.c:612
i2c_stop_on_bus
void i2c_stop_on_bus(uint32_t i2c_periph)
generate a STOP condition on I2C bus
Definition: gd32f3x0_i2c.c:285
I2C_CTL1_DMALST
#define I2C_CTL1_DMALST
Definition: gd32f3x0_i2c.h:58
I2C_FLAG_ADDSEND
#define I2C_FLAG_ADDSEND
Definition: gd32f3x0_i2c.h:186
I2C_STAT1
#define I2C_STAT1(i2cx)
Definition: gd32f3x0_i2c.h:30
i2c_start_on_bus
void i2c_start_on_bus(uint32_t i2c_periph)
generate a START condition on I2C bus
Definition: gd32f3x0_i2c.c:274
I2C_DTCY_2
#define I2C_DTCY_2
Definition: gd32f3x0_i2c.h:230
I2C_DATA
#define I2C_DATA(i2cx)
Definition: gd32f3x0_i2c.h:28
rcu_clock_freq_get
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
get the system clock, bus and peripheral clock frequency
Definition: gd32f3x0_rcu.c:964
i2c_interrupt_enable
void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype)
enable I2C interrupt
Definition: gd32f3x0_i2c.c:495
I2C_CTL1_I2CCLK
#define I2C_CTL1_I2CCLK
Definition: gd32f3x0_i2c.h:53
I2C_CTL0_DISSTRC
#define I2C_CTL0_DISSTRC
Definition: gd32f3x0_i2c.h:43
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_dac.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_dac.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifdef GD32F350
13 #include "gd32f3x0_dac.h"
14
21 void dac_deinit(void)
22 {
23 rcu_periph_reset_enable(RCU_DACRST);
24 rcu_periph_reset_disable(RCU_DACRST);
25 }
26
33 void dac_enable(void)
34 {
35 DAC_CTL |= DAC_CTL_DEN;
36 }
37
44 void dac_disable(void)
45 {
46 DAC_CTL &= ~DAC_CTL_DEN;
47 }
48
55 void dac_dma_enable(void)
56 {
57 DAC_CTL |= DAC_CTL_DDMAEN;
58 }
59
66 void dac_dma_disable(void)
67 {
68 DAC_CTL &= ~DAC_CTL_DDMAEN;
69 }
70
77 void dac_output_buffer_enable(void)
78 {
79 DAC_CTL &= ~DAC_CTL_DBOFF;
80 }
81
88 void dac_output_buffer_disable(void)
89 {
90 DAC_CTL |= DAC_CTL_DBOFF;
91 }
92
99 void dac_trigger_enable(void)
100 {
101 DAC_CTL |= DAC_CTL_DTEN;
102 }
103
110 void dac_trigger_disable(void)
111 {
112 DAC_CTL &= ~DAC_CTL_DTEN;
113 }
114
121 void dac_software_trigger_enable(void)
122 {
123 DAC_SWT |= DAC_SWT_SWTR;
124 }
125
132 void dac_software_trigger_disable(void)
133 {
134 DAC_SWT &= ~DAC_SWT_SWTR;
135 }
136
143 void dac_interrupt_enable(void)
144 {
145 DAC_CTL |= DAC_CTL_DDUDRIE;
146 }
147
154 void dac_interrupt_disable(void)
155 {
156 DAC_CTL &= ~DAC_CTL_DDUDRIE;
157 }
158
171 void dac_trigger_source_config(uint32_t triggersource)
172 {
173 DAC_CTL &= ~DAC_CTL_DTSEL;
174 DAC_CTL |= triggersource;
175 }
176
186 void dac_wave_mode_config(uint32_t wave_mode)
187 {
188 DAC_CTL &= ~DAC_CTL_DWM;
189 DAC_CTL |= wave_mode;
190 }
191
210 void dac_wave_bit_width_config(uint32_t bit_width)
211 {
212 DAC_CTL &= ~DAC_CTL_DWBW;
213 DAC_CTL |= bit_width;
214 }
215
234 void dac_lfsr_noise_config(uint32_t unmask_bits)
235 {
236 DAC_CTL &= ~DAC_CTL_DWBW;
237 DAC_CTL |= unmask_bits;
238 }
239
258 void dac_triangle_noise_config(uint32_t amplitude)
259 {
260 DAC_CTL &= ~DAC_CTL_DWBW;
261 DAC_CTL |= amplitude;
262 }
263
270 uint16_t dac_output_value_get(void)
271 {
272 uint16_t data = 0U;
273 data = (uint16_t)DAC_DO;
274 return data;
275 }
276
283 FlagStatus dac_flag_get(void)
284 {
285 /* check the DMA underrun flag */
286 if((uint8_t)RESET != (DAC_STAT & DAC_STAT_DDUDR)){
287 return SET;
288 }else{
289 return RESET;
290 }
291 }
292
299 void dac_flag_clear(void)
300 {
301 DAC_STAT &= ~DAC_STAT_DDUDR;
302 }
303
310 FlagStatus dac_interrupt_flag_get(void)
311 {
312 FlagStatus temp_flag = RESET;
313 uint32_t ddudr_flag = 0U, ddudrie_flag = 0U;
314 /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */
315 ddudr_flag = DAC_STAT & DAC_STAT_DDUDR;
316 ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE;
317 if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){
318 temp_flag = SET;
319 }
320 return temp_flag;
321 }
322
329 void dac_interrupt_flag_clear(void)
330 {
331 DAC_CTL &= ~DAC_CTL_DDUDRIE;
332 }
333
344 void dac_data_set(uint32_t dac_align, uint16_t data)
345 {
346 switch(dac_align){
347 /* data right 12b alignment */
348 case DAC_ALIGN_12B_R:
349 DAC_R12DH = data;
350 break;
351 /* data left 12b alignment */
352 case DAC_ALIGN_12B_L:
353 DAC_L12DH = data;
354 break;
355 /* data right 8b alignment */
356 case DAC_ALIGN_8B_R:
357 DAC_R8DH = data;
358 break;
359 default:
360 break;
361 }
362 }
363 #endif /* GD32F350 */
rcu_periph_reset_disable
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
disable reset the peripheral
Definition: gd32f3x0_rcu.c:186
rcu_periph_reset_enable
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
reset the peripherals
Definition: gd32f3x0_rcu.c:160
gd32f3x0_dac.h
definitions for the DAC
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_fwdgt.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Source
gd32f3x0_fwdgt.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_fwdgt.h"
13
20 void fwdgt_write_disable(void)
21 {
22 FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
23 }
24
31 void fwdgt_counter_reload(void)
32 {
33 FWDGT_CTL = FWDGT_KEY_RELOAD;
34 }
35
42 void fwdgt_enable(void)
43 {
44 FWDGT_CTL = FWDGT_KEY_ENABLE;
45 }
46
53 ErrStatus fwdgt_window_value_config(uint16_t window_value)
54 {
55 uint32_t time_index = FWDGT_WND_TIMEOUT;
56 uint32_t flag_status = RESET;
57
58 /* enable write access to FWDGT_WND */
59 FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
60
61 /* wait until the WUD flag to be reset */
62 do{
63 flag_status = FWDGT_STAT & FWDGT_STAT_WUD;
64 }while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
65
66 if ((uint32_t)RESET != flag_status){
67 return ERROR;
68 }
69
70 FWDGT_WND = WND_WND(window_value);
71
72 return SUCCESS;
73 }
74
89 ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
90 {
91 uint32_t timeout = FWDGT_PSC_TIMEOUT;
92 uint32_t flag_status = RESET;
93
94 /* enable write access to FWDGT_PSC,and FWDGT_RLD */
95 FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
96
97 /* wait until the PUD flag to be reset */
98 do{
99 flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
100 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
101
102 if ((uint32_t)RESET != flag_status){
103 return ERROR;
104 }
105
106 /* configure FWDGT */
107 FWDGT_PSC = (uint32_t)prescaler_div;
108
109 timeout = FWDGT_RLD_TIMEOUT;
110 /* wait until the RUD flag to be reset */
111 do{
112 flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
113 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
114
115 if ((uint32_t)RESET != flag_status){
116 return ERROR;
117 }
118
119 FWDGT_RLD = RLD_RLD(reload_value);
120
121 /* reload the counter */
122 FWDGT_CTL = FWDGT_KEY_RELOAD;
123
124 return SUCCESS;
125 }
126
136 FlagStatus fwdgt_flag_get(uint16_t flag)
137 {
138 if(FWDGT_STAT & flag){
139 return SET;
140 }
141 return RESET;
142 }
FWDGT_KEY_ENABLE
#define FWDGT_KEY_ENABLE
Definition: gd32f3x0_fwdgt.h:69
FWDGT_RLD_TIMEOUT
#define FWDGT_RLD_TIMEOUT
Definition: gd32f3x0_fwdgt.h:74
fwdgt_write_disable
void fwdgt_write_disable(void)
disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND
Definition: gd32f3x0_fwdgt.c:20
FWDGT_WND
#define FWDGT_WND
Definition: gd32f3x0_fwdgt.h:25
FWDGT_WRITEACCESS_ENABLE
#define FWDGT_WRITEACCESS_ENABLE
Definition: gd32f3x0_fwdgt.h:66
fwdgt_counter_reload
void fwdgt_counter_reload(void)
reload the counter of FWDGT
Definition: gd32f3x0_fwdgt.c:31
FWDGT_RLD
#define FWDGT_RLD
Definition: gd32f3x0_fwdgt.h:23
FWDGT_WRITEACCESS_DISABLE
#define FWDGT_WRITEACCESS_DISABLE
Definition: gd32f3x0_fwdgt.h:67
fwdgt_window_value_config
ErrStatus fwdgt_window_value_config(uint16_t window_value)
configure the free watchdog timer counter window value
Definition: gd32f3x0_fwdgt.c:53
FWDGT_CTL
#define FWDGT_CTL
Definition: gd32f3x0_fwdgt.h:21
FWDGT_KEY_RELOAD
#define FWDGT_KEY_RELOAD
Definition: gd32f3x0_fwdgt.h:68
WND_WND
#define WND_WND(regval)
Definition: gd32f3x0_fwdgt.h:63
gd32f3x0_fwdgt.h
definitions for the FWDGT
RLD_RLD
#define RLD_RLD(regval)
Definition: gd32f3x0_fwdgt.h:60
FWDGT_STAT_WUD
#define FWDGT_STAT_WUD
Definition: gd32f3x0_fwdgt.h:40
fwdgt_flag_get
FlagStatus fwdgt_flag_get(uint16_t flag)
get flag state of FWDGT
Definition: gd32f3x0_fwdgt.c:136
FWDGT_STAT_PUD
#define FWDGT_STAT_PUD
Definition: gd32f3x0_fwdgt.h:38
FWDGT_PSC_TIMEOUT
#define FWDGT_PSC_TIMEOUT
Definition: gd32f3x0_fwdgt.h:73
FWDGT_STAT
#define FWDGT_STAT
Definition: gd32f3x0_fwdgt.h:24
fwdgt_config
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
configure counter reload value, and prescaler divider value
Definition: gd32f3x0_fwdgt.c:89
FWDGT_STAT_RUD
#define FWDGT_STAT_RUD
Definition: gd32f3x0_fwdgt.h:39
fwdgt_enable
void fwdgt_enable(void)
start the free watchdog timer counter
Definition: gd32f3x0_fwdgt.c:42
FWDGT_PSC
#define FWDGT_PSC
Definition: gd32f3x0_fwdgt.h:22
FWDGT_WND_TIMEOUT
#define FWDGT_WND_TIMEOUT
Definition: gd32f3x0_fwdgt.h:72
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Source/gd32f3x0_rtc.c Source File

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gd32f3x0_rtc.c
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1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "gd32f3x0_rtc.h"
13
20 ErrStatus rtc_deinit(void)
21 {
22 ErrStatus error_status = ERROR;
23
24 /* RTC_TAMP register is not under write protection */
25 RTC_TAMP = RTC_REGISTER_RESET;
26
27 /* disable the write protection */
28 RTC_WPK = RTC_UNLOCK_KEY1;
29 RTC_WPK = RTC_UNLOCK_KEY2;
30
31 /* reset RTC_CTL register, this can be done without the init mode */
32 RTC_CTL &= RTC_REGISTER_RESET;
33
34 /* enter init mode */
35 error_status = rtc_init_mode_enter();
36
37 if(ERROR != error_status){
38 /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition.
39 in order to read calendar from shadow register, not the real registers being reset */
40 RTC_TIME = RTC_REGISTER_RESET;
41 RTC_DATE = RTC_DATE_RESET;
42
43 RTC_PSC = RTC_PSC_RESET;
44
45 /* reset RTC_STAT register, also exit init mode.
46 at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */
47 RTC_STAT = RTC_STAT_RESET;
48
49 /* to write RTC_ALRM0SS register, ALRM0EN bit in RTC_CTL register should be reset as the condition */
50 RTC_ALRM0TD = RTC_REGISTER_RESET;
51 RTC_ALRM0SS = RTC_REGISTER_RESET;
52
53 /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */
54 RTC_SHIFTCTL = RTC_REGISTER_RESET;
55 RTC_HRFC = RTC_REGISTER_RESET;
56
57 error_status = rtc_register_sync_wait();
58 }
59
60 /* enable the write protection */
61 RTC_WPK = RTC_LOCK_KEY;
62
63 return error_status;
64 }
65
87 ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct)
88 {
89 ErrStatus error_status = ERROR;
90 uint32_t reg_time = 0x00U, reg_date = 0x00U;
91
92 reg_date = (DATE_YR(rtc_initpara_struct->rtc_year) | \
93 DATE_DOW(rtc_initpara_struct->rtc_day_of_week) | \
94 DATE_MON(rtc_initpara_struct->rtc_month) | \
95 DATE_DAY(rtc_initpara_struct->rtc_date));
96
97 reg_time = (rtc_initpara_struct->rtc_am_pm| \
98 TIME_HR(rtc_initpara_struct->rtc_hour) | \
99 TIME_MN(rtc_initpara_struct->rtc_minute) | \
100 TIME_SC(rtc_initpara_struct->rtc_second));
101
102 /* 1st: disable the write protection */
103 RTC_WPK = RTC_UNLOCK_KEY1;
104 RTC_WPK = RTC_UNLOCK_KEY2;
105
106 /* 2nd: enter init mode */
107 error_status = rtc_init_mode_enter();
108
109 if(ERROR != error_status){
110 RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->rtc_factor_asyn)| \
111 PSC_FACTOR_S(rtc_initpara_struct->rtc_factor_syn));
112
113 RTC_TIME = (uint32_t)reg_time;
114 RTC_DATE = (uint32_t)reg_date;
115
116 RTC_CTL &= (uint32_t)(~RTC_CTL_CS);
117 RTC_CTL |= rtc_initpara_struct->rtc_display_format;
118
119 /* 3rd: exit init mode */
120 rtc_init_mode_exit();
121
122 /* 4th: wait the RSYNF flag to set */
123 error_status = rtc_register_sync_wait();
124 }
125
126 /* 5th: enable the write protection */
127 RTC_WPK = RTC_LOCK_KEY;
128
129 return error_status;
130 }
131
138 ErrStatus rtc_init_mode_enter(void)
139 {
140 uint32_t time_index = RTC_INITM_TIMEOUT;
141 uint32_t flag_status = RESET;
142 ErrStatus error_status = ERROR;
143
144 /* check whether it has been in init mode */
145 if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)){
146 RTC_STAT |= RTC_STAT_INITM;
147
148 /* wait until the INITF flag to be set */
149 do{
150 flag_status = RTC_STAT & RTC_STAT_INITF;
151 }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status));
152
153 if((uint32_t)RESET != flag_status){
154 error_status = SUCCESS;
155 }
156 }else{
157 error_status = SUCCESS;
158 }
159 return error_status;
160 }
161
168 void rtc_init_mode_exit(void)
169 {
170 RTC_STAT &= (uint32_t)(~RTC_STAT_INITM);
171 }
172
180 ErrStatus rtc_register_sync_wait(void)
181 {
182 volatile uint32_t time_index = RTC_RSYNF_TIMEOUT;
183 uint32_t flag_status = RESET;
184 ErrStatus error_status = ERROR;
185
186 if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)){
187 /* disable the write protection */
188 RTC_WPK = RTC_UNLOCK_KEY1;
189 RTC_WPK = RTC_UNLOCK_KEY2;
190
191 /* firstly clear RSYNF flag */
192 RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF);
193
194 /* wait until RSYNF flag to be set */
195 do{
196 flag_status = RTC_STAT & RTC_STAT_RSYNF;
197 }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status));
198
199 if((uint32_t)RESET != flag_status){
200 error_status = SUCCESS;
201 }
202
203 /* enable the write protection */
204 RTC_WPK = RTC_LOCK_KEY;
205 }else{
206 error_status = SUCCESS;
207 }
208
209 return error_status;
210 }
211
233 void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct)
234 {
235 uint32_t temp_tr = 0x00U, temp_dr = 0x00U, temp_pscr = 0x00U, temp_ctlr = 0x00U;
236
237 temp_tr = (uint32_t)RTC_TIME;
238 temp_dr = (uint32_t)RTC_DATE;
239 temp_pscr = (uint32_t)RTC_PSC;
240 temp_ctlr = (uint32_t)RTC_CTL;
241
242 /* get current time and construct rtc_parameter_struct structure */
243 rtc_initpara_struct->rtc_year = (uint8_t)GET_DATE_YR(temp_dr);
244 rtc_initpara_struct->rtc_month = (uint8_t)GET_DATE_MON(temp_dr);
245 rtc_initpara_struct->rtc_date = (uint8_t)GET_DATE_DAY(temp_dr);
246 rtc_initpara_struct->rtc_day_of_week = (uint8_t)GET_DATE_DOW(temp_dr);
247 rtc_initpara_struct->rtc_hour = (uint8_t)GET_TIME_HR(temp_tr);
248 rtc_initpara_struct->rtc_minute = (uint8_t)GET_TIME_MN(temp_tr);
249 rtc_initpara_struct->rtc_second = (uint8_t)GET_TIME_SC(temp_tr);
250 rtc_initpara_struct->rtc_factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr);
251 rtc_initpara_struct->rtc_factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr);
252 rtc_initpara_struct->rtc_am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM);
253 rtc_initpara_struct->rtc_display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS);
254 }
255
262 uint32_t rtc_subsecond_get(void)
263 {
264 uint32_t reg = 0x00U;
265 /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */
266 reg = (uint32_t)RTC_SS;
267 /* read RTC_DATE to unlock the 3 shadow registers */
268 (void) (RTC_DATE);
269
270 return reg;
271 }
272
291 void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time)
292 {
293 uint32_t reg_alrm0td = 0x00U;
294
295 reg_alrm0td = (rtc_alarm_time->rtc_alarm_mask | \
296 rtc_alarm_time->rtc_weekday_or_date | \
297 rtc_alarm_time->rtc_am_pm | \
298 ALRM0TD_DAY(rtc_alarm_time->rtc_alarm_day) | \
299 ALRM0TD_HR(rtc_alarm_time->rtc_alarm_hour) | \
300 ALRM0TD_MN(rtc_alarm_time->rtc_alarm_minute) | \
301 ALRM0TD_SC(rtc_alarm_time->rtc_alarm_second));
302
303 /* disable the write protection */
304 RTC_WPK = RTC_UNLOCK_KEY1;
305 RTC_WPK = RTC_UNLOCK_KEY2;
306
307 RTC_ALRM0TD = (uint32_t)reg_alrm0td;
308
309 /* enable the write protection */
310 RTC_WPK = RTC_LOCK_KEY;
311 }
312
336 void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond)
337 {
338 /* disable the write protection */
339 RTC_WPK = RTC_UNLOCK_KEY1;
340 RTC_WPK = RTC_UNLOCK_KEY2;
341
342 RTC_ALRM0SS = mask_subsecond | subsecond;
343
344 /* enable the write protection */
345 RTC_WPK = RTC_LOCK_KEY;
346 }
347
354 void rtc_alarm_enable(void)
355 {
356 /* disable the write protection */
357 RTC_WPK = RTC_UNLOCK_KEY1;
358 RTC_WPK = RTC_UNLOCK_KEY2;
359
360 RTC_CTL |= RTC_CTL_ALRM0EN;
361
362 /* enable the write protection */
363 RTC_WPK = RTC_LOCK_KEY;
364 }
365
372 ErrStatus rtc_alarm_disable(void)
373 {
374 volatile uint32_t time_index = RTC_ALRM0WF_TIMEOUT;
375 ErrStatus error_status = ERROR;
376 uint32_t flag_status = RESET;
377
378 /* disable the write protection */
379 RTC_WPK = RTC_UNLOCK_KEY1;
380 RTC_WPK = RTC_UNLOCK_KEY2;
381
382 /* clear the state of alarm */
383 RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN);
384
385 /* wait until ALRM0WF flag to be set after the alarm is disabled */
386 do{
387 flag_status = RTC_STAT & RTC_STAT_ALRM0WF;
388 }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status));
389
390 if((uint32_t)RESET != flag_status){
391 error_status = SUCCESS;
392 }
393
394 /* enable the write protection */
395 RTC_WPK = RTC_LOCK_KEY;
396
397 return error_status;
398 }
399
418 void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time)
419 {
420 uint32_t reg_alrm0td = 0x00U;
421
422 /* get the value of RTC_ALRM0TD register */
423 reg_alrm0td = RTC_ALRM0TD;
424
425 /* get alarm parameters and construct the rtc_alarm_struct structure */
426 rtc_alarm_time->rtc_alarm_mask = reg_alrm0td & RTC_ALARM_ALL_MASK;
427 rtc_alarm_time->rtc_am_pm = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_PM);
428 rtc_alarm_time->rtc_weekday_or_date = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_DOWS);
429 rtc_alarm_time->rtc_alarm_day = (uint8_t)GET_ALRM0TD_DAY(reg_alrm0td);
430 rtc_alarm_time->rtc_alarm_hour = (uint8_t)GET_ALRM0TD_HR(reg_alrm0td);
431 rtc_alarm_time->rtc_alarm_minute = (uint8_t)GET_ALRM0TD_MN(reg_alrm0td);
432 rtc_alarm_time->rtc_alarm_second = (uint8_t)GET_ALRM0TD_SC(reg_alrm0td);
433 }
434
441 uint32_t rtc_alarm_subsecond_get(void)
442 {
443 return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC));
444 }
445
454 void rtc_timestamp_enable(uint32_t edge)
455 {
456 uint32_t reg_ctl = 0x00U;
457
458 /* clear the bits to be configured in RTC_CTL */
459 reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN)));
460
461 /* new configuration */
462 reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN);
463
464 /* disable the write protection */
465 RTC_WPK = RTC_UNLOCK_KEY1;
466 RTC_WPK = RTC_UNLOCK_KEY2;
467
468 RTC_CTL = (uint32_t)reg_ctl;
469
470 /* enable the write protection */
471 RTC_WPK = RTC_LOCK_KEY;
472 }
473
480 void rtc_timestamp_disable(void)
481 {
482 /* disable the write protection */
483 RTC_WPK = RTC_UNLOCK_KEY1;
484 RTC_WPK = RTC_UNLOCK_KEY2;
485
486 /* clear the TSEN bit */
487 RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN);
488
489 /* enable the write protection */
490 RTC_WPK = RTC_LOCK_KEY;
491 }
492
510 void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp)
511 {
512 uint32_t temp_tts = 0x00U, temp_dts = 0x00U;
513
514 /* get the value of time_stamp registers */
515 temp_tts = (uint32_t)RTC_TTS;
516 temp_dts = (uint32_t)RTC_DTS;
517
518 /* get timestamp time and construct the rtc_timestamp_struct structure */
519 rtc_timestamp->rtc_am_pm = (uint32_t)(temp_tts & RTC_TTS_PM);
520 rtc_timestamp->rtc_timestamp_month = (uint8_t)GET_DTS_MON(temp_dts);
521 rtc_timestamp->rtc_timestamp_date = (uint8_t)GET_DTS_DAY(temp_dts);
522 rtc_timestamp->rtc_timestamp_day = (uint8_t)GET_DTS_DOW(temp_dts);
523 rtc_timestamp->rtc_timestamp_hour = (uint8_t)GET_TTS_HR(temp_tts);
524 rtc_timestamp->rtc_timestamp_minute = (uint8_t)GET_TTS_MN(temp_tts);
525 rtc_timestamp->rtc_timestamp_second = (uint8_t)GET_TTS_SC(temp_tts);
526 }
527
534 uint32_t rtc_timestamp_subsecond_get(void)
535 {
536 return ((uint32_t)RTC_SSTS);
537 }
538
557 void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper)
558 {
559 /* disable tamper */
560 RTC_TAMP &= (uint32_t)~(rtc_tamper->rtc_tamper_source);
561
562 /* tamper filter must be used when the tamper source is voltage level detection */
563 RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT;
564
565 /* the tamper source is voltage level detection */
566 if(rtc_tamper->rtc_tamper_filter != RTC_FLT_EDGE ){
567 RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT);
568
569 /* check if the tamper pin need precharge, if need, then configure the precharge time */
570 if(DISABLE == rtc_tamper->rtc_tamper_precharge_enable){
571 RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU;
572 }else{
573 RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_precharge_time);
574 }
575
576 RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_sample_frequency);
577 RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_filter);
578 }
579
580 RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS;
581
582 if(DISABLE != rtc_tamper->rtc_tamper_with_timestamp){
583 /* the tamper event also cause a time-stamp event */
584 RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS;
585 }
586
587 /* configure the tamper trigger */
588 RTC_TAMP &= ((uint32_t)~((rtc_tamper->rtc_tamper_source) << RTC_TAMPER_TRIGGER_POS));
589 if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->rtc_tamper_trigger){
590 RTC_TAMP |= (uint32_t)((rtc_tamper->rtc_tamper_source)<< RTC_TAMPER_TRIGGER_POS);
591 }
592 /* enable tamper */
593 RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_source);
594 }
595
604 void rtc_tamper_disable(uint32_t source)
605 {
606 /* disable tamper */
607 RTC_TAMP &= (uint32_t)~source;
608
609 }
610
620 void rtc_interrupt_enable(uint32_t interrupt)
621 {
622 /* disable the write protection */
623 RTC_WPK = RTC_UNLOCK_KEY1;
624 RTC_WPK = RTC_UNLOCK_KEY2;
625
626 /* enable the interrupts in RTC_CTL register */
627 RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE);
628 /* enable the interrupts in RTC_TAMP register */
629 RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE);
630
631 /* enable the write protection */
632 RTC_WPK = RTC_LOCK_KEY;
633 }
634
644 void rtc_interrupt_disable(uint32_t interrupt)
645 {
646 /* disable the write protection */
647 RTC_WPK = RTC_UNLOCK_KEY1;
648 RTC_WPK = RTC_UNLOCK_KEY2;
649
650 /* disable the interrupts in RTC_CTL register */
651 RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE);
652 /* disable the interrupts in RTC_TAMP register */
653 RTC_TAMP &= (uint32_t)~(interrupt & RTC_TAMP_TPIE);
654
655 /* enable the write protection */
656 RTC_WPK = RTC_LOCK_KEY;
657 }
658
676 FlagStatus rtc_flag_get(uint32_t flag)
677 {
678 FlagStatus flag_state = RESET;
679
680 if((uint32_t)RESET != (RTC_STAT & flag)){
681 flag_state = SET;
682 }
683 return flag_state;
684 }
685
698 void rtc_flag_clear(uint32_t flag)
699 {
700 RTC_STAT &= (uint32_t)(~flag);
701 }
702
718 void rtc_alter_output_config(uint32_t source, uint32_t mode)
719 {
720 /* disable the write protection */
721 RTC_WPK = RTC_UNLOCK_KEY1;
722 RTC_WPK = RTC_UNLOCK_KEY2;
723
724 RTC_CTL &= (uint32_t)~(RTC_CTL_COEN | RTC_CTL_OS | RTC_CTL_OPOL | RTC_CTL_COS);
725
726 RTC_CTL |= (uint32_t)(source);
727
728 /* alarm output */
729 if((uint32_t)RESET != (source & RTC_OS_ENABLE)){
730 RTC_TAMP &= (uint32_t)~(RTC_TAMP_PC13VAL);
731 RTC_TAMP |= (uint32_t)(mode);
732 }
733
734 /* enable the write protection */
735 RTC_WPK = RTC_LOCK_KEY;
736 }
737
746 void rtc_hour_adjust(uint32_t operation)
747 {
748 /* disable the write protection */
749 RTC_WPK = RTC_UNLOCK_KEY1;
750 RTC_WPK = RTC_UNLOCK_KEY2;
751
752 RTC_CTL |= (uint32_t)(operation);
753
754 /* enable the write protection */
755 RTC_WPK = RTC_LOCK_KEY;
756 }
757
764 void rtc_bypass_shadow_enable(void)
765 {
766 /* disable the write protection */
767 RTC_WPK = RTC_UNLOCK_KEY1;
768 RTC_WPK = RTC_UNLOCK_KEY2;
769
770 RTC_CTL |= (uint8_t)RTC_CTL_BPSHAD;
771
772 /* enable the write protection */
773 RTC_WPK = RTC_LOCK_KEY;
774 }
775
782 void rtc_bypass_shadow_disable(void)
783 {
784 /* disable the write protection */
785 RTC_WPK = RTC_UNLOCK_KEY1;
786 RTC_WPK = RTC_UNLOCK_KEY2;
787
788 RTC_CTL &= (uint8_t)~RTC_CTL_BPSHAD;
789
790 /* enable the write protection */
791 RTC_WPK = RTC_LOCK_KEY;
792 }
793
800 ErrStatus rtc_refclock_detection_enable(void)
801 {
802 ErrStatus error_status = ERROR;
803
804 /* disable the write protection */
805 RTC_WPK = RTC_UNLOCK_KEY1;
806 RTC_WPK = RTC_UNLOCK_KEY2;
807
808 /* enter init mode */
809 error_status = rtc_init_mode_enter();
810
811 if(ERROR != error_status){
812 RTC_CTL |= (uint32_t)RTC_CTL_REFEN;
813 /* exit init mode */
814 rtc_init_mode_exit();
815 }
816
817 /* enable the write protection */
818 RTC_WPK = RTC_LOCK_KEY;
819
820 return error_status;
821 }
822
829 ErrStatus rtc_refclock_detection_disable(void)
830 {
831 ErrStatus error_status = ERROR;
832
833 /* disable the write protection */
834 RTC_WPK = RTC_UNLOCK_KEY1;
835 RTC_WPK = RTC_UNLOCK_KEY2;
836
837 /* enter init mode */
838 error_status = rtc_init_mode_enter();
839
840 if(ERROR != error_status){
841 RTC_CTL &= (uint32_t)~RTC_CTL_REFEN;
842 /* exit init mode */
843 rtc_init_mode_exit();
844 }
845
846 /* enable the write protection */
847 RTC_WPK = RTC_LOCK_KEY;
848
849 return error_status;
850 }
851
861 ErrStatus rtc_second_ajust(uint32_t add, uint32_t minus)
862 {
863 uint32_t time_index = RTC_SHIFTCTL_TIMEOUT;
864 ErrStatus error_status = ERROR;
865 uint32_t flag_status = RESET;
866 uint32_t temp=0U;
867
868 /* disable the write protection */
869 RTC_WPK = RTC_UNLOCK_KEY1;
870 RTC_WPK = RTC_UNLOCK_KEY2;
871
872 /* check if a shift operation is ongoing */
873 do{
874 flag_status = RTC_STAT & RTC_STAT_SOPF;
875 }while((--time_index > 0x00U) && ((uint32_t)RESET != flag_status));
876
877 temp = RTC_CTL & RTC_CTL_REFEN;
878 /* check if the function of reference clock detection is disabled */
879 if(((uint32_t)RESET == flag_status) && (RESET == temp)){
880 RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus));
881 error_status = rtc_register_sync_wait();
882 }
883
884 /* enable the write protection */
885 RTC_WPK = RTC_LOCK_KEY;
886
887 return error_status;
888 }
889
903 ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus)
904 {
905 uint32_t time_index = RTC_HRFC_TIMEOUT;
906 ErrStatus error_status = ERROR;
907 uint32_t flag_status = RESET;
908
909 /* disable the write protection */
910 RTC_WPK = RTC_UNLOCK_KEY1;
911 RTC_WPK = RTC_UNLOCK_KEY2;
912
913 /* check if a calibration operation is ongoing */
914 do{
915 flag_status = RTC_STAT & RTC_STAT_SCPF;
916 }while((--time_index > 0x00U) && ((uint32_t)RESET != flag_status));
917
918 if((uint32_t)RESET == flag_status){
919 RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus));
920 error_status = SUCCESS;
921 }
922
923 /* enable the write protection */
924 RTC_WPK = RTC_LOCK_KEY;
925
926 return error_status;
927 }
GET_ALRM0TD_SC
#define GET_ALRM0TD_SC(regval)
Definition: gd32f3x0_rtc.h:307
RTC_TIME
#define RTC_TIME
Definition: gd32f3x0_rtc.h:21
PSC_FACTOR_S
#define PSC_FACTOR_S(regval)
Definition: gd32f3x0_rtc.h:299
rtc_alarm_struct::rtc_alarm_hour
uint8_t rtc_alarm_hour
Definition: gd32f3x0_rtc.h:207
RTC_CTL_ALRM0EN
#define RTC_CTL_ALRM0EN
Definition: gd32f3x0_rtc.h:66
SHIFTCTL_SFS
#define SHIFTCTL_SFS(regval)
Definition: gd32f3x0_rtc.h:335
RTC_ALRM0TD_PM
#define RTC_ALRM0TD_PM
Definition: gd32f3x0_rtc.h:105
rtc_parameter_struct::rtc_minute
uint8_t rtc_minute
Definition: gd32f3x0_rtc.h:193
RTC_SHIFTCTL
#define RTC_SHIFTCTL
Definition: gd32f3x0_rtc.h:29
GET_DTS_DAY
#define GET_DTS_DAY(regval)
Definition: gd32f3x0_rtc.h:352
ALRM0TD_HR
#define ALRM0TD_HR(regval)
Definition: gd32f3x0_rtc.h:312
RTC_STAT_ALRM0WF
#define RTC_STAT_ALRM0WF
Definition: gd32f3x0_rtc.h:79
GET_ALRM0TD_MN
#define GET_ALRM0TD_MN(regval)
Definition: gd32f3x0_rtc.h:310
RTC_TIME_PM
#define RTC_TIME_PM
Definition: gd32f3x0_rtc.h:50
GET_TTS_SC
#define GET_TTS_SC(regval)
Definition: gd32f3x0_rtc.h:342
rtc_alarm_struct::rtc_alarm_mask
uint32_t rtc_alarm_mask
Definition: gd32f3x0_rtc.h:204
RTC_CTL_CS
#define RTC_CTL_CS
Definition: gd32f3x0_rtc.h:65
RTC_REGISTER_RESET
#define RTC_REGISTER_RESET
Definition: gd32f3x0_rtc.h:441
rtc_hour_adjust
void rtc_hour_adjust(uint32_t operation)
ajust the daylight saving time by adding or substracting one hour from the current time ...
Definition: gd32f3x0_rtc.c:746
RTC_PSC_RESET
#define RTC_PSC_RESET
Definition: gd32f3x0_rtc.h:444
RTC_ALRM0TD_DOWS
#define RTC_ALRM0TD_DOWS
Definition: gd32f3x0_rtc.h:109
rtc_alarm_disable
ErrStatus rtc_alarm_disable(void)
disable RTC alarm
Definition: gd32f3x0_rtc.c:372
RTC_HRFC_TIMEOUT
#define RTC_HRFC_TIMEOUT
Definition: gd32f3x0_rtc.h:449
RTC_STAT_RESET
#define RTC_STAT_RESET
Definition: gd32f3x0_rtc.h:443
RTC_CTL_COEN
#define RTC_CTL_COEN
Definition: gd32f3x0_rtc.h:76
RTC_CTL_OPOL
#define RTC_CTL_OPOL
Definition: gd32f3x0_rtc.h:74
RTC_TAMP_TPIE
#define RTC_TAMP_TPIE
Definition: gd32f3x0_rtc.h:150
rtc_parameter_struct::rtc_year
uint8_t rtc_year
Definition: gd32f3x0_rtc.h:188
rtc_timestamp_struct::rtc_timestamp_second
uint8_t rtc_timestamp_second
Definition: gd32f3x0_rtc.h:221
RTC_CTL_TSEG
#define RTC_CTL_TSEG
Definition: gd32f3x0_rtc.h:62
rtc_timestamp_struct::rtc_timestamp_date
uint8_t rtc_timestamp_date
Definition: gd32f3x0_rtc.h:217
ALRM0TD_MN
#define ALRM0TD_MN(regval)
Definition: gd32f3x0_rtc.h:309
RTC_WPK
#define RTC_WPK
Definition: gd32f3x0_rtc.h:27
rtc_tamper_enable
void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper)
enable RTC tamper
Definition: gd32f3x0_rtc.c:557
rtc_tamper_struct::rtc_tamper_sample_frequency
uint32_t rtc_tamper_sample_frequency
Definition: gd32f3x0_rtc.h:231
RTC_TTS_PM
#define RTC_TTS_PM
Definition: gd32f3x0_rtc.h:129
rtc_init
ErrStatus rtc_init(rtc_parameter_struct *rtc_initpara_struct)
initialize RTC registers
Definition: gd32f3x0_rtc.c:87
RTC_INITM_TIMEOUT
#define RTC_INITM_TIMEOUT
Definition: gd32f3x0_rtc.h:447
rtc_parameter_struct::rtc_am_pm
uint32_t rtc_am_pm
Definition: gd32f3x0_rtc.h:197
rtc_tamper_struct::rtc_tamper_with_timestamp
ControlStatus rtc_tamper_with_timestamp
Definition: gd32f3x0_rtc.h:234
RTC_SHIFTCTL_TIMEOUT
#define RTC_SHIFTCTL_TIMEOUT
Definition: gd32f3x0_rtc.h:450
RTC_UNLOCK_KEY1
#define RTC_UNLOCK_KEY1
Definition: gd32f3x0_rtc.h:436
rtc_alarm_enable
void rtc_alarm_enable(void)
enable RTC alarm
Definition: gd32f3x0_rtc.c:354
rtc_bypass_shadow_disable
void rtc_bypass_shadow_disable(void)
disable RTC bypass shadow registers function
Definition: gd32f3x0_rtc.c:782
RTC_STAT_SOPF
#define RTC_STAT_SOPF
Definition: gd32f3x0_rtc.h:80
GET_TTS_MN
#define GET_TTS_MN(regval)
Definition: gd32f3x0_rtc.h:345
TIME_HR
#define TIME_HR(regval)
Definition: gd32f3x0_rtc.h:244
RTC_TAMP
#define RTC_TAMP
Definition: gd32f3x0_rtc.h:34
DATE_DOW
#define DATE_DOW(regval)
Definition: gd32f3x0_rtc.h:269
rtc_parameter_struct::rtc_display_format
uint32_t rtc_display_format
Definition: gd32f3x0_rtc.h:198
rtc_alarm_config
void rtc_alarm_config(rtc_alarm_struct *rtc_alarm_time)
configure RTC alarm
Definition: gd32f3x0_rtc.c:291
RTC_PSC
#define RTC_PSC
Definition: gd32f3x0_rtc.h:25
rtc_interrupt_enable
void rtc_interrupt_enable(uint32_t interrupt)
enable specified RTC interrupt
Definition: gd32f3x0_rtc.c:620
rtc_timestamp_struct::rtc_am_pm
uint32_t rtc_am_pm
Definition: gd32f3x0_rtc.h:222
rtc_parameter_struct::rtc_date
uint8_t rtc_date
Definition: gd32f3x0_rtc.h:190
GET_TIME_HR
#define GET_TIME_HR(regval)
Definition: gd32f3x0_rtc.h:245
RTC_CTL_TSEN
#define RTC_CTL_TSEN
Definition: gd32f3x0_rtc.h:67
PSC_FACTOR_A
#define PSC_FACTOR_A(regval)
Definition: gd32f3x0_rtc.h:302
rtc_alarm_struct::rtc_alarm_day
uint8_t rtc_alarm_day
Definition: gd32f3x0_rtc.h:206
rtc_refclock_detection_enable
ErrStatus rtc_refclock_detection_enable(void)
enable RTC reference clock detection function
Definition: gd32f3x0_rtc.c:800
rtc_alarm_get
void rtc_alarm_get(rtc_alarm_struct *rtc_alarm_time)
get RTC alarm
Definition: gd32f3x0_rtc.c:418
rtc_timestamp_struct::rtc_timestamp_day
uint8_t rtc_timestamp_day
Definition: gd32f3x0_rtc.h:218
GET_DATE_DOW
#define GET_DATE_DOW(regval)
Definition: gd32f3x0_rtc.h:270
RTC_ALRM0SS
#define RTC_ALRM0SS
Definition: gd32f3x0_rtc.h:35
rtc_parameter_struct::rtc_hour
uint8_t rtc_hour
Definition: gd32f3x0_rtc.h:192
RTC_ALRM0TD
#define RTC_ALRM0TD
Definition: gd32f3x0_rtc.h:26
rtc_calibration_config
ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus)
configure RTC calibration register
Definition: gd32f3x0_rtc.c:903
rtc_flag_get
FlagStatus rtc_flag_get(uint32_t flag)
check specified flag
Definition: gd32f3x0_rtc.c:676
RTC_CTL_BPSHAD
#define RTC_CTL_BPSHAD
Definition: gd32f3x0_rtc.h:64
GET_PSC_FACTOR_S
#define GET_PSC_FACTOR_S(regval)
Definition: gd32f3x0_rtc.h:300
rtc_parameter_struct::rtc_second
uint8_t rtc_second
Definition: gd32f3x0_rtc.h:194
RTC_DTS
#define RTC_DTS
Definition: gd32f3x0_rtc.h:31
RTC_HRFC
#define RTC_HRFC
Definition: gd32f3x0_rtc.h:33
rtc_interrupt_disable
void rtc_interrupt_disable(uint32_t interrupt)
disble specified RTC interrupt
Definition: gd32f3x0_rtc.c:644
rtc_timestamp_disable
void rtc_timestamp_disable(void)
disable RTC time-stamp
Definition: gd32f3x0_rtc.c:480
GET_DATE_YR
#define GET_DATE_YR(regval)
Definition: gd32f3x0_rtc.h:280
rtc_parameter_struct::rtc_day_of_week
uint8_t rtc_day_of_week
Definition: gd32f3x0_rtc.h:191
DATE_DAY
#define DATE_DAY(regval)
Definition: gd32f3x0_rtc.h:251
TIME_SC
#define TIME_SC(regval)
Definition: gd32f3x0_rtc.h:238
DATE_MON
#define DATE_MON(regval)
Definition: gd32f3x0_rtc.h:254
ALRM0TD_DAY
#define ALRM0TD_DAY(regval)
Definition: gd32f3x0_rtc.h:315
RTC_CTL_OS
#define RTC_CTL_OS
Definition: gd32f3x0_rtc.h:75
RTC_STAT_SCPF
#define RTC_STAT_SCPF
Definition: gd32f3x0_rtc.h:90
RTC_TAMP_PC13VAL
#define RTC_TAMP_PC13VAL
Definition: gd32f3x0_rtc.h:158
RTC_TAMPER_TRIGGER_POS
#define RTC_TAMPER_TRIGGER_POS
Definition: gd32f3x0_rtc.h:404
RTC_TAMP_TPTS
#define RTC_TAMP_TPTS
Definition: gd32f3x0_rtc.h:153
rtc_init_mode_exit
void rtc_init_mode_exit(void)
exit RTC init mode
Definition: gd32f3x0_rtc.c:168
rtc_refclock_detection_disable
ErrStatus rtc_refclock_detection_disable(void)
disable RTC reference clock detection function
Definition: gd32f3x0_rtc.c:829
rtc_parameter_struct::rtc_factor_asyn
uint16_t rtc_factor_asyn
Definition: gd32f3x0_rtc.h:195
GET_TTS_HR
#define GET_TTS_HR(regval)
Definition: gd32f3x0_rtc.h:348
ALRM0TD_SC
#define ALRM0TD_SC(regval)
Definition: gd32f3x0_rtc.h:306
RTC_SS
#define RTC_SS
Definition: gd32f3x0_rtc.h:28
rtc_alarm_subsecond_get
uint32_t rtc_alarm_subsecond_get(void)
get RTC alarm subsecond
Definition: gd32f3x0_rtc.c:441
RTC_TAMP_FLT
#define RTC_TAMP_FLT
Definition: gd32f3x0_rtc.h:155
RTC_DATE_RESET
#define RTC_DATE_RESET
Definition: gd32f3x0_rtc.h:442
rtc_parameter_struct
Definition: gd32f3x0_rtc.h:186
rtc_tamper_disable
void rtc_tamper_disable(uint32_t source)
disable RTC tamper
Definition: gd32f3x0_rtc.c:604
rtc_alarm_struct::rtc_alarm_minute
uint8_t rtc_alarm_minute
Definition: gd32f3x0_rtc.h:208
RTC_DATE
#define RTC_DATE
Definition: gd32f3x0_rtc.h:22
RTC_TAMP_DISPU
#define RTC_TAMP_DISPU
Definition: gd32f3x0_rtc.h:157
RTC_SSTS
#define RTC_SSTS
Definition: gd32f3x0_rtc.h:32
RTC_OS_ENABLE
#define RTC_OS_ENABLE
Definition: gd32f3x0_rtc.h:285
RTC_CTL_REFEN
#define RTC_CTL_REFEN
Definition: gd32f3x0_rtc.h:63
HRFC_CMSK
#define HRFC_CMSK(regval)
Definition: gd32f3x0_rtc.h:364
DATE_YR
#define DATE_YR(regval)
Definition: gd32f3x0_rtc.h:279
rtc_tamper_struct::rtc_tamper_trigger
uint32_t rtc_tamper_trigger
Definition: gd32f3x0_rtc.h:229
rtc_init_mode_enter
ErrStatus rtc_init_mode_enter(void)
enter RTC init mode
Definition: gd32f3x0_rtc.c:138
rtc_timestamp_struct
Definition: gd32f3x0_rtc.h:214
rtc_tamper_struct::rtc_tamper_source
uint32_t rtc_tamper_source
Definition: gd32f3x0_rtc.h:228
GET_PSC_FACTOR_A
#define GET_PSC_FACTOR_A(regval)
Definition: gd32f3x0_rtc.h:303
rtc_timestamp_struct::rtc_timestamp_minute
uint8_t rtc_timestamp_minute
Definition: gd32f3x0_rtc.h:220
rtc_alarm_struct::rtc_weekday_or_date
uint32_t rtc_weekday_or_date
Definition: gd32f3x0_rtc.h:205
RTC_TAMP_FREQ
#define RTC_TAMP_FREQ
Definition: gd32f3x0_rtc.h:154
RTC_TTS
#define RTC_TTS
Definition: gd32f3x0_rtc.h:30
GET_TIME_MN
#define GET_TIME_MN(regval)
Definition: gd32f3x0_rtc.h:242
RTC_STAT_INITM
#define RTC_STAT_INITM
Definition: gd32f3x0_rtc.h:84
GET_ALRM0TD_DAY
#define GET_ALRM0TD_DAY(regval)
Definition: gd32f3x0_rtc.h:316
RTC_ALARM_ALL_MASK
#define RTC_ALARM_ALL_MASK
Definition: gd32f3x0_rtc.h:323
RTC_ALRM0SS_SSC
#define RTC_ALRM0SS_SSC
Definition: gd32f3x0_rtc.h:166
rtc_tamper_struct::rtc_tamper_precharge_enable
ControlStatus rtc_tamper_precharge_enable
Definition: gd32f3x0_rtc.h:232
RTC_CTL
#define RTC_CTL
Definition: gd32f3x0_rtc.h:23
rtc_second_ajust
ErrStatus rtc_second_ajust(uint32_t add, uint32_t minus)
ajust RTC second or subsecond value of current time
Definition: gd32f3x0_rtc.c:861
GET_DTS_MON
#define GET_DTS_MON(regval)
Definition: gd32f3x0_rtc.h:355
RTC_RSYNF_TIMEOUT
#define RTC_RSYNF_TIMEOUT
Definition: gd32f3x0_rtc.h:448
GET_DATE_MON
#define GET_DATE_MON(regval)
Definition: gd32f3x0_rtc.h:255
rtc_alarm_struct::rtc_alarm_second
uint8_t rtc_alarm_second
Definition: gd32f3x0_rtc.h:209
rtc_flag_clear
void rtc_flag_clear(uint32_t flag)
clear specified flag
Definition: gd32f3x0_rtc.c:698
rtc_alarm_struct::rtc_am_pm
uint32_t rtc_am_pm
Definition: gd32f3x0_rtc.h:210
RTC_STAT
#define RTC_STAT
Definition: gd32f3x0_rtc.h:24
rtc_register_sync_wait
ErrStatus rtc_register_sync_wait(void)
wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers ...
Definition: gd32f3x0_rtc.c:180
rtc_timestamp_subsecond_get
uint32_t rtc_timestamp_subsecond_get(void)
get RTC time-stamp subsecond
Definition: gd32f3x0_rtc.c:534
GET_ALRM0TD_HR
#define GET_ALRM0TD_HR(regval)
Definition: gd32f3x0_rtc.h:313
rtc_timestamp_struct::rtc_timestamp_month
uint8_t rtc_timestamp_month
Definition: gd32f3x0_rtc.h:216
RTC_STAT_INITF
#define RTC_STAT_INITF
Definition: gd32f3x0_rtc.h:83
rtc_tamper_struct::rtc_tamper_precharge_time
uint32_t rtc_tamper_precharge_time
Definition: gd32f3x0_rtc.h:233
RTC_TAMPER_TRIGGER_EDGE_RISING
#define RTC_TAMPER_TRIGGER_EDGE_RISING
Definition: gd32f3x0_rtc.h:399
rtc_deinit
ErrStatus rtc_deinit(void)
reset most of the RTC registers
Definition: gd32f3x0_rtc.c:20
gd32f3x0_rtc.h
definitions for the RTC
RTC_STAT_RSYNF
#define RTC_STAT_RSYNF
Definition: gd32f3x0_rtc.h:82
rtc_alarm_struct
Definition: gd32f3x0_rtc.h:202
rtc_timestamp_enable
void rtc_timestamp_enable(uint32_t edge)
enable RTC time-stamp
Definition: gd32f3x0_rtc.c:454
rtc_parameter_struct::rtc_factor_syn
uint16_t rtc_factor_syn
Definition: gd32f3x0_rtc.h:196
rtc_tamper_struct
Definition: gd32f3x0_rtc.h:226
GET_TIME_SC
#define GET_TIME_SC(regval)
Definition: gd32f3x0_rtc.h:239
rtc_parameter_struct::rtc_month
uint8_t rtc_month
Definition: gd32f3x0_rtc.h:189
rtc_bypass_shadow_enable
void rtc_bypass_shadow_enable(void)
enable RTC bypass shadow registers function
Definition: gd32f3x0_rtc.c:764
rtc_subsecond_get
uint32_t rtc_subsecond_get(void)
get current subsecond value
Definition: gd32f3x0_rtc.c:262
rtc_timestamp_get
void rtc_timestamp_get(rtc_timestamp_struct *rtc_timestamp)
get RTC timestamp time and date
Definition: gd32f3x0_rtc.c:510
RTC_FLT_EDGE
#define RTC_FLT_EDGE
Definition: gd32f3x0_rtc.h:385
RTC_ALRM0WF_TIMEOUT
#define RTC_ALRM0WF_TIMEOUT
Definition: gd32f3x0_rtc.h:451
RTC_UNLOCK_KEY2
#define RTC_UNLOCK_KEY2
Definition: gd32f3x0_rtc.h:437
rtc_timestamp_struct::rtc_timestamp_hour
uint8_t rtc_timestamp_hour
Definition: gd32f3x0_rtc.h:219
rtc_alter_output_config
void rtc_alter_output_config(uint32_t source, uint32_t mode)
configure rtc alternate output source
Definition: gd32f3x0_rtc.c:718
GET_DTS_DOW
#define GET_DTS_DOW(regval)
Definition: gd32f3x0_rtc.h:358
rtc_tamper_struct::rtc_tamper_filter
uint32_t rtc_tamper_filter
Definition: gd32f3x0_rtc.h:230
RTC_CTL_COS
#define RTC_CTL_COS
Definition: gd32f3x0_rtc.h:73
RTC_LOCK_KEY
#define RTC_LOCK_KEY
Definition: gd32f3x0_rtc.h:438
RTC_TAMP_PRCH
#define RTC_TAMP_PRCH
Definition: gd32f3x0_rtc.h:156
TIME_MN
#define TIME_MN(regval)
Definition: gd32f3x0_rtc.h:241
GET_DATE_DAY
#define GET_DATE_DAY(regval)
Definition: gd32f3x0_rtc.h:252
rtc_current_time_get
void rtc_current_time_get(rtc_parameter_struct *rtc_initpara_struct)
get current time and date
Definition: gd32f3x0_rtc.c:233
rtc_alarm_subsecond_config
void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond)
configure subsecond of RTC alarm
Definition: gd32f3x0_rtc.c:336
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usb_core.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
usb_core.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "usb_core.h"
13
14 static void usb_commonint_enable (usb_core_handle_struct *pudev);
15 static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev);
16
23 static void usb_commonint_enable (usb_core_handle_struct *pudev)
24 {
25 #ifndef USE_OTG_MODE
26
27 /* clear any pending USB interrupts */
28 USB_GOTGINTF = 0xFFFFFFFFU;
29
30 #endif /* USE_OTG_MODE */
31
32 /* enable the usb wakeup and suspend interrupts */
33 USB_GINTEN = GINTEN_WKUPIE | GINTEN_SPIE;
34
35 #ifdef USE_OTG_MODE
36
37 /* enable the OTG interrupts, session interrrupts and connector ID pin interrupt */
38 USB_GINTEN |= GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE;
39
40 #endif /* USE_OTG_MODE */
41 }
42
49 static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev)
50 {
51 uint32_t count = 0U;
52
53 /* enable core soft reset */
54 USB_GRSTCTL |= GRSTCTL_CSRST;
55
56 /* wait for the core to be soft reset */
57 do {
58 if (++count > 200000U) {
59 break;
60 }
61 } while (1U == (USB_GRSTCTL & GRSTCTL_CSRST));
62
63 /* wait for addtional 3 PHY clocks */
64 if (NULL != pudev->udelay) {
65 pudev->udelay(3U);
66 }
67
68 return USB_OK;
69 }
70
79 usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len)
80 {
81 uint32_t count32b = 0U, i = 0U;
82 __IO uint32_t *fifo = USB_FIFO(chep_num);
83
84 count32b = (len + 3U) / 4U;
85
86 for (i = 0U; i < count32b; i++) {
87 *fifo = *((__packed uint32_t *)src);
88
89 src += 4U;
90 }
91
92 return USB_OK;
93 }
94
102 void *usb_fifo_read (uint8_t *dest, uint16_t len)
103 {
104 uint32_t i = 0U;
105 uint32_t count32b = (len + 3U) / 4U;
106
107 __IO uint32_t *fifo = USB_FIFO(0U);
108
109 for (i = 0U; i < count32b; i++) {
110 *(__packed uint32_t *)dest = *fifo;
111
112 dest += 4U;
113 }
114
115 return ((void *)dest);
116 }
117
125 usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id)
126 {
127 /* at startup the core is in FS mode */
128 pudev->cfg.core_speed = USB_CORE_SPEED_FULL;
129 pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE;
130
131 /* initialize the core parameters */
132 if (USB_FS_CORE_ID == core_id) {
133
134 pudev->cfg.core_id = USB_FS_CORE_ID;
135
136 /* set the host channel numbers */
137 pudev->cfg.host_channel_num = USBFS_MAX_HOST_CHANNELCOUNT;
138
139 /* set the device endpoint numbers */
140 pudev->cfg.dev_endp_num = USBFS_MAX_DEV_EPCOUNT;
141
142 /* fifo size is in terms of DWORD */
143 pudev->cfg.max_fifo_size = USBFS_MAX_FIFO_WORDLEN;
144
145 /* OTG_FS core use embedded physical layer */
146 pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY;
147
148 #ifdef USBFS_SOF_OUTPUT_ENABLED
149 pudev->cfg.sof_output = 1U;
150 #endif /* USBFS_SOF_OUTPUT_ENABLED */
151
152 #ifdef USBFS_LOW_PWR_MGMT_SUPPORT
153 pudev->cfg.low_power = 1U;
154 #endif /* USBFS_LOW_PWR_MGMT_SUPPORT */
155 }
156
157 return USB_OK;
158 }
159
167 usb_status_enum usb_core_init (usb_core_handle_struct *pudev)
168 {
169 /* soft reset the core */
170 usb_core_reset(pudev);
171
172 /* active the transceiver and enable vbus sensing */
173 USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN;
174
175 /* set Tx FIFO empty level to half empty mode */
176 USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF;
177
178 #ifndef VBUS_SENSING_ENABLED
179 USB_GCCFG |= GCCFG_VBUSIG;
180 #endif /* VBUS_SENSING_ENABLED */
181
182 if(pudev->cfg.sof_output){
183 USB_GCCFG |= GCCFG_SOFOEN;
184 }
185
186 if (NULL != pudev->mdelay) {
187 pudev->mdelay(20U);
188 }
189
190
191 #ifdef USE_OTG_MODE
192 /* enable OTG features */
193 USB_GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP;
194 USB_OTG_EnableCommonInt(pudev);
195
196 #endif /* USE_OTG_MODE */
197
198 return USB_OK;
199 }
200
208 usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num)
209 {
210 uint32_t count = 0U;
211
212 USB_GRSTCTL &= ~GRSTCTL_TXFNUM;
213 USB_GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF;
214
215 /* wait for Tx FIFO flush bit is set */
216 do {
217 if (++count > 200000U) {
218 break;
219 }
220 } while (USB_GRSTCTL & GRSTCTL_TXFF);
221
222 /* wait for 3 PHY clocks */
223 if (NULL != pudev->udelay) {
224 pudev->udelay(3U);
225 }
226
227 return USB_OK;
228 }
229
236 usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev)
237 {
238 uint32_t count = 0U;
239
240 USB_GRSTCTL = GRSTCTL_RXFF;
241
242 /* wait for Rx FIFO flush bit is set */
243 do {
244 if (++count > 200000U) {
245 break;
246 }
247 } while (USB_GRSTCTL & GRSTCTL_RXFF);
248
249 /* wait for 3 PHY clocks */
250 if (NULL != pudev->udelay) {
251 pudev->udelay(3U);
252 }
253
254 return USB_OK;
255 }
256
266 usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode)
267 {
268 if (HOST_MODE == mode) {
269 USB_GUSBCS &= ~GUSBCS_FDM;
270 USB_GUSBCS |= GUSBCS_FHM;
271 } else if (DEVICE_MODE == mode) {
272 USB_GUSBCS &= ~GUSBCS_FHM;
273 USB_GUSBCS |= GUSBCS_FDM;
274 } else {
275 /* no operation */
276 }
277
278 if (NULL != pudev->mdelay) {
279 pudev->mdelay(50U);
280 }
281
282 return USB_OK;
283 }
284
285 #ifdef USE_HOST_MODE
286
293 usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev)
294 {
295 uint32_t i = 0U;
296 __IO uint32_t nptxfifolen = 0U;
297 __IO uint32_t ptxfifolen = 0U;
298
299 #ifdef USE_OTG_MODE
300 __IO uint32_t otgctl = 0;
301 #endif /* USE_OTG_MODE */
302
303 /* restart the PHY clock */
304 USB_PWRCLKCTL = 0U;
305
306 /* initialize host configuration register */
307 if (USB_CORE_ULPI_PHY == pudev->cfg.phy_interface) {
308 USB_FSLSCLOCK_INIT(HCTLR_30_60_MHZ);
309 } else {
310 USB_FSLSCLOCK_INIT(HCTLR_48_MHZ);
311 }
312
313 /* configure data FIFO sizes */
314 if (USB_FS_CORE_ID == pudev->cfg.core_id) {
315 /* set Rx FIFO size */
316 USB_GRFLEN = USBFS_RX_FIFO_SIZE;
317
318 /* set non-periodic Tx FIFO size and address */
319 nptxfifolen &= ~HNPTFLEN_HNPTXRSAR;
320 nptxfifolen |= USBFS_RX_FIFO_SIZE;
321 nptxfifolen &= ~HNPTFLEN_HNPTXFD;
322 nptxfifolen |= USBFS_HTX_NPFIFO_SIZE << 16;
323 USB_HNPTFLEN = nptxfifolen;
324
325 /* set periodic Tx FIFO size and address */
326 ptxfifolen &= ~HPTFLEN_HPTXFSAR;
327 ptxfifolen |= USBFS_RX_FIFO_SIZE + USBFS_HTX_PFIFO_SIZE;
328 ptxfifolen &= ~HPTFLEN_HPTXFD;
329 ptxfifolen |= USBFS_HTX_PFIFO_SIZE << 16;
330 USB_HPTFLEN = ptxfifolen;
331 }
332
333 #ifdef USE_OTG_MODE
334
335 /* clear Host Set HNP Enable bit in the USB OTG Control Register */
336 otgctl |= GOTGCS_HHNPEN;
337 USB_GOTGCS &= ~otgctl;
338 USB_GOTGCS |= 0;
339
340 #endif /* USE_OTG_MODE */
341
342 /* make sure the FIFOs are flushed */
343
344 /* flush all Tx FIFOs in device or host mode */
345 usb_txfifo_flush(pudev, 0x10U);
346
347 /* flush the entire Rx FIFO */
348 usb_rxfifo_flush(pudev);
349
350 /* clear all pending host channel interrupts */
351 USB_HACHINTEN &= ~HACHINTEN_CINTEN;
352
353 for (i = 0U; i < pudev->cfg.host_channel_num; i++) {
354 USB_HCHxINTEN(i) = 0U;
355 USB_HCHxINTF(i) = 0xFFFFFFFFU;
356 }
357
358 #ifndef USE_OTG_MODE
359 usb_vbus_drive(pudev, 1U);
360 #endif /* USE_OTG_MODE */
361
362 usb_hostint_enable(pudev);
363
364 return USB_OK;
365 }
366
374 void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state)
375 {
376 __IO uint32_t host_port = 0U;
377
378 /* enable or disable the external charge pump */
379 if ((void *)0 != pudev->host.vbus_drive) {
380 pudev->host.vbus_drive(pudev, state);
381 }
382
383 /* turn on the host port power. */
384 host_port = USB_PORT_READ();
385
386 if ((0U == (host_port & HPCS_PP)) && (1U == state)) {
387 host_port |= HPCS_PP;
388 } else if ((1U == (host_port & HPCS_PP)) && (0U == state)) {
389 host_port &= ~HPCS_PP;
390 } else {
391 /* no operation */
392 }
393
394 USB_HPCS = host_port;
395
396 if (NULL != pudev->mdelay) {
397 pudev->mdelay(200U);
398 }
399 }
400
407 usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev)
408 {
409 uint32_t gintf = 0U;
410
411 /* disable all interrupts */
412 USB_GINTEN = 0U;
413
414 /* clear any pending interrupts */
415 USB_GINTF = 0xFFFFFFFFU;
416
417 /* enable the common interrupts */
418 usb_commonint_enable(pudev);
419
420 gintf |= GINTF_RXFNEIF;
421
422 /* enable host_mode-related interrupts */
423 gintf |= GINTF_HPIF | GINTF_HCIF | GINTF_DISCIF | GINTF_SOF | GINTF_ISOONCIF;
424
425 USB_GINTEN &= ~gintf;
426 USB_GINTEN |= gintf;
427
428 return USB_OK;
429 }
430
437 uint32_t usb_port_reset (usb_core_handle_struct *pudev)
438 {
439 USB_HPCS = USB_PORT_READ() | HPCS_PRST;
440
441 if (NULL != pudev->mdelay) {
442 pudev->mdelay(100U);
443 }
444
445 USB_HPCS &= ~HPCS_PRST;
446
447 if (NULL != pudev->mdelay) {
448 pudev->mdelay(20U);
449 }
450
451 return USB_OK;
452 }
453
461 usb_status_enum usb_hostchannel_init(usb_core_handle_struct *pudev, uint8_t hc_num)
462 {
463 uint8_t is_low_speed = 0U;
464 __IO uint32_t chinten = 0U;
465 __IO uint32_t chctl = 0U;
466
467 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
468
469 /* clear old interrupt conditions for this host channel */
470 USB_HCHxINTF((uint16_t)hc_num) = 0xFFFFFFFFU;
471
472 /* enable channel interrupts required for this transfer */
473 switch (puhc->endp_type) {
474 case USB_EPTYPE_CTRL:
475 case USB_EPTYPE_BULK:
476 chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE \
477 | HCHINTEN_DTERIE | HCHINTEN_NAKIE;
478
479 if (puhc->endp_in) {
480 chinten |= HCHINTEN_BBERIE;
481 } else {
482 chinten |= HCHINTEN_NYETIE;
483 }
484 break;
485
486 case USB_EPTYPE_INTR:
487 chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \
488 | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE;
489
490 if (puhc->endp_in) {
491 chinten |= HCHINTEN_BBERIE;
492 }
493 break;
494
495 case USB_EPTYPE_ISOC:
496 chinten |= HCHINTEN_TFIE | HCHINTEN_REQOVRIE | HCHINTEN_ACKIE;
497
498 if (puhc->endp_in) {
499 chinten |= HCHINTEN_USBERIE | HCHINTEN_BBERIE;
500 }
501 break;
502
503 default:
504 break;
505 }
506
507 USB_HCHxINTEN((uint16_t)hc_num) = chinten;
508
509 /* enable the top level host channel interrupt */
510 USB_HACHINTEN |= 1U << hc_num;
511
512 /* make sure host channel interrupts are enabled */
513 USB_GINTEN |= GINTEN_HCIE;
514
515 /* program the hcctlr register */
516 chctl = 0U;
517
518 if (HPRT_PRTSPD_LOW_SPEED == puhc->dev_speed) {
519 is_low_speed = 1U;
520 }
521
522 chctl |= (uint32_t)puhc->dev_addr << 22U;
523 chctl |= (uint32_t)puhc->endp_type << 18U;
524 chctl |= (uint32_t)puhc->endp_id << 11U;
525 chctl |= (uint32_t)puhc->endp_in << 15U;
526 chctl |= (uint32_t)is_low_speed << 17U;
527 chctl |= puhc->endp_mps;
528
529 if (HCCHAR_INTR == puhc->endp_type) {
530 chctl |= HCHCTL_ODDFRM;
531 }
532
533 USB_HCHxCTL((uint16_t)hc_num) = chctl;
534
535 return USB_OK;
536 }
537
545 usb_status_enum usb_hostchannel_startxfer(usb_core_handle_struct *pudev, uint8_t hc_num)
546 {
547 uint16_t dword_len = 0U;
548 uint16_t packet_num = 0U;
549
550 __IO uint32_t chxlen = 0U;
551 __IO uint32_t chctl = 0U;
552
553 usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num];
554
555 /* compute the expected number of packets associated to the transfer */
556 if (puhc->xfer_len > 0U) {
557 packet_num = ((uint16_t)puhc->xfer_len + puhc->endp_mps - 1U) / puhc->endp_mps;
558
559 if (packet_num > HC_MAX_PACKET_COUNT) {
560 packet_num = HC_MAX_PACKET_COUNT;
561 puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps);
562 }
563 } else {
564 packet_num = 1U;
565 }
566
567 if (puhc->endp_in) {
568 puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps);
569 }
570
571 /* initialize the host channel length register */
572 chxlen &= ~HCHLEN_TLEN;
573 chxlen |= puhc->xfer_len;
574 chxlen &= ~HCHLEN_PCNT;
575 chxlen |= (uint32_t)packet_num << 19;
576 chxlen &= ~HCHLEN_DPID;
577 chxlen |= (uint32_t)(puhc->DPID) << 29;
578 USB_HCHxLEN((uint16_t)hc_num) = (uint32_t)chxlen;
579
580 /* set host channel enable */
581 chctl = USB_HCHxCTL((uint16_t)hc_num);
582
583 if (1 == USB_EVEN_FRAME()) {
584 chctl |= HCHCTL_ODDFRM;
585 } else {
586 chctl &= ~HCHCTL_ODDFRM;
587 }
588
589 chctl |= HCHCTL_CEN;
590 chctl &= ~HCHCTL_CDIS;
591 USB_HCHxCTL((uint16_t)hc_num) = chctl;
592
593 if ((0U == puhc->endp_in) && (puhc->xfer_len > 0U)) {
594 dword_len = (uint16_t)(puhc->xfer_len + 3U) / 4U;
595
596 switch (puhc->endp_type) {
597 /* non-periodic transfer */
598 case USB_EPTYPE_CTRL:
599 case USB_EPTYPE_BULK:
600 /* check if there is enough space in fifo space */
601 if (dword_len > (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) {
602 /* need to process data in non-periodic transfer fifo empty interrupt */
603 USB_GINTEN |= GINTEN_NPTXFEIE;
604 }
605 break;
606
607 /* periodic transfer */
608 case USB_EPTYPE_INTR:
609 case USB_EPTYPE_ISOC:
610 /* check if there is enough space in FIFO space */
611 if (dword_len > (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) {
612 /* need to process data in periodic transfer fifo empty interrupt */
613 USB_GINTEN |= GINTEN_PTXFEIE;
614 }
615 break;
616
617 default:
618 break;
619 }
620
621 /* write packet into the Tx FIFO. */
622 usb_fifo_write(puhc->xfer_buff, hc_num, (uint16_t)puhc->xfer_len);
623 }
624
625 return USB_OK;
626 }
627
635 usb_status_enum usb_hostchannel_halt(usb_core_handle_struct *pudev, uint8_t hc_num)
636 {
637 uint8_t endp_type = 0U;
638 __IO uint32_t chctl = USB_HCHxCTL((uint16_t)hc_num);
639
640 chctl |= HCHCTL_CEN | HCHCTL_CDIS;
641
642 endp_type = (uint8_t)((chctl & HCHCTL_EPTYPE) >> 18U);
643
644 /* check for space in the request queue to issue the halt. */
645 if ((HCCHAR_CTRL == endp_type) || (HCCHAR_BULK == endp_type)) {
646 if (0U == (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) {
647 chctl &= ~HCHCTL_CEN;
648 }
649 } else {
650 if (0U == (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) {
651 chctl &= ~HCHCTL_CEN;
652 }
653 }
654
655 USB_HCHxCTL((uint16_t)hc_num) = chctl;
656
657 return USB_OK;
658 }
659
666 void usb_host_stop(usb_core_handle_struct *pudev)
667 {
668 uint32_t i;
669
670 /* disable all host channel interrupt */
671 USB_HACHINTEN = 0U;
672 USB_HACHINT = 0xFFFFFFFFU;
673
674 /* flush out any leftover queued requests */
675 for (i = 0U; i < pudev->cfg.host_channel_num; i++) {
676 USB_HCHxCTL(i) |= HCHCTL_CEN | HCHCTL_CDIS | HCHCTL_EPDIR;
677 }
678
679 /* flush the FIFO */
680 usb_rxfifo_flush(pudev);
681 usb_txfifo_flush(pudev, 0x10U);
682 }
683
684 #endif /* USE_HOST_MODE */
685
686
687 #ifdef USE_DEVICE_MODE
688
689 /* USB endpoint Tx FIFO size */
690 static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_DEV_EPCOUNT] =
691 {
692 (uint16_t)TX0_FIFO_FS_SIZE,
693 (uint16_t)TX1_FIFO_FS_SIZE,
694 (uint16_t)TX2_FIFO_FS_SIZE,
695 (uint16_t)TX3_FIFO_FS_SIZE
696 };
697
698 static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev);
699
706 usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev)
707 {
708 uint32_t i, ram_address = 0U;
709 __IO uint32_t devinep0intf = USB_DIEP0TFLEN;
710 __IO uint32_t devinepintf = 0U;
711
712 /* restart the Phy Clock (Maybe don't need to...) */
713 USB_PWRCLKCTL = 0U;
714
715 /* config periodic frmae interval to default */
716 USB_DCFG &= ~DCFG_EOPFT;
717 USB_DCFG |= FRAME_INTERVAL_80;
718
719 if (USB_FS_CORE_ID == pudev->cfg.core_id) {
720 /* set full speed PHY */
721 USB_DCFG &= ~DCFG_DS;
722 USB_DCFG |= USB_SPEED_INP_FULL;
723
724 /* set Rx FIFO size */
725 USB_GRFLEN &= ~GRFLEN_RXFD;
726 USB_GRFLEN |= (uint32_t)RX_FIFO_FS_SIZE;
727
728 /* set endpoint 0 Tx FIFO length and RAM address */
729 devinep0intf &= ~DIEP0TFLEN_IEP0TXFD;
730 devinep0intf |= (uint32_t)TX0_FIFO_FS_SIZE << 16;
731 devinep0intf &= ~DIEP0TFLEN_IEP0TXRSAR;
732 devinep0intf |= (uint32_t)RX_FIFO_FS_SIZE;
733
734 USB_DIEP0TFLEN = devinep0intf;
735
736 ram_address = (uint32_t)RX_FIFO_FS_SIZE;
737
738 /* set endpoint 1 to 3's Tx FIFO length and RAM address */
739 for (i = 1U; i < USBFS_MAX_DEV_EPCOUNT; i++) {
740 ram_address += USBFS_TX_FIFO_SIZE[i - 1U];
741
742 devinepintf &= ~DIEPTFLEN_IEPTXFD;
743 devinepintf |= (uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U;
744 devinepintf &= ~DIEPTFLEN_IEPTXRSAR;
745 devinepintf |= ram_address;
746
747 USB_DIEPxTFLEN(i) = devinepintf;
748 }
749 }
750
751 /* make sure all FIFOs are flushed */
752
753 /* flush all Tx FIFOs */
754 usb_txfifo_flush(pudev, 0x10U);
755
756 /* flush entire Rx FIFO */
757 usb_rxfifo_flush(pudev);
758
759 /* clear all pending device interrupts */
760 USB_DIEPINTEN = 0U;
761 USB_DOEPINTEN = 0U;
762 USB_DAEPINT = 0xFFFFFFFFU;
763 USB_DAEPINTEN = 0U;
764
765 /* configure all IN/OUT endpoints */
766 for (i = 0U; i < pudev->cfg.dev_endp_num; i++) {
767 if (USB_DIEPxCTL(i) & DEPCTL_EPEN) {
768 USB_DIEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK;
769 } else {
770 USB_DIEPxCTL(i) = 0U;
771 }
772
773 if (USB_DOEPxCTL(i) & DEPCTL_EPEN) {
774 USB_DOEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK;
775 } else {
776 USB_DOEPxCTL(i) = 0U;
777 }
778
779 /* set IN/OUT endpoint transfer length to 0 */
780 USB_DIEPxLEN(i) = 0U;
781 USB_DOEPxLEN(i) = 0U;
782
783 /* clear all pending IN/OUT endpoints interrupts */
784 USB_DIEPxINTF(i) = 0xFFU;
785 USB_DOEPxINTF(i) = 0xFFU;
786 }
787
788 usb_devint_enable(pudev);
789
790 return USB_OK;
791 }
792
799 static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev)
800 {
801 uint32_t int_mask = 0U;
802
803 /* disable all interrupts */
804 USB_GINTEN = 0U;
805
806 /* clear any pending interrupts */
807 USB_GINTF = 0xBFFFFFFFU;
808
809 /* enable the common interrupts */
810 usb_commonint_enable(pudev);
811
812 int_mask = GINTEN_RXFNEIE;
813
814 /* enable device_mode-related interrupts */
815 int_mask |= GINTEN_SPIE | GINTEN_RSTIE | GINTEN_ENUMFIE \
816 | GINTEN_IEPIE | GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE \
817 | GINTEN_ISOINCIE;
818
819 #ifdef VBUS_SENSING_ENABLED
820 int_mask |= GINTEN_SESIE | GINTEN_OTGIE;
821 #endif /* VBUS_SENSING_ENABLED */
822
823 USB_GINTEN &= ~int_mask;
824 USB_GINTEN |= int_mask;
825
826 return USB_OK;
827 }
828
835 void usb_ep0_startout(usb_core_handle_struct *pudev)
836 {
837 __IO uint32_t ep0len = 0U;
838
839 /* set OUT endpoint 0 receive length to 24 bytes */
840 ep0len &= ~DOEP0LEN_TLEN;
841 ep0len |= 8U * 3U;
842
843 /* set OUT endpoint 0 receive length to 1 packet */
844 ep0len &= ~DOEP0LEN_PCNT;
845 ep0len |= 1U << 19;
846
847 /* set SETUP packet count to 3 */
848 ep0len &= ~DOEP0LEN_STPCNT;
849 ep0len |= 3U << 29;
850
851 USB_DOEPxLEN(0U) = ep0len;
852 }
853
860 void usb_remotewakeup_active(usb_core_handle_struct *pudev)
861 {
862 __IO uint32_t power_clock;
863
864 if (pudev->dev.remote_wakeup) {
865 if (1U == (USB_DSTAT & DSTAT_SPST)) {
866 if (pudev->cfg.low_power) {
867 /* ungate USB core clock */
868 power_clock = USB_PWRCLKCTL;
869 power_clock &= ~PWRCLKCTL_SHCLK;
870 power_clock &= ~PWRCLKCTL_SUCLK;
871
872 USB_PWRCLKCTL = power_clock;
873 }
874
875 /* active remote wakeup signaling */
876 USB_DCTL |= DCTL_RWKUP;
877
878 if (pudev->mdelay != (void *)0) {
879 pudev->mdelay(5U);
880 }
881
882 USB_DCTL &= ~DCTL_RWKUP;
883 }
884 }
885 }
886
893 void usb_clock_ungate(usb_core_handle_struct *pudev)
894 {
895 if (pudev->cfg.low_power) {
896 __IO uint32_t power_clock;
897
898 if (1U == (USB_DSTAT & DSTAT_SPST)) {
899 /* un-gate USB core clock */
900 power_clock = USB_PWRCLKCTL;
901 power_clock &= ~PWRCLKCTL_SHCLK;
902 power_clock &= ~PWRCLKCTL_SUCLK;
903
904 USB_PWRCLKCTL = power_clock;
905 }
906 }
907 }
908
915 void usb_device_stop (usb_core_handle_struct *pudev)
916 {
917 uint32_t i;
918
919 pudev->dev.status = 1U;
920
921 for (i = 0U; i < pudev->cfg.dev_endp_num; i++) {
922 USB_DIEPxINTF(i) = 0xFFU;
923 USB_DOEPxINTF(i) = 0xFFU;
924 }
925
926 USB_DIEPINTEN = 0U;
927 USB_DOEPINTEN = 0U;
928 USB_DAEPINTEN = 0U;
929 USB_DAEPINT = 0xFFFFFFFFU;
930
931 /* flush the FIFO */
932 usb_rxfifo_flush(pudev);
933 usb_txfifo_flush(pudev, 0x10U);
934 }
935 #endif /* USE_DEVICE_MODE */
HCHLEN_DPID
#define HCHLEN_DPID
Definition: usb_regs.h:329
HCHINTEN_BBERIE
#define HCHINTEN_BBERIE
Definition: usb_regs.h:317
USB_DIEPxTFLEN
#define USB_DIEPxTFLEN(x)
Definition: usb_regs.h:51
USB_DIEP0TFLEN
#define USB_DIEP0TFLEN
Definition: usb_regs.h:46
GINTEN_OTGIE
#define GINTEN_OTGIE
Definition: usb_regs.h:195
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:48
DOEP0LEN_TLEN
#define DOEP0LEN_TLEN
Definition: usb_regs.h:473
USBFS_MAX_PACKET_SIZE
#define USBFS_MAX_PACKET_SIZE
Definition: usb_defines.h:24
GRFLEN_RXFD
#define GRFLEN_RXFD
Definition: usb_regs.h:206
GINTEN_ISOINCIE
#define GINTEN_ISOINCIE
Definition: usb_regs.h:181
USB_DOEPINTEN
#define USB_DOEPINTEN
Definition: usb_regs.h:69
USB_DIEPxINTF
#define USB_DIEPxINTF(x)
Definition: usb_regs.h:85
USB_FSLSCLOCK_INIT
#define USB_FSLSCLOCK_INIT(ClockFreq)
Definition: usb_regs.h:614
GRSTCTL_TXFNUM
#define GRSTCTL_TXFNUM
Definition: usb_regs.h:136
USB_HNPTFLEN
#define USB_HNPTFLEN
Definition: usb_regs.h:45
GINTF_RXFNEIF
#define GINTF_RXFNEIF
Definition: usb_regs.h:165
HPRT_PRTSPD_LOW_SPEED
#define HPRT_PRTSPD_LOW_SPEED
Definition: usb_defines.h:75
USB_GCCFG
#define USB_GCCFG
Definition: usb_regs.h:48
GINTEN_NPTXFEIE
#define GINTEN_NPTXFEIE
Definition: usb_regs.h:192
USB_EPTYPE_ISOC
#define USB_EPTYPE_ISOC
Definition: usb_defines.h:52
DIEP0TFLEN_IEP0TXFD
#define DIEP0TFLEN_IEP0TXFD
Definition: usb_regs.h:213
DOEP0LEN_STPCNT
#define DOEP0LEN_STPCNT
Definition: usb_regs.h:471
HPCS_PP
#define HPCS_PP
Definition: usb_regs.h:272
HCHCTL_CDIS
#define HCHCTL_CDIS
Definition: usb_regs.h:284
FRAME_INTERVAL_80
#define FRAME_INTERVAL_80
Definition: usb_regs.h:517
GINTEN_RSTIE
#define GINTEN_RSTIE
Definition: usb_regs.h:187
usb_hostchannel_struct::xfer_buff
uint8_t * xfer_buff
Definition: usb_core.h:165
GINTEN_ISOONCIE
#define GINTEN_ISOONCIE
Definition: usb_regs.h:180
DEPCTL_SNAK
#define DEPCTL_SNAK
Definition: usb_regs.h:437
USB_DAEPINTEN
#define USB_DAEPINTEN
Definition: usb_regs.h:71
usb_core_cfgs_struct::dev_endp_num
uint8_t dev_endp_num
Definition: usb_core.h:65
USB_DIEPINTEN
#define USB_DIEPINTEN
Definition: usb_regs.h:68
HCHINTEN_STALLIE
#define HCHINTEN_STALLIE
Definition: usb_regs.h:322
usb_core_cfgs_struct::max_packet_size
uint16_t max_packet_size
Definition: usb_core.h:68
GAHBCS_TXFTH
#define GAHBCS_TXFTH
Definition: usb_regs.h:117
DEPCTL_EPEN
#define DEPCTL_EPEN
Definition: usb_regs.h:431
HNPTFQSTAT_NPTXFS
#define HNPTFQSTAT_NPTXFS
Definition: usb_regs.h:219
GCCFG_VBUSBCEN
#define GCCFG_VBUSBCEN
Definition: usb_regs.h:228
HC_MAX_PACKET_COUNT
#define HC_MAX_PACKET_COUNT
Definition: usb_core.h:21
USB_EPTYPE_INTR
#define USB_EPTYPE_INTR
Definition: usb_defines.h:54
DIEP0TFLEN_IEP0TXRSAR
#define DIEP0TFLEN_IEP0TXRSAR
Definition: usb_regs.h:214
USBFS_MAX_HOST_CHANNELCOUNT
#define USBFS_MAX_HOST_CHANNELCOUNT
Definition: usb_defines.h:25
HCHINTEN_TFIE
#define HCHINTEN_TFIE
Definition: usb_regs.h:325
HCHINTEN_DTERIE
#define HCHINTEN_DTERIE
Definition: usb_regs.h:315
USB_GUSBCS
#define USB_GUSBCS
Definition: usb_regs.h:38
USB_GINTEN
#define USB_GINTEN
Definition: usb_regs.h:41
usb_core_handle_struct::udelay
void(* udelay)(const uint32_t usec)
Definition: usb_core.h:216
HCCHAR_INTR
#define HCCHAR_INTR
Definition: usb_defines.h:84
GRSTCTL_CSRST
#define GRSTCTL_CSRST
Definition: usb_regs.h:141
GUSBCS_FDM
#define GUSBCS_FDM
Definition: usb_regs.h:123
GCCFG_PWRON
#define GCCFG_PWRON
Definition: usb_regs.h:230
USB_OK
Definition: usb_core.h:29
USB_HNPTFQSTAT
#define USB_HNPTFQSTAT
Definition: usb_regs.h:47
USB_EVEN_FRAME
#define USB_EVEN_FRAME()
Definition: usb_regs.h:608
USB_GINTF
#define USB_GINTF
Definition: usb_regs.h:40
usb_hostchannel_struct::endp_in
uint8_t endp_in
Definition: usb_core.h:160
USB_EPTYPE_CTRL
#define USB_EPTYPE_CTRL
Definition: usb_defines.h:51
DEPCTL_EPD
#define DEPCTL_EPD
Definition: usb_regs.h:432
USB_DIEPxLEN
#define USB_DIEPxLEN(x)
Definition: usb_regs.h:87
HCHINTEN_NAKIE
#define HCHINTEN_NAKIE
Definition: usb_regs.h:321
TXFIFO_EMPTY_HALF
#define TXFIFO_EMPTY_HALF
Definition: usb_regs.h:504
USB_GRFLEN
#define USB_GRFLEN
Definition: usb_regs.h:44
USB_HCHxLEN
#define USB_HCHxLEN(x)
Definition: usb_regs.h:63
DCTL_RWKUP
#define DCTL_RWKUP
Definition: usb_regs.h:352
USB_GOTGCS
#define USB_GOTGCS
Definition: usb_regs.h:35
HCHCTL_EPTYPE
#define HCHCTL_EPTYPE
Definition: usb_regs.h:288
usb_txfifo_flush
usb_status_enum usb_txfifo_flush(usb_core_handle_struct *pudev, uint8_t fifo_num)
flush a Tx FIFO or all Tx FIFOs
Definition: usb_core.c:208
USB_PWRCLKCTL
#define USB_PWRCLKCTL
Definition: usb_regs.h:91
HPCS_PRST
#define HPCS_PRST
Definition: usb_regs.h:274
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:217
USB_HACHINT
#define USB_HACHINT
Definition: usb_regs.h:57
HPTFLEN_HPTXFSAR
#define HPTFLEN_HPTXFSAR
Definition: usb_regs.h:237
usb_fifo_write
usb_status_enum usb_fifo_write(uint8_t *src, uint8_t chep_num, uint16_t len)
write a packet into the Tx FIFO associated with the endpoint
Definition: usb_core.c:79
GCCFG_SOFOEN
#define GCCFG_SOFOEN
Definition: usb_regs.h:227
usb_core_cfgs_struct::phy_interface
uint8_t phy_interface
Definition: usb_core.h:63
USB_DOEPxINTF
#define USB_DOEPxINTF(x)
Definition: usb_regs.h:86
GINTEN_IEPIE
#define GINTEN_IEPIE
Definition: usb_regs.h:183
USB_CORE_ULPI_PHY
#define USB_CORE_ULPI_PHY
Definition: usb_defines.h:34
DIEPTFLEN_IEPTXFD
#define DIEPTFLEN_IEPTXFD
Definition: usb_regs.h:240
USB_SPEED_INP_FULL
#define USB_SPEED_INP_FULL
Definition: usb_regs.h:500
GINTEN_OEPIE
#define GINTEN_OEPIE
Definition: usb_regs.h:182
USB_DIEPxCTL
#define USB_DIEPxCTL(x)
Definition: usb_regs.h:83
USB_CORE_SPEED_FULL
#define USB_CORE_SPEED_FULL
Definition: usb_defines.h:22
usb_hostchannel_struct
Definition: usb_core.h:154
HCCHAR_CTRL
#define HCCHAR_CTRL
Definition: usb_defines.h:81
HCCHAR_BULK
#define HCCHAR_BULK
Definition: usb_defines.h:83
GINTEN_SOFIE
#define GINTEN_SOFIE
Definition: usb_regs.h:194
USB_HCHxINTF
#define USB_HCHxINTF(x)
Definition: usb_regs.h:61
usb_core_cfgs_struct::sof_output
uint8_t sof_output
Definition: usb_core.h:66
GINTEN_SESIE
#define GINTEN_SESIE
Definition: usb_regs.h:173
USB_CORE_EMBEDDED_PHY
#define USB_CORE_EMBEDDED_PHY
Definition: usb_defines.h:35
GRSTCTL_TXFF
#define GRSTCTL_TXFF
Definition: usb_regs.h:137
usb_hostchannel_struct::endp_mps
uint16_t endp_mps
Definition: usb_core.h:162
GUSBCS_FHM
#define GUSBCS_FHM
Definition: usb_regs.h:124
USB_DAEPINT
#define USB_DAEPINT
Definition: usb_regs.h:70
USB_DSTAT
#define USB_DSTAT
Definition: usb_regs.h:67
HCHINTEN_NYETIE
#define HCHINTEN_NYETIE
Definition: usb_regs.h:319
usb_core_cfgs_struct::core_speed
uint8_t core_speed
Definition: usb_core.h:62
usb_core_cfgs_struct::low_power
uint8_t low_power
Definition: usb_core.h:67
GCCFG_VBUSACEN
#define GCCFG_VBUSACEN
Definition: usb_regs.h:229
GINTEN_ENUMFIE
#define GINTEN_ENUMFIE
Definition: usb_regs.h:186
DOEP0LEN_PCNT
#define DOEP0LEN_PCNT
Definition: usb_regs.h:472
usb_fifo_read
void * usb_fifo_read(uint8_t *dest, uint16_t len)
read a packet from the Rx FIFO associated with the endpoint
Definition: usb_core.c:102
HACHINTEN_CINTEN
#define HACHINTEN_CINTEN
Definition: usb_regs.h:268
usb_hostchannel_struct::DPID
uint8_t DPID
Definition: usb_core.h:158
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:266
usb_hostchannel_struct::xfer_len
uint32_t xfer_len
Definition: usb_core.h:166
GINTF_HCIF
#define GINTF_HCIF
Definition: usb_regs.h:149
USB_FIFO
#define USB_FIFO(x)
Definition: usb_regs.h:93
usb_core.h
USB core driver header file.
USB_HCHxINTEN
#define USB_HCHxINTEN(x)
Definition: usb_regs.h:62
USB_DOEPxCTL
#define USB_DOEPxCTL(x)
Definition: usb_regs.h:84
USB_GOTGINTF
#define USB_GOTGINTF
Definition: usb_regs.h:36
DSTAT_SPST
#define DSTAT_SPST
Definition: usb_regs.h:357
GRSTCTL_RXFF
#define GRSTCTL_RXFF
Definition: usb_regs.h:138
USB_HPTFQSTAT
#define USB_HPTFQSTAT
Definition: usb_regs.h:56
HCHCTL_ODDFRM
#define HCHCTL_ODDFRM
Definition: usb_regs.h:285
HPTFLEN_HPTXFD
#define HPTFLEN_HPTXFD
Definition: usb_regs.h:236
GINTEN_WKUPIE
#define GINTEN_WKUPIE
Definition: usb_regs.h:172
HCHCTL_EPDIR
#define HCHCTL_EPDIR
Definition: usb_regs.h:290
usb_status_enum
usb_status_enum
Definition: usb_core.h:27
usb_hostchannel_struct::dev_addr
uint8_t dev_addr
Definition: usb_core.h:156
HCHCTL_CEN
#define HCHCTL_CEN
Definition: usb_regs.h:283
HNPTFLEN_HNPTXRSAR
#define HNPTFLEN_HNPTXRSAR
Definition: usb_regs.h:210
USB_HCHxCTL
#define USB_HCHxCTL(x)
Definition: usb_regs.h:60
GCCFG_VBUSIG
#define GCCFG_VBUSIG
Definition: usb_regs.h:226
USB_FS_CORE_ID
Definition: usb_defines.h:89
HCHINTEN_USBERIE
#define HCHINTEN_USBERIE
Definition: usb_regs.h:318
usb_core_handle_struct
Definition: usb_core.h:200
usb_hostchannel_struct::dev_speed
uint8_t dev_speed
Definition: usb_core.h:157
DIEPTFLEN_IEPTXRSAR
#define DIEPTFLEN_IEPTXRSAR
Definition: usb_regs.h:241
USB_HACHINTEN
#define USB_HACHINTEN
Definition: usb_regs.h:58
USBFS_MAX_FIFO_WORDLEN
#define USBFS_MAX_FIFO_WORDLEN
Definition: usb_defines.h:27
USBFS_MAX_DEV_EPCOUNT
#define USBFS_MAX_DEV_EPCOUNT
Definition: usb_defines.h:26
HNPTFLEN_HNPTXFD
#define HNPTFLEN_HNPTXFD
Definition: usb_regs.h:209
GINTEN_PTXFEIE
#define GINTEN_PTXFEIE
Definition: usb_regs.h:176
GINTF_HPIF
#define GINTF_HPIF
Definition: usb_regs.h:150
USB_DOEPxLEN
#define USB_DOEPxLEN(x)
Definition: usb_regs.h:88
NULL
#define NULL
Definition: usb_defines.h:18
USB_GRSTCTL
#define USB_GRSTCTL
Definition: usb_regs.h:39
HCHLEN_PCNT
#define HCHLEN_PCNT
Definition: usb_regs.h:330
usb_core_cfgs_struct::max_fifo_size
uint16_t max_fifo_size
Definition: usb_core.h:69
usb_hostchannel_struct::endp_type
uint8_t endp_type
Definition: usb_core.h:161
usb_core_cfgs_struct::core_id
uint8_t core_id
Definition: usb_core.h:61
PWRCLKCTL_SUCLK
#define PWRCLKCTL_SUCLK
Definition: usb_regs.h:493
USB_HPCS
#define USB_HPCS
Definition: usb_regs.h:59
usb_rxfifo_flush
usb_status_enum usb_rxfifo_flush(usb_core_handle_struct *pudev)
flush the entire Rx FIFO
Definition: usb_core.c:236
GINTEN_RXFNEIE
#define GINTEN_RXFNEIE
Definition: usb_regs.h:193
GINTF_ISOONCIF
#define GINTF_ISOONCIF
Definition: usb_regs.h:152
USB_HPTFLEN
#define USB_HPTFLEN
Definition: usb_regs.h:50
HPTFQSTAT_PTXFS
#define HPTFQSTAT_PTXFS
Definition: usb_regs.h:257
USB_DCFG
#define USB_DCFG
Definition: usb_regs.h:65
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:167
USB_PORT_READ
#define USB_PORT_READ()
Definition: usb_regs.h:611
GINTEN_HCIE
#define GINTEN_HCIE
Definition: usb_regs.h:177
usb_core_cfgs_struct::host_channel_num
uint8_t host_channel_num
Definition: usb_core.h:64
USB_GAHBCS
#define USB_GAHBCS
Definition: usb_regs.h:37
HCTLR_30_60_MHZ
#define HCTLR_30_60_MHZ
Definition: usb_defines.h:77
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:125
GINTEN_SPIE
#define GINTEN_SPIE
Definition: usb_regs.h:188
GINTF_SOF
#define GINTF_SOF
Definition: usb_regs.h:166
DCFG_DS
#define DCFG_DS
Definition: usb_regs.h:341
DEVICE_MODE
#define DEVICE_MODE
Definition: usb_defines.h:47
HCHLEN_TLEN
#define HCHLEN_TLEN
Definition: usb_regs.h:331
HCTLR_48_MHZ
#define HCTLR_48_MHZ
Definition: usb_defines.h:78
DCFG_EOPFT
#define DCFG_EOPFT
Definition: usb_regs.h:338
GINTF_DISCIF
#define GINTF_DISCIF
Definition: usb_regs.h:146
USB_DCTL
#define USB_DCTL
Definition: usb_regs.h:66
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:86
HCHINTEN_REQOVRIE
#define HCHINTEN_REQOVRIE
Definition: usb_regs.h:316
usb_core_handle_struct::cfg
usb_core_cfgs_struct cfg
Definition: usb_core.h:202
HCHINTEN_ACKIE
#define HCHINTEN_ACKIE
Definition: usb_regs.h:320
USB_EPTYPE_BULK
#define USB_EPTYPE_BULK
Definition: usb_defines.h:53
PWRCLKCTL_SHCLK
#define PWRCLKCTL_SHCLK
Definition: usb_regs.h:492
usb_hostchannel_struct::endp_id
uint8_t endp_id
Definition: usb_core.h:159
GOTGCS_HHNPEN
#define GOTGCS_HHNPEN
Definition: usb_regs.h:101
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Source/usbh_core.c Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Source
usbh_core.c
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #include "usbh_hcs.h"
13 #include "usbh_core.h"
14 #include "usbh_int.h"
15 #include "stdio.h"
16 #include "usbh_std.h"
17 #include "usbh_ctrl.h"
18 #include "usb_core.h"
19
20 extern class_polling_fun_cb_struct class_polling_cb;
21
22 uint8_t usbh_sof (usb_core_handle_struct *pudev);
23 uint8_t usbh_connected (usb_core_handle_struct *pudev);
24 uint8_t usbh_disconnected (usb_core_handle_struct *pudev);
25
26 usbh_hcd_int_cb_struct usbh_hcd_int_cb =
27 {
28 usbh_sof,
29 usbh_connected,
30 usbh_disconnected,
31 };
32
33 usbh_hcd_int_cb_struct *usbh_hcd_int_fops = &usbh_hcd_int_cb;
34 extern usbh_state_handle_struct usbh_state_core;
35
36 static void host_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
37 static void host_dev_attached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
38 static void host_dev_detached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
39 static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
40 static void host_enum_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
41 static void host_class_request_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
42 static void host_class_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
43 static void host_user_input_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
44 static void host_suspended_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
45 static void host_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate);
46
47 static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
48 static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate);
49
50 /* the host state handle function array */
51 void (*host_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) =
52 {
53 host_idle_handle,
54 host_dev_attached_handle,
55 host_dev_detached_handle,
56 host_detect_dev_speed_handle,
57 host_enum_handle,
58 host_class_request_handle,
59 host_class_handle,
60 host_user_input_handle,
61 host_suspended_handle,
62 host_error_handle,
63 };
64
65 /* the host state handle table */
66 state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE] =
67 {
68 /* the current state the current event the next state the event function */
69 {HOST_IDLE, HOST_EVENT_ATTACHED, HOST_DEV_ATTACHED, only_state_move },
70 {HOST_DEV_ATTACHED, HOST_EVENT_ENUM, HOST_ENUMERATION, only_state_move },
71 {HOST_ENUMERATION, HOST_EVENT_USER_INPUT, HOST_USER_INPUT, only_state_move },
72 {HOST_USER_INPUT, HOST_EVENT_CLASS_REQ, HOST_CLASS_REQUEST, only_state_move },
73 {HOST_CLASS_REQUEST, HOST_EVENT_CLASS, HOST_CLASS, only_state_move },
74 {HOST_CLASS, HOST_EVENT_ERROR, HOST_ERROR, only_state_move },
75 {HOST_ERROR, HOST_EVENT_IDLE, HOST_IDLE, only_state_move },
76 {HOST_DEV_DETACHED, HOST_EVENT_IDLE, HOST_IDLE, only_state_move },
77 {HOST_CLASS_REQUEST, HOST_EVENT_ERROR, HOST_ERROR, only_state_move },
78 };
79
88 usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev,
89 usbh_host_struct *puhost,
90 void *pustate)
91 {
92 usbh_state_handle_struct *p_state = (usbh_state_handle_struct *)pustate;
93
94 scd_begin(p_state, HOST_FSM_ID);
95
96 if (-1 == p_state->usbh_current_state_stack_top) {
97 uint8_t cur_state = p_state->usbh_current_state;
98
99 if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != cur_state)) {
100 if (HOST_DEV_DETACHED != cur_state) {
101 p_state->usbh_current_state = HOST_DEV_DETACHED;
102 cur_state = HOST_DEV_DETACHED;
103 }
104 }
105
106 host_state_handle[cur_state](pudev, puhost, p_state);
107 } else {
108 uint8_t stack0_state = p_state->stack[0].state;
109
110 if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != stack0_state)) {
111 if (HOST_DEV_DETACHED != stack0_state) {
112 p_state->stack[0].state = HOST_DEV_DETACHED;
113 stack0_state = HOST_DEV_DETACHED;
114 p_state->usbh_current_state = HOST_DEV_DETACHED;
115 }
116 }
117
118 host_state_handle[stack0_state](pudev, puhost, p_state);
119 }
120
121 return USBH_OK;
122 }
123
132 static void host_idle_handle (usb_core_handle_struct *pudev,
133 usbh_host_struct *puhost,
134 usbh_state_handle_struct *pustate)
135 {
136 if (hcd_is_device_connected(pudev)) {
137 scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ATTACHED, pustate->usbh_current_state);
138
139 if ((void *)0 != pudev->mdelay) {
140 pudev->mdelay(100U);
141 }
142 }
143 }
144
153 static void host_dev_attached_handle (usb_core_handle_struct *pudev,
154 usbh_host_struct *puhost,
155 usbh_state_handle_struct *pustate)
156 {
157 puhost->usr_cb->device_connected();
158 puhost->control.hc_out_num = usbh_channel_alloc(pudev, 0x00U);
159 puhost->control.hc_in_num = usbh_channel_alloc(pudev, 0x80U);
160
161 /* reset usb device */
162 if (0U == usb_port_reset(pudev)) {
163 puhost->usr_cb->device_reset();
164
165 /* wait for USB USBH_ISR_PrtEnDisableChange()
166 * host is now ready to start the enumeration
167 */
168 puhost->device.speed = (uint8_t)USB_CURRENT_SPEED_GET();
169 puhost->usr_cb->device_speed_detected(puhost->device.speed);
170
171 /* open IN control pipes */
172 usbh_channel_open (pudev,
173 puhost->control.hc_in_num,
174 puhost->device.address,
175 puhost->device.speed,
176 USB_EPTYPE_CTRL,
177 (uint16_t)puhost->control.ep0_size);
178
179 /* open OUT control pipes */
180 usbh_channel_open (pudev,
181 puhost->control.hc_out_num,
182 puhost->device.address,
183 puhost->device.speed,
184 USB_EPTYPE_CTRL,
185 (uint16_t)puhost->control.ep0_size);
186
187 scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ENUM, pustate->usbh_current_state);
188 }
189 }
190
199 static void host_enum_handle (usb_core_handle_struct *pudev,
200 usbh_host_struct *puhost,
201 usbh_state_handle_struct *pustate)
202 {
203 if (USBH_OK == enum_state_polling_fun(pudev, puhost, pustate)) {
204 puhost->usr_cb->enumeration_finish();
205 scd_event_handle(pudev,
206 puhost,
207 pustate,
208 HOST_EVENT_USER_INPUT,
209 pustate->usbh_current_state);
210 }
211 }
212
221 static void host_user_input_handle (usb_core_handle_struct *pudev,
222 usbh_host_struct *puhost,
223 usbh_state_handle_struct *pustate)
224 {
225 if (USBH_USER_RESP_OK == puhost->usr_cb->user_input()) {
226 if (USBH_OK == (puhost->class_init(pudev, puhost))) {
227 scd_event_handle(pudev,
228 puhost,
229 pustate,
230 HOST_EVENT_CLASS_REQ,
231 pustate->usbh_current_state);
232 }
233 }
234 }
235
244 static void host_class_request_handle (usb_core_handle_struct *pudev,
245 usbh_host_struct *puhost,
246 usbh_state_handle_struct *pustate)
247 {
248 if (USBH_OK == class_req_state_polling_fun(pudev, puhost, pustate)) {
249 scd_event_handle(pudev, puhost, pustate, HOST_EVENT_CLASS, pustate->usbh_current_state);
250 }
251 }
252
261 static void host_class_handle (usb_core_handle_struct *pudev,
262 usbh_host_struct *puhost,
263 usbh_state_handle_struct *pustate)
264 {
265 class_state_polling_fun(pudev, puhost, pustate);
266 }
267
276 static void host_suspended_handle (usb_core_handle_struct *pudev,
277 usbh_host_struct *puhost,
278 usbh_state_handle_struct *pustate)
279 {
280 /* no operation */
281 }
282
291 static void host_error_handle (usb_core_handle_struct *pudev,
292 usbh_host_struct *puhost,
293 usbh_state_handle_struct *pustate)
294 {
295 /* re-initilaize host for new enumeration */
296 usbh_deinit (pudev, puhost,&usbh_state_core);
297 puhost->usr_cb->deinit();
298 puhost->class_deinit(pudev, &puhost->device);
299 scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state);
300 }
301
310 static void host_dev_detached_handle (usb_core_handle_struct *pudev,
311 usbh_host_struct *puhost,
312 usbh_state_handle_struct *pustate)
313 {
314 /* manage user disconnect operations*/
315 puhost->usr_cb->device_disconnected();
316
317 /* re-initilaize host for new enumeration */
318 usbh_deinit(pudev, puhost,&usbh_state_core);
319 puhost->usr_cb->deinit();
320 puhost->class_deinit(pudev, &puhost->device);
321 usbh_allchannel_dealloc(pudev);
322 scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state);
323 }
324
333 static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev,
334 usbh_host_struct *puhost,
335 usbh_state_handle_struct *pustate)
336 {
337 /* no operation */
338 }
339
346 uint8_t usbh_connected (usb_core_handle_struct *pudev)
347 {
348 pudev->host.connect_status = 1U;
349
350 return 0U;
351 }
352
359 uint8_t usbh_disconnected (usb_core_handle_struct *pudev)
360 {
361 pudev->host.connect_status = 0U;
362
363 return 0U;
364 }
365
372 uint8_t usbh_sof (usb_core_handle_struct *pudev)
373 {
374 /* this callback could be used to implement a scheduler process */
375 return 0U;
376 }
377
385 uint32_t hcd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
386 {
387 pudev->host.connect_status = 0U;
388
389 pudev->host.host_channel[0].endp_mps = 8U;
390
391 usb_core_select(pudev, core_id);
392
393 #ifndef DUAL_ROLE_MODE_ENABLED
394
395 USB_GLOBAL_INT_DISABLE();
396
397 usb_core_init(pudev);
398
399 /* force host mode*/
400 usb_mode_set(pudev, HOST_MODE);
401
402 usb_hostcore_init(pudev);
403
404 USB_GLOBAL_INT_ENABLE();
405
406 #endif
407
408 return 0U;
409 }
410
417 uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev)
418 {
419 return (uint32_t)(pudev->host.connect_status);
420 }
421
429 urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num)
430 {
431 return pudev->host.host_channel[channel_num].urb_state;
432 }
433
441 uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num)
442 {
443 return pudev->host.host_channel[channel_num].xfer_count;
444 }
445
453 usbh_status_enum usbh_deinit(usb_core_handle_struct *pudev,
454 usbh_host_struct *puhost,
455 usbh_state_handle_struct* pustate)
456 {
457 /* software init */
458
459 puhost->control.ep0_size = USB_MAX_EP0_SIZE;
460
461 puhost->device.address = USBH_DEVICE_ADDRESS_DEFAULT;
462 puhost->device.speed = HPRT_PRTSPD_FULL_SPEED;
463
464 usbh_channel_free(pudev, puhost->control.hc_in_num);
465 usbh_channel_free(pudev, puhost->control.hc_out_num);
466
467 scd_init(pustate);
468 scd_table_regist(pustate, host_handle_table, HOST_FSM_ID, HOST_HANDLE_TABLE_SIZE);
469 scd_table_regist(pustate, enum_handle_table, ENUM_FSM_ID, ENUM_HANDLE_TABLE_SIZE);
470 scd_table_regist(pustate, ctrl_handle_table, CTRL_FSM_ID, CTRL_HANDLE_TABLE_SIZE);
471
472 scd_begin(pustate,HOST_FSM_ID);
473 scd_state_move(pustate, HOST_IDLE);
474
475 return USBH_OK;
476 }
477
484 void scd_init(usbh_state_handle_struct* pustate)
485 {
486 /* init the state core */
487 pustate->usbh_current_state = 0U;
488 pustate->usbh_current_state_table = NULL;
489 pustate->usbh_current_state_table_size = 0U;
490
491 pustate->usbh_current_state_stack_top = -1;
492 pustate->stack->state = 0U;
493 pustate->stack->table_size = 0U;
494 pustate->stack->table = NULL;
495
496 pustate->usbh_regist_state_table_num = 0U;
497 pustate->usbh_regist_state_table->table = NULL;
498 pustate->usbh_regist_state_table->table_size = 0U;
499 pustate->usbh_regist_state_table->id = 0U;
500
501 /* init the control and the enumeration polling handle flag */
502 ctrl_polling_handle_flag = 0U;
503 enum_polling_handle_flag = 0U;
504 }
505
515 void scd_table_regist (usbh_state_handle_struct* pustate,
516 state_table_struct* pstate_table,
517 uint8_t table_id,
518 uint8_t current_table_size)
519 {
520 usbh_state_regist_table_struct *cur_state_reg_table;
521
522 cur_state_reg_table = &pustate->usbh_regist_state_table[pustate->usbh_regist_state_table_num];
523
524 cur_state_reg_table->id = table_id;
525 cur_state_reg_table->table = pstate_table;
526 cur_state_reg_table->table_size = current_table_size;
527
528 pustate->usbh_regist_state_table_num++;
529 }
530
538 void scd_begin(usbh_state_handle_struct* pustate, uint8_t table_id)
539 {
540 uint8_t i = 0U, table_num = pustate->usbh_regist_state_table_num;
541 usbh_state_regist_table_struct *cur_state_reg_table;
542
543 for (i = 0U; i < table_num; i++) {
544 cur_state_reg_table = &pustate->usbh_regist_state_table[i];
545
546 if (table_id == cur_state_reg_table->id) {
547 pustate->usbh_current_state_table = cur_state_reg_table->table;
548 pustate->usbh_current_state_table_size = cur_state_reg_table->table_size;
549 break;
550 }
551 }
552 }
553
561 void scd_state_move(usbh_state_handle_struct* pustate, uint8_t state)
562 {
563 pustate->usbh_current_state = state;
564 }
565
576 usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev,
577 usbh_host_struct *puhost,
578 usbh_state_handle_struct* pustate,
579 uint8_t event,
580 uint8_t state)
581 {
582 uint8_t i = 0U;
583 ACT_FUN event_act_fun = NULL;
584 state_table_struct *backup_state_t = pustate->usbh_current_state_table;
585 state_table_struct *executive_state_table = pustate->usbh_current_state_table;
586
587 /* look up the table to find the action function */
588 for (i = 0U; i < pustate->usbh_current_state_table_size; i++) {
589 if (state == executive_state_table->cur_state) {
590 if (event == executive_state_table->cur_event) {
591 state = executive_state_table->next_state;
592 event_act_fun = executive_state_table->event_action_fun;
593 break;
594 } else {
595 executive_state_table++;
596 }
597 } else {
598 executive_state_table++;
599 }
600 }
601
602 pustate->usbh_current_state_table = backup_state_t;
603
604 /* if the action function is not NULL, execute the action function */
605 if (event_act_fun) {
606 if (event_act_fun == &only_state_move) {
607 pustate->usbh_current_state = state;
608 } else {
609 return event_act_fun(pudev, puhost, pustate);
610 }
611 }
612
613 return USBH_BUSY;
614 }
615
622 void scd_table_push(usbh_state_handle_struct* pustate)
623 {
624 usbh_state_stack_struct *top_state_element;
625
626 if (pustate->usbh_current_state_stack_top < MAX_USBH_STATE_STACK_DEEP) {
627 pustate->usbh_current_state_stack_top++;
628
629 top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top];
630
631 /* put the current state table into the state stack */
632 top_state_element->state = pustate->usbh_current_state;
633 top_state_element->table = pustate->usbh_current_state_table;
634 top_state_element->table_size = pustate->usbh_current_state_table_size;
635 }
636 }
637
644 void scd_table_pop (usbh_state_handle_struct* pustate)
645 {
646 usbh_state_stack_struct *top_state_element;
647
648 top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top];
649
650 if (pustate->usbh_current_state_stack_top > -1) {
651 /* get the current state table from the state stack */
652 pustate->usbh_current_state = top_state_element->state;
653 pustate->usbh_current_state_table = top_state_element->table;
654 pustate->usbh_current_state_table_size = top_state_element->table_size;
655 pustate->usbh_current_state_stack_top--;
656 }
657 }
666 static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
667 {
668 return class_polling_cb.class_req_polling(pudev, puhost, pustate);
669 }
670
679 static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
680 {
681 return class_polling_cb.class_polling(pudev, puhost, pustate);
682 }
683
692 usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
693 {
694 return USBH_OK;
695 }
696
705 usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
706 {
707 scd_table_pop((usbh_state_handle_struct *)pustate);
708
709 return USBH_OK;
710 }
usbh_hcd_int_fops
usbh_hcd_int_cb_struct * usbh_hcd_int_fops
Definition: usbh_core.c:33
usbh_state_handle_struct::usbh_current_state
uint8_t usbh_current_state
Definition: usbh_core.h:229
HOST_EVENT_IDLE
Definition: usbh_core.h:75
usb_core_select
usb_status_enum usb_core_select(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize core parameters
Definition: usb_core.c:125
usbh_core.h
header file for usbh_core.c
usbh_std.h
header file for usbh_std.c
HOST_MODE
#define HOST_MODE
Definition: usb_defines.h:48
usb_mode_set
usb_status_enum usb_mode_set(usb_core_handle_struct *pudev, uint8_t mode)
set operation mode (host or device)
Definition: usb_core.c:266
usbh_state_handle_struct
Definition: usbh_core.h:227
HOST_EVENT_CLASS_REQ
Definition: usbh_core.h:71
enum_polling_handle_flag
uint8_t enum_polling_handle_flag
Definition: usbh_std.c:19
hcd_is_device_connected
uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev)
check if the device is connected.
Definition: usbh_core.c:417
ENUM_FSM_ID
#define ENUM_FSM_ID
Definition: usbh_core.h:39
usbh_state_stack_struct::state
uint8_t state
Definition: usbh_core.h:213
usbh_channel_free
uint8_t usbh_channel_free(usb_core_handle_struct *pudev, uint8_t index)
free the usb host channel
Definition: usbh_hcs.c:114
host_handle_table
state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE]
Definition: usbh_core.c:66
HOST_EVENT_CLASS
Definition: usbh_core.h:72
state_table_struct::event_action_fun
ACT_FUN event_action_fun
Definition: usbh_core.h:207
urb_state_enum
urb_state_enum
Definition: usb_core.h:48
usbh_user_callback_struct::user_input
usbh_user_status_enum(* user_input)(void)
Definition: usbh_core.h:170
CTRL_FSM_ID
#define CTRL_FSM_ID
Definition: usbh_core.h:41
HOST_EVENT_ENUM
Definition: usbh_core.h:69
usbh_ctrl_struct::hc_in_num
uint8_t hc_in_num
Definition: usbh_core.h:127
scd_event_handle
usbh_status_enum scd_event_handle(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate, uint8_t event, uint8_t state)
state core driver event handle
Definition: usbh_core.c:576
usbh_state_handle_struct::usbh_current_state_table
state_table_struct * usbh_current_state_table
Definition: usbh_core.h:231
scd_table_push
void scd_table_push(usbh_state_handle_struct *pustate)
state core driver table push
Definition: usbh_core.c:622
HOST_CLASS
Definition: usbh_core.h:59
HOST_ERROR
Definition: usbh_core.h:62
scd_state_move
void scd_state_move(usbh_state_handle_struct *pustate, uint8_t state)
state core driver move state
Definition: usbh_core.c:561
HOST_DEV_DETACHED
Definition: usbh_core.h:55
usbh_user_callback_struct::device_connected
void(* device_connected)(void)
Definition: usbh_core.h:153
USB_EPTYPE_CTRL
#define USB_EPTYPE_CTRL
Definition: usb_defines.h:51
usbh_host_struct::class_deinit
void(* class_deinit)(usb_core_handle_struct *pudev, void *phost)
Definition: usbh_core.h:195
HOST_EVENT_ERROR
Definition: usbh_core.h:73
usbh_status_enum
usbh_status_enum
Definition: usbh_core.h:106
scd_table_regist
void scd_table_regist(usbh_state_handle_struct *pustate, state_table_struct *pstate_table, uint8_t table_id, uint8_t current_table_size)
state core driver table regist
Definition: usbh_core.c:515
usbh_host_struct
Definition: usbh_core.h:188
usbh_ctrl_struct::ep0_size
uint8_t ep0_size
Definition: usbh_core.h:129
usbh_connected
uint8_t usbh_connected(usb_core_handle_struct *pudev)
usb connect callback function from the interrupt.
Definition: usbh_core.c:346
HOST_DEV_ATTACHED
Definition: usbh_core.h:54
scd_begin
void scd_begin(usbh_state_handle_struct *pustate, uint8_t table_id)
state core driver begin
Definition: usbh_core.c:538
scd_init
void scd_init(usbh_state_handle_struct *pustate)
state core driver init
Definition: usbh_core.c:484
CTRL_HANDLE_TABLE_SIZE
#define CTRL_HANDLE_TABLE_SIZE
Definition: usbh_ctrl.h:18
usbh_state_handle_struct::usbh_regist_state_table
usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]
Definition: usbh_core.h:236
usb_core_handle_struct::mdelay
void(* mdelay)(const uint32_t msec)
Definition: usb_core.h:217
usbh_host_struct::usr_cb
usbh_user_callback_struct * usr_cb
Definition: usbh_core.h:193
usbh_user_callback_struct::enumeration_finish
void(* enumeration_finish)(void)
Definition: usbh_core.h:169
usbh_state_handle_struct::usbh_regist_state_table_num
uint8_t usbh_regist_state_table_num
Definition: usbh_core.h:237
usbh_state_regist_table_struct::table_size
uint8_t table_size
Definition: usbh_core.h:223
usbh_device_struct::speed
uint8_t speed
Definition: usbh_core.h:141
hcd_init
uint32_t hcd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id)
initialize the host portion of the driver.
Definition: usbh_core.c:385
usbh_ctrl.h
header file for usbh_ctrl.c
hcd_urb_state_get
urb_state_enum hcd_urb_state_get(usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate
Definition: usbh_core.c:429
usbh_state_regist_table_struct::id
uint8_t id
Definition: usbh_core.h:221
state_table_struct::next_state
uint8_t next_state
Definition: usbh_core.h:206
HOST_FSM_ID
#define HOST_FSM_ID
Definition: usbh_core.h:38
HOST_ENUMERATION
Definition: usbh_core.h:57
usbh_deinit
usbh_status_enum usbh_deinit(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
de-initialize host
Definition: usbh_core.c:453
scd_table_pop
void scd_table_pop(usbh_state_handle_struct *pustate)
state core driver table pop
Definition: usbh_core.c:644
usbh_hcd_int_cb
usbh_hcd_int_cb_struct usbh_hcd_int_cb
Definition: usbh_core.c:26
hcd_xfer_count_get
uint32_t hcd_xfer_count_get(usb_core_handle_struct *pudev, uint8_t channel_num)
this function returns the last URBstate
Definition: usbh_core.c:441
USBH_USER_RESP_OK
Definition: usbh_core.h:121
usbh_state_stack_struct
Definition: usbh_core.h:211
state_table_struct
Definition: usbh_core.h:202
usbh_state_handle_struct::stack
usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]
Definition: usbh_core.h:233
usbh_int.h
USB host mode interrupt handler header file.
usb_core.h
USB core driver header file.
state_table_struct::cur_state
uint8_t cur_state
Definition: usbh_core.h:204
usbh_state_stack_struct::table
state_table_struct * table
Definition: usbh_core.h:214
ACT_FUN
usbh_status_enum(* ACT_FUN)(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
Definition: usbh_core.h:199
usbh_user_callback_struct::device_disconnected
void(* device_disconnected)(void)
Definition: usbh_core.h:155
usbh_hcs.h
header file for usbh_hcs.c
usbh_sof
uint8_t usbh_sof(usb_core_handle_struct *pudev)
usb sof callback function from the interrupt.
Definition: usbh_core.c:372
usbh_device_struct::address
uint8_t address
Definition: usbh_core.h:140
ctrl_polling_handle_flag
uint8_t ctrl_polling_handle_flag
Definition: usbh_ctrl.c:16
host_state_handle
void(* host_state_handle[])(usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate)
Definition: usbh_core.c:51
usbh_state_regist_table_struct::table
state_table_struct * table
Definition: usbh_core.h:222
USB_GLOBAL_INT_DISABLE
#define USB_GLOBAL_INT_DISABLE()
Definition: usb_regs.h:545
usb_core_handle_struct
Definition: usb_core.h:200
HOST_EVENT_ATTACHED
Definition: usbh_core.h:68
usbh_state_core
usbh_state_handle_struct usbh_state_core
ctrl_handle_table
state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]
Definition: usbh_ctrl.c:46
usbh_state_handle_struct::usbh_current_state_stack_top
int8_t usbh_current_state_stack_top
Definition: usbh_core.h:234
usbh_state_handle_struct::usbh_current_state_table_size
uint8_t usbh_current_state_table_size
Definition: usbh_core.h:230
HPRT_PRTSPD_FULL_SPEED
#define HPRT_PRTSPD_FULL_SPEED
Definition: usb_defines.h:74
USB_MAX_EP0_SIZE
#define USB_MAX_EP0_SIZE
Definition: usb_core.h:19
usbh_host_struct::class_init
usbh_status_enum(* class_init)(usb_core_handle_struct *pudev, void *phost)
Definition: usbh_core.h:194
usbh_state_stack_struct::table_size
uint8_t table_size
Definition: usbh_core.h:215
usbh_host_struct::device
usbh_device_struct device
Definition: usbh_core.h:192
USBH_OK
Definition: usbh_core.h:108
NULL
#define NULL
Definition: usb_defines.h:18
USB_GLOBAL_INT_ENABLE
#define USB_GLOBAL_INT_ENABLE()
Definition: usb_regs.h:542
goto_up_state_fun
usbh_status_enum goto_up_state_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function to the up state
Definition: usbh_core.c:705
usb_core_init
usb_status_enum usb_core_init(usb_core_handle_struct *pudev)
initializes the USB controller registers and prepares the core device mode or host mode operation ...
Definition: usb_core.c:167
usbh_user_callback_struct::deinit
void(* deinit)(void)
Definition: usbh_core.h:152
class_polling_cb
class_polling_fun_cb_struct class_polling_cb
HOST_CLASS_REQUEST
Definition: usbh_core.h:58
usbh_hcd_int_cb_struct
Definition: usbh_int.h:17
usbh_allchannel_dealloc
uint8_t usbh_allchannel_dealloc(usb_core_handle_struct *pudev)
free all usb host channel
Definition: usbh_hcs.c:129
usbh_host_struct::control
usbh_ctrl_struct control
Definition: usbh_core.h:191
ENUM_HANDLE_TABLE_SIZE
#define ENUM_HANDLE_TABLE_SIZE
Definition: usbh_std.h:23
host_state_polling_fun
usbh_status_enum host_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of HOST state
Definition: usbh_core.c:88
MAX_USBH_STATE_STACK_DEEP
#define MAX_USBH_STATE_STACK_DEEP
Definition: usbh_core.h:35
usbh_user_callback_struct::device_reset
void(* device_reset)(void)
Definition: usbh_core.h:154
HOST_USER_INPUT
Definition: usbh_core.h:60
enum_handle_table
state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]
Definition: usbh_std.c:48
usbh_state_regist_table_struct
Definition: usbh_core.h:219
USB_CURRENT_SPEED_GET
#define USB_CURRENT_SPEED_GET()
Definition: usb_regs.h:617
HOST_IDLE
Definition: usbh_core.h:53
usbh_disconnected
uint8_t usbh_disconnected(usb_core_handle_struct *pudev)
usb disconnect callback function from the interrupt.
Definition: usbh_core.c:359
USBH_DEVICE_ADDRESS_DEFAULT
#define USBH_DEVICE_ADDRESS_DEFAULT
Definition: usbh_core.h:24
usbh_user_callback_struct::device_speed_detected
void(* device_speed_detected)(uint8_t device_speed)
Definition: usbh_core.h:157
usbh_ctrl_struct::hc_out_num
uint8_t hc_out_num
Definition: usbh_core.h:128
HOST_HANDLE_TABLE_SIZE
#define HOST_HANDLE_TABLE_SIZE
Definition: usbh_core.h:48
usbh_channel_open
uint8_t usbh_channel_open(usb_core_handle_struct *pudev, uint8_t channel_num, uint8_t dev_addr, uint8_t dev_speed, uint8_t ep_type, uint16_t ep_mps)
open a channel
Definition: usbh_hcs.c:27
usbh_channel_alloc
uint8_t usbh_channel_alloc(usb_core_handle_struct *pudev, uint8_t ep_addr)
allocate a new channel for the pipe
Definition: usbh_hcs.c:96
enum_state_polling_fun
usbh_status_enum enum_state_polling_fun(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the polling function of enumeration state
Definition: usbh_std.c:71
USBH_BUSY
Definition: usbh_core.h:109
state_table_struct::cur_event
uint8_t cur_event
Definition: usbh_core.h:205
usb_core_id_enum
usb_core_id_enum
Definition: usb_defines.h:86
only_state_move
usbh_status_enum only_state_move(usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate)
the function is only used to state move
Definition: usbh_core.c:692
HOST_EVENT_USER_INPUT
Definition: usbh_core.h:70
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_usbfs_driver/Include/usbd_int.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_usbfs_driver
  • Include
usbd_int.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef USBD_INT_H
13 #define USBD_INT_H
14
15 #include "usbd_core.h"
16
17 typedef struct
18 {
19 uint8_t (*SOF) (usb_core_handle_struct *pudev);
20 }usbd_int_cb_struct;
21
22 extern usbd_int_cb_struct *usbd_int_fops;
23
24 /* function declarations */
25 /* USB device-mode interrupts global service routine handler */
26 uint32_t usbd_isr (usb_core_handle_struct *pudev);
27
28 #endif /* USBD_INT_H */
29
usbd_int_fops
usbd_int_cb_struct * usbd_int_fops
usbd_isr
uint32_t usbd_isr(usb_core_handle_struct *pudev)
USB device-mode interrupts global service routine handler.
Definition: usbd_int.c:57
usb_core_handle_struct
Definition: usb_core.h:200
usbd_int_cb_struct
Definition: usbd_int.h:17
usbd_core.h
USB device mode core driver header file.
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_cmp.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_cmp.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_CMP_H
13 #define GD32F3X0_CMP_H
14
15 #include "gd32f3x0.h"
16
17 /* CMP definitions */
18 #define CMP CMP_BASE
20 /* registers definitions */
21 #define CMP_CS REG32((CMP) + 0x00U)
23 /* CMP_CS bits definitions */
24 #define CMP_CS_CMP0EN BIT(0)
25 #define CMP_CS_CMP0SW BIT(1)
26 #define CMP_CS_CMP0M BITS(2,3)
27 #define CMP_CS_CMP0MSEL BITS(4,6)
28 #define CMP_CS_CMP0OSEL BITS(8,10)
29 #define CMP_CS_CMP0PL BIT(11)
30 #define CMP_CS_CMP0HST BITS(12,13)
31 #define CMP_CS_CMP0O BIT(14)
32 #define CMP_CS_CMP0LK BIT(15)
33 #define CMP_CS_CMP1EN BIT(16)
34 #define CMP_CS_CMP1M BITS(18,19)
35 #define CMP_CS_CMP1MSEL BITS(20,22)
36 #define CMP_CS_WNDEN BIT(23)
37 #define CMP_CS_CMP1OSEL BITS(24,26)
38 #define CMP_CS_CMP1PL BIT(27)
39 #define CMP_CS_CMP1HST BITS(28,29)
40 #define CMP_CS_CMP1O BIT(30)
41 #define CMP_CS_CMP1LK BIT(31)
43 /* consts definitions */
44 /* operating mode */
45 typedef enum{
46 CMP_HIGHSPEED = 0,
47 CMP_MIDDLESPEED,
48 CMP_LOWSPEED,
49 CMP_VERYLOWSPEED
50 }operating_mode_enum;
51
52 /* inverting input */
53 typedef enum{
54 CMP_1_4VREFINT = 0,
55 CMP_1_2VREFINT,
56 CMP_3_4VREFINT,
57 CMP_VREFINT,
58 CMP_DAC,
59 CMP_PA5,
60 CMP_PA_0_2
61 }inverting_input_enum;
62
63 /* hysteresis */
64 typedef enum{
65 CMP_HYSTERESIS_NO = 0,
66 CMP_HYSTERESIS_LOW,
67 CMP_HYSTERESIS_MIDDLE,
68 CMP_HYSTERESIS_HIGH
69 }cmp_hysteresis_enum;
70
71 /* output */
72 typedef enum{
73 CMP_OUTPUT_NONE = 0,
74 CMP_OUTPUT_TIMER0BKIN,
75 CMP_OUTPUT_TIMER0IC0,
76 CMP_OUTPUT_TIMER0OCPRECLR,
77 CMP_OUTPUT_TIMER1IC3,
78 CMP_OUTPUT_TIMER1OCPRECLR,
79 CMP_OUTPUT_TIMER2IC0,
80 CMP_OUTPUT_TIMER2OCPRECLR
81 }cmp_output_enum;
82
83 /* CMP0 mode */
84 #define CS_CMP0M(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
85 #define CS_CMP0M_HIGHSPEED CS_CMP0M(0)
86 #define CS_CMP0M_MIDDLESPEED CS_CMP0M(1)
87 #define CS_CMP0M_LOWSPEED CS_CMP0M(2)
88 #define CS_CMP0M_VERYLOWSPEED CS_CMP0M(3)
90 /* comparator 0 inverting input */
91 #define CS_CMP0MSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
92 #define CS_CMP0MSEL_1_4VREFINT CS_CMP0MSEL(0)
93 #define CS_CMP0MSEL_1_2VREFINT CS_CMP0MSEL(1)
94 #define CS_CMP0MSEL_3_4VREFINT CS_CMP0MSEL(2)
95 #define CS_CMP0MSEL_VREFINT CS_CMP0MSEL(3)
96 #define CS_CMP0MSEL_DAC CS_CMP0MSEL(4)
97 #define CS_CMP0MSEL_PA5 CS_CMP0MSEL(5)
98 #define CS_CMP0MSEL_PA0 CS_CMP0MSEL(6)
100 /* CMP0 output */
101 #define CS_CMP0OSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
102 #define CS_CMP0OSEL_OUTPUT_NONE CS_CMP0OSEL(0)
103 #define CS_CMP0OSEL_OUTPUT_TIMER0BKIN CS_CMP0OSEL(1)
104 #define CS_CMP0OSEL_OUTPUT_TIMER0IC0 CS_CMP0OSEL(2)
105 #define CS_CMP0OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP0OSEL(3)
106 #define CS_CMP0OSEL_OUTPUT_TIMER1IC3 CS_CMP0OSEL(4)
107 #define CS_CMP0OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP0OSEL(5)
108 #define CS_CMP0OSEL_OUTPUT_TIMER2IC0 CS_CMP0OSEL(6)
109 #define CS_CMP0OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP0OSEL(7)
111 /* CMP0 hysteresis */
112 #define CS_CMP0HST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
113 #define CS_CMP0HST_HYSTERESIS_NO CS_CMP0HST(0)
114 #define CS_CMP0HST_HYSTERESIS_LOW CS_CMP0HST(1)
115 #define CS_CMP0HST_HYSTERESIS_MIDDLE CS_CMP0HST(2)
116 #define CS_CMP0HST_HYSTERESIS_HIGH CS_CMP0HST(3)
118 /* CMP1 mode */
119 #define CS_CMP1M(regval) (BITS(18,19) & ((uint32_t)(regval) << 18))
120 #define CS_CMP1M_HIGHSPEED CS_CMP1M(0)
121 #define CS_CMP1M_MIDDLESPEED CS_CMP1M(1)
122 #define CS_CMP1M_LOWSPEED CS_CMP1M(2)
123 #define CS_CMP1M_VERYLOWSPEED CS_CMP1M(3)
125 /* CMP1 inverting input */
126 #define CS_CMP1MSEL(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
127 #define CS_CMP1MSEL_1_4VREFINT CS_CMP1MSEL(0)
128 #define CS_CMP1MSEL_1_2VREFINT CS_CMP1MSEL(1)
129 #define CS_CMP1MSEL_3_4VREFINT CS_CMP1MSEL(2)
130 #define CS_CMP1MSEL_VREFINT CS_CMP1MSEL(3)
131 #define CS_CMP1MSEL_DAC CS_CMP1MSEL(4)
132 #define CS_CMP1MSEL_PA5 CS_CMP1MSEL(5)
133 #define CS_CMP1MSEL_PA2 CS_CMP1MSEL(6)
135 /* CMP1 output */
136 #define CS_CMP1OSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
137 #define CS_CMP1OSEL_OUTPUT_NONE CS_CMP1OSEL(0)
138 #define CS_CMP1OSEL_OUTPUT_TIMER0BKIN CS_CMP1OSEL(1)
139 #define CS_CMP1OSEL_OUTPUT_TIMER0IC0 CS_CMP1OSEL(2)
140 #define CS_CMP1OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP1OSEL(3)
141 #define CS_CMP1OSEL_OUTPUT_TIMER1IC3 CS_CMP1OSEL(4)
142 #define CS_CMP1OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP1OSEL(5)
143 #define CS_CMP1OSEL_OUTPUT_TIMER2IC0 CS_CMP1OSEL(6)
144 #define CS_CMP1OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP1OSEL(7)
146 /* CMP1 hysteresis */
147 #define CS_CMP1HST(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
148 #define CS_CMP1HST_HSTHYSTERESIS_NO CS_CMP1HST(0)
149 #define CS_CMP1HST_HYSTERESIS_LOW CS_CMP1HST(1)
150 #define CS_CMP1HST_HYSTERESIS_MIDDLE CS_CMP1HST(2)
151 #define CS_CMP1HST_HYSTERESIS_HIGH CS_CMP1HST(3)
153 /* comparator x definitions */
154 #define CMP0 ((uint32_t)0x00000000)
155 #define CMP1 ((uint32_t)0x00000010)
157 /* comparator output level */
158 #define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001)
159 #define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000)
161 /* output polarity of comparator */
162 #define CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001)
163 #define CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000)
165 /* function declarations */
166
167 /* initialization functions */
168 /* CMP deinit */
169 void cmp_deinit(void);
170 /* CMP mode init */
171 void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis);
172 /* CMP output init */
173 void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity);
174
175 /* enable functions */
176 /* enable CMP */
177 void cmp_enable(uint32_t cmp_periph);
178 /* disable CMP */
179 void cmp_disable(uint32_t cmp_periph);
180 /* enable CMP switch */
181 void cmp_switch_enable(void);
182 /* disable CMP switch */
183 void cmp_switch_disable(void);
184 /* enable the window mode */
185 void cmp_window_enable(void);
186 /* disable the window mode */
187 void cmp_window_disable(void);
188 /* lock the CMP */
189 void cmp_lock_enable(uint32_t cmp_periph);
190 /* unlock the CMP */
191 void cmp_lock_disable(uint32_t cmp_periph);
192
193 /* output functions */
194 /* get output level */
195 uint32_t cmp_output_level_get(uint32_t cmp_periph);
196
197 #endif /* GD32F3X0_CMP_H */
CMP_HYSTERESIS_MIDDLE
Definition: gd32f3x0_cmp.h:67
cmp_window_disable
void cmp_window_disable(void)
disable the window mode
Definition: gd32f3x0_cmp.c:202
CMP_HIGHSPEED
Definition: gd32f3x0_cmp.h:46
CMP_VREFINT
Definition: gd32f3x0_cmp.h:57
CMP_PA5
Definition: gd32f3x0_cmp.h:59
cmp_lock_enable
void cmp_lock_enable(uint32_t cmp_periph)
lock the comparator
Definition: gd32f3x0_cmp.c:215
CMP_OUTPUT_NONE
Definition: gd32f3x0_cmp.h:73
CMP_HYSTERESIS_LOW
Definition: gd32f3x0_cmp.h:66
CMP_VERYLOWSPEED
Definition: gd32f3x0_cmp.h:49
operating_mode_enum
operating_mode_enum
Definition: gd32f3x0_cmp.h:45
cmp_mode_init
void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis)
initialize comparator mode
Definition: gd32f3x0_cmp.c:51
CMP_DAC
Definition: gd32f3x0_cmp.h:58
cmp_output_init
void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity)
initialize comparator output
Definition: gd32f3x0_cmp.c:82
CMP_OUTPUT_TIMER2IC0
Definition: gd32f3x0_cmp.h:79
CMP_OUTPUT_TIMER1IC3
Definition: gd32f3x0_cmp.h:77
CMP_OUTPUT_TIMER0IC0
Definition: gd32f3x0_cmp.h:75
CMP_HYSTERESIS_NO
Definition: gd32f3x0_cmp.h:65
CMP_OUTPUT_TIMER1OCPRECLR
Definition: gd32f3x0_cmp.h:78
CMP_1_2VREFINT
Definition: gd32f3x0_cmp.h:55
CMP_OUTPUT_TIMER0OCPRECLR
Definition: gd32f3x0_cmp.h:76
CMP_OUTPUT_TIMER0BKIN
Definition: gd32f3x0_cmp.h:74
cmp_switch_enable
void cmp_switch_enable(void)
enable comparator switch
Definition: gd32f3x0_cmp.c:144
cmp_output_level_get
uint32_t cmp_output_level_get(uint32_t cmp_periph)
get output level
Definition: gd32f3x0_cmp.c:168
cmp_deinit
void cmp_deinit(void)
deinitialize comparator
Definition: gd32f3x0_cmp.c:20
CMP_1_4VREFINT
Definition: gd32f3x0_cmp.h:54
CMP_HYSTERESIS_HIGH
Definition: gd32f3x0_cmp.h:68
cmp_switch_disable
void cmp_switch_disable(void)
disable comparator switch
Definition: gd32f3x0_cmp.c:155
CMP_LOWSPEED
Definition: gd32f3x0_cmp.h:48
CMP_OUTPUT_TIMER2OCPRECLR
Definition: gd32f3x0_cmp.h:80
cmp_hysteresis_enum
cmp_hysteresis_enum
Definition: gd32f3x0_cmp.h:64
CMP_3_4VREFINT
Definition: gd32f3x0_cmp.h:56
cmp_window_enable
void cmp_window_enable(void)
enable the window mode
Definition: gd32f3x0_cmp.c:191
inverting_input_enum
inverting_input_enum
Definition: gd32f3x0_cmp.h:53
cmp_output_enum
cmp_output_enum
Definition: gd32f3x0_cmp.h:72
CMP_MIDDLESPEED
Definition: gd32f3x0_cmp.h:47
CMP_PA_0_2
Definition: gd32f3x0_cmp.h:60
cmp_enable
void cmp_enable(uint32_t cmp_periph)
enable comparator
Definition: gd32f3x0_cmp.c:112
cmp_lock_disable
void cmp_lock_disable(uint32_t cmp_periph)
unlock the comparator
Definition: gd32f3x0_cmp.c:232
cmp_disable
void cmp_disable(uint32_t cmp_periph)
disable comparator
Definition: gd32f3x0_cmp.c:129
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_adc.h Source File

  • E:
  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_adc.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_ADC_H
13 #define GD32F3X0_ADC_H
14
15 #include "gd32f3x0.h"
16
17 /* ADC definitions */
18 #define ADC ADC_BASE
19
20 /* registers definitions */
21 #define ADC_STAT REG32(ADC + 0x00U)
22 #define ADC_CTL0 REG32(ADC + 0x04U)
23 #define ADC_CTL1 REG32(ADC + 0x08U)
24 #define ADC_SAMPT0 REG32(ADC + 0x0CU)
25 #define ADC_SAMPT1 REG32(ADC + 0x10U)
26 #define ADC_IOFF0 REG32(ADC + 0x14U)
27 #define ADC_IOFF1 REG32(ADC + 0x18U)
28 #define ADC_IOFF2 REG32(ADC + 0x1CU)
29 #define ADC_IOFF3 REG32(ADC + 0x20U)
30 #define ADC_WDHT REG32(ADC + 0x24U)
31 #define ADC_WDLT REG32(ADC + 0x28U)
32 #define ADC_RSQ0 REG32(ADC + 0x2CU)
33 #define ADC_RSQ1 REG32(ADC + 0x30U)
34 #define ADC_RSQ2 REG32(ADC + 0x34U)
35 #define ADC_ISQ REG32(ADC + 0x38U)
36 #define ADC_IDATA0 REG32(ADC + 0x3CU)
37 #define ADC_IDATA1 REG32(ADC + 0x40U)
38 #define ADC_IDATA2 REG32(ADC + 0x44U)
39 #define ADC_IDATA3 REG32(ADC + 0x48U)
40 #define ADC_RDATA REG32(ADC + 0x4CU)
41 #define ADC_OVSAMPCTL REG32(ADC + 0x80U)
43 /* bits definitions */
44 /* ADC_STAT */
45 #define ADC_STAT_WDE BIT(0)
46 #define ADC_STAT_EOC BIT(1)
47 #define ADC_STAT_EOIC BIT(2)
48 #define ADC_STAT_STIC BIT(3)
49 #define ADC_STAT_STRC BIT(4)
51 /* ADC_CTL0 */
52 #define ADC_CTL0_WDCHSEL BITS(0,4)
53 #define ADC_CTL0_EOCIE BIT(5)
54 #define ADC_CTL0_WDEIE BIT(6)
55 #define ADC_CTL0_EOICIE BIT(7)
56 #define ADC_CTL0_SM BIT(8)
57 #define ADC_CTL0_WDSC BIT(9)
58 #define ADC_CTL0_ICA BIT(10)
59 #define ADC_CTL0_DISRC BIT(11)
60 #define ADC_CTL0_DISIC BIT(12)
61 #define ADC_CTL0_DISNUM BITS(13,15)
62 #define ADC_CTL0_IWDEN BIT(22)
63 #define ADC_CTL0_RWDEN BIT(23)
64 #define ADC_CTL0_DRES BITS(24,25)
66 /* ADC_CTL1 */
67 #define ADC_CTL1_ADCON BIT(0)
68 #define ADC_CTL1_CTN BIT(1)
69 #define ADC_CTL1_CLB BIT(2)
70 #define ADC_CTL1_RSTCLB BIT(3)
71 #define ADC_CTL1_DMA BIT(8)
72 #define ADC_CTL1_DAL BIT(11)
73 #define ADC_CTL1_ETSIC BITS(12,14)
74 #define ADC_CTL1_ETEIC BIT(15)
75 #define ADC_CTL1_ETSRC BITS(17,19)
76 #define ADC_CTL1_ETERC BIT(20)
77 #define ADC_CTL1_SWICST BIT(21)
78 #define ADC_CTL1_SWRCST BIT(22)
79 #define ADC_CTL1_TSVREN BIT(23)
80 #define ADC_CTL1_VBETEN BIT(24)
82 /* ADC_SAMPTx x=0,1 */
83 #define ADC_SAMPTX_SPTN BITS(0,2)
85 /* ADC_IOFFx x=0..3 */
86 #define ADC_IOFFX_IOFF BITS(0,11)
88 /* ADC_WDHT */
89 #define ADC_WDHT_WDHT BITS(0,11)
91 /* ADC_WDLT */
92 #define ADC_WDLT_WDLT BITS(0,11)
94 /* ADC_RSQx x=0..2 */
95 #define ADC_RSQX_RSQN BITS(0,4)
96 #define ADC_RSQ0_RL BITS(20,23)
98 /* ADC_ISQ */
99 #define ADC_ISQ_ISQN BITS(0,4)
100 #define ADC_ISQ_IL BITS(20,21)
102 /* ADC_IDATAx x=0..3*/
103 #define ADC_IDATAX_IDATAN BITS(0,15)
105 /* ADC_RDATA */
106 #define ADC_RDATA_RDATA BITS(0,15)
108 /* ADC_OVSAMPCTL */
109 #define ADC_OVSAMPCTL_OVSEN BIT(0)
110 #define ADC_OVSAMPCTL_OVSR BITS(2,4)
111 #define ADC_OVSAMPCTL_OVSS BITS(5,8)
112 #define ADC_OVSAMPCTL_TOVS BIT(9)
114 /* constants definitions */
115 /* ADC flag definitions */
116 #define ADC_FLAG_WDE ADC_STAT_WDE
117 #define ADC_FLAG_EOC ADC_STAT_EOC
118 #define ADC_FLAG_EOIC ADC_STAT_EOIC
119 #define ADC_FLAG_STIC ADC_STAT_STIC
120 #define ADC_FLAG_STRC ADC_STAT_STRC
122 /* adc_ctl0 register value */
123 #define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13))
125 /* ADC special function */
126 #define ADC_SCAN_MODE ADC_CTL0_SM
127 #define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA
128 #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN
130 /* ADC data alignment */
131 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
132 #define ADC_DATAALIGN_LEFT ADC_CTL1_DAL
134 /* external trigger select for regular channel */
135 #define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
136 #define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0)
137 #define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1)
138 #define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2)
139 #define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3)
140 #define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4)
141 #define ADC_EXTTRIG_REGULAR_T14_CH1 CTL1_ETSRC(5)
142 #define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6)
143 #define ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7)
145 /* external trigger select for inserted channel */
146 #define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12))
147 #define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0)
148 #define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1)
149 #define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2)
150 #define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3)
151 #define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4)
152 #define ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5)
153 #define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6)
154 #define ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7)
156 /* adc_samptx register value */
157 #define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
158 #define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0)
159 #define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1)
160 #define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2)
161 #define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3)
162 #define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4)
163 #define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5)
164 #define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6)
165 #define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7)
167 /* ADC data offset for inserted channel x*/
168 #define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
169
170 /* ADC analog watchdog high threshold */
171 #define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
172
173 /* ADC analog watchdog low threshold */
174 #define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
175
176 /* ADC regular channel group length */
177 #define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
178
179 /* ADC inserted channel group length */
180 #define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
181
182 /* ADC resolution definitions */
183 #define CTL0_DRES(regval) (BITS(24,25) & ((regval) << 24))
184 #define ADC_RESOLUTION_12B CTL0_DRES(0)
185 #define ADC_RESOLUTION_10B CTL0_DRES(1)
186 #define ADC_RESOLUTION_8B CTL0_DRES(2)
187 #define ADC_RESOLUTION_6B CTL0_DRES(3)
189 /* ADC oversampling shift */
190 #define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
191 #define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0)
192 #define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1)
193 #define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2)
194 #define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3)
195 #define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4)
196 #define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5)
197 #define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6)
198 #define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7)
199 #define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8)
201 /* ADC oversampling ratio */
202 #define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2))
203 #define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0)
204 #define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1)
205 #define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2)
206 #define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3)
207 #define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4)
208 #define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5)
209 #define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6)
210 #define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7)
212 /* ADC triggered oversampling */
213 #define ADC_OVERSAMPLING_ALL_CONVERT 0U
214 #define ADC_OVERSAMPLING_ONE_CONVERT 1U
216 /* ADC channel group definitions */
217 #define ADC_REGULAR_CHANNEL ((uint8_t)0x01U)
218 #define ADC_INSERTED_CHANNEL ((uint8_t)0x02U)
219 #define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U)
220 #define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U)
222 /* ADC inserted channel definitions */
223 #define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U)
224 #define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U)
225 #define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U)
226 #define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U)
228 /* ADC channel definitions */
229 #define ADC_CHANNEL_0 ((uint8_t)0x00U)
230 #define ADC_CHANNEL_1 ((uint8_t)0x01U)
231 #define ADC_CHANNEL_2 ((uint8_t)0x02U)
232 #define ADC_CHANNEL_3 ((uint8_t)0x03U)
233 #define ADC_CHANNEL_4 ((uint8_t)0x04U)
234 #define ADC_CHANNEL_5 ((uint8_t)0x05U)
235 #define ADC_CHANNEL_6 ((uint8_t)0x06U)
236 #define ADC_CHANNEL_7 ((uint8_t)0x07U)
237 #define ADC_CHANNEL_8 ((uint8_t)0x08U)
238 #define ADC_CHANNEL_9 ((uint8_t)0x09U)
239 #define ADC_CHANNEL_10 ((uint8_t)0x0AU)
240 #define ADC_CHANNEL_11 ((uint8_t)0x0BU)
241 #define ADC_CHANNEL_12 ((uint8_t)0x0CU)
242 #define ADC_CHANNEL_13 ((uint8_t)0x0DU)
243 #define ADC_CHANNEL_14 ((uint8_t)0x0EU)
244 #define ADC_CHANNEL_15 ((uint8_t)0x0FU)
245 #define ADC_CHANNEL_16 ((uint8_t)0x10U)
246 #define ADC_CHANNEL_17 ((uint8_t)0x11U)
247 #define ADC_CHANNEL_18 ((uint8_t)0x12U)
249 /* ADC interrupt definitions */
250 #define ADC_INT_WDE ADC_STAT_WDE
251 #define ADC_INT_EOC ADC_STAT_EOC
252 #define ADC_INT_EOIC ADC_STAT_EOIC
254 /* ADC interrupt flag */
255 #define ADC_INT_FLAG_WDE ADC_STAT_WDE
256 #define ADC_INT_FLAG_EOC ADC_STAT_EOC
257 #define ADC_INT_FLAG_EOIC ADC_STAT_EOIC
259 /* function declarations */
260 /* reset ADC */
261 void adc_deinit(void);
262 /* enable ADC interface */
263 void adc_enable(void);
264 /* disable ADC interface */
265 void adc_disable(void);
266
267 /* ADC calibration and reset calibration */
268 void adc_calibration_enable(void);
269 /* enable DMA request */
270 void adc_dma_mode_enable(void);
271 /* disable DMA request */
272 void adc_dma_mode_disable(void);
273
274 /* enable the temperature sensor and Vrefint channel */
275 void adc_tempsensor_vrefint_enable(void);
276 /* disable the temperature sensor and Vrefint channel */
277 void adc_tempsensor_vrefint_disable(void);
278 /* enable the vbat channel */
279 void adc_vbat_enable(void);
280 /* disable the vbat channel */
281 void adc_vbat_disable(void);
282
283 /* configure ADC discontinuous mode */
284 void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length);
285 /* configure ADC special function */
286 void adc_special_function_config(uint32_t function, ControlStatus newvalue);
287
288 /* configure ADC data alignment */
289 void adc_data_alignment_config(uint32_t data_alignment);
290 /* configure the length of regular channel group or inserted channel group */
291 void adc_channel_length_config(uint8_t channel_group, uint32_t length);
292 /* configure ADC regular channel */
293 void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
294 /* configure ADC inserted channel */
295 void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
296 /* configure ADC inserted channel offset */
297 void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset);
298 /* enable ADC external trigger */
299 void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue);
300 /* configure ADC external trigger source */
301 void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source);
302 /* enable ADC software trigger */
303 void adc_software_trigger_enable(uint8_t channel_group);
304
305 /* read ADC regular group data register */
306 uint16_t adc_regular_data_read(void);
307 /* read ADC inserted group data register */
308 uint16_t adc_inserted_data_read(uint8_t inserted_channel);
309
310 /* get the ADC flag bits */
311 FlagStatus adc_flag_get(uint32_t flag);
312 /* clear the ADC flag bits */
313 void adc_flag_clear(uint32_t flag);
314 /* get the ADC interrupt bits */
315 FlagStatus adc_interrupt_flag_get(uint32_t flag);
316 /* clear the ADC flag */
317 void adc_interrupt_flag_clear(uint32_t flag);
318 /* enable ADC interrupt */
319 void adc_interrupt_enable(uint32_t interrupt);
320 /* disable ADC interrupt */
321 void adc_interrupt_disable(uint32_t interrupt);
322
323 /* configure ADC analog watchdog single channel */
324 void adc_watchdog_single_channel_enable(uint8_t channel);
325 /* configure ADC analog watchdog group channel */
326 void adc_watchdog_group_channel_enable(uint8_t channel_group);
327 /* disable ADC analog watchdog */
328 void adc_watchdog_disable(void);
329 /* configure ADC analog watchdog threshold */
330 void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold);
331
332 /* configure ADC resolution */
333 void adc_resolution_config(uint32_t resolution);
334 /* configure ADC oversample mode */
335 void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio);
336 /* enable ADC oversample mode */
337 void adc_oversample_mode_enable(void);
338 /* disable ADC oversample mode */
339 void adc_oversample_mode_disable(void);
340
341 #endif /* GD32F3X0_ADC_H */
adc_flag_clear
void adc_flag_clear(uint32_t flag)
clear the ADC flag
Definition: gd32f3x0_adc.c:594
adc_watchdog_disable
void adc_watchdog_disable(void)
disable ADC analog watchdog
Definition: gd32f3x0_adc.c:763
adc_interrupt_flag_get
FlagStatus adc_interrupt_flag_get(uint32_t flag)
get the ADC interrupt flag
Definition: gd32f3x0_adc.c:609
adc_special_function_config
void adc_special_function_config(uint32_t function, ControlStatus newvalue)
configure ADC special function
Definition: gd32f3x0_adc.c:201
adc_vbat_enable
void adc_vbat_enable(void)
enable the vbat channel
Definition: gd32f3x0_adc.c:123
adc_oversample_mode_disable
void adc_oversample_mode_disable(void)
disable ADC oversample mode
Definition: gd32f3x0_adc.c:842
adc_interrupt_disable
void adc_interrupt_disable(uint32_t interrupt)
disable ADC interrupt
Definition: gd32f3x0_adc.c:693
adc_data_alignment_config
void adc_data_alignment_config(uint32_t data_alignment)
configure ADC data alignment
Definition: gd32f3x0_adc.c:241
adc_dma_mode_enable
void adc_dma_mode_enable(void)
enable DMA request
Definition: gd32f3x0_adc.c:77
adc_tempsensor_vrefint_enable
void adc_tempsensor_vrefint_enable(void)
enable the temperature sensor and Vrefint channel
Definition: gd32f3x0_adc.c:99
adc_resolution_config
void adc_resolution_config(uint32_t resolution)
configure ADC resolution
Definition: gd32f3x0_adc.c:152
adc_oversample_mode_config
void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio)
configure ADC oversample mode
Definition: gd32f3x0_adc.c:811
adc_flag_get
FlagStatus adc_flag_get(uint32_t flag)
get the ADC flag bits
Definition: gd32f3x0_adc.c:572
adc_software_trigger_enable
void adc_software_trigger_enable(uint8_t channel_group)
enable ADC software trigger
Definition: gd32f3x0_adc.c:502
adc_interrupt_flag_clear
void adc_interrupt_flag_clear(uint32_t flag)
clear ADC interrupt flag
Definition: gd32f3x0_adc.c:650
adc_inserted_channel_offset_config
void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset)
configure ADC inserted channel offset
Definition: gd32f3x0_adc.c:397
adc_watchdog_threshold_config
void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold)
configure ADC analog watchdog threshold
Definition: gd32f3x0_adc.c:775
adc_regular_data_read
uint16_t adc_regular_data_read(void)
read ADC regular group data register
Definition: gd32f3x0_adc.c:520
adc_inserted_channel_config
void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time)
configure ADC inserted channel
Definition: gd32f3x0_adc.c:357
adc_external_trigger_source_config
void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source)
configure ADC external trigger source
Definition: gd32f3x0_adc.c:475
adc_enable
void adc_enable(void)
enable ADC interface
Definition: gd32f3x0_adc.c:32
adc_tempsensor_vrefint_disable
void adc_tempsensor_vrefint_disable(void)
disable the temperature sensor and Vrefint channel
Definition: gd32f3x0_adc.c:111
adc_deinit
void adc_deinit(void)
reset ADC
Definition: gd32f3x0_adc.c:20
adc_oversample_mode_enable
void adc_oversample_mode_enable(void)
enable ADC oversample mode
Definition: gd32f3x0_adc.c:831
adc_vbat_disable
void adc_vbat_disable(void)
disable the vbat channel
Definition: gd32f3x0_adc.c:135
adc_inserted_data_read
uint16_t adc_inserted_data_read(uint8_t inserted_channel)
read ADC inserted group data register
Definition: gd32f3x0_adc.c:536
adc_dma_mode_disable
void adc_dma_mode_disable(void)
disable DMA request
Definition: gd32f3x0_adc.c:88
adc_discontinuous_mode_config
void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length)
configure ADC discontinuous mode
Definition: gd32f3x0_adc.c:170
adc_watchdog_single_channel_enable
void adc_watchdog_single_channel_enable(uint8_t channel)
configure ADC analog watchdog single channel
Definition: gd32f3x0_adc.c:719
adc_calibration_enable
void adc_calibration_enable(void)
ADC calibration and reset calibration.
Definition: gd32f3x0_adc.c:56
adc_external_trigger_config
void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue)
enable or disable ADC external trigger
Definition: gd32f3x0_adc.c:423
adc_disable
void adc_disable(void)
disable ADC interface
Definition: gd32f3x0_adc.c:45
adc_watchdog_group_channel_enable
void adc_watchdog_group_channel_enable(uint8_t channel_group)
configure ADC analog watchdog group channel
Definition: gd32f3x0_adc.c:737
adc_regular_channel_config
void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time)
configure ADC regular channel
Definition: gd32f3x0_adc.c:299
adc_interrupt_enable
void adc_interrupt_enable(uint32_t interrupt)
enable ADC interrupt
Definition: gd32f3x0_adc.c:665
adc_channel_length_config
void adc_channel_length_config(uint8_t channel_group, uint32_t length)
configure the length of regular channel group or inserted channel group
Definition: gd32f3x0_adc.c:262
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1


GD32F3x0_Firmware_Library: E:/GD32F3x0_Firmware_Library/Firmware/GD32F3x0_standard_peripheral/Include/gd32f3x0_dbg.h Source File

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  • GD32F3x0_Firmware_Library
  • Firmware
  • GD32F3x0_standard_peripheral
  • Include
gd32f3x0_dbg.h
Go to the documentation of this file.
1
6 /*
7 Copyright (C) 2017 GigaDevice
8
9 2017-06-06, V1.0.0, firmware for GD32F3x0
10 */
11
12 #ifndef GD32F3X0_DBG_H
13 #define GD32F3X0_DBG_H
14
15 #include "gd32f3x0.h"
16
17 /* DBG definitions */
18 #define DBG DBG_BASE
19
20 /* registers definitions */
21 #define DBG_ID REG32(DBG + 0x00U)
22 #define DBG_CTL0 REG32(DBG + 0x04U)
23 #define DBG_CTL1 REG32(DBG + 0x08U)
25 /* bits definitions */
26 /* DBG_ID */
27 #define DBG_ID_ID_CODE BITS(0,31)
29 /* DBG_CTL0 */
30 #define DBG_CTL0_SLP_HOLD BIT(0)
31 #define DBG_CTL0_DSLP_HOLD BIT(1)
32 #define DBG_CTL0_STB_HOLD BIT(2)
33 #define DBG_CTL0_FWDGT_HOLD BIT(8)
34 #define DBG_CTL0_WWDGT_HOLD BIT(9)
35 #define DBG_CTL0_TIMER0_HOLD BIT(10)
36 #define DBG_CTL0_TIMER1_HOLD BIT(11)
37 #define DBG_CTL0_TIMER2_HOLD BIT(12)
38 #define DBG_CTL0_I2C0_HOLD BIT(15)
39 #define DBG_CTL0_I2C1_HOLD BIT(16)
40 #define DBG_CTL0_I2C2_HOLD BIT(17)
41 #ifdef GD32F350
42 #define DBG_CTL0_TIMER5_HOLD BIT(19)
43 #endif /* GD32F350 */
44 #define DBG_CTL0_TIMER13_HOLD BIT(27)
46 /* DBG_CTL1 */
47 #define DBG_CTL1_RTC_HOLD BIT(10)
48 #define DBG_CTL1_TIMER14_HOLD BIT(16)
49 #define DBG_CTL1_TIMER15_HOLD BIT(17)
50 #define DBG_CTL1_TIMER16_HOLD BIT(18)
52 /* constants definitions */
53 #define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD
54 #define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD
55 #define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD
57 /* define the peripheral debug hold bit position and its register index offset */
58 #define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
59 #define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
60 #define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
61
62 /* register index */
63 enum dbg_reg_idx
64 {
65 DBG_IDX_CTL0 = 0x04U,
66 DBG_IDX_CTL1 = 0x08U,
67 };
68
69 /* peripherals hold bit */
70 typedef enum
71 {
72 DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U),
73 DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U),
74 DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U),
75 DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 11U),
76 DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U),
77 #ifdef GD32F350
78 DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U),
79 #endif /* GD32F350 */
80 DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U),
81 DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U),
82 DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U),
83 DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U),
84 DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U),
85 DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U),
86 DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 17U),
87 DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U),
88 }dbg_periph_enum;
89
90 /* function declarations */
91 /* deinitialize the DBG */
92 void dbg_deinit(void);
93 /* read DBG_ID code register */
94 uint32_t dbg_id_get(void);
95
96 /* enable low power behavior when the MCU is in debug mode */
97 void dbg_low_power_enable(uint32_t dbg_low_power);
98 /* disable low power behavior when the MCU is in debug mode */
99 void dbg_low_power_disable(uint32_t dbg_low_power);
100
101 /* enable peripheral behavior when the MCU is in debug mode */
102 void dbg_periph_enable(dbg_periph_enum dbg_periph);
103 /* disable peripheral behavior when the MCU is in debug mode */
104 void dbg_periph_disable(dbg_periph_enum dbg_periph);
105
106 #endif /* GD32F3X0_DBG_H */
DBG_I2C1_HOLD
Definition: gd32f3x0_dbg.h:85
dbg_periph_enum
dbg_periph_enum
Definition: gd32f3x0_dbg.h:70
dbg_periph_enable
void dbg_periph_enable(dbg_periph_enum dbg_periph)
enable peripheral behavior when the mcu is in debug mode
Definition: gd32f3x0_dbg.c:93
DBG_I2C0_HOLD
Definition: gd32f3x0_dbg.h:84
DBG_TIMER16_HOLD
Definition: gd32f3x0_dbg.h:83
dbg_deinit
void dbg_deinit(void)
deinitialize the DBG
Definition: gd32f3x0_dbg.c:22
DBG_TIMER2_HOLD
Definition: gd32f3x0_dbg.h:76
DBG_RTC_HOLD
Definition: gd32f3x0_dbg.h:87
DBG_WWDGT_HOLD
Definition: gd32f3x0_dbg.h:73
DBG_IDX_CTL0
Definition: gd32f3x0_dbg.h:65
DBG_TIMER14_HOLD
Definition: gd32f3x0_dbg.h:81
dbg_low_power_enable
void dbg_low_power_enable(uint32_t dbg_low_power)
enable low power behavior when the mcu is in debug mode
Definition: gd32f3x0_dbg.c:49
dbg_reg_idx
dbg_reg_idx
Definition: gd32f3x0_dbg.h:63
DBG_IDX_CTL1
Definition: gd32f3x0_dbg.h:66
DBG_FWDGT_HOLD
Definition: gd32f3x0_dbg.h:72
dbg_low_power_disable
void dbg_low_power_disable(uint32_t dbg_low_power)
disable low power behavior when the mcu is in debug mode
Definition: gd32f3x0_dbg.c:64
DBG_TIMER15_HOLD
Definition: gd32f3x0_dbg.h:82
DBG_TIMER1_HOLD
Definition: gd32f3x0_dbg.h:75
DBG_I2C2_HOLD
Definition: gd32f3x0_dbg.h:86
DBG_TIMER13_HOLD
Definition: gd32f3x0_dbg.h:80
dbg_periph_disable
void dbg_periph_disable(dbg_periph_enum dbg_periph)
disable peripheral behavior when the mcu is in debug mode
Definition: gd32f3x0_dbg.c:122
dbg_id_get
uint32_t dbg_id_get(void)
read DBG_ID code register
Definition: gd32f3x0_dbg.c:34
DBG_TIMER0_HOLD
Definition: gd32f3x0_dbg.h:74
DBG_REGIDX_BIT
#define DBG_REGIDX_BIT(regidx, bitpos)
Definition: gd32f3x0_dbg.h:58
Generated on Tue Jun 27 2017 14:36:11 for GD32F3x0_Firmware_Library by doxygen 1.8.9.1