main.c 2.0 KB

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  1. /*!
  2. \file main.c
  3. \brief CTC is used to trim internal 48MHz RC oscillator with GPIO
  4. */
  5. /*
  6. Copyright (C) 2017 GigaDevice
  7. 2017-06-06, V1.0.0, firmware for GD32F3x0
  8. */
  9. #include "gd32f3x0.h"
  10. #include "gd32f3x0_eval.h"
  11. void ctc_config(void);
  12. /*!
  13. \brief main function
  14. \param[in] none
  15. \param[out] none
  16. \retval none
  17. */
  18. int main(void)
  19. {
  20. /* init led1*/
  21. gd_eval_led_init(LED1);
  22. /* enable IRC48M clock */
  23. rcu_osci_on(RCU_IRC48M);
  24. /* wait till IRC48M is ready */
  25. rcu_osci_stab_wait(RCU_IRC48M);
  26. /* configure PA8 as external reference signal source input with 32khz */
  27. rcu_periph_clock_enable(RCU_GPIOA);
  28. gpio_af_set(GPIOA, GPIO_AF_6 ,GPIO_PIN_8);
  29. gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLDOWN, GPIO_PIN_8);
  30. gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_8);
  31. /* CTC peripheral clock enable */
  32. rcu_periph_clock_enable(RCU_CTC);
  33. /* CTC config */
  34. ctc_config();
  35. while(1){
  36. /* if the clock trim is OK */
  37. if(RESET != ctc_flag_get(CTC_FLAG_CKOK)){
  38. gd_eval_led_on(LED1);
  39. }else{
  40. gd_eval_led_off(LED1);
  41. }
  42. }
  43. }
  44. /*!
  45. \brief configure the CTC peripheral
  46. \param[in] none
  47. \param[out] none
  48. \retval none
  49. */
  50. void ctc_config(void)
  51. {
  52. /* config CTC reference signal source prescaler */
  53. ctc_refsource_prescaler_config(CTC_REFSOURCE_PSC_DIV32);
  54. /* select reference signal source */
  55. ctc_refsource_signal_select(CTC_REFSOURCE_GPIO);
  56. /* select reference signal source polarity */
  57. ctc_refsource_polarity_config(CTC_REFSOURCE_POLARITY_RISING);
  58. /* config hardware automatically trim mode */
  59. ctc_hardware_trim_mode_config(CTC_HARDWARE_TRIM_MODE_ENABLE);
  60. /* config CTC counter reload value, Fclock/Fref-1 */
  61. ctc_counter_reload_value_config(0xBB7F);
  62. /* config clock trim base limit value, Fclock/Fref*0.0012/2 */
  63. ctc_clock_limit_value_config(0x1D);
  64. /* CTC counter enable */
  65. ctc_counter_enable();
  66. }