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GD32F3x0_standard_peripheral
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gd32f3x0_dma.h

gd32f3x0_dma.h 17 KB
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  1. /*!
    2. 

  2.     \file  gd32f3x0_dma.h
    3. 

  3.     \brief definitions for the DMA
    4. 

  4. */
    5. 

  5. 

  6. /*
    7. 

  7.     Copyright (C) 2017 GigaDevice
    8. 

  8. 

  9.     2017-06-06, V1.0.0, firmware for GD32F3x0
    10. 

  10. */
    11. 

  11. 

  12. #ifndef GD32F3X0_DMA_H
    13. 

  13. #define GD32F3X0_DMA_H
    14. 

  14. 

  15. #include "gd32f3x0.h"
    16. 

  16. 

  17. /* DMA definitions */
    18. 

  18. #define DMA                               DMA_BASE              /*!< DMA base address */
    19. 

  19. 

  20. /* registers definitions */
    21. 

  21. #define DMA_INTF                          REG32(DMA + 0x00U)    /*!< DMA interrupt flag register */
    22. 

  22. #define DMA_INTC                          REG32(DMA + 0x04U)    /*!< DMA interrupt flag clear register */
    23. 

  23. #define DMA_CH0CTL                        REG32(DMA + 0x08U)    /*!< DMA channel 0 control register */
    24. 

  24. #define DMA_CH0CNT                        REG32(DMA + 0x0CU)    /*!< DMA channel 0 counter register */
    25. 

  25. #define DMA_CH0PADDR                      REG32(DMA + 0x10U)    /*!< DMA channel 0 peripheral base address register */
    26. 

  26. #define DMA_CH0MADDR                      REG32(DMA + 0x14U)    /*!< DMA channel 0 memory base address register */
    27. 

  27. #define DMA_CH1CTL                        REG32(DMA + 0x1CU)    /*!< DMA channel 1 control register */
    28. 

  28. #define DMA_CH1CNT                        REG32(DMA + 0x20U)    /*!< DMA channel 1 counter register */
    29. 

  29. #define DMA_CH1PADDR                      REG32(DMA + 0x24U)    /*!< DMA channel 1 peripheral base address register */
    30. 

  30. #define DMA_CH1MADDR                      REG32(DMA + 0x28U)    /*!< DMA channel 1 memory base address register */
    31. 

  31. #define DMA_CH2CTL                        REG32(DMA + 0x30U)    /*!< DMA channel 2 control register */
    32. 

  32. #define DMA_CH2CNT                        REG32(DMA + 0x34U)    /*!< DMA channel 2 counter register */
    33. 

  33. #define DMA_CH2PADDR                      REG32(DMA + 0x38U)    /*!< DMA channel 2 peripheral base address register */
    34. 

  34. #define DMA_CH2MADDR                      REG32(DMA + 0x3CU)    /*!< DMA channel 2 memory base address register */
    35. 

  35. #define DMA_CH3CTL                        REG32(DMA + 0x44U)    /*!< DMA channel 3 control register */
    36. 

  36. #define DMA_CH3CNT                        REG32(DMA + 0x48U)    /*!< DMA channel 3 counter register */
    37. 

  37. #define DMA_CH3PADDR                      REG32(DMA + 0x4CU)    /*!< DMA channel 3 peripheral base address register */
    38. 

  38. #define DMA_CH3MADDR                      REG32(DMA + 0x50U)    /*!< DMA channel 3 memory base address register */
    39. 

  39. #define DMA_CH4CTL                        REG32(DMA + 0x58U)    /*!< DMA channel 4 control register */
    40. 

  40. #define DMA_CH4CNT                        REG32(DMA + 0x5CU)    /*!< DMA channel 4 counter register */
    41. 

  41. #define DMA_CH4PADDR                      REG32(DMA + 0x60U)    /*!< DMA channel 4 peripheral base address register */
    42. 

  42. #define DMA_CH4MADDR                      REG32(DMA + 0x64U)    /*!< DMA channel 4 memory base address register */
    43. 

  43. #define DMA_CH5CTL                        REG32(DMA + 0x6CU)    /*!< DMA channel 5 control register */
    44. 

  44. #define DMA_CH5CNT                        REG32(DMA + 0x70U)    /*!< DMA channel 5 counter register */
    45. 

  45. #define DMA_CH5PADDR                      REG32(DMA + 0x74U)    /*!< DMA channel 5 peripheral base address register */
    46. 

  46. #define DMA_CH5MADDR                      REG32(DMA + 0x78U)    /*!< DMA channel 5 memory base address register */
    47. 

  47. #define DMA_CH6CTL                        REG32(DMA + 0x80U)    /*!< DMA channel 6 control register */
    48. 

  48. #define DMA_CH6CNT                        REG32(DMA + 0x84U)    /*!< DMA channel 6 counter register */
    49. 

  49. #define DMA_CH6PADDR                      REG32(DMA + 0x88U)    /*!< DMA channel 6 peripheral base address register */
    50. 

  50. #define DMA_CH6MADDR                      REG32(DMA + 0x8CU)    /*!< DMA channel 6 memory base address register */
    51. 

  51. 

  52. /* bits definitions */
    53. 

  53. /* DMA_INTF */
    54. 

  54. #define DMA_INTF_GIF                      BIT(0)                /*!< global interrupt flag of channel */
    55. 

  55. #define DMA_INTF_FTFIF                    BIT(1)                /*!< full transfer finish flag of channel */
    56. 

  56. #define DMA_INTF_HTFIF                    BIT(2)                /*!< half transfer finish flag of channel */
    57. 

  57. #define DMA_INTF_ERRIF                    BIT(3)                /*!< error flag of channel */
    58. 

  58. 

  59. /* DMA_INTC */
    60. 

  60. #define DMA_INTC_GIFC                     BIT(0)                /*!< clear global interrupt flag of channel */
    61. 

  61. #define DMA_INTC_FTFIFC                   BIT(1)                /*!< clear transfer finish flag of channel */
    62. 

  62. #define DMA_INTC_HTFIFC                   BIT(2)                /*!< clear half transfer finish flag of channel */
    63. 

  63. #define DMA_INTC_ERRIFC                   BIT(3)                /*!< clear error flag of channel */
    64. 

  64. 

  65. /* DMA_CHxCTL,x=0..6 */
    66. 

  66. #define DMA_CHXCTL_CHEN                   BIT(0)                /*!< channel x enable */
    67. 

  67. #define DMA_CHXCTL_FTFIE                  BIT(1)                /*!< enable bit for channel x transfer complete interrupt */
    68. 

  68. #define DMA_CHXCTL_HTFIE                  BIT(2)                /*!< enable bit for channel x transfer half complete interrupt */
    69. 

  69. #define DMA_CHXCTL_ERRIE                  BIT(3)                /*!< enable bit for channel x error interrupt */
    70. 

  70. #define DMA_CHXCTL_DIR                    BIT(4)                /*!< direction of the data transfer on the channel */
    71. 

  71. #define DMA_CHXCTL_CMEN                   BIT(5)                /*!< circulation mode */
    72. 

  72. #define DMA_CHXCTL_PNAGA                  BIT(6)                /*!< next address generation algorithm of peripheral */
    73. 

  73. #define DMA_CHXCTL_MNAGA                  BIT(7)                /*!< next address generation algorithm of memory */
    74. 

  74. #define DMA_CHXCTL_PWIDTH                 BITS(8,9)             /*!< transfer data size of peripheral */
    75. 

  75. #define DMA_CHXCTL_MWIDTH                 BITS(10,11)           /*!< transfer data size of memory */
    76. 

  76. #define DMA_CHXCTL_PRIO                   BITS(12,13)           /*!< priority level of channelx */
    77. 

  77. #define DMA_CHXCTL_M2M                    BIT(14)               /*!< memory to memory mode */
    78. 

  78. 

  79. /* DMA_CHxCNT,x=0..6 */
    80. 

  80. #define DMA_CHXCNT_CNT                    BITS(0,15)            /*!< transfer counter */
    81. 

  81. 

  82. /* DMA_CHxPADDR,x=0..6 */
    83. 

  83. #define DMA_CHXPADDR_PADDR                BITS(0,31)            /*!< peripheral base address */
    84. 

  84. 

  85. /* DMA_CHxMADDR,x=0..6 */
    86. 

  86. #define DMA_CHXMADDR_MADDR                BITS(0,31)            /*!< memory base address */
    87. 

  87. 

  88. /* constants definitions */
    89. 

  89. /* DMA channel select */
    90. 

  90. typedef enum 
    91. 

  91. {
    92. 

  92.     DMA_CH0 = 0,                          /*!< DMA Channel0 */
    93. 

  93.     DMA_CH1,                              /*!< DMA Channel1 */ 
    94. 

  94.     DMA_CH2,                              /*!< DMA Channel2 */ 
    95. 

  95.     DMA_CH3,                              /*!< DMA Channel3 */ 
    96. 

  96.     DMA_CH4,                              /*!< DMA Channel4 */ 
    97. 

  97.     DMA_CH5,                              /*!< DMA Channel5 */ 
    98. 

  98.     DMA_CH6                               /*!< DMA Channel6 */
    99. 

  99. } dma_channel_enum;
    100. 

  100. 

  101. /* DMA initialize struct */
    102. 

  102. typedef struct
    103. 

  103. {
    104. 

  104.     uint32_t periph_addr;                 /*!< peripheral base address */
    105. 

  105.     uint32_t periph_width;                /*!< transfer data size of peripheral */
    106. 

  106.     uint8_t periph_inc;                   /*!< peripheral increasing mode */
    107. 

  107.     uint32_t memory_addr;                 /*!< memory base address */
    108. 

  108.     uint32_t memory_width;                /*!< transfer data size of memory */
    109. 

  109.     uint8_t memory_inc;                   /*!< memory increasing mode */
    110. 

  110.     uint8_t direction;                    /*!< channel data transfer direction */
    111. 

  111.     uint32_t number;                      /*!< channel transfer number */
    112. 

  112.     uint32_t priority;                    /*!< channel priority level */
    113. 

  113. } dma_parameter_struct;
    114. 

  114. 

  115. /* DMA reset value */
    116. 

  116. #define DMA_CHCTL_RESET_VALUE             ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXCTL register */
    117. 

  117. #define DMA_CHCNT_RESET_VALUE             ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXCNT register */
    118. 

  118. #define DMA_CHPADDR_RESET_VALUE           ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXPADDR register */
    119. 

  119. #define DMA_CHMADDR_RESET_VALUE           ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXMADDR register */
    120. 

  120. #define DMA_CHINTF_RESET_VALUE            (DMA_INTF_GIF | DMA_INTF_FTFIF | \
    121. 

  121.                                            DMA_INTF_HTFIF | DMA_INTF_ERRIF)
    122. 

  122. 

  123. #define DMA_FLAG_ADD(flag,shift)          ((flag) << ((uint32_t)(shift) * 4U))            /*!< DMA channel flag shift */
    124. 

  124. 

  125. /* DMA_CHCTL base address */
    126. 

  126. #define DMA_CHXCTL_BASE                   (DMA + 0x08U)                                   /*!< the base address of DMA channel CHXCTL register */
    127. 

  127. #define DMA_CHXCNT_BASE                   (DMA + 0x0CU)                                   /*!< the base address of DMA channel CHXCNT register */
    128. 

  128. #define DMA_CHXPADDR_BASE                 (DMA + 0x10U)                                   /*!< the base address of DMA channel CHXPADDR register */
    129. 

  129. #define DMA_CHXMADDR_BASE                 (DMA + 0x14U)                                   /*!< the base address of DMA channel CHXMADDR register */
    130. 

  130. 

  131. /* DMA channel shift bit */
    132. 

  132. #define DMA_CHCTL(channel)                REG32(DMA_CHXCTL_BASE + 0x14U * (uint32_t)(channel))         /*!< the address of DMA channel CHXCTL register */
    133. 

  133. #define DMA_CHCNT(channel)                REG32(DMA_CHXCNT_BASE + 0x14U * (uint32_t)(channel))         /*!< the address of DMA channel CHXCNT register */
    134. 

  134. #define DMA_CHPADDR(channel)              REG32(DMA_CHXPADDR_BASE + 0x14U * (uint32_t)(channel))       /*!< the address of DMA channel CHXPADDR register */
    135. 

  135. #define DMA_CHMADDR(channel)              REG32(DMA_CHXMADDR_BASE + 0x14U * (uint32_t)(channel))       /*!< the address of DMA channel CHXMADDR register */
    136. 

  136. 

  137. /* DMA_INTF register */
    138. 

  138. /* interrupt flag bits */
    139. 

  139. #define DMA_INT_FLAG_G                    DMA_INTF_GIF                                    /*!< global interrupt flag of channel */
    140. 

  140. #define DMA_INT_FLAG_FTF                  DMA_INTF_FTFIF                                  /*!< full transfer finish interrupt flag of channel */
    141. 

  141. #define DMA_INT_FLAG_HTF                  DMA_INTF_HTFIF                                  /*!< half transfer finish interrupt flag of channel */
    142. 

  142. #define DMA_INT_FLAG_ERR                  DMA_INTF_ERRIF                                  /*!< error interrupt flag of channel */
    143. 

  143. 

  144. /* flag bits */
    145. 

  145. #define DMA_FLAG_G                        DMA_INTF_GIF                                    /*!< global interrupt flag of channel */
    146. 

  146. #define DMA_FLAG_FTF                      DMA_INTF_FTFIF                                  /*!< full transfer finish flag of channel */
    147. 

  147. #define DMA_FLAG_HTF                      DMA_INTF_HTFIF                                  /*!< half transfer finish flag of channel */
    148. 

  148. #define DMA_FLAG_ERR                      DMA_INTF_ERRIF                                  /*!< error flag of channel */
    149. 

  149. 

  150. /* DMA_CHxCTL register */
    151. 

  151. /* interrupt enable bits */
    152. 

  152. #define DMA_INT_FTF                       DMA_CHXCTL_FTFIE                                /*!< enable bit for channel full transfer finish interrupt */
    153. 

  153. #define DMA_INT_HTF                       DMA_CHXCTL_HTFIE                                /*!< enable bit for channel half transfer finish interrupt */
    154. 

  154. #define DMA_INT_ERR                       DMA_CHXCTL_ERRIE                                /*!< enable bit for channel error interrupt */
    155. 

  155. 

  156. /* transfer direction */
    157. 

  157. #define DMA_PERIPHERAL_TO_MEMORY          ((uint32_t)0x00000000U)                         /*!< read from peripheral and write to memory */
    158. 

  158. #define DMA_MEMORY_TO_PERIPHERAL          ((uint32_t)0x00000001U)                         /*!< read from memory and write to peripheral */
    159. 

  159. 

  160. /* peripheral increasing mode */
    161. 

  161. #define DMA_PERIPH_INCREASE_DISABLE       ((uint32_t)0x00000000U)                         /*!< next address of peripheral is fixed address mode */
    162. 

  162. #define DMA_PERIPH_INCREASE_ENABLE        ((uint32_t)0x00000001U)                         /*!< next address of peripheral is increasing address mode */
    163. 

  163. 

  164. /* memory increasing mode */
    165. 

  165. #define DMA_MEMORY_INCREASE_DISABLE       ((uint32_t)0x00000000U)                         /*!< next address of memory is fixed address mode */
    166. 

  166. #define DMA_MEMORY_INCREASE_ENABLE        ((uint32_t)0x00000001U)                         /*!< next address of memory is increasing address mode */
    167. 

  167. 

  168. /* transfer data size of peripheral */
    169. 

  169. #define CHCTL_PWIDTH(regval)              (BITS(8,9) & ((regval) << 8))                   /*!< transfer data size of peripheral */
    170. 

  170. #define DMA_PERIPHERAL_WIDTH_8BIT         CHCTL_PWIDTH(0)                                 /*!< transfer data size of peripheral is 8-bit */
    171. 

  171. #define DMA_PERIPHERAL_WIDTH_16BIT        CHCTL_PWIDTH(1)                                 /*!< transfer data size of peripheral is 16-bit */
    172. 

  172. #define DMA_PERIPHERAL_WIDTH_32BIT        CHCTL_PWIDTH(2)                                 /*!< transfer data size of peripheral is 32-bit */
    173. 

  173. 

  174. /* transfer data size of memory */
    175. 

  175. #define CHCTL_MWIDTH(regval)              (BITS(10,11) & ((regval) << 10))                /*!< transfer data size of memory */
    176. 

  176. #define DMA_MEMORY_WIDTH_8BIT             CHCTL_MWIDTH(0)                                 /*!< transfer data size of memory is 8-bit */
    177. 

  177. #define DMA_MEMORY_WIDTH_16BIT            CHCTL_MWIDTH(1)                                 /*!< transfer data size of memory is 16-bit */
    178. 

  178. #define DMA_MEMORY_WIDTH_32BIT            CHCTL_MWIDTH(2)                                 /*!< transfer data size of memory is 32-bit */
    179. 

  179. 

  180. /* channel priority level */
    181. 

  181. #define CHCTL_PRIO(regval)                (BITS(12,13) & ((regval) << 12))                /*!< DMA channel priority level */
    182. 

  182. #define DMA_PRIORITY_LOW                  CHCTL_PRIO(0)                                   /*!< low priority */
    183. 

  183. #define DMA_PRIORITY_MEDIUM               CHCTL_PRIO(1)                                   /*!< medium priority */
    184. 

  184. #define DMA_PRIORITY_HIGH                 CHCTL_PRIO(2)                                   /*!< high priority */
    185. 

  185. #define DMA_PRIORITY_ULTRA_HIGH           CHCTL_PRIO(3)                                   /*!< ultra high priority */
    186. 

  186. 

  187. /* DMA_CHxCNT register */
    188. 

  188. /* transfer counter */
    189. 

  189. #define DMA_CHANNEL_CNT_MASK              DMA_CHXCNT_CNT                    
    190. 

  190. 

  191. /* function declarations */
    192. 

  192. /* deinitialize DMA a channel registers */
    193. 

  193. void dma_deinit(dma_channel_enum channelx);
    194. 

  194. /* initialize DMA channel */
    195. 

  195. void dma_init(dma_channel_enum channelx, dma_parameter_struct init_struct);
    196. 

  196. /* enable DMA circulation mode */
    197. 

  197. void dma_circulation_enable(dma_channel_enum channelx);
    198. 

  198. /* disable DMA circulation mode */
    199. 

  199. void dma_circulation_disable(dma_channel_enum channelx);
    200. 

  200. /* enable memory to memory mode */
    201. 

  201. void dma_memory_to_memory_enable(dma_channel_enum channelx);
    202. 

  202. /* disable memory to memory mode */
    203. 

  203. void dma_memory_to_memory_disable(dma_channel_enum channelx);
    204. 

  204. /* enable DMA channel */
    205. 

  205. void dma_channel_enable(dma_channel_enum channelx);
    206. 

  206. /* disable DMA channel */
    207. 

  207. void dma_channel_disable(dma_channel_enum channelx);
    208. 

  208. 

  209. /* set DMA peripheral base address */
    210. 

  210. void dma_periph_address_config(dma_channel_enum channelx, uint32_t address);
    211. 

  211. /* set DMA memory base address */
    212. 

  212. void dma_memory_address_config(dma_channel_enum channelx, uint32_t address);
    213. 

  213. /* set the number of remaining data to be transferred by the DMA */
    214. 

  214. void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number);
    215. 

  215. /* get the number of remaining data to be transferred by the DMA */
    216. 

  216. uint32_t dma_transfer_number_get(dma_channel_enum channelx);
    217. 

  217. /* configure priority level of DMA channel */
    218. 

  218. void dma_priority_config(dma_channel_enum channelx, uint32_t priority);
    219. 

  219. /* configure transfer data size of memory */
    220. 

  220. void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth);
    221. 

  221. /* configure transfer data size of peripheral */
    222. 

  222. void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth);
    223. 

  223. /* enable next address increasement algorithm of memory */
    224. 

  224. void dma_memory_increase_enable(dma_channel_enum channelx);
    225. 

  225. /* disable next address increasement algorithm of memory */
    226. 

  226. void dma_memory_increase_disable(dma_channel_enum channelx);
    227. 

  227. /* enable next address increasement algorithm of peripheral */
    228. 

  228. void dma_periph_increase_enable(dma_channel_enum channelx);
    229. 

  229. /* disable next address increasement algorithm of peripheral */
    230. 

  230. void dma_periph_increase_disable(dma_channel_enum channelx);
    231. 

  231. /* configure the direction of data transfer on the channel */
    232. 

  232. void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction);
    233. 

  233. 

  234. /* check DMA flag is set or not */
    235. 

  235. FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag);
    236. 

  236. /* clear DMA a channel flag */
    237. 

  237. void dma_flag_clear(dma_channel_enum channelx, uint32_t flag);
    238. 

  238. /* check DMA flag and interrupt enable bit is set or not */
    239. 

  239. FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag);
    240. 

  240. /* clear DMA a channel flag */
    241. 

  241. void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag);
    242. 

  242. /* enable DMA interrupt */
    243. 

  243. void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source);
    244. 

  244. /* disable DMA interrupt */
    245. 

  245. void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source);
    246. 

  246. 

  247. #endif /* GD32F3X0_DMA_H */
    248.