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GD32F3x0_Firmwa...
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Firmware
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GD32F3x0_standard_peripheral
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Include
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gd32f3x0_adc.h

gd32f3x0_adc.h 23 KB
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  1. /*!
    2. 

  2.     \file  gd32f3x0_adc.h
    3. 

  3.     \brief definitions for the ADC
    4. 

  4. */
    5. 

  5. 

  6. /*
    7. 

  7.     Copyright (C) 2017 GigaDevice
    8. 

  8. 

  9.     2017-06-06, V1.0.0, firmware for GD32F3x0
    10. 

  10. */
    11. 

  11. 

  12. #ifndef GD32F3X0_ADC_H
    13. 

  13. #define GD32F3X0_ADC_H
    14. 

  14. 

  15. #include "gd32f3x0.h"
    16. 

  16. 

  17. /* ADC definitions */
    18. 

  18. #define ADC                              ADC_BASE
    19. 

  19. 

  20. /* registers definitions */
    21. 

  21. #define ADC_STAT                         REG32(ADC + 0x00U)               /*!< ADC status register */
    22. 

  22. #define ADC_CTL0                         REG32(ADC + 0x04U)               /*!< ADC control register 0 */
    23. 

  23. #define ADC_CTL1                         REG32(ADC + 0x08U)               /*!< ADC control register 1 */
    24. 

  24. #define ADC_SAMPT0                       REG32(ADC + 0x0CU)               /*!< ADC sampling time register 0 */
    25. 

  25. #define ADC_SAMPT1                       REG32(ADC + 0x10U)               /*!< ADC sampling time register 1 */
    26. 

  26. #define ADC_IOFF0                        REG32(ADC + 0x14U)               /*!< ADC inserted channel data offset register 0 */
    27. 

  27. #define ADC_IOFF1                        REG32(ADC + 0x18U)               /*!< ADC inserted channel data offset register 1 */
    28. 

  28. #define ADC_IOFF2                        REG32(ADC + 0x1CU)               /*!< ADC inserted channel data offset register 2 */
    29. 

  29. #define ADC_IOFF3                        REG32(ADC + 0x20U)               /*!< ADC inserted channel data offset register 3 */
    30. 

  30. #define ADC_WDHT                         REG32(ADC + 0x24U)               /*!< ADC watchdog high threshold register */
    31. 

  31. #define ADC_WDLT                         REG32(ADC + 0x28U)               /*!< ADC watchdog low threshold register */
    32. 

  32. #define ADC_RSQ0                         REG32(ADC + 0x2CU)               /*!< ADC regular sequence register 0 */
    33. 

  33. #define ADC_RSQ1                         REG32(ADC + 0x30U)               /*!< ADC regular sequence register 1 */
    34. 

  34. #define ADC_RSQ2                         REG32(ADC + 0x34U)               /*!< ADC regular sequence register 2 */
    35. 

  35. #define ADC_ISQ                          REG32(ADC + 0x38U)               /*!< ADC inserted sequence register */
    36. 

  36. #define ADC_IDATA0                       REG32(ADC + 0x3CU)               /*!< ADC inserted data register 0 */
    37. 

  37. #define ADC_IDATA1                       REG32(ADC + 0x40U)               /*!< ADC inserted data register 1 */
    38. 

  38. #define ADC_IDATA2                       REG32(ADC + 0x44U)               /*!< ADC inserted data register 2 */
    39. 

  39. #define ADC_IDATA3                       REG32(ADC + 0x48U)               /*!< ADC inserted data register 3 */
    40. 

  40. #define ADC_RDATA                        REG32(ADC + 0x4CU)               /*!< ADC regular data register */
    41. 

  41. #define ADC_OVSAMPCTL                    REG32(ADC + 0x80U)               /*!< ADC oversampling control register */
    42. 

  42. 

  43. /* bits definitions */
    44. 

  44. /* ADC_STAT */
    45. 

  45. #define ADC_STAT_WDE                     BIT(0)                           /*!< analog watchdog event flag */
    46. 

  46. #define ADC_STAT_EOC                     BIT(1)                           /*!< end of conversion */
    47. 

  47. #define ADC_STAT_EOIC                    BIT(2)                           /*!< inserted channel end of conversion */
    48. 

  48. #define ADC_STAT_STIC                    BIT(3)                           /*!< inserted channel start flag */
    49. 

  49. #define ADC_STAT_STRC                    BIT(4)                           /*!< regular channel start flag */
    50. 

  50. 

  51. /* ADC_CTL0 */
    52. 

  52. #define ADC_CTL0_WDCHSEL                 BITS(0,4)                        /*!< analog watchdog channel select bits */
    53. 

  53. #define ADC_CTL0_EOCIE                   BIT(5)                           /*!< interrupt enable for EOC */
    54. 

  54. #define ADC_CTL0_WDEIE                   BIT(6)                           /*!< analog watchdog interrupt enable */
    55. 

  55. #define ADC_CTL0_EOICIE                  BIT(7)                           /*!< interrupt enable for inserted channels */
    56. 

  56. #define ADC_CTL0_SM                      BIT(8)                           /*!< scan mode */
    57. 

  57. #define ADC_CTL0_WDSC                    BIT(9)                           /*!< when in scan mode, analog watchdog is effective on a single channel */
    58. 

  58. #define ADC_CTL0_ICA                     BIT(10)                          /*!< automatic inserted group conversion */
    59. 

  59. #define ADC_CTL0_DISRC                   BIT(11)                          /*!< discontinuous mode on regular channels */
    60. 

  60. #define ADC_CTL0_DISIC                   BIT(12)                          /*!< discontinuous mode on inserted channels */
    61. 

  61. #define ADC_CTL0_DISNUM                  BITS(13,15)                      /*!< discontinuous mode channel count */
    62. 

  62. #define ADC_CTL0_IWDEN                   BIT(22)                          /*!< analog watchdog enable on inserted channels */
    63. 

  63. #define ADC_CTL0_RWDEN                   BIT(23)                          /*!< analog watchdog enable on regular channels */
    64. 

  64. #define ADC_CTL0_DRES                    BITS(24,25)                      /*!< ADC data resolution */
    65. 

  65. 

  66. /* ADC_CTL1 */
    67. 

  67. #define ADC_CTL1_ADCON                   BIT(0)                           /*!< ADC converter on */
    68. 

  68. #define ADC_CTL1_CTN                     BIT(1)                           /*!< continuous conversion */
    69. 

  69. #define ADC_CTL1_CLB                     BIT(2)                           /*!< ADC calibration */
    70. 

  70. #define ADC_CTL1_RSTCLB                  BIT(3)                           /*!< reset calibration */
    71. 

  71. #define ADC_CTL1_DMA                     BIT(8)                           /*!< direct memory access mode */
    72. 

  72. #define ADC_CTL1_DAL                     BIT(11)                          /*!< data alignment */
    73. 

  73. #define ADC_CTL1_ETSIC                   BITS(12,14)                      /*!< external trigger select for inserted channel */
    74. 

  74. #define ADC_CTL1_ETEIC                   BIT(15)                          /*!< external trigger enable for inserted channel */
    75. 

  75. #define ADC_CTL1_ETSRC                   BITS(17,19)                      /*!< external trigger select for regular channel */
    76. 

  76. #define ADC_CTL1_ETERC                   BIT(20)                          /*!< external trigger enable for regular channel */
    77. 

  77. #define ADC_CTL1_SWICST                  BIT(21)                          /*!< start on inserted channel */
    78. 

  78. #define ADC_CTL1_SWRCST                  BIT(22)                          /*!< start on regular channel */
    79. 

  79. #define ADC_CTL1_TSVREN                  BIT(23)                          /*!< enable channel 16 and 17 */
    80. 

  80. #define ADC_CTL1_VBETEN                  BIT(24)                          /*!< VBAT enable */
    81. 

  81. 

  82. /* ADC_SAMPTx x=0,1 */
    83. 

  83. #define ADC_SAMPTX_SPTN                  BITS(0,2)                        /*!< channel n sample time selection */
    84. 

  84. 

  85. /* ADC_IOFFx x=0..3 */
    86. 

  86. #define ADC_IOFFX_IOFF                   BITS(0,11)                       /*!< data offset for inserted channel x */
    87. 

  87. 

  88. /* ADC_WDHT */
    89. 

  89. #define ADC_WDHT_WDHT                    BITS(0,11)                       /*!< analog watchdog high threshold */
    90. 

  90. 

  91. /* ADC_WDLT */
    92. 

  92. #define ADC_WDLT_WDLT                    BITS(0,11)                       /*!< analog watchdog low threshold */
    93. 

  93. 

  94. /* ADC_RSQx x=0..2 */
    95. 

  95. #define ADC_RSQX_RSQN                    BITS(0,4)                        /*!< x conversion in regular sequence */
    96. 

  96. #define ADC_RSQ0_RL                      BITS(20,23)                      /*!< regular channel sequence length */
    97. 

  97. 

  98. /* ADC_ISQ */
    99. 

  99. #define ADC_ISQ_ISQN                     BITS(0,4)                        /*!< n conversion in regular sequence */
    100. 

  100. #define ADC_ISQ_IL                       BITS(20,21)                      /*!< inserted sequence length */
    101. 

  101. 

  102. /* ADC_IDATAx x=0..3*/
    103. 

  103. #define ADC_IDATAX_IDATAN                BITS(0,15)                       /*!< inserted channel x conversion data  */
    104. 

  104. 

  105. /* ADC_RDATA */
    106. 

  106. #define ADC_RDATA_RDATA                  BITS(0,15)                       /*!< regular channel data */
    107. 

  107. 

  108. /* ADC_OVSAMPCTL */
    109. 

  109. #define ADC_OVSAMPCTL_OVSEN              BIT(0)                           /*!< oversampling enable */
    110. 

  110. #define ADC_OVSAMPCTL_OVSR               BITS(2,4)                        /*!< oversampling ratio */
    111. 

  111. #define ADC_OVSAMPCTL_OVSS               BITS(5,8)                        /*!< oversampling shift */
    112. 

  112. #define ADC_OVSAMPCTL_TOVS               BIT(9)                           /*!< triggered oversampling */
    113. 

  113. 

  114. /* constants definitions */
    115. 

  115. /* ADC flag definitions */
    116. 

  116. #define ADC_FLAG_WDE                     ADC_STAT_WDE                                /*!< analog watchdog event flag */
    117. 

  117. #define ADC_FLAG_EOC                     ADC_STAT_EOC                                /*!< end of group conversion flag */
    118. 

  118. #define ADC_FLAG_EOIC                    ADC_STAT_EOIC                               /*!< end of inserted channel group conversion flag */
    119. 

  119. #define ADC_FLAG_STIC                    ADC_STAT_STIC                               /*!< start flag of inserted channel group */
    120. 

  120. #define ADC_FLAG_STRC                    ADC_STAT_STRC                               /*!< start flag of regular channel group */
    121. 

  121. 

  122. /* adc_ctl0 register value */
    123. 

  123. #define CTL0_DISNUM(regval)              (BITS(13,15) & ((uint32_t)(regval) << 13))  /*!< number of conversions in discontinuous mode */
    124. 

  124. 

  125. /* ADC special function */
    126. 

  126. #define ADC_SCAN_MODE                    ADC_CTL0_SM                                 /*!< scan mode */
    127. 

  127. #define ADC_INSERTED_CHANNEL_AUTO        ADC_CTL0_ICA                                /*!< inserted channel group convert automatically */
    128. 

  128. #define ADC_CONTINUOUS_MODE              ADC_CTL1_CTN                                /*!< continuous mode */
    129. 

  129. 

  130. /* ADC data alignment */
    131. 

  131. #define ADC_DATAALIGN_RIGHT              ((uint32_t)0x00000000U)                     /*!< LSB alignment */
    132. 

  132. #define ADC_DATAALIGN_LEFT               ADC_CTL1_DAL                                /*!< MSB alignment */
    133. 

  133. 

  134. /* external trigger select for regular  channel */
    135. 

  135. #define CTL1_ETSRC(regval)               (BITS(17,19) & ((uint32_t)(regval) << 17))  
    136. 

  136. #define ADC_EXTTRIG_REGULAR_T0_CH0       CTL1_ETSRC(0)                               /*!< TIMER0 CH0 event select */
    137. 

  137. #define ADC_EXTTRIG_REGULAR_T0_CH1       CTL1_ETSRC(1)                               /*!< TIMER0 CH1 event select */
    138. 

  138. #define ADC_EXTTRIG_REGULAR_T0_CH2       CTL1_ETSRC(2)                               /*!< TIMER0 CH2 event select */
    139. 

  139. #define ADC_EXTTRIG_REGULAR_T1_CH1       CTL1_ETSRC(3)                               /*!< TIMER1 CH1 event select */
    140. 

  140. #define ADC_EXTTRIG_REGULAR_T2_TRGO      CTL1_ETSRC(4)                               /*!< TIMER2 TRGO event select */
    141. 

  141. #define ADC_EXTTRIG_REGULAR_T14_CH1      CTL1_ETSRC(5)                               /*!< TIMER14 CH1 event select */
    142. 

  142. #define ADC_EXTTRIG_REGULAR_EXTI_11      CTL1_ETSRC(6)                               /*!< external interrupt line 11 */
    143. 

  143. #define ADC_EXTTRIG_REGULAR_NONE         CTL1_ETSRC(7)                               /*!< software trigger */
    144. 

  144. 

  145. /* external trigger select for inserted channel */
    146. 

  146. #define CTL1_ETSIC(regval)               (BITS(12,14) & ((uint32_t)(regval) << 12))  
    147. 

  147. #define ADC_EXTTRIG_INSERTED_T0_TRGO     CTL1_ETSIC(0)                               /*!< TIMER0 TRGO event select */
    148. 

  148. #define ADC_EXTTRIG_INSERTED_T0_CH3      CTL1_ETSIC(1)                               /*!< TIMER0 CH3 event select */
    149. 

  149. #define ADC_EXTTRIG_INSERTED_T1_TRGO     CTL1_ETSIC(2)                               /*!< TIMER1 TRGO event select */
    150. 

  150. #define ADC_EXTTRIG_INSERTED_T1_CH0      CTL1_ETSIC(3)                               /*!< TIMER1 CH0 event select */
    151. 

  151. #define ADC_EXTTRIG_INSERTED_T2_CH3      CTL1_ETSIC(4)                               /*!< TIMER2 CH3 event select */
    152. 

  152. #define ADC_EXTTRIG_INSERTED_T14_TRGO    CTL1_ETSIC(5)                               /*!< TIMER14 TRGO event select */
    153. 

  153. #define ADC_EXTTRIG_INSERTED_EXTI_15     CTL1_ETSIC(6)                               /*!< external interrupt line 15 */
    154. 

  154. #define ADC_EXTTRIG_INSERTED_NONE        CTL1_ETSIC(7)                               /*!< software trigger */
    155. 

  155. 

  156. /* adc_samptx register value */
    157. 

  157. #define SAMPTX_SPT(regval)               (BITS(0,2) & ((uint32_t)(regval) << 0))     
    158. 

  158. #define ADC_SAMPLETIME_1POINT5           SAMPTX_SPT(0)                               /*!< 1.5 sampling cycles */
    159. 

  159. #define ADC_SAMPLETIME_7POINT5           SAMPTX_SPT(1)                               /*!< 7.5 sampling cycles */
    160. 

  160. #define ADC_SAMPLETIME_13POINT5          SAMPTX_SPT(2)                               /*!< 13.5 sampling cycles */
    161. 

  161. #define ADC_SAMPLETIME_28POINT5          SAMPTX_SPT(3)                               /*!< 28.5 sampling cycles */
    162. 

  162. #define ADC_SAMPLETIME_41POINT5          SAMPTX_SPT(4)                               /*!< 41.5 sampling cycles */
    163. 

  163. #define ADC_SAMPLETIME_55POINT5          SAMPTX_SPT(5)                               /*!< 55.5 sampling cycles */
    164. 

  164. #define ADC_SAMPLETIME_71POINT5          SAMPTX_SPT(6)                               /*!< 71.5 sampling cycles */
    165. 

  165. #define ADC_SAMPLETIME_239POINT5         SAMPTX_SPT(7)                               /*!< 239.5 sampling cycles */
    166. 

  166. 

  167. /* ADC data offset for inserted channel x*/
    168. 

  168. #define IOFFX_IOFF(regval)               (BITS(0,11) & ((uint32_t)(regval) << 0))    
    169. 

  169. 

  170. /* ADC analog watchdog high threshold  */
    171. 

  171. #define WDHT_WDHT(regval)                (BITS(0,11) & ((uint32_t)(regval) << 0))    
    172. 

  172. 

  173. /* ADC analog watchdog low  threshold */
    174. 

  174. #define WDLT_WDLT(regval)                (BITS(0,11) & ((uint32_t)(regval) << 0))    
    175. 

  175. 

  176. /* ADC regular channel group length */
    177. 

  177. #define RSQ0_RL(regval)                  (BITS(20,23) & ((uint32_t)(regval) << 20))  
    178. 

  178. 

  179. /* ADC inserted channel group length */
    180. 

  180. #define ISQ_IL(regval)                   (BITS(20,21) & ((uint32_t)(regval) << 20))  
    181. 

  181. 

  182. /* ADC resolution definitions */
    183. 

  183. #define CTL0_DRES(regval)                (BITS(24,25) & ((regval) << 24))            /*!< ADC resolution */
    184. 

  184. #define ADC_RESOLUTION_12B               CTL0_DRES(0)                                /*!< 12-bit ADC resolution */
    185. 

  185. #define ADC_RESOLUTION_10B               CTL0_DRES(1)                                /*!< 10-bit ADC resolution */
    186. 

  186. #define ADC_RESOLUTION_8B                CTL0_DRES(2)                                /*!< 8-bit ADC resolution */
    187. 

  187. #define ADC_RESOLUTION_6B                CTL0_DRES(3)                                /*!< 6-bit ADC resolution */
    188. 

  188. 

  189. /* ADC oversampling shift */
    190. 

  190. #define OVSAMPCTL_OVSS(regval)           (BITS(5,8) & ((uint32_t)(regval) << 5))     
    191. 

  191. #define ADC_OVERSAMPLING_SHIFT_NONE      OVSAMPCTL_OVSS(0)                           /*!< no oversampling shift */
    192. 

  192. #define ADC_OVERSAMPLING_SHIFT_1B        OVSAMPCTL_OVSS(1)                           /*!< 1-bit oversampling shift */
    193. 

  193. #define ADC_OVERSAMPLING_SHIFT_2B        OVSAMPCTL_OVSS(2)                           /*!< 2-bit oversampling shift */
    194. 

  194. #define ADC_OVERSAMPLING_SHIFT_3B        OVSAMPCTL_OVSS(3)                           /*!< 3-bit oversampling shift */
    195. 

  195. #define ADC_OVERSAMPLING_SHIFT_4B        OVSAMPCTL_OVSS(4)                           /*!< 4-bit oversampling shift */
    196. 

  196. #define ADC_OVERSAMPLING_SHIFT_5B        OVSAMPCTL_OVSS(5)                           /*!< 5-bit oversampling shift */
    197. 

  197. #define ADC_OVERSAMPLING_SHIFT_6B        OVSAMPCTL_OVSS(6)                           /*!< 6-bit oversampling shift */
    198. 

  198. #define ADC_OVERSAMPLING_SHIFT_7B        OVSAMPCTL_OVSS(7)                           /*!< 7-bit oversampling shift */
    199. 

  199. #define ADC_OVERSAMPLING_SHIFT_8B        OVSAMPCTL_OVSS(8)                           /*!< 8-bit oversampling shift */
    200. 

  200. 

  201. /* ADC oversampling ratio */
    202. 

  202. #define OVSAMPCTL_OVSR(regval)           (BITS(2,4) & ((uint32_t)(regval) << 2))     
    203. 

  203. #define ADC_OVERSAMPLING_RATIO_MUL2      OVSAMPCTL_OVSR(0)                           /*!< oversampling ratio multiple 2 */
    204. 

  204. #define ADC_OVERSAMPLING_RATIO_MUL4      OVSAMPCTL_OVSR(1)                           /*!< oversampling ratio multiple 4 */
    205. 

  205. #define ADC_OVERSAMPLING_RATIO_MUL8      OVSAMPCTL_OVSR(2)                           /*!< oversampling ratio multiple 8 */
    206. 

  206. #define ADC_OVERSAMPLING_RATIO_MUL16     OVSAMPCTL_OVSR(3)                           /*!< oversampling ratio multiple 16 */
    207. 

  207. #define ADC_OVERSAMPLING_RATIO_MUL32     OVSAMPCTL_OVSR(4)                           /*!< oversampling ratio multiple 32 */
    208. 

  208. #define ADC_OVERSAMPLING_RATIO_MUL64     OVSAMPCTL_OVSR(5)                           /*!< oversampling ratio multiple 64 */
    209. 

  209. #define ADC_OVERSAMPLING_RATIO_MUL128    OVSAMPCTL_OVSR(6)                           /*!< oversampling ratio multiple 128 */
    210. 

  210. #define ADC_OVERSAMPLING_RATIO_MUL256    OVSAMPCTL_OVSR(7)                           /*!< oversampling ratio multiple 256 */
    211. 

  211. 

  212. /* ADC triggered oversampling */
    213. 

  213. #define ADC_OVERSAMPLING_ALL_CONVERT     0U                                          /*!< all oversampled conversions for a channel are done consecutively after a trigger */
    214. 

  214. #define ADC_OVERSAMPLING_ONE_CONVERT     1U                                          /*!< each oversampled conversion for a channel needs a trigger */
    215. 

  215. 

  216. /* ADC channel group definitions */
    217. 

  217. #define ADC_REGULAR_CHANNEL              ((uint8_t)0x01U)                            /*!< ADC regular channel group */
    218. 

  218. #define ADC_INSERTED_CHANNEL             ((uint8_t)0x02U)                            /*!< ADC inserted channel group */
    219. 

  219. #define ADC_REGULAR_INSERTED_CHANNEL     ((uint8_t)0x03U)                            /*!< both regular and inserted channel group */
    220. 

  220. #define ADC_CHANNEL_DISCON_DISABLE       ((uint8_t)0x04U)                            /*!< disable discontinuous mode of regular & inserted channel */
    221. 

  221. 

  222. /* ADC inserted channel definitions */
    223. 

  223. #define ADC_INSERTED_CHANNEL_0           ((uint8_t)0x00U)                            /*!< ADC inserted channel 0 */
    224. 

  224. #define ADC_INSERTED_CHANNEL_1           ((uint8_t)0x01U)                            /*!< ADC inserted channel 1 */
    225. 

  225. #define ADC_INSERTED_CHANNEL_2           ((uint8_t)0x02U)                            /*!< ADC inserted channel 2 */
    226. 

  226. #define ADC_INSERTED_CHANNEL_3           ((uint8_t)0x03U)                            /*!< ADC inserted channel 3 */
    227. 

  227. 

  228. /* ADC channel definitions */
    229. 

  229. #define ADC_CHANNEL_0                    ((uint8_t)0x00U)                            /*!< ADC channel 0 */
    230. 

  230. #define ADC_CHANNEL_1                    ((uint8_t)0x01U)                            /*!< ADC channel 1 */
    231. 

  231. #define ADC_CHANNEL_2                    ((uint8_t)0x02U)                            /*!< ADC channel 2 */
    232. 

  232. #define ADC_CHANNEL_3                    ((uint8_t)0x03U)                            /*!< ADC channel 3 */
    233. 

  233. #define ADC_CHANNEL_4                    ((uint8_t)0x04U)                            /*!< ADC channel 4 */
    234. 

  234. #define ADC_CHANNEL_5                    ((uint8_t)0x05U)                            /*!< ADC channel 5 */
    235. 

  235. #define ADC_CHANNEL_6                    ((uint8_t)0x06U)                            /*!< ADC channel 6 */
    236. 

  236. #define ADC_CHANNEL_7                    ((uint8_t)0x07U)                            /*!< ADC channel 7 */
    237. 

  237. #define ADC_CHANNEL_8                    ((uint8_t)0x08U)                            /*!< ADC channel 8 */
    238. 

  238. #define ADC_CHANNEL_9                    ((uint8_t)0x09U)                            /*!< ADC channel 9 */
    239. 

  239. #define ADC_CHANNEL_10                   ((uint8_t)0x0AU)                            /*!< ADC channel 10 */
    240. 

  240. #define ADC_CHANNEL_11                   ((uint8_t)0x0BU)                            /*!< ADC channel 11 */
    241. 

  241. #define ADC_CHANNEL_12                   ((uint8_t)0x0CU)                            /*!< ADC channel 12 */
    242. 

  242. #define ADC_CHANNEL_13                   ((uint8_t)0x0DU)                            /*!< ADC channel 13 */
    243. 

  243. #define ADC_CHANNEL_14                   ((uint8_t)0x0EU)                            /*!< ADC channel 14 */
    244. 

  244. #define ADC_CHANNEL_15                   ((uint8_t)0x0FU)                            /*!< ADC channel 15 */
    245. 

  245. #define ADC_CHANNEL_16                   ((uint8_t)0x10U)                            /*!< ADC channel 16 */
    246. 

  246. #define ADC_CHANNEL_17                   ((uint8_t)0x11U)                            /*!< ADC channel 17 */
    247. 

  247. #define ADC_CHANNEL_18                   ((uint8_t)0x12U)                            /*!< ADC channel 18 */
    248. 

  248. 

  249. /* ADC interrupt definitions */
    250. 

  250. #define ADC_INT_WDE                      ADC_STAT_WDE                                /*!< analog watchdog event interrupt */
    251. 

  251. #define ADC_INT_EOC                      ADC_STAT_EOC                                /*!< end of group conversion interrupt */
    252. 

  252. #define ADC_INT_EOIC                     ADC_STAT_EOIC                               /*!< end of inserted group conversion interrupt */
    253. 

  253. 

  254. /* ADC interrupt flag */
    255. 

  255. #define ADC_INT_FLAG_WDE                 ADC_STAT_WDE                                /*!< analog watchdog event interrupt flag */
    256. 

  256. #define ADC_INT_FLAG_EOC                 ADC_STAT_EOC                                /*!< end of group conversion interrupt flag */
    257. 

  257. #define ADC_INT_FLAG_EOIC                ADC_STAT_EOIC                               /*!< end of inserted group conversion interrupt flag */
    258. 

  258. 

  259. /* function declarations */
    260. 

  260. /* reset ADC */
    261. 

  261. void adc_deinit(void);
    262. 

  262. /* enable ADC interface */
    263. 

  263. void adc_enable(void);
    264. 

  264. /* disable ADC interface */
    265. 

  265. void adc_disable(void);
    266. 

  266. 

  267. /* ADC calibration and reset calibration */
    268. 

  268. void adc_calibration_enable(void);
    269. 

  269. /* enable DMA request */
    270. 

  270. void adc_dma_mode_enable(void);
    271. 

  271. /* disable DMA request */
    272. 

  272. void adc_dma_mode_disable(void);
    273. 

  273. 

  274. /* enable the temperature sensor and Vrefint channel */
    275. 

  275. void adc_tempsensor_vrefint_enable(void);
    276. 

  276. /* disable the temperature sensor and Vrefint channel */
    277. 

  277. void adc_tempsensor_vrefint_disable(void);
    278. 

  278. /* enable the vbat channel */
    279. 

  279. void adc_vbat_enable(void);
    280. 

  280. /* disable the vbat channel */
    281. 

  281. void adc_vbat_disable(void);
    282. 

  282. 

  283. /* configure ADC discontinuous mode */
    284. 

  284. void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length);
    285. 

  285. /* configure ADC special function */
    286. 

  286. void adc_special_function_config(uint32_t function, ControlStatus newvalue);
    287. 

  287. 

  288. /* configure ADC data alignment */
    289. 

  289. void adc_data_alignment_config(uint32_t data_alignment);
    290. 

  290. /* configure the length of regular channel group or inserted channel group */
    291. 

  291. void adc_channel_length_config(uint8_t channel_group, uint32_t length);
    292. 

  292. /* configure ADC regular channel */
    293. 

  293. void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
    294. 

  294. /* configure ADC inserted channel */
    295. 

  295. void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
    296. 

  296. /* configure ADC inserted channel offset */
    297. 

  297. void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset);
    298. 

  298. /* enable ADC external trigger */
    299. 

  299. void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue);
    300. 

  300. /* configure ADC external trigger source */
    301. 

  301. void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source);
    302. 

  302. /* enable ADC software trigger */
    303. 

  303. void adc_software_trigger_enable(uint8_t channel_group);
    304. 

  304. 

  305. /* read ADC regular group data register */
    306. 

  306. uint16_t adc_regular_data_read(void);
    307. 

  307. /* read ADC inserted group data register */
    308. 

  308. uint16_t adc_inserted_data_read(uint8_t inserted_channel);
    309. 

  309. 

  310. /* get the ADC flag bits */
    311. 

  311. FlagStatus adc_flag_get(uint32_t flag);
    312. 

  312. /* clear the ADC flag bits */
    313. 

  313. void adc_flag_clear(uint32_t flag);
    314. 

  314. /* get the ADC interrupt bits */
    315. 

  315. FlagStatus adc_interrupt_flag_get(uint32_t flag);
    316. 

  316. /* clear the ADC flag */
    317. 

  317. void adc_interrupt_flag_clear(uint32_t flag);
    318. 

  318. /* enable ADC interrupt */
    319. 

  319. void adc_interrupt_enable(uint32_t interrupt);
    320. 

  320. /* disable ADC interrupt */
    321. 

  321. void adc_interrupt_disable(uint32_t interrupt);
    322. 

  322. 

  323. /* configure ADC analog watchdog single channel */
    324. 

  324. void adc_watchdog_single_channel_enable(uint8_t channel);
    325. 

  325. /* configure ADC analog watchdog group channel */
    326. 

  326. void adc_watchdog_group_channel_enable(uint8_t channel_group);
    327. 

  327. /* disable ADC analog watchdog */
    328. 

  328. void adc_watchdog_disable(void);
    329. 

  329. /* configure ADC analog watchdog threshold */
    330. 

  330. void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold);
    331. 

  331. 

  332. /* configure ADC resolution */
    333. 

  333. void adc_resolution_config(uint32_t resolution);
    334. 

  334. /* configure ADC oversample mode */
    335. 

  335. void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio);
    336. 

  336. /* enable ADC oversample mode */
    337. 

  337. void adc_oversample_mode_enable(void);
    338. 

  338. /* disable ADC oversample mode */
    339. 

  339. void adc_oversample_mode_disable(void);
    340. 

  340. 

  341. #endif /* GD32F3X0_ADC_H */
    342.