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GD32F3x0_standard_peripheral
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gd32f3x0_tsi.h

gd32f3x0_tsi.h 25 KB
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  1. /*!
    2. 

  2.     \file  gd32f3x0_tsi.h
    3. 

  3.     \brief definitions for the TSI
    4. 

  4. */
    5. 

  5. 

  6. /*
    7. 

  7.     Copyright (C) 2017 GigaDevice
    8. 

  8. 

  9.     2017-06-06, V1.0.0, firmware for GD32F3x0
    10. 

  10. */
    11. 

  11. 

  12. #ifndef GD32F3X0_TSI_H
    13. 

  13. #define GD32F3X0_TSI_H
    14. 

  14. 

  15. #include "gd32f3x0.h"
    16. 

  16. 

  17. /* TSI definitions */
    18. 

  18. #define TSI                     TSI_BASE                /*!< TSI base address */
    19. 

  19. 

  20. /* registers definitions */
    21. 

  21. #define TSI_CTL0                REG32(TSI + 0x00U)      /*!< TSI control register0 */
    22. 

  22. #define TSI_INTEN               REG32(TSI + 0x04U)      /*!< TSI interrupt enable register */
    23. 

  23. #define TSI_INTC                REG32(TSI + 0x08U)      /*!< TSI interrupt flag clear register */
    24. 

  24. #define TSI_INTF                REG32(TSI + 0x0CU)      /*!< TSI interrupt flag register */
    25. 

  25. #define TSI_PHM                 REG32(TSI + 0x10U)      /*!< TSI pin hysteresis mode register */
    26. 

  26. #define TSI_ASW                 REG32(TSI + 0x18U)      /*!< TSI analog switch register */
    27. 

  27. #define TSI_SAMPCFG             REG32(TSI + 0x20U)      /*!< TSI sample configuration register */
    28. 

  28. #define TSI_CHCFG               REG32(TSI + 0x28U)      /*!< TSI channel configuration register */
    29. 

  29. #define TSI_GCTL                REG32(TSI + 0x30U)      /*!< TSI group control register */
    30. 

  30. #define TSI_G0CYCN              REG32(TSI + 0x34U)      /*!< TSI group 0 cycle number register */
    31. 

  31. #define TSI_G1CYCN              REG32(TSI + 0x38U)      /*!< TSI group 1 cycle number register */
    32. 

  32. #define TSI_G2CYCN              REG32(TSI + 0x3CU)      /*!< TSI group 2 cycle number register */
    33. 

  33. #define TSI_G3CYCN              REG32(TSI + 0x40U)      /*!< TSI group 3 cycle number register */
    34. 

  34. #define TSI_G4CYCN              REG32(TSI + 0x44U)      /*!< TSI group 4 cycle number register */
    35. 

  35. #define TSI_G5CYCN              REG32(TSI + 0x48U)      /*!< TSI group 5 cycle number register */
    36. 

  36. #define TSI_CTL1                REG32(TSI + 0x300U)     /*!< TSI control registers1 */
    37. 

  37. 

  38. /* bits definitions */
    39. 

  39. /* TSI_CTL0 */
    40. 

  40. #define TSI_CTL0_TSIEN          BIT(0)                  /*!< TSI enable */
    41. 

  41. #define TSI_CTL0_TSIS           BIT(1)                  /*!< TSI start */
    42. 

  42. #define TSI_CTL0_TRGMOD         BIT(2)                  /*!< trigger mode selection */
    43. 

  43. #define TSI_CTL0_EGSEL          BIT(3)                  /*!< edge selection */
    44. 

  44. #define TSI_CTL0_PINMOD         BIT(4)                  /*!< pin mode */
    45. 

  45. #define TSI_CTL0_MCN            BITS(5,7)               /*!< max cycle number of a sequence */
    46. 

  46. #define TSI_CTL0_CTCDIV         BITS(12,14)             /*!< CTCLK clock division factor */
    47. 

  47. #define TSI_CTL0_ECDIV          BIT(15)                 /*!< ECCLK clock division factor */
    48. 

  48. #define TSI_CTL0_ECEN           BIT(16)                 /*!< extend charge state enable */
    49. 

  49. #define TSI_CTL0_ECDT           BITS(17,23)             /*!< extend charge State maximum duration time */
    50. 

  50. #define TSI_CTL0_CTDT           BITS(24,27)             /*!< charge transfer state duration time */
    51. 

  51. #define TSI_CTL0_CDT            BITS(28,31)             /*!< charge state duration time */
    52. 

  52. 

  53. /* TSI_INTEN */
    54. 

  54. #define TSI_INTEN_CTCFIE        BIT(0)                  /*!< charge transfer complete flag interrupt enable */
    55. 

  55. #define TSI_INTEN_MNERRIE       BIT(1)                  /*!< max cycle number error interrupt enable */
    56. 

  56. 

  57. /* TSI_INTC */
    58. 

  58. #define TSI_INTC_CCTCF          BIT(0)                  /*!< clear charge transfer complete flag */
    59. 

  59. #define TSI_INTC_CMNERR         BIT(1)                  /*!< clear max cycle number error */
    60. 

  60. 

  61. /* TSI_INTF */
    62. 

  62. #define TSI_INTF_CTCF           BIT(0)                  /*!< charge transfer complete flag */
    63. 

  63. #define TSI_INTF_MNERR          BIT(1)                  /*!< max cycle number error */
    64. 

  64. 

  65. /* TSI interrupt enable bit */
    66. 

  66. #define TSI_INT_CCTCF           TSI_INTEN_CTCFIE        /*!< charge transfer complete flag interrupt enable */
    67. 

  67. #define TSI_INT_MNERR           TSI_INTEN_MNERRIE       /*!< max cycle number error interrupt enable */
    68. 

  68. 

  69. /* I2C interrupt flags */
    70. 

  70. #define TSI_INT_FLAG_CTCF       TSI_INTF_CTCF           /*!< charge transfer complete flag */
    71. 

  71. #define TSI_INT_FLAG_MNERR      TSI_INTF_MNERR          /*!< max cycle number error */
    72. 

  72. 

  73. /* I2C interrupt clear flags */
    74. 

  74. #define TSI_INT_FLAG_CTCF_CLR   TSI_INTC_CCTCF           /*!< clear charge transfer complete flag */
    75. 

  75. #define TSI_INT_FLAG_MNERR_CLR  TSI_INTC_CMNERR          /*!< clear max cycle number error */
    76. 

  76. 

  77. /* I2C flags */
    78. 

  78. #define TSI_FLAG_CTCF           TSI_INTF_CTCF           /*!< charge transfer complete flag */
    79. 

  79. #define TSI_FLAG_MNERR          TSI_INTF_MNERR          /*!< max cycle number error */
    80. 

  80. 

  81. /* I2C clear flags */
    82. 

  82. #define TSI_FLAG_CTCF_CLR       TSI_INTC_CCTCF           /*!< clear charge transfer complete flag */
    83. 

  83. #define TSI_FLAG_MNERR_CLR      TSI_INTC_CMNERR          /*!< clear max cycle number error */
    84. 

  84. 

  85. /* TSI_PHM */
    86. 

  86. #define TSI_PHM_G0P0            BIT(0)                  /*!< pin G0P0 Schmitt trigger hysteresis state */
    87. 

  87. #define TSI_PHM_G0P1            BIT(1)                  /*!< pin G0P1 Schmitt trigger hysteresis state */
    88. 

  88. #define TSI_PHM_G0P2            BIT(2)                  /*!< pin G0P2 Schmitt trigger hysteresis state */
    89. 

  89. #define TSI_PHM_G0P3            BIT(3)                  /*!< pin G0P3 Schmitt trigger hysteresis state */
    90. 

  90. #define TSI_PHM_G1P0            BIT(4)                  /*!< pin G1P0 Schmitt trigger hysteresis state */
    91. 

  91. #define TSI_PHM_G1P1            BIT(5)                  /*!< pin G1P1 Schmitt trigger hysteresis state */
    92. 

  92. #define TSI_PHM_G1P2            BIT(6)                  /*!< pin G1P2 Schmitt trigger hysteresis state */
    93. 

  93. #define TSI_PHM_G1P3            BIT(7)                  /*!< pin G1P3 Schmitt trigger hysteresis state */
    94. 

  94. #define TSI_PHM_G2P0            BIT(8)                  /*!< pin G2P0 Schmitt trigger hysteresis state */
    95. 

  95. #define TSI_PHM_G2P1            BIT(9)                  /*!< pin G2P1 Schmitt trigger hysteresis state */
    96. 

  96. #define TSI_PHM_G2P2            BIT(10)                 /*!< pin G2P2 Schmitt trigger hysteresis state */
    97. 

  97. #define TSI_PHM_G2P3            BIT(11)                 /*!< pin G2P3 Schmitt trigger hysteresis state */
    98. 

  98. #define TSI_PHM_G3P0            BIT(12)                 /*!< pin G3P0 Schmitt trigger hysteresis state */
    99. 

  99. #define TSI_PHM_G3P1            BIT(13)                 /*!< pin G3P1 Schmitt trigger hysteresis state */
    100. 

  100. #define TSI_PHM_G3P2            BIT(14)                 /*!< pin G3P2 Schmitt trigger hysteresis state */
    101. 

  101. #define TSI_PHM_G3P3            BIT(15)                 /*!< pin G3P3 Schmitt trigger hysteresis state */
    102. 

  102. #define TSI_PHM_G4P0            BIT(16)                 /*!< pin G4P0 Schmitt trigger hysteresis state */
    103. 

  103. #define TSI_PHM_G4P1            BIT(17)                 /*!< pin G4P1 Schmitt trigger hysteresis state */
    104. 

  104. #define TSI_PHM_G4P2            BIT(18)                 /*!< pin G4P2 Schmitt trigger hysteresis state */
    105. 

  105. #define TSI_PHM_G4P3            BIT(19)                 /*!< pin G4P3 Schmitt trigger hysteresis state */
    106. 

  106. #define TSI_PHM_G5P0            BIT(20)                 /*!< pin G5P0 Schmitt trigger hysteresis state */
    107. 

  107. #define TSI_PHM_G5P1            BIT(21)                 /*!< pin G5P1 Schmitt trigger hysteresis state */
    108. 

  108. #define TSI_PHM_G5P2            BIT(22)                 /*!< pin G5P2 Schmitt trigger hysteresis state */
    109. 

  109. #define TSI_PHM_G5P3            BIT(23)                 /*!< pin G5P3 Schmitt trigger hysteresis state */
    110. 

  110. 

  111. /* TSI_ASW */
    112. 

  112. #define TSI_ASW_G0P0            BIT(0)                  /*!< pin G0P0 analog switch state */
    113. 

  113. #define TSI_ASW_G0P1            BIT(1)                  /*!< pin G0P1 analog switch state */
    114. 

  114. #define TSI_ASW_G0P2            BIT(2)                  /*!< pin G0P2 analog switch state */
    115. 

  115. #define TSI_ASW_G0P3            BIT(3)                  /*!< pin G0P3 analog switch state */
    116. 

  116. #define TSI_ASW_G1P0            BIT(4)                  /*!< pin G1P0 analog switch state */
    117. 

  117. #define TSI_ASW_G1P1            BIT(5)                  /*!< pin G1P1 analog switch state */
    118. 

  118. #define TSI_ASW_G1P2            BIT(6)                  /*!< pin G1P2 analog switch state */
    119. 

  119. #define TSI_ASW_G1P3            BIT(7)                  /*!< pin G1P3 analog switch state */
    120. 

  120. #define TSI_ASW_G2P0            BIT(8)                  /*!< pin G2P0 analog switch state */
    121. 

  121. #define TSI_ASW_G2P1            BIT(9)                  /*!< pin G2P1 analog switch state */
    122. 

  122. #define TSI_ASW_G2P2            BIT(10)                 /*!< pin G2P2 analog switch state */
    123. 

  123. #define TSI_ASW_G2P3            BIT(11)                 /*!< pin G2P3 analog switch state */
    124. 

  124. #define TSI_ASW_G3P0            BIT(12)                 /*!< pin G3P0 analog switch state */
    125. 

  125. #define TSI_ASW_G3P1            BIT(13)                 /*!< pin G3P1 analog switch state */
    126. 

  126. #define TSI_ASW_G3P2            BIT(14)                 /*!< pin G3P2 analog switch state */
    127. 

  127. #define TSI_ASW_G3P3            BIT(15)                 /*!< pin G3P3 analog switch state */
    128. 

  128. #define TSI_ASW_G4P0            BIT(16)                 /*!< pin G4P0 analog switch state */
    129. 

  129. #define TSI_ASW_G4P1            BIT(17)                 /*!< pin G4P1 analog switch state */
    130. 

  130. #define TSI_ASW_G4P2            BIT(18)                 /*!< pin G4P2 analog switch state */
    131. 

  131. #define TSI_ASW_G4P3            BIT(19)                 /*!< pin G4P3 analog switch state */
    132. 

  132. #define TSI_ASW_G5P0            BIT(20)                 /*!< pin G5P0 analog switch state */
    133. 

  133. #define TSI_ASW_G5P1            BIT(21)                 /*!< pin G5P1 analog switch state */
    134. 

  134. #define TSI_ASW_G5P2            BIT(22)                 /*!< pin G5P2 analog switch state */
    135. 

  135. #define TSI_ASW_G5P3            BIT(23)                 /*!< pin G5P3 analog switch state */
    136. 

  136. 

  137. /* TSI_SAMPCFG */
    138. 

  138. #define TSI_SAMPCFG_G0P0        BIT(0)                  /*!< pin G0P0 sample pin mode */
    139. 

  139. #define TSI_SAMPCFG_G0P1        BIT(1)                  /*!< pin G0P1 sample pin mode */
    140. 

  140. #define TSI_SAMPCFG_G0P2        BIT(2)                  /*!< pin G0P2 sample pin mode */
    141. 

  141. #define TSI_SAMPCFG_G0P3        BIT(3)                  /*!< pin G0P3 sample pin mode */
    142. 

  142. #define TSI_SAMPCFG_G1P0        BIT(4)                  /*!< pin G1P0 sample pin mode */
    143. 

  143. #define TSI_SAMPCFG_G1P1        BIT(5)                  /*!< pin G1P1 sample pin mode */
    144. 

  144. #define TSI_SAMPCFG_G1P2        BIT(6)                  /*!< pin G1P2 sample pin mode */
    145. 

  145. #define TSI_SAMPCFG_G1P3        BIT(7)                  /*!< pin G1P3 sample pin mode */
    146. 

  146. #define TSI_SAMPCFG_G2P0        BIT(8)                  /*!< pin G2P0 sample pin mode */
    147. 

  147. #define TSI_SAMPCFG_G2P1        BIT(9)                  /*!< pin G2P1 sample pin mode */
    148. 

  148. #define TSI_SAMPCFG_G2P2        BIT(10)                 /*!< pin G2P2 sample pin mode */
    149. 

  149. #define TSI_SAMPCFG_G2P3        BIT(11)                 /*!< pin G2P3 sample pin mode */
    150. 

  150. #define TSI_SAMPCFG_G3P0        BIT(12)                 /*!< pin G3P0 sample pin mode */
    151. 

  151. #define TSI_SAMPCFG_G3P1        BIT(13)                 /*!< pin G3P1 sample pin mode */
    152. 

  152. #define TSI_SAMPCFG_G3P2        BIT(14)                 /*!< pin G3P2 sample pin mode */
    153. 

  153. #define TSI_SAMPCFG_G3P3        BIT(15)                 /*!< pin G3P3 sample pin mode */
    154. 

  154. #define TSI_SAMPCFG_G4P0        BIT(16)                 /*!< pin G4P0 sample pin mode */
    155. 

  155. #define TSI_SAMPCFG_G4P1        BIT(17)                 /*!< pin G4P1 sample pin mode */
    156. 

  156. #define TSI_SAMPCFG_G4P2        BIT(18)                 /*!< pin G4P2 sample pin mode */
    157. 

  157. #define TSI_SAMPCFG_G4P3        BIT(19)                 /*!< pin G4P3 sample pin mode */
    158. 

  158. #define TSI_SAMPCFG_G5P0        BIT(20)                 /*!< pin G5P0 sample pin mode */
    159. 

  159. #define TSI_SAMPCFG_G5P1        BIT(21)                 /*!< pin G5P1 sample pin mode */
    160. 

  160. #define TSI_SAMPCFG_G5P2        BIT(22)                 /*!< pin G5P2 sample pin mode */
    161. 

  161. #define TSI_SAMPCFG_G5P3        BIT(23)                 /*!< pin G5P3 sample pin mode */
    162. 

  162. 

  163. /* TSI_CHCFG */
    164. 

  164. #define TSI_CHCFG_G0P0          BIT(0)                  /*!< pin G0P0 channel pin mode */
    165. 

  165. #define TSI_CHCFG_G0P1          BIT(1)                  /*!< pin G0P1 channel pin mode */
    166. 

  166. #define TSI_CHCFG_G0P2          BIT(2)                  /*!< pin G0P2 channel pin mode */
    167. 

  167. #define TSI_CHCFG_G0P3          BIT(3)                  /*!< pin G0P3 channel pin mode */
    168. 

  168. #define TSI_CHCFG_G1P0          BIT(4)                  /*!< pin G1P0 channel pin mode */
    169. 

  169. #define TSI_CHCFG_G1P1          BIT(5)                  /*!< pin G1P1 channel pin mode */
    170. 

  170. #define TSI_CHCFG_G1P2          BIT(6)                  /*!< pin G1P2 channel pin mode */
    171. 

  171. #define TSI_CHCFG_G1P3          BIT(7)                  /*!< pin G1P3 channel pin mode */
    172. 

  172. #define TSI_CHCFG_G2P0          BIT(8)                  /*!< pin G2P0 channel pin mode */
    173. 

  173. #define TSI_CHCFG_G2P1          BIT(9)                  /*!< pin G2P1 channel pin mode */
    174. 

  174. #define TSI_CHCFG_G2P2          BIT(10)                 /*!< pin G2P2 channel pin mode */
    175. 

  175. #define TSI_CHCFG_G2P3          BIT(11)                 /*!< pin G2P3 channel pin mode */
    176. 

  176. #define TSI_CHCFG_G3P0          BIT(12)                 /*!< pin G3P0 channel pin mode */
    177. 

  177. #define TSI_CHCFG_G3P1          BIT(13)                 /*!< pin G3P1 channel pin mode */
    178. 

  178. #define TSI_CHCFG_G3P2          BIT(14)                 /*!< pin G3P2 channel pin mode */
    179. 

  179. #define TSI_CHCFG_G3P3          BIT(15)                 /*!< pin G3P3 channel pin mode */
    180. 

  180. #define TSI_CHCFG_G4P0          BIT(16)                 /*!< pin G4P0 channel pin mode */
    181. 

  181. #define TSI_CHCFG_G4P1          BIT(17)                 /*!< pin G4P1 channel pin mode */
    182. 

  182. #define TSI_CHCFG_G4P2          BIT(18)                 /*!< pin G4P2 channel pin mode */
    183. 

  183. #define TSI_CHCFG_G4P3          BIT(19)                 /*!< pin G4P3 channel pin mode */
    184. 

  184. #define TSI_CHCFG_G5P0          BIT(20)                 /*!< pin G5P0 channel pin mode */
    185. 

  185. #define TSI_CHCFG_G5P1          BIT(21)                 /*!< pin G5P1 channel pin mode */
    186. 

  186. #define TSI_CHCFG_G5P2          BIT(22)                 /*!< pin G5P2 channel pin mode */
    187. 

  187. #define TSI_CHCFG_G5P3          BIT(23)                 /*!< pin G5P3 channel pin mode */
    188. 

  188. 

  189. /* TSI_GCTL */
    190. 

  190. #define TSI_GCTL_GE0            BIT(0)                  /*!< group0 enable */
    191. 

  191. #define TSI_GCTL_GE1            BIT(1)                  /*!< group1 enable */
    192. 

  192. #define TSI_GCTL_GE2            BIT(2)                  /*!< group2 enable */
    193. 

  193. #define TSI_GCTL_GE3            BIT(3)                  /*!< group3 enable */
    194. 

  194. #define TSI_GCTL_GE4            BIT(4)                  /*!< group4 enable */
    195. 

  195. #define TSI_GCTL_GE5            BIT(5)                  /*!< group5 enable */
    196. 

  196. #define TSI_GCTL_GC0            BIT(16)                 /*!< group0 complete */
    197. 

  197. #define TSI_GCTL_GC1            BIT(17)                 /*!< group1 complete */
    198. 

  198. #define TSI_GCTL_GC2            BIT(18)                 /*!< group2 complete */
    199. 

  199. #define TSI_GCTL_GC3            BIT(19)                 /*!< group3 complete */
    200. 

  200. #define TSI_GCTL_GC4            BIT(20)                 /*!< group4 complete */
    201. 

  201. #define TSI_GCTL_GC5            BIT(21)                 /*!< group5 complete */
    202. 

  202. 

  203. /* TSI_CTL1 */
    204. 

  204. #define TSI_CTL1_CTCDIV         BIT(24)                 /*!< CTCLK clock division factor */
    205. 

  205. #define TSI_CTL1_ECDIV          BITS(28,29)             /*!< ECCLK clock division factor */
    206. 

  206. 

  207. /* constants definitions */
    208. 

  208. /* CTCLK clock division factor */
    209. 

  209. #define TSI_CTCDIV_DIV1         ((uint32_t)0x00000000U) /*!< fCTCLK = fHCLK */
    210. 

  210. #define TSI_CTCDIV_DIV2         ((uint32_t)0x00000001U) /*!< fCTCLK = fHCLK/2 */
    211. 

  211. #define TSI_CTCDIV_DIV4         ((uint32_t)0x00000002U) /*!< fCTCLK = fHCLK/4 */
    212. 

  212. #define TSI_CTCDIV_DIV8         ((uint32_t)0x00000003U) /*!< fCTCLK = fHCLK/8 */
    213. 

  213. #define TSI_CTCDIV_DIV16        ((uint32_t)0x00000004U) /*!< fCTCLK = fHCLK/16 */
    214. 

  214. #define TSI_CTCDIV_DIV32        ((uint32_t)0x00000005U) /*!< fCTCLK = fHCLK/32 */
    215. 

  215. #define TSI_CTCDIV_DIV64        ((uint32_t)0x00000006U) /*!< fCTCLK = fHCLK/64 */
    216. 

  216. #define TSI_CTCDIV_DIV128       ((uint32_t)0x00000007U) /*!< fCTCLK = fHCLK/128 */
    217. 

  217. #define TSI_CTCDIV_DIV256       ((uint32_t)0x00000008U) /*!< fCTCLK = fHCLK/256 */
    218. 

  218. #define TSI_CTCDIV_DIV512       ((uint32_t)0x00000009U) /*!< fCTCLK = fHCLK/512 */
    219. 

  219. #define TSI_CTCDIV_DIV1024      ((uint32_t)0x0000000AU) /*!< fCTCLK = fHCLK/1024 */
    220. 

  220. #define TSI_CTCDIV_DIV2048      ((uint32_t)0x0000000BU) /*!< fCTCLK = fHCLK/2048 */
    221. 

  221. #define TSI_CTCDIV_DIV4096      ((uint32_t)0x0000000CU) /*!< fCTCLK = fHCLK/4096 */
    222. 

  222. #define TSI_CTCDIV_DIV8192      ((uint32_t)0x0000000DU) /*!< fCTCLK = fHCLK/8192 */
    223. 

  223. #define TSI_CTCDIV_DIV16384     ((uint32_t)0x0000000EU) /*!< fCTCLK = fHCLK/16384 */
    224. 

  224. #define TSI_CTCDIV_DIV32768     ((uint32_t)0x0000000FU) /*!< fCTCLK = fHCLK/32768 */
    225. 

  225. 

  226. /* charge transfer state duration Time */
    227. 

  227. #define CTL_CTDT(regval)        (BITS(24,27) & ((uint32_t)(regval) << 24U))
    228. 

  228. #define TSI_TRANSFER_1CTCLK     CTL_CTDT(0)             /*!< the duration time of transfer state is 1 CTCLK */
    229. 

  229. #define TSI_TRANSFER_2CTCLK     CTL_CTDT(1)             /*!< the duration time of transfer state is 2 CTCLK */
    230. 

  230. #define TSI_TRANSFER_3CTCLK     CTL_CTDT(2)             /*!< the duration time of transfer state is 3 CTCLK */
    231. 

  231. #define TSI_TRANSFER_4CTCLK     CTL_CTDT(3)             /*!< the duration time of transfer state is 4 CTCLK */
    232. 

  232. #define TSI_TRANSFER_5CTCLK     CTL_CTDT(4)             /*!< the duration time of transfer state is 5 CTCLK */
    233. 

  233. #define TSI_TRANSFER_6CTCLK     CTL_CTDT(5)             /*!< the duration time of transfer state is 6 CTCLK */
    234. 

  234. #define TSI_TRANSFER_7CTCLK     CTL_CTDT(6)             /*!< the duration time of transfer state is 7 CTCLK */
    235. 

  235. #define TSI_TRANSFER_8CTCLK     CTL_CTDT(7)             /*!< the duration time of transfer state is 8 CTCLK */
    236. 

  236. #define TSI_TRANSFER_9CTCLK     CTL_CTDT(8)             /*!< the duration time of transfer state is 9 CTCLK */
    237. 

  237. #define TSI_TRANSFER_10CTCLK    CTL_CTDT(9)             /*!< the duration time of transfer state is 10 CTCLK */
    238. 

  238. #define TSI_TRANSFER_11CTCLK    CTL_CTDT(10)            /*!< the duration time of transfer state is 11 CTCLK */
    239. 

  239. #define TSI_TRANSFER_12CTCLK    CTL_CTDT(11)            /*!< the duration time of transfer state is 12 CTCLK */
    240. 

  240. #define TSI_TRANSFER_13CTCLK    CTL_CTDT(12)            /*!< the duration time of transfer state is 13 CTCLK */
    241. 

  241. #define TSI_TRANSFER_14CTCLK    CTL_CTDT(13)            /*!< the duration time of transfer state is 14 CTCLK */
    242. 

  242. #define TSI_TRANSFER_15CTCLK    CTL_CTDT(14)            /*!< the duration time of transfer state is 15 CTCLK */
    243. 

  243. #define TSI_TRANSFER_16CTCLK    CTL_CTDT(15)            /*!< the duration time of transfer state is 16 CTCLK */
    244. 

  244. 

  245. /* charge state duration time */
    246. 

  246. #define CTL_CDT(regval)         (BITS(28,31) & ((uint32_t)(regval) << 28U))
    247. 

  247. #define TSI_CHARGE_1CTCLK       CTL_CDT(0)              /*!< the duration time of charge state is 1 CTCLK */
    248. 

  248. #define TSI_CHARGE_2CTCLK       CTL_CDT(1)              /*!< the duration time of charge state is 2 CTCLK */
    249. 

  249. #define TSI_CHARGE_3CTCLK       CTL_CDT(2)              /*!< the duration time of charge state is 3 CTCLK */
    250. 

  250. #define TSI_CHARGE_4CTCLK       CTL_CDT(3)              /*!< the duration time of charge state is 4 CTCLK */
    251. 

  251. #define TSI_CHARGE_5CTCLK       CTL_CDT(4)              /*!< the duration time of charge state is 5 CTCLK */
    252. 

  252. #define TSI_CHARGE_6CTCLK       CTL_CDT(5)              /*!< the duration time of charge state is 6 CTCLK */
    253. 

  253. #define TSI_CHARGE_7CTCLK       CTL_CDT(6)              /*!< the duration time of charge state is 7 CTCLK */
    254. 

  254. #define TSI_CHARGE_8CTCLK       CTL_CDT(7)              /*!< the duration time of charge state is 8 CTCLK */
    255. 

  255. #define TSI_CHARGE_9CTCLK       CTL_CDT(8)              /*!< the duration time of charge state is 9 CTCLK */
    256. 

  256. #define TSI_CHARGE_10CTCLK      CTL_CDT(9)              /*!< the duration time of charge state is 10 CTCLK */
    257. 

  257. #define TSI_CHARGE_11CTCLK      CTL_CDT(10)             /*!< the duration time of charge state is 11 CTCLK */
    258. 

  258. #define TSI_CHARGE_12CTCLK      CTL_CDT(11)             /*!< the duration time of charge state is 12 CTCLK */
    259. 

  259. #define TSI_CHARGE_13CTCLK      CTL_CDT(12)             /*!< the duration time of charge state is 13 CTCLK */
    260. 

  260. #define TSI_CHARGE_14CTCLK      CTL_CDT(13)             /*!< the duration time of charge state is 14 CTCLK */
    261. 

  261. #define TSI_CHARGE_15CTCLK      CTL_CDT(14)             /*!< the duration time of charge state is 15 CTCLK */
    262. 

  262. #define TSI_CHARGE_16CTCLK      CTL_CDT(15)             /*!< the duration time of charge state is 16 CTCLK */
    263. 

  263. 

  264. /* max cycle number of a sequence */
    265. 

  265. #define CTL_MCN(regval)         (BITS(5,7) & ((uint32_t)(regval) << 5U))
    266. 

  266. #define TSI_MAXNUM255           CTL_MCN(0)              /*!< the max cycle number of a sequence is 255 */
    267. 

  267. #define TSI_MAXNUM511           CTL_MCN(1)              /*!< the max cycle number of a sequence is 511 */
    268. 

  268. #define TSI_MAXNUM1023          CTL_MCN(2)              /*!< the max cycle number of a sequence is 1023 */
    269. 

  269. #define TSI_MAXNUM2047          CTL_MCN(3)              /*!< the max cycle number of a sequence is 2047 */
    270. 

  270. #define TSI_MAXNUM4095          CTL_MCN(4)              /*!< the max cycle number of a sequence is 4095 */
    271. 

  271. #define TSI_MAXNUM8191          CTL_MCN(5)              /*!< the max cycle number of a sequence is 8191 */
    272. 

  272. #define TSI_MAXNUM16383         CTL_MCN(6)              /*!< the max cycle number of a sequence is 16383 */
    273. 

  273. 

  274. /* ECCLK clock division factor */
    275. 

  275. #define TSI_EXTEND_DIV1         ((uint32_t)0x00000000U) /*!< fECCLK = fHCLK */
    276. 

  276. #define TSI_EXTEND_DIV2         ((uint32_t)0x00000001U) /*!< fECCLK = fHCLK/2 */
    277. 

  277. #define TSI_EXTEND_DIV3         ((uint32_t)0x00000002U) /*!< fECCLK = fHCLK/3 */
    278. 

  278. #define TSI_EXTEND_DIV4         ((uint32_t)0x00000003U) /*!< fECCLK = fHCLK/4 */
    279. 

  279. #define TSI_EXTEND_DIV5         ((uint32_t)0x00000004U) /*!< fECCLK = fHCLK/5 */
    280. 

  280. #define TSI_EXTEND_DIV6         ((uint32_t)0x00000005U) /*!< fECCLK = fHCLK/6 */
    281. 

  281. #define TSI_EXTEND_DIV7         ((uint32_t)0x00000006U) /*!< fECCLK = fHCLK/7 */
    282. 

  282. #define TSI_EXTEND_DIV8         ((uint32_t)0x00000007U) /*!< fECCLK = fHCLK/8 */
    283. 

  283. 

  284. /* extend charge state maximum duration time */
    285. 

  285. #define TSI_EXTENDMAX(regval)   (BITS(17,23) & ((uint32_t)(regval) << 17U)) /* value range 1..128,extend charge state maximum duration time */
    286. 

  286. 

  287. /* hardware trigger mode */
    288. 

  288. #define TSI_FALLING_TRIGGER     0x00U                   /*!< falling edge trigger TSI charge transfer sequence */
    289. 

  289. #define TSI_RISING_TRIGGER      0x01U                   /*!< rising edge trigger TSI charge transfer sequence */
    290. 

  290. 

  291. /* pin mode */
    292. 

  292. #define TSI_OUTPUT_LOW          0x00U                   /*!< TSI pin will output low when IDLE */
    293. 

  293. #define TSI_INPUT_FLOATING      0x01U                   /*!< TSI pin will keep input_floating when IDLE */
    294. 

  294. 

  295. /* function declarations */
    296. 

  296. /* reset TSI peripheral */
    297. 

  297. void tsi_deinit(void);
    298. 

  298. /* initialize TSI plus prescaler,charge plus,transfer plus,max cycle number */
    299. 

  299. void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number);
    300. 

  300. /* enable TSI module */
    301. 

  301. void tsi_enable(void);
    302. 

  302. /* disable TSI module */
    303. 

  303. void tsi_disable(void);
    304. 

  304. /* enable sample pin */
    305. 

  305. void tsi_sample_pin_enable(uint32_t sample);
    306. 

  306. /* disable sample pin */
    307. 

  307. void tsi_sample_pin_disable(uint32_t sample);
    308. 

  308. /* enable channel pin */
    309. 

  309. void tsi_channel_pin_enable(uint32_t channel);
    310. 

  310. /* disable channel pin */
    311. 

  311. void tsi_channel_pin_disable(uint32_t channel);
    312. 

  312. 

  313. /* configure TSI triggering by software */
    314. 

  314. void tsi_sofeware_mode_config(void);
    315. 

  315. /* start a charge-transfer sequence when TSI is in software trigger mode */
    316. 

  316. void tsi_software_start(void);
    317. 

  317. /* stop a charge-transfer sequence when TSI is in software trigger mode */
    318. 

  318. void tsi_software_stop(void);
    319. 

  319. /* configure TSI triggering by hardware */
    320. 

  320. void tsi_hardware_mode_config(uint8_t trigger_edge);
    321. 

  321. /* configure TSI pin mode when charge-transfer sequence is IDLE */
    322. 

  322. void tsi_pin_mode_config(uint8_t pin_mode);
    323. 

  323. /* configure extend charge state */
    324. 

  324. void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration);
    325. 

  325. 

  326. /* configure charge plus and transfer plus */
    327. 

  327. void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration);
    328. 

  328. /* configure the max cycle number of a charge-transfer sequence */
    329. 

  329. void tsi_max_number_config(uint32_t max_number);
    330. 

  330. /* switch on hysteresis pin */
    331. 

  331. void tsi_hysteresis_on(uint32_t group_pin);
    332. 

  332. /* switch off hysteresis pin */
    333. 

  333. void tsi_hysteresis_off(uint32_t group_pin);
    334. 

  334. /* switch on analog pin */
    335. 

  335. void tsi_analog_on(uint32_t group_pin);
    336. 

  336. /* switch off analog pin */
    337. 

  337. void tsi_analog_off(uint32_t group_pin);
    338. 

  338. 

  339. /* enable TSI interrupt */
    340. 

  340. void tsi_interrupt_enable(uint32_t source);
    341. 

  341. /* disable TSI interrupt */
    342. 

  342. void tsi_interrupt_disable(uint32_t source);
    343. 

  343. /* clear interrupt flag */
    344. 

  344. void tsi_interrupt_flag_clear(uint32_t flag);
    345. 

  345. /* get TSI interrupt flag */
    346. 

  346. FlagStatus tsi_interrupt_flag_get(uint32_t flag);
    347. 

  347. 

  348. /* clear flag */
    349. 

  349. void tsi_flag_clear(uint32_t flag);
    350. 

  350. /* get flag */
    351. 

  351. FlagStatus tsi_flag_get(uint32_t flag);
    352. 

  352. 

  353. /* enbale group */
    354. 

  354. void tsi_group_enable(uint32_t group);
    355. 

  355. /* disbale group */
    356. 

  356. void tsi_group_disable(uint32_t group);
    357. 

  357. /* get group complete status */
    358. 

  358. FlagStatus tsi_group_status_get(uint32_t group);
    359. 

  359. /* get the cycle number for group0 as soon as a charge-transfer sequence completes */
    360. 

  360. uint16_t tsi_group0_cycle_get(void);
    361. 

  361. /* get the cycle number for group1 as soon as a charge-transfer sequence completes */
    362. 

  362. uint16_t tsi_group1_cycle_get(void);
    363. 

  363. /* get the cycle number for group2 as soon as a charge-transfer sequence completes */
    364. 

  364. uint16_t tsi_group2_cycle_get(void);
    365. 

  365. /* get the cycle number for group3 as soon as a charge-transfer sequence completes */
    366. 

  366. uint16_t tsi_group3_cycle_get(void);
    367. 

  367. /* get the cycle number for group4 as soon as a charge-transfer sequence completes */
    368. 

  368. uint16_t tsi_group4_cycle_get(void);
    369. 

  369. /* get the cycle number for group5 as soon as a charge-transfer sequence completes */
    370. 

  370. uint16_t tsi_group5_cycle_get(void);
    371. 

  371. 

  372. #endif /* GD32F3X0_TSI_H */
    373.