gd32f3x0_dbg.c 4.9 KB

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  1. /*!
  2. \file gd32f3x0_dbg.c
  3. \brief DBG driver
  4. */
  5. /*
  6. Copyright (C) 2017 GigaDevice
  7. 2017-06-06, V1.0.0, firmware for GD32F3x0
  8. */
  9. #include "gd32f3x0_dbg.h"
  10. #define DBG_RESET_VAL 0x00000000U
  11. /*!
  12. \brief deinitialize the DBG
  13. \param[in] none
  14. \param[out] none
  15. \retval none
  16. */
  17. void dbg_deinit(void)
  18. {
  19. DBG_CTL0 = DBG_RESET_VAL;
  20. DBG_CTL1 = DBG_RESET_VAL;
  21. }
  22. /*!
  23. \brief read DBG_ID code register
  24. \param[in] none
  25. \param[out] none
  26. \retval DBG_ID code
  27. */
  28. uint32_t dbg_id_get(void)
  29. {
  30. return DBG_ID;
  31. }
  32. /*!
  33. \brief enable low power behavior when the mcu is in debug mode
  34. \param[in] dbg_low_power:
  35. this parameter can be any combination of the following values:
  36. \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
  37. \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
  38. \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
  39. \param[out] none
  40. \retval none
  41. */
  42. void dbg_low_power_enable(uint32_t dbg_low_power)
  43. {
  44. DBG_CTL0 |= dbg_low_power;
  45. }
  46. /*!
  47. \brief disable low power behavior when the mcu is in debug mode
  48. \param[in] dbg_low_power:
  49. this parameter can be any combination of the following values:
  50. \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
  51. \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
  52. \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
  53. \param[out] none
  54. \retval none
  55. */
  56. void dbg_low_power_disable(uint32_t dbg_low_power)
  57. {
  58. DBG_CTL0 &= ~dbg_low_power;
  59. }
  60. /*!
  61. \brief enable peripheral behavior when the mcu is in debug mode
  62. \param[in] dbg_periph: DBG peripheral
  63. only one parameter can be selected which is shown as below:
  64. \arg DBG_SLEEP_HOLD: keep debugger connection during sleep mode
  65. \arg DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode
  66. \arg DBG_STANDBY_HOLD: keep debugger connection during standby mode
  67. \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
  68. \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
  69. \arg DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted
  70. \arg DBG_TIMER1_HOLD: TIMER1 counter kept when core is halted
  71. \arg DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted
  72. \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
  73. \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
  74. \arg DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted
  75. \arg DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted
  76. \arg DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted
  77. \arg DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted
  78. \arg DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted
  79. \arg DBG_I2C2_HOLD: hold I2C2 SMBUS when core is halted
  80. \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
  81. \param[out] none
  82. \retval none
  83. */
  84. void dbg_periph_enable(dbg_periph_enum dbg_periph)
  85. {
  86. DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
  87. }
  88. /*!
  89. \brief disable peripheral behavior when the mcu is in debug mode
  90. \param[in] dbg_periph: DBG peripheral
  91. only one parameter can be selected which is shown as below:
  92. \arg DBG_SLEEP_HOLD: keep debugger connection during sleep mode
  93. \arg DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode
  94. \arg DBG_STANDBY_HOLD: keep debugger connection during standby mode
  95. \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
  96. \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
  97. \arg DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted
  98. \arg DBG_TIMER1_HOLD: TIMER1 counter kept when core is halted
  99. \arg DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted
  100. \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
  101. \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
  102. \arg DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted
  103. \arg DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted
  104. \arg DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted
  105. \arg DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted
  106. \arg DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted
  107. \arg DBG_I2C2_HOLD: hold I2C2 SMBUS when core is halted
  108. \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
  109. \param[out] none
  110. \retval none
  111. */
  112. void dbg_periph_disable(dbg_periph_enum dbg_periph)
  113. {
  114. DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
  115. }